1. Field of the Invention
The invention generally relates to a p-type field effect transistor and a method of forming the transistor using a double buried oxide silicon-on-insulator wafer that allows for a thick growth of strained silicon germanium in the source/drain regions to create longitudinal stress on the channel region.
2. Description of the Related Art
U.S. Pat. No. 6,621,131 to Murthy (hereinafter “Murthy”) discloses embodiments that were satisfactory for the purposes for which they were intended. The disclosure of Murthy, in its entirety, is hereby expressly incorporated by reference into the present invention for purposes including, but not limited to, indicating the background of the present invention and illustrating the state of the art. It has been shown that the strain in the silicon channel can affect the mobility of complimentary metal oxide semiconductor (CMOS) transistor carriers significantly. Compressive longitudinal stress along the channel is known to help the PFET (P-type field effect transistor) drive current while it degrades the NFET (N-type field effect transistor) performance. There have been many proposals to improve both NFET and PFET device performance using tensile and compressive longitudinal stresses, respectively, which include modulating middle of line (MOL) nitride liner and spacer intrinsic stresses and STI (shallow trench isolation) material changes individually for the two MOSFETs (metal oxide semiconductor field effect transistors) using masks. The stress state in the channel that can be imposed by any of these approaches is typically a few hundred MPa.
Another approach is to use silicon germanium based strained silicon substrates, where silicon germanium is used as part of the whole substrate. When silicon (Si) is grown epitaxially on the “relaxed” silicon germanium layer, a tensile strain results in the Si and thereby improves electron mobility. However, this technique requires silicon germanium to be relaxed, which demands a very thick silicon germanium layer (i.e., 0.5-1 micron) in bulk systems. In bulk systems silicon germanium relaxes through the formation of a dense network of misfit dislocations. These dislocations are known to cause a major yield issue. Hole mobility is even more difficult to enhance in this approach since we need a very large germanium percentage in the relaxed silicon germanium film which causes an even bigger yield and dislocation problem. In silicon germanium-on-insulator (SGOI) systems the germanium is grown on a silicon-on-insulator (SOI) wafer and is then thermally mixed with the silicon to give a “relaxed” silicon germanium on a buried oxide (BOX) substrate. On this silicon germanium on insulator, Si is epitaxially grown to get a tensile film. Unfortunately, in the SGOI system, as the silicon germanium relaxes, dislocations (and in addition, stacking faults) form with concomitant yield degradation. Further, the cost of the process is also prohibitive. Some techniques such as graded germanium concentration and chemical mechanical polishing (CMP) are used to improve the quality of the films, but in general, this process is plagued by a high density of defects and prohibitive costs.
USPTO Backgrounds
USPTO Backgrounds