(a) Field of the Invention:
The present invention relates to a semiconductor device having an interconnection of a laminate structure and a method for manufacturing the same and, more particularly, to a new laminate structure of an interconnection pattern in a semiconductor device.
(b) Description of the Related Art:
Some semiconductor devices have an interconnection pattern composed of a laminate structure including a main conductor of copper (Cu).
FIGS. 1A-1C shows cross-sectional views of a first conventional interconnection pattern in a semiconductor device in consecutive steps for fabrication thereof described in Publication No. JP-A-88-156341. First, a 50 nanometer (nm)-thick first titanium (Ti) film for making ohmic contacts with diffused regions of a semiconductor substrate 101, an 100 nm-thick first titanium nitride (TIN) film constituting a barrier layer against diffusion of Cu atoms, a 700 nm-thick Cu film constituting a main conducting layer and a 200 nm-thick second TiN Film constituting a barrier layer against the Cu diffusion arc consecutively formed on a silicon dioxide (SiO.sub.2) film 104 overlying a silicon (Si) substrate 101. Next, the second TiN film iS etched to form a film pattern 107b by a known technology. Then, the Cu film is etched to form a Cu pattern 109b by an ion-milling technology using the second TiN pattern 107b as a mask. The first TiN film and the first Ti film, both underlying the Cu pattern 109b, are etched to form TiN and Ti patterns 107a and 106 by a reactive ion etching (RIE) technology using a mixed gas composed of sulfur hexafluoride (SF.sub.6) and oxygen (O.sub.2) gases in a flow rate of 10:1. Thus the structure shown in FIG. 1A is obtained.
FIG. 1B shows the interconnection structure in a subsequent step after forming a 300 nm-thick TiN film 107c using a bias-sputtering technology on a top surface of the interconnection pattern, on sidewalls of the interconnection pattern and on a surface of the SiO.sub.2 film 104. FIG. 1C illustrates the interconnection pattern in a step following an anisotropic RIE which has etched off the TiN film 107c located both on the SiO.sub.2 104 and on the top surface of the interconnection pattern to leave TiN film 107c only on the sidewalls of the interconnection pattern. As a result, a structure is obtained wherein substantially all surfaces of the interconnection pattern are coated and protected with the TiN films 107b and 107c, which guarantees a low resistivity and a long-term reliability of the interconnection. Alternatively, W, Mo, Ta, Cr films etc. may be used as a barrier metal against Cu diffusion instead of the TiN film as described above.
FIG. 2A and 2B are cross-sectional views of a second conventional interconnection pattern in consecutive steps for fabrication, which is disclosed in Publication No. JP-B-74-3237. As shown in FIG. 2A, a SiO.sub.2 film is formed on a Si substrate 101 and patterned to form a film pattern 104 having a contact-hole 105a (a via-hole for a first-level interconnection, which will be referred to as a "via-hole" hereinafter) using a known technology. Subsequently, a TiN film 107a is formed on a surface of the SiO.sub.2 film 104 and inside the via-hole 105a using a reactive sputtering technology, which is further followed by a step for consecutively forming a thin Ti film 108a and a gold (Au) film 109c constituting a main conductive layer as shown in FIG. 2B. The second Ti film 108a is provided to increase an adhesion force between the Au film 109c constituting a main conductive layer and the TiN film 107a constituting a barrier layer against Au diffusion.
FIGS. 3A-3C are cross-sectional views of a third conventional interconnection pattern in consecutive steps for fabrication, which is reported by K. Ohno et al. in the Extended Abstracts of 183rd Electrochemical Society Meeting, Vol. 93-1, P. 468 (May of 1993). First, an about 500 nm-thick SiO.sub.2 film 104 is formed on a Si substrate 101. A 30 nm-thick first Ti film 106 and an 100 nm-thick first TiN film 107a are tilth consecutively formed by using a sputtering and a reactive sputtering technologies, respectively.
Next, a 30 nm-thick first tungsten (W) film 108c and a 500 nm-thick Cu film 109b are consecutively formed using a sputtering technology. Then, a 30 nm-thick second W film 108d and a 50 nm-thick second TiN film 107b are consecutively formed on the Cu film 109b using sputtering technology, which provides a device structure shown in FIG. 3A.
Among the steps described above, the step for forming the first Ti film 106 is performed for reducing a contact resistance between a diffused region formed in the Si substrate 101 and the first TiN film 107a as well as for increasing an adhesion force between the SiO.sub.2 film 104 and the first TiN film 107a. Here, the first and second TiN films 107a and 107b are provided for avoiding diffusion, oxidation and corrosion of Cu in the Cu film 109b. Those TiN films have also a function for improving durabilities against both electromigration and stressmigration, thereby obtaining a long-term reliability of the interconnection.
On the other hand, the W films 108c and 108d are provided for increasing the adhesion force between the Cu film 109b and the TiN films 107a and 107b. Unless the W films 108c and 108d exist between Cu film 109b and TiN films 107a and 107b, radicals including chlorine (Cl) atoms attack an interface between the Cu film 109b and the TiN films 107a and 107b to induce either side-etching or peeling-off of the TiN films 107a and 107b during the step for patterning the Cu film 109b performed at a high temperature using gases including chlorine atoms.
Subsequently, an about 400-500 nm-thick silicon nitride (Si.sub.3 N.sub.4) film is formed on the TiN film 107b by a plasma-enhanced chemical vapor deposition (PE-CVD) technology. The Si.sub.3 N.sub.4 film is then patterned employing a known photolithographic and dry etching technology to form a Si.sub.3 N.sub.4 mask pattern 110a to be used for etching the metallic films, which provides a device structure shown in FIG. 3B.
Furthermore, an RIE step using gases composed of silicon tetrachloride (SiCl.sub.4), Cl.sub.2, nitrogen (N.sub.2) and ammonia (NH.sub.3) is performed to etch the laminate including the TiN film 107b, the W film 108d, the Cu film 109b, the W film 108c, the TiN film 107a and the Ti film 106 at a substrate temperature of 280.degree. C., thereby obtaining an interconnection pattern as shown in FIG. 3C. During the RIE step, an extremely thin film having a composition approximately equal to the Si.sub.3 N.sub.4 film is deposited on the sidewalls of the interconnection (unshown in the figures) as a by-product, which acts as a sidewall protective film for the Cu pattern 109b.
A fourth conventional interconnection pattern having a protective film for protecting a Cu surface against oxidation and corrosion is reported by J. Cho et al. in 11th Symposium on VLSI Technology, the Digest of Technical Papers, P. 39 (May of 1991). J. Cho illustrates two structures of Cu interconnection encapsulated in a protective film, a non-planar structure and a planar structure. FIGS. 4A-4D show cross-sectional views of an interconnection pattern of the non-planar structure mentioned above in consecutive steps for fabrication thereof while FIGS. 5A-5D similarly show an interconnection pattern of the planar structure as a fifth conventional structure.
A first SiO.sub.2 film 104 and a TiW film 107d are first formed consecutively on a Si substrate 101 as shown in FIG. 4A. Then, a second SiO.sub.2 film is grown on the TiW film 107d at a low temperature, following which the second SiO.sub.2 film is patterned by a known technology to form a SiO.sub.2 mask pattern 110b having a trench 105b for temporarily accepting an interconnection.
Subsequently, a thin W film 108c is selectively grown on the TiW film 107d constituting the bottom surface of the SiO.sub.2 trench 105b by a known technology of a selective W-CVD procedure. Thereafter, a Cu film 109b is selectively formed on the W film 108c by employing a Chemical-Mechanical-Polishing (CMP) of Cu film after non-selective Cu-CVD or a selective Cu-CVD technology, which provides a structure shown in FIG. 4B.
A subsequent etch-back of both the SiO.sub.2 mask pattern 110b and the TiW film 107d by using the Cu film 109b as a mask provides an interconnection of a laminate structure including the TiW film 107d, the W film 108c and the Cu film 109b as shown in FIG. 4C. Subsequently, a W film 111 is formed covering the laminate structure by employing a selective W-CVD technology to protect the Cu film 109b against oxidation and corrosion as shown in FIG. 4D.
On the other hand, the aforementioned method for forming the planar structure shown in FIGS. 5A-5D similarly starts the process steps with formation of a first SiO.sub.2 film 104 on a Si substrate 101. A second SiO.sub.2 film is formed and patterned by employing a known technology to form a SiO.sub.2 mask pattern 110b having a trench 105b for permanently embedding an interconnection. Then, a TiW film 107d is sputter-deposited covering the substantially entire surface to obtain a structure shown in FIG. 5A.
A photoresist film is formed covering the substantially entire surface by spin-coating. The photoresist film and the TiW film are then subjected to an etch-back under a condition that the photoresist film 112 and the TiW film 107d remain only inside the SiO.sub.2 trench 105b as shown in FIG. 5B. Then, the photoresist film 112 is removed and a Si.sub.3 N.sub.4 film is grown on the substantially entire surface, which is then subjected to an anisotropic etch-back under a condition to obtain Si.sub.3 N.sub.4 sidewall spacers 113 remaining only on the inside sidewalls of the SiO.sub.2 trench 105b as shown in FIG. 5C. FIG. 5D shows a final interconnection structure including a W film 108c, a Cu film 109b and a W film 108d formed on the TiW film 107d.
FIGS. 6A-6B are cross-sectional views of a sixth conventional interconnection structure in consecutive steps for fabrication thereof in which a niobium nitride (NbN) protective film is formed in a self-aligning manner for protecting the surface of a Cu interconnection. The structure is reported by H. Itoh et al. at 39th Spring Meeting of the Japan Society of Applied Physics and Related Societies, Vol. 2, P. 707, Presentation No. 30p-ZH-8 (1992).
The steps start with forming a SiO.sub.2 film 104 on a Si substrate 101 followed by formation of a Nb film 114a and a Cu film 109b using a sputter-deposition and a patterning technologies as shown in FIG. 6A. Next, a heat treatment is performed at about 750.degree. C. for half an hour in N.sub.2 ambient to diffuse Nb atoms through Cu film 109b to a surface of the Cu film 109b and to form a NbN protective film 114b as shown in FIG. 6A. Nb atoms remain in the Cu film 109b to an extent of about 3 atomic (at) % after the heat treatment. However, the resistivity of the Cu Film 109b stays low, for instance, at 1.89 .mu..OMEGA.-cm. X-ray diffraction (XRD) analysis verifies that a crystallinity of the Cu film thus formed on the Nb film 114a shows a strong orientation tendency toward an (111) direction, which means a superior durability of thus formed interconnection pattern against both of electro- and stress-migrations.
The five species of conventional technologies mentioned above exhibit relatively good performances except for defects to be detailed later.
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