1. Field of the Invention
The present invention relates to semiconductor devices having double pad structure, a method of manufacturing the same, and a semiconductor package formed thereby, and more particularly, to semiconductor devices having double pad structure for providing sufficient pad size required for a bonding process with outside circuits even with the decreased size of the semiconductor chips, a method of manufacturing the same, and a semiconductor package formed thereby.
2. Description of the Related Art
Semiconductor device fabrication processing involves various processes for a semiconductor wafer such as deposition, oxidation, photo-etch, etc., which are repeatedly carried out so that a pre-designed specific pattern is formed on the semiconductor wafer. Finally, by forming specific metallic conductive lines on the uppermost layer on the semiconductor wafer, covering the surface of the semiconductor wafer with a passivation layer in order to prevent the insulation with the outside, and the contamination from the outside, opening a pad layer thereon for the electrical communication contact, and dicing along the scribe line on the semiconductor wafer, each of the semiconductor chips is fabricated.
Referring to FIGS. 1 and 2, a conventional semiconductor chip fabrication process is illustrated in detail.
FIG. 1 is a top view showing a single chip fabricated by the conventional method, the semiconductor chip 10, which is cut out of the semiconductor wafer, is composed of a cell portion 16 on its center with a pre-set circuit pattern thereon and a peri-portion 14 on its peripheral area with a pad 12 for the electrical contact with outside circuits, and specific control elements. The pad 12 on the peri-portion 14, as shown in FIG. 1, can be of several types including a quad type with the pads formed along the four sides of the semiconductor chip 10, or a dual type with pads formed on any two sides thereof, etc.
FIG. 2 is a cross-sectional view showing the region taken along the line II--II of FIG. 1. The description of the semiconductor device fabrication process including the formation of the pad is made with reference to FIG. 2. A specific intermediate insulating layer 20 is formed on a semiconductor substrate (not shown), and an uppermost metallic conductive layer 17 is formed on the intermediate insulating layer 20 for the circuit pattern by means of a typical deposition, and photo-etch process, etc. within the cell-portion 16. Typically, a pad layer 18 is formed on the peri-portion 14 simultaneously with the formation of the metallic conductive layer 17 using the same material as the metallic conductive layer 17, e.g., aluminum.
Then, a passivation layer 22 is formed over the semiconductor substrate with the metallic conductive layer 17 and the pad layer 18. That is, by forming the passivation layer, e.g., an insulating oxide layer, by carrying out photo-etch process so as to expose the pad layer 18, and carrying out dicing, a single semiconductor chip 10 is formed.
Then, a package process is carried out so as to bond the semiconductor chip 10 with a printed circuit substrate having outside circuits thereon. The package process may be one of several types, e.g., a wire-bonding process of connecting the lead of a lead frame with the exposed pad on the semiconductor chip using wire, or a ball-bonding process of forming a ball on the pad of the semiconductor chip, and bonding with the printed circuit substrate.
However, the above wire-bonding or the ball-bonding process for the electrical contact with the outside circuits requires a pad having a certain minimum size, irrespective of the recent trend of the highly-integrated semiconductor devices. The number of the pads formed on a single chip and the number of the semiconductor chips formed from a single semiconductor wafer are increasing with the high-integration and the sophistication of the semiconductor devices, while the size of a single semiconductor chip is decreasing. In other words, the size of the pad should be made over a certain threshold even with the decrease of the single chip size, and the increase in the number of pads. As a result, a new pad structure is required in order to overcome the above problems.
Further, as shown in FIG. 2, the covering of the passivation layer 22 for opening the pad layer 18 in the conventional pad formation process includes a dry-etch process, but the surface of the pad layer 18 can be damaged by the plasma during the dry-etch process. Contamination can also occur. Either result in the malfunctioning in the subsequent bonding process.
USPTO Backgrounds
USPTO Backgrounds