Embodiments relate to a semiconductor device and a method for forming the same, and more particularly to a reservoir capacitor.
A semiconductor device includes a plurality of circuits. Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) includes a cell region in which a circuit for storing data is formed, a core region for accessing the data stored in the cell region, and a peripheral region in which a circuit configured to drive the semiconductor memory device as well as to carry out data input/output (I/O).
The cell region includes a plurality of memory cells, each of which includes a cell transistor and a cell capacitor, and the memory cells are arranged in row and column directions and in an array shape. A group of memory cells arranged in an array shape is referred to as a unit cell array. In order to access a specific memory cell of a unit cell array, a row and a column are designated separately from each other, and a circuit for designating the row and the column is formed in a core region located adjacent to the cell region.
The core region includes a sub-word line driver, a sense-amplifier, and the like. In this case, the sub-word line driver is configured to select a sub-word line coupled to the specific memory cells of the unit cell array. Since electric charges stored in a cell capacitor of a memory cell are small, it is difficult for the sense-amplifier to quickly convert the electric charges into a digital signal and output the digital signal to an external part, such that the small amount of electric charges can be amplified.
The DRAM is implemented as a bank structure that includes a plurality of unit cell arrays and a plurality of core regions. For example, a 512-Mbit DDR2 device includes four banks. In more detail, a peripheral region including a power circuit, a free decoder, an input buffer, an output buffer, etc. is located between a plurality of banks. Meanwhile, a reservoir capacitor is located in the vicinity of the power circuit so as to prevent the occurrence of noise caused by power-potential switching.
In the case of forming a transistor of the cell region, reservoir capacitors are simultaneously formed in the peripheral region in such a manner that the reservoir capacitors can be formed in many more regions of the semiconductor device. In general, the reservoir capacitor may include a MOS-type capacitor which is formed including a gate and a source/drain.
However, with the increasing integration degree of semiconductor devices, many more circuits must be formed in a limited-sized chip region. As a result, the semiconductor device is gradually reduced in size in proportion to the increasing integration degree of the semiconductor device. Specifically, as a design rule is gradually reduced in a memory device such as DRAM, a unit cell size of a semiconductor device is gradually reduced. Likewise, as a design rule is gradually reduced in the peripheral region, semiconductor device elements provided in the peripheral region is gradually reduced in size. Therefore, a reservoir capacitor formed in the vicinity of the power circuit is gradually reduced in size, as well.
Specifically, since a typical reservoir capacitor is configured to form an array by interconnecting two units, and a large-sized region is required to form the reservoir capacitor, there may be a structural limitation in noise reduction and chip integration.
USPTO Backgrounds
USPTO Backgrounds