1. Field of the Invention
The present invention relates generally to a Silicon On Insulator (SOI) pass-gate disturb solution, and more particularly pertains to an SOI pass-gate disturb solution for an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) wherein a resistor is connected between the gate and the body if the MOSFET to eliminate the disturb condition.
2. Description of Prior Art
N-type MOSFETs are used as pass-gates in Complementary Metal Oxide Semiconductor (CMOS) circuits for improved density and performance. In the SOI, the body or the substrate of the FET electrically floats. This floating leads to a disturb problem when the source and the drain electrodes are held high for greater than the thermal generation time and the gate is held low, followed by a transition from high to low by the input, which is usually the source. Holes generated in the body prior to the transition are drawn into the source by the low potential during the transition. The bipolar gain, with the source acting as the emitter, the body as the base, and the drain as the collector, results in a current pulse at the output of the pass-gate, which is usually the drain, given by the NPN beta times the body discharge current formula (Cgate.times.Vdd/Tfall). This current pulse can cause the circuit, which is to be isolated by the pass-gate, to falsely make a transition to the low state.
The current approach to solving this problem is to either increase the noise tolerance of the circuit being isolated by the pass-gate, and/or to add processing steps to reduce the NPN parasitic bipolar gain.
Increasing the immunity of the isolated circuit, called the latch, to this current pulse compromises performance as more current is now required from the pass-gate to complete a desired transition to the low state. Reduction of the NPN gain requires introduction of additional processing steps which involve compromises in leakage and manufacturing heat cycles.
USPTO Backgrounds
USPTO Backgrounds