The present invention relates generally to integrated circuits, and more specifically to a method and system including a reduced number of row command generators for accessing rows in a plurality of respective memory banks within a memory device.
Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (xe2x80x9cROMsxe2x80x9d) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (xe2x80x9cSRAMxe2x80x9d). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium(copyright) and Pentium II(copyright) microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a lower clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a substantially lower frequency. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (xe2x80x9cDRAMsxe2x80x9d). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (xe2x80x9cSDRAMsxe2x80x9d) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a computer architecture known as a synchronous link architecture. In the synchronous link architecture, the system memory may be coupled to the processor either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, synchronous link memory devices receive command packets that include both control and address information. The synchronous link memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus.
An example of a computer system 10 using the synchronous link architecture is shown in FIG. 1. The computer system 10 includes a processor 12 having a processor bus 14 coupled through a memory controller 18 and system memory bus 23 to three packetized or synchronous link dynamic random access memory (xe2x80x9cSLDRAMxe2x80x9d) devices 16a-c. The computer system 10 also includes one or more input devices 20, such as a keypad or a mouse, coupled to the processor 12 through a bus bridge 22 and an expansion bus 24, such as an industry standard architecture (xe2x80x9cISAxe2x80x9d) bus or a peripheral component interconnect (xe2x80x9cPCIxe2x80x9d) bus. The input devices 20 allow an operator or an electronic device to input data to the computer system 10. One or more output devices 30 are coupled to the processor 12 to display or otherwise output data generated by the processor 12. The output devices 30 are coupled to the processor 12 through the expansion bus 24, bus bridge 22 and processor bus 14. Examples of output devices 24 include printers and a video display units. One or more data storage devices 38 are coupled to the processor 12 through the processor bus 14, bus bridge 22, and expansion bus 24 to store data in or retrieve data from storage media (not shown). Examples of storage devices 38 and storage media include fixed disk drives floppy disk drives, tape cassettes and compact-disk read-only memory drives.
In operation, the processor 12 sends a data transfer command via the processor bus 14 to the memory controller 18, which, in turn, communicates with the memory devices 16a-c via the system memory bus 23 by sending the memory devices 16a-c command packets that contain both control and address information. Data are coupled between the memory controller 18 and the memory devices 16a-c through a data bus portion of the system memory bus 23. During a read operation, data are transferred from the SLDRAMs 16a-c over the memory bus 23 to the memory controller 18 which, in turn, transfers the data over the processor 14 to the processor 12. The processor 12 transfers write data over the processor bus 14 to the memory controller 18 which, in turn, transfers the write data over the system memory bus 23 to the SLDRAMs 16a-c. Although all the memory devices 16a-c are coupled to the same conductors of the system memory bus 23, only one memory device 16a-c at a time reads or writes data, thus avoiding bus contention on the memory bus 23. Bus contention is avoided by each of the memory devices 16a-c on the system memory 22 having a unique identifier, and the command packet contains an identifying code that selects only one of these components.
The computer system 10 also includes a number of other components and signal lines that have been omitted from FIG. 1 in the interests of brevity. For example, as explained below, the memory devices 16a-c also receive a master clock signal to provide internal timing signals, a data clock signal clocking data into and out of the memory device 16, and a FLAG signal signifying the start of a command packet.
A typical command packet CA less than 0:39 greater than  for an SLDRAM is shown in FIG. 2 and is formed by 4 packet words CA less than 0:9 greater than , each of which contains 10 bits of data. As will be explained in more detail below, each packet word CA less than 0:9 greater than  is applied on a command address bus CA including 10 lines CA0-CA9. In FIG. 2, the four packet words CA less than 0:9 greater than  comprising a command packet CA less than 0:39 greater than  are designated PW1-PW4. The first packet word PW1 contains 7 bits of data identifying the packetized DRAM 16a-c that is the intended recipient of the command packet. As explained below, each of the packetized DRAMs is provided with a unique ID code that is compared to the 7 ID bits in the first packet word PW1. Thus, although all of the packetized DRAMs 16a-c will receive the command packet, only the packetized DRAM 16a-c having an ID code that matches the 7 ID bits of the first packet word PW1 will respond to the command packet.
The remaining 3 bits of the first packet word PW1 as well as 3 bits of the second packet word PW2 comprise a 6 bit command. Typical commands are read and write in a variety of modes, such as accesses to pages or banks of memory cells. The remaining 7 bits of the second packet word PW2 and portions of the third and fourth packet words PW3 and PW4 comprise a 20 bit address specifying a bank, row and column address for a memory transfer or the start of a multiple bit memory transfer. In one embodiment, the 20-bit address is divided into 3 bits of bank address, 10 bits of row address, and 7 bits of column address. Although the command packet shown in FIG. 2 is composed of 4 packet words PW1-PW4 each containing up to 10 bits, it will be understood that a command packet may contain a lesser or greater number of packet words, and each packet word may contain a lesser or greater number of bits.
The memory device 16a is shown in block diagram form in FIG. 3. Each of the memory devices 16a-c includes a clock generator circuit 40 that receives a command clock signal CCLK and generates a large number of other clock and timing signals to control the timing of various operations in the memory device 16a. The memory device 16a also includes a command buffer 46 and an address capture circuit 48 which receive an internal clock signal ICLK, a command packet CA less than 0:9 greater than  on a 10 bit command-address bus CA, and a terminal 52 receiving a FLAG signal. A memory controller (not shown) or other device normally transmits the command packet CA less than 0:9 greater than  to the memory device 16a in synchronism with the command clock signal CCLK. As explained above, the command packet, which generally includes four 10-bit packet words PW1-PW4, contains control and address information for each memory transfer. The FLAG signal identifies the start of a command packet, and also signals the start of an initialization sequence. The command buffer 46 receives the command packet from the conmmand-address bus CA, and compares at least a portion of the command packet to identifying data from an ID register 56 to determine if the command packet is directed to the memory device 16a or some other memory device 16b, c. If the command buffer 46 determines that the command is directed to the memory device 16a, it then provides the command to a command decoder and sequencer 60. The command decoder and sequencer 60 generates a large number of internal control signals to control the operation of the memory device 16a during a memory transfer.
The address capture circuit 48 also receives the command packet from the command-address bus CA and outputs a 20-bit address corresponding to the address information in the command packet. The address is provided to an address sequencer 64, which generates a corresponding 3-bit bank address on bus 66, a 10-bit row address on bus 68, and a 7-bit column address on bus 70. The row and column addresses are processed by row and column address paths, as will be described in more detail below.
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The SLDRAM 16a shown in FIG. 3 largely avoids this problem by using a plurality of memory banks 80, in this case eight memory banks 80a-h. After a read from one bank 80a, the bank 80a can be precharged while the remaining banks 80b-h are being accessed. Each of the memory banks 80a-h receives a row address from a respective row latch/decoder/driver 82a-h. All of the row latch/decoder/drivers 82a-h receive the same row address from a predecoder 84 which, in turn, receives a row address from either a row address register 86 or a refresh counter 88 as determined by a multiplexer 90. However, only one of the row latch/decoder/drivers 82a-h is active at any one time as determined by bank control logic 94 as a function of a bank address from a bank address register 96.
The column address on bus 70 is applied to a column latch/decoder 100, which supplies I/O gating signals to an I/O gating circuit 102. The I/O gating circuit 102 interfaces with columns of the memory banks 80a-h through sense amplifiers 104. Data is coupled to or from the memory banks 80a-h through the sense amps 104 and I/O gating circuit 102 to a data path subsystem 108 which includes a read data path 110 and a write data path 112. The read data path 110 includes a read latch 120 that stores data from the I/O gating circuit 102.
In the memory device 16a shown in FIG. 3, 64 bits of data are stored in the read latch 120. The read latch then provides four 16-bit data words to an output multiplexer 122 that sequentially supplies each of the 16-bit data words to a read FIFO buffer 124. Successive 16-bit data words are clocked into the read FIFO buffer 124 by a clock signal RCLK generated from the internal clock signal ICLK. The 16-bit data words are then clocked out of the read FIFO buffer 124 by a clock signal obtained by coupling the RCLK signal through a programmable delay circuit 126. The programmable delay circuit 126 is programmed during initialization of the memory device 16a so that the data from the memory device is received by a memory controller, processor, or other device (not shown in FIG. 3) at the proper time. The FIFO buffer 124 sequentially applies the 16-bit data words to a driver circuit 128 which, in turn, applies the 16-bit data words to a data bus DQ forming part of the processor bus 14 (see FIG. 1). The driver circuit 128 also applies one of two data clock signals DCLK0 and DCLK1 to respective data clock lines 132 and 133. The data clocks DCLK0 and DCLK1 enable a device, such as the processor 12, reading the data on the data bus DQ to be synchronized with the data. Particular bits in the command portion of the command packet CA0-CA9 determine which of the two data clocks DCLK0 and DCLK1 is applied by the driver circuit 128. It should be noted that the data clocks DCLK0 and DCLK1 are differential clock signals, each including true and complementary signals, but for ease of explanation, only one signal for each clock is illustrated and described.
The write data path 112 includes a receiver buffer 140 coupled to the data bus 130. The receiver buffer 140 sequentially applies 16-bit data words from the data bus DQ to four input registers 142, each of which is selectively enabled by a signal from a clock generator circuit 144. The clock generator circuit 144 generates these enable signals responsive to the selected one of the data clock signals DCLK0 and DCLK1. The memory controller or processor determines which data clock DCLK0 or DCLK1 will be utilized during a write operation using the command portion of a command packet applied to the memory device 16a. As with the command clock signal CCLK and command packet, the memory controller or other device (not shown) normally transmits the data to the memory device 16a in synchronism with the selected one of the data clock signals DCLK0 and DCLK1. The clock generator 144 is programmed during initialization to adjust the timing of the clock signal applied to the input registers 142 relative to the selected one of the data clock signals DCLK0 and DCLK1 so that the input registers 142 can capture the write data at the proper times. In response to the selected data clock DCLK0 or DCLK1, the input registers 142 sequentially store four 16-bit data words and combine them into one 64-bit data word applied to a write FIFO buffer 148. The write FIFO buffer 148 is clocked by a signal from the clock generator 144 and an internal write clock WCLK to sequentially apply 64-bit write data to a write latch and driver 150. The write latch and driver 150 applies the 64-bit write data to one of the memory banks 80a-h through the I/O gating circuit 102 and the sense amplifiers 104.
As is well-known in the art, reading from a conventional memory bank in a DRAM requires that a selected row of memory cells corresponding to a row address first be activated. In activating a row, a pair of complementary digit lines for each column in the array are equilibrated. A word line coupled to each memory cell in the selected row is then activated, coupling each of the memory cells to a digit line for a respective column. A respective sense amplifier coupled to the complementary digit lines for each column is then able to sense, store, and collectively output the data stored in the selected row. These operations are performed responsive to internally generated xe2x80x9crow commandsxe2x80x9d, i.e., commands that activate an addressed row, then activate the sense amplifiers, and thereafter make the data stored in the row available for reading. Data provided by each of the sense amplifiers are then selected by a respective column address for coupling to an external data terminal through a data path. These operations are performed responsive to internally generated xe2x80x9ccolumn commandsxe2x80x9d, i.e., commands that select and output data from a column. For example, in a synchronous DRAM, a row command may be received along with a row address and a row address strobe signal to activate or xe2x80x9copenxe2x80x9d the addressed row. A column command may then be received along with a column address and a column address strobe signal. For example, a page read command may cause data to be read from a sequence of columns of the open row starting at the column designated by the column address. Another row command may then be received, such as a command to deactivate or xe2x80x9cclosexe2x80x9d the open row of memory cells.
In the packetized memory device 16a of FIG. 3, each of the memory banks 80a-h receives row control signals from the corresponding row latch/decoder/driver 82a-h to access a row of memory cells in that particular bank. Each of the row latch/decoder/driver circuits 82a-h typically includes a row address decoder that decodes the received row address and a driver or row command generator that generates row control signals to access a row corresponding to the decoded row address. More specifically, the row command generator typically generates a {overscore (FIREROW)} signal for opening the row corresponding to the decoded row address and an {overscore (NSENSE)} signal for activating the sense amplifiers coupled to the digit lines of the corresponding memory bank. A PSENSE signal may also be generated by the row generator and applied to activate PMOS transistors in the sense amplifier, as understood by one skilled in the art. In the following description, however, only the {overscore (NSENSE)} signal will be described as activating the sense amplifier. As understood by one skilled in the art, the row command generator must activate the {overscore (FIREROW)} and {overscore (NSENSE)} signals at the proper times in order to open a row and accurately sense the data stored in the opened row. For example, in accessing a row the {overscore (FIREROW)} signal is coupled to the word line corresponding to the selected row, coupling each of the memory cells in the selected row to the corresponding digit line as previously described. The row command generator thereafter activates the {overscore (NSENSE)} signal, enabling the sense amplifiers to sense and store the data in the opened row of memory cells. The {overscore (NSENSE)} signal should not be activated until each memory cell has been accessed, which includes being coupled to the corresponding digit line and transferring charge between the memory cell and the digit line. If the {overscore (NSENSE)} signal is activated before each memory cell has been accessed, it is possible for the activated sense amplifiers to sense the wrong data, as will be understood by one skilled in the art. Similarly, when closing a row, the row command generator must deactivate the {overscore (FIREROW)} signal and then deactivate the {overscore (NSENSE)} signal a predetermined time later. Once again, the {overscore (FIREROW)} signal must be deactivated sufficiently before the {overscore (NSENSE)} signal is deactivated to ensure each of the memory cells is decoupled from the corresponding digit line before the sense amplifiers are deactivated, as will be understood by one skilled in the art.
The required timing of the {overscore (FIREROW)} and {overscore (NSENSE)} signals generated by each row command generator depends in part on the physical characteristics of word lines in the memory banks. For example, the resistance and capacitance of a word line affects the opening and closing of rows due to the resulting delay between activating or deactivating the word line in response to the {overscore (FIREROW)} signal, and driving the voltage on the word line to a level sufficient to couple/decouple each memory cell to/from the corresponding digit line. Thus, in order to activate and deactivate the {overscore (FIREROW)} and {overscore (NSENSE)} signals at the proper times, each of the row command generators must include circuitry that emulates the timing of an actual word line. In other words, each row command generator must include a timing circuit that activates the {overscore (NSENSE)} signal a predetermined time after the {overscore (FIREROW)} signal, and deactivates the {overscore (NSENSE)} signal a predetermined time after deactivating the {overscore (FIREROW)} signal. Such timing circuits typically occupy a relatively large area on the substrate in which the memory device is formed due to the components required to accurately emulate the timing of the actual word lines and generate the {overscore (FIREROW)} and {overscore (NSENSE)} signals at the proper times. More specifically, each timing circuit typically includes a xe2x80x9cdummyxe2x80x9d word line or xe2x80x9cmini arrayxe2x80x9d component which is a word line formed crossing the same number of digit lines as an actual word line, thus occupying a relatively large area on the substrate, as understood by one skilled in the art. As the number of memory banks in a memory device increases, the area occupied by the corresponding row command generators may occupy an unacceptably large portion of the substrate in which the memory device is formed.
In memory devices including a plurality of memory banks, such as packetized memory devices like SLDRAMs, there is a need to reduce the area occupied by the row command generators utilized to access rows of memory cells in the respective banks. Although the above discussion is directed towards packetized memory devices such as SLDRAMs, the concepts apply to other types of integrated circuits as well, including other types of memory devices having multiple memory banks.
A row command unit is contained in an integrated circuit including a plurality of memory banks. The row command unit includes a plurality of row control latches, each row control latch having an output coupled to a respective memory bank, and having an enable terminal and a control terminal. Each row control latch latches a signal applied on the control terminal when an active enable signal is applied on the enable terminal. A delay circuit has an output terminal coupled to the control terminals of the row control latches. The delay circuit also has an input terminal and generates a row control signal on its output responsive to an activation signal applied on its input. A bank control circuit is coupled to the input terminal of the delay circuit and has input terminals adapted to receive respective bank address and bank control signals. The bank control circuit also has a plurality of output terminals, each output terminal being coupled to a respective enable terminal of one of the row control latches. The bank control circuit applies an active enable signal to one of the row control latches and applies an active activation signal to the delay circuit responsive to the bank control and bank address signals.
According to a second aspect of the present invention, the row command unit is contained in a packetized memory device including a plurality of memory banks coupled to respective row control latches, and having a minimum bank-to-bank access time t1 between which successive banks may be accessed. Each of the row-timing circuits includes an open-row and close-row timing circuit, each having a delay-reset time of t2. The number of row-timing circuits contained in the packetized memory device corresponds to t2/t1 rounded up to the nearest integer. One skilled in the art will appreciate that although the row command unit is described as being contained in a packetized memory device, the row command unit may be contained in any type of integrated circuit having a plurality of memory banks, including other types of memory devices, such as conventional asynchronous DRAMs.
USPTO Backgrounds
USPTO Backgrounds