The present invention relates to a semiconductor device and a method of manufacture thereof, and, more particularly, the invention relates to a semiconductor device and a manufacturing method which is designed to improve the yield of the semiconductor devices by improving the testing thereof.
Currently, typical semiconductor devices are manufactured using the following steps:
Integrated circuit forming step for forming a number of integrated circuits on a wafer;
Probe test step for implementing a probe test (test on conductivity) on the large number of integrated circuits formed on the wafer;
Dicing step for dicing the wafer into a plurality of chips (cutting individual integrated circuits) after the probe test step;
Packaging step for packaging per chip as a semiconductor device; and
Burn-in test step for implementing a burn-in test (thermal load test) on the semiconductor devices.
Among the above-mentioned steps, the probe test step is a step for testing the conductivity of electrical signals by bringing probes into contact with electrode pads while the plane of a probe unit on which the probes are provided faces the surface of the wafer to be tested. For the probes, tungsten wires whose tip diameter is several xcexcm, or metallic projections created by means of etching or the like in a polyimide membrane, are used. Each probe normally presses against an electrode pad of the integrated circuits with a load of 1 through 20 gf.
A group of probes provided on a disk-like multi-layered wiring glass epoxy substrate is referred to as a probe card, and a probe card using the metallic projections created by means of etching or the like in a polyimide membrane is called a membrane probe card.
The following are typical examples of known technology related to a membrane probe card:
Nippon Avionics Co., Ltd. (Packard Hughes) Catalog:
According to this known technology (hereinafter referred to as the first known technology), the periphery of the membrane is fixed by a stiffener, a pressure plate is disposed and fixed on the back of part of the membrane where a group of probes (contacts) are created and a spring for applying a suitable load to the wafer is disposed at the center of the upper face of the pressure plate. One center pivot is provided at the center of the pressure plate between the spring and the pressure plate.
Hoya Probe Technology Membrane Probe Card Catalog:
According to this known technology (hereinafter referred to as the second prior art technology), an elastomer is interposed between the membrane and the pressure plate to absorb a dispersion of the height of the probes (bump) more or less.
It is also described in this publication, similarly to the first known technology, that the pressure plate and the membrane are supported by one pivot at the center of the pressure plate so that the pressure plate turns, following the plane to be tested, by pivoting on the center pivot at the moment when the probes come into contact with the wafer even when the pressure plate is not parallel to the plane to be tested.
However, the above-mentioned manufacturing methods have had the following problems from the aspects of reliability and productivity.
[Probe Inspection Step]
The number of integrated circuits which can be tested in batch on one wafer has been limited to one to four so far and so the pressing actions have to be repeated many times in order to test all integrated circuits on the wafer in the above-mentioned first and second technologies. The reason why the number of integrated circuits tested in batch has been limited will be described below.
The electrode pads to be probed are made of a thin Al film 0.8 to 1 xcexcm thick deposited on Si, and a natural oxide film that is an insulator is formed on the surface thereof as it is left in air. It is essential to control the pressure load (or degree of push) in bringing the individual probe into contact with the electrode pad within an adequate value in order to cause the probes to properly contact all pads in an area to be probed. The adequate value of the pressure load is determined here on the basis of that pressure which causes a probe having a largest load to penetrate through the Al film and reach the Si substrate under the Al film without harming it within the pressure plane, i.e., within the area of the pressure plate, and on the basis of that pressure which causes a probe having the least load to reach the Al film by breaking through the natural oxide film and determine the conductivity. These values of load are influenced by the shape (curvature) of the tip of the probe, the hardness of the Al film and the like.
Primary factors in the dispersion of the pressure load (hereinafter referred to as dispersion) and dispersion absorbing mechanisms of the known technologies will be explained with reference to FIG. 1 and Table 1.
FIG. 1 is a section view of a pressing mechanism and a wafer showing a structural concept of a known typical membrane probe card and the primary factors which contribute to the dispersion of the load, which is problematic when the pressing area is expanded.
A group of probes 1 are formed in the membrane 2, such as a polyimide membrane, in which a single or a plurality of layers of wires are provided and the membrane 2 is bonded to one pressure plate 4 via an elastomer 3. Normally, one pivot member 5 is in point contact with the pressure plate 4 at the center of the upper part of the plate and is connected to a fixed member 7 via a spring 6. The peripheral portion of the membrane 2 is connected electrically and mechanically to a multi-layered wiring glass epoxy substrate. The fixed member 7 is connected mechanically to the substrate.
The primary factors for the dispersion are: 1) an individual difference in the height of the probes, 2) a relative gradient of the pressure plane (the plane where the probes are formed and the surface of wafer), 3) an irregularity (warp) in the wafer (or of the probe forming plane), and 4) a pressure (positioning) error in the height direction. These factors will be explained below in this order.
1) Individual Difference in the Height of the Probes:
The difference in height of each probe caused by error in manufacturing the membrane probe is normally from several to ten-odd xcexcm.
2) Relative Gradient of the Pressure Plane:
The relative gradient between the pressure plane and the plane to be tested (the surface of wafer) is typically caused by an inclination of the probe card when it is set in the unit, a warping of the glass epoxy substrate itself, an inclination of a wafer chucking plane and the like.
3) Irregularity (Warp) of the Wafer (or of the Probe Forming Plane):
An out-of-plane deformation of the wafer is caused when stress is released in slicing the wafer from a Si ingot or by stress in forming the integrated circuits on the wafer. The allowance thereof is several hundreds xcexcm in case of a wafer 6 inches in diameter produced in a mass-production process. The allowance is greater for a wafer having a larger diameter.
Meanwhile, the irregularity of the probe forming plane is created mainly in the step of pasting the membrane sheet to the pressure plate.
4) Pressure (Positioning) Error in the Height Direction:
The repeatability of movement in the height direction of the wafer chuck for bringing the probes into contact with the electrode pads is normally around xc2x1 several xcexcm.
The probe test is carried out normally while heating the wafer up to 100 to 150xc2x0 C. At this time, the probe card is also affected and is heated up. As a result, a phenomenon may occur in that mainly the glass epoxy substrate warps out-of-plane. This is also a large factor in the dispersion of the pressure.
Meanwhile, the known membrane probe card as described above is provided with dispersion absorbing mechanisms corresponding to those respective factors of dispersion. Table 1 shows the correspondence between each factor and the dispersion absorbing mechanism, i.e., the purpose of each dispersion absorbing mechanism.
The elastomer brings about an effect of regulating a local elastic deformation of large curvature, the pivot produces an effect of a lever and the spring an effect of regulating the height of the whole pressure plate, thereby to absorb the respective factors of dispersion.
It is effective to expand the pressing area of the probe card to increase the number of integrated circuits which can be tested in batch in order to improve the efficiency of the probe test and to improve the productivity of the semiconductor devices.
However, when the pressing area is to be expanded by expanding the size of the pressure plate and the membrane while keeping the known structure, the influence of the primary factors of dispersion 2) and 3) in particular, as seen in Table 1, i.e., the relative gradient of the pressure plane and the irregularity (warp) of the pressuring plane and the plane of the wafer (or the probe forming plane), increases, thus increasing the dispersion of the pressure load. Further, because a required total pressure load increases in proportion to the increase of the testing area, the sliding frictional force of the pivot increases as a result and its ability to follow the relative gradient drops.
Still more, because an excessive load which should be allocated equally to all of the probes is applied transiently and concentratedly to the probe that contacts the wafer earliest, temporally, due to the state of the gradient and the irregularity, the Si substrate of the wafer may be damaged or the longevity (usable number of times for testing) of the probes may drop remarkably due to excessive abrasion.
These phenomena have not only reduced the longevity of the probe card and increased the repair and maintenance costs, but also have damaged the wafer (integrated circuits) which is the object to be probed, thus becoming the largest obstacle to any increase in the number of integrated circuits which can be tested simultaneously in batch. Accordingly, it has been difficult in practice to test a large area simultaneously in batch while keeping the known structure, and it has been impossible to test one large integrated circuit having a size greater than a certain value in one operation.
The burn-in test step also has had a problem in implementing the test of packaged semiconductor devices in that the cost is increased wastefully because chips including an initial failure are also packaged.
Accordingly, it is an object of the present invention to provide semiconductor devices and a method of manufacture thereof, which enhance the reliability and productivity of the integrated circuits by suppressing dispersion of the load within an allowable range even if probes in a larger area are pressed in batch and by implementing a probe test/burn-in test on a large number of integrated circuits or an integrated circuit having a large dimension in one operation.
It is another object of the present invention to provide semiconductor devices and a method of manufacture thereof which enhance the productivity by omitting the burn-in test step without packaging chips which include an initial failure.
The above-mentioned problems may be solved as follows.
(1) A semiconductor device manufacturing method is employed which comprises a integrated circuit forming step for forming a number of integrated circuits on a wafer; a probe test step for implementing a probe test (test on conductivity) on the wafer on which a large number of integrated circuits have been formed; a burn-in test step for implementing a burn-in test (thermal load test) on the wafer on which a large number of integrated circuits have been formed; and a dicing step for dicing the wafer into a plurality of chips after completion of the probe test step and the burn-in test step.
Because this manufacturing method allows the burn-in test to be carried out in the wafer state, the heating furnace may be scaled down and the quantity of heat may be reduced as compared to the known burn-in test in the state of final products in the manufacture of resin encapsulated type semiconductor devices. Thereby, the productivity of the semiconductor devices may be improved.
Further, because this manufacturing method allows chips including an initial failure to be eliminated, it is possible to prevent useless cost by not packaging chips including an initial failure.
(2) In the semiconductor device manufacturing method of paragraph (1), integrated circuit protecting members/external connecting terminals are attached to an integrated circuit forming plane of the wafer after completion of the probe test step and the burn-in test step, and the dicing step is carried out thereafter.
This manufacturing method allows the productivity of semiconductor devices to be improved because the external connection terminals are attached in the wafer state and the semiconductor devices are consummated at the point of time when the dicing step ends.
(3) In a semiconductor device manufacturing method comprising an integrated circuit forming step for forming a number of integrated circuits on a wafer; a probe test step is carried out for implementing a probe test (test on conductivity) on the wafer on which a large number of integrated circuits have been formed; and a burn-in test step is carried out for implementing a burn-in test (thermal load test) on the wafer on which a large number of integrated circuits have been formed; the probe test step/burn-in test step comprising a pressing step for pressing a plurality of probes provided in a membrane to the wafer by using pressure members, and the pressure load is applied to a plurality of locations of a plane of the pressure member on the side opposite the wafer in pressing the plurality of probes.
(4) In the semiconductor device manufacturing method of paragraphs (1) or (2), the probe test step/burn-in test step further comprises a pressing step for pressing a plurality of probes provided in a membrane against the wafer by using pressure members and a pressure load is applied to a plurality of locations of planes of the pressure members on the side opposite from the wafer in pressing the plurality of probes.
These manufacturing methods allow the reliability and productivity of the semiconductor devices to be enhanced because the dispersion of the load in pressing the pressure members against the wafer may be controlled within an allowance, even if an irregularity exists on the wafer, and so a large number of integrated circuits may be tested reliably in one testing operation.
It is noted that the pressure member mentioned here is a member for pressing the plurality of probes provided on the membrane against the wafer and does not include a material (elastomer and the like) for attaching the pressure member to the membrane.
(5) In the semiconductor device manufacturing method of paragraphs (3) or (4), a plurality of pressure members may be provided.
(6) In the semiconductor device manufacturing method of paragraphs (3) or (4), a plurality of pressure members may be provided, and the pressure load is applied to planes of the plurality of pressure members on the side opposite the wafer in pressing the plurality of probes.
These manufacturing methods allow the reliability and productivity of the semiconductor devices to be enhanced because there are a plurality of pressure members and the irregularity absorbing capability is enhanced. Further, it is possible to avoid problems of the wafer being damaged and the longevity of the probe being reduced due to transient concentration of the load because, even if a dead load (pressure load) of a weight works on part of the probes temporarily, the total load applied by one weight is within a range of the dead load (pressure load) of that weight.
(7) In the semiconductor device manufacturing method of paragraphs (3) or (4), one weight is used to apply the pressure load and the planes of the pressure members on the side opposite from the wafer are connected with the weight by a plurality of elastic bodies.
(8) In the semiconductor device manufacturing method paragraphs (3) or (4), there are a plurality of pressure members, one weight is used to apply the pressure load, and the planes of the pressure members on the side opposite from the wafer are connected with the weight by a plurality of elastic bodies.
These manufacturing methods allow the structure to be simplified because there is only one weight. Further, because it is not necessary to set the size of the weight in the wafer plane direction in correspondence to the size of the pressure plate, it is possible to provide a larger (heavier) weight. Still more, because it is possible to more flexibly accommodate an irregularity on the surface of the wafer, the system works more effectively even for an irregularity on the surface of the wafer which cannot be absorbed by the elastic body by using a more flexible material for the weight.
(9) Semiconductor devices may be manufactured by any one of the manufacturing methods of paragraphs (1) through (8). The highly reliable semiconductor devices whose productivity is enhanced may be provided by the inventive manufacturing methods described above.
The specific nature of the invention, as well as other objects, uses and advantages thereof, will clearly appear from the following description and from the accompanying drawings in which like numerals refer to like parts.
USPTO Backgrounds
USPTO Backgrounds