1. Field of the Invention
The present invention relates to a method for manufacturing and operating a nonvolatile memory, and more particularly to a method for manufacturing and operating a nonvolatile memory, in which a floating gate is formed on a silicon substrate to reduce the difference in heights between a memory region and logic region so that a process margin is assured when contact holes are subsequently formed.
2. Description of the Related Art
The functionally ideal memories available are nonvolatile semiconductor memories, which are easily programmed by switching their memory states using an electrical method voluntarily by a user, and maintain their memory states even when power is not supplied.
In terms of process technique, nonvolatile semiconductor memories (NVSM) are divided into floating gate memories and Metal-Insulator-Semiconductor (MIS) memories in which at least two kinds of dielectric films are stacked.
The floating gate memories exhibit memory characteristics using potential wells. For example, EPROM tunnel oxide (ETOX) structure is the most widely applied structure of recent flash EEPROMs. When the integration of the structure of an ETOX type flash cell is improved, a short channel effect occurs. In order to prevent the generation of leakage current of a floating gate and short between a source/drain contact and the floating gate, the cells must be separated from each other by a designated interval, thereby increasing the sizes of the cell.
Hereinafter, problems of the conventional nonvolatile memory will be described with reference to the accompanying drawings.
FIG. 1 is a schematic sectional view of a conventional nonvolatile memory. Now, a conventional method for manufacturing a flash memory is described with reference to FIG. 1, as follows. First, a shallow trench isolation (STI) film 110 for isolating memories from each other is formed on a silicon substrate 100, and a tunnel oxidation film 120 is formed thereon by thermal oxidation.
Then, a floating gate polysilicon film 130, an insulating film 140, such as an ONO dielectric film, and a control gate polysilicon film 150 are sequentially formed on the tunnel oxidation film 120, and a stack-type structure is obtained by photolithography and etching.
Thereafter, channel ion implantation (not shown) is performed, source/drain junction regions 160 are formed, and then an interlayer insulating film 170 is deposited thereon. Contact holes are formed by photolithography and etching such that the contact holes are connected to the source/drain junction regions 160, and a metal wiring 180 is formed on the contact holes.
According to the above conventional method for manufacturing the flash memory, since a floating gate is formed on the silicon substrate, the height of the floating gate causes difficulty in obtaining a contact margin when the contact holes are formed. As the memory has been minimized, the above problem is made more severe. Further, when the flash memory is integrated with a logic element into a single chip, a difference in heights between a logic region and a flash memory region is increased, thus decreasing the margin in a subsequent step of forming the contact holes.
USPTO Backgrounds
USPTO Backgrounds