The present invention relates to a technique for inputting information which is suitable for use in a semiconductor device supplied with the information, e.g., a technique effective for application to a DDR (Double Data Rate)-operable SDRAM (Synchronous Dynamic Random Access Memory).
With the speeding up of operation, an external interface such as an SDRAM is now migrating toward a small-amplitude signal interface like SSTL (Stub Series Terminated Transceiver Logic). A differential amplifier circuit provided with a current mirror load has widely been adopted for an input buffer of the SSTL specs-based interface. Since a through current always flows in the differential amplifier circuit in an active state, the differential amplifier circuit increases power consumption as compared with a CMOS input buffer comprising a complementary type MOS circuit, but is capable of receiving a small signal therein at high speed.
In a synchronous memory like the SDRAM, timing provided to operate it is controlled based on an external clock signal like an externally supplied system clock signal. This type of synchronous memory has the feature that the setting of internal operating timings by the use of the external clock signal becomes relatively easy and a relatively high-speed operation is made possible.
As the SDRAM used herein, there are known a so-called SDR (Single Data Rate) type SDRAM wherein the input and output of data are performed in synchronism with the rising edge of an external clock signal, and a so-called DDR type SDRAM wherein the input and output of data are carried out in synchronism with both the rising and falling edges of an external clock signal.
USPTO Backgrounds
USPTO Backgrounds