The present invention relates generally to integrated circuit memory devices, and in particular to the development of Dynamic Random Access Memory (DRAM) devices having multiple capacitors utilizing the same die area.
Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes integrated circuit memory devices.
Integrated circuit memory devices are rapidly-accessible memory devices. In an integrated circuit memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes Dynamic Random Access Memory (DRAM). A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line.
The memory cells are typically arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines, i.e., the bit lines and word lines. Memory cells are located at intersections of the bit lines and word lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to an address decoder. In response to the decoded address, row access circuitry activates a word line. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. In response to the decoded column address, column access circuitry selects a bit line. For a read operation, the selected word line activates the access transistors for a given word line address, and data is latched to the selected bit line.
Designers are under constant pressure to increase memory cell density to reduce costs and increase performance. As memory cell density is increased, memory cell size is generally decreased. Available die area for the capacitor also generally decreases with decreasing memory cell size. As capacitance is proportional to capacitor surface area, decreasing the available die area makes it more difficult to maintain capacitance levels. While three-dimensional structures, enhanced surface area materials and high-k dielectric materials can be used to increase capacitance for a given die area, these techniques have practical limitations.
To read a memory cell of the type described herein, the charge stored on the capacitor is sensed and amplified. Sensing of the charge stored on the capacitor often involves sensing a differential between a reference node and a sensing node coupled to the capacitor. If the capacitance of the memory cell capacitor becomes too small, it may become difficult or impossible to sense this differential.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative structures and processes for improving capacitance in memory devices.
Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.
For one embodiment, the invention provides a memory cell. The memory cell includes an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line. The memory cell further includes a capacitor coupled to the first source/drain region of the access transistor. The capacitor is overlying at least a portion of a capacitor of a second memory cell, wherein the second memory cell has an access transistor having a source/drain region coupled to the bit line.
For another embodiment, the invention provides a memory cell. The memory cell includes an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line. The memory cell further includes a capacitor coupled to the first source/drain region of the access transistor through an extension. The extension is laterally adjacent a second capacitor of a second memory cell and the first capacitor is underlying at least a portion of the second capacitor.
For yet another embodiment, the invention provides a method of forming a pair of memory cells. The method includes forming a first insulative layer on the substrate, patterning the first insulative layer to define future first source/drain regions, and forming a pair of first source/drain regions in the substrate. The method further includes forming a first storage node coupled to a first one of the pair of first source/drain regions and forming an extension coupled to a second one of the pair of first source/drain regions, wherein the extension is isolated from the first storage node. The method still further includes forming a first cell dielectric layer overlying the first storage node and the extension, forming a first cell plate layer overlying the first cell dielectric layer, forming a second insulative layer overlying the first cell plate layer, and exposing a portion of the extension. The method still further includes forming a second storage node coupled to the exposed portion of the extension and isolated from the first storage node and the first cell plate layer, forming a second cell dielectric layer overlying the second storage node, forming a second cell plate layer overlying the second cell dielectric layer and forming a third insulative layer overlying the second cell plate layer. The method still further includes cleaving the substrate, thereby exposing a surface of the substrate, and planarizing the exposed surface of the substrate to expose the first source/drain regions. The method still further includes forming word lines overlying at least a portion of the pair of first source/drain regions and forming a second source/drain region in the substrate interposed between the word lines.
For a still further embodiment, the invention provides a method of forming capacitors for a pair of memory cells. The method includes forming a first insulative layer on a substrate, removing a portion of the first insulative layer to expose first and second portions of the substrate and forming a first capacitor overlying the first insulative layer and coupled to the first portion of the substrate, wherein the first capacitor includes a storage node, a cell dielectric layer and a cell plate layer. The method further includes forming a conductive extension coupled to the second portion of the substrate and isolated from the storage node of the first capacitor and forming a second capacitor overlying at least a portion of the first capacitor and coupled to the second portion of the substrate through the conductive extension, wherein the second capacitor includes a storage node, a cell dielectric layer and a cell plate layer.
Further embodiments of the invention include apparatus and methods of varying scope.
USPTO Backgrounds
USPTO Backgrounds