Various techniques are known in the art for sharing memory resources between processors. For example, U.S. Pat. No. 7,818,529, whose disclosure is incorporated herein by reference, describes an integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. The first interface decoder is coupled to a control chip through a first Serial Peripheral Interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit can share the same memory.
USPTO Backgrounds
USPTO Backgrounds