1. Field of the Invention.
This invention relates to a circuit for synchronizing information bits to a wide range of frequencies, in general, and to a circuit for establishing a clock signal synchronization with low jitter, in particular.
2. Prior Art.
There are many synchronizing circuits known in the art. These circuits can be used to synchronize the operation of various circuits or circuit functions. In the context of the technology described herein, the prior art is, basically, a circuit that recovers a clock signal from digital data. The circuits described in the prior art, include, inter alia, a transition detector, a phase detector, an up-down counter, a variable divider and a window counter that, basically, measures how far the signal is from sync. However, the up-down counter has never been used in an existing design and the window counter has not been used in an existing implementation known to applicants. The prior art uses a variable divider network which determines when the incoming signals exhibit transitions from one state to another. The prior art circuit operates to divide down a reference signal to make it match the incoming signal. The window of the counter of the prior art system is set at half the clock frequency and counts the difference between the incoming signal and the transition. The prior art circuitry tries to correct this difference in a half-step-type jump to bring the signals into sync rapidly. The prior art system may include a counter referred to as a "K counter" to assure that the system does not correct too often and produce an undesirable "jitter" effect.
This type of sync circuit is especially useful in, for example, a data link where a signal, e.g. a video signal, is sent over an RF link. That is, the sync circuit recovers and converts the transmitted video signal to a specified base band. However, it is also necessary and/or desirable to recover a clock signal from the data transition so that the data can be clocked in and used as digital information.
The clock signal is necessary to sample the data. That is, a data link is frequently used in conjunction with a match filter which, essentially, integrates over the data time period to indicate that a data bit was a one or a zero (or an estimate of some range in between). In order to know what period is to be sampled, a clock signal is necessary and this clock signal is recovered from that data which is supplied. In other words, as part of the recovery of the data, and in order to determine exactly what kind of data it is, the clock signal must first be recovered out of that data.
Reference is made to U.S. Pat. No. 4,280,099, entitled DIGITAL TIMING RECOVERY SYSTEM, by G. D. Rattlingourd, and assigned to the common assignee. This patent describes a method and apparatus for performing digital data recovery. The patent also refers to the analog phase lock loop technique which is a common method of performing this sampling. The patent also describes some of the disadvantages and shortcomings of the analog approach as compared to the digital technique. In most prior art digital techniques, the circuit is designed to work on only one particular frequency. That is, data is supplied at a certain rate and an oscillator is selected which operates at a particular multiple of the data rate. Thereafter, the circuit is capable of recovering a clock signal for only a particular data rate signal. The basic method used to recover the clock from incoming video data is to start with a frequency about 100 times larger than the desired recovered clock signal, divide this frequency by 100, and then compare the transitions of the incoming video signal with the rising transition of the divided by 100 frequency. If the video signal transition is prior to the divided frequency transition, the "divide by" factor is changed from 100 to 99 for one period. This effectively, moves the divided frequency transition closer to the video input signal transition. This operation continues until the two transitions line up.
Conversely, if the video transition is subsequent to the divided frequency transition, the "divide-by" factor is changed to 101 for one period. This process is continued until the input signal transition lines up with the clock signal transition. At this point, the divided clock is the recovered clock for the input video data.
Thus, the prior art provides a system for effecting a synchronization which is subject to a relatively large "error" condition and with many limitations on the operation thereof.
USPTO Backgrounds
USPTO Backgrounds