1. Field of Invention
The present invention is directed to a digital modulation phase locked loop and more particularly to a system for synchronizing a local pseudo-random sequence signal generator to a received baseband signal wherein modulation was performed using a pseudo-random sequence signal.
2. Description of the Prior Art
In communication systems phase locked loops have been used to synchronize a variable frequency oscillator in phase or frequency with the carrier portion of a received signal. In digital type communication systems the problem of phase jitter caused by a lack of synchronization between the phase of the local oscillator, usually a train of clock pulses, and the carrier or reference signal of the received signal, causes errors in the detected bit stream.
A prior art system of interest is disclosed in U.S. Pat. No. 3,447,085, entitled "Synchronization of Receiver Time Base in Plural Frequency Differential Phase Shift System" by T. DE HAAS et al. The system disclosed in the prior art patent achieves synchronization of the receiver time base with the time base of the received signals without the use of pilot tones. Locally generated signals are combined with the received signal and correlated to derive output signals which vary in accordance with the phase difference between the locally generated signals and the time base of the received signal. The output signals are fed to decision circuits which produce command signals. The command signals are used to control the frequency of the receiver time base by adding or deleting pulses from a pulse train, to thereby produce a receiver time base signal whose phase corresponds to the phase of the time base of the received signals.
Another prior art circuit of interest is disclosed in U.S. Pat. No. 3,745,248, entitled "Course Initial Timing Recovery Circuit", by EARL D. GIBSON. The circuit of the prior art patent achieves synchronization of a locally generated timing signal with the baud rate of a received signal without the use of pilot tones. A pair of comparators are used to provide output signals each time the received signal crosses through one of several preselected thresholds. An EARLY/LATE detector compares the locally generated timing signal against the output signals from the comparators and provides a first signal when the comparison is late and a second signal when the comparison is early. A pulse train generator generates the local timing signal which signal is modified by the first or second detection provided signals by adding or deleting pulses into the local timing signal to synchronize the local timing signal to the baud rate of the received signal.
USPTO Backgrounds
USPTO Backgrounds