1. Field of the Invention
The present invention relates to address decoding. Embodiments of the present invention relate to a circuit for driving an address decoder which is tolerant of metastable signals.
2. Description of the Prior Art
In a data processing apparatus, such as a pipelined data processing apparatus, a series of serially connected stages are formed. The processing circuitry of each processing stage is responsive to input signals received from preceding processing stages in the pipeline or from elsewhere and generates output signals. Between each stage of the pipeline is provided a signal capture element such as a latch or a sense amplifier into which one or more signal values are stored. The latch receives the input signals, stores the input signal value and presents this stored value on its output in response to a clock signal provided thereto.
In order for the latch to reliably store the input signals provided at its input, it is necessary for the input signal to achieve a particular voltage level representative of a value to be stored at a time which is no later than a predetermined period prior to the clock signal being provided to the latch (known as the set-up period) and for this voltage level to be maintained for a predetermined period following the provision of the clock signal (known as the hold period).
However, in the event that the input signals provided to the latch transitions in the set-up or hold period then metastability can occur. A consequence of this is that the output provided by the latch does not make a clean transition between logic levels but instead achieves a value somewhere therebetween, known as a metastable voltage. Typically, the metastable voltage is a level approximately midway between the valid logic level voltages.
Metastability is typically avoided by ensuring that the input signals only transition outside of the set-up and hold periods. This ensures that the input signals can be cleanly sampled by the latch.
However, in order to attempt to improve the performance of data processing apparatuses, it is known to increase the speed at which the processing stages are driven by increasing the clock rate until the slowest processing stage in the pipelined processor is unable to keep pace. Also, in situations where it is desired to reduce the power consumption of the data processing apparatus, it is known to reduce the operating voltage up to the point at which the slowest processing stage is no longer to keep pace. In both of these situations it is no longer possible to ensure that the signal transitions do not occur within the set-up and hold periods and metastability can occur.
A consequence of such metastability is that erroneous data values may be generated. In extreme cases, erroneous control signals may also be generated which may cause valid data to be corrupted. For example, should metastability occur whilst performing an access to a memory then a corruption of the internal state of the memory may occur.
In order to avoid metastability causing corruption of the internal state of the RAM, it is known to place write accesses to the RAM in a write queue. The write accesses are then only allowed to occur once system level validation process has confirmed that the signals associated with the write access are valid and that no metastability in those signals exists.
It is desired to provide techniques for accessing memory which are tolerant of metastable signals.
USPTO Backgrounds
USPTO Backgrounds