1. Field of the Invention
The present invention relates to a multilayer type test board assembly for high-precision inspection, and more particularly to a test board assembly for high-precision inspection capable of measuring a micro current and a low current by safely protecting the test board assembly from an influence of external signals.
2. Description of the Related Art
In general, a semiconductor device is manufactured by a fabrication process that includes forming patterns on a wafer and an assembling process that includes assembling the wafer having the patterns into unit chips.
An electric die sorting (EDS) process is performed between the fabrication and assembling processes that includes inspecting the electrical characteristics of the unit chips of the wafer.
In the EDS process, undesirable unit chips of the wafer are sorted and only the unit chips of high quality are subject to subsequent processes.
The EDS process mainly uses a tester, which is an inspection apparatus that applies electrical signals to the unit chips to determine whether the unit chips are acceptable by checking signals from the applied electrical signals.
The tester is provided with a test board that applies electrical signals to the unit chips and that receives electrical signals from the chips.
However, since a conventional test board performs various functions using devices such as an analog-to-digital (A-D) converter, a digital-to-analog (D-A) converter, a micro control unit (MCU), and a measure probe simultaneously, the size of the test board can be excessively large. If the size of the test board is large, the head size of the tester is also large. Therefore, a sufficient work space is necessary to utilize the tester, which is uneconomical.
In order to solve this problem, a technology in which test boards are separated according to their functions, and are spaced apart from each other by a predetermined interval, has been suggested. Japanese Patent Laid-Open No. 2003-75515, entitled “Tester for Semiconductor Integrated Circuit and its Testing Method,” incorporated herein in its entirety by reference, discloses a structure in which multifunctional substrates are divided and multilayered.
FIG. 1 is a side sectional view of a conventional structure 100 in which test boards TB are multilayered.
As shown in FIG. 1, the structure 100 includes a plurality of test boards or substrates TB, that are multilayered at predetermined intervals by separating the substrates or test boards TB according to their functions using spacers S. This results in a significant reduction in the area size of the test boards TB. Thus, the amount of space for mounting a tester and a tester head in test equipment is reduced, which is economical.
However, the test equipment not only performs a function of determining whether unit devices such as a semiconductor device are acceptable, but the test equipment also precisely measures output signals received from the unit devices being tested. Here, a plurality of mounting devices are mounted to the test boards TB, and are used in performing precise measurements. However, the mounting devices generate natural signals, such as electrical signals.
Therefore, since those mounting devices related to precise measurements of the test boards may react sensitively to external electrical signals, for example, from other mounting devices generating natural signals, while measuring the output signals from the unit devices, the ability for the test equipment to take precise measurements may be limited due to the influence of the external signals on the mounting devices.
USPTO Backgrounds
USPTO Backgrounds