In semiconductor manufacturing, a fabricated integrated circuit (IC) device is usually assembled into a package to be utilized on a printed circuit board as part of a larger circuit. In order for the leads of the package to make electrical contact with the bonding pads of the fabricated IC device, the metal bond is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame, or a solder ball connection to a ceramic or polymeric chip carrier.
In the past, Al and Al alloys have been used as conventional chip wiring materials. Al wiring material is being replaced by Cu and Cu alloys since Cu wiring provides improved chip performance and superior reliability when compared to Al and alloys of Al. The packaging of IC devices employing copper wiring presents a number of technical issues related to the reaction of copper with material used in the solder-ball process and/or susceptibility of copper to environmental attack and corrosion.
A typical prior art fabricated IC structure before interconnecting with a package is shown in FIG. 1. Specifically, the fabricated prior art IC structure shown in FIG. 1 comprises a semiconductor wafer 10 having at least one Cu wiring region 12 embedded in its surface. It is noted that semiconductor wafer 10 includes a plurality of IC device regions therein. For clarity, these IC device regions are not shown in the drawing. The prior art IC structure of FIG. 1 further includes a passivating layer 14 formed on the surface of semiconductor wafer 10 having an opening therein extending over regions of Cu wiring 12. In the opening, there is shown a terminal via barrier layer 16 which also extends over portions of the passivating layer near the opening. A second passivating layer 18 typically composed of an organic material such as a polyimide film having an opening over Cu wiring 12 is located on the surface of passivating layer 14.
The prior art structure shown in FIG. 1 is normally fabricated by providing a planarized IC wafer containing Cu wiring therein; forming a passivating layer on the surface of the planarized IC wafer; reactive ion etching (RIE) the passivating layer to form terminal via openings over the underlying Cu wiring; providing a barrier layer to said terminal via opening; forming an organic passivating layer on the surface of the barrier layer; and then etching the outer passivating layer to provide an opening to the Cu wiring.
In current practice, large (90 .mu.m) terminal via openings are formed in passivating layer 14 to expose pads that are created at the underlying Cu wiring level. This process that is utilized in the prior art for Cu back-of-the-line (BEOL) structures was developed from previous BEOL technology wherein wirebond connections are made directly through the terminal via openings to the underlying Cu wiring. For current applications where additional Cu wiring levels are being employed, there are several problems with using the above technology.
First, since copper does not form a self-passivating oxide layer as does aluminum, copper exposed to atmospheric conditions will corrode to a depth of several thousand angstroms degrading the reliability of the IC device. Second, for the solder-ball application, the commonly used ball-limiting or barrier metallurgies may not be compatible with copper metallization and might allow the mixing of the leadtin (Pb--Sn) solder material with the underlying copper. In this event, brittle Cu-Sn intermetallics will form increasing the electrical resistivity and compromising the reliability of the interconnection scheme.
In view of the drawbacks mentioned with the prior art process of a packaging connection on copper wiring IC structures, there is a continued need to develop new and improved processes that overcome the disadvantages associated with prior art processes. The requirements of this structure and method are that it be compatible with conventional chip packaging and test methodologies and that it protect the copper wiring from environmental attack and/or reactions with the packaging materials.
USPTO Backgrounds
USPTO Backgrounds