The present invention relates to an analog/digital converter, and more particularly to a fast A/D converter which uses remainder signals for determining some of the bits.
Many important signal sources produce their signals in analog, or continuously varying, form. Examples include the human voice or the output of a strain gauge. Analog signals must be converted to digital form before they are suitable for digital processing or digital communication. The speed with which this conversion takes place is an important factor, particularly if the analog signals have a high frequency, since the degree to which a digital signal can conform to its analog equivalent depends upon how frequently these conversions can be made.
A number of schemes for converting analog signals to their digital equivalents have been developed. One such prior art A/D converter is illustrated in FIG. 1. In FIG. 1, a reference voltage source 20 supplies a reference voltage V.sub.R to a biasing network 22 in the form of a voltage divider made of series-connected resistors 24. Biasing network 22 provides progressively increasing bias potentials to one terminal of each of comparators 26. The remaining input terminals of comparators 26 are supplied in common with an analog voltage V.sub.in applied to input terminal 28. The output of each comparator 26 goes "high" if the analog input voltage equals or exceeds the bias voltage for that comparator. However, these outputs do not represent a binary word equivalent to the analog input voltage V.sub.in. Instead, these outputs must be supplied to Highest Comparator "ON" Detector Circuit 30, which determines which comparator 26 is connected to the higest bias potential which does not exceed the analog input V.sub.in. The result is then converted by encoder 32 into a multi-bit binary signal on output terminals 34.
It will be apparent to those skilled in the art that the circuit of FIG. 1 is incomplete, with missing components indicated by dots. That is, a large number of resistors 24 and comparators 26 must be used in order to achieve a digital output having a significant number of bits. In fact, in order to achieve a digital output word of n bits, 2.sup.n-1 comparators must be employed. The one great advantage of the circuit of FIG. 1 is that it is fast.
There exist prior art A/D converters which provide a relatively large number of output bits without using the excessive number of components of the system illustrated in FIG. 1. In the "dual-slope" converter, for example, an analog input voltage charges a capacitor while a clock signal is delivered to a binary counter. When the counter overflows the capacitor is then discharged at a constant rate, with the counter receiving clock pulses until the capacitor has completely discharged. As a result the final binary output of the counter will correspond to the original analog input voltage. However, A/D schemes which rely upon a clock in such a manner require a relatively long time to make the conversion. In the dual-slope converter, for example, the time required for the conversion is on the order of 2.sup.n+1 clock cycles. An eight-bit dual-slope converter would require 512 pulses for each conversion.
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USPTO Backgrounds