This invention relates to a semiconductor substrate for a one-chip electronic device and its manufacturing method.
The spread and popularization of portable telephones and other compact wireless communication devices has increased the needs to downsizing, low-power consumption, and cost reduction of high frequency circuits incorporated in these devices. To this end, a monolithic IC has been recently developed as a one chip electronic device incorporating active elements, such as transistors and diodes, as well as passive elements, such as resistors, capacitors, and inductors, which are integrated on a semiconductor substrate, especially on a silicon substrate, together with various circuits including high-frequency oscillators, amplifiers and filter circuits.
However, when the inductors are formed on semiconductor substrates, the problem arises in that parasitic capacitance and parasitic resistance (i.e., eddy current loss) are produced between electric conductors, constituting the inductor, and the semiconductor substrates, as described in xe2x80x9cLarge Suspended Inductors on Silicon and Their Use in a 2-xcexcm CMOS RF Amplifier,xe2x80x9d by J. Y. C. Chang et al., IEEE Electron Device Letters, Vol. 14, No.5, pp.246-248 (1993). Accordingly, a key for obtaining the inductors having high Q (quality factor) is to reduce the parasitic capacitance and the parasitic resistance.
To solve this problem, Chang et al. propose to form a groove (i.e., a cavity) under an inductor disposed on the surface of a semiconductor substrate. However, this arrangement brings the following problems.
First, the process of removing a silicon region located under the inductor by etching is inconsistent with the conventionally and widely used silicon LSI manufacturing processes. Second, according to the above-described arrangement, a mechanical strength of the insulator is insufficient due to an aerial wiring structure of the inductor.
To solve the above-described problem, the unexamined Japanese patent publication 2001-77315 discloses an IC device including a groove having a depth of 20 xcexcm or more formed partly on a semiconductor substrate. According to this prior art, the groove is filled with an insulating material. Active elements, including inductors, are formed on the surface of the insulating material thus filled into the groove. This arrangement makes it possible to effectively reduce the parasitic capacitance and the parasitic resistance residing between the electric conductor constituting the inductor and the semiconductor substrate. This arrangement provides good matching with the conventional silicon LSI manufacturing processes and accordingly assures a sufficient strength.
However, according to the method disclosed in the unexamined Japanese patent publication 2001-77315, the insulating material is an organic insulating fluid which causes the following problems.
In general, this kind of insulating fluid causes a volumetric change (i.e., volumetric shrinkage) in the process of self-hardening. This possibly causes an altitudinal difference between a semiconductor substrate surface on which the active elements are formed and an upper surface of the shrunken insulating material on which the passive elements are formed. Furthermore, the upper surface of the shrunken insulating material is not flat. The volumetric change possibly produces a stress acting on the substrate which results in warp of the substrate. To flatten the upper surface of the shrunken insulating material, this prior art discloses a method for removing an excessive insulating material other than the groove according to the CMP (Chemical-Mechanical Polishing). However, manufacturing processes of the IC device become complicated.
In view of the foregoing problems of the prior art, the present invention has an object to provide a novel semiconductor substrate capable of sufficiently reducing the parasitic capacitance and the parasitic resistance and also assuring a sufficient strength for an insulating layer, which is preferably applicable to a semiconductor device comprising active and passive elements formed on the semiconductor substrate.
Another object of the present invention is to provide a related manufacturing method of the semiconductor substrate.
To accomplish the above and other related objects, the present invention provides a semiconductor substrate comprising a passive element disposed on an insulating member, an active element formed in a surficial region of the insulating member, and a thermal oxide layer formed at a region corresponding to the passive element, the thermal oxide layer having a thickness of 10 xcexcm or more.
Providing the thermal oxide layer having the thickness of 10 xcexcm or more is effective to sufficiently reduce the parasitic capacitance and the parasitic resistance. As the passive elements do not employ an aerial wiring structure, it becomes possible to assure a sufficient mechanical strength.
According to the semiconductor substrate of the present invention, it is preferable that the semiconductor substrate is an SOI (Silicon On Insulator) substrate. It is also preferable that the passive element is operative at high frequencies.
It is also preferable that a cavity is formed inside the thermal oxide layer. For example, the cavity has a relative dielectric constant of approximately 1 which is fairly smaller than 3.9 of the silicon dioxide. It becomes possible to reduce the parasitic capacitance compared with the one having no cavity. As a result, it becomes possible to obtain the effect of reducing transmission loss with a relatively thin thermal oxide layer.
The present invention provides a first method for manufacturing a semiconductor substrate comprising a passive element disposed on an insulating member and an active element formed in a surficial region of the insulating member. The first manufacturing method comprises a step of forming a groove having a depth of 10 xcexcm or more at a predetermined portion of the semiconductor substrate where the passive element is formed, and a step of performing a thermal oxidation treatment to let an oxide film grow from an inside surface of the groove so as to fill an inside space of the groove with a thermal oxide film thus grown.
The present invention provides a second method for manufacturing a semiconductor substrate comprising a passive element disposed on an insulating member and an active element formed in a surficial region of the insulating member. The second manufacturing method comprises a step of forming a plurality of grooves each having a depth of 10 xcexcm or more and arranged adjacent to each other at a predetermined portion of the semiconductor substrate where the passive element is formed, and a step of performing a thermal oxidation treatment to let an oxide film grow from an inside surface of the groove so as to fill an inside space of the groove with a thermal oxide film thus grown and turn an entire portion intervening between adjacent grooves into a thermal oxide layer.
According to the first and second manufacturing methods, the oxide film grows and fills the inside space of the groove in the process of forming the thermal oxide layer. Thus, no stress is applied to the substrate material when the oxide film causes volumetric expansion. The semiconductor substrate is not suffered with warp. Furthermore, the thick thermal oxide layer has a flat surface substantially level with the semiconductor substrate surface. The thermal oxide layer can be formed at a desired region. No special flattening process is required. Furthermore, the first and second manufacturing methods of the present invention makes it possible to manufacture a great amount of semiconductor substrates without changing the conventional LSI manufacturing processes. This makes it possible to realize a mass production of high-performance semiconductor devices.
According to the first or second manufacturing method of the present invention, it is preferable that each groove has a width of 10 xcexcm or less, and the width of a semiconductor material intervening between two adjacent grooves is 81.8% or more with respect to the groove width. This ensures that the groove is completely filled with the thermal oxide film.
Furthermore, it is preferable that the first or second manufacturing method of the present invention further comprises a step of forming a laterally extending bore for connecting adjacent grooves at a bottom region thereof so as to leave a cavity tying the plurality of grooves in a row, after accomplishing the step of forming the plurality of grooves arranged adjacent to each other. And, the thermal oxidation treatment is performed to let the oxide film grow from an inside surface of the cavity as well as from the inside space of the groove so as to fill the inside space of the groove with the thermal oxide film thus grown and leave a closed cavity shrunken from the cavity.
Furthermore, it is preferable that the first or second manufacturing method of the present invention further comprises a step of forming a laterally extending bore for connecting adjacent grooves at a bottom region thereof so as to leave a cavity tying the plurality of grooves in a row, after accomplishing the step of forming the plurality of grooves arranged adjacent to each other. And, the thermal oxidation treatment is performed to let the oxide film grow from an inside surface of the cavity as well as from the inside space of the groove so as to fill the inside space of the groove with the thermal oxide film thus grown and turn an entire portion intervening between adjacent grooves into a thermal oxide layer, and finally leave a closed cavity shrunken from the cavity.
Furthermore, the present invention provides a third method for manufacturing a semiconductor substrate comprising a passive element disposed on an insulating member and an active element formed in a surficial region of the insulating member. The third manufacturing method comprises a step of forming a plurality of grooves each having a depth of 10 xcexcm or more and arranged adjacent to each other at a predetermined portion of the semiconductor substrate where the passive element is formed, a step of performing a thermal oxidation treatment to let an oxide film grow from an inside surface of the groove so as to incompletely fill an inside space of the groove with a thermal oxide film thus grown and turn an entire portion intervening between adjacent grooves into a thermal oxide layer, and a step of filling a narrowed groove incompletely shrunken from the groove with an insulating material.
It is preferable that the third manufacturing method of the present invention further comprises a step of forming a laterally extending bore for connecting adjacent grooves at a bottom region thereof so as to leave a cavity tying the plurality of grooves in a row, after accomplishing the step of forming the plurality of grooves arranged adjacent to each other. And, the thermal oxidation treatment is performed to let the oxide film grow from an inside surface of the cavity as well as from the inside space of the groove so as to incompletely fill the inside space of the groove with the thermal oxide film thus grown and turn an entire portion intervening between adjacent grooves into a thermal oxide layer, and finally leave a closed cavity shrunken from the cavity.
According to the third manufacturing method of the present invention, it is preferable that a width of a semiconductor material intervening between two adjacent grooves is 81.8% or less with respect to a groove width of the groove.
According to the third manufacturing method of the present invention, it is preferable that the thermal oxidation treatment is performed together with a thermal oxidation treatment performed for forming an element separating oxide film on an upper surface of the semiconductor substrate.
According to the third manufacturing method of the present invention, it is preferable that the thermal oxidation treatment is performed in an oxidizing atmosphere containing hydrogen at 965xc2x0 C. or above. It is especially preferable that the thermal oxidation treatment is performed in an oxidizing atmosphere containing hydrogen at 1,100xc2x0 C. or above.
Moreover, it is preferable that a reactive ion etching or a plasma etching is used in the step of forming the groove. For example, the anisotropic etching such as the reactive ion etching using a fluorine group gas, especially the high-density plasma etching, ensures that a resultant groove has a depth of 10 xcexcm or more and a width of 1 xcexcm or less so as to extend perpendicularly to the substrate surface.
According to the third manufacturing method of the present invention, it is preferable that the semiconductor substrate is an SOI (Silicon On Insulator) substrate and the passive element is operative at high frequencies.
USPTO Backgrounds
USPTO Backgrounds