1. Field of the Invention
The present invention relates to a semiconductor device which operates in synchronization with a clock, and particularly relates to a synchronous semiconductor device having a configuration for controlling operation timings after issuing various commands in response to latencies.
2. Description of Related Art
Recently SDRAM (Synchronous Dynamic Random Access Memory) of DDR (Double Data Rate) type has been a mainstream as a synchronous semiconductor memory device to allow high speed operation. Since this DDR-SDRAM (referred to as DDR-SDRAM hereinafter) is provided with a latency counter in which the number of clock cycles required between issuing a command and completing data transmission in read/write operation is set as a latency and the set latency is counted based on an internal clock. In the DDR-SDRAM, different latencies are defined for various types of operations and a user can preset a desired latency in a mode register.
Meanwhile, as the speed of an external clock of the DDR-SDRAM increases, a multistage latency counter capable of corresponding to latencies covering a wide range is required. Therefore, an increase in consumption current becomes a problem. A configuration is proposed in Patent Reference 1 given below as a latency counter capable of suppressing an increase in consumption current. The patent reference 1 disclose the latency counter of a dual-phase configuration including dual counter circuits in each of which the external clock is frequency-divided by two to generate internal clocks having phases different by 180 degrees from each other, and the counter circuits are synchronized with the internal clocks respectively. As shown in FIG. 2 of the patent reference 1, the operation of selectors is controlled in response to a set latency, and a signal path through either or both of the dual counter circuits is formed for an input command signal, thereby selectively counting even latencies and odd latencies. By this configuration, the internal clocks whose frequency is half that of the external clock can be used, and thus, it is effective for reducing the consumption current.
Patent Reference 1: Japanese Patent Application Laid-open No. 2007-115351
However, as the speed of the external clock of the DDR-SDRAM further increases, the consumption current in the conventional latency counter is required to be further reduced. Particularly, internal clocks obtained by frequency-dividing the external clock by two are respectively applied to a large number of D flip flops forming the dual counter circuits, the magnitude of the overall consumption current becomes negligible. Although the input command signal is activated within a limited period in the latency counter disclosed in the Patent Reference 1, it is in a state where the current always keeps flowing because the internal clocks are constantly operating. In this manner, when using a faster external clock in the conventional latency counter, a problem arises that there is a limit to suppress the consumption current.
USPTO Backgrounds
USPTO Backgrounds