The invention relates to electronic semiconductor devices, and, more particularly, to dielectric structures and fabrication methods for such structures.
The performance of high density integrated circuits is dominated by metal interconnect level RC time delays due to the resistivity of the metal lines and the capacitive coupling between adjacent lines. The capacitive cooling can be reduced by decreasing the relative permittivity (dielectric constant, k) of the dielectric (insulator) between adjacent lines.
Various dielectric materials have been suggested for use in silicon integrated circuits; namely, silicon dioxide (k about 4.0), fluorinated silicon dioxide (k about 3.0-4.0), organic materials such as polyimide, parylene, amorphous teflon (k about 1.9-3.9), and porous dielectrics such as silicon dioxide xerogels (k dependent upon pore size and typically 1.3-3.0). The porosity can be up to 99% by volume. See Smith et al, Preparation of Low-Density Xerogel at Ambient Pressure for Low k Dielectrics, 381 Mat.Res.Soc.Symp.Proc. 261 (1995).
Thin film silica xerogels for integrated circuit dielectric use can be fabricated by the generic steps of (1) precursor preparation, (2) spin coating, (3) aging, (4) solvent exchange, and (5) drying. The acid-base sol-gel reactions could be as follows:
Hydrolyze an alkoxide in a solvent: 
The solvent could be ethanol.
Then condense (gel) the hydrolyzed alkoxides: 
The condensation would be controlled so that spin coating occurs after partial condensation to a convenient viscosity.
The solvent exchange replaces the original solvent residing within the pores of gel by low-surface-tension solvent to reduce the capillary pressure during drying and minimizing the collapse of the pores. U.S. Pat. No. 5,561,318 discloses variations of the process.
However, silica xerogels have not yet become manufacturable.
The present invention provides silica xerogel dielectric with enhanced surface adhesion by plasma activation, ion beam shell formation, or open surface pore filling deposition and/or with reducing atmosphere sintering to lower dielectric constant and incorporated as a multilevel integrated circuit dielectric.
This has the advantages of manufacturable interlevel dielectrics incorporating xerogel to lower dielectric constant.
USPTO Backgrounds
USPTO Backgrounds