1. Field of the Invention
The field of art to which this invention relates is semiconductor manufacturing techniques. Specifically, this-invention relates to apparatus and methods for planarizing semiconductor wafers.
2. Description of the Related Art
The manufacture of an integrated circuit device requires the formation of various layers (both conductive and non-conductive) above the base substrate to form the necessary components and interconnects. During the manufacturing process, removal of a certain layer or portions of a layer must be achieved in order to pattern and form the various components and interconnects. Generally this removal process is termed "etching" or "polishing."
One of the techniques available for removal is a chemical-mechanical polishing (hereinafter "CMP") process in which a chemical slurry is used along with a polishing pad. The mechanical movement of the pad relative to the wafer and the abrasive slurry provide the abrasive force for removing the exposed material off the wafer surface. Planarization is a method of treating a surface to remove discontinuities, such as by polishing (or etching), thereby "planarizing" the surface. Various methods and apparatus have been developed in the art for polishing semiconductor wafers. However, it has been found that during polishing, the load imposed on the wafer leads to a higher concentration of slurry contacting the wafer edges, than its center. As a result, there is greater polishing action at the edges, thus causing center-to-edge non-uniformity in thickness and poor flatness of the wafer.
FIG. 1 shows a typical apparatus for polishing a semiconductor wafer 1. The apparatus includes a wafer carrier 2 which is coupled to a spindle 3, which in turn is coupled to any suitable motor or driving means (not shown) for moving the carrier 2 in the directions indicated by arrows 4a, 4b, and 4c (rotation). The spindle 3 supports a load 5, which is exerted against the carrier 2 and thus against the wafer 2 during polishing. The carrier 2 also includes a wafer retaining ring 6, which prevents the wafer 1 from sliding out from under the carrier 2 as the carrier 2 moves. The semiconductor wafer 1, which is to be polished, is mounted to the carrier 2, positioned between the carrier 2 and the rotatable turntable assembly 7 located below the carrier 2. The turntable assembly 7 includes a polishing table 8, on which a polishing pad 9 is positioned, and the polishing table 8 is rotated around the shaft 10 in the direction indicated by arrow 11 by any suitable motor or driving means (not shown).
During polishing, a slurry (not shown) is introduced to the polishing pad 9 which works its way between the wafer carrier 2 and the pad 9. Due to the load 5 which is imposed on the wafer carrier 2, a higher concentration of slurry generally contacts the wafer edges, as previously noted, resulting in a greater polishing action at the edges.
Efforts have been made in the art to obtain a more uniform polishing action across the wafer surface. The prior art teaches the various mechanisms employed to maintain the process uniformity and regional rates of removal during the CMP process. These mechanisms generally pump slurry through the platen and a porous polishing pad thereby ensuring an adequate supply of slurry at the polishing surface of the polishing pad.
While this process has its advantages, it also has drawbacks. The prior art mechanisms are expensive and complicated. The conventional polishing systems cannot be easily reconfigured to provide the adequate slurry delivery mechanism. Additionally, the slurry distribution mechanisms of the prior art do not provide for removal and/or recycling of the used slurry.
USPTO Backgrounds
USPTO Backgrounds