1. Field of the Invention
This invention relates to manufacture of a MOSFET device and more particularly to improved channel doping.
2. Description of Related Art
For circuit performance optimization, a different threshold voltage V.sub.t or different channel doping is required. In general, one extra mask is required to implement such circuit performance optimization.
FIG. 1A shows a prior art device 100 with a Vt' mask 28 and an active area 34 with a polysilicon gate 35. FIG. 1B shows a prior art device 200 with an active area 37 with another polysilicon gate 36. In FIGS. 1A and 1B an aspect of a typical prior art process for getting a different V.sub.t is illustrated. Device 200 is a normal device with threshold voltage V.sub.t1 and device 100 is another device with a threshold voltage V.sub.t2, V.sub.t1 .noteq.t.sub.t2. In general device 100 needs an extra V.sub.t ' mask 28 and ion implantation to get a different V.sub.t as provided with device 200.
FIGS. 3A to 3H show cross sectional views of a prior art process of fabrication of a semiconductor device on a silicon substrate 10 in which a P-well 12 and an N-well 14 in an N or P-sub 11 have been formed by a conventional process, with only the P-well 12 shown in FIGS. 3F and 3H.
Referring to FIGS. 3A AND 3B, a blanket silicon dioxide (Pad oxide) layer 16 is deposited over the entire device followed by a silicon nitride (Si.sub.3 N.sub.4) layer (18, 18', 18" which silicon nitride layer is patterned into Si.sub.3 N.sub.4 structures 18, 18', 18" to be used as a mask in forming active layer patterning.
In FIGS. 3C and 3D, a photoresist mask 20 has been formed over the N-well 14 portions of the product of FIGS. 3A and 3B, and then a NMOS field implantation of ions 22 is made in the P-well 12 producing dopant 13 in the surface of the P-well 12 aside from the Si.sub.3 N.sub.4 structures 18 and 18'.
In FIGS. 3E and 3F, a device similar to that in FIGS. 3C and 3D is shown with a slightly different scale, after the photoresist mask 20 has been removed. A field oxidation process is performed producing FOX structures 25, 25', 25" followed by stripping of the remaining portions of the silicon nitride layer 18, 18', 18" on the surface of the device. Then a V.sub.t1 blanket ion implantation with ions 24 is performed producing dopant 15 in the surface of the P-well 12 between the FOX structures 25, 25', 25". There are P-regions 27 beneath FOX structures 25, 25', 25" formed during ion implantation 22 and field oxidation step.
In FIGS. 3G and 3H, the product of FIGS. 3E and 3F is covered with a V.sub.t ' photoresist mask 28 on the right side leaving the space between one pair of FOX structures 25, 25' exposed and the other space between FOX structures 25', 25" covered. The exposed region between FOX structures 25 and 25' is then implanted with a V.sub.t ' ion implant of ions 26 yielding a V.sub.t dose of ions 17 where V.sub.t2 =V.sub.t1 +V.sub.t ', which is greater than V.sub.t1 which is the value for the ions 15 under the second photoresist layer.
The photoresist mask 28 is then removed. Then the conventional process is followed including the polysilicon gate CMOS process, PAD oxide 16 is removed, gate oxidation, polysilicon gate definition, source/drain implant and backend process contact, metallization, passivation, etc. as is well known by those skilled in the art.
FIGS. 4A-4C show cross sectional views of another prior art process of fabrication of another semiconductor device. In FIGS. 4A and 4B, a P-well 12 and an N-well 14 have been formed by a conventional process, whereas in FIG. 4C, the N-well is absent from the view which is of larger scale.
FIG. 4A shows a substrate 10 with an N or P-sub 11, a P-well 12 and an N-well 14 formed by a conventional process and a field oxidation process has been performed leaving FOX structures 25, 25', 25" and 25"'. The structure is covered with gate oxide layer 16 between the FOX structures 25, 25', 25" and 25"'.
In FIG. 4B, a photoresist mask 31 has been formed over the N-well 14 portions of the product of FIG. 4A, and then a field implantation of B11 ions 29 at between about 120 keV and 200 keV is made into the P-well 12 leaving a dose of ions 27 under FOX structures 25, 25' and part of FOX structure 25" and ions 35 between FOX structures 25 and 25' and between structures 25' and 25".
In FIG. 4C, the N-well 14 is absent from the view which is of a larger scale with the thickness retained low for convenience of illustration. The product of FIG. 4C has a V.sub.t1 blanket ion implantation 15 Performed thereon. Next the device in FIG. 4C is covered with a V.sub.'t photoresist 32 on the right side leaving the space between one pair of FOX structures 25 and 25' exposed and the other space between FOX structures 25' and 25" covered. The exposed region is then implanted with a V.sub.t 'ion implant of ions 30 yielding a V.sub.t dose of ions 15 and 17 where V.sub.t =V.sub.t1 +V.sub.t ', which is greater than V.sub.t1 which is the value under the second photoresist layer 32 between FOX structures 25' and 25".
The photoresist mask 32 is then removed, leaving the silicon dioxide gate oxide layer 16 above the region of P-well 12 containing Vt' ions 15 between FOX regions 25' and 25".
The photoresist mask 32 is then removed. Then the conventional process is followed including the polysilicon gate CMOS process, PAD oxide 16 is removed, gate oxidation, polysilicon gate definition, source/drain implant and backend process contact, metallization, passivation, etc. as is well known by those skilled in the art.
USPTO Backgrounds
USPTO Backgrounds