Transistors have been continuously scaled down in size to increase performance and reduce power consumption. This has led to the advent of more efficient, scalable electronic devices and increased user experiences. However, as transistors have decreased in size, the complexity of manufacturing them for optimal performance has increased. One area of challenge faced by manufacturers of transistors is cell layout variability for static random access memory (SRAM). As cell size of SRAM shrinks, variability in design layout becomes limited. Variability is related to effective channel width (Weff) and the effective channel length (Leff) of semiconductor devices. Prior approaches for SRAM cell on finFET includes an orthogonal layout for the SRAM cell, wherein silicon fins are formed at a 90 degree angle relative to the overlying gate. Unfortunately, there is insufficient variability available with the orthogonal design layout
As shown in FIG. 1, a conventional finFET structure with an orthogonal design is illustrated with a gate 101 and a fin 103 extending through the overlying gate in an orthogonal direction relative to the gate 101. The gate has a length (Lg) that is illustrated between directional arrows 111a and 111b. The fin 103 includes source region 105 and drain region 107 and has a fin height (Fin_H) 109a and fin width (Fin_W) 109b. The fin width in this illustration is 10 nanometers (nm) and the fin height is calculated by the device width divided by two. Weff is calculated by the following equation:Weff=2×Fin_H+Fin_W 
A need therefore exists for forming a finFET based design layout that is suitable for implementation of SRAM cells, and for implementation of integrated circuits using finFET architectures with flexible layout features to allow for cell shrinkage, and the resulting device.
USPTO Backgrounds
USPTO Backgrounds