The invention relates generally to video graphics processing and more particularly to a method and apparatus for determining a representative Z values in a video graphics system.
Computers are used in many applications. As computers continue to evolve, the display requirements for computers become more complex and more demanding. In many cases, one of the limiting factors in the speed with which video graphics images can be displayed and updated is related to the speed with which the memory storing the current display frame can be accessed by the render backend block, which updates the images in the frame. Because video graphics primitives generated by the computer system are continuously provided for rendering, which includes blending video graphics primitives with image data currently stored for a particular display frame in a frame buffer, any memory access speed limitations between the render backend block and the frame buffer can have significant adverse effects on overall display system performance.
Because the memory used to store the image data for the frame may be relatively large in terms of die area required on an integrated circuit, the memory maybe constructed as an individual integrated circuit that is coupled to another integrated circuit that includes the video graphics rendering circuitry. This is done to reduce system costs. The interface between these integrated circuits may not be capable of operating at the same speeds that would be possible if the memory structure and the render backend block were included on the same integrated circuit. One solution is to include the render backend block portion of the video graphics processing circuitry on the same integrated circuit as the frame buffer. This can increase the speed with which the render backend block is able to access the frame buffer. Although the pixel fragment data must be relayed from the video graphics processing integrated circuit to that which includes the frame buffer and render backend block over an inter-chip interface, only one transfer is required across this interface per fragment. Because the render backend, block may perform multiple memory accesses in order to incorporate the information included in a pixel fragment into the image data stored in the frame buffer, the efficiency gained by including the render backend block on the same integrated circuit as the frame buffer can be substantial.
However, including the render backend block on the same integrated circuit as the frame buffer can be detrimental to other optimizations designed for reducing the processing requirements for rendering certain data graphics primitives. Including additional circuitry on the integrated circuit that includes the render backend block and the frame buffer can be expensive and complicated as the memory structures used for storing the frame buffer are commonly dynamic random access memory (DRAM) memory structures, and the processes used to manufacture such memory structures make the inclusion of additional circuitry and interconnect expensive. Therefore, any additional circuitry added for supporting optimizations included in other portions of the video graphics pipeline should be implemented using a minimal amount of circuitry and interconnect.
One optimization that can be used in order to reduce the processing operations required for rendering video graphics primitives is to determine representative Z values (where Z represents a depth coordinate in three-dimensional space) for the primitives and comparing these representative Z values with one or more representative Z values for the portions of the image data in the frame buffer. Such comparisons can then be used to determine whether or not certain primitives to be rendered will be visible if they are rendered, thus enabling non-visible primitives to be discarded. As such, a circuit for determining representative Z values for different portions of the frame buffer is desirable. In prior art solutions, this may have been accomplished using complex circuitry included in the render backend block or associated circuitry. Such complex circuitry is not practical if the render backend block is implemented on the same integrated circuit as the frame buffer when the process used to manufacture such an integrated circuit is the type of process associated with manufacturing DRAM memory circuits.
Therefore, a need exists for a method and apparatus for determining representative Z values for various portions of the image data stored in a frame buffer using a limited amount of circuitry and interconnect.
USPTO Backgrounds
USPTO Backgrounds