1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a structure suitable for enhancing an integration degree of the same.
2. Description of the Background Art
FIG. 18 shows the layout of a mask (hereinafter referred to simply as a "mask layout") used for manufacturing a former semiconductor device. FIG. 19 is a cross-sectional view showing a semiconductor device manufactured through use of the mask layout shown in FIG. 18. As shown in FIG. 19, the former semiconductor device comprises a silicon substrate 10, and an n-well 12 and a p-well 14 formed on the silicon substrate 10. In the p-well 14 are formed a first diffusion region 16, a second diffusion region 18, and a p-type high-density region 20.
The first diffusion region 16 corresponds to an n-type semiconductor region used as the source region of a transistor and will be hereinafter referred to as an "n-type source region 16." The second diffusion region 18 corresponds to an n-type semiconductor region used as the drain region of the transistor and will be hereinafter referred to as an "n-type drain region 18." The high-density p-type impurity region 20 corresponds to a p-type semiconductor region containing impurities of the same conductivity type as those contained in the p-well 14 and at a density higher than that in the p-well 14. This region will be hereinafter referred to as a "well contact 20."
An isolation oxide film 22 is formed in the semiconductor device in order to divide the n-well 12 and the p-well 14 into predetermined regions. The well contact 20 is isolated from adjacent regions, i.e., the n-type source region 16 and the n-type drain region 18, by means of the isolation oxide film 22. A channel region is formed from a portion of the p-well 14 between the n-type source region 16 and the n-type drain region 18. A gate oxide film 24 and a gate electrode 26 are formed on top of the channel region 14. A sidewall 28 is formed on the side surface of the gate electrode 26, and a metal silicide (CoSi.sub.2) layer 29 is formed on the respective surfaces of the N-type source region 16, the N-type drain region 18, and the well contact 20.
An interlayer oxide film 30 is formed on the isolation oxide film 22, the gate electrode 26, and the metal silicide layer 29. Contact holes 31 are formed in the interlayer oxide film 30 such that they reach respective areas in the vicinity of the n-type source region 16, in the vicinity of the n-type drain region 18, and in the vicinity of the well contact 20. A barrier metal layer 32 is grown on the surface of the interlayer oxide film 30 and the wall surface of each of the contact holes 31. A first contact plug 34, a second contact plug 36, and a well contact plug 38 are formed inside the individual contact holes 31.
An aluminum wiring layer 40 is formed on the interlayer oxide film 30 so as to become electrically connected to the first contact plug 34 and the well contact plug 38. An aluminum wiring layer 42 is formed on the interlayer oxide film 30 so as to become electrically connected to the second contact plug 36. As shown in FIG. 18, the semiconductor device further comprises a gate contact plug 44 electrically connected to the gate electrode 26. The semiconductor device is connected to an external element by way of the aluminum wiring layers 40 and 42 and the gate contact plug 44.
In FIG. 18, reference symbol DM1 denotes a distance between the edge of the n-type source region 16 and the first contact plug 34 over the mask layout. Similarly, DM2 denotes a distance between the edge of the n-type drain region 18 and the second contact plug 36 over the mask layout; SM1 denotes a distance between the first contact plug 34 and the gate electrode 26 over the mask layout; and SM2 denotes a distance between the second contact plug 36 and the gate electrode 26 over the mask layout.
In the former semiconductor device, the mask layout is determined such that DM1=DM2 and SM1=SM2. As DM1, DM2, SM1, and SM2 assume smaller values, the degree of integration of the semiconductor device is improved. However, if SM1 and SM2 are set so as to assume irrelevantly small values, the contact holes 31 for the first and second contact plugs 34 and 36 are apt to overlap the gate electrode 26. In this case, since a desired structure is not achieved, the characteristics of the transistor elements would deteriorate.
Further, if DM1=DM2 is set so as to assume an irrelevantly small values, the contact hole 31 for the second contact plug 36 is apt to jut out from the n-type drain region 18. If the contact hole 31 is formed so as to jut out from the n-type drain region 18, a portion of the isolation oxide film 22 is lost, thereby rendering the n-type drain region 18 and the p-well 14 more apt to become short-circuited. At the time of operation of the former semiconductor device, a potential differing from that of the p-well 14 flows into the n-type drain region 18. If a short circuit exists between the n-type drain region 18 and the p-well 14, the operating characteristic of the transistor is impaired.
In order to prevent these problems, in the mask layout of the former semiconductor device, the value of SM1=SM2 is determined so as to prevent the contact holes 31 for the first and second contact plugs 34 and 36 from overlapping with the gate electrode 26, and the value of DM1=DM2 is determined so as to prevent the contact holes 31 for the first and second contact plugs 34 and 36 from jutting out from the n-type source region 16 or the n-type drain region 18 without regard to various types of variations in the manufacturing process. Such a mask layout leads to high-yield manufacture of transistors having superior characteristics.
The former semiconductor device described above is used with the n-type source region 16 and the well contact 20 short-circuited, i.e., with the n-type source region 16 and the p-well 14 short-circuited. Therefore, even if the n-type source region 16 and the p-well 14 are short-circuited as a result of jutting of the contact hole 31 for the first contact plug 34 from the n-type source region 16, the operating characteristic of the transistor will not be deteriorated. If the short circuit between the n-type source region 16 and the p-well 14 is allowed, DM1 can be made smaller than DM2, thus enabling an increase in the degree of integration of the transistor. In this respect, the former technique which employs an identical value for DM1 and DM2 unnecessarily limits the degree of integration of the transistor.
USPTO Backgrounds
USPTO Backgrounds