Field of the Invention
The present invention is related to integrated circuits and more particularly to failures in integrated circuits.
Description of the Related Art
In general, the gate oxide of a transistor is subjected to extreme stress during operation, e.g., stresses due to high overshoots and undershoots of a signal applied to the gate of the transistor or stresses due to power supply over-voltages used to boost the performance of the transistor and associated system. As semiconductor manufacturing technology shrinks transistor dimensions, the gate oxide thickness also decreases, causing higher electric fields to be observed by the gate oxide. Those higher electric fields stress gate oxide structures and cause failures of the transistors in time over continuous operation. Therefore, it is desirable to evaluate the failure rates of transistors due to gate oxide degradation in response to high dielectric stresses. Time Dependent Dielectric Breakdown (TDDB) is a conventional methodology that assumes that upon a breakdown of the gate oxide, the transistor undergoes catastrophic breakage and no longer functions. This assumption causes an amount of pessimism in the device reliability calculations and predictions based on that methodology. Accordingly, improved techniques for determining device reliability are desired.
USPTO Backgrounds
USPTO Backgrounds