The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor that include an air-gap spacer and methods for forming a field-effect transistor with an air-gap spacer.
Device structures for a field-effect transistor include a source, a drain, a channel situated between the source and drain, and a gate structure including a gate electrode and a gate dielectric separating the gate electrode from the channel. A gate voltage applied to the gate electrode is used to provide switching that selectively connects the source and drain to each another through the channel. The channel of a metal-oxide-semiconductor field-effect transistor (MOSFET) is located beneath the top surface of the substrate on which the gate structure is supported.
A fin-type field-effect transistor (FinFET) is a type of MOSFET that is capable of being more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a semiconductor fin, a gate electrode that overlaps a channel in the semiconductor fin, and heavily-doped source/drain regions formed in sections of the semiconductor fin peripheral to the gate structure. The channel of a FinFET is effectively elevated above the top surface of the substrate so that the gate structure can wrap about multiple sides of the channel. The wrapped-arrangement between the gate electrode and fin improves control of the channel and reduces the leakage current when the FinFET is in its ‘off’ state. This, in turn, enables the use of lower threshold voltages and results in better performance and power.
Air-gap spacers may be formed adjacent to the sidewalls of the gate electrode of a field-effect transistor in order to reduce the gate-source capacitance, which may lead to a performance boost. The formation of an air-gap spacer may require removal of a dummy spacer material with an etching process. The etch depth may be difficult to control during the performance of the etching process used to remove the dummy spacer material. If the etch depth is too great, then the gate dielectric material may be exposed by the air-gap spacer. If the etch depth is too shallow, then the boost in performance may not be optimized by the formation of the air-gap spacer.
Improved structures for a field-effect transistor and methods for forming a field-effect transistor are needed.
USPTO Backgrounds
USPTO Backgrounds