1. Technical Field
The technology relates to methods and structures for making enhanced-mobility field-effect transistors having sub-50-nanometer channel lengths. More particularly, the technology relates to controlling epitaxial growth in source an drain regions, so as to prevent faceting at undesirable locations.
2. Discussion of Related Art
Transistors are fundamental device elements of modern digital processors and memory devices. Currently, there are a variety of transistor designs or types that may be used for different applications. Various transistor types include, for example, bipolar junction transitors (BJT), junction field-effect transistors (JFET), metal-oxide-semiconductor field-effect transistors (MOSFET), vertical channel or trench field-effect transistors, and superjunction or multi-drain transistors. As is widely known, the size of transistors' active areas continue to reduce with each new generation of micro- and nano-fabricated devices, and this reduction can be characterized according to Moore's law. The reduction in transistor dimensions has presented and continues to pose various fabrication challenges as transistor channel dimensions have reduced below 250 nanometers (nm).
An example of a pFET 100 is depicted in the elevation view of FIG. 1. The pFET may be formed at a small region on a semiconductor substrate, and may comprise a source region 120, a body region 130, and a drain region 140. The source and drain regions may be doped to be of a first conductivity type (P), whereas the body region 130 may be doped to be of a second conductivity type (N). The source and drain regions may be formed by ion implantation and diffusion. Adjacent the body region and at the surface of the substrate may be a gate 110 formed of a conductive material (e.g., a metal, a highly doped semiconductor, polycrystalline or amorphous silicon, etc.). The gate 110 may be electrically insulated from the body, source, and drain regions by a thin insulating layer 105 (e.g., a thin oxide, a thin dielectric). The source, gate and drain may be covered by a passivation layer 115, such as an oxide or hard baked polymer. Holes or vias may be opened in the passivation layer 115 so that conductive contacts 150 can be formed to contact the source, gate, and drain terminals of the FET. Biasing the gate 110 at an appropriate voltage (typically less than or equal to 0 volts for a pFET), draws minority carriers (holes for the pFET) from the body region 130 to form an inversion layer, or channel 102, having a length L below the gate. The channel permits current flow between the source and drain regions. In fabricating a semiconductor chip, up to hundreds of thousands of FETs like that shown in FIG. 1 may be formed on a single chip.
USPTO Backgrounds
USPTO Backgrounds