1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory array for a non-volatile memory device and a method of operating the memory array.
2. Description of the Related Art
Erasable and programmable read only memory (EPROM), electrically erasable and programmable ROM (EEPROM), Flash EEPROM, etc., are non-volatile memory devices, which maintain stored data even when a power supply is stopped.
Recently, non-volatile memory devices using a non-conductor that can locally trap charges have been the subject of publications because they have a simple fabrication process and can procude a more highly integrated memory chip using photolithography-etching compared with conventional non-volatile memory devices using a floating gate. A representative example of non-conductors capable of trapping charges is a silicon nitride layer. Typically, an oxide-nitride-oxide (ONO) layer, in which a silicon nitride layer is sandwiched between two oxide layers, is used as a charge storage layer for the non-volatile memory devices.
A prior art non-volatile memory device using ONO layer is disclosed in U.S. Pat. No. 5,168,334 issued to Alan T. Mitchel et al. FIG. 1A is a schematic sectional view of a non-volatile memory device as disclosed by Alan T. Mitchel in U.S. Pat. No. 5,168,334, and FIG. 1B is an equivalent circuit diagram of FIG. 1A. In FIGS. 1A and 1B, reference numeral 1 represents a substrate, reference numeral 3 represents an ONO layer of oxide-nitride-oxide, reference numeral 5 represents a gate, and reference numeral 7 represents source/drain regions.
Referring to FIGS. 1A and 1B, the non-volatile memory device includes the ONO layer 3 (including an oxide layer 2a, a nitride layer 2b, and another oxide layer 2c) and the gate 5 sequentially stacked on the substrate 1, and is a single bit non-volatile memory device 6 which expresses either logic ‘0’ or logic ‘1’ depending on whether a charge trapped in a nitride layer 2b of the ONO layer 3 exists or not. However, a memory device that can express two or more states to increase the information storage capability without increasing the size of the memory device is desirable.
In actual application, non-volatile memory devices are often used in a large memory array. Since the semiconductor industry requires a high integration of semiconductor devices that can store more information in a smaller-sized package, it is necessary to package many memory cells in a memory array. Further, the memory array should be fabricated as small as possible. For this purpose, Richard M. Fastow et al. discloses a memory array 900 shown in FIG. 2 in U.S. Pat. No. 6,477,083. In the memory array 900, Richard M. Fastow et al. discloses a virtual ground structure which does not use a common source line for all transistors constituting the memory array 900.
Referring to FIG. 2, the virtual ground structure by Richard M. Fastow et al. includes a memory cell array 904, word lines 1001, 1003, 1005, bit lines 802, 804, 806, 810 and selection transistors 840, 842, 846, 848. The bit lines are connected to memory cells in a row direction, and the selection transistors are connected to the bit lines alternatively at an upper portion and a lower portion of the memory array 904. The selection transistors 840 and 842 in odd columns are connected to each other while sharing a drain 828, and the selection transistors 846 and 848 in even columns are connected to each other while sharing the drain 829. In the aforementioned virtual ground structure, source or drain of a selected memory cell is activated (or accessed) by properly biasing the selection transistors.
However, the memory array structure 900 shown in FIG. 2 may cause a neighbor cell effect, which is caused by a non-selected memory cell in a read operation and results in deterioration in the sensing margin. For example, it is assumed that bit information stored in a memory cell 101 is read. For this purpose, when 5 V is applied to the word line, 2.5 V is applied to the bit line 806, and the ground voltage (0 V) is applied to the bit line 802, memory cells 103 and 105, at both sides of the selected memory cell 101, are turned on so that all the memory cells to which the selected memory cell 101 pertains, i.e., all the memory cells in a direction of the selected word line 1003 are basically turned on. Thus a voltage applied to the drain and source of the selected memory cell 101 or an output voltage therefrom may be adversely influenced. Accordingly, a new memory array structure that can secure a reliable operation is required.
To accomplish a high integration that can store more information in a smaller sized package, it is required that the size of memory cells packaged in a memory array should be small so that more information bits can be stored in the same memory cell size.
To this end, a variety of two bits non-volatile memory devices are introduced. For instance, U.S. Pat. No. 5,768,192 assigned to Boaz Eitan et al., U.S. Pat. No. 6,706,599 assigned to Michael Sadd et al., U.S. Pat. No. 6,248,633 assigned to Seiki Ogura et al., or the like disclose two bit non-volatile memory devices.
FIG. 3A is a sectional view schematically showing a memory device disclosed in U.S. Pat. No. 5,768,192 to Boaz Eitan et al., and FIG. 3B is an equivalent circuit diagram of FIG. 3A. In FIGS. 3A and 3B, reference numeral 21 represents a substrate, reference numeral 23 represents an ONO layer, reference numeral 22a represents an oxide layer, reference numeral 22b represents a nitride layer, reference numeral 22c represents an oxide layer, reference numeral 25 represents a gate, and reference numeral 27 represents source/drain regions. Unlike the non-volatile memory device of FIG. 1A, the non-volatile memory device to Boaz Eitan et al., is characterized in that the nitride layer 22b of the ONO layer 23 has two positions of charge trap regions 24L and 24R. Charges are selectively and independently stored in the charge trap regions 24L and 24R of the nitride layer 22b. This non-volatile memory device uses a channel-hot-electron (CHE) to inject electrons into the charge storing nitride layer 22b and injects hot-holes (HH), generated in a band-to-band-tunnel (BTBT) method, into the charge trap region so as to remove the electrons injected into the charge trap regions 24L and 24. This non-volatile memory device injects charges into the charge trap regions 24L and 25R selectively and independently by applying a proper bias voltage to the gate 25, source 27, drain 27, and substrate 21 of the memory device, respectively.
As shown in FIG. 3B, the non-volatile memory device of FIG. 3A can be represented by three transistors 26L, 26C, and 26R having respective channels Ls1, Lc, and Ls2 and connected in series. Threshold voltages of the memory devices, i.e., the memory transistor 26L having the channel Ls1 and the memory transistor 26R having the channel Ls2, are varied depending on the amount of charges injected into the charge trap regions.
Similarly to the memory device of FIG. 1A, this non-volatile memory device is advantageous in that it can have a simple structure with relatively low fabrication costs, thereby allowing an inexpensive memory chip to be realized. However, since one gate 25 has to control the three transistors 26L, 26C, and 26R, an applied operation voltage is severely limited, so that a signal difference, i.e., the sensing margin characteristic, between bit information of the memory device, logic ‘1’ and logic ‘0’, is lowered. In particular, for highly integrated devices, the device size is decreased making the distance between the drain 27 and the source 27 smaller. In other words, the charge trap regions 24L and 24R become adjacent to each other. Since the charges stored in the insulation nitride layer 22b are laterally diffused and gradually moved toward the channel direction of the device, the effective distance between the two charge trap regions 24L and 24R becomes narrower, and at the worst, the two charge trap regions 24L and 24R are physically connected to each other, so that a phenomenon occurs where the two different bit informations cannot be differentiated from each other. This problem is very serious in that it is counterproductive to the scaling down to accomplish low prices and high device density.
FIG. 4A is a sectional view schematically showing the non-volatile memory device disclosed in U.S. Pat. No. 6,706,599 to Michael Sadd et al., and FIG. 4B is an equivalent circuit diagram of FIG. 4A. In FIGS. 4A and 4B, reference numeral 31 represents a substrate, reference numeral 33 represents an ONO layer, reference numeral 32a represents an oxide layer, reference numeral 32b represents a nitride layer, reference numeral 32c represents an oxide layer, reference numeral 35 represents a gate, and reference numeral 37 represents source/drain regions. Unlike the non-volatile memory device of FIG. 3A, the non-volatile memory device of FIG. 4A is characterized by having a nitride layer 32b of the ONO layer 33 that can store charges in physically separated regions. According to this non-volatile memory device, although the device size is decreased, two different charge trap regions 34L and 34R are not electrically connected by a diffusion of charges. Although the structure of FIG. 4A has an advantage in that the device size is further scaled down while maintaining the same operation characteristics as those of the non-volatile memory device of FIG. 3A, this non-volatile memory device still has to control three transistors 36L, 36C, and 36R using one gate 35 like the device of FIG. 3A. Therefore, an applied operation voltage is rigorously limited, so that a signal difference, i.e., the sensing margin characteristic, between bit information of the memory device, logic ‘1’ and logic ‘0’, is lowered.
FIG. 5A is a sectional view schematically showing the memory device disclosed in U.S. Pat. No. 6,248,633 to Seiki Ogura et al., and FIG. 5B is an equivalent circuit diagram of FIG. 5A. In FIGS. 5A and 5B, reference numeral 41 represents a substrate, reference numeral 43 represents an ONO layer, reference numeral 42a represents an oxide layer, reference numeral 42b represents a nitride layer, reference numeral 42c represents an oxide layer, reference numerals 45L and 45R represent a control gate, reference numeral 47 represents source/drain regions, and reference numeral 49 represents a select gate. This non-volatile memory device includes the control gates 45L and 45R, which are disposed at both sidewalls of the select gate 49 and independently controllable, and the ONO layer 43 having charge trap regions 44L and 44R respectively disposed below the control gates 45L and 45R. The select gate 49 between the control gates 45L and 45R is insulated by an oxide layer 42g from the substrate 41 and insulated by an oxide layer 42s from the control gates 45L and 45R. Since the non-volatile memory device can be formed using a process for forming a sidewall of a MOS transistor, it has an advantage that the control gates 45L and 45R are physically formed in a nano-scale size to decrease the overall size of the device. Also, since the independent control gates 45L and 45R are formed in the respective charge trap regions 44L and 44R and the select gate 49 can be separately controlled, optimal voltages can be applied to the respective gates. As a result, a signal difference, i.e., sensing margin characteristic, between bit information of the memory device, logic ‘1’ and logic ‘0’, is enhanced. However, in the prior art non-volatile memory device, the number of gates to be controlled is high, which complicates a peripheral circuit needed to operate and control the devices. Also, since the role of the select gate 49 is not necessarily needed according to the charge injection method (program/erase mechanism), it has an additional structure that may prevent optimal scaling down of the device.
Accordingly, it is desirable to develop a low price, high density, and highly reliable non-volatile memory device.
USPTO Backgrounds
USPTO Backgrounds