1. Field of the Invention
The present invention relates to a high-voltage device process and, more particularly, to a high-voltage device process compatible with a low-voltage device process, in which a gate structure and a P-body are formed within a high-voltage device area and then a gate structure is formed within a low-voltage device area.
2. Description of the Related Art
In current semiconductor processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as VDMOS, IGBT and LDMOS, is employed to increase power switching efficiency and decrease the loss of energy resources. Since the high-voltage device and the low-voltage device with different breakdown voltages are required on a single chip, making the high-voltage device process compatible with the low-voltage device process has become an important issue.
In high-voltage device processing, a P-body is required by an epitaxial layer to achieve a high breakdown voltage. Conventionally, the P-body is formed by a self-alignment P-body process after the gate structures are formed in the high-voltage device area and the low-voltage device area. FIGS. 1A and 1B are sectional diagrams showing the conventional self-alignment P-body process. As shown in FIG. 1A, in a case using a P-type semiconductor silicon substrate 10, a high-voltage device area H and a low-voltage device area L are defined on the substrate 10. Also, an N-type epitaxial layer 12 is formed on the substrate 10, a field oxide layer 14 is formed in the epitaxial layer 12 within the high-voltage device area H, and a P-type well 16 is formed in the epitaxial layer 12 within the low-voltage device area L. In patterning gate structures on the epitaxial layer 12, a gate oxide layer 18, a polysilicon layer 20 and a metal silicide layer 22 are deposited and then etched by photolithography to provide two gate structures within the high-voltage device area H and the low-voltage device area L, respectively.
Next, as shown in FIG. 1B, a self-alignment P-body process with P-type ion implantation and thermal annealing is carried out in the high-voltage device area H to form a P-body 24 in the epitaxial layer 12 in the high-voltage device area H. In order to obtain channel length LD, considerable thermal budget is required to drive the P-type ions to laterally diffuse under the gate structure, resulting in a preferred laterally-extending length. However, the large thermal budget may vary the original distribution of ions and the junction profile within the low-voltage device area L, causing problems related to the threshold voltage, the saturated circuits and the resistance of the well region of the low-voltage device.
The present invention provides a high-voltage device process compatible with a low-voltage device process to solve the problems caused by the prior method.
In the high-voltage device process compatible with a low-voltage device process, a high-voltage device area and a low-voltage device area are defined on an N-type epitaxial layer of P-type semiconductor silicon substrate. Then, an ion implantation modulating threshold voltage is employed on predetermined gate structure areas within the high-voltage device area. Next, a plurality of first gate structures are patterned on the predetermined gate structure areas within the high-voltage device area, in which each first gate structure is stacked by a first gate oxide layer and a first polysilicon layer. Next, a P+-type ion implantation and a thermal annealing are performed on the high-voltage device area to form a P-body in the epitaxial layer between two adjacent first gate structures. Finally, a plurality of second gate structures are formed on the low-voltage device area, in which each second gate structure is stacked by a second gate oxide layer, a second polysilicon layer and a metal silicide layer.
Accordingly, it is a principal object of the invention to provide first gate structure in the high-voltage device area and the second gate structure in the low-voltage device area in different steps.
It is another object of the invention to prevent problems related to the threshold voltage, the saturated circuits and the resistance of the well region of the low-voltage device caused by the thermal budget required by the formation of the P-body.
USPTO Backgrounds
USPTO Backgrounds