The present invention relates to a semiconductor memory system for transmitting data on a board on which a synchronous DRAM (SDRAM) and its controller are mounted, and more particularly to a semiconductor memory system that can realize high-speed synchronization type data transmission with reliability.
Generally, a semiconductor memory is used as a DIMM (Dual Inline Memory Module) when it is mounted in a personal computer, etc. FIG. 1 is a plan view illustrating a general DIMM. On the DIMM, eight or sixteen memory chips 81 are mounted to input or output the data and signals via terminals 82 formed on both sides of a substrate.
A memory-board in a personal computer, etc. generally comprises four sockets and a controller for controlling four DIMMs so that these DIMMs can be mounted on the memory board.
FIG. 2 is a diagram illustrating a concept of the memory board on which a controller 83 and four DIMMs are mounted. The controller 83 transmits four common clocks CLK synchronizing and controlling memory chips on the four DIMMs (DIMM1 to DIMM4) to each of the DIMMs. Each of the DIMMs transmits 64-bit data DQ to the controller 83 via a common data bus.
In the semiconductor memory system comprising the controller and DIMMS, the problem is the timing at which the controller fetches the data from the DIMMs. Since the distances between the controller and the respective DIMMs are different, the flight times of the clock CLK and the data DQ are also different. For this reason, the fetch timing of the data is different, depending on the DIMM to which the controller makes an access.
This situation will be explained by using a timing chart of FIG. 3. FIG. 3 illustrates the access condition of two DIMM1 and DIMM4 shown in FIG. 2. In this case, it is assumed that each of the DIMMs alternately outputs the different data items such as "1", "0", "1", "0", . . . .
As for the controller, a leading clock that is expected to output the data and the following clock are referred to as clocks CLK. In the figure, each arrow indicates the flight time from the leading clock. In order to generate the common data fetch timing in both cases where the controller receives the data from the DIMM1 and where it receives the data from the DIMM4, a strobe signal needs to be generated during periods (data windows) in which oblique lines are drawn in the drawing. However, the data windows vary according to the condition of the board or the mounted condition of the DIMMs, and it may be often impossible to set the data windows common to the DIMMs. The method of determining the timing of the strobe signal for the data fetch, and how the timing of the strobe signal for such a data fetch should be determined and how the system which can correspond to any flight time should be produced, are important for realization of a high-speed memory board system.
USPTO Backgrounds
USPTO Backgrounds