1. Field of Invention
The present invention relates to a manufacturing process for chip package. More particularly, the present invention relates to a manufacturing process for reducing the thickness of chip package.
2. Description of Related Art
In the current information society, users are pursuing electronic products with high speed, high quality and multi-function. As to the product appearance, the trend of the design of electronic products is light, thin, short and small. To achieve the above mentioned purposes, many manufacturers adopt the concept of systemization when designing circuits, with which a single chip can have many functions so as to reduce the number of chips used in an electronic product. Besides, as to the electronic package technology, in order to meet the design trend of being light, thin, short and small, various design concepts of chip package have been developed, e.g. multi-chip module (MCM), chip scale package (CSP) and stacked die package. A few of the traditional stacked die packages are illustrated respectively below.
FIG. 1 is a schematic section drawing of the traditional stacked die package. Referring to FIG. 1, the traditional stacked die package structure 50 includes a circuit substrate 100 and a number of chip packages 200a and 200b which are stacked on the circuit substrate 100 and electrically connected with the circuit substrate 100. Each of the chip packages 200a and 200b includes a package substrate 210, a chip 220, a number of bumps 230, an under fill 240 and a number of solder balls 250. The chip 220 and the bumps 230 are disposed on the package substrate 210 and the bumps 230 are disposed between the chip 220 and the package substrate 210 with which the chip 220 is electrically connected through these bumps. The under fill 240 is disposed between the chip 220 and the package substrate 210 to cover these bumps 230.
The package substrate 210 has a number of conducting poles 212 and a number of bonding pads 214; wherein, these conducting poles 212 run through the package substrate 210 respectively, and these bonding pads 214 are respectively disposed on these conducting poles 212. Besides, the solder balls 250 are disposed on these bonding pads 214. Thus, the chip package 200a and 200b are electrically connected with each other through the solder balls 250, and the chip package 200b is electrically connected to the circuit substrate 100 through the solder balls 250.
Generally, the fabrication of the package substrate 210 is that: using the core as core material, by means of the fully additive process, the semi-additive process, the subtractive process or other process, the patterned circuit layers and the patterned dielectric layers are interleavedly stacked on the core. Consequently, the core takes a relative great proportion of the whole thickness of the package substrate 210. Therefore, if the thickness of the core can not be effectively reduced, it will be very difficult to reduce the thickness of the chip packages 200a and 200b. 
Naturally, if there is a bottleneck in reducing the thickness of the chip packages 200a and 200b, it will be hard for the whole thickness of the stacked die package 50 to be remarkably reduced. Furthermore, it will be impossible to effectively increase the package integration of the stacked die package 50.
USPTO Backgrounds
USPTO Backgrounds