(1) Field of the Invention:
The present invention relates to improvements in field effect transistor (FET) semiconductor devices and methods of manufacturing the devices, more particularly to FET devices having improved performance and high immunity to hot carrier effects.
(2) Description of the Prior Art:
It is well known to provide a spacer element on the vertical sidewall of the gate of an FET device. Such spacer elements are conventionally formed by initially providing a gate insulating film on the surface of a semiconductor device, forming a layer of polycrystalline silicon over the gate insulator film and then patterning the layer and film to form an electrode with vertical sidewalls. An ion implantation is performed using the gate electrode as a mask to form a lightly doped shallow impurity region in the substrate. Subsequently, a compound layer of insulating material, typically SiO.sub.2, is deposited on the surface of the gate electrode and vertical sidewalls, and the surface of the substrate. The conformal SiO.sub.2 layer is then etched by anisotropic reactive ion etching. The SiO.sub.2 layer is removed on the horizontal surface areas of the gate electrode and substrate. However, portions of the layer remain on the vertical sidewalls of the gate electrode acting as spacers. A second deeper ion implantation is then performed, using the gate electrode and sidewall spacer elements as a mask. The ion implantation results in source and drain impurity regions in the substrate. The first impurity regions are joined to the second impurity regions and provide lightly doped shallow regions that extend beneath the spacer elements. The impurity regions are of course suitably annealed to heal the crystalline damage in the substrate caused by the ion implantations. The spacer elements provide a method of forming the lightly doped source and drain regions adjacent the gate electrode. The lightly doped drain (LDD) region reduces the longitudinal peak electric field at the drain end, thereby relieving the hot carrier effects. The conventional LDD structure, however, has the problem of "spacer-induced degradation". The trapped electrons in the oxide spacer induce positive charges in the LDD region, leading to the increase of LDD resistance and the degradation of current driving capability. Several fully overlapped LDD structures have been proposed to solve this problem. With the gate and the LDD region fully overlapped, the positive gate voltage for NMOSFETs induces negative charges in the LDD region and alleviates the spacer-induced degradation. Moreover, the greater vertical electric field in the LDD regions opposes the hot electron injection.
One of the best ways to achieve full overlap between the gate and the LDD is to use a conductive spacer (e.g. doped polysilicon) rather than an oxide spacer. Sub-half micron NMOS transistors with better current driving capability and additional immunity to hot carrier induced degradation have been demonstrated with single polysilicon spacer. However, the devices with single polysilicon spacer still have problems such as incompatibility with the Self-Aligned siliCIDE (SALICIDE) process, suffering of the contact to gate design rule and large gate to drain overlap capacitance C.sub.gd.
This invention overcomes the above problems with double spacers, where the inner spacer is comprised of conductive material (e.g. doped polysilicon) and the outer spacer is comprised of material with low dielectric constant (e.g. SiO.sub.2). The deeper source/drain implant is self-aligned to the outer oxide spacer edge. With the outer oxide spacer, a much thinner polysilicon spacer can be used, thereby reducing the suffering of the contact to gate design rule and the gate to drain overlap capacitance. The above reasoning is based on a published simulation result that the longitudinal electric field peak, corresponding to the location for hot carrier injection, is very localized at the gate edge. Hence, a thin polysilicon spacer is enough to cover most of the area where hot carriers inject into the gate oxide under the spacer. The outer oxide spacer provides another freedom for the LDD length L.sub.n- optimization. Furthermore, the outer oxide spacer makes the new structure compatible with the SALICIDE process and less susceptible to the band-to-band tunneling effect.
Various U.S. Patents have proposed a number of double spacer elements for gate electrodes. U.S. Pat. Nos. 5,108,939 to Manley et al, 5,073,514 to Ito et al, 5,091,763 to Sanchez and Japanese Kokai 2-292833 to Nawata, show various double spacer structures.
USPTO Backgrounds
USPTO Backgrounds