The inventive concepts described herein relate to nonvolatile memory devices and to programming methods performed in the same, and more particularly, to nonvolatile flash memory devices including multi-level cell (MLC) memory cells and to programming methods performed in the same.
FIG. 1 schematically illustrates a memory cell array in which a plurality of nonvolatile memory cells MC <1:9> are coupled at respective intersections of word lines WL <m+1:m−1> and bit lines BL <n+1:n−1>. A multi-level cell (MLC) memory device is characterized by to programming of two (2) or more bits of stored data in each single memory cell. In the case of an N-bit MLC flash memory device (where N is a positive integer), this is accomplished by setting the threshold voltage (e.g., through Fowler-Nordheim tunneling) of each memory cell MC to within one of 2N threshold distributions.
FIG. 2 is a schematic diagram which illustrates an example of programming of a 3-bit MLC flash memory device. Generally, programming of an N-bit MLC memory cell includes a sequence of N programming steps, i.e., one programming step for each bit of the MLC memory cell. Thus, in the case of the 3-bit MLC programming of FIG. 2, a sequence of three (3) programming steps are executed, namely, an least significant bit (LSB) programming, a central significant bit (CSB) programming, and a most significant bit (MSB) programming.
Flash memory devices are partially characterized by being erased before written. This is shown at the top of FIG. 2 in which the initial programmed state of an MLC memory cell is an erase stated E having the lowest threshold voltage (Vth) distribution. In a first LSB programming step, the threshold voltage (Vth) of the MLC memory cell is set to one of the erased state E or a programmed state LP. In a second CSB programming step, the threshold voltage (Vth) of the MLC memory cell is set to one of the erase stated E or a programmed state CP1 (from erased state E), or to one of a programmed state CP2 or CP3 (from programmed state LP). In a third MSB programming step, the threshold voltage (Vth) is set to one of the erased state E or programmed state P1 (from erased state E), or to one of a programmed state P2 or P3 (from programmed state CP1), or to one of a programmed state P4 or P5 (from programmed state CP2), or to one of a programmed state P6 or P7 (from programmed state CP3).
According to an MLC programming method of storing 2-bit data in each cell, each memory cell has one of these states: ‘11’, ‘10’, ‘01’, and ‘00’. A memory cell with the state of ‘11’ is an erased cell and has the lowest threshold voltage. A memory cell with one of the states ‘10’, ‘01’, and ‘00’ is a programmed cell and has a higher threshold voltage than the cell with the state of ‘11’. On the other hand, according to an MLC programming method of storing 3-bit data in each cell, each memory cell has one of these states: ‘111’, ‘110’, ‘101’, ‘100’, ‘011’, ‘010’, ‘001’, and ‘000’. A memory cell with the state of ‘111’ is an erased cell and has the lowest threshold voltage. Memory cells in the other states are programmed cells, and have higher threshold voltages than the cell with the state of ‘111’.
Generally, each bit of the MLC memory cells has a separate page address. For example, in a 2-bit MLC memory cell, the stored LSB bits of the cells of a word line constitute a first page of data, and the stored MSB bits of the cells of the word line constitute a second page of data. Thus, the N-bit MLC memory cells (where N is two or more) connected to a given word line stores N pages of data. In a programming operation, data is programmed in a page-by-page sequence from the LSB to the MSB, i.e., in the order of a first page, a second page, . . . , an (N−1)th page, and an Nth page.
MLC memory devices have been developed in response to the demand for higher integration. However, as is apparent from FIG. 2, the gaps between threshold voltage distributions of the MLC memory cells is reduced as the number of bits (N) increases, which can have a negative impact on read margins. In addition, memory chips are being physically integrated at ever higher densities, which can create problems resulting from a coupling effect between memory cells during programming. For example, referring to the memory cell array of FIG. 1, the programming of memory cell MC5 can alter the threshold voltage distributions of neighboring memory cells MC2 and/or MC8. This also can negatively impact read margins.
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