In many electronic circuits, for example also in smart cards, dedicated voltage regulators generate a stable tension for the system. Load changes in the system exert a strain on the voltage regulator, which, because of the regulator characteristic of e.g. an N-regulator, can cause temporary collapses of the supply voltage. If the voltage collapses too much, an error-free operation of the circuit or the current-fed system is no longer guaranteed.
In intelligent cards (smart cards), e.g. the supply voltage is in addition monitored by sensors, which, in the event the voltage falls outside the permissible range, reset the system.
FIG. 16 shows by way of an example a graphic representation of a voltage collapse of a regulator (voltage regulator) of a chip card (e.g. a smart card) at a load change.
The graphic representation of FIG. 16 is designated in its whole by 1600. A first graphic representation 1610 shows a voltage evolution 1620 over time of a regulator voltage present at an output of a voltage regulator. On an abscissa 1630 is shown the time. An ordinate 1632 describes a voltage at the output of the regulator, thus e.g. at an internal (e.g. internal with respect to the chip card) supply-voltage feed line. A second graphic representation 1650 describes an evolution of a current provided by the regulator. On an abscissa 1680 is, here too, shown the time, while a corresponding abscissa 1682 represents a current provided by the regulator.
Furthermore, the second graphic representation 1650 shows an evolution 1690 of the current. At one moment, the current rises abruptly from an initial value to a final value. Thereupon the voltage present at the output of the regulator drops. The voltage present at the output of the regulator 1620 then rises again with a time constant and approaches the stationary final value.
Under abrupt change of the current should be understood a change of the current that occurs faster than the time constant of the regulator. In other words, a “more abrupt” rise of the current occurs within a period that is shorter than the period in which the regulator can readjust according to the load change. A rise of the current can however also already be considered as abrupt when the rise occurs faster than during the time constant occurring at the restoring of the output voltage originally present at the regulator.
The time constant for the drop of the output voltage present at the regulator or for the rise of the output voltage present at the regulator can be defined e.g. in that within the time constant the deviation from the minimum value (at a drop of the output voltage) or the stationary final value (at a rise of the output voltage) decreases to 1/e times the initially present deviation.
From the graphic representations 610, 650 in FIG. 16, one can thus see that the regulator voltage at the output of the regulator collapses at the load change, starting from an initial stationary value. The collapse occurs with a first time constant of the regulator, and the recovery of the regulator voltage to the stationary value occurs with a second time constant.
According to the state of the art, the collapse of the supply voltage at a load change shown in FIG. 16 is monitored only by means of special sensors. When the voltage drops below the minimum permissible supply voltage, the sensors suppress the system clock pulses of a switching arrangement fed by the regulator until the supply voltage has recovered through automatic readjusting of the regulator. The described mechanism however necessitates some clock pulses (system clock pulses) until it becomes operative, since it is an integrative mechanism. A certain period or number of system clock pulses is namely necessitated to observe the supply voltage or synchronize clock-pulse suppression.
The described mechanism is in addition inoperative for power consumers that do not permit suppressing clock pulses.
Thus, it should be noted that according to the state of the art a reaction to a load change only occurs when a collapse of the supply voltage present at the output of the regulator below a predetermined threshold value is identified. It has proven that according to the state of the art voltage collapses cannot be optimally minimized. According to the state of the art, the threshold value could of course be increased, however, as a result system clock pulses would then more often—also unnecessarily—be suppressed, whereby the system performance would drop.
USPTO Backgrounds
USPTO Backgrounds