Digital-to-analog converters (DACs) are implemented in many electronic devices. The process of outputting an analog signal that corresponds to a digital input relies on imperfect components. Accordingly, DAC design often accounts for such imperfections. As an example, oversampling and Dynamic Element Matching (DEM) are two techniques that may be used improve DAC performance. DEM refers to selecting different DAC elements to represent a given digital code at different times, thereby translating element mismatches (DC error) into a wideband high-pass-shaped noise. The shaped mismatch noise which resides at high frequency can then be filtered out. Data-weighted averaging (DWA) is a practical DEM technique albeit still imperfect. In DWA, DAC elements participating in digital-to-analog conversion are sequentially selected from a DAC array, beginning with the next available unused DAC element. Several variations of DWA have been developed such as dithered DWA, incremental DWA (IDWA), bi-directional DWA (Bi-DWA), partitioned DWA (P-DWA), rotated DWA (RDWA), randomized DWA (RnDWA), and pseudo DWA. Although DWA techniques are effective for overcoming issues such as DAC element mismatches, existing DWA techniques do not overcome flicker noise in DAC elements. As transistor processes (e.g., complementary metal-oxide semiconductor (CMOS) processes) for DACs are reduced in size, flicker noise in DAC elements increases.
USPTO Backgrounds
USPTO Backgrounds