Aspects of the present invention relate generally to the field of circuit design and test, and more specifically to static timing analysis and simulation of electronics.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the elements and devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are often performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis where the signals between components are analyzed and tested, for example using static timing analysis (STA) or gate level simulation (GLS). STA is used to model the expected timing of a digital circuit by estimating the expected delay within the circuit, via the anticipated worst case signal path for example, without requiring a lengthy and cost prohibitive full simulation of the circuit.
In order to identify the timing of a path through the circuit, a timing model for various circuit stages may be created. Such models typically include an estimate of the effects of multiple neighboring nets (aka aggressor nets) on the modeled net (aka victim net). However, in complex circuit designs having small, densely packed elements, the number of neighboring nets that may interfere with the victim net is often very large. To effectively model such designs, conventionally either the effect of each individual aggressor net is modeled, which is often very costly, or the effect of multiple aggressor nets are estimated together as a single aggressor, which is quicker but less accurate.
Accordingly, there is a need in the art to efficiently develop aggressor models for complex designs while maintaining accurate timing results.
USPTO Backgrounds
USPTO Backgrounds