Most digital memory circuits are “single port” memory devices that can only be read from or written to by a single user at a time. For example, the well-known standard six-transistor (6T) SRAM bit cell only has a single port into the bit cell for reading or writing data bit values. However, for many applications it is desirable to have “multi-port” memory systems where more than one memory user can read from single memory cell at the same time. For example, in a multi-core processor system it is advantageous to allow multiple cores to read from the same memory address concurrently.
To allow for more than one memory reader to concurrently access a single memory bit cell, the circuit design of the memory bit cell may be altered to include more physical ports into the memory bit cell. For example, the standard single-port 6T SRAM bit cell may be made into a dual-port memory cell by inserting two additional transistors into the memory bit cell circuit that implement a second physical port for accessing the data bit stored in the memory bit cell. Such dual-port 8T SRAM bit cells are often used when a digital system needs the ability to perform two concurrent memory accesses.
Adding two additional transistors into a memory cell allows for two concurrent readers of the memory cell but reduces other important metrics of the memory bit cell. Specifically, inserting two additional transistors increases the size of the memory bit cell and thus reduces the memory density of an array created from the 8T SRAM cells. Furthermore, due to the risk of losing the value of the data bit currently stored in the SRAM bit cell if two concurrent read operations are received, certain transistors in the dual-port 8T SRAM bit cell must be made much larger thus further increasing the size of the dual-port 8T SRAM bit cell and reducing memory density. Adding additional ports (such as a third or fourth port) by adding even more transistors further compounds these problems. Thus, as a result, multi-port memory bit cells tend to have very low memory density metrics. The additional transistors will also require additional power to operate such that multi-port memory systems will also consume more power than single port memory systems. Therefore, it would be desirable to have alternative circuit designs for implementing multi-port memory cells.
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