1. Field of the Invention
The present invention relates to a system for converting header information included in a packet for transmitting information, and in particular to a converting function of header information included in an ATM cell for use with an ATM switch system.
2. Description of the Related Art
In recent years, a service that integrally handles a variety of communications including picture data requiring a high transmission speed in addition to audio data and text data has become essential. The core technology of such a service is the ATM (Asynchronous Transmission Mode).
In the ATM, a data transmission unit having a payload composed of 48 octets of information (a fixed length) and control information (such as address information) composed of 5 octets, is used. The control information is referred to as a header.
FIGS. 1A and 1B are schematic diagrams showing the structures of formats of ATM cells. ATM cells have two different formats that are defined in a UNI (User-Network Interface) and in an NNI (Network--Network Interface). The UNI is an interface point between a subscriber and an ATM switch system. The NNI is an interface point between ATM switch systems or between stations.
FIG. 1A shows the format of an ATM cell in the UNI. Referring to FIG. 1A, the first four bits of the header is an area for storing a GFC (General Flow Control) used to prevent cells from colliding in the UNI. The GFC is followed by an 8-bit VPI (Virtual Path Identifier), followed by a 16-bit VCI (Virtual Channel Identifier), followed by a PTI (Payload Type Identifier), followed by an HEC (Header Error Control), and followed by a payload. FIG. 1B shows the format of an ATM cell in the NNI. Referring to FIG. 1B, the format of an ATM cell in the NNI format is the same as that in the UNI format except that the GFC is not provided and the number of bits of the VPI is 12.
The VPI is data for use in identifying a virtual path while the VCI is data for use in identifying a virtual channel. The identification information VPI/VCI is referred to as routing information.
FIG. 2 is a schematic diagram showing a construction of an ATM switch system. The switch system comprises virtual channel conversion units (VCC) on the input and output sides of the switch. That is, the VPI/VCI stored in the header of the input cell (input VPI/VCI) is converted into a VPI/VCI for use in the switch (internal VPI/VCI) on the input side of the switch. The internal VPI/VCI stored in the header of the cell output from the switch is converted into the VPI/VCI for use in outputting the cell (output VPI/VCI) on the output side of the switch. The method of using an internal VPI/VCI in a switch is adopted as a method of performing a high-speed process in a switch system.
Input line interface units 101-1 to 101-3 accommodate subscriber lines and lines to other switches. On subscriber lines, ATM cells in the format shown in FIG. 1A are transmitted corresponding to the UNI. On lines between switch systems, ATM cells in the format shown in FIG. 1B are transmitted corresponding to the NNI. Each of the input line interface units 101-1 to 101-3 performs such as a header converting process (converting the input VPI/VCI into an internal VPI/VCI for a cell that is input through such lines and sends the resultant cell to an ATM switch 102.
Each of the input line interface units 101-1 to 101-3 accommodates a plurality of input lines and has VCCs (Virtual Channel Conversion units) for individual input lines. Each VCC in the input line interface units 101-1-101-3 retrieves the internal VPI/VCI as the header information in the ATM switch 102 as an input VPI/VCI, and rewrites the input VPI/VCI into an internal VPI/VCI. In other words, header information of each of cells that are input to the ATM switch is converted by a particular VCC. The resultant cell is sent to the ATM switch 102.
The ATM switch 102 is a self-routing switch. The hardware of the ATM switch 102 autonomously switches and sends an input cell to one of output line interface units 103-1 to 103-3 corresponding to the header information of the input cell.
Each of the output line interface units 103-1 to 103-3 accommodates an output line assigned a VCC. The VCC converts the internal VPI/VCI stored in the header of the cell output from the ATM switch 102 into an output VPI/VCI and outputs it to an output line.
Thus, the header information about the cell input to the ATM switch is converted by the input line interface units 101-1-101-3 and the output line interface units 103-1-103-3, and the cell is output to the output line identified by the VPI/VCI.
FIG. 3A is a block diagram showing a construction of an input line interface unit 101. The input line interface unit 101 has a discrete portion 110 and a common portion 120. The discrete portion 110 accommodates a plurality of input lines #0 to #3. The common portion 120 performs a converting process for the header information and a multiplexing process. The discrete portion 110 has line terminating units 111 (#0 to #3) for individual input lines. The common portion 120 is duplicated as a common portion 121 of system 0 and a common portion 122 of system 1, so as to allow the switch system to perform processes run even if a defect occurs or maintenance of the switch system is performed. The common portion 121 of system 0 has VCC 123 (#0 to #3) corresponding to the line terminating units 111 (#0 to #3) of the discrete portion 110. For example, when a cell is input through the line terminating unit 111 (#0), the header information of the cell is converted by the VCC 123 (#0) and output to the ATM switch 102. The construction of the common portion 122 of system 1 is the same as that of the common portion 121 of system 0. These common portions 121 and 122 execute their processes in parallel. One of the output signals from the common portions 121 and 122 is sent to the ATM switch 102.
FIG. 3B shows the configuration of the output line interface unit 103. The output line interface unit 103 comprises VCC 151 (#0-#3) for each output line. Each output line is terminated by a line terminating unit 152 (#0-#3). The VCC 151 (#0-#3) is not shown in the attached drawings, but is also a duplex system as with the VCC 123 (#0-#3).
FIG. 4A is a block diagram showing a construction of the VCC 123. The construction of a VCC 123 is the same as that for each of #0 to #3. The VCC 123 has a conversion controlling unit CNV 130 (that controls a converting process of header information) and a VPI/VCI conversion table VCT 140 (hereinafter referred to as conversion table) that stores data used in the converting process. When a cell is input to the VCC 123, an input header analyzing unit 131 in the conversion controlling unit 130 analyzes the header information of the input cell. A table access controlling unit 132 accesses a memory 141 in a conversion table 140 corresponding to an address generated corresponding to the analyzed header information. That is, the header information (internal VPI/VCI) is read from the conversion table 140 using the input VPI/VCI stored in the header of the input cell as an address. The resultant output header information is sent to a header converting unit 134. Further, the input cell is delayed by a delaying circuit 133 with a predetermined time period and then sent to the header converting unit 134. The header information of the input cell is converted into output header information read from the conversion table 140 by the header converting unit 134. The contents of the conversion table 140 are rewritten by a control system of the ATM switch system (CPR).
FIG. 4B shows the configuration of the VCC 151. The configuration of the VCC 151 is fundamentally the same as that of the VCC 123. However, the conversion table in the VCC 151 stores the output VPI/VCI, that is, the routing information, for use in outputting a cell to an output line using as an address the internal VPI/VCI stored in the header of the cell output from the ATM switch 102.
Thus, in the conventional ATM switch system, the VCCs are disposed for individual input lines in a VCC distributed construction.
However, the construction in which VCCs are distributed has the following problems. Described below is the operations performed on the input side of the ATM switch 102. The problems are the same on the output side.
(1) Low use efficiency of hardware
As described above, when VCCs are disposed for individual input lines, the number of conversion controlling units 130 and conversion tables 140 should be correspondingly increased. With the configuration, although the circuit size of the conversion controlling unit 130 can be comparatively reduced, the circuit scale of the conversion table 140 tends to increase. In other words, as shown in FIG. 1A, the bit lengths of the VPI/VCI in the UNI (User-Network Interface) are, for example, 8 bits and 16 bits, respectively. Thus, if header information (internal VPI/VCI) is assigned to all input VPIs/VCIs for conversion, the number of combinations becomes 2.sup.8 .times.2.sup.16 =2.sup.24 =16,777,216. Further, as shown in FIG. 1B, the bit lengths of VPI/VCI in the NNI (Network--Network Interface) are, for example, 12 bits and 12 bits, respectively. Thus, if output header information is designated to all input VPIs/VCIs, the number of combinations becomes 2.sup.12 .times.2.sup.16 =2.sup.28 =268,435,456.
To store such a huge amount of output header Information, a very large table (memory) is required. Consequently, it is not practical to dispose such tables for individual input lines. In reality, the numbers of VPIs/VCIs communicated at the same time are calculated by a simulation or the like corresponding to the average use ratios of the input lines or the like. The size (memory capacity) of each of the conversion tables is determined corresponding to the calculation results. The resultant tables of the calculated size (memory capacities) are disposed for the individual input lines.
However, in the ATM switch system, a situation in which the use ratio of a particular line becomes high may take place. For example, if a defect takes place on a line connected between certain stations, cells sent through the line are routed to another line. Thus, the use ratio of the routing line increases. When the use ratio of a particular line increases, the numbers of VPIs/VCIs communicated on the line at the same time increases. Thus, it is necessary to provide a conversion table with sufficient free space for storing the header information necessary for converting all VPIs/VCIs. Since the variation of the line use ratio may take place on any line, to securely convert headers on all lines, the conversion tables of all the lines should have sufficient free space.
However, since the use ratio of each line is around the average use ratio, if the conversion tables of all the lines have free space, non-use areas of the memories of the conversion tables increase and thereby the use efficiency thereof deteriorates. In other words, since the memories of the conversion tables have unnecessary storage capacities, the hardware size corresponding to individual lines increases and the cost of the entire switch system rises.
(2) Low adaptivity for duplicate construction
As described above, in the input line interface unit 101 with the VCCs, to prevent the switching service from stopping due to a hardware defect or the like, the common portion 120 is duplicated as shown in FIG. 3. In addition, the header converting process for a cell is performed by the VCC 123 of the input line interface unit 101. However, if a defect takes place in the header conversion, since a cell may be incorrectly switched or discarded, the service will be seriously affected. To prevent such a problem, the common portion 120 is duplicated. In other words, the construction of the common portion 122 of system 1 is the same as that of the common portion 121 of system 0. Each of the common portion 122 of system 1 and the common portion 121 of system 0 has VCC 123 (#0 to #3) corresponding to the input lines #0 to #3. One of the common portion 121 of system 0 and the common portion 122 of system 1 should be operated in an active state and the other should be operated in a standby state.
To immediately switch one system with a defect to the other system, it is necessary to cause the common portion 121 of system 0 to operate in the same manner as the common portion 122 of system 1. In other words, the VCC 123 (#0 to #3) of the common portion 121 of system 0 should perform the same header converting processes as the relevant VCC 123 (#0 to #3) of the common portion 122 of system 1. For example, the state of the VCC 123 (#0) of the common portion 121 of system 0 should be the same as the state of the VCC 123 (#0) of the common portion 122 of system 1. In reality, the contents of the conversion tables of the VCC 123 (#0 to #3) of the common portion 121 of system 0 should accord with those of the common portion 122 of system 1. In other words, the relation of the input VPI/VCI and the internal VPI/VCI stored in the conversion tables of system 0 should accord with that of the system 1. The same designations are performed for the conversion tables of the systems 0 and 1 by the software of the controlling unit of the switch system.
If a defect takes place in the VCC 123 (#0) of the common portion 121 of system 0 in the duplicated input line interface unit 101, the common portion 121 of system 0 is placed in the out-of-service state. In this case, the hardware of the common portion 121 of system 0 should be repaired or replaced and the common portion 120 should be re-duplicated so as to place the common portion 121 of system 0 in the in-service state. In this case, the contents of the VCCs of the common portion 122 of system 1 should be designated to the VCCs of the common portion 121 of system 0. The process for designating the contents of VCCs of one common portion to the contents of VCCs of the other common portion, and placing the other common portion in the in-service state, is referred to as a VCC copy process.
As a method for accomplishing the VCC copy process, the software of the controlling unit of the switch system (processed by a control processor CPR that manages and controls the entire switch system) performs the designations for the VCCs of the common port on 122 of system 1 to the VCCs of the common portion 121 of system 0. In this method, it is not necessary to dispose special hardware for performing the VCC copy process. However, since all processes are performed by the software of the controlling unit of the switch system, when the number of input lines accommodated by the switch system increases, the load on the control system proportionally increases. In other words, since the controlling unit of the switch system performs the VCC copy process, its resources are correspondingly used, and thereby the capacity of the switching process is proportionally decreased. Thus, a system for performing the VCC copy process in a short time and with a decrease in processes of the controlling unit of the switch system is desired.
To satisfy such requirements, as shown in FIG. 5, a system in which a common portion 120 of an input line interface unit 101 has hardware with a mutual connection bus for allowing the VCC copy process to be performed between VCCs of both the systems, has been accomplished. The construction of the mutual connection bus is disposed for each of VCCs (namely, VCC #0, VCC #1, VCC #2, and VCC #3). However, the hardware scale of the construction of the mutual connection bus is generally large. In addition, a processor that performs the VCC copy process and firmware thereof are required. Thus, in the construction in which VCCs are disposed for individual lines, when the number of lines accommodated in the switch system increases, the number of VCCs proportionally increases. Consequently, the hardware scale necessary for the VCC copy process increases and the cost thereof rises.
Thus, in the VCC distributed construction in which VCCs are disposed for individual lines, the use efficiency of hardware (in particular, the memories disposed in the VCCs) is low. In addition, the construction in which the processes of the controlling unit of the switch system are reduced and the VCC copy process is performed at a low cost, cannot be accomplished.
USPTO Backgrounds
USPTO Backgrounds