A data storage subsystem having a cache memory can serve as a buffer for frequently accessed data between a host computer system and back-end data storage, such as disk drive arrays or non-volatile (e.g., flash) memory arrays. A data storage subsystem having a cache memory may be, for example, in the form of an accelerator card that promotes low data access latency between the host and the back-end data storage. A caching system may determine the frequency with which data stored in the cache memory is accessed, and maintain only the most frequently accessed data in the cache memory while evicting the least frequently accessed data.
In a caching system, it is desirable to minimize latency, which is the amount of time between receiving a request from the host to write or read data and completing the write or read operation. A property that impacts latency is the look-up time required for the caching system to translate the logical addresses identified by the host into the physical storage locations in the cache memory and the time required for the caching system to subsequently transfer data to or from those storage locations.
A common type of caching is known as “write back,” in which data received from the host in a write request is first stored in the cache memory and made available for the host to read, and then later copied to back-end storage when conditions facilitate the copy operation having less impact on latency. Data that is stored in cache memory but which has not yet been copied to back-end storage is commonly referred to as “dirty” data. A drawback of write-back caching is that dirty data may be vulnerable to loss due to system failures, such as power interruptions. Similarly, data loss can result from such failures interrupting the process of storing data in the cache memory, which can undesirably result in a sequence of storage locations containing a portion of the data associated with a first write request and a portion of the data associated with a subsequent write request.
A caching system may be direct-mapped, fully associative, or a hybrid of such types. In a direct-mapped caching system, the logical address of a data block is mapped to only one address or physical location in the cache memory at which the data block can be stored. For example, the physical address may be computed by modular arithmetic: cache address=logical address MOD(number of addresses in cache memory). In contrast, in a fully associative caching system, a cache block can be stored in any physical memory location in the cache memory. A fully associative caching system generally benefits memory usage efficiency and hit rate. However, a drawback of a fully associative caching system is that the look-up process for translating the logical addresses identified into the physical storage locations in the cache memory can be slow and thus impact latency.
USPTO Backgrounds
USPTO Backgrounds