1. Field of the Invention
The invention concerns microcomputers made in the form of integrated circuit chips and, more particularly in such microcomputers, it concerns a system of tests that are performed on the chip.
2. Description of the Prior Art
As can be seen in FIG. 1, a computer comprises mainly: a central processing unit or processor 10 that performs arithmetic or logic operations on numbers; at least one memory 11 containing the numbers on which and through which said operations are performed; peripheral elements 12, such as a keyboard, printer and additional memory, which are used for entering the information to be processed and the operations to be performed, and for collecting the results of the operations performed; and transmission devices 13 and 14, called buses, which enable the different elements 10, 11 and 12 to communicate with one another. The central processing unit or processor 10 includes a register 15, called instruction register, that receives from the bus 13 the numbers or operation codes indicating the elementary operations to be performed, an operator device 17 that performs the elementary operations, and a device 16 to control said operations, that converts the codes of the elementary instructions into signals for controlling the device 17.
Of the transmission devices or buses 13 or 14, the device 13 (the data bus) is assigned the task of bidirectional transmission of data or operands on which the operations indicated by the operation codes in the register 15 are performed, while the other bus, 14, is assigned the task of one-directional transmission of the addressing codes of the memory 11 and of the peripheral elements 12. The operands are given by the memory and the operator device 17, while the addressing codes are generated by the operator device 17.
To perform an information processing operation, the processor carries out a sequence of operations, the operation codes or instructions of which are contained in the memory 11: these instructions as a whole constitute a program.
In present-day computers, the processor is made in the form of circuits that are integrated into a small-sized silicon substrate called a chip. At the end of the production line for the manufacture of these chips, the processors, also called microprocessors, have to be checked tested so that faulty components are detected and discarded.
Generally, the testing of a microprocessor consists, first of all, in generating input signals and ascertaining that the output signals conform to those expected in normal operation. There are many ways of carrying out such a test. In one of them, the microprocessor is connected to a testing machine which gives the input signals and compares the output signals with those that correspond to normal operation.
In another method, the testing is done by the microprocessor itself through the incorporation of specific elements on the substrate of the chip itself. The purpose of these specific elements is, firstly, to generate input signals and, secondly, to check the output signals. The input signals are obtained by a read-only memory (ROM). The output signals are checked by a polynomial divider or counter which gives a code at the end of the execution of the test program. This code is compared with the one that should have been obtained in the event of faultless operation, the latter reference code being recorded in the read-only memory.
This type of test, called an integrated test, has the following drawbacks. First of all, the performance of a complete test entails the use of a memory with a relatively high capacity, which is used solely by the test. This memory uses a non-negligible portion, either of the chip surface area when the memory is a single one, or of the program memory when this memory is integrated into a chip.
Then, this type of test entails the assumption that the processor is capable of reading the operation codes and the operands in the memory and that this memory is faultless. This factor, in the event of a fault at this level, leads to a divergence in the test sequence from the very start, and this divergence is not due to the failure of the processor.
Finally, a large number of operation codes do not entail any modification in the states of the data and address buses, but modify the content of the internal registers of the operator device 17 or of the so-called "status" bits. For a reliable test, the program associated with these operation codes should be designed to ascertain, by comparison and connection instructions, that the instruction has been carried out accurately within the operator device 17. This entails a correlative increase in the size of the read-only memory.
USPTO Backgrounds
USPTO Backgrounds