1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device comprising a substrate formed from organic material, as well as to a method of manufacturing the semiconductor device.
2. Description of Related Art
FIG. 8 is a cross-sectional view showing a conventional semiconductor layer. In FIG. 8, reference numeral 17 designates a ceramic substrate formed from ceramic material; 2 designates a semiconductor chip connected to the ceramic substrate 17 via bumps 3 by means of flip-chip solder bonding; 4 designates an underfill resin to be used for filling a gap between the semiconductor chip 2 and the ceramic substrate 17; 12 designates a chip capacitor fabricated on the ceramic substrate 17 for reducing switching noise; and 9 designates a solder ball formed on the undersurface of the ceramic substrate 17.
As shown in FIG. 8, in the case of a conventional semiconductor device to be used in an application where special demand exists for high electrical performance, the length of an electrical connection is shortened by interconnecting, for example, a ball-grid array (BGA) substrate (i.e., the ceramic substrate 17) formed from ceramic material and the semiconductor chip 2, via the bumps 3. The coefficient of thermal expansion of the semiconductor device formed from ceramic material differs from that of a system board formed from organic material. In order to ensure packaging reliability, use of a BGA package is limited to solely an area where there is to be fabricated a device having a small outer dimension; i.e., an area where there is to be fabricated a device having a small number of terminals. For this reason, a pin-grid array (PGA) package is employed for an area where there is to be fabricated a device having a large outer dimension; i.e., an area where there is to be fabricated a device having a large number of terminals. Accordingly, sockets to be used for connection of a semiconductor device must be provided on both the semiconductor device and the system board, respectively, thus incurring excessive cost.
FIG. 9 is an electrical model showing the chip capacitor shown in FIG. 8. In FIG. 9, those elements assigned the same reference numerals as those provided in FIG. 8 have the same features, and hence repetition of their explanations is omitted here for brevity. In FIG. 9, reference numeral 13a designates a power supply plane embedded in the ceramic substrate 17, which is multilayered; 13b designates a ground plane embedded in the ceramic substrate 17; and 18 designates inductance of wiring patterns.
In association with an increase in a signal processing rate of an electronic device, switching noise has conventionally presented a problem. As shown in FIG. 9, a conventional semiconductor device employs a multilayered substrate comprising 10 or more layers and achieves high performance by means of building up the power supply plane 13a and the ground plane 13b (hereinafter referred to collectively as xe2x80x9cpower/ground planes 13xe2x80x9d). In order to greatly improve the characteristics of the power/ground planes 13, a chip capacitor 12 of high capacitance is disposed on the ceramic substrate 17 as a noise absorption capacitor for absorbing switching noise.
If the chip capacitor 12 and the semiconductor chip 2 are disposed side-by-side, an interconnection used for connecting the semiconductor chip 2 and the chip capacitor 12 becomes excessively long, thus resulting in an increase in the inductance of a wiring pattern. Thus, even when the low-inductance chip capacitor 12 is employed for realizing high performance by virtue of reduction of switching noise, the chip capacitor 12 cannot make full use of its high performance. Moreover, the chip capacitor 12 itself is expensive.
The present invention has been conceived to solve the problems involved in the background art, and the object of the present invention is to provide a semiconductor device which ensures high packaging reliability and can be embodied inexpensively even when the device has a large number of terminals, as well as to provide a method of manufacturing the semiconductor device.
Another object of the present invention is to provide a semiconductor device which maintain high power/ground plane characteristics and can be embodied inexpensively even when the device has a large number of terminals, as well as to provide a method of manufacturing the semiconductor device.
According to a first aspect of the present invention, there is provided a semiconductor device comprising: an organic substrate formed from organic material; a package section formed by stacking a plurality of the organic substrates; stacked vias formed by directly joining together connection holes formed in respective the organic substrates stacked in the package section, in the stacking direction of the organic substrates; and a semiconductor chip having bumps bonded to the organic substrate forming the upper surface of the package section and formed at a predetermined pitch, wherein the stacked vias are formed at the same pitch as that at which the bumps are formed on the semiconductor chip.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a package section by stacking a plurality of organic substrates formed from organic material; forming stacked vias by directly joining together connection holes formed in the respective organic substrates stacked in the package section, in the stacking direction of the organic substrates; and bonding a semiconductor chip having bumps formed at a predetermined pitch on the organic substrate forming the upper surface of the package section, wherein the stacked vias are formed at the same pitch as that at which the bumps are formed on the semiconductor chip.
The above and other objects, effects, features and advantages of the present invention will become more apparent from the following description of the embodiments thereof taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds