1. Field of the Invention
The invention relates to three-dimensional circuits and more particularly to the formation of three-dimensional circuits.
2. Background
Commonly-owned U.S. Pat. No. 6,034,882, titled xe2x80x9cVertically Stacked Field Programmable Nonvolatile Memory and Method of Fabricationxe2x80x9d describes, in one aspect, a three-dimensional memory circuit array such as a field programmable, nonvolatile memory array, wherein memory cells are fabricated in a vertical arrangement over rather than in a surface of a planar substrate. The substrate may be, for example, a semiconductor substrate, with decoders and input/output (I/O) circuitry formed either in the substrate or in thin film transistors above the substrate. The memory array is stacked vertically in numerous layers to form a cell level. A three-dimensional memory array may have one or more levels of memory cells in the form of pillars separated by signal lines (e.g., word and bit lines) and a level may interact with adjacent levels. The memory array is fabricated sequentially, i.e., level by level. The cell material at a level may consist of a single layer or a plurality of layers. Included in that description is a cell material of a steering element and a state change element connected in series. The steering element generally enhances the flow in one direction while the state change element retains a programmed state.
U.S. Pat. No. 5,835,396 issued to Zhang also describes a three dimensional arrangement of memory elements. In that patent, memory elements are stacked over a substrate with separate metallic select lines addressing memory cells of a level and an interlevel insulating layer covering the select lines between levels. Depending upon the application (e.g., MPROM, EPROM), the memory elements consist of quasi-conduction material of, for example, doped amorphous silicon and metal oxides.
U.S. Pat. No. 4,646,266 issued to Ovshinsky et al. describes a device having programmable cells formed over an insulating substrate in a three dimensional array between orthogonally-configured metal address lines. In one example, the cells are formed sequentially of separate layers of amorphous silicon in a back-to-back PIN diode configuration.
In three dimensional circuits, consistent performance between the individual circuits at different levels is generally desired. Heretofore, the contribution of the thermal budget associated with the fabrication of a three dimensional circuit has not been reported. What is needed are techniques for managing the thermal budget in multiple level arrays.
This invention is directed to postponing at least some thermal processing operations, as multiple levels of a three dimensional circuit are formed.
Additional features, embodiments, and benefits will be evident in view of the figures and detailed description presented herein.
USPTO Backgrounds
USPTO Backgrounds