This invention relates to a fabrication technology for a semiconductor device and, more particularly, to a process for fabricating a semiconductor device having via holes.
A large number of circuit components are fabricated on a single semiconductor chip, to form an integrated circuit device. The integrated circuit has become more complicated, and, accordingly, the circuit components have been increased. However, it is not desirable to enlarge the size of the semiconductor chip. For this reason, the manufacturer miniaturizes the circuit components of the integrated circuit. A multi-layered wiring structure is required for the integrated circuit, and the conductive lines on different levels are connected through via-holes. The via-holes have been also miniaturized. A multi-layered wiring structure for an ultra large scale integration includes via-holes, the aspect ratio of which may be equal to or greater than 1.
Conductive lines on an upper-level are usually formed of aluminum or aluminum alloy. The aluminum/aluminum alloy is deposited by using a sputtering process, and the aluminum/aluminum alloy layer is patterned into conductive lines through a photo-lithography and an etching step. While the aluminum/aluminum alloy target is being sputtered, the aluminum/aluminum alloy fills the via-holes, and swells into the aluminum/aluminum alloy layer over the inter-level insulating layer However, the aluminum/aluminum alloy hardly forms a smooth upper surface around the via-holes with the aspect ratio of not less than 1, and thus the step-coverage is poor. The poor step-coverage results in a low reliability of the upper-level conductive lines.
A multiple-step high-temperature sputtering technology is proposed for improving the step coverage in Japanese Patent Publication of Unexamined Application No. 64-76736. FIGS. 1A to 1H illustrate the prior art multiple-step high-temperature sputtering technology disclosed in the Japanese Patent Publication of Unexamined Application.
Circuit components are fabricated on a silicon substrate (not shown), and are covered with a first inter-level insulating layer 1. A lower metal line 2 of aluminum is patterned on a the lower inter-level insulating layer 1 as shown in FIG. 1A. Insulating material is deposited over the entire surface of the resultant structure by using a plasma-assisted chemical vapor deposition at 380 degrees Centigrade, and forms a second inter-level insulating layer 3 as shown in FIG. 1B.
A photo-resist etching mask (not shown) is formed on the second inter-level insulating layer 3, and has an opening over the lower metal line 2. Using the photo-resist etching mask exposes a part of the second inter-level insulating layer 3 to an etchant, and the second inter-level insulating layer 3 is selectively etched away so as to form a via-hole 4 in the second inter-level insulating layer 3 as shown in FIG. 1C.
Subsequently, an outgassing is carried out in high-temperature vacuum. The resultant structure is placed in vacuum, and is heated to 450 degrees Centigrade. The high-temperature vacuum ambient for the outgassing is higher in temperature than a sputtering temperature described hereinlater with reference to FIG. 1G. Then, the second inter-level insulating layer 3 emits gas as indicated by arrows in FIG. 1D.
In order to enhance the surface property known as wettability, titanium is deposited over the entire surface, and forms a titanium layer 5. The resultant structure is maintained in the vacuum chamber without breaking the vacuum, and aluminum is deposited over the entire surface in low-temperature ambient at a high sputtering rate. Thus, an aluminum layer 6 is deposited on the titanium layer 5 as shown in FIG. 1F. The aluminum layer 6 defines a secondary via-hole 7.
Subsequently, aluminum is deposited over the entire surface of the resultant structure in a high-temperature ambience at a low sputtering rate without breaking the vacuum. The high-temperature low-rate sputtering results in a surface diffusion of aluminum. The aluminum fills the secondary via-hole 7, and swells into an aluminum layer 8 The aluminum layer 8 is merged into the aluminum layer 6, and the titanium reacts with the aluminum to form a titanium-aluminum alloy layer 9 as shown in FIG. 1G.
The titanium-aluminum layer 9 and the aluminum layer 8 are patterned into an upper metal line 10 by using a photo-lithography and etching process. The resultant wiring structure is shown in FIG. 1H.
The high-temperature low-rate sputtering gives rise to the surface diffusion, and fills the miniature via-hole 7 with the aluminum. As a result, the step-coverage is substantially improved. However, a problem is encountered in the prior art process in that hillocks and whiskers are grown from the lower metal line 2 due to the thermal stress. The hillocks and the whiskers may cause a short-circuit between the aluminum lines.
It is therefore an important object of the present invention to provide a process for fabricating a semiconductor device which has improved step coverage without any short-circuit.
The present inventor contemplated the problem. Although the lower metal line 2 of refractory metal such as tungsten or titanium nitride was free from the problem, the refractory metal and the refractory metal nitride have larger resistivity values than aluminum, and were not desirable for a high-speed integrated circuit. Then, the present inventor investigated the prior art process, and paid attention to the outgassing step. The present inventor carried out the outgassing at different temperatures in the prior art process, and obtained plural groups of samples different in outgassing temperature. The present inventor observed the plural groups of samples to see how may lower metal lines 2 were damaged by hillocks and whiskers. The present inventor plotted the number of damaged samples in terms of the heating temperature as shown in FIG. 2. The present inventor noticed that the number of damaged samples drastically increased from where the outgassing temperature was roughly equal to the deposition temperature of the second inter-level insulating layer 3. The present inventor concluded that the critical outgassing temperature was roughly equal to the deposition temperature of the second inter-level insulating layer 3.
To accomplish the object, the present invention proposed to carry out an outgassing process at a temperature that is not higher than a deposition temperature of the inter-level insulating layer.
In accordance with one aspect of the present invention, there is provided a process for fabricating a semiconductor device comprising the steps of a) forming a lower metal line over a semiconductor substrate, b) covering the lower metal line with an inter-level insulating layer under the condition that the semiconductor substrate is heated to a first temperature at the maximum, c) forming a via-hole in the inter-level insulating layer, d) carrying out an outgassing under the condition that the semiconductor substrate is heated to a second temperature equal to or less than the first temperature so as to remove contaminants from the inter-level insulating layer and e) forming an upper metal line penetrating into the via-hole and formed of a conductive material selected from the group consisting of aluminum and aluminum alloys.
USPTO Backgrounds
USPTO Backgrounds