This application is a continuation in part of, and claims benefit of the filing date of, and hereby incorporates fully by reference, a parent application entitled “Method for Fabricating a Self-Aligned Bipolar Transistor and Related Structure,” Ser. No. 10/218,527 filed Aug. 13, 2002, and now U.S. Pat. No. 6,784,467 and assigned to the assignee of the present application. This application also hereby incorporates fully by reference a related U.S. patent application entitled “Method for Fabricating a Self-Aligned Emitter in a Bipolar Transistor” Ser. No. 09/721,344 filed Nov. 22, 2000, issued as U.S. Pat. No. 6,534,372, and assigned to the assignee of the present application.
1. Field of the Invention
The present invention is generally in the field of fabrication of semiconductor devices. More specifically, the invention is in the field of fabrication of bipolar transistors.
2. Background Art
As modern electronic devices increase in speed while decreasing in size and price, semiconductor manufacturers are challenged to provide low-cost, high speed, and small size transistors for these devices. To meet this challenge, semiconductor manufacturers must accurately control the size of certain features that critically affect the performance of transistors on a semiconductor wafer, such as emitter widths of bipolar transistors. Furthermore, various parts of the bipolar transistor must be properly aligned to ensure that the bipolar transistor meets performance requirements. For example, the emitter and the extrinsic base implant in a heterojunction bipolar transistor (HBT) must be properly aligned to prevent an undesirable increase in base resistance.
In one conventional fabrication process for a bipolar transistor, such as an HBT, semiconductor manufacturers utilize a first photomask to control the bipolar transistor's emitter width, which is generally referred to as a critical dimension, or “CD.” A second photomask, which must be properly aligned with the first photomask, is utilized to determine the boundaries of the heavily doped extrinsic base regions of the bipolar transistor. Misalignment of the two photomasks causes, among other things, problems in manufacturability of the bipolar transistor. Additionally, in the two-photomask fabrication process described above, the first photomask must be accurately controlled to control the emitter width of the bipolar transistor. Also, misalignment of the two photomasks can cause an undesirable reduction in manufacturing yield, which can cause a corresponding increase in manufacturing cost.
Other fabrication processes and tools have been tried in attempts to solve the problem of aligning the extrinsic base to the emitter in bipolar transistor devices. One approach requires the use of selective epitaxy along with the use of an inside spacer. Selective epitaxy presents a problem in that it is not currently used in high volume production of semiconductor devices. Selective epitaxy presents another problem in that selective epitaxial deposition occurs only on silicon regions and not on oxide regions. Since most process monitoring is done on oxide regions, selective epitaxy results in a substantial loss of process monitoring capability. Use of an inside spacer presents a further problem in that variability of emitter width is greater than with other methods, so some accuracy in control of emitter width is lost.
In addition, as feature sizes of bipolar devices are reduced, it is important and more difficult to achieve accurate control over the size of certain features, such as the emitter width of the bipolar transistor.
Thus, there is need in the art for a fabrication process for bipolar transistors which does not rely on the alignment of separate photomasks to form the intrinsic base region, the base-emitter junction, and to implant the heavily doped extrinsic base region.
USPTO Backgrounds
USPTO Backgrounds