1. Field of the Invention
The invention is in the field of manufacturing integrated circuits and is directed to a method for structuring a silicon layer and, in particular, to a method for structuring a layer using a hard mask composed of silicon.
2. Description of the Related Art
Structuring of layers usually utilizes a mask that is applied onto the layer to be structured and leaves those regions of the layer to be structured uncovered that are to be eroded by a subsequent etching.
Masks can be fundamentally divided into two main groups. Lacquer masks, which form the first group, are relatively sensitive to mechanical erosion. Moreover, they frequently do not exhibit any high temperature stability. However, they can be easily manufactured and structured. Another advantage of lacquer masks is that they can be composed of a radiation-sensitive material, particularly of a photoresist, and can thus be directly lithographically structured.
In comparison, hard masks are composed of a comparatively temperature-stable and hard material. These masks exhibit greater resistance to mechanical erosion. Hard masks exhibit a comparatively slight erosion particularly in view of anisotropic etching methods that directly bombard the structure with reactive molecules or atoms. As a result, the structures fashioned in the hard mask can be transferred to the layer to be structured with greater dimensional accuracy.
Hard masks must usually be structured with lacquer masks first before they can be employed as mask.
The employment of a hard mask of amorphous silicon for forming via holes between metallization levels (“vias”) is disclosed, for example, by U.S. Pat. No. 6,165,695. The amorphous silicon is first selectively etched relative to a lacquer mask using magnetically enhanced relative ion etching (MERIE) utilizing Cl2 and HBr. The structural transfer from lacquer mask onto the amorphous silicon, however, is not very satisfactory.
Other etching methods are also known for etching silicon relative to lacquer layers. Thus, U.S. Pat. No. 6,235,214 B1 discloses the single-stage etching with an SF6/O2/CHF3 mix or the two-stage etching with an SF6/O2/CHF3 mix and an SF6/O2 mix. In contrast, an HBr/Cl2/He—O2 mix is employed according to U.S. Pat. No. 5,767,018. An HBr/Cl2/He—O2 mix is likewise employed in U.S. Pat. No. 6,136,211 for etching polysilicon. Other etching methods employ an NF3/HBr mix.
These methods, however, are only conditionally suitable for future structure sizes that lie in the range of 140 nm and below, since the selectivity between the lacquer mask and silicon in these methods is often low and—over and above this—the etching leads to sidewalls having a slope that cannot be controlled or can only be controlled with great difficulty. However, an improved structure transfer from the lacquer mask onto the silicon layer is needed for the small structures that have been mentioned.
USPTO Backgrounds
USPTO Backgrounds