New generations of microprocessors are continuously evolving. The need for processing an ever increasing amount of information in shorter and shorter times is leading the manufacturers of these devices to lower the voltage supply and increase the input current requirement. Accordingly, modern microprocessors may require currents of many amperes (up to 50 A at present), not in a continues manner, but determined by the amount of operations to be processed at a certain instant. Therefore, the current absorbed may change from tens of mA to 10-12 A in a few nanoseconds. A common slew rate requirement is of about 5 A/ns which is generally fulfilled using an array of large capacitors, often placed in the socket mount of the microprocessor.
This approach does not relieve the power supply from quickly responding to the sudden need for current. In addition, the slew rate value which at present seems to be needed to maintain a stable level of the supply voltage of the array of capacitors is of about 30 A/.mu.s, a quite respectable figure which is not easily ensured.
The manufacturers of power supplies are adopting particular approaches in trying to speed up the response of switching DC--DC converters used therein. Current mode converters are by far the most widely used because of their good response characteristics. However, they require the use of a current sensing resistor of few Ohms connected in series to the inductor. The sensing resistor leads to a power dissipation, which increases with the square of the output current of a DC--DC step-down converter, and is, thus, becoming more and more unacceptable.
Accordingly, voltage mode approaches are gaining ground because they do not require such a dissipating sensing resistor. However, due to their slow response, they require special "tricks" to attain an acceptable speed of response.
A commonly adopted approach includes placing two comparators about the reference voltage of the system. These comparators continuously check the real output voltage and act on the control loop at the instant in which a certain range is exceeded. At present this is implemented in the commercial converters LTC1430 and LTC1553 manufactured by Linear Technology and in the series of devices 4900/01/02 of Microlinear, all functioning in a voltage mode.
The response time of current mode converters is normally in the vicinity of a few clock cycles and therefore no need has ever been felt in the past for increasing their response speed. Moreover, new current control techniques have made these types of converters an interesting approach even for high current applications (for instance, the technique of exploiting the RdsON of the external power MOS transistor for sensing the current). In view of slew rate requirements as those cited above, it may become necessary to improve even the already fast response time of current mode converters to attain delay times that do not exceed a few hundred nanoseconds before the turn-on of the external MOS transistor occurs.
FIG. 1 shows the scheme of a prior art current mode Buck converter. In the ensuing description reference will be made to this circuit topology even though the invention is similarly applicable to any other topology of switching converters, operating in a current mode.
The block indicated with the symbol .SIGMA. is the so called "error summing" block, whose internal diagram is shown in FIG. 2. This block .SIGMA. is responsible for stabilizing the system and for the precision of the output voltage. Indeed, this block .SIGMA. decides when to turn-off or turn-on the power transistors Hside and Lside of the switching converter.
The block .SIGMA. receives three distinct differential input signals: the error voltage of the comparison between the reference voltage and the output of the converter (Vref-Vfb), the potential difference (Isense-Vsense) on the sensing resistor connected in series with the output inductor Lf of the converter, and the voltage signal (slope+ slope-) coming from the sawtooth oscillator which creates the ramp compensation. The error summing block .SIGMA. governs the turn-off of the power transistor Hside when the sum of the three contributing signals, with the indicated signs, reaches the zero value.
The low pass filter, LP-Filter, placed between the converter output and the error summing block .SIGMA. is needed for stabilizing the system. The pole introduced by the filter may range from a few kHz to tens of kHz, depending on the application.
The PWM-control-block manages all the control signals coming from the analog parts (zero-crossing comparators, under/over-voltage, etc.) and from the error summing block .SIGMA. itself and generates the signals for the MOS driver block which directly drives the external power MOS transistors. To obtain systems operating at a constant frequency while the turn-off of the external MOS (Hside) is totally asynchronous and controlled by the signal Ersum signal, the turn-on cannot take place at any successive instant but rather, only in synchronism with the clock.
Unfortunately, this characteristic introduces a certain turn-on delay, whose maximum value is equal to the clock period. In other words, if the signal Ersum decided that a turn-on must take place again a few nanoseconds after a clock pulse, the turn-on may occur only at the next pulse and not immediately as decided by the signal Ersum.
FIG. 2 is the diagram of the error summing block .SIGMA.. The blocks X0, X1 and X2 usually are amplifiers of a very low gain (of a few units or of unity gain) and their contribution is summed in block X14 to produce a signal which is compared with the zero (gnd) by the output comparator XS, thus converting the information into the form of a logic signal (signal outesc).
USPTO Backgrounds
USPTO Backgrounds