Present very large scale integrated (VLSI) circuit technology allows the realization of single chip semiconductor devices having equivalent circuit elements an order of magnitude greater in number than on available devices of only a few years ago. Equivalent gates and circuits of VLSI devices, such as Motorola's M68000 microprocessor having 68,000 circuit elements, are approaching numbers near 100,000 with ranges of up to 500,000 anticipated by the mid-1980's. This trend of increasing chip complexity has been paralleled by a growing demand for the application of microprocessors in multiplexed data bus systems.
An example of such an application is the Integrated Avionics Control System (IACS) terminal developed by the assignee of the present invention. Designed to interface with a control network data bus, the IACS terminal may be used to carry out monitoring and control functions for any of a wide variety of control subsystems in ground vehicles, automatic test equipment, space systems, water vehicles, avionics systems, central controllers, etc. The military standard (MIL-STD) 1553 biphase serial bus, for which the IACS terminal was developed, provides for standardized inter-subsystem communication in such control systems by defining a flexible set of message formats and communication protocols. Accordingly, the IACS terminal satisfies the MIL-STD-1553 protocols by providing a custom LSI buffer interface between a G3008 general purpose microprocessor and a Harris HD-15531 Manchester Encoder/Decoder linked to the serial bus by a CT 1231 Transceiver, manufactured by Circuit Technology.
U.S. Pat. No. 4,222,116, issued to Groves, provides another example of a device designed for Manchester-encoded data multiplexing. The Groves device adds to the prior art the capability of handling varied data rates in Manchester encoded data streams.
A shortcoming of the above and other presently available devices, however, is that a dedicated processing device is required to generate the complex timing patterns involved in monitoring and controlling data transfers on the serial bus. As a result, existing network serial bus systems are limited as to the applicable processing devices employed in each subsystem terminal. Flexibility in control subsystem design is limited, therefore, by the capabilities of processors which can be adapted to present multiplex terminals.
A major object of this invention, then, is the provision of a bus interface unit capable of handling the protocols of a wide variety of flexible bus communication message formats and data transfer algorithms. Such message formats and data transfer algorithms may, for example, be designed to implement MIL-STD-1553 protocols.
Another object of the present invention is the design of a bus interface unit which frees an associated processing device from monitoring and controlling data transfer over an associated network serial bus. In keeping with this object, a goal of the present design is the implementation of a direct memory access with an associated microprocessor memory in which data transfer sequences between the network serial bus and microprocessor memory are conducted in a transparent fashion with respect to the microprocessor.
Yet another object of the present invention is the provision of a bus interface unit capable of being operated in either a bus controller or a remote terminal mode. As a bus controller, the bus interface unit initiates intersubsystem messages, while as a remote terminal, it responds in a predetermined manner to commands from another similar unit acting as a bus controller.
A still further object of this invention is to supply a bus interface unit which is compatible with a wide variety of existing microprocessors and transmitter/receivers.
It is yet a further objective of the present invention to provide such a unit which minimizes software interface requirements and processor interaction with the network bus. Realization of this objective maximizes bus utilization capability as well as freeing the processor to collect subsystem information concurrently with bus communications.
One still further object of this invention is to provide a bus interface unit with extensive means for error checking in serial bus communication to allow fail-safe control system operation.
It is another general object of this invention to provide a bus interface unit having a regular and structured architecture which may be implemented on a single chip using presently available technology.
USPTO Backgrounds
USPTO Backgrounds