Memristor and two-terminal devices generally may utilize a crossbar configuration including a switching material or device disposed between two conducting electrodes that overlap one another perpendicularly. Since such devices do not need a single-crystal silicon or a monolithic substrate, they can be integrated at a greater density compared to standard microelectronic devices when using a stacked three-dimensional structure. The stacking capability can lead to advances in the storage capacity, for example, of memory chips. However, stacking multiple layers of crossbar structures may need a number of lithography process steps proportional to the number of layers stacked, which can add expense to devices using such crossbar structures.
For example, fabrication of a single plane of crossbar arrays may generally use two or more lithography steps. Therefore, stacking multiple (e.g., N) layers of the single plane of crossbar arrays may use at least 2*N lithography steps. Additional lithography steps may be needed to form vias that contact these arrays. A via is a vertical electrical connection between different layers of conductors, for example, in a printed circuit board. For an eight layer stacked architecture, therefore, upwards of sixteen lithography steps may be needed. As discussed above, such multiple steps can add expense to devices using such crossbar structures that may include multiple layers.
USPTO Backgrounds
USPTO Backgrounds