Applicant hereby incorporates by reference Japanese Application No. 2001-188174 (P), filed Jun. 21, 2001, in its entirety.
1. Technical Field
The present invention relates to the manufacture of LSIs, and more particularly relates to methods for manufacturing semiconductor devices, including highly integrated semiconductor devices with an improved embedded wiring and metal plugging technology.
2. Related Art
As the progress is being made for even higher integration of LSIs, and further miniaturization of LSI chips, the structure of multiple wiring layers is further miniaturized, and the embedded wiring technology is becoming more important. In particular, as the aspect ratio of a connection hole (contact hole or via hole) becomes greater, an embedded wiring, which is represented by a W (tungsten) plug, becomes more difficult to be embedded within a gap.
FIGS. 3(a)-(d) show cross sections of portions of a method for forming an embedded wiring with a common W plug. As shown in FIG. 3(a), a hole 32 that connects to a lower conductive region 40 (a diffusion layer or a lower wiring layer) is formed in an interlayer dielectric layer 31, using a lithography technique.
Next, as shown in FIG. 3(b), a step of enlarging an opening area of the hole 32 is conducted. In this step, an inverse sputter step is conducted, using Ar plasma, to physically etch an opening edge section of the hole by the ion impact. Enlarging the opening area of the hole 32 makes it easier to embed W in the hole having a high aspect ratio. Also, the surface of the lower conductive region 40 is cleaned by the ion impact, such that a contact resistance between the W and the conduction region is lowered.
Next, as shown in FIG. 3(c), a barrier metal 33 is vapor deposited on the interior of the hole 32 by a sputter method. The barrier metal 33 is vapor deposited by a sputter method in a manner to cover at least a bottom section of the hole. Next, W is deposited to embed the hole 32. Then, the W is etched back by using a plasma etching technique to complete a W plug 34 in the hole 34.
Next, as shown in FIG. 3(d), an upper wiring layer 35 (351, 352) is patterned by using a lithography technique. The wiring layer 352, which is located adjacent to the wiring layer 351, is to be connected to another W plug (not shown).
USPTO Backgrounds
USPTO Backgrounds