Serializer and De-serializer (SerDes) circuits facilitate the transmission of data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a storage or transmission channel to the second point where it received and converted from serial data to parallel data. In general, a clock signal is not transmitted along with the data signal, and it is necessary to recover the sampling clock at the receiver to sample the received data at the correct points. A clock and data recovery (CDR) circuit in a serializer and de-serializer detects timing of the input data stream and uses the detected timing to set correct frequency and phase of a local clock from which the sampling clock for data sampling is derived. The objective of the clock and data recovery circuit is to track the phase of a sampling clock based on some criterion. However, digital clock and data recovery circuits typically cannot acquire the transmitter clock where a large frequency offset in the thousands of parts per million between the transmitter and receiver clocks, due to their high latencies. This severely deteriorates system performance. A rotation frequency detection (RFD) algorithm employing an eye scope latch can be used to adjust the clock and data recovery circuit to acquire the transmitter clock. However, the eye scope latch significantly increases the hardware complexity and power consumption and requires calibration of the eye scope latch.
USPTO Backgrounds
USPTO Backgrounds