1. Field of the Invention
The present invention generally relates to a soft-start circuit, and particularly, to a full digital soft-start circuit workable under low power supply.
2. Description of Related Art
In a conventional power supply system which requires a pulse width modulation (PWM) scheme, a large inductance or a large capacitance is often needed for power storage or power conversion to boost or buck voltages. Typically, a soft-start circuit is usually employed in such a power supply system to protect components and internal circuitry from being damaged by high transient currents during initialization of the power supply system.
In a typical soft-start circuit for a conventional power supply system, a resistor capacitor loop is often introduced for the required output voltage. FIG. 1(a) is a schematic diagram of a conventional soft-start circuit. As shown in FIG. 1(a), the conventional soft-start circuit includes transistors 101 and 103, a resistor 102, a capacitor 104, and a comparator 105.
The transistor 101 includes a gate electrode connected to an enable signal ENB, a source electrode connected to a voltage supply, and a drain electrode connected to a first terminal of the resistor 102. The transistor 103 includes a gate electrode connected to the enable signal ENB, a source electrode coupled to GND, and a drain electrode connected to a second terminal of the resistor 102, a positive input terminal of the comparator 105, and a first terminal of the capacitor 104.
The first terminal of the resistor 102 is connected to the drain electrode of the transistor 101, and the second terminal of the resistor 102 is connected to the positive input terminal of the comparator 105, the drain electrode of the transistor 103, and the first terminal of the capacitor 104. The positive input terminal of the comparator 105 is connected to the first terminal of the capacitor 104, the first terminal of the resistor 102, and the drain electrode (which is also a node voltage VST) of the transistor 103. A negative input terminal of the comparator 105 receives a triangle signal TRI. The first terminal of the capacitor 104 is connected to the positive input terminal of the comparator 105, the second terminal of the resistor 102, and the drain electrode of the transistor 103. The second terminal of the capacitor 104 is connected to GND.
The comparator 105 compares the triangle signal TRI with the node voltage VST which is charged by the resistor 102 and the capacitor 104. As shown FIG. 1(b), when the triangle signal TRI is lower than the node voltage VST, an output signal EXT of the comparator 105 is at logic high level, and when the triangle signal TRI is higher than the node voltage VST, the output signal EXT of the comparator 105 is at logic low level. As time going on, the node voltage VST keeps ascending, so does a duty cycle of the output signal EXT.
In order to avoid large currents from damaging components and the circuitry during initialization of the power supply system, the node voltage VST must ascend slowly, and therefore the capacitance of the capacitor 104 should be about several μF. Further, this system requires analog circuits such as a triangle signal generator and a comparator 105, so that the soft-start circuit must be operated at an operation voltage higher than 1V for maintaining the normal operation.
As such, it is desirable to develop a soft-start circuit adapted to eliminate the disadvantage of the conventional technology that requires external capacitors.
It is also desirable to develop a full digital soft-start circuit without using external capacitors that can be obtained by complementary metal-oxide-semiconductor processes.
USPTO Backgrounds
USPTO Backgrounds