(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method to automatically assemble flex Ball Grid Array (BGA) packages that have been enhanced.
(2) Description of the Prior Art
In the semiconductor manufacturing industry, device performance continues to improve concurrent with the unrelenting strain of competitive advantage gained by tight control of device manufacturing cost. The basic laws of electronic design and device performance derived therefrom dictate that device performance in most cases can only be gained if device feature dimensions are further reduced. This has led to the era of the Ultra Large Scale Integration (ULSI) where device feature dimensions in the micron and sub-micron range are becoming the norm. This results in greatly increased device density, which in turn results in increased requirements that are imposed on the technology that concerns itself with the connection of the completed devices to the surrounding electronic interfaces or components.
Increased device circuit density does not necessarily result in smaller device packages. In fact, in many applications, device package size has increased concurrently with the increase in device density. The requirements to connect higher density, larger size devices to the surrounding environment has led to the development of surface mounted packages. With the increase in device density and the concomitant increase in functions being packaged per Integrated Circuit (IC), the need has arisen to provide increased input/output (I/O) capabilities for the IC. This increase in I/O connectivity however must be provided while reducing the footprint of the interconnecting medium, while maintaining acceptable thermal performance of the package and at the same time having no negative impact on the package reliability.
One of the conventional methods that have been used to assemble IC""s with high device density and high I/O requirements has been the use of Tape Automated Bonding (TAB) or lead-frame packages. A TAB or lead-frame typically contains only one layer of interconnect lines. As is well known in the art, these packages can thermally and electrically perform satisfactorily with an I/O count of up to 300 leads at a thermal rating of 10 Watts while operating at a clock rate of 50 MHz. The area that is taken up be the I/O connects is determined not only by the footprint of the interconnect points but also by the distance or pitch between these I/O interconnect points. The presently established pitch is around 0.5 mm between adjacent I/O points; this does however impose limitations on the IC device interconnectivity. It is also clear that device operating speed will continue to increase at the same time that power (watts) consumed per IC device will continue to increase concurrent with the increase in circuit density. Decreasing the pitch of the I/O interconnect lines requires ever increasing sophistication in the deposition of the interconnect lines, a requirement that is further emphasized by requirements of adhesion to the underlying surface, contact resistance, resistance to corrosion and, ultimately, requirements of reliability in the face of high temperature down-stream processing.
The development of the Ball Grid Array (BGA) devices has offered the opportunity to spread device I/O interconnect points over the entire surface of the device, this as opposed to having I/O connect points available only around the periphery of the IC device. Typically, the BGA package is surface mounted and mounted on the surface of a motherboard (a Printed Circuit Board or PCB). The concerns of making reliable I/O interconnects now have shifted from fine pitch in-line lines to contact balls. General sizes that are currently in use for Quad Flat Pack (QFP) packages are a footprint in the 25xc3x9725 mm range, a lead pitch of around 0.5 mm while the package itself is about 2 mm thick. A typical ball pitch for a BGA package is around 1.5 mm, with a footprint similar in size to the QFP package and a package thickness similar or slightly less than the thickness of a QFP package.
In assembling a BGA package to a PCB, the lower surface of the PCB is typically provided with contact balls that connect to an interfacing network of conducting lines that connect to surrounding electrical components or systems. A typical PCB contains two layers of interconnect metal. A cavity is typically formed in the upper surface of the PCB, the semiconductor device that is to be mounted on the PCB is inserted into this cavity. The contact balls of the BGA make electrical contact with the layers of interconnect metal in the PCB, the BGA die is further wire bonded to the PCB and enclosed in a molded casing. The operation of wire bonding limits the size of the surface on which the wire is connected which in turn increases the size of the die that can be used. The side of the BGA that faces the PCB in this arrangement is the backside of the IC die, heat exchange between the BGA die and the underlying PCB takes place through this interface of the BGA die with the PCB. Since signal lines (in the PCB) are typically of fine construction, these lines do not lend themselves to provide a good path for heat exchange. The heat exchange between the BGA and the PCB must therefore depend on (wider or larger in cross section) ground planes in the PCB, which brings with it a limitation on the space that is available to route signal lines in the PCB.
Present PCB technology is limited in the reduction of line size that it can apply in a cost effective and reliable design. This limits the operating clock cycle for the circuit application in which the PCB can be used.
In mounting relatively small size IC devices on the surface of relatively large size PCB""s, the thermal expansion and the related acceptance or rejection or moisture content within the larger PCB can have a serious negative effect on the package performance under elevated temperatures. In the case where there is a high moisture content present in the assembled PCB, this moisture content will expand rapidly during down-stream operations, especially where these down-stream operations are required for the assembly of the BGA packages to the PCB. This rapid expansion of the PCB can cause severe thermal stress in interconnected surfaces to the point where these surfaces may be dislocated and break. It is therefore of great importance that every effort is made to limit the moisture content in the PCB prior to the assembling of the BGA into the PCB.
Thermal performance of a PCB mounted BGA can be improved by enhancing the contact between the PCB and the BGA by adding a body of metal in the cavity that is created in the PCB for the insertion of the BGA. This method has been applied successfully when mounting the BGA in a cavity that is created in the lower surface of the PCB. This method of mounting the BGA is however more difficult and incurs added cost in the manufacturing process.
Many of the techniques that have been discussed for mounting IC devices that have extended I/O capabilities do not lend themselves to high speed, automated methods of assembly. The well-known technique of Tape Ball Grid Array (TBGA) suffers from this disadvantage resulting in high assembly cost for the package. An exception from this is the Plastic Ball Grid Array (PBGA) where multiple PBGA""s can be formed from a single PCB strip while standard processing equipment has been designed to perform the process of assembling the package. The PCB strip that is used to assemble the PBGA package constitutes a substrate for providing interconnects in the package while serving as structural support for the package. The cost of assembling the PBGA package is sharply increased by the fact that, during assembly of the package, a relatively large amount of the PCB is discarded during the assembly.
A further consideration in using mounting methods for mounting BGA devices is the reflow and melting temperature of the contact balls. For BGA devices that are mounted on for instance PCB strips, some of the materials that make up the PCB strip may be affected by increased temperatures in an unacceptable process. If therefore the temperature of the PCB mounted BGA device is raised, for instance for rework purposes, damage to the PCB material may result. The chemical composition of the material used for the contact balls also plays a role in this in that the flow or softening of the contact balls is determined by the materials that have the lowest flow or melting point thereby making the contact balls unsuitable for high temperature environments. It can in this manner occur that, when a PBGA is removed from the motherboard for rework, some of the contact balls will separate from the PBGA package and adhere to the PCB. This results in time consuming and expensive rework or in complete loss of the removed device or even the PCB from which the device was removed.
Solder ball fatigue and mechanical stress that is exerted on the solder ball where the balls make contact determine the reliability performance of the ball interconnects. Ball fatigue is strongly influenced and determined by the thermal environment in which the contact balls are used with frequent and extreme variations in the temperature of the surrounding environment having a serious negative effect on the long term reliability of the contact balls. This effect can further be aggravated and can result in mechanical failure (sheer or breakage) if the thermal expansion of the environment with which the contact balls interface reacts have thermal coefficients of expansion that differ significantly from the thermal expansion of the contact balls. Under these conditions of thermal reaction, the mechanical stress that is exerted on the contact balls due to the thermally induced and mutually contradictory way of expansion and contraction, the contact balls have a high probability of mechanical failure making the overall package unreliable. It is therefore of key importance to realize that thermal performance is part of the overall package design and that considerations of cooling and transmission of heat generated by the devices that are mounted in these packages are very important in creating a successful package design.
U.S. Pat. No. 5,843,808 (Karnezos) shows an assembly of a Tab grid array assembly in strip form. Cited by the inventors.
U.S. Pat. No. 5,409,865 (Karnezos) and U.S. Pat. No. 5,397,921 (Karnezos) show TAB grid arrays.
U.S. Pat. No. 5,852,870 (Freyman et al.) shows a method for a Grid array assembly.
U.S. Pat. No. 5,635,671 (Freyman et al.) shows a mold runner removal process for a package.
U.S. Pat. No. 5,620,928 (Lee et al.) teaches a BGA method using a flex tape.
A principle objective of the invention is to provide a reliable and cost effective package for packaging BGA devices. The package comprises a tape with adhesive and copper traces attached below, a solder mask layer with openings that covers the copper traces, a stiffener structure having a cavity for accommodating the die having an electrically conductive surface
In accordance with the objectives of the invention a new package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape. The invention offers the means for single unit (or package) attachment and transportation, a process carrier is used for this purpose. The process carrier is a flexible band or tape on which a single package is mounted and transported between processing stations. A carrier holder interfaces between the single unit and the process carrier.
USPTO Backgrounds
USPTO Backgrounds