1. Field
Circuit structures.
2. Relevant Art
Integrated circuits typically use conductive interconnections to connect individual devices on a chip or to send or receive signals external to the chip. A currently popular choice of interconnection material for such interconnections is a copper or copper alloy material.
One process used to form interconnections, particularly copper (alloy) interconnections, is a damascene process. In a damascene process, a trench is cut in a dieletric and filled with copper to form the interconnection. A via may be in the dielectric beneath the trench with a conductive material in the via to connect the interconnection to underlying integrated circuit devices or underlying interconnections. In one damascene process (a “dual damascene process”), the trench and via are each filled with copper material, by, for example, a single deposition.
A photoresist is typically used over the dielectric to pattern a via or a trench or both in the dielectric for the interconnection. After patterning, the photoresist is removed. The photoresist is typically removed by oxygen plasma (oxygen ashing). The oxygen used in the oxygen ashing can react with an underlying copper interconnection and oxidize the interconnection. Accordingly, damascene processes typically employ a barrier layer of silicon nitride (Si3N4) directly over the copper interconnection to protect the copper from oxidation during oxygen ashing in the formation of a subsequent level interconnection. In interlayer interconnection levels (e.g., beyond a first level over a device substrate), the barrier layer also protects against misguided or unlanded vias extending to an underlying dielectric layer or level (e.g. the barrier layer serves as an etch stop)
In general, the Si3N4 barrier layer is very thin, for example, roughly 10 percent of the thickness of an interlayer dielectric (ILD) layer. A thin barrier layer is preferred primarily because Si3N4 has a relatively high dielectric constant (k) on the order of 6 to 7. The dielectric constant of a dielectric material, such as an interlayer dielectric, generally describes the parasitic capacitance of the material. As the parasitic capacitance is reduced, the cross talk (e.g., the characterization of the electric field between adjacent interconnections) is reduced as is the resistance-capacitance (RC) time delay and power consumption. Thus, the effective dielectric constant (keff) of an ILD layer is defined by the thin barrier layer and another dielectric material having a lower dielectric constant so that the effect of the dielectric material typically used for the barrier layer (e.g., Si3N4) is minimized.
In prior art integrated circuit structures, a popular dielectric material for use in combination with a barrier layer to form ILD layers was silicon dioxide (SiO2). Currently, efforts have focused at minimizing the effective dielectric constant of an ILD layer so materials having a dielectric constant lower than SiO2 have garnered significant consideration. Many of these materials, such as carbon doped oxide (CDO), are porous. The dielectric constant of a dielectric material can be substantially effected by water or liquid absorbed in the pores of the dielectric material.
A typical part of a damascene process to form an interconnection in an ILD layer is a planarization after a deposition of the interconnect material. A typical planarization is a chemical mechanical polish (CMP). A CMP is a wet process that can introduce water or other liquid into a porous dielectric material. In addition, it can add mechanical stress to a dielectric layer. Stress can damage a dielectric layer and effect circuit performance.
The features of the described embodiments are specifically set forth in the appended claims. Referring to the following description and accompanying drawings, in which similar parts are identified by like reference numerals, best understand the embodiments.
USPTO Backgrounds
USPTO Backgrounds