1. Field of the Invention
The invention relates to semiconductor processing, and more particularly to a method of improving the temperature uniformity from the edge to the center of a wafer during rapid thermal annealing (RTA).
2. Description of the Related Art
During rapid thermal anneal (RTA) temperature uniformity from the edge to the center of a semiconductor wafer is a concern especially at high temperatures. In current processes it has been observed that the temperature tends to be higher at the edge of the wafer causing higher boron penetration and higher silicide resistance at the edge. This effect results in a very undesirable spread of the threshold voltage V.sub.t with lower voltages measured at the edge than in the center of the wafer.
A way to improve temperature uniformity is to apply an in situ polysilicon layer to the backside of the wafer. A number of U.S. Patents teach coating of the backside of the wafer to solve a variety of problems.
U.S. Pat. No. 5,716,875 (Jones, Jr. et al.) discloses the use of a hydrogen anneal to reduce dangling atomic bonds at the dielectric/substrate interface of transistors. A silicon nitride layer is then deposited over the transistors and on the backside of the wafer substrate in order to encapsulate the effects of the hydrogen anneal to the CMOS transistors.
U.S. Pat. No. 5,656,510 (Chrapacz et al.) presents a method to provide a backside dielectric layer which protects the semiconductor from electro-static discharge. The backside dielectric layer may be either a nitride or an oxide.
U.S. Pat. No. 5,605,602 (DeBusk) provides a method and device for removing a thin film from a wafer backside. Dopant ions or polysilicon can be deposited upon the exposed backside to enhance extrinsic gettering properties.
U.S. Pat. No. 5,395,770 (Miki et al.) teaches a method of controlling a misfit dislocation by introducing an extrinsic strain on the back surface of the semiconductor substrate and then depositing an epitaxial layer on the semiconductor substrate.
U.S. Pat. No. 4,853,345 (Himelick) describes a process for an n-channel transistor to form a predeposit simultaneously over the polysilicon gate electrode and over the back surface drain region of the chip. This predeposit is followed by a step to form an n-type source region and to make the back surface more conductive
U.S. Pat. No. 4,608,096 (Hill) teaches the use of a 0.05 to 2.0 micron thick layer of polysilicon on the backside to improve gettering capabilities.
It should be noted that none of these above-cited U.S. Patents of the related art address correction of the problem of temperature non-uniformity.
USPTO Backgrounds
USPTO Backgrounds