Row and column decoders are well known in the art for activating rows and columns in array devices. Many array devices are memory arrays, and the technology of row decoders has, in great part, been developed for use with such memory devices. Another type of array device is the array display device. This category includes liquid crystal display ("LCD") devices. In general, a row decoder is used to activate a particular row of the display such that data present on a plurality of column lines will affect the intended row. To date, the row and column decoders used with such video display devices are not substantially different in concept from comparable devices which are used in conjunction with memory array devices.
Another device known in the field is the predecoder. One skilled in the art will recognize that a predecoder will allow a required amount of binary data to be transmitted on fewer data lines than might be required if the data were not to be "predecoded". For example, four different row addresses can be referenced according to the four different logical state combinations of two data lines.
It is known in the art that capacitive interaction between adjoining data lines will substantially detract from the ability of such lines to change state rapidly. Where one line of two adjacent lines is changing state, this is somewhat of a problem. However, where the two adjacent lines are simultaneously attempting to change states in opposite direction (one is going high, while the other is going low), this problem is severely compounded, especially when the adjacent lines are long.
It would be a significant improvement if a method or apparatus were found to decrease the detrimental effect caused by the simultaneous state changes of adjacent data lines within a row or column decoder. This is particularly important given the present quest for increased speed and/or lower power consumption. (In this case, as in many such instances, there is a trade off between speed and power consumption. That is, a decrease in the capacitive interaction between adjacent lines could be used to cause greater operational speed for a given applied power. Alternatively, less power could be used to achieve the same speed, or some combination of improved speed and power consumption could be accomplished.) However, to the inventor's knowledge, no such improvement in the design of row and column decoders has been presented prior to the present invention.
USPTO Backgrounds
USPTO Backgrounds