The present invention relates to a semiconductor integrated circuit device and wiring correction equipment, and, more specifically, to technology which is particularly effective for a dynamic RAM (Random Access Memory) having a defect saving function, and wiring correction equipment thereof.
There has been proposed a dynamic RAM which is basically formed by a memory array consisting of a plurality of orthogonally crossing word lines and bit lines and dynamic memory cells being arranged, in the form of a lattice, at the intersecting points of these word lines and bit lines. As a method of enhancing product yield of these dynamic RAMs, the so-called "defect saving system" has been proposed, in which redundant word lines and redundant bit lines are provided for the memory array. These redundant elements are used to replace defective word lines or defective bit lines selectively. Accordingly, a number of dynamic RAMs are now provided with such defect saving systems. One example of such a dynamic RAM having a defect saving system has been described, for example, in an article in NIKKEI ELECTRONICS, pp. 209-231, Jun. 3, 1985, issued by Nikkei McGraw-Hill.
In a conventional dynamic RAM providing the defect saving system as explained above, the defective word lines and defective bit lines which are replaced with the redundant word lines or redundant bit lines are left connected with the memory array. From their studies the inventors have found that if a current leak path is formed, for example, via the common source line and bit line precharge circuits and defective word lines or defective bit lines of these circuits, such a chip will be considered as a defective product in the DC state because it will have a defective stand-by current and a defective plate level, although the chip is quite normal in its ordinary operating function. As a result of this, the saving rate of the dynamic RAM cannot be improved as much as expected even though it has the defect saving function. This creates a problem that the expected improvement for realizing low cost has been restricted.
Meanwhile, a conventional dynamic RAM providing such a defect saving function is typically provided with a plurality of defective address ROMS. These defective address ROMs are provided corresponding to redundant word lines or redundant bit lines to store defective addresses assigned to corresponding redundant word lines or redundant bit lines. The defective address ROMs include a plurality of fuse means which are cut in a predetermined combination, and a plurality of address comparison circuits which compare and collate, bit by bit, the known defective addresses with addresses supplied at the time of memory access, and which select the corresponding redundant word lines or redundant bit lines when these addresses are matched. When a dynamic RAM tends to have larger capacity, the number of bits of address signal also increases and thereby the number of required fuse means also increases, resulting in an increase of required layout area of the defective address ROM and address comparison circuit. Moreover, the number of logical stages of the address comparison circuit, etc. increases, and a comparatively longer time is required for the redundant word lines or redundant bit lines to be selected from the start of dynamic RAM. As a result, a problem is created that the chip area of dynamic RAMs having the defect saving function increases, so that the desired improvement for low cost is interfered with and the access time is delayed.
USPTO Backgrounds
USPTO Backgrounds