The present invention relates to a semiconductor device and a method of manufacturing the same, specifically to an effective technique for use in the semiconductor device incorporating high-speed ICs conforming to plural external supply voltages.
In general, the supply voltage externally supplied to LSIs formed on a semiconductor chip is not necessarily specified as one type, although the functions of the LSIs are identical. For example, the lower supply voltage is advantageous for higher-speed, or lower power consumption, but the time that the power supply voltage of the system using the LSIs is switched into the lower voltage in the market is not clearly foreseen, and the time comes differently depending on the users or the purposes for use. Some systems require modifying the supply voltage specification of the I/O (Input/Output) circuit in view of the noises against the signal.
Accordingly, an LSI manufacturer has to develop different LSIs with one and the same function at the same time, in correspondence with the different specifications of plural external supply voltages. In such a case, to develop the LSIs with the same function individually by each of the supply voltage specifications will require enormous design works, which invites an elongated development term and increased production cost. Therefore, the usual practice searches for common grounds as much as possible in the specifications of the circuits that can be designed commonly, thus enhancing the design efficiency.
The inventor has examined the circuit configuration of the LSI that has the same function and conforms to the two types of the external supply voltage specifications. The system that the inventor has examined will be outlined as follows.
FIG. 29 illustrates one example of the supply voltage specifications required for an LSI. The two types of external supply voltages (VDD) to be supplied to the LSI are assumed to be 3.3 V and 2.5 V; and the I/O supply voltages (VDDQ) are assumed to be 3.3 V and 2.5 V. The I/O supply voltages (VDDQ) represent the maximum values of the input signal levels that are inputted to the LSI. The internal supply voltages (VDDI) (supply voltages for the internal circuits) are assumed to be 1.5 V in both specifications.
FIG. 30 illustrates one example of the gate insulating film thickness (TOX) and the minimum processing gate length (Lg) of the MOS transistor that is optimized so as to conform to the above three kinds of supply voltages (3.3 V, 2.5 V, 1.5 V). As the supply voltage applied to the MOS transistor increases, the gate insulating film thickness (TOX) becomes thicker, and the minimum processing gate length (Lg) becomes longer accordingly.
FIG. 31 illustrates one example of the LSI circuit construction conforming to the supply voltage specifications shown in FIG. 29. The LSI (000) is composed of an input circuit (001), step-down circuit (002), internal circuit (101), and output circuit (003). The step-down circuit (002) lowers the external supply voltage (VDD) to the internal supply voltage (VDDI), which is supplied to the internal circuit (101). The input circuit (001) and the output circuit (003) are directly supplied with the input signal (IN) and the I/O supply voltage (VDDQ) that varies depending upon the external supply voltage specifications.
In the foregoing circuit construction, by designing the step-down circuit (002) to bring the internal supply voltage (VDDI) into 1.5 V in either case of the external supply voltage (VDD) being 3.3 V and 2.5 V, the design and manufacturing process of the internal circuit (101) can be unified into two types of LSIs. That is, in either of the LSIs, the internal circuit (101) is supplied only with the supply voltage of 1.5 V, and the internal circuit can be formed with MOS transistors having the withstand voltage of 1.5 V shown in FIG. 30.
On the other hand, the input circuit (001) and the output circuit (003) are formed with MOS transistors having such a withstand voltage that prevents breakdown of the gate insulating film even in case of the I/O supply voltage (VDDQ) being high (3.3 V), and the same circuit is also used in case of the I/O supply voltage (VDDQ) being low (2.5 V). That is, the input circuit (001) and the output circuit (003) are configured with the 3.3 V withstanding MOS transistor having the gate insulating film thickness (TOX)=8 nm and the minimum processing gate length (Lg)=0.4 xcexcm, as shown in FIG. 30, in either case of the LSI of 3.3 V specification and the LSI of 2.5 V specification.
FIG. 32 is a circuit diagram illustrating the above circuit construction in detail, and FIG. 33 illustrates the waveforms of the internal operations in this circuit. The MOS transistors (f01, f02) constituting the input circuit (001) and the MOS transistors (f03 to f10) constituting the output circuit (003) are supplied with the I/O supply voltage (VDDQ) and the input signal (IN) that differ depending on the external supply voltage specifications; therefore, the 3.3 V withstanding MOS transistor is used for these, as mentioned above.
However, if this circuit construction is adopted, the I/O supply voltage (VDDQ) is brought into 2.5 V, in case of the LSI with the specification of the external supply voltage (VDD) being 2.5 V; accordingly, the MOS transistor (005) is supplied with less than 2.5 V across the gate and the source thereof. Accordingly, the current drive capability of the MOS transistors (f01 to f10) is extremely lowered, since these transistors are optimized at 3.3 V, which creates a problem that increases the delay times of the input circuit (001) and the output circuit (003).
FIG. 34 illustrates the second example of the LSI circuit construction conforming to the supply voltage specifications shown in FIG. 29. This example forms inside the LSI (000) the input circuit (001a) and the output circuit (003a) configured with the 3.3 V MOS transistor having the gate insulating film thickness (TOX)=8 nm and the minimum processing gate length (Lg)=0.4 xcexcm, and the input circuit (001b) and the output circuit (003b) configured with the 2.5 V MOS transistor (006) having the gate insulating film thickness (TOX)=6 nm and the minimum processing gate length (Lg)=0.3 xcexcm. Further, when the LSI of 3.3 V specification is manufactured, the wiring (010) of 3.3 V specification is connected in the wiring formation step, and when the LSI of 2.5 V specification is manufactured, the wiring (011) of 2.5 V specification is formed.
When the second circuit construction is adopted, it is possible to avoid the problem of increasing the delay times of the input circuit (001) and the output circuit (003), in the LSI with the specification of the external supply voltage (VDD) being 2.5 V. However, in either of the LSI of 2.5 V specification and the LSI of 3.3 V specification, the size of the input/output circuit becomes double, compared with the first circuit construction, which leads to a problem that increases the chip size and the production cost.
The present invention has been made in view of these circumstances, and it is an object of the invention to provide a system that realizes the high-speed operation of a semiconductor device that conforms to plural supply voltage specifications.
Another object of the invention is to provide a system that reduces the production cost of a semiconductor device conforming to plural supply voltage specifications.
Another object of the invention is to provide a system that shortens the development term of a semiconductor device conforming to plural supply voltage specifications.
The above and other objects and novel features of the invention will become apparent from the descriptions and accompanying drawings of this specification.
In accordance with one aspect of the invention, the semiconductor device includes an input circuit or an output circuit configured with a plurality of first MOS transistors in a first area of a principal plane on a semiconductor substrate, and an internal circuit configured with a plurality of second MOS transistors in a second area of the principal plane on the semiconductor substrate, in which a spacing between a first gate electrode of the first MOS transistors constituting the input circuit or the output circuit and a first contact hole for connecting a wiring to a source region or a drain region of the first MOS transistors is larger than a minimum processing dimension of the spacing between the first gate electrode and the first contact hole, and a spacing between a second gate electrode of the second MOS transistors constituting the internal circuit and a second contact hole for connecting a wiring to a source region or a drain region of the second MOS transistors is equal to a minimum processing dimension of the spacing between the second gate electrode and the second contact hole.
In accordance with another aspect of the invention, the semiconductor device includes an input circuit or an output circuit configured with a plurality of first MOS transistors in a first area of a principal plane on a semiconductor substrate, and an internal circuit configured with a plurality of second MOS transistors in a second area of the principal plane on the semiconductor substrate, in which a spacing between an edge of a first active region where the first MOS transistors constituting the input circuit or the output circuit are formed and a first contact hole for connecting a wiring to a source region or a drain region of the first MOS transistors is larger than a minimum processing dimension of the spacing between the edge of the first active region and the first contact hole, and a spacing between an edge of a second active region where the second MOS transistors constituting the internal circuit are formed and a second contact hole for connecting a wiring to a source region or a drain region of the second MOS transistors is equal to a minimum processing dimension of the spacing between the edge of the second active region and the second contact hole.
In accordance with another aspect of the invention, the method of manufacturing a semiconductor device includes plural processes for forming plural types of MOS transistors to which different power supply voltages are applied in correspondence with external power supply voltages, in which the plural processes are composed of a process common to the plural types of MOS transistors and a process different by each of the plural types of MOS transistors.
In accordance with another aspect of the invention, the method of manufacturing a semiconductor device includes the steps of: forming a first semiconductor device configured with a plurality of first MOS transistors, which includes an input circuit or an output circuit supplied with a first external supply voltage, on a principal plane of a first semiconductor wafer, and forming on the principal plane of a second semiconductor wafer a second semiconductor device configured with a plurality of second MOS transistors, including an input circuit or an output circuit supplied with a second external supply voltage different from the first external supply voltage, which has the same function as the first semiconductor device. The plural processes that form the first MOS transistors on the principal plane of the first semiconductor wafer, and the plural processes that form the second MOS transistors on the principal plane of the second semiconductor wafer are composed of a first process common to the first and second MOS transistors, a second process following the first process, which is different in the first MOS transistors and the second MOS transistors, and a third process following the second process, which is common to the first and second MOS transistors.
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