1. Technical Field
The present disclosure relates to nonvolatile memories and particularly electrically programmable and erasable memories of the FLASH type.
2. Description of the Related Art
The market for electrically programmable and erasable memories on semiconductor wafers is traditionally divided between EEPROM memories and FLASH memories (or FLASH-EEPROM).
EEPROM memories comprise memory cells consisting of one floating gate transistor and one access transistor. FLASH-type memories comprise only one floating gate transistor per memory cell, and have the advantage being highly compact as far as the semiconductor surface occupied is concerned (the number of memory cells per surface unit). On the other hand, the absence of an access transistor involves the provision of positive threshold voltages for both the erased memory cells and the programmed memory cells so as to not create short circuits upon the bit lines. The gate oxides are therefore thick in order to durably maintain the electrical charges trapped in the floating gates, which entails a longer erase time. The erasure of FLASH memory cells is often done by tunnel effect whereas their programming is done by hot electron injection. The time for writing the memory cells is short, for example 5 microseconds, whereas the erase time is long, for example 100 milliseconds. Moreover, hot electron injection programming involves a high programming current, such that the number of memory cells able to be simultaneously programmed is generally limited to one byte.
FLASH memories were thus originally dedicated to mass storage. Various improvements have since been proposed so that they may offer features closer to those of EEPROM memories. Among the improvements that may be cited is a page-erasable FLASH memory, such as that described by U.S. Pat. No. 6,807,103, which is hereby incorporated by reference in its entirety.
These improvements have allowed for the commercialization of page-erasable FLASH memories offering the same apparent functionalities as those of EEPROM memories, but in which certain limitations remain:                a long erase time, which may be cumbersome in certain applications. Indeed, the apparent write time of a byte is determined by the erase time of the page that will receive the byte, the page to be completely erased each time a new byte is to be written within, the other bytes initially present in the page also to be written within; and        a lack of protection against untimely power interruptions during the erasure of a page or the writing of blocks.        
As a result, FLASH memories were initially unable to be used as embedded memories in integrated circuits destined for applications where there is a high risk of a power supply interruption, mainly applications for chip cards or electronic tags, in which the power supplied to the integrated circuit may disappear in the case of a “tearing” (removal of the card from the card reader).
Other improvements to FLASH memories thus aimed to improve the data write time and to protect the data from tearing. To this end, data write methods called “delayed erase” were proposed. According to these methods, the writing of data is only done in erased pages and comprises memory cell write cycles without associated erase cycles. The successive writing of data in erased pages reveals invalid data, filling up more memory space than that which is necessary to store the valid data. As the memory space diminishes, the invalid data are erased to free up memory space (delayed erase). It has generally been proposed to use the write methods with delayed erase in relation with the protection of data against tearing (“tearing proof programming” or “anti-tearing methods”), because the applications requiring a fast data write are generally applications that are sensitive to power supply problems (chip cards).
As an example, the patent application publication No. US2005/0251643 describes a method of writing data protected against tearing (“tearing proof programming”, Cf. paragraph 0008) adapted to FLASH memories. The memory pages are used to store, in addition to the useful data, a logical page address and a counter value. A look-up table allows a logical address to be associated with a physical address (electric address). When a data is to be written in a page, the page contents are copied into a page buffer. The new data is incorporated therein, and the counter value is incremented. The updated page contents are then written into another page, with the same logical address. The initial page is then erased.
U.S. Patent Application Publication No. US2008/0301357, which is incorporated herein by reference in its entirety describes a method of writing data with delayed erase, in which the page erasure is done in “N” steps of partial erasure of short duration, which are applied to pages other than those used to write the data. A step of partial erasure is launched after each step of writing of data, such that after N steps of writing, erased pages are obtained. Then a rotation is performed between the erased pages and the pages containing invalid data, the erased pages being used to write new data while the invalid pages are then submitted to the progressive erasure process. To this end, an auxiliary memory zone comprises a “current” sector comprising erased auxiliary pages usable to write the data, a “save” sector comprising auxiliary pages containing data linked to pages to erase or being erased, a “transfer” sector comprising pages containing data to transfer into the erased pages, and an “unavailable” sector comprising pages being erased.
Additionally, the documents U.S. Patent Application Publication Nos. 2008/082736 and 2005/0144357 disclose a memory comprising sectors of data and zones of management data, including an erase counter, that are placed in a sector overhead zone.
In summary, the above methods of delayed erase may handle entire pages. The pages of data are written in pre-erased material pages, the addresses of which are arbitrary, and a page logical address or “tag” that allows the page to be found is attributed to each page of data. This “tag” is saved with the page data and is “attached” to them, that is to say concatenated and placed in the same physical page. Another feature of the above methods is that each writing of a data in response to a write command involves the reading of all the page data, the insertion of the new data into the page data, then the rewriting of all the updated page data. As a result, a large “consumption” of erased pages occurs, in other words a high “cycling” and therefore an accelerated memory cell wear (the “cycling” representing the number of times that a page has been erased).
USPTO Backgrounds
USPTO Backgrounds