1. Field of the Invention
The present invention relates to an electroluminescent (EL) display and, more particularly, to an EL display where a signal distortion is reduced or prevented by introducing appropriate distortion to a scan waveform of each pixel of a display device to equalize a variation of a kickback voltage.
2. Description of the Related Art
Recently, various flat panel displays with reduced weight and volume have been developed. Such flat panel displays include a Liquid Crystal Display (LCD), a Field Emission Display (FED), a Plasma Display Panel (PDP), an Electroluminescent (EL) display, and the like. These displays address the drawbacks associated with weight and volume of a Cathode Ray Tube (CRT).
Among these, in the EL display using an organic EL device, a fluorescent material and a phosphorescent material are excited using carriers, such as electrons and holes, to display image or picture. Such use of carriers to excite the fluorescent material and the phosphorescent material makes it possible to drive the organic EL device with a low DC voltage and provides an improved response time. Therefore, research on the EL display as a next generation display have recently been accelerated.
Such EL displays can be classified into a passive matrix type and an active matrix type. Of these, in the active matrix type display, a light emitting device is driven by setting a driving device in each pixel, and applying a voltage or current based on the image data of the pixel. A conventional active matrix type EL display is shown in FIG. 1.
FIG. 1 is a block diagram illustrating a conventional EL display.
The data driver 10 is connected to a plurality of data lines D1, D2, D3, . . . , such that it receives data signals from a control unit (not shown) and sends the data to an organic EL panel 40.
Further, the scan driver 20, which includes a shift register 21 that sequentially drives a selection signal and a level shifter 22 that amplifies the amplitude of the selection signal driven by the shift register 21, is connected to each scan line S(n), S(n+1) . . . . Alternatively, depending on the designer's preferences, the configuration of the shift register 21 and the level shifter 22 may be different, and/or the level shifter 22 may be included in the control unit. By way of example, the level shifter 22 may first amplify the selection signal, and then provide it to the shift register 21 for sequential driving.
When a drive control signal is supplied by the control unit (not shown), the data driver 10 sequentially selects a predetermined data line among a plurality of data lines D1, D2, D3, . . . and outputs RGB image signals to the pixels 41 through transistors M1 and M2 (referring to FIG. 2 or FIG. 5) in each pixel. Further, the scan driver 20 sequentially selects a predetermined scan line among a plurality of scan lines S(n), S(n+1) . . . and applies a scan signal Vscan to turn on the switching transistor M1 connected to one of the scan lines S(n), S(n+1) . . . . Here, the shift register 21 of the scan driver 20 selects a first scan line in response to a start signal, and sequentially applies the selection signal based on the subsequent clock signals. In addition, the level shifter 22 amplifies a low-voltage signal, outputted from the shift register 21 or the control unit (not shown), to a high-voltage signal, and thus outputs the high-voltage signal to each scan line.
FIG. 2 is a pixel circuit of the EL display of FIG. 1.
As shown in FIG. 2, a data line transmitting a pixel signal is arranged as a column, and a scan line transmitting a switching signal is arranged as a row. Further, the switching transistor M1 has a gate connected to the scan line, and a source connected to the data line. A driving transistor M2 has a gate connected to a drain of the switching transistor M1 and a source connected to an anode voltage Vdd. An anode of an organic EL device OLED is connected to a drain of the driving transistor M2. The circuit also includes a capacitor Cst connected between the gate of the driving transistor M2 and the anode voltage Vdd.
The operation of the pixel circuit 41, configured as described above, is as follows: first, when an on signal is applied through the scan line S(n), the switching transistor M1 is turned on, transmitting a data voltage transmitted through the data line to the capacitor Cst. Therefore, since the capacitor Cst stores the data voltage, although the scan line is turned off, the driving transistor M2 transmits a current corresponding to a first frame to the organic EL device (OLED) using the voltage charged in the capacitor Cst.
A timing diagram illustrating the foregoing operation is shown in FIG. 3.
The scan voltage Vscan is a selection signal transmitted through the scan line, the data voltage Vdata is a pixel signal transmitted through the data line, and the pixel voltage Vp is a voltage stored in the capacitor Cst.
In the pixel driving circuit of FIG. 2, a parasitic capacitor Cgs is generated between the gate and the drain of the switching transistor M1, and the parasitic capacitor Cgs along with a charging capacitor Cst acts as a total storage charging capacitor.
Hence, the voltage stored in the parasitic capacitor Cgs and the charging capacitor Cst when the scan voltage Vscan is applied through the scan line to turn the switching transistor M1 on, should be maintained when the switching transistor M1 is off. However, as shown in FIG. 3, when the scan voltage Vscan changes from an on voltage to an off voltage (i.e., low-to-high transition of Vscan in FIG. 3), the pixel voltage Vp is increased by a certain voltage, and one of reasons for this increase is the kickback voltage ΔVp. Here, for the Vscan signal, the on voltage is the logic low voltage for turning on the switching transistor M1, and the off voltage is the logic high voltage for turning off the switching transistor M1. The ΔVp is generated by redistribution of the charges charged into the parasitic capacitor Cgs and the charging capacitor Cst. Such redistribution takes place as the voltage is changed at both ends of the parasitic capacitor Cgs when the scan voltage changes from the on voltage to the off voltage.
By way of example, the kickback voltage ΔVp is generated when there is a mismatching of the load impedance between the input side and the output side of the scan driver 20, and the magnitude of the voltage ΔVp depends on the magnitude of the load at both the input side and the output side.
That is, the variation of signal distortion due to the kickback voltage is higher at the pixels near the scan driver than at the pixels separated from the scan driver by some distance. This is because, with the increased number of wiring and devices, an RC delay caused by the internal resistance and capacitance is reduced as the pixel becomes nearer to the scan driver. Therefore, in the conventional organic EL panel, there is a difference in a signal distortion range due to the kickback phenomenon, such that the luminance of the organic EL devices in the organic EL panel is not uniform.
USPTO Backgrounds
USPTO Backgrounds