1. Field of the Invention
The present invention relates to the field of data communications. More particularly, the present invention relates to converting high speed differential serial transmission signals to single-ended CMOS logic circuit level signals.
2. Description of Related Art
It is well-known in the data communications field that for the transmission of high bit rate data signals small differential signals provide a number of advantages. A differential channel provides rejection of common mode noise present between a transmitting and receiving node such as power supply noise. Differential signals can be transmitted on twisted pair cables which are less expensive than coaxial or fiber optic cables and which when shielded offer very good rejection of interference from external noise sources. Using small signal level differential signals on a shielded twisted pair cable reduces EMI emissions, simplifies transmitter design and reduces power dissipation.
One of the most important characteristics of a differential communication channel is that it reduces timing distortion due to mismatched rise and fall times and receiver threshold. Timing distortion must be minimized since in a digital communication system data is encoded in both time and amplitude. FIG. 1(a) illustrates a single-ended system with mismatched rise and fall times and a threshold VT. As can be seen the mismatch in rise and fall times causes duty cycle distortion (Tpulse does not equal T.sub.bc where T.sub.bc is the bit cell width and Tpulse is the received pulse width.) It is very difficult in a single-ended communication system to match the rise and fall times and this mismatch becomes significant when data rates become high (50 Mbaud or more).
Differential systems on the other hand do not suffer duty cycle distortion due to rise and fall time mismatch. As shown in FIG. 1(b), as long as signal A and B have equivalent rise times and equivalent fall times the signal's pulse width is preserved. This type of matching is much more simple to guarantee in an integrated circuit design that has a symmetric layout for the A and B signals. It is also important to note that in a differential receiver the threshold is not set externally as in the single-ended system which was set by the VT reference shown in FIG. 1(a). Instead, the threshold in a differential system is a function of the received signal and therefore tracks with the received signal corresponding to when A=B (the signal crossing point).
Circuits composed of CMOS digital logic generally require signal swings having a range of 5 or 3 volts, usually between +5 volts and 0 volts or +3 to 0 volts. When a CMOS circuit receives a small amplitude differential binary signal, it is necessary to convert the binary differential signal into a single-ended signal amplified to CMOS digital voltage levels usable by the CMOS logic. As data transmission rates increase, it is necessary that the signal conversion circuitry be able to handle ever faster incoming differential signals for conversion to digital levels.
In other technology areas it has been necessary to convert signals from one domain to another domain. U.S. Pat. No. 4,437,171 illustrates circuitry for converting ECL level signals to signals suitable for use by a MOS memory.
USPTO Backgrounds
USPTO Backgrounds