The present invention relates generally to semiconductor devices, and more particularly to reducing parasitic resistance in source and drain contacts in non-planar integrated circuit transistors.
Trigate and finFET devices employ a channel connecting source and drain contact regions structured as a three-dimensional fin. The gate electrode controlling the channel current is applied to three exposed surfaces, i.e., two sides and a top. An insulating spacer layer may be applied to protect the gate electrode wrapped around and over the channel portion of the fin. The exposed source and drain regions of the fin may be metalized for electrical contact with a salicidation process. The thickness of the spacer generally limits the contact surface area available to the source drain region, a condition that becomes increasingly burdensome as device technology scales to smaller dimensions. The spacer conventionally flares at the base of the gate, limiting source/drain contact area and the uniformity of the gate on the fin's sidewalls and top.
Features, elements, and aspects of the invention that are referenced by the same numerals in different figures represent the same, equivalent, or similar features, elements, or aspects, in accordance with one or more embodiments. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
USPTO Backgrounds
USPTO Backgrounds