Integrated circuits are used in many electronic devices. A typical integrated circuit includes a semiconductor substrate including active regions, and one or more interconnect layers formed on the substrate. The adjacent interconnect layers are typically separated by an interlevel dielectric layer. A semiconductor wafer including a plurality of integrated circuit die may be positioned into a plasma deposition chamber to deposit some of the desired layers. The wafer is cut after processing into the discrete integrated circuit die.
Tungsten, tungsten silicide and titanium nitride, for example, are metals that are conventionally deposited on the wafer by chemical vapor deposition (CVD) during manufacturing. These metals may be deposited in a reaction chamber that holds from one to several wafers, and which also supplies an elevated temperature and/or plasma to enhance the deposition. Unfortunately, such metals would also be deposited on the edge and backside of the wafer if these areas were unprotected during CVD. The metals tend to peel and flake and would contaminate other portions of the wafer during subsequent processing steps. Also, any residual metal can be sputtered back onto the surface during subsequent processing steps.
One approach to preventing undesired deposition on the backside and particularly the edge of the wafer is disclosed, for example, in U.S. Pat. No. 5,843,233 to van de Ven et al. and assigned to Novellus Systems, Inc. Novellus also offers the system described in the patent as its minimal overlap exclusion ring (MOER) process. The apparatus includes a chamber for positioning of five wafers therein, a pedestal to support each wafer, and an exclusion ring for each wafer.
The exclusion ring includes an extension which slightly overlaps the front peripheral region of the wafer and defines a restrictive gap or opening therewith. So-called deposition control gas is introduced under the exclusion guard extension and exits through the gap. Orifices may be provided through the extension to further increase uniformity of deposition on the front of the wafer adjacent the edge.
To increase the useable area on the wafer, the deposition is desirably uniform until reaching the edge. For example, for a 200 mm wafer, a 6 mm ring of the wafer was left unusable in the past. More recently, the ring is now desirably reduced to only 4 mm. Many wafers include beveled edges which complicates the mechanics of deposition edge exclusion. In addition, a typical deposition chamber is desirably used for a number of different processes, some with slower deposition rates, and others with faster rates. Unfortunately, to accommodate different processes typically requires compromising flow rates and deposition chemistry to ensure proper edge exclusion. In addition, as the chamber is continually used, deposits also tend to build-up on the surfaces of the exclusion ring. Accordingly, these must be periodically cleaned to ensure adequate performance. Opening the chamber for such cleaning may result in many hours of downtime for the apparatus. Changing the rings to substitute others with different dimensions would also entail significant apparatus downtime, and is therefore impractical.
USPTO Backgrounds
USPTO Backgrounds