The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
Over the course of semiconductor fabrication evolution, different packaging technologies have been proposed and implemented. For example, these packaging technologies may include wire-bonding, flip chip, and wafer-level chip scale package (WL-CSP). The WL-CSP technology (referred hereinafter as WL-CSP for the sake of simplicity) involves a wafer-level packaging scheme and mounts the semiconductor dies directly to a printed circuit board (PCB). Compared to some of the other packaging technologies, WL-CSP offers benefits such as lower costs, shorter cycle time, and small form factor. However, existing WL-CSP implementations may have less flexible circuit routing capabilities.
Therefore, while existing WL-CSP implementations are generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.
USPTO Backgrounds
USPTO Backgrounds