The term “tool” is understood to encompass software used to aid in and automate the design of electronics. The term “start point” is understood to encompass flip-flops (flops) and input ports. The term “end point” is understood to encompass registers and output ports. A system-on-chip (SoC) comprises at least one network-on-chip (NoC). A NoC comprises a set of units the interconnection of which transports transactions between at least one master and at least one slave intellectual property core (IP). The IP cores themselves may be considered components of a NoC. A model of a NoC can be exported as a register transfer level (RTL) language description and in other representations such as SystemC or IP-XACT. Each instantiation of a unit has a configuration and each configuration of an instantiation of a unit has a model. The model can be exported from the tool as one or more RTL language modules, which are synthesized into a netlist of cells. Unit models comprise one or more component models, which in turn may comprise one or more component models and so on. Ultimately, each component model is composed entirely of elementary models such as individual gates and registers, connected by nets, one property of which is an estimated size.
State of the art NoC architectures are designed using a tool with a graphical user interface (GUI). The GUI shows units that comprise the NoC and allows the user to configure the connections between the units, cumulatively known as the topology of the NoC. The prior art configuration process 100 is shown in FIG. 1 and is as follows.
A user configures a NoC (102) using the NoC design tool. The NoC design tool exports a model of the NoC in a RTL language (104). The RTL language model describes the functionality and connectivity of the NoC units. The RTL model includes registers that consist of one or more flops. The RTL model is synthesized by a synthesis tool (106), which is different from a NoC design tool, into a netlist of cells. The synthesis tool reports the cell area of modules within the NoC RTL model. The synthesis tool also estimates the delay time for signal propagation along all logical paths between inputs and flops, between every two flops with a logical connection, and between flops and outputs, as well as fully combinatorial paths between inputs and outputs.
For a more accurate estimate of path delays in the final hardware implementation, place and route (P&R) tool takes the netlist and places each cell within a floorplan of the SoC silicon die connected by wires routed within the floorplan (108). A static timing analysis (STA) tool carefully calculates the delay time for signal propagation along all logical paths between inputs and flops, between every two flops with a logical connection, and between flops and outputs, as well as fully combinatorial paths between inputs and outputs (108).
Both the synthesis and static timing analysis tools produce a timing report showing the path delay through each cell in the netlist. The listed paths are typically sorted in order of the amount of delay, beginning with the longest. Paths with delay longer than a target clock period are known as critical paths. Critical paths prevent the SoC from operating correctly at the clock frequency corresponding to the target clock period. If there are no critical paths then the timing is met and the process is complete. If there are critical paths then the NoC topology is reconfigured (102) in the GUI and the process repeated.
In another case, the listed paths are sorted in order of the amount of delay, beginning with the shortest. Paths with delay shorter than a target hold time period are known as violating a hold time constraint. Paths that violate a hold time constraint prevent the SoC from operating correctly at any clock frequency and can only be corrected by adding logic delay such as combinatorial buffers. If there are no paths violating hold time constraints then the timing is met and the process is complete. If there are paths violating hold time constraints then the NoC topology is reconfigured in the GUI and the process repeated.
USPTO Backgrounds
USPTO Backgrounds