Radar sensors featuring high angular resolution normally rely on large antenna apertures. This can be achieved with the use of a dielectric lens in front of a small number of antenna elements, or with a large number of receiving (RX) elements in a phased array configuration as e.g. Bosch LRR3. Lens-antenna based techniques have the disadvantage of a small angular field-of-view of +10 degrees, making this approach less suitable for short- and middle-range radar applications where a larger field of view is required i.e. larger than ±60° degrees. In the following description the term RX is used to indicate a receiver and the term TX is used to indicate a transmitter, together with their plural forms RXs and TXs, respectively.
The large RX antenna array, on the other hand, leads to a large sensor physical size which is a drawback in many practical circumstances e.g. placement behind the bumper, etc.
It has been shown that the application of Multiple Input Multiple Output (MIMO) techniques that combines a relatively small number of RXs e.g. 4 with a small number of TXs e.g. 4 [Feger-2009 ‘A 77-GHz FMCW MIMO Radar Based on an SiGe Single-Chip Transceiver’, Reinhard Feger et al., IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, MAY 2009, pp. 1020-1035] provides a larger “effective” receiving aperture, effectively the aperture of 16 receiving antennas, without the drawbacks mentioned above, meaning that the field of view is kept relatively large and the physical size is comparable to a small array of 4 RXs. The MIMO technique described above works by sequentially switching the TXs while the RXs acquire and store data, so that a set of measurements for all combinations of TX and RX antennas is obtained after the data acquisition cycle completes [TX1, RX1, RX2, . . . ], [TX2, RX1, RX2, . . . ]. The radar processing is then completed by post-processing the set of measured results for the different TX1, . . . , TXn possibilities.
An alternative technique for MIMO radar signal acquisition and processing is described in US2012/0001791 and it is shown in FIG. 1. In this application the phase of a TX path TX0 is binary toggled from chirp to chirp, whereas the phase of the second TX path TX1 is kept constant from chirp to chirp. The data acquisition process is simultaneous for TX0 and TX1, instead of sequential as in the method proposed by Feger. The phase toggling in path TX0 allows the signal from the two TXs antennas to be separated in subsequent signal processing steps.
Throughout this disclosure, a chirp is considered to be the sweep signal generated by the radar.
In FIG. 2 a generic MIMO radar system is shown. The system comprises a radar IC on the left hand side and a microcontroller/Digital Signal Processing (uC/DSP). The radar IC is able to perform MIMO data acquisition according to the above-mentioned techniques. The radar IC contains three independently-controlled transmitters TX1, . . . , TX3, four receivers RX1, . . . , RX4 and a waveform generator 8 providing for a flexible chirp control. Each receiver includes a 12 bit Successive Approximation (SAR) ADC and a data serializer for transferring data to an external DSP chip for further processing either in real time operation mode, or into a data capturing mode for offline processing.
The interface to the uC/DSP consists of
                four high-speed serial lines (ADC1, . . . , ADC4) containing the ADC data;        an SPI communication bus; and        two additional control lines Window active and Ready INT indicating the state of the data acquisition cycle to the micro-controller.        
The Window active signal and the Ready INT signal are generated by a timing engine 1. Furthermore, the Data Received Via the SPI Communication Bus is Stored in an SPI Register 7.
In FIG. 3, a typical data acquisition cycle is presented. Before the chirp sequence starts, the RXs and TXs are in an Idle state, meaning that the system is in a power-down mode in order to save the power consumption. After starting the chirp sequence, the front-end elements are activated i.e. enabled, using a specific set of control signals values for the TX1, . . . , TXn stages. One may observe that there are two levels of on/off control for the TX sections. It is an enable function to control full-power down of the active circuitry, in addition to an on-off switch that effectively suppresses the output signal when the power amplifiers are in active state. The reason for this double control is to avoid large supply voltage transient states during the data acquisition cycle. Supply voltage disturbances created by the on-off switch are reasonable small because the DC current flowing in the TX sections is kept almost constant.
The signals controlling each TX consist of the state of the on-off switch i.e. 1/0 bits, and the state of the binary phase shifter. In FIG. 3, it is indicated that the states of the TXs sections change for the second chirp in the sequence, and so on until the data acquisition cycle is completed. Typical data acquisition cycles consist of 128, 256, 512, up to 1024 chirps.
In FIG. 3, control parameters for the frequency chirp itself, are shown too. They are the start and stop frequencies, dwell time and settle time parameters, a time allocated for collecting of valid ADC samples Window active, a time for indicating to local oscillator to return to the start frequency, and finally an overall parameter Tchirp indicating the overall time length of each acquisition chirp.
In general, a Frequency Modulated Continuous Wave (FMCW) radar data acquisition cycle in the context of this application consists of a sequence of frequency chirps with precise timing, as depicted in FIG. 3. Additionally, for MIMO data acquisition systems, the settings for the TXs active states and/or the state of the phase shifters in each TX can change from chirp to chirp, as described e.g. in Feger-2009 and US2012/0001791.
Without a dedicated control block within the radar front-end chip, the timing of the frequency chirps as well as chirp-to-chirp changes need to be controlled via SPI transactions from the uC towards the radar IC. This is undesirable, because:                SPI communications are in general not suitable for precise timing of functional operations, because the generation of control strings relies on software routines running inside the micro-controller;        SPI response may have a relatively large latency due to message header overhead,        and        SPI bus activity during communication can disturb sensitive portions of the radar IC during the data acquisition cycle.        
For a precise and reliable data acquisition cycle, it is therefore important that the process of complete acquisition sequence does not depend on SPI communications.
USPTO Backgrounds
USPTO Backgrounds