Memory cells, such as conventional static random access memory (“SRAM”) cells, are susceptible to cosmic radiation, neutrons and alpha particles, among other external factors. Such external factors can lead to a change in state of such SRAM cells. This change in state caused by such external factors is known as a Single Event Upset (“SEU”).
SEUs are becoming more problematic as semiconductor process geometries decrease (“shrink”) and supply voltages for operation of integrated circuit transistors decrease. Thus, failure rate due to SEUs measured per megabit for a unit of time is increasing. Furthermore, the number of megabits per SRAM is also increasing with shrinkage of process geometries. Accordingly, the number of failures for an SRAM semiconductor die per unit of time due to SEUs is on the increase. This increase in SEU susceptibility may lead to a mean time to failure (“MTTF”) rate of less than ten years.
To address the problem of SEUs, others have suggested implementing SRAM cells that are less susceptible to SEUs. However, such SEU hardened SRAM cells either use more area than conventional SRAM cells or are made using unconventional complementary metal-oxide semiconductor (“CMOS”) processing technology.
In programmable logic devices (“PLDs”), such as field programmable gate arrays (“FPGAs”), configuration bits are used to program programmable logic. In conventional uses of FPGAS, configuration logic blocks (“CLBs”) are configured to include lookup tables (“LUTs”) though other configurations, such as shift registers (“SRs”) and random access memories (“RAMs”), are possible. However, configuration bits used for configuring function generators (“FGs”) as SRs or RAMs are a relatively small percentage of the total number of configuration bits used, as conventionally CLBs are configured for LUTs. Unfortunately, memory cells used for configuring conventional FGs as SRs or RAMs cannot be read from and written to at the same time without significant risk of data corruption. Furthermore, FGs conventionally share address lines, and thus heretofore memory cells used for LUTs could not be segmented from memory cells used for SRs or RAMS. Thus, all such memory cells were read only during non-write operation intervals.
Accordingly, it would be desirable and useful to provide means that would facilitate reading configuration bits stored in memory cells during write operations, such as for error checking to determine if an SEU has occurred. More particularly, it would be desirable and useful to provide means for a continuous readback of at least substantially all configuration bits. In a PLD, it would be desirable if such continuous readback were independent and transparent from a user implemented design in a configurable portion of the PLD.
USPTO Backgrounds
USPTO Backgrounds