In general, dynamic random access memory (DRAM) memory cells comprise one cell transistor and one cell capacitor. Thus, data (or charge) stored in the cell capacitor is lost by leakage current after a predetermined amount of time passes. Accordingly, data are repeatedly read from and written to the DRAM cell capacitors before the data stored in the cell capacitors are lost. These operations are referred to as refresh operations.
For example, when the refresh period of major memory cells of a DRAM is 64 ms and the refresh period of minor memory cells of the DRAM is 32 ms, the general refresh period of the DRAM may be set to 32 ms or less. This may result in a lower DRAM yield.
In a DRAM comprising 2048 memory cells each having a refresh period of 64 ms, a memory controller outputs a refresh command to a DRAM core every 31.2 μs. If, however, the refresh period is 32 ms, then the memory controller outputs a refresh command to the DRAM core every 15.6 μs. Accordingly, if the refresh period of a DRAM is determined on the basis of minor memory cells having a generally shorter refresh period, then the DRAM memory controller outputs refresh commands to the DRAM core at a generally higher frequency. This may increase the load on a bus between the memory controller and the DRAM core and may also increase power consumption in the DRAM.
USPTO Backgrounds
USPTO Backgrounds