1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit technology. In particular, the present invention relates to an electrostatic discharge protection circuit having a P-type flash memory cell.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during the handling of semiconductor integrated circuit, IC hereinafter, devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely disrupt its operation.
There are several ESD stress models based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standards models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been proposed. The human-body model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. The military standard models the electrostatic stress produced on an IC device when a human carrying electrostatic charges touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electric charges contacts the lead pins of the IC device The charged device model describes the ESD current generated when an IC already carrying electric charges is grounded while being handled.
However, with the trend toward submicron scale IC fabrication in view, CMOS IC have become more vulnerable to ESD damage due to advanced processes, such as use of a lightly-doped drain ("LDD") structure and clad silicide diffusions. Therefore, lateral silicon-controlled rectifiers (LSCRs) have been utilized as main components of ESD protection circuits for facilitating ESD protection. As an example, R. N. Rountree et al., "A PROCESS-TOLERANT INPUT PROTECTION CIRCUIT FOR ADVANCED CMOS PROCESSES," has been proposed in EOS/ESD Symp. Proc., EOS-10, pp.201-205, 1988.
Referring to FIG. 1, a conventional lateral silicon-controlled rectifier, hereinafter LSCR, is schematically illustrated in a top view. The conventional lateral silicon-controlled rectifier is fabricated in a P-type semiconductor substrate 10 having an N-well 11 formed therein. A P-type doped region 12 and an N-type doped region 13 are formed within the N-well 11 while another N-type doped region 14 and P-type doped region 15 are formed in the P-type semiconductor substrate 10. The P-type doped region 12 is electrically connected with the N-type doped region 13 to be an anode 16 of the LSCR while the N-type doped region 14 and P-type doped region 15 are tied together to be a cathode 17 thereof. A cross-sectional view taken along a line II--II of FIG. 1 is illustrated in FIG. 2.
As shown in FIG. 2, the P-type doped region 12, N-well 11, and P-type semiconductor substrate 10 serve as the emitter, base, and collector, respectively, of a PNP bipolar junction transistor. In addition, the N-well region 11, the P-type semiconductor substrate 10, and the N-type doped region 14 serve as the collector, base, and emitter, respectively, of a NPN bipolar junction transistor.
However, there is one inherent constraining design factor for the LSCR's used in ESD protection circuits for sub-micron semiconductor devices. The required voltage for triggering conventional LSCR's heavily relies upon the junction breakdown between the P-type semiconductor substrate 10 and the N-well 11, being therefore in the range of about 30.about.50 V. Nevertheless, the typical thickness of gate oxide layers in CMOS fabrication processes employing a resolution of 0.6-0.8 microns is about 150-200 angstroms. Taking a dielectric breakdown strength of 10 MV/cm for typical SiO.sub.X material into consideration, the gate oxide layers in these sub-micron CMOS devices would have been destroyed by a voltage of about 15.about.20 V. Even worse, as to 0.5 .mu.m feature size CMOS technology with a gate oxide thickness of 105 angstroms, measurable Flower-Nordheim tunneling through the gate oxide starts at around 7 V and oxide breakdown occurs at about 14.5 V. Therefore, the conventional LSCR's have no effect on ESD protection for sub-micron CMOS IC devices.
Therefore, there is a need to provide an electrostatic discharge protection circuit that is triggered at a voltage lower than the breakdown voltage of gate oxide layers, especially suitable for sub-micron CMOS fabrication, to confirm ESD protection efficacy.
USPTO Backgrounds
USPTO Backgrounds