The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
The scaling down process may lead to fabrication challenges. For example, in certain semiconductor applications, a dummy gate may be formed adjacent to a functional gate. As the semiconductor features continue to get scaled down, the distance between the dummy gate and the functional gate is reduced. Therefore, an electrical voltage applied to the dummy gate may create a leakage path through a gate oxide insulator to the adjacent functional gate, which can cause damage to the functional gate.
Therefore, while existing methods of forming functional gates and dummy gates have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.
USPTO Backgrounds
USPTO Backgrounds