A frequency synthesizer is an electronic system for generating signals having a range of frequencies using the output of a single fixed timebase or oscillator. Frequency synthesizers are found in many modern devices including, but not limited to, radio transceiver apparatus, mobile telephones, radiotelephones, walkie-talkies, CB radios, satellite receivers, GPS systems, etc. Synthesizers commonly utilize a phase-locked loop to control the frequency of a controlled oscillator and thereby produce an output signal having a desired frequency. The frequency of the controlled oscillator is usually established by the voltage at a control input, and hence such a controlled oscillator is known as a voltage controlled oscillator (VCO). The output frequency of a phase-locked loop synthesizer in the locked condition is determined by the loop divide number. In fractional-N (or so-called FRAC-N) frequency synthesizers the loop divide number can have a fractional portion in addition to an integer portion. Fractional-N frequency synthesizers are particularly valued because of their ability to achieve relatively fine frequency resolution and effectively manage the compromise between lock time and sideband noise. These synthesizers dynamically switch between different relatively small integer loop divide values, one at a time, so that on the average a fractional divide number is effectively obtained over a period of time. The number of different integer loop divide values available for selection by this dynamic switching action is typically 2K, where K is a number of digital accumulators within the synthesizer. For example, a synthesizer having two accumulators utilizes a set of four different integer loop divide numbers; a synthesizer having three accumulators utilizes a set of eight different loop divide numbers; etc. These integer divide numbers are typically adjacent integer values, but this is not essential.
Typically, a compromise is made in selecting this set of integer loop divide values. In order to achieve relatively fast lock time and low noise, the integer loop divide values should be relatively small so that the comparison frequency at a phase detector can be correspondingly larger. However, the amount of cycle-to-cycle phase excursion that is produced by a loop divider output and then applied at a phase detector input increases at lower divide values. This phase excursion must not exceed certain bounds. Otherwise, phase detector nonlinearities will cause excessive distortion and degrade spectral purity of the synthesizer. As a result, there is a practical lower limit on the allowable integer loop divide values. For some relatively high frequency applications of fractional-N synthesizers, for example those approaching 1 GHz or more, this does not present a problem. This is because the loop divide number needed to bring such a voltage-controlled oscillator (VCO) frequency down near the frequency of commonly available crystal oscillators (typically between 10 MHz and 30 MHz) is already sufficiently large to prevent excess distortion.
There are, however, applications for fractional-N synthesizers where support for a relatively wide range of VCO frequencies is desired. For example, operation may be needed at VHF frequencies in the 100 MHz range. In addition, operation at UHF or beyond 1 GHz may be required. In order to operate at the lower VCO frequency ranges with suitable crystal oscillators, a reference frequency divider is generally used to reduce the frequency of the reference signal applied to the phase detector (and correspondingly increase the loop divide numbers), and thereby prevent the distortion problem described above. In order to achieve the best compromise in operating performance (lock time, noise, and distortion) over a wide range of VCO frequencies, the reference frequency divider is typically programmable between different allowable integer divide values.
Through extensive simulations, testing and experimentation, Applicants discovered that nonlinear elements within the signal path preceding the reference input port of the phase detector can cause intermodulation between interfering radio frequency (RF) signals (such as the VCO signal or its harmonics) and a desired signal, causing undesired spurious sidebands (also referred to herein as spurs) around the reference signal frequency. The reference frequency divider described above, together with any associated limiting amplifiers or buffers that process the crystal oscillator output signal can produce such intermodulation. If such spurious sidebands are near the reference frequency then they will be very difficult to remove once created, especially if the spurious modulation sidebands are within the synthesizer loop bandwidth, wherein the loop filter would thereby provide negligible attenuation.
It is important to note that these relatively high frequency intermodulation sidebands appearing on the reference signal are distinct from the production of low frequency spurious signals that are produced by the phase detector when it samples and down-converts RF interfering signals, which enter into the phase detector. Prior art techniques propose using dither to reduce such low frequency spurs, which is normally applied in situations where a sampling and/or quantization process produces the spurious tones.
More particularly, known techniques describe the application of dither or jitter to the phase detector input signals to impart a timing jitter on the signal edges, in order to reduce the spurious signals produced by the phase detector. However, when nonlinear elements in the signal path preceding the phase detector have already produced spurious sidebands on the reference signal as described above, Applicants further discovered during their simulations, testing and experimentation that subsequent dither of this corrupted reference signal before it is applied at a phase detector input is ineffective in reducing the spurious outputs of the synthesizer.
Thus, there exists a need for a method and apparatus for reducing spurious signals caused by non-linear elements within the signal path preceding the reference input port of the phase detector.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments. In addition, the description and drawings do not necessarily require the order illustrated. Apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the various embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Thus, it will be appreciated that for simplicity and clarity of illustration, common and well-understood elements that are useful or necessary in a commercially feasible embodiment may not be depicted in order to facilitate a less obstructed view of these various embodiments.
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