1. Field of the Invention
The present invention relates to a method of manufacturing a bonded wafer such as an SOI wafer having a thin BOX layer and a DSB wafer.
2. Discussion of the Background
In contrast to conventional silicon wafers, silicon-on-insulator (SOI) wafers afford the advantages of device isolation, reduced parasitic capacitance between device and substrate, and the ability to form three-dimensional structures. Utilizing these advantages, SOI wafers have been employed in high-speed, low power consumption LSIs. (large scale integration integrated circuit) and the like in recent years.
A conventional SOI wafer is comprised of two wafers bonded through a relatively thick (for example, about 1,500 Angstrom) oxide film. However, with the use of new devices in recent years, demand has been increasing for SOI wafers having thin oxide films and direct silicon bonding (DSB) wafers in which two wafers are directly bonded without an oxide film.
It is known that multiple voids form on the bonding surface when two wafers are directly bonded to manufacture a DSB wafer. To reduce these voids, Japanese Unexamined Patent Publication (KOKAI) No. 2006-156770 or English language family member EP 1 818 971 A1, which are expressly incorporated herein by reference in their entirety, proposes a method in which the two wafers are bonded through a thin oxide film, after which a heat treatment is conducted to remove the interface oxide film.
Normally, a vertical furnace is used to form a BOX oxide film. However, when employing a vertical furnace, treatment for at least several tens of minutes is required to produce an oxide film. Further, in vertical furnaces, the higher the oxidation temperature, the more rapid the rate of growth of the oxide film, making it difficult to control the film thickness. Accordingly, forming the thin oxide films that have been in ever greater demand in recent years with uniform thickness in vertical ovens requires low-temperature processing. However, low-temperature processing presents the risks of the growth of precipitation nuclei in the wafer and excessive precipitation, resulting in the problem of failed lithography and the like in device processing.
USPTO Backgrounds
USPTO Backgrounds