1. Technical Field
The present invention relates generally to Programmable Logic Devices (PLDs) that are programmable through what is commonly known as the Joint Test Action Group (JTAG) port, but otherwise is officially known as the IEEE Standard 1149.1 port. More particularly, the present invention relates to a soft core for a PLD that allows a user to access a Serial Peripheral Interface (SPI) Programmable Read Only Memory (PROM).
2. Related Art
Programmable Logic Devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. PLDs are typically used on a Printed Circuit Board (PCB) to enable programming or instantiating various components on the PCB. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
A configuration memory internal to a PLD is typically programmed through a PLD's JTAG port. JTAG is a four-wire interface primarily used for system testing and debugging, but the JTAG interface is also commonly used as a programming interface for Field Programmable Gate Arrays (FPGAs), Complex PLDs (CPLDs), and some microcontrollers, processors, and digital signal processors (DSPs.). Two defining specifications for JTAG are IEEE 1149.1 and IEEE 1532. The “JTAG Port” is commonly referred to as the JTAG or 1149.1 test access port, or “TAP.” The IEEE 1149.1 is the evolutionary standard. The IEEE 1532 is based on the IEEE 1149.1. For convenience further reference to such a port herein will be referred to as “JTAG Port,” although it is understood that this is intended to reference JTAG, TAP, IEEE 1149.1, IEEE 1532 or similar port structures.
A PLD such as an FPGA may be coupled to a Serial Peripheral Interface Programmable Read Only Memory (SPI PROM). The SPI PROM is a nonvolatile memory chip in which the content is created by a user rather than by the manufacturer of the chip. In order for a programming host device external to the FPGA to work with the SPI PROM, SPI ports would also have to be connected with the FPGA and SPI software used to access the SPI PROM. This would mean adding four pins to such items as programmer sockets.
It would be desirable to provide a process by which a user can use JTAG software to access an SPI PROM associated with an FPGA via the already existing JTAG ports of the FPGA.
USPTO Backgrounds
USPTO Backgrounds