1. Field of the Invention
The present invention relates in general to a sense amplifier for use in a semiconductor memory device, and more particularly to a high-speed sense amplifier which is capable of minimizing an occupied area and power consumption and performing data amplification at a high speed.
2. Description of the Prior Art
Generally, a semiconductor memory device such as a dynamic random access memory (referred to hereinafter as DRAM) comprises a plurality of memory cells, each of which includes one transistor and one capacitor. The DRAM has been highly integrated so that it can have a capacity from 256 megabits up to 1 gigabit or more. The high integration of the semiconductor memory device results in limitations in occupied areas of the memory cells and the associated peripheral circuits and increase in capacities and resistances of bit and bus lines.
It is common to use a supply voltage to drive the memory cells and the associated peripheral circuits in the DRAM. The Supply voltage is on a gradually reduced trend as a voltage used in most of information communication equipments is reduced. The reduction of the supply voltage to the DRAM results in reduction in charge storage amounts in the capacitors of the memory cells and in charge transfer amounts from the bit and bus lines. For this reason, data accessed in the DRAM becomes more sensitive to a noise effect. Because of the high integration, the DRAM is required to access the data at a high speed.
A sense amplifier is generally connected to the bit line or the bus line of the semiconductor memory device to sense and amplify the data on the bit line or the bus line. Because of the high integration, the supply voltage reduction and the high-speed operation of the semiconductor memory device, the sense amplifier must be designed to meet the following several factors.
First, the sense amplifier must have a high data sense margin to secure reliability.
Second, the sense amplifier must sense and amplify the data at the high speed suitably to the high-speed operation of the semiconductor memory device.
Third, the sense amplifier must have such a minimized, occupied area that it can be arranged according to a pitch of the bit line.
Finally, the sense amplifier must have a simple control signal related to its operation.
Generally, sense amplifiers designed in consideration of the above factors my be classified into two types, one for sensing and amplifying current on the bit line and the other for sensing and amplifying a voltage on the bit line.
The sense amplifier of the current difference sense type is mainly used in a read only memory (referred to hereinafter as ROM), whereas the sense amplifier of the voltage difference sense type is mainly used in a random access memory (referred to hereinafter as RAM) such as the DRAM. The DRAM has employed the sense amplifier of the current difference sense type beyond 64 megabits, too, because of the supply voltage reduction and transistor's current driving capability.
However, the sense amplifier of the voltage difference sense type is desirable in that it is simple in construction, but has the disadvantage that it senses and amplifies the data at a very low speed. The sense amplifier of the current difference sense type senses and amplifies the data at a relatively high speed as compared with the sense amplifier of the voltage difference sense type. However, the sense amplifier of the current difference sense type requires separate write and read data bus lines, resulting in complexity in a layout of the semiconductor memory device.
Such problems with the sense amplifier of the voltage difference sense type and the sense amplifier of the current difference sense type will hereinafter be described in detail with reference to FIGS. 1 to 3.
Referring to FIG. 1, there is shown a circuit diagram of a DRAM to which a conventional voltage difference sense type-sense amplifier is applied. As shown in this drawing, the DRAM comprises a bit line sense amplifier 11 which includes two PMOS transistors P1 and P2 cross coupled between true and complementary bit lines BL and /BL. The bit line sense amplifier 11 also includes two NMOS transistors N1 and N2 cross coupled between the true and complementary bit lines BL and /BL in a similar manner to the PMOS transistors P1 and P2.
The operation of the DRAM with the above-mentioned construction will hereinafter be described with reference to FIG. 2 which is a timing diagram illustrating operating states of the components in FIG. 1.
First, when a precharge control signal PC is high in logic, half a supply voltage, HVcc, is precharged on the true and complementary bit lines BL and /BL and true and complementary data bus lines DB and /DB. The precharge operation of the true and complementary bit lines BL and /BL is performed by three NMOS transistors N5-N7.
In the case where a bootstrapped high voltage Vpp is transferred to a word line WLi selected by a row decoder (not shown) under the condition that the precharge control signal PC is disabled to low in logic, a voltage charged on a first cell capacitor C1 is supplied to the true bit line BL through an NMOS transistor N3. As a result, a little voltage difference is generated between the true and complementary bit lines BL and /BL.
The bit line sense amplifier 11 is operated when first and second amplification control signals SAP and SAN have a supply voltage Vcc and a ground voltage GND, respectively. As being operated, the bit line sense amplifier 11 allows true and complementary data on the true and complementary bit lines BL and /BL to have the supply voltage Vcc and the ground voltage GND, respectively.
The true and complementary data on the true and complementary bit lines BL and /BL amplified by the bit line sense amplifier 11 are transferred to the true and complementary data bus lines DB and /DB through NMOS transistors N8 and N9, respectively. The NMOS transistors N8 and N9 are turned on when a column transfer control signal Yj goes high in logic by a column decoder (not shown). As being turned on, the NMOS transistors N8 and N9 form transfer paths of the true and complementary data from the true and complementary bit lines BL and /BL to the true and complementary data bus lines DB and /DB, respectively.
The true and complementary data on the true and complementary data bus lines DL and /DL are amplified by a data bus line sense amplifier (not shown) and then transferred to a data output stage.
Referring to FIG. 3, there is shown a circuit diagram of a DRAM to which a conventional current difference sense type-sense amplifier is applied. As shown in this drawing, the DRAM comprises the same memory cells and bit line precharge circuit as those of the DRAM in FIG. 1. The DRAM in FIG. 3 also comprises a bit line sense amplifier 12 which is the same as the bit line sense amplifier 11 in FIG. 1. Further, the DRAM in FIG. 3 comprises true and complementary write bus lines WDB and /WDB fox inputting true and complementary write data, respectively, and true and complementary read bus lines RDB and /RDB fox outputting true and complementary read data, respectively.
The DRAM in FIG. 3 further comprises two NMOS transistors N10 and N11 being turned on when a read select signal YRj is high in logic. As being turned on, the NMOS transistors N10 and N11 connect the true and complementary read bus lines RDB and /RDB to NMOS transistors N12 and N13, respectively: The NMOS transistor N12 is driven in response to the true data on the true bit line BL to open/close a current path between the NMOS transistor N10 and a ground voltage source GND. The NMOS transistor N13 is driven in response to the complementary data on the complementary bit line BL to open/close a current path between the NMOS transistor N11 and the ground voltage source GND. The two NMOS transistors N12 and N13 function to amplify currents of the true and complementary data on the true and complementary bit lines BL and /BL.
The true and complementary write bus lines WDB and /WDB are selectively connected to the true and complementary bit lines BL and /BL by NMOS transistors N14 and N15, respectively. The NMOS transistor N14 is turned on when a write select signal YWj is high in logic. As being ruined on, the NMOS transistor N14 transfers the true write data on the true write bus line WDB to the true bit line BL. The NMOS transistor N15 is turned on when the write select signal YWj is high in logic. As being turned on, the NMOS transistor N15 transfers the complementary write data on the complementary write bus line /WDB to the complementary bit line /BL.
In the DRAM in FIG. 3, the bit line sense amplifier 12 and the two NMOS transistors N12 and N13 for current amplification are connected between the bit lines and the data bus lines so that they can be driven at the same time that the word line is selected. For this reason, the sense amplifier of the current difference sense type can sense and amplify the data at a relatively high speed as compared with the sense amplifier of the voltage difference sense type in FIG. 1.
However, the above-mentioned conventional sense amplifier of the current difference sense type requires the two bus lines for data input/output and the associated drive circuit, resulting in complexity in a layout of the semiconductor memory device.
USPTO Backgrounds
USPTO Backgrounds