This invention relates generally to field-effect transistors (FET's), and, more particularly, to field-effect transistors capable of operation at extremely high frequencies, as high as 300 gigahertz (GHz) or higher. Since the wavelength at these frequencies is one millimeter (mm) or less, such devices are occasionally referred to as milimeter-wave devices. High-frequency transistors of this type may be usefully incorporated into monolithic circuits, either digital or analog, operating at millimeter and shorter wavelengths. Discrete transistor devices of the same type may be employed as amplifiers and oscullators, as well as in mixers, frequency multipliers and so forth.
A field-effect transistor (FET) is a three-terminal amplifying or switching semiconductor device in which charge carriers flow along an active channel region between a source terminal and a drain terminal. When a bias voltage is applied to a gate terminal adjacent to the channel, a carrier depletion region is formed in the channel and the current flow is correspondingly inhibited. In a conventional FET, the source and drain terminals make contact with source and drain semiconductor regions of the same conductivity type, and the active channel takes the form of a planar layer extending between the source and drain regions. The gate terminal makes contact with the channel at a point between the source and the drain, and usually on thge same face of the device as the source and drain terminals.
The performance of such a conventional FET at high frequencies is limited principally by the transconductance of the device, the source resistance, the source inductance, and by other circuit "parasitics", that is by internal impendances associated with the transistor. Various attempts have been made to design field-effect transistors that reduce parasitic impendances and thereby increase the frequency of operation. For example David R. Decker has proposed in his U.S. Pat. No. 4,141,021, that the gate and the source be positioned on opposite faces of the channel. If electrical contact is made with the source from the face opposite the gate, the inherent source resistance and inductance are significantly reduced. However, other parasitics are still present, and the incremental transconductance per unit width of the device is still relatively low.
Other prior patents have also suggested the use of a source located on the opposite face with respect to a gate. For example, U.S. Pat. No. 4,249,190 to Cho includes a floating gate between the source and gate. U.S. Pat. No. 4,129,879 to Tantraporn and U.S. Pat. No. 4,236,166 to Cho et al. have the source and drain on opposite faces and the gate buried between the faces in a position intermediate the source and drain. Finally, Nelson, in U.S. Pat. No. 2,985,805, suggests the use of a gate on the opposite face of the device with respect to the source and drain terminals.
However, all of the prior art devices are still limited in their performance at high frequencies by a relatively low incremental transconductance per unit width, and by the presence of significant parasitic impedences. The present invention overcomes these disabvantages.
USPTO Backgrounds
USPTO Backgrounds