Traditional MOS transistors in semiconductor devices utilize a gate electrode formed over a semiconductor substrate and separated from the substrate by a thin gate dielectric layer. Source and drain electrodes of the transistor are formed by implanting a high dose of impurity atoms into the substrate on each side of the gate electrode and subsequently contacting the implanted regions with a conductive layer which is electrically isolated from the gate electrode. While these traditional MOS transistors found much success in the semiconductor industry, device limitations became apparent as transistor size was reduced. In particular, high electric fields in the substrate often caused undesirable hot carrier injection into the gate dielectric layer. Trapped charge in the dielectric layer as a result of hot carrier injection will negatively impact a transistor's electrical characteristics, particularly over an extended period of time.
To overcome some of the problems associated with hot carrier injection, many semiconductor manufacturers started to form MOS transistors with LDD (lightly doped drain) regions. One way of fabricating LDD MOS transistors is to form a gate electrode over a semiconductor substrate, where the gate electrode and substrate are separated by a thin gate dielectric layer. A low dose of impurity atoms is implanted in the substrate on each side of the gate electrode, forming two LDD regions. Sidewall spacers are formed along sides of the gate electrode to offset a high dose implant. The high dose implant forms source and drain electrodes of the transistor in the substrate such that the source and drain are offset from the gate by a distance approximately equal to the width of the sidewall spacer. In having the source and drain offset from the gate and in having the LDD regions formed in the substrate, the depletion distance (the width of the depletion layer between the source or the drain and the channel) is increased, thereby lowering the electric field in the portion of the substrate between the two LDD regions, also known as the channel region. A decrease in the lateral electric field in the channel region suppresses hot carrier effects and also reduces current in the substrate, thus LDD MOS transistors were considered an improvement over the traditional MOS transistors described earlier. LDD MOS transistors, however, have a disadvantage in that the LDD regions create an increase in source-drain series resistance in the transistor in comparison to traditional MOS transistors. An increase in series resistance is caused by trapped charge at an interface between an LDD region and a dielectric sidewall spacer, resulting in depleted LDD regions.
Another known structure, an ITLDD (inverse-T LDD) MOS transistor, provides lower electric fields in the channel region and lower substrate current in comparison to traditional MOS transistors. Furthermore, ITLDD transistors have reduced series resistance in comparison to other LDD transistors. ITLDD transistors utilize an inverted T-shaped gate electrode formed over a semiconductor substrate. LDD regions are formed in the substrate beneath the wings or shelves of the T-shaped gate. Source and drain electrodes are formed by a high dose implant of impurity atoms into the substrate and are aligned to the shelf edges. Because the LDD regions are beneath the shelf portions of the gate electrode, as opposed to being aligned to gate edges, the gate electrode can modulate any trapped charge in the LDD regions to prevent depletion, thereby minimizing source-drain series resistance. ITLDD transistors, however, have a significant disadvantage with respect to transistor size. The shape of an ITLDD gate electrode necessitates a gate length which is larger than a channel length in the substrate. In an industry which is continually driven to reduce device size, it is important to minimize the size of transistors used in semiconductor devices. ITLDD structures are, therefore, unfavorable since use of ITLDD transistors is in a direction which is opposite that of demand.
A need, therefore, exists for an improved semiconductor device, and more particularly for an improved semiconductor device having MOS transistors and process for making the same which provides a low lateral electric field in a channel region of the transistor, which provides low substrate current, and which occupies a minimal amount of space in the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds