1. Field of the Invention
This invention relates to the fabrication of integrated circuits and, more particularly, to techniques for fabricating a high-resolution, composite silicide-on-polysilicon structure in a metal-oxide-semiconductor (MOS) device and to devices made utilizing such techniques.
2. Art Background
It is known to utilize a refractory metal silicide on polysilicon to achieve a high conductivity gate-level metallization for MOS devices. Specific examples of such silicide-on-polysilicon composite structures are described in U.S. Pat. No. 4,276,557 issued to Levinstein et al on June 30, 1981. These examples include a tantalum silicide-on-polysilicon structure formed by plasma etching tantalum silicide and polysilicon in a plasma of CF.sub.4 and O.sub.2, which plasma produces a generally isotropic etching of the tantalum silicide and polysilicon. Additional details concerning the use of tantalum silicide-on-polysilicon composites in MOS devices are contained in an article by Murarka et al entitled "Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects," IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 4, August 1980, pages 474-482.
A tantalum silicide-on-polysilicon structure is a particularly attractive composite for use in very-large-scale-integrated (VLSI) MOS devices to form, for example, high conductivity, high resolution gate electrodes. The width of these high resolution gate electrodes is typically 2 micrometers (.mu.m) or smaller. To produce such small features in a composite layer of tantalum silicide-on-polysilicon (which composite layer is typically 1 .mu.m or less in thickness) requires, for example, methods for anisotropically patterning layers of tantalum silicide and polysilicon, i.e., methods wherein the maximum horizontal undercutting produced during the patterning is less than about one-quarter of the total vertical etch depth. Such anisotropic patterning is desirable to prevent the composite layer of material from being entirely etched away laterally while the material is being etched vertically through its thickness. Accordingly, efforts have been directed at trying to devise anisotropic etching processes, including reactive ion etching processes, for patterning such layers. Heretofore, however, known efforts to devise an effective anisotropic etching process for tantalum silicide-on-polysilicon useful for defining high-resolution features in VLSI devices have not been successful. Moreover, no other methods for producing an anisotropically patterned, composite layer of tantalum slicide-on-polysilicon, other than the methods which attempt to directly, anisotropically etch tantalum silicide and polysilicon, have been available or have, until now, been developed.
USPTO Backgrounds
USPTO Backgrounds