The present invention relates to a logic simulation method, and more specifically to a program logic array (PLA) simulation method for minimizing the required data volume used for PLA logical simulation, thus improving the efficiency of a simulation process.
A PLA is a digital circuit module for obtaining as much various output data as desired by a user according to the combination of numerous input data.
FIG. 1 shows an explanatory view of a 4-input-to-2-output PLA. By applying input data (a0, a1, a2, and a3) through a number of pins, output data (b0 and b1) are obtained from output pins according to the combination of the values of the input data.
The relationship between the input data array and the output data array can be shown in a table referred to as "PLA data" (FIG. 1B). In the PLA data, for example, when the values in the input data array (a0, a1, a2, a3) are (0, 0, 0, 0), the resultant output (1, 0) is obtained in the output data array (b0, b1). Or, for example, when the values in the input data array are (0, 0, 0, 1), the resultant output is (1, 1). Thus, output values are determined by the combination of data input to an input data array. Each PLA module has its own PLA data.
Ordinarily, in the logic simulation of a circuit, the above described PLA data are used to simulate a PLA module. That is, an output value is obtained by retrieving PLA data from each PLA module corresponding to design input data applied to a PLA module, then identifying the same input data array therein as that of design input data, thus obtaining the output corresponding to the input data array as the output value of the PLA module.
However, in the prior art technology, there is a problem in that the simulation speed slows down when PLA data are prepared on a large scale.
The scale of PLA data grows exponentially larger with the increase of the number of input data arrays. That is, when the number of input data arrays is n, the amount of PLA data is 2.sup.n. In the prior art technology, all PLA data are retrieved to find equivalent data in design input data and PLA data where values in the respective input data arrays match. Therefore, there can be a large number of input data arrays and large amounts of PLA data, thus increasing the time needed to retrieve PLA data which also reduces simulation speed.
There is another problem in that a large volume of PLA data used for the simulation process occupies greater amounts of memory capacity, thus limiting analysis of the circuit to be used for the simulation to a smaller scale since the available data volume in a circuit's simulation process is not infinitive, but limited.
USPTO Backgrounds
USPTO Backgrounds