1. Field of the Invention
The present invention relates to a stacked electronic component constituted by stacking a plurality of electronic components, and a manufacturing method thereof.
2. Description of the Related Art
Recently, to realize a miniaturization and a high-density mounting, and so on, of semiconductor devices, a stacked-type multi chip package in which a plurality of semiconductor elements (semiconductor chip) are stacked and sealed in one package is put into practical use. In the stacked-type multi chip package, the plurality of semiconductor elements are stacked sequentially on a circuit board via an adhesive such as a die attach material. Electrode pads of the respective semiconductor elements are electrically connected to electrode portions of the circuit board via bonding wires. Such a stacked structure is packaged with a sealing resin, and thereby, the stacked-type multi chip package is constituted.
In the stacked-type multi chip package as stated above, when the semiconductor element at an upper side is smaller than the semiconductor element at a lower side, the semiconductor element at the upper side does not interfere with the bonding wire of the semiconductor element at the lower side. However, in such a structure, the applicable semiconductor element is largely restricted. Therefore, it is proceeding that an applicable scope of the stacked-type multi chip package is spread to the semiconductor elements of the same shape, or further to the structure in which a larger semiconductor element is stacked at the upper side than that of the lower side (for example, refer to Japanese Patent Laid-open Application No. 2001-217384).
At this time, when the same shaped semiconductor element or a large shaped semiconductor element is stacked at the upper side compared to the lower side, the bonding wire of the semiconductor element at the lower side may be in contact with the semiconductor element at the upper side. Herewith, it becomes important to prevent occurrences of an insulation failure, a short circuiting, and so on, caused by the contact of the bonding wire. Consequently, a spacer in which a thickness is set so that a lower surface of the semiconductor element at the upper side is to be higher than a height of the bonding wire connected to the semiconductor element at the lower side, is disposed between the upper and lower semiconductor elements (for example, refer to Japanese Patent Application Laid-open No. 2003-179200, Japanese Patent Laid-open Application No. 2003-218316).
However, a usage of such a thick spacer disturbs to make a package (semiconductor device) thinner. Besides, it is considered to give a spacer function to an adhesive layer in itself between the semiconductor elements, but in this case, the package is disturbed to be thinner. It is suggested that an insulating layer is formed at the lower surface side of the semiconductor element at the upper side, and thereby, the occurrences of the insulation failure, the short circuiting, and so on, can be suppressed when the bonding wire of the semiconductor element at the lower side is in contact with the semiconductor element at the upper side (for example, refer to Japanese Patent Laid-open Application No. Hei. 8-288455 and Japanese Patent Laid-open Application No. 2002-222913).
In Japanese Patent Laid-open Application No. Hei. 8-288455, a structure in which an insulating resin layer and a fixing resin layer are sequentially formed on the semiconductor element at the lower side, and thereafter, the semiconductor element at the upper side is disposed and fixed, is described. In Japanese Patent Laid-open Application No. 2002-222913, a structure in which an insulating layer composed of a polyimide resin and an adhesive layer composed of an epoxy resin are stacked into a sheet, the sheet is bonded to a rear surface of the semiconductor element at the upper side, and the semiconductor element at the upper side is adhered on the semiconductor element at the lower side by using the adhesive layer of the sheet, is described. An application of this insulating layer shows an effect for the suppression of the insulation failure, the short circuiting, and so on. However, there is an objection that a peeling off is easy to occur between the stacked semiconductor elements caused by, for example, a difference of thermal expansion coefficient between the insulating layer composed of a polyimide resin and the adhesive layer composed of an epoxy resin.
Further, when a larger semiconductor element is stacked at the upper side than that of the lower side, the semiconductor element at the upper side is disposed protruding from the semiconductor element at the lower side, and therefore, below the protruding portion becomes to be in a hollow state. Besides, when the semiconductor elements of the same shape are stacked, the position of the semiconductor element at the upper side is offset, a part thereof becomes to be protruded from the semiconductor element at the lower side. If a wire bonding is performed to the semiconductor element having such protruding portion, a deflection occurs to the semiconductor element by a loading at that time. Such the deflection may be a cause of occurrences of a crack, and so on, of the semiconductor element, and a cause for a connection failure of the bonding wire. Besides, a reliability at a wire connection portion may be deteriorated by diffusing an ultrasonic output at the bonding time, into the hollow portion below the protruding portion.
Incidentally, in the above-mentioned Japanese Patent Laid-open Application No. 2001-217384, there is described the stacked-type semiconductor device in which the semiconductor element at the lower side is mounted on a substrate, then it is resin sealed, and on this resin sealed portion, the semiconductor element at the upper side is mounted, in a structure that a larger semiconductor element than that of the lower side is stacked at the upper side. According to this structure, the resin sealing portion is existing under the semiconductor element at the upper side, and therefore, a bonding failure, the crack of the semiconductor element, and so on, can be prevented, but on the other hand, it is required to perform a resin sealing process after mounting the respective semiconductor elements, and therefore, there is the objections that the number of manufacturing processes or a manufacturing cost is increasing. Further, the respective resin sealing portions becomes to be disturbing factors to make the stacked-type semiconductor device thin or small.
As stated above, in the semiconductor device applying a conventional stacked-type multi chip package structure, the insulating layer provided at the lower surface side of the semiconductor element at the upper side shows an effect for suppressing the insulation failure, the short circuiting, and so on, but it causes the peeling between the elements resulting from the difference of the thermal expansion coefficient between the insulating layer and the adhesive layer, the increase of the manufacturing cost, and soon. Further, when a larger semiconductor element, and so on, is stacked at the upper side than that of the lower side, a part of the semiconductor element at the upper side protrudes from the semiconductor element at the lower side, and below the protruding portion is inevitable to be in the hollow state. The stacked structure with the protruding portion has problems that the crack of the semiconductor element, the connection failure of the wire, and so on, are easy to occur. These problems occur for a stacked-type electronic component in which various electronic components are stacked and packaged as well as for the semiconductor device in which the plural semiconductor elements are stacked.
USPTO Backgrounds
USPTO Backgrounds