1. Field of the Invention
The invention relates to an integrated circuit device, more particularly to an integrated circuit device with a built-in detecting circuit for detecting maximum memory access time of an embedded memory.
2. Description of the Related Art
In view of recent advancements in the field of semiconductor fabrication technology, system-on-a-chip (SoC) applications are growing at a rapid pace. As a matter of fact, SoC devices are commonly found in many portable applications, such as personal digital assistants, mobile telephones, and even in multi-media products, such as digital cameras, computer games, etc. An SoC device contains millions of logic gates built into a single chip, and includes a processor core, such as a central processing unit or a digital signal processor, an embedded memory, such as a DRAM, SRAM, or flash memory, and an analog core, such as a phase-locked loop, operational amplifiers, etc. The embedded memory, which is used for storing data and instructions, occupies the largest area in SoC devices.
Since memory access time is an important factor commonly considered when determining the quality and price of a product, as to how memory access time can be measured quickly and accurately is an important topic in the industry.
U.S. Pat. No. 6,424,583 discloses a system for measuring access time of a memory that forms part of an integrated circuit chip. In the proposed system, a built-in self-test (BIST) controller and a separate measurement circuit are applied to determine the maximum time period for accessing data stored in an embedded integrated circuit memory. The BIST controller includes a finite state controller for operating state control, a pattern generator for generating a patterned stimulus to be applied to the memory, and a comparator for comparing the stimulus response of the memory to a reference response. The measurement circuit includes logic circuits that operate on data read from the memory, and time delay elements that introduce time delays in the data prior to delivery to the logic circuits.
The aforesaid conventional system is disadvantageous in that, while the built-in measurement circuit is capable of measuring the access time of each addressable location of the embedded memory, external automated test equipment is still needed to determine the maximum memory access time of the embedded memory. Accordingly, since the access time data of each memory location is sent to the external automated test equipment, time delay elements are necessary in the measurement circuit for introducing time delays to the access time data in order to enable measurement of the data by the external automated test equipment. There is also a need for additional circuitry, such as a ring oscillator, to determine the exact amount of the time delays introduced by the delay elements.
USPTO Backgrounds
USPTO Backgrounds