Research and development efforts are made for semiconductor memory devices with high integration density. One of the approaches to increase the integration density is to miniaturize each memory cell to reduce the occupation area. However, a problem is encountered in reduction in production yield due to , for example, lattice defects. The higher integration density the semiconductor memory device has, the more memory cells each lattice defect influences. Moreover, the semiconductor memory device with higher integration density is more sensitive to irregulation of process parameters. Then, a rescue is required for enhancement of production yield. One of the rescue preparations is to provide redundant memory cells which are replaceable with a memory cell group including a defect memory cell. This rescue preparation is so effective that the redundant memory cells are widely applied to the semiconductor memory devices.
In a rewritable/erasable programmable read only memory device ( which is frequently abbreviated as "EPROM "), defective bit lines occupy a substantial part of troubles as well as defective memory cells and defective word lines, so that several redundant memory cell groups respectively accompanied by bit lines are incorporated in the rewritable/erasable programmable read only memory devices for rescuing a considerable part of them from such troubles. This arrangement is hereinunder referred to as "bit-line redundancy ", and, on the other hand, a plurality of redundant memory cell groups respectively accompanied by word lines are referred to as word-line redundancy. However, the bit-line redundancy is relatively complex in circuit arrangement with respect to the word-line redundancy, so that the word-line redundancy is widely applied to the semiconductor memory device rather than the bit-line redundancy. However, the word-line redundancy is less advantageous over the bit-line redundancy in read-out time, because the bit-line redundancy is usually accompanied by sense amplifiers and write-in circuits and, accordingly, no time delay due to replacement takes place in the read-out operation. Then, there is a trade-off between the complexity and the read-out time.
A typical example of the rewritable/erasable programmable memory device with the bit-line redundancy is illustrated in FIG. 1 of the drawings. The rewritable/erasable programmable read only memory device largely comprises a plurality of memory cell arrays 1 to 2 each provided with memory cells arranged in rows and columns and a redundant memory cell array 3 arranged in rows and columns. Each of the memory cells is capable of storing a data bit of logic "1" or "0" level, and a plurality of memory cell columns are replaced with the redundant memory cell columns if necessary. Namely, when defective memory cells are detected during a diagnostic operation, the memory cell columns including the defective memory cells as a whole are replaced with the same number of the redundant memory cell columns and, then, data bits are written into or read out from the redundant memory cells instead of the replaced memory cells.
The memory cells or the redundant memory cells in each row is coupled to each word line (not shown), and each of bit lines 4, 5 and 6 is shared by the memory cells or the redundant memory cells. Though not shown in the drawings, a row address decoder circuit (not shown) is responsive to a row address signal and activates one of the word lines for specifying a row address assigned to the memory cells and the redundant memory cells. Each of the memory cell arrays 1 to 2 is coupled to a column selecting circuit 7 or 8 which selects a bit line from the bit lines 5 or 6 to provide a conduction path between the selected bit line and a write-in circuit 9 or 10 or a sense amplifier circuit 11 or 12. The redundant memory cell array 3 also is accompanied by a column selecting circuit 13 to transfer a data bit between a selected bit line and a write-in circuit 14 and a sense amplifier circuit 15.
When the memory cell columns are replaced with the redundant memory cell columns, the replacement is memorized into a non-volatile memory cell circuit 16 as a replacing information. The non-volatile memory cell circuit 16 provides the replacing information to a control circuit 17 which compares the replacing information with an address information represented by the address signal. If the address information specifies a memory cell column including at least one of the defective memory cells, the control circuit 17 produces a multi-bit control signal.
The rewritable/erasable programmable read only memory device further comprises a plurality of input data buffer circuits 18 to 19 associated with input data distributing circuits 20 to 21, respectively, and output data buffer circuits 22 to 23 respectively associated with output data selecting circuits 24 to 25. Each of the input data buffer circuits 18 to 19 is paired with each of the output data buffer circuits 22 to 23 to form a combination circuit which is coupled to each of input/output data terminal 26 to 27.
In a write-in operation, a row address signal and a column address signal are supplied to the rewritable/erasable programmable read only memory device in succession. The row address decoder circuit (not shown) activates one of the word lines on the basis of the row address signal. Each of the column selecting circuits 7 to 8 provides the conduction path between one of the memory cell columns and the write-in circuit 9 or 10 specified by the column address signal, and the control circuit 17 compares the address information with the accessed column address specified by the column address signal. If the memory cell column specified by the column address signal is replaced with one of the redundant memory cell columns, the multi-bit control signal is supplied from the control circuit 17 to the input data distributing circuits 20 to 21 to cause one of the input data distributing circuits 20 to 21 to provide a conduction path to the write-in circuit 14 instead of a conduction path to the write-in circuit 9 or 10 associated with the memory cell array with the defective memory cell or cells. In this situation, an input data bit supplied to one of the input/output data terminals for the defective memory cell is transferred from the input data distributing circuit 20 or 21 to the write-in circuit 14 associated with the redundant memory cell array 3, but the other data bits supplied to the other input/output data terminals are transferred from the input data distributing circuits to the write-in circuits associated with the memory cell arrays. Thus, a set of the input data bits are written into the memory cell arrays and the redundant memory cell array.
On the other hand, when the rewritable/erasable programmable read only memory device is shifted to a read-out operation, the multi-bit control signal is supplied from the control circuit 17 to the output data selecting circuits 24 to 25. Then, the output data selecting circuits 24 to 25 allows the output data bits read out from the perfect memory cells from the sense amplifier circuits to the output data buffer circuits, but no conduction path is established from the sense amplifier circuit associated with the memory cell array including the defective memory cell or cells. However, the output data selecting circuit transfers the data bit read out from the redundant memory cell array 3 to the output data buffer circuit, so that a set of the data bits without false data information bit are supplied to the input/output data terminals 26 to 27.
However, a problem is encountered in the prior-art rewritable/erasable programmable read only memory device in diagnostic operation for the memory cell arrays and the redundant memory cell array. In the diagnostic operation, the input data bits are written into not only the memory cells but also the redundant memory cells. However, as described above, an input data bit is written into either memory cell or redundant memory cell depending upon the multi-bit control signal. Especially, the rewritable/erasable programmable read only memory device consumes several hundred micro-seconds to write a byte of data bits into the memory cells or the redundant memory cells. Then, a prolonged time period is consumed for the diagnostic operation, and, for this reason, the diagnostic expenses become large in the production cost of the high-integration density rewritable/erasable programmable read only memory device.
USPTO Backgrounds
USPTO Backgrounds