1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to a manufacturing method of an electro line for a liquid crystal display (LCD) device.
2. Discussion of the Related Art
A liquid crystal display (LCD) device is widely used for notebook computers and desktop monitors, etc. because of its superior resolution, color image display and quality of displayed images.
In general, a liquid crystal display (LCD) device includes two substrates spaced apart and facing each other, and a liquid crystal material layer interposed between the two substrates. Each of the first and second substrates includes an electrode, whereby the electrodes of each of the first and second substrates face each other. When a voltage is applied to each of the electrodes, an electric field is induced between the electrodes. Accordingly, an alignment of the liquid crystal molecules of the liquid crystal material layer is changed by the varying intensity or direction of the induced electric field. Thus, the LCD device displays an image by varying transmittance of light through the liquid crystal material layer according to the arrangement of the liquid crystal molecules.
An active matrix LCD device, which has pixels in a matrix type, has been widely used because of high resolution and fast moving images. An array panel of the active matrix LCD device includes a plurality of thin film transistors (TFTs) and a plurality of pixel electrodes, each of which connects with each of TFTs.
A related art LCD device will be described hereinafter more in detail.
FIG. 1 is a plan view of an array substrate for a related art liquid crystal display device. In FIG. 1, a gate line 14 is formed horizontally in the context of the figure and a data line 20 is formed vertically in the context of the figure. The gate and data lines 14 and 20 cross each other to define a pixel region “P”. At the crossing of the gate and data lines 14 and 20, a thin film transistor “T” is formed as a switching device, and the thin film transistor “T” is electrically connected to the gate and data lines 14 and 20. A pixel electrode 30 is formed in the pixel region “P”, and the pixel electrode 30 is connected to the thin film transistor “T” through a drain contact hole 28.
The thin film transistor “T” includes a gate electrode 12 extended from the gate line 14, an active layer 18 overlapping the gate electrode 12, a source electrode 22 extended from the data line 20 and overlapping the active layer 18, and a drain electrode 24 spaced apart from the source electrode 22 and overlapping the active layer 18.
FIG. 2 is a cross-sectional view along the line II-II of FIG. 1. In FIG. 2, a gate electrode 12 is formed on a transparent substrate 1 and a gate insulator 16 is formed on the gate electrode 12. An active layer 18 made of amorphous silicon is formed on the gate insulator 16 and is positioned over the gate electrode 12. An ohmic contact layer 19 is formed on the active layer 18, and the ohmic contact layer 19 is made of doped amorphous silicon. Source and drain electrodes 22 and 24 are formed on the ohmic contact layer 19 and spaced apart from each other. The active layer 18 exposed between the source and drain electrodes 22 and 24 is a channel “ch” of a thin film transistor. A passivation layer 26 is formed on the source and drain electrodes 22 and 24, and the passivation layer 26 has a drain contact hole 28 exposing the drain electrode 24. A pixel electrode 30 is formed in a pixel region “P” on the passivation layer 26 and is connected to the drain electrode 24 through the drain contact hole 28.
Scanning signals or data signals from outer integrated circuits (not shown) are supplied to a liquid crystal panel including the array substrate illustrated above through the gate line or the data line. Each transistor turns on/off in regular sequence according to the scanning signal transmitted through the gate line. When the thin film transistor turns on, the data signal transmitted through the data line is supplied to the pixel electrode via the thin film transistor.
Recently, scanning time is becoming shorter and signaling speeds are increasing due to the large area and high resolution of the LCD device. The gate and data lines are made of material having low resistivity such as aluminum (Al) or aluminum alloy to prevent signal delay. However, Al is easily corroded by acid.
Therefore, copper (Cu), which has lower resistivity than Al and has strong chemical corrosion resistance, has been proposed as a material for the gate and data lines.
However, Cu has poor adhesive strength to a glass substrate, which is widely used as a substrate for the LCD device, and is easily diffused into a layer including silicon in relatively low temperature of about 200 degrees.
To solve the above problem, a structure having a titanium (Ti) layer as a barrier layer has been proposed.
FIGS. 3A to 3C show a manufacturing process of a gate line including a Cu layer in the related art.
In FIG. 3A, a gate line 32, which is composed of a titanium (Ti) layer 32a and a copper (Cu) layer 32b, is formed in a first region “A” on a substrate 1. A manufacturing process of the gate line 32 is as follows. First, the Ti layer 32a and the Cu layer 32b are subsequently deposited on the substrate 1. The Ti layer 32a functions as a barrier between the Cu layer 32b and the substrate 1. A photoresist pattern (not shown) is formed on the Cu layer 32b by coating, exposing, and developing a photoresist resin. The Cu layer 32b and the Ti layer 32a are subsequently etched using the photoresist pattern as a mask. Next, the photoresist pattern is stripped.
The Ti layer 32a is etched by an etchant including a fluoride ion (F−). HF may be used as the etchant. The HF removes not only the Ti layer 32a but also the substrate 1, which is made of glass including silicon (Si). Therefore, the substrate 1 is also etched by a thickness of “C” in a second region “B”, which does not have gate line 32 thereon, and the substrate 1 has a surface that is not flat.
As shown in FIG. 3C, a new gate line 34 is formed in place of the gate line 32 of FIG. 3A on the surface of the substrate 1 which is not flat. A reworking process of the gate line is shown in FIGS. 3B and 3C.
In FIG. 3B, the gate line 32 of FIG. 3A is removed. At this time, while the gate line 32 of FIG. 3A is removed, the substrate 1 in the second region “B” is also removed. Accordingly, the surface of the substrate 1 in the second region “B” has a step “D” above the surface of the substrate 1 in the region “A”, wherein the step “D” is larger than the thickness “C”. The flatness of the substrate 1 is much lower than in FIG. 3A.
In FIG. 3C, new gate line 34 is formed on the substrate 1 through the process in FIG. 3A. At this time, the gate line 34 may be formed on a borderline between the first region “A” and the second region “B” because of a process margin. Then, the gate line 34 has an uneven surface along the step “D” of the substrate 1, which leads to poor patterns being formed on the gate line.
FIG. 4 shows a manufacturing process of source and drain electrodes including a Cu layer in the related art. In FIG. 4, a gate line 32 is formed on a substrate 1 and a gate insulator 36 is formed on the gate line 32. The gate line 32 is made of two layers of a Ti layer 32a and a Cu layer 32b. The Ti layer 32a functions as a barrier between the Cu layer 32b and the substrate 1. An active layer (not shown) and an ohmic contact layer (not shown) are subsequently formed on the gate insulator 36. Though not shown in the figure, source and drain electrodes made of a Ti layer and a Cu layer are formed on the ohmic contact layer by depositing and patterning the Ti layer and the Cu layer. The Ti layers of the source and drain electrodes are etched by an etchant including a fluoride ion (F−). Thus, the gate insulator including silicon may be etched by the etchant, and the gate electrode 32 may be exposed in a step area “E”, where the gate insulator 36 has worse properties than in other regions.
USPTO Backgrounds
USPTO Backgrounds