1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which defective memory cells can be replaced with redundant cells and a manufacturing method thereof.
2. Description of Related Art
Semiconductor memories typified by a DRAM (Dynamic Random Access Memory) include a large number of memory cells, some of which inevitably become defective due to manufacturing conditions and other factors. In order to ship such semiconductor memories as conforming products, the redundancy repair technique of replacing defective memory cells with redundant cells is needed.
According to the redundancy repair technique, a semiconductor memory in a wafer state is initially subjected to an operation test to detect the addresses of defective memory cells (defect addresses). The detected addresses are programmed into optical fuses in the semiconductor memory. Optical fuses are fuses that can be blown by irradiation of a laser beam or the like. Since blown optical fuses cannot be restored to a conducting state again, it is possible to store information in a nonvolatile and irreversible manner. When access is requested to the addresses programmed in the optical fuses, redundant cells (alternative cells) are accessed instead of the defective memory cells, whereby the addresses are repaired.
Memory cell defects occur mainly in the wafer stage (manufacturing steps for forming a plurality of circuits on a wafer; so-called front-end processes). Most defects are therefore repaired by replacement using optical fuses. However, new defects can occur after the replacement using optical fuses, in back-end processes including assembly. For example, new defects may occur due to a thermal load during packaging. It is not possible to repair such defects by using the optical fuses.
As a solution to the problem, Japanese Patent Application Laid-Open No. 2002-25289 and Japanese Patent Application Laid-Open No. 2007-328914 propose semiconductor devices that can implement both the replacement using optical fuses and replacement using electrical fuses.
Since the tester for use in the back-end processes needs to operate at high speed, it is not realistic to mount a large-capacity analysis memory as with low-speed testers used in the wafer stage. In order to analyze defects occurring in the back-end processes by using the tester, the number of semiconductor devices to be simultaneously tested needs to be reduced. This has caused a problem of a significant drop in production efficiency.
Japanese Patent Application Laid-Open No. 2001-52497 describes a method of compressing the amount of information related to defective memory cells by determining a plurality of defective memory cells detected to be a line defect, not individual bit defects, if the defective memory cells fall on the same line.
The method described in Japanese Patent Application Laid-Open No. 2001-52497, in short, is to handle a plurality of bit defects as a line defect. Such a method can reduce the final amount of information, whereas it is hardly possible to reduce the work area needed for address analysis, i.e., the storage capacity of the analysis memory. The reason is that information on a large number of bit defects needs to be retained before the determination of a line defect, depending on the order of defective memory cells detected.
The present inventors have proposed a semiconductor device employing an analysis circuit which analyzes a defective address. According to this, since a storage capacity required for an analysis memory can be significantly reduced, the analysis memory can be integrated into the semiconductor device. However, an operating speed at the time of a test will be restricted by operating speeds of the analysis circuit and the analysis memory in this case. In addresses of a semiconductor device, an address not to become defect at the time of low-speed access, but become defect at the time of high-speed access may exist. There is a possibility that such a defect cannot be discovered only by the test of operation using the internal analysis circuit and the analysis memory. Therefore, it is desirable to discover such a defect and to replace a defective cell by a redundant cell. The present invention is made based on such technical findings.
USPTO Backgrounds
USPTO Backgrounds