Description of the Related Art
A memory cell configuring a nonvolatile semiconductor memory device such as a NAND type flash memory includes a semiconductor layer, a control gate, and a charge accumulation layer. The memory cell changes its threshold voltage according to a charge accumulated in the charge accumulation layer and stores a magnitude of this threshold voltage as data. In recent years, enlargement of capacity and raising of integration level has been proceeding in such a nonvolatile semiconductor memory device. Moreover, a nonvolatile semiconductor memory device in which the memory cells are three-dimensionally disposed (a three-dimensional type semiconductor memory device) has been proposed to raise integration level of the memory.
USPTO Backgrounds
USPTO Backgrounds