1. Field of the Invention
The present invention relates to a semiconductor device in a power supply circuit, and more particularly to a technique for improving power conversion efficiency in a semiconductor device used in DC/DC converters that is referred to as a system-in-package, in which a high-side switch, a low-side switch, and a driver are included in a single package.
2. Background Art
The following is an analysis of the technologies relating to semiconductor devices in power supply circuits.
In response to the growing demand for smaller size and faster load response in power supply circuits, the frequencies of the power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) used in power supplies are becoming increasingly higher.
In particular, there is a growing tendency to increase current levels and frequencies in the non-isolated DC/DC converters used in the power supply circuits for personal computers and computer game machines. This is due to the increasing current levels in the CPUs to be driven, demand for smaller passive components, such as choke coils, and demand for smaller input/output capacitance.
Non-isolated DC/DC converters are widely used in the power supply circuit for personal computers and computer game machines, for example. As a result of the increasing current and lower voltage levels in CPUs mounted on these electronic systems, there is a need for higher efficiency and smaller size in non-isolated DC/DC converters.
Such non-isolated DC/DC converters consist of a high-side switch and a low-side switch, each employing a power MOSFET.
These switches perform voltage conversion by turning themselves on and off alternately in a synchronized manner. The high-side switch is a switch for controlling the DC/DC converter, while the low-side switch is a switch for synchronous rectification.
There is also the trend toward system-in-packages, with the high-side switch, low-side switch, and their drivers implemented in a single package, in response to demand for modern DC/DC converters with reduced parasitic inductance between chips, faster response, and smaller size.
Hereafter, an example of the conventional system-in-package that the inventors have analyzed as a basis for the present invention will be described with reference to FIGS. 8 to 10.
FIG. 8 shows an example of the circuit configuration of a conventional system-in-package for a DC/DC converter. A system-in-package 29 is made up of a high-side MOSFET 2, a low-side MOSFET 3, and drivers 5 and 6 for driving the individual MOSFETs. The high-side MOSFET 2 is disposed in a semiconductor chip 7; the low-side MOSFET 3 is disposed in a semiconductor chip 8; and the drivers 5 and 6 are disposed in a semiconductor chip 9. These three chips are included in a single package.
The operational principle and the individual terminals of the DC/DC converter employing the system-in-package will be described below. When a PWM signal is inputted from a PWM controller 10 to a PWM input terminal 18, the drivers 5 and 6 drive the gates of the high-side MOSFET 2 and low-side MOSFET 3 via wires 14 and 16. The drivers 5 and 6 are fed with the source potential of the high-side MOSFET 2 and low-side MOSFET 3 via wires 15 and 17, and the individual gate voltages are determined with reference to the source potential. The voltage applied to the gate of each MOSFET is fed from external power supplies VGH and VGL via VGH input terminal 20 and VGL input terminal 19, respectively. Depending on the ratio of the on-period of the high-side MOSFET 2 and low-side MOSFET 3, the voltage applied to an input terminal 23 is converted into a desired voltage and then outputted to an output terminal 24. The output voltage is smoothed by a smoothing inductor 11 and a smoothing capacitor 12.
In this system-in-package, because the high-side MOSFET 2 employs an n-type MOSFET, a bootstrap circuit is used for driving the gate. For this purpose, a capacitor 28 and a boot terminal 21 are provided. Although the bootstrap circuit employs a diode for back-flow prevention purposes, the diode is not shown, as it is irrelevant to the present invention. The system-in-package also includes a VGH monitor terminal 22 and a VGL monitor terminal 26 for monitoring the gate voltages of the high-side MOSFET 2 and low-side MOSFET 3, a power ground terminal 25, and a logic ground terminal 27.
FIG. 9 shows an exterior view and an example of the chip configuration and wire bonding configuration of the conventional system-in-package for the DC/DC converter. The package employs a quad flat non-leaded package (QFN), which is a type of non-leaded surface mounting packaging technology. As shown, the tab of the package is divided into three sections, namely, for semiconductor chip 7 of the high-side MOSFET, semiconductor chip 8 of the low-side MOSFET, and semiconductor chip 9 of the drivers. The individual chips are connected by wire bonding. One feature is that the wires 14 and 16 for driving the gate of the individual MOSFETs and the wires 15 and 17 for transmitting the reference source potential are disposed closely and in parallel, thereby reducing the parasitic inductance in the gate-driver and source-driver sections of the MOSFETs.
In this DC/DC converter, however, if the high-side MOSFET 2 is turned on when the low-side MOSFET 3 is off, the drain voltage (at the output terminal 24 in FIGS. 8 and 9) of the low-side MOSFET 3 increases. This voltage causes a charge current to flow between the gate and source of the low-side MOSFET 3 via the feedback capacitance between the gate and drain of the low-side MOSFET 3, resulting in an increase in the gate voltage of the low-side MOSFET 3. Regarding this phenomenon, if the gate voltage of the low-side MOSFET 3 exceeds a threshold voltage, the low-side MOSFET 3 turns on, whereby a large shoot-through current flows from the high-side MOSFET 2 to the low-side MOSFET 3 (“self-turn-on phenomenon”), which significantly reduces conversion efficiency.
FIG. 10 shows a timing chart of the individual voltages for illustrating the self-turn-on phenomenon. When the high-side MOSFET 2 turns on, the voltage at the output terminal 24 increases, and the gate-source voltage of the low-side MOSFET 3 exhibits peak voltage at the same time as the peak voltage at the output terminal 24 and exceeds the threshold voltage. In an actual low-side MOSFET, a MOSFET with a sufficiently high threshold voltage must be used so that the self-turn-on phenomenon can be avoided. This leads to an increase in conduction loss and an inability to achieve higher efficiency.
As a solution for the aforementioned problem, Patent Document 1 discloses that the low-side switch and an auxiliary switch are built inside the same package, with the auxiliary switch connected between the gate and source of the low-side switch. When the gate voltage of the low-side switch increases, the auxiliary switch is turned on so as to short-circuit the gate-source junction of the low-side switch, thereby preventing the increase in the gate voltage and the self-turn-on phenomenon.    Patent Document 1: JP Patent Publication (Kokai) No. 2002-290224 A
USPTO Backgrounds
USPTO Backgrounds