1. Field of the Invention
The present invention relates to a semiconductor device structure having an interlayer dielectric film made of a resinous material. The invention also relates to a method of fabricating such a semiconductor device structure.
2. Description of the Related Art
Techniques for fabricating thin-film transistors (TFTs), using a thin film semiconductor formed on a glass substrate or quartz substrate, have been known.
The prior art steps for fabricating a TFT are shown in FIGS. 3(A) and 3(B). This TFT is disposed in a pixel region of an active matrix liquid crystal display.
First, a silicon oxide film is formed as a buffer layer 302 on a substrate 301 of glass or quartz to a thickness of 3000 .ANG. by plasma CVD. Then, an amorphous silicon film (not shown) is formed to a thickness of about 500 to 1500 .ANG. by plasma CVD or LPCVD. This amorphous film acts as a starting film in forming an active layer of TFTs. Subsequently, the amorphous silicon film (not shown) is heat-treated or illuminated with laser light to crystallize the amorphous film. In this way, a crystalline silicon film (not shown) is obtained.
Then, this crystalline silicon film is patterned to form regions (303, 304, 305 in FIG. 3(A)) which will become the active layer of the TFTs later. Thereafter, a silicon oxide film 306 which covers the active layer and acts as a gate-insulating film is formed to a thickness of 1000 to 1500 .ANG. by plasma CVD. Then, a gate electrode 307 is formed from a metallic material or silicide material. Thus, a state shown in FIG. 3(A) is obtained. Under this condition, dopant ions are implanted, and the source region 303, the drain region 305, and the channel formation region 304 are formed by self-aligned technology. This is followed by heat-treatment or laser illumination, for annealing the doped regions.
Then, a first dielectric film 308 is formed from silicon nitride or silicon oxide to a thickness of 2000 to 6000 .ANG. by plasma CVD. Subsequently, contact holes are formed. A source electrode and interconnects, 309, extending from it are formed from an appropriate metal material (FIG. 3(B)).
Then, a second interlayer dielectric film 310 is formed from silicon oxide or silicon nitride. The thickness of this second interlayer dielectric film is set greater than 7000 .ANG. to assure that the surface is sufficiently flat. Then, a contact hole 311 is formed, thus obtaining a state shown in FIG. 3(C).
Thereafter, an ITO electrode 312 forming a pixel electrode is formed. In consequence, a TFT disposed in the pixel region of the active matrix regions is completed. During these fabrication steps, the formation of the pixel electrode 312 presents the following problems.
In recent years, the sizes of conductor patterns and TFT patterns have tended to diminish, because there is an increasing demand for increased device densities. Furthermore, active matrix liquid crystal displays are required to reduce such patterns to increase the aperture ratio of pixels.
As such patterns are reduced in size, it is, of course, necessary to reduce the size of the window hole 311. However, if the contact hole 311 is reduced in size, the material, or ITO, of the pixel electrode 312 does not form a film with good coverage within the small hole. As a result, it is difficult to make required contacts. In particular, the contact hole is elongated. The material for making a contact may break inside the hole. As a consequence, poor contact takes place.
USPTO Backgrounds
USPTO Backgrounds