This invention relates to semiconductor integrated circuit devices and methods of fabricating the same, and in particular to an improvement in the method of forming transistors and the contacts of resistors connected to these transistors in a bipolar semiconductor integrated circuit device (bipolar IC).
The transistors of a bipolar IC are formed in electrically isolated islands, the isolation being achieved by means of pn junctions, oxide films formed by selective oxidation, or the techniques using triple diffusion. The fabrication of an npn transistor by oxide film isolation is described below. However, the present invention applies to the other methods of isolation as well, and also to pnp transistors.
The components of a bipolar IC are generally transistors, diodes, and resistors. Diode fabrication is similar to transistor fabrication, so the example discussed below is that of a transistor-resistor circuit in which a resistor R is connected to the base B of a transistor Tr as shown in FIG. 5.
This device is conventionally fabricated as shown in FIGS. 6a to 6e. The prior art fabrication method will be described with reference to these figures.
First, a first and a second n-type (n.sup.+ -type) layer 2a and 2b of high impurity concentration are selectively formed in a p-type (.sup.- -type) silicon substrate 1 of low impurity concentration, as in FIG. 6a. The first of these layers 2a will become the buried collector. Next an n.sup.- -type epitaxial layer 3 is grown over these layers.
On this n.sup.- -type epitaxial layer 3 are next formed first an oxide underfilm 101 and then a nitride film 201 as in FIG. 6b. The nitride film is patterned to form a mask for selective oxidation to create a thick isolation oxide film 102 surrounding the transistor-forming region and the resistor-forming region. At the same time, a p-type channel-cut layer 4 is created below the isolation oxide film 102. That part of the n.sup.- -type epitaxial layer 3 remaining in the transistor forming region becomes the collector region of the transistor, which will be called a first n.sup.- -type epitaxial layer. The part of the n.sup.- -type epitaxial layer 3 remaining in the resistor region will be called a second n.sup.- -type epitaxial layer.
Next the nitride film 201, used as mask in the selective oxidation described above, is stripped off together with the oxide underfilm 101 and a new oxide film 103 is formed over the n.sup.- -type epitaxial layers 3a and 3b for protection during ion implantation, as shown in FIG. 6c. A p.sup.+ -tupe layer 5 that has one side adjacent to the isolation oxide 102 which separates the transistor region from the resistor region, and becomes the external base region is then created by ion implantation, using a photoresist film (not shown in the figure) as a mask, on a part of the surface of the first n.sup.- -type epitaxial layer 3a. Then the photoresist film is stripped off, a new photoresist film 301 is formed, and a second ion implantation is carried out, using the photoresist film as the mask, to create a p-type layer 6 in the surface of the first n.sup.- -type epitaxial layer 3a adjacent to the external base region 5, this layer 6 becoming the active base region, and a p-type layer 9 that becomes the resistor region in the second n.sup.- -type epitaxial layer 3b.
Next the photoresist film 301 is stripped off and a passivation film 401, usually made of phophosilicate glass (PSG), is deposited over the entire surface as in FIG. 6d. Heat treatment is then conducted to anneal the external base region 5, the active base region 6, and the resistor region 9, formed by ion implantation and to sinter the PSG layer 401 to form the external base region 5 and the active base region 6 and the resistor region 9. Then windows 70 and 80 are opened in the PSG layer 401 and ion implantation is conducted to form an n.sup.+ -type region 7, which is to become the emitter, in part of the surface of the active base region 6 and an n.sup.+ -type region 8, which is to become the collector contact, in part of the surface of the first n.sup.- -type epitaxial layer 3a.
The ion-implanted regions are annealed to complete the formation of the external base region 5, the active base region 6, and the resistor region 9. The emitter region 7 and the collector contact region 8 are created, followed by the base contact window 50 and the resistor contact windows 91 and 92, as in FIG. 6e. A metal silicide film 501 (platinum slicide (Pt-Si), palladium silicide (Pd-Si), or the like) for preventing contact junction spiking is then deposited in the windows 50, 70, 80, 91 and 92, and then a low-resistance metal such as aluminum is deposted to form base electrode interconnection 12, emitter electrode interconnection 10, collector electrode interconnection 11, resistor-to-base interconnection 13 and resistor electrode interconnection 14.
FIG. 7 is a plan view of a transistor fabricated by the prior art method described above. The frequency characteristics of the transistor depend on the base-collector capacitance and the base resistance, and these two factors need to be reduced to improve the frequency characteristics. The purpose of the external base region 5 in the structure described above is to reduce the base resistance, but this has the drawback of increasing the base-collector capacitance. The base resistance also depends on the distance D.sub.1 between the emitter region 7 and the base contact window 50. In the prior art D.sub.1 is the sum of the gap between the base contact interconnection line 12 and the emitter contact interconnection line 10 and the amounts by which these interconnection lines 12 and 10 project from the contact windows 50 and 70. Improved photoetching accuracy can reduce the gap between the interconnection lines, but the reduction in D.sub.1 has been limited because of the interconnection lines projecting from the windows.
Moreover, the resistor region 9 connected to the base of the transistor is formed by diffusioon, so that it must be isolated by the oxide film 102 from the transistor region, and the base-to-resistor interconnection 13 and the resistor contact interconnection 14 are provided, thereby restricting the routing of further interconnection lines over the resistor region 9. As a result, it is difficult to achieve higher integration densities. In addition, since the resistor region 9 is isolated by a p-n junction, it has a capacitance, which also causes frequency degradation.
The difficulty associated with the provision of additional interconnection lines over the resistor region is described below. In the bipolar intergrated circuit, it sometimes happens that, as shown in FIG. 8, additional interconnection lines 16 and 17 (two lines are illustrated, but there can be more) are routed over the resistor 9. In this case, the length of the resistor 9 is large and hence the width of the resistor must be large to obtain a relatively small resistance. This is because the resistance value is proportional to the length (L in the figure) between the contact parts 91 and 92 of the interconnection 13 and 14 and inversely proportional to the resistor width (W in the figure) so that when many interconnection lines must be routed over the resistor, the length L is increased, and hence it is necessary to increase the width W by a large amount to obtain a small resistance value. Thus with the prior art, large resistor sizes are required and integration density is lowered and the capacitance of the resistor is increased, and the characteristics may be degraded.
In the master-slice technology, in which the resistors which have been formed are altered at the step of forming the resistor contact windows and the subsequent steps, the diffusion is performed to provide the maximum resistance (maximum L) that might be needed in the final device, and the contact windows 91 and 92 are formed in the subsequent fabrication process at a separation corresponding tot he resistance actually desired, as shown in FIG. 9. Accordingly, even resistors with small resistance values have the capacitance of the maximum resistor. This excess capacitance degrades the characteristics of the device.
USPTO Backgrounds
USPTO Backgrounds