This invention is in the field of processing circuitry architecture, and is more specifically directed to memory management for co-processing architectures.
As is fundamental in modern computer architectures, virtually all computer or processing architectures include input and output functions, a control function, arithmetic and logic functionality, and memory. And as is also fundamental in the art, efficient communication of information between the memory resources and the arithmetic and logic unit (ALU) is important in achieving high system performance. As such, many advances have been made in computing and processing architectures to improve this functionality, such advances including higher-speed and wider datapaths between memory and the central processing unit (CPU), cache memory hierarchies to improve the efficiency of data retrieval and storage for often-accessed memory locations, and of course higher-speed semiconductor memory technologies.
Of course, another significant factor in overall processing system performance is the rate at which the CPU or ALU can execute its arithmetic and logical operations. As known in the art, huge advances have also been made in the speed at which the processing circuitry executes instructions, reflected by the “clock rate” of modern microprocessors. In addition, architectural advances including the use of multi-state instruction pipelines in modern CPUs, and multiple processor “cores”, have had dramatic impact in the computational capacity of modern processing systems.
The use of “co-processors” in modern processing systems has also greatly provided substantial performance improvement. As fundamental in the art, a co-processor is typically a special purpose arithmetic and logical unit, designed to rapidly and efficiently execute certain types of operations, usually complex arithmetic operations. Examples of co-processors include floating-point units (ALUs constructed to perform floating-point arithmetic), and digital signal processor co-processors (ALUs constructed to rapidly perform multiply-and-add operations). In a typical co-processor system, the main CPU will “call” a routine for execution by the co-processor, in response to which the co-processor will access memory to execute its specific arithmetic operation on stored data, and store the results in memory for later access by the main CPU. Use of a co-processor in a system enables the main CPU to be constructed as a relatively modest general purpose processor, while still obtaining high-performance execution of complex arithmetic instructions and routines.
However, the implementation of a co-processor into a computing system complicates system operation, to some extent. The co-processor particularly impacts memory management in the system, because the co-processor must have access to the input data on which it is to operate, and must also have access to a memory resource to store the results of its operation. This co-processor memory management can be effected by permitting the co-processor to access the same main memory as the main CPU, which requires the management of access to the main memory to avoid conflicts in access from the CPU and co-processor, and to avoid issues of data coherency because the memory is accessible to multiple functions. The co-processor need not have access to the main memory if the system is arranged so that the CPU “passes” the input data to the co-processor and so that the co-processor “passes” the results back to the CPU. In this manner, the CPU can manage all accesses to main memory, avoiding the possibility of conflict and coherency issues; however, substantial computing capacity becomes occupied by the transfer of data in this manner. These and other tradeoffs must be faced by the system architect in the design of the system.
Many important advances have also been made in the miniaturization and portability of modern computer systems. These advances have enabled small electronic systems to perform highly advanced computing tasks, thus providing digital computing functionality in a wide range of applications. For example, these advances are beginning to enable the use of digital signal processing techniques in battery-powered miniaturized hearing aids, to improve the sound and intelligibility of amplified sound for the hearing-impaired. For example, a common problem faced by hearing aid wearers in the past was due to conventional hearing aids amplifying noise along with the desired speech or sound, making the hearing aid effectively useless in noisy environments such as restaurants and arenas. It is contemplated that digital signal processing techniques can more intelligently amplify the desired sound rather than noise, providing great improvement in the intelligibility of the sound.
Of course, battery life and thus system power consumption is a significant issue in portable computing systems. Hearing aids are especially sensitive to battery life. As mentioned above, the use of a co-processor to perform specific complex arithmetic functions, such as digital signal processing routines, is attractive in providing high system performance without requiring highly advanced CPUs. However, the passing of data to and from the co-processor, either via the CPU or by way of the co-processor directly accessing main memory, necessarily involves substantial power consumption. For example, in a conventional co-processor system, the co-processor reads or receives the input data, stores that input data in its memory, stores the results of its computations in its memory, and writes those results (directly, or via a CPU) into the main memory for use by the CPU. The power consumption involved in these memory accesses, as repeatedly performed in digital signal processing routine such as a Discrete Fourier Transform or digital filter, can be significant, especially in miniature battery-powered systems such as hearing aids.
USPTO Backgrounds
USPTO Backgrounds