1. Technical Field
The present invention relates to the field of rule-based operations and, more particularly, to a data-driven design rule check (DRC) method and system.
2. Description of the Related Art
A logic simulator is a software tool which is capable of performing functional and timing simulations for digital electronic designs which are written in a hardware description language (HDL) such as VHSIC Hardware Description Language (VHDL) or Verilog. The VHSIC acronym stands for Very High Speed Integrated Circuits. VHDL and Verilog are HDLs used to design and document electronic systems. Verilog, for example, permits hardware designers to define signals at a very high level of abstraction. The abstracted signal representations can be translated to actual pins on a microchip using any of a variety of commercial electronic design automation (EDA) software tools.
Design Rule Check (DRC) is a crucial step in validating an electronic design before actual hardware implementation. A failed DRC signals a critical error which may lead to silicon failure. The goal of DRC is to identify places in the integrated circuit design where the design rules, such as the spacing between two features or the width of a wire, have been violated. Design rules tend to change frequently and with many different fabrication processes, particularly in the sub-micron domain, there could be many subtly different design rules. Thus, with design density growing and more hardware features being introduced, DRC is also growing in complexity. A typical new design block such as an embedded PowerPC in an field programmable gate array (FPGA)-based System-on-Chip (SOC) or a multi-Gigabit transceiver often requires a large number of complex design rule checks to be done.
In existing design rule checkers, the rules are often coded in software source code (e.g., C/C++) and then compiled into a software library. For example, in order to check whether Pin A of a component B is connected to a Ground signal, the following code fragment would be used:
function check_pinAofB(componentX)                {                    if(typeof(X)==B)            {                            Pin pX =getpinA(X);                if(driven_by_Ground(pX))                                    issueError( );                                                                    }                        }        
If a small change has to be made to the design rule above, the entire function (and hence the entire program file) must be recompiled. Such process is time-consuming and risky and hence makes rule modification difficult. Also, if other rules must be added to check the same condition for a different component, a large part of the above function/procedure must be replicated. Such a system is inflexible and hard to maintain.
USPTO Backgrounds
USPTO Backgrounds