There is a stacked semiconductor memory device including memory cells that are three-dimensionally disposed for increasing the degree of integration of memory. The semiconductor memory device includes a plurality of semiconductor pillars extending in a stacking direction and a plurality of electrode films (word lines) that extend in a direction intersecting the stacking direction and are arranged in the stacking direction. A memory cell is formed between the semiconductor pillar and the electrode film. In such a semiconductor memory device, it is desired to make the data erasing characteristics of the memory cell favorable.
USPTO Backgrounds
USPTO Backgrounds