Microelectronic systems commonly contain power devices prone to the generation of excess heat during operation, particularly when operated at higher power levels and, perhaps, when operated at higher RF frequencies. In the absence of adequate heat dissipation means for removing excess heat from the system, undesirably elevated temperatures or “hot spots” can occur at localized regions within the microelectronic system and the power device(s) contained therein. Such highly elevated localized temperatures can detract from device performance and reliability, as well as degraded the overall reliability of the microelectronic system by accelerating common failure modes, such as solder joint fatigue. For this reason, microelectronic systems containing power devices, such packaged or unpackaged RF semiconductor die, are often fabricated utilizing embedded coined substrates; that is, substrates incorporating metal (e.g., Cu) slugs or “coins” having relatively high thermal conductivities. By attaching a power device or a module containing one or more power device(s) to an embedded coin, excess heat concentrations may be more effectively dissipated to enhance the thermal performance of the microelectronic system.
While generally having improved heat dissipation capabilities, microelectronic systems fabricated utilizing embedded coin substrates remain limited in multiple regards. The manufacturing processes utilized to fabricate coined substrates tend to be undesirably complex, costly, and may involve exposure to highly elevated processing temperatures at which substrate warpage and other deleterious effects can occur. Manufacturing cost and complexity may further increase when utilizing an embedded coin for electrical interconnection purposes; e.g., to electrically couple a ground pad of a power device or device-containing component, such as a PAM package, to a ground layer contained within a substrate. For example, in one known manufacturing approach, a multilayer PCB is produced to include at least one upper PCB layer composed of a higher quality dielectric material, as well as one or more lower PCB layers composed of a lower cost dielectric material, such as FR4. The PCB further contains an embedded coin and a ring-shaped cluster of vias or “via farm,” which extends through the upper PCB layers to connect the embedded coin to electrical ground. Fabricating an embedded coin substrate in this manner can reduce PCB manufacturing costs, while enhancing the dielectric performance of the upper PCB laminates; however, embedded coin PCBs of this type do little to improve the overall heat dissipation capabilities of the resultant microelectronic system.
Even when setting aside the manufacturing-related limitations described above, microelectronic systems fabricated utilizing embedded coin substrates remain limited in other respects, as well. As conventionally designed and fabricated, such systems often rely upon legacy materials, such as solder materials, to attach heat-generating microelectronic components to the upper surfaces of coins embedded within a particular PCB or substrate. While suitable for many applications, the thermal conductivities and temperature tolerances of such materials can be undesirably restrictive in the context of high power and high frequency (e.g., RF) applications. As a result, the integration of conventional embedded coined substrates into microelectronic systems containing power devices often provides an incomplete or suboptimal heat dissipation solution. Consequently, highly elevated local temperatures may still occur at certain junctures within the thermal stack (that is, the various layers of materials through which conductive heat flow is desired) in a manner exacerbating failure modes of the microelectronic system when operated at higher power levels and/or at higher (e.g., RF) frequencies.
For simplicity and clarity of illustration, descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds