The present invention relates generally to a complementary circuit, and more particularly, but not by way of limitation, to a complementary circuit including at least one logic unit and a level shifting circuit.
In conventional thin-film transistor (TFT) technologies, only one TFT type (n-channel or p-channel) is available. This precludes the use of complementary metal-oxide-semiconductor (CMOS) circuits which are highly desired for reducing power consumption. In addition, in some emerging TFT technologies including a variety of metal-oxide and organic materials, the TFTs are depletion-mode/normally-on devices adding further complexity in designing low-power circuits. An important application for such circuitry is monolithic drivers for active-matrix displays which are highly desired for realizing displays with narrower edges (borders) for portable devices (e.g., cell phones and tablets), as well as flexible displays (e.g., which require at least one of the row or column drivers to be flexible thereby precluding the use of externally mounted rigid chips).
An exception to this limitation is low-temperature poly-silicon (LTPS) which allows both n-channel and p-channel TFTs. LTPS also enables higher device and circuit performance due to higher TFT mobility. However, the TFT fabrication cost is significantly higher for LTPS. Further, the required TFT process temperatures (400-600° C.) are too high for low-cost glass or plastic substrates to be utilized.
Similar to conventional LTPS TFTs, complementary circuits may be realized by integrating n-channel and p-channel Heterojunction Field Effect Transistor (HJFET) devices. While the fabrication cost and complexity of HJFET is significantly lower than that of conventional LTPS TFTs (for either or both of channel types), the fabrication cost and complexity of integrating both n- and p-channel HJFET devices is higher than that of just n-channel or p-channel HJFET.
USPTO Backgrounds
USPTO Backgrounds