The present invention relates, in general, to protection circuitry and, more particularly, to high voltage protection of input circuitry.
It is well known that monolithic integrated circuits may become damaged by exposing their input terminals to large abnormal voltages. These large abnormal voltages can rupture the dielectric materials within the integrated devices such as gate oxides or it may melt conductive materials such as polysilicon or aluminum interconnects, thereby irreparably damaging the integrated circuits.
Generally, integrated circuit manufacturers include protection devices that shunt current away from input circuitry within integrated devices to prevent the integrated devices from being damaged by large voltage transients. One technique for protecting integrated device input circuitry is to improve the energy dissipation capability of the protection circuitry. This is done by laying out the protection circuit to have larger geometries, wider metal interconnects, more and larger contacts, etc. A disadvantage of this approach is it increases the size of the integrated device, thereby decreasing the number of integrated circuits per semiconductor wafer and increasing the cost of manufacturing the integrated circuits.
Accordingly, it would be advantageous to save a circuit for protecting input circuitry from damaging overvoltages. It would be of further advantage for the circuit to occupy a small area and be compatible with standard processing techniques. In addition, it would be further advantage for the circuit to not affect the operation of components external to the circuit by not drawing large currents while protecting the input circuitry .
USPTO Backgrounds
USPTO Backgrounds