The on and off properties of a power switch, namely, a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), is often used to implement efficient conversion of signals and energy in a switch power supply, a switch amplifier, a charge pump, and the like. Typically, a large current passes through a power MOSFET when the power MOSFET is on, and if the current passing through the power MOSFET exceeds the tolerance of the power MOSFET, the power MOSFET may be damaged permanently. Therefore, in order to ensure the reliability of the power MOSFET, continuous detection may be performed on the current passing through the power MOSFET, and overcurrent protection over the power MOSFET may be performed when the passing current is too large.
FIG. 1 gives an overcurrent detection circuit for the case in which an N-type MOSFET (NMOS) serves as the power switch. As shown in FIG. 1, NMOS N1 as a power switch has a ratio of N:1 in size over NMOS N2, and is in common-gate and common-drain connection with NMOS N2, with both gates connected to a first bias voltage CP1, and both drains connected to an input voltage Vin. The source of NMOS N1 is connected to the negative input of an amplifier A1, and the source of NMOS N2 is connected to the positive input of the amplifier A1 and the drain of an NMOS N3. The output of the amplifier A1 is connected to the gate of NMOS N3, which is in common-gate and common-source connection with an NMOS N4, with both sources connected to ground. The drain of NMOS N4 is connected to a resistor R1 and the negative input of a comparator OP1. One end of resistor R1 is connected to the drain of NMOS N4, and the other end of resistor R1 is connected to voltage Vin. One end of a resistor R2 is connected to the positive input of comparator OP1 and a reference current source Q1, and the other end of R2 is connected to input voltage Vin. The power terminal of comparator OP1 is connected to input voltage Vin, and comparator OP1 generates an output signal OCP.
During the operation of the overcurrent detection circuit shown in FIG. 1, as amplifier A1 is in negative feedback connection, the virtual shorting effect of amplifier A1 equalizes the voltages at the positive and negative inputs of the amplifier A1. NMOS N2 samples the current passing through NMOS N1, which is N times of the current passing through NMOS N2, where N is a positive integer. The current passing through NMOS N3 is that through NMOS N2. NMOS N4 mirrors the current in NMOS N3, resulting in a current Is passing through NMOS N4. The voltage drop across resistor R1 is R1*Is, the voltage drop across resistor R2 is R2*Ir, where Ir indicates the current supplied by reference current source Q1. When the current passing through NMOS N1 is small, the current passing through NMOS N2 is also small and R1*Is<R2Ir. The output signal OCP of comparator OP1 is low or inactive in this case; indicating no overcurrent in NMOS N1. When the current passing through NMOS N1 reaches an overcurrent protection threshold, or R1*Is>R2Ir, the output signal OCP of comparator OP1 is high or active; indicating that an overcurrent has occurred in NMOS N1.
There are some drawbacks to the circuit of FIG. 1. In the overcurrent detection circuit shown in FIG. 1, input voltage Vin is typically has a high voltage value, and thus each device in the circuit has to be able to tolerate higher voltages. Additionally, there will be a large error in the current Is passing through NMOS N4 obtained by current mirroring; reducing the accuracy of overcurrent detection.
Further, the amplifier A1 in FIG. 1 has a structure typically as shown in FIG. 2. The gate of NMOS N21 is the negative input, the source of NMOS N21 is connected to the source of NMOS N22, and to the ground via a current source Q21, and the drain of NMOS N21 is connected to the drain of and the gate of a P-type MOSFET (PMOS) P21, and to the gate of PMOS P22. PMOS P21 and PMOS P22 are in common-source and common-gate connection, forming a current mirroring circuit. The gate of NMOS N22 is the positive input of the amplifier, the drain of NMOS N22 is connected to that of PMOS P22 and the gate of PMOS P23. The drain of PMOS P23 is the output, and is connected to ground via current source Q22. When voltages at the positive and negative inputs of the amplifier shown in FIG. 2 are close or equal to the supply voltage, the voltages at the drain and the source of NMOS N21 are very close to each other, making NMOS N21 operate in a linear region, thereby reducing the gain of the amplifier.
USPTO Backgrounds
USPTO Backgrounds