(1) Field of the Invention
The present invention relates to a parallel data processing apparatus which comprises a plurality of processors which are operated in parallel in synchronization with a common clock, and the operations of which are started upon receiving a common asynchronous request signal. Typically, the present invention can be applied to a single instruction stream multiple data stream (SIMD) type parallel data processing apparatus.
(2) Description of the Related Art
In the above parallel data processing apparatuses, the above asynchronous request signal may be an interrupt signal output from a host processor to the processors in the parallel data processing apparatus. For the parallel data processing apparatus to work properly, the above asynchronous request signal must be received (latched) at the same time to ensure a synchronous parallel operation of all of the processors. Conventionally, the lengths of signal lines for each of the asynchronous request signal and the clock signal from the output point thereof to the plurality of processors are designed to be the same (that is, equal-length wiring), so that the asynchronous request signal is received simultaneously in each of the plurality of processors.
The above equal-length wiring, however, imposes a very severe design requirement on the designer of the parallel data processing apparatus. Further, high accuracy timing of the operations of the plurality of processors cannot be achieved by the equal-length wiring. Therefore, the the clock signal cannot be increased to a high frequency in a parallel data processing apparatus designed to use the equal-length wiring because of the degraded accuracy of timing.
USPTO Backgrounds
USPTO Backgrounds