1. Field of the Invention
This invention relates to a switching power supply for generating DC voltage by switching, and more particularly to a switching power supply which is suitable for use in generation of DC voltage by a so-called synchronous rectification.
2. Description of the Related Art
Conventionally, a forward-type power supply 51 shown in FIG. 5 is well known as a switching power supply of the above-mentioned kind. The power supply 51 is comprised of a transformer 32 for use in switching, a capacitor 3, an FET 4, a diode 6, a switching control circuit 53, an FET 22 for use in synchronous rectification which incorporates a diode 23 as a body diode, an FET 54 similarly for use in synchronous rectification, a choke coil 25, and a capacitor 26. The capacitor 3, the FET 4, the diode 6, and the switching control circuit 53 are arranged on the side of a primary winding 32a and a reset winding 32c of the transformer 32, while the FET 22, the FET 54, the choke coil 25, and the capacitor 26 are arranged on the side of a secondary winding 32b and auxiliary windings 32d and 32e of the transformer 32. In the power supply 51, the switching control circuit 53 delivers to the gate of the FET 4 a switching signal S21 which is a PWM (Pulse-Width Modulation) signal for regulating the voltage across the capacitor 26.
When the input voltage is supplied to the power supply 51, the switching control circuit 53 delivers to the gate of the FET 4 the switching signal S21 with a repetition period set to a constant time period TSW and a high-level period controlled to an ON time period TON1 dependent on the input voltage and the output current. When the switching signal S21 is at the high level, the FET 4 is held in an ON state, allowing a current to flow through the primary winding 32a, whereby voltages V21 and V22 directed as shown in FIG. 5 are generated in the secondary winding 32b and the auxiliary winding 32d, respectively (see FIG. 6B). As a result, the positive voltage V22 is applied between the gate and the source of the FET 54, whereby the FET 54 is turned on. Consequently, a current I21 flows in a direction shown in FIG. 5 through a current path of the secondary winding 32b, the FET 54, the choke coil 25, and the capacitor 26, whereby the capacitor 26 is charged, and at the same time an output current is supplied to a load circuit, not shown. In this state, the transformer 32 is magnetized according to a predetermined B-H curve by the current flowing through the primary winding 32a, whereby exciting energy is accumulated in the transformer 32.
Subsequently, when the switching control circuit 53 changes the switching signal S21 from the high level to a low level, the FET 4 is turned off. At this time, the direction of the voltage V21 is reversed, so that the current I21 stops flowing. On the other hand, in the auxiliary winding 32e, a voltage V23 directed as shown in FIG. 5 is generated (see FIG. 6C), and the voltage V23,which is positive, is applied between the gate and the source of the FET 22, whereby the FET 22 is turned on. As a result, energy accumulated in the choke coil 25 causes a free-wheeling current I22 to flow through a current path of the choke coil 25, the capacitor 26, and the FET 22 (see FIG. 6D).
At the same time, a reset voltage V24 generated in the reset winding 32c causes a reset current I24 to flow in a direction shown in FIG. 5 through a current path of the reset winding 32c, the capacitor 3, and the diode 6, whereby the exciting energy accumulated in the transformer 32 is released from the same and regenerated in the capacitor 3. In this case, the reset voltage V24 is limited to a voltage value which is approximately equivalent to the input voltage.
When a reset time period TR1 which is dependent on the input voltage, the ON time period TON1 of the FET 4, etc. has elapsed, the release of exciting energy accumulated in the transformer 32 is completed, and the transformer 32 is reset. In this state, the voltage V23 ceases to be generated (see FIG. 6C), so that the FET 22 is turned off. As a result, in place of the current path including the source and the drain of the FET 22, and a free-wheeling current I23 flows through a current path of the choke coil 25, the capacitor 26, and the diode 23 within the FET 22 (see FIG. 6E).
In this case, assuming that the FET 22 has an ON resistance of 20 m.OMEGA. between its drain and source, a forward voltage of a general rectifying diode is 0.7 V, and the output current is 10A, the FET 22 has an ON voltage of 0.2 V between its drain and source, and hence power loss by the FET 22 is smaller than power loss by a rectifying diode. Therefore, the use of the FET 22 in place of the rectifying diode improves conversion efficiency of the power supply 51.
When the switching control circuit 53 changes the switching signal S21 from the low level to the high level in the following switching period, the above operations are carried out again. As described above, according to this power supply 51, electric power transmitted to the secondary winding 32b by switching the FET 4 is rectified synchronously by the FETs 22 and 54, whereby the conversion efficiency of the power supply 51 is enhanced.
However, the conventional power supply 51 suffers from the following problem: When the input voltage is increased, for instance, the conversion efficiency of the device 51 is degraded. More specifically, in this power supply 51, it is required to provide the reset time period TR1 for resetting the transformer 32 whenever the time period TSW as the switching period elapses. The reset time period TR1 is dependent on the input voltage and the ON time period TON1 of the FET 4. For this reason, when the input voltage is low, the ON time period TON1 is increased, and since the reset voltage V24 is decreased, the reset time period TR1 is required to be increased. Therefore, in order to ensure that the reset time TR1 is set within each of the time periods TSW even when the input voltage is low, it is required to increase each of the time periods TSW to some extent. In other words, switching frequency is required to be reduced to some degree. On the other hand, when the input voltage is high, the ON time period TON1 is reduced, and since the reset voltage V24 is increased, the reset time period TR1 is required to be reduced. Therefore, a ratio of a time period over which the free-wheeling current I23 flows through the diode 22 to the time period TSW is increased. As a result, in the conventional power supply 51, when the input voltage is high, power loss by the diode 23 with a forward voltage of approximately 1V is increased, which makes it impossible to reduce power loss by the power supply 51 to an expected degree despite of use of the synchronous rectification.
USPTO Backgrounds
USPTO Backgrounds