The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
FIG. 1 shows a cross-sectional view of a conventional sealing layer 112 for a field effect transistor 100 having a substrate recess 110. The field effect transistor 100 can be formed over a portion of the substrate 102. The field effect transistor 100 includes a gate structure 108 comprising a gate insulator 104 and a gate electrode 106 sequentially formed over the substrate 102, and the sealing layer 112 respectively formed on opposite sidewalls of the gate structure 108. However, problems arise when integrating the sealing layer 112 in a complementary metal-oxide-semiconductor (CMOS) process flow. For example, during the sealing layer 112 etching, a surface of the substrate 102 adjacent to the sealing layer 112 may be damaged and form a recess 110. Further, during subsequent implant processing, dopants distribution in active regions may be shifted. Thus, performance characteristics such as threshold voltage, capacitance overlay, and reliability may degrade.
Accordingly, what is needed is a sealing structure for a semiconductor device having no substrate recess.
USPTO Backgrounds
USPTO Backgrounds