Delay circuits are commonly used for a variety of purposes in integrated circuits to perform operations at predetermined times relative to the rising and falling edges of digital signals such as those found in clock signals, timing delay circuits, and oscillators. Examples of integrated circuits utilizing any number of such components include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by an external clock signal, and operations within the memory device typically must be synchronized to both the external operations and to components within the device itself. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. Although the present description is directed to memory devices, the principles described herein are equally applicable to other types of integrated circuits.
A typical delay circuit 100 for conventional memory devices is shown in FIG. 1. The delay circuit 100 provides a delay that varies according to changes in a supply voltage applied to the delay circuit 100 or as the temperature of the delay circuit 100 varies. While the design of the delay circuit 100 is relatively simple, designing one that can be set precisely to a required delay period that is constant over variations in voltage and temperature is difficult. The conventional delay circuit 100 of FIG. 1 includes a first delay stage 101 and a second delay stage 102. The total delay provided by the delay circuit 100 is the sum of the delay of the first delay stage 101 and the delay of the second delay stage 102. More delay stages may be connected to the delay circuit 100 to increase the total delay. The first delay stage 101 includes a PMOS transistor 134 and an NMOS transistor 136 having a drain connected to a drain of the PMOS transistor 134. The respective gates of the PMOS transistor 134 and the NMOS transistor 136 are connected to each other and receive an input signal VIN. The transistors 134, 136 function as an inverter having an output node 140. A supply voltage VCC connected to the delay circuit 100 at a node 150 is applied to a source of the PMOS transistor 134 through a PMOS transistor 132. Similarly, a source of the NMOS transistor 136 is connected to ground through an NMOS transistor 138. The PMOS transistor 132 and the NMOS transistor 138 are designed with a long channel length to provide a high resistance between the supply voltage and the PMOS transistor 134 and between the NMOS transistor 136 and ground, respectively. A capacitor 146 is connected to the output node 140 of the first delay stage 101 to increase the delay of the first delay stage 101. Each delay stage of the delay circuit 100 are configured in the same manner and function in the same way, however, in the interest of brevity only the first delay stage 101 is described in detail.
In operation, when VIN is low, the NMOS transistor 136 is turned OFF and the PMOS transistor 134 is turned ON to connect the supply voltage VCC to the capacitor 146 through the PMOS transistor 132. The capacitor 146 is then charged towards VCC with a delay that is determined by the time required for the capacitor 146 to charge through the PMOS transistor 132 to a threshold VCC/2 of the first stage 101. The delay is therefore essentially determined by the resistance of the PMOS transistor 132 and the capacitance of the capacitor 146. When VIN subsequently transitions from low-to-high, the PMOS transistor 134 is turned OFF and the NMOS transistor 136 is turned ON to connect the capacitor 146 to ground through the NMOS transistor 138. The capacitor 146 is then discharged towards ground with a delay that is determined by the time required for the capacitor 146 to discharge through the NMOS transistor 138 to a threshold VCC/2 of the second stage 102. Again, the delay is essentially determined by the resistance of the NMOS transistor 138 and the capacitance of the capacitor 146.
The delays provided by the first and second stages 101, 102, respectively, will be constant as long as the supply voltage VCC and the resistances of the transistors 132, 138 are constant. Unfortunately, the magnitude of the supply voltage VCC can vary, and the resistances of the transistors 132, 138 can vary with temperature. For example, the delay of the first delay stage 101 and the delay of the second delay stage 102 will decrease as the supply voltage is increased because the capacitor 146 will charge to the higher voltage more quickly and the higher voltage to which the capacitor 146 is charged will cause it to discharge more quickly. As a result, the total delay of the delay circuit 100 will decrease as the supply voltage increases and increase as the supply voltage decreases. The same effect will result as the temperature varies, since the charge current through the PMOS transistor 132 and the discharge current through the NMOS transistor 138 vary with the temperature induced changes in the resistances of the transistors 132, 138. These variations in the delay caused by variations in supply voltage and temperature are undesirable in integrated circuits that require constant delays to properly time internal operations and to synchronize circuits internal to integrated circuits with external signals.
Therefore, there is a need for a delay circuit to provide a constant delay that is independent of voltage and temperature variations.
USPTO Backgrounds
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