Semiconductor memory devices for storing data can typically be categorized as either volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their stored data when their power supplies are interrupted, however nonvolatile memory devices retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are widely used in applications where the possibility of power supply interruption is present.
Conventional nonvolatile memory devices include a type of electrically erasable programmable read only memory (EEPROM) device typically referred to as a flash EEPROM device. Flash EEPROM devices typically include a semiconductor substrate of first conductivity type (e.g., P-type), spaced source and drain regions of second conductivity type (e.g., N-type) in the substrate, a channel region at a face of the substrate, between the spaced source and drain regions, a floating gate for storing charge carriers when the device is programmed and a control gate which overlies the floating gate, opposite the channel region. Operation of a flash EEPROM device is typically divided into three modes including programming, erasing and reading.
Programming of a flash EEPROM device is typically achieved by biasing the drain region to a first positive bias, relative to the source region, and biasing the control gate to a second positive bias which is greater than the first positive bias. In the absence of any stored charge on the floating gate, these biases cause the formation of an inversion-layer channel of electrons at the face of the substrate, between the source and drain regions. As will be understood by those skilled in the art, the drain-to-source voltage accelerates these electrons through the channel to the drain region where they acquire sufficiently large kinetic energy and are typically referred to as "hot" electrons. The larger positive bias on the control gate also establishes an electrical field in a tunneling oxide layer which separates the floating gate from the channel region. This electric field attracts the hot electrons and accelerates them toward the floating gate, which is disposed between the control gate and the channel region, by a process known as tunneling. The floating gate then accumulates and traps the accumulated charge. Fortunately, the process of charging the floating gate is self-limiting. The negative charge that accumulates on the floating gate reduces the strength of the electric field in the tunneling oxide layer to the point where it is no longer capable of accelerating "hot" electrons from the drain side of the channel region.
As will be understood by those skilled in the art, the accumulation of a large quantity of trapped charge (electrons) on the floating gate will cause the effective threshold voltage (V.sup.th) of the field effect transistor comprising the source region, drain region, channel region and control gate to increase. If this increase is sufficiently large, the field effect transistor will remain in a nonconductive "off" state when a predetermined "read" voltage is applied to the control gate during a read operation (i.e., V.sub.th &gt;V.sub.read). In this state, known as the programmed state, the EEPROM device may be said to be storing a logic 0. Once programmed, the EEPROM device retains its higher threshold voltage even when its power supply is interrupted or turned off for long periods of time.
Reading of the EEPROM device is achieved by applying a predetermined read voltage (V.sub.read) to the control gate, typically via a word line connecting a row of identical EEPROM devices or "cells", and applying a positive bias to the drain region, typically via a bit line connecting a column of identical EEPROM cells. If the EEPROM device is programmed, it will not conduct drain current (I.sub.ds). However, if the EEPROM device has not been programmed (or has been erased), it will heavily conduct. In this state, the EEPROM device may be said to be storing a logic 1. Thus, by monitoring the bit line current, the programmed state (i.e., 1 or 0) of the EEPROM device can be determined.
Erasing of the EEPROM device may also be achieved by removing the stored charge from the floating gate. The erasure process can be achieved, for example, by grounding the control gate and applying a positive bias to the substrate (e.g., 10-20 Volts). Accordingly, flash EEPROM devices typically require bulk erasure of large portions of an array of cells since the effects of applying a large substrate bias typically cannot be confined to a single EEPROM cell.
Although the above-described memory cells have been described as two-state devices having only one erased and one programmed state, accurate control of the threshold voltages of an EEPROM cell can be utilized to provide a multi-bit memory device having more than two states. For example, rather than just an erased state where Vth.ltoreq.-3V and a programmed state where Vth.gtoreq.1V, an EEPROM memory cell may be carefully programmed to have four (4) states, for example, where a Vth.ltoreq.-2V represents state "11", Vth=-1 represents state "10", Vth=0V represents state "01" and Vth=1V represents state "00". Thus, an EEPROM memory cell can be programmed as a two-bit device instead of just a one-bit device to advantageously double the amount of information an EEPROM memory cell may contain. Exemplary integrated circuit memory devices containing multi-bit cells therein are described in U.S. Pat. No. 5,566,125 to Fazio et al. entitled Method and Circuitry for Storing Discrete Amounts of Charge in a Single Memory Element and U.S. Pat. No. 5,550,772 to Gill entitled Memory Array Utilizing Multi-State Memory Cells.
An integrated circuit memory device containing multi-bit cells therein is also described in an article by M. Bauer et al. entitled A Multilevel-Cell 32 Mb Flash Memory, ISSC Digest of Technical Papers, pp. 132-133, February (1995). In the Bauer et al. article, a memory cell array is arranged in a NOR-type arrangement. Each memory cell is capable of storing one of four states with two bits such as "00", "01", "10" and "11". Each of the four states corresponds to a unique voltage level, e.g., "00"=2.5V, "01"=1.5V, "10"=0.5V and "11"=-3V. The voltage levels are stored as threshold voltages of the cells.
To detect a state of a multi-bit memory cell, a read voltage having a level interposed between a threshold voltage level (or positioned on a lower side or a higher side from the level of a threshold voltage) must be applied to gates of the memory cells through a word line coupled thereto. Here, the width between adjacent threshold voltages (hereinafter referred to as the threshold voltage "window") is less than in a normal flash memory. For example, the window in a four-state flash memory is about 0.6V. Furthermore, when a word line voltage for reading is located in the window of about 0.6V, the margin from an edge of the threshold voltage profile and the level of the word line voltage may be not more than about 0.3V. Therefore, if a multi-bit flash memory is made with accompanying variations in the manufacturing process or influenced by variations in word line voltage level and temperature, the possibility of experiencing an invalid sensing operation (i.e., read operation) is increased. Such weak immunity against variations in external conditions typically limits the utility of these multi-bit devices to the storage of mass information such as audio data, where memory loss or corruption of small amounts of data does not significantly affect the fidelity of the information when read as a whole. Moreover, even though the advantages of the normal single-bit and newer multi-bit flash memories are well known, the two types of flash memories are typically fabricated on separate semiconductor chips.
Thus, notwithstanding the above described techniques for improving the capacity of an integrated circuit memory device by employing multi-bit memory devices therein, there continues to be a need for improved memory devices which can advantageously use multi-bit devices therein.
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