1. Field of the Invention
The present invention generally relates to a driving apparatus, in particular, to a shift register apparatus and a shift register thereof in a driving apparatus.
2. Description of Related Art
FIG. 1 illustrates a conventional shift register, namely, a Thomson circuit, in a driving apparatus. The shift register includes NMOS (N-type metal oxide semiconductor) transistors 102˜108 and capacitors 110 and 112. The “IN”, “OUT”, “RES”, and “COM” respectively represent an input signal, an output signal, a reset signal, and a common voltage, and the “CLK1” and “CLK2” respectively represent two different clock signals.
The input signal IN is a pulse signal. The pulse enable durations of the input signal IN and the clock signal CLK1 are the same, and the pulse enable durations of the clock signals CLK1 and CLK2 are different. When the clock signal CLK1 is at a high voltage level and the clock signal CLK2 is at a low voltage level, the shift register sustains the gate voltage of the NMOS transistor 104 with the capacitors 110 and 112 in order to maintain the turned-on status of the NMOS transistor 104, so that the output signal OUT can be output when the clock signal CLK2 is turned to a high voltage level.
FIG. 2 illustrates a conventional shift register apparatus. The shift register apparatus is broadly applied to liquid crystal displays (LCDs), for example, as the gate driver in a LCD. Referring to FIG. 2, the shift register apparatus includes shift registers 201˜N+1 as illustrated in FIG. 1. In FIG. 2, “IN” represents an input signal, OUT(1)˜OUT(N) respectively represent the output signals of the shift registers 201˜N, and “CLKS1” and “CLKS2” respectively represent two different clock signals. In each shift register, “IP” denotes the input terminal of the circuit in FIG. 1 for receiving the input signal IN, “RP” denotes the input terminal of the circuit in FIG. 1 for receiving the reset signal RES, “CLK1P” denotes the input terminal of the circuit in FIG. 1 for receiving the clock signal CLK1, and “CLK2P” denotes the input terminal of the circuit in FIG. 1 for receiving the clock signal CLK2.
In such a shift register apparatus, the reset signal of each shift register is the output signal of the next shift register. Accordingly, N+1 shift registers are required even though only N output signals are provided in the shift register apparatus.
As described above, the shift register apparatus described above has to use an extra shift register, therefore the size thereof is large and the fabrication cost thereof is high.
USPTO Backgrounds
USPTO Backgrounds