1. Field of the Invention
The present invention generally relates to power supply adjusting circuits and semiconductor devices using these circuits, and more particularly to a power supply adjusting circuit and a semiconductor device using a power supply adjusting circuit generating a plurality of internal power supplies based on an external power supply.
2. Description of the Related Art
In recent years, semiconductor devices such as Dynamic Random Access Memories (DRAMs) and the like have been manufactured with high density and high speed. In order to support this trend, parts used therein such as transistors, diodes, resistances, condensers and so on are required to be scaled down and operating voltages applied thereon are required to be lower.
For example, a DRAM semiconductor device causes a power supply adjusting circuit thereof to generate an internal step-down voltage Vii (for example, Vii=2.5V) based on an external voltage VDD (for example, VDD=3.3V) and supplies the internal step-down voltage Vii to internal circuits therein. The internal step-down voltage Vii is, however, subject to deviation from a design voltage due to dispersion of element characteristics caused during the manufacturing of the semiconductor device. The power supply adjusting circuit usually corrects such deviation by adjusting fuse boxes thereof.
FIG. 1 is a diagram showing a configuration of a conventional power supply adjusting circuit.
As shown in this diagram, the conventional power supply adjusting circuit includes a plurality of fuse boxes 10, a test register 11, a switch circuit 12, an internal reference power supply circuit 13, an internal step-down power supply circuit 14, and an internal step-up or boosted voltage generating circuit 20 generating an internal step-up voltage VPP.
The internal step-up voltage generating circuit 20 further includes a reference voltage generating circuit 21, a voltage dividing circuit 22, a comparator 23, an internal step-up voltage control circuit 24, and a charge pump 25.
The fuse boxes 10 and the test register 11 are connected to the internal reference power supply circuit 13 via the switch circuit 12. The switch circuit 12 switches between being connected to the fuse boxes 10 in a normal mode and being connected to the test register 11 in a test mode. The switch circuit 12 receives setting signals "a" from the fuse boxes 10 in the normal mode or setting signals "b" from the test register 11 in the test mode, and sends them to the internal reference power supply circuit 13.
According to the setting signals "a" or "b", the internal reference power supply circuit 13 generates an internal reference voltage Vrf from an external voltage VDD and supplies the internal reference voltage Vrf to the internal step-down power supply circuit 14.
According to the internal reference voltage Vrf, the internal step-down power supply circuit 14 generates an internal step-down voltage Vii, which is adjusted by adjusting the internal reference voltage Vrf.
First, the internal step-down voltage Vii is adjusted in the test mode such that the setting signals "b" are supplied to the internal reference power supply circuit 13 from the test register 11 and are adjusted by adjusting a setting of the test register 11 until the internal step-down voltage Vii reaches an optimum value. At this time, if the fuse boxes 10 are adjusted so as to correspond to the setting of the test register 11, the internal step-down voltage Vii can be adjusted to reach an optimum value in the normal mode. As a result, the internal step-down voltage Vii is thus adjusted to reach its optimum value.
In general, a semiconductor device generates other internal voltages besides the above-mentioned internal step-down voltage Vii. For example, the internal step-up voltage generating circuit 20 receives the internal reference voltage Vrf and generates the internal step-up voltage VPP.
Specifically, when receiving the internal reference voltage Vrf, the reference voltage generating circuit 21 generates an internal reference voltage Vpref1 and supplies it to the comparator 23. The comparator 23 compares the internal reference voltage Vpref1 to a divided voltage VPP' obtained by dividing the internal step-up voltage VPP in the voltage dividing circuit 22 so as to send a comparison result VPPSZ to the internal step-up voltage control circuit 24. The VPP control circuit 24 controls the charge pump 25 according to the comparison result VPPSZ so as to make the internal step-up voltage VPP reach its optimum value.
In addition, configurations of the voltage dividing circuit 22 and the comparator 23 can be understood from FIG. 2.
The conventional power supply adjusting circuit generates, however, the internal step-down voltage Vii and the internal step-up voltage VPP based on the one internal reference voltage Vrf. In other words, since the internal step-down voltage Vii and the internal step-up voltage VPP are varied according to the internal reference voltage Vrf, a problem occurs in that relative adjustment between the internal step-down voltage Vii and the internal step-up voltage VPP cannot be made.
For example, in the case of correcting the voltage deviation caused by the dispersion of the element characteristics in the semiconductor device manufacturing, it is impossible for the internal step-down voltage Vii and the internal step-up voltage VPP to be adjusted independently.
USPTO Backgrounds
USPTO Backgrounds