1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
In a non-volatile memory cell, typically an NAND-type flash memory, writing is performed by applying a high electric field to trap electrons in an oxide film to vary the threshold of the cell, and reading is performed with the use of a difference in threshold thereof. In recent years, a multivalue storage technology to store data of two or more bits in a single memory cell came in to use. This makes it possible to increase the memory capacity by several times in the same physical cell size.
The conventional reading in the NAND-type flash memory first includes charging a precharge voltage on a bit line. A read voltage is then applied to a read-desired word line, and an ON-enabling voltage is applied to other word lines. Thereafter, an ON-enabling voltage is also applied to a selection transistor located between the bit line and the NAND-type flash memory. In this case, if the read-desired cell is kept ON, a cell current flows therein to lower the voltage on the precharged bit line. To the contrary, if it is kept OFF, no cell current flows therein, and the bit line is kept at the precharged voltage. The voltage precharged on the bit line is identified to determine H/L of the memory cell. The threshold of the memory cell varies depending on the temperature and thus it has a temperature characteristic. Therefore, when a constant voltage is applied to a selected word line in the NAND-type flash memory for reading, a deviation arises depending on the temperature and accordingly the read-desired data may not be read out. Therefore, in the conventional art, a temperature characteristic is imparted to the selected word line so that the voltage applied to the selected word line on reading is varied depending on the temperature to read data out of the memory cell. (See JP 2002-170391, on page 11, FIG. 1, for example).
If the temperature characteristic is imparted to the selected word line and the voltage is applied thereto as above, there are needs for a voltage set for reading or verifying, a process of trimming the voltage and, in the case of multivalue, a temperature characteristic-imparted voltage per threshold distribution. Further, in a binary or higher multivalue memory cell, a circuit is required to generate read voltages with temperature characteristics imparted thereto in accordance with the number of multiple values. This causes a problem because the circuit scale becomes too large and trimming can not be performed. cl SUMMARY OF THE INVENTION
In an aspect the present invention provides a semiconductor memory device, comprising: a memory cell array of a plurality of memory cell units, each memory cell unit including a plurality of serially connected memory cells formed on the same well region, each memory cell having a floating gate and a control gate stacked, said serially connected memory cells having one end serially connected to a first selection gate transistor, said serially connected memory cells having the other end connected to a common source line via a second selection gate transistor; a sense amp connected to one end of said first selection gate transistor via a bit line and operative to read data out of said memory cell array; and wherein a voltage applied to said well region and said source line varies to cancel a change of threshold of said memory cells depending on the temperature.
USPTO Backgrounds
USPTO Backgrounds