A general trend of modern day electronic product, as demanded by the market place, is product miniaturization while maintaining its functionality and low cost. With no exception, the same trend also applies to the segment of power semiconductor devices. Here, reducing numerous parasitic impedances accompanying the device packaging environment can be very important as these parasitic impedances usually contribute to undesirable degradation of device performance such as reduced power conversion efficiency and/or increased noise emission from its associated power electronic circuits.
There were numerous prior arts directed to low-resistance, low-inductance power semiconductor device packaging. U.S. Pat. No. 6,841,852 by Luo et al, as illustrated in FIG. 1, described an integrated circuit IC package with a leadframe 108 that includes a leadframe pad 103a disposed under a die 100 and a bonding metal area 101a disposed over at least two adjacent sides of the die. An increase in the bonding metal area 101a increases the number of source bond wires 104 between the metal area 101a and the die 100 to reduce the parasitic electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body 106 is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The IC die 100 is applicable for MOSFET devices and the bonding metal area 101a is used for the source terminal 101. The bonding metal area 101a may be implemented with a variety of shapes.
While, as shown, the use of multiple parallel short source bond wires 104 can somewhat reduce the parasitic impedance (in this case resistance and inductance), the use of short wires alone can still result in an overall higher parasitic impedance as the source current flow now tends to be limited by the on-die interconnections and, under standard foundry IC processes, the thickness of these on-die interconnections is typically very thin. Thicker on-die interconnections are expensive and may require non-standard foundry processes that are highly undesirable. On the other hand, limiting die size to achieve a correspondingly reduced parasitic impedance attributable to these on-die interconnections can end up lowering the overall device performance such as its power handling ability.
U.S. Pat. No. 5,767,567 by Hu et al, entitled “Design of device layout for integration with power MOSFET packaging to achieve better lead wire connections and lower on resistance” and as illustrated in FIG. 2, disclosed a MOSFET power IC device 100 formed in a semiconductor chip including numerous source contact areas 150-1, 150-2, 150-3, and 150-4 for connecting to a lead-frame 120 via numerous lead-wires 135, 160. The power IC device 100 includes many lead-wire contact points 170 on the source contact areas 150-1, 150-2, 150-3, and 150-4 for securely attaching the lead wires 160 onto the source contact areas. These lead-wire contact points 170 are uniformly distributed substantially over the source contact areas to reduce the spread resistance thus improving the device on-resistance and device performance.
As the deployment of uniformly distributed lead-wire contact points 170 substantially over the source contact areas 150-1, 150-2, 150-3, and 150-4 requires, for reaching distant regions of the source contact areas, using some long bond wires with correspondingly higher resistance and higher inductance, this approach still results in an overall higher parasitic impedance. On the other hand, limiting die size to achieve a correspondingly reduced parasitic impedance attributable to these long bond wires can end up lowering the overall device performance such as its power handling ability.
U.S. application Ser. No. 11/226,913 by Ho at al and U.S. application Ser. No. 11/544,453 by Sun et al disclosed semiconductor device package having plate interconnections. These are briefly shown in partial sectional perspective view in FIG. 3A, cross sectional view taken along line 2-2 in FIG. 3B and cross sectional view taken along line 3-3 in FIG. 3C. As shown in FIG. 3B, while the bottom of a power semiconductor die 120 is directly bonded to a drain contact portion 107 of leadframe, the top of the power semiconductor die 120 is connected to a source contact portion 110 of a leadframe with a patterned source plate 125 in lieu of bond wires. Likewise in FIG. 3C, while the bottom of the power semiconductor die 120 is directly bonded to a drain contact portion 107 of leadframe, the top of the power semiconductor die 120 is connected to a leadframe gate contact area 115 with a patterned gate plate 137, in lieu of bond wires, having a locking ball 155 mechanism for the patterned gate plate 137 to clip on thus further facilitate the packaging process. The encapsulant 135 just covers up all environmentally sensitive parts for long term device reliability.
The plate-connection package as disclosed above is a high-performance package as it is characterized by:                lower cost since a single plate, instead of multiple bond wires, is used to connect regions;        low parasitic resistance and inductance since device current is well distributed throughout the plate cross section; and        high production through put since a matrix type clip attachment can be devised to handle simultaneous packaging of multiple device dies.        
However, the drawback of the plate-connection package is its cost and need for non-standard tooling to attach the plates and the plates themselves must be customized to the package and die. Also, this is a post-wafer, packaging-level process dealing with already separated dies, which implies much higher cost compared to an otherwise wafer-level process. In conclusion, there exists a need of major reduction of device packaging related parasitic impedance with a high-performance/low cost package that is compatible with the standard wafer-level process and that requires no non-standard tooling.
USPTO Backgrounds
USPTO Backgrounds