1. Field of the Invention
This invention relates to a heterojunction bipolar transistor and its integration method and its manufacturing method.
2. Description of the Prior Art
Heterojunction bipolar transistors (HBT) have attracted a great degree of attention as the next generation of very-high speed devices which enjoy large current driving capabilities and excellent high frequency characteristics. In his article "Heterojunction Bipolar Transistors and Integrated Circuits," Proc. IEEE., Vol. 70, P. 13, 1982, H. Kroemer reported that the collector top type of heterojunction bipolar transistors HBT with a collector on the top of the devices are more favorable than the conventional emitter top type heterojunction bipolar transistors HBT with an emitter on the top thereof, because the former provides ease of implementing of high gain and high speed Integrated Injection Logic (I.sup.2 L) reduction of the area of base collector junctions, highly reliable high frequency performance, ease of implementing of grounded-emitter circuits, and so forth.
Of the collector top type heterojunction bipolar transistors, heterojunction bipolar transistors with a symmetric structure where the collector is also made up of a wide-gap material in relation with the base are in greatest demand, because they are beneficial to the application of I.sup.2 L and Emitter Coupled Logic (ECL) circuits. This is especially due to the capability to execute not only collector top performance but also emitter top performance. A feature of I.sup.2 L gates that the need of an isolation region may be eliminated by reversing the roles of the emitter and the collector in the conventional npn bipolar transistor to permit use as emitter-ground circuit and commonly using a n.sup.+ type substrate and that fundamental gates may be implemented without resistors by using pnp bipolar transistors as a current injection source. I.sup.2 L gates are, therefore, thought to meet high density and low power consumption requirements. As a matter of fact, I.sup.2 L gates were proposed where the collector top type or symmetric structure npn heterojunction bipolar transistors (HBT) are used as switching transistors and lateral pnp bipolar transistors (BT) as a current injection source, in an attempt to develop high gain, high speed and easy-to-manufacture I.sup.2 L gate integrated circuits.
P. M. Asbeck et al. reported in their article "GaAlAs/GaAs Heterojunction Bipolar Transistor Device and IC Technology for High-Performance Analog and Microwave Applications," IEEE Trans. Microwave Theory Tech., Vol. 37, P. 2032, 1989, that ON voltages of the base-to-emitter diodes of AlGaAs/GaAs heterojunction bipolar transistors were 1.35 V and about 60% higher than those of Si bipolar transistors (about 0.8 V), causing the problem of an increase in power dissipation.
H. Kroemer pointed out in his report problems with integration of the conventional heterojunction bipolar transistors that element-to-element wirings are complex and the necessity of isolation regions between individual transistors hampers higher density integration.
A first prior art heterojunction bipolar transistor proposed by H. Kroemer was to implement heterojunction bipolar transistors with a symmetric structure. This sort of bipolar transistor was also reported by S. Tiwari et al. in "Symmetric-Gain, Zero-Offset, Self-Aligned, and Refractory-Contact Double HBT's," IEEE Electron Device Lett., Vol. 9, P. 417, 1987. FIG. 12 is a cross-sectional view of a first conventional symmetric structure NpN type heterojunction bipolar transistor device. Disposed on a semi-insulating GaAs substrate 21 is an epitaxial growth structure which consists of a first contact layer 22 of highly doped n type GaAs, a collector or emitter layer 23 of n type AlGaAs, a base layer 24 of highly doped p type GaAs, a collector or emitter layer 25 of n type AlGaAs and a second contact layer 26 of highly doped n type GaAs stacked sequentially on the named order.
To form a base electrode, a portion of the second contact layer 26 and a portion of the emitter or collector layer 25 which are located on an external base region are removed by a wet etching technology using a solution of sulfuric acid and hydrogen peroxide or the like or the dry etching technology using chlorine gas or the like. Be ion implantation step completes the setup of the external base region 24a. An interelement isolation region 27 and an interelement isolation 28 are defined by implanting boron and proton ions, respectively. The final step is to deposit a collector/emitter electrode 9a, the base electrode 9b and an emitter/collector electrode 9c.
A second heterojunction bipolar transistor as discussed hereinafter was proposed as a solution to the second problem in an attempt to lower the ON voltage of the base-to-emitter diode. FIG. 13 is an energy band diagram of the second prior art heterojunction bipolar transistor which is typically an NpN type heterojunction bipolar transistor of an InGaAs/InAlAs system disposed with lattice matching on an InP substrate. This device structure comprises a grading layer which helps in reducing the ON voltage of the base-to-emitter diode. The illustrated structure includes an emitter 133 of n type In.sub.x Al.sub.1-x As (x=0.52), a base 144 of p type In.sub.x Ga.sub.1-x As (x=0.53) and a collector 155 of n type In.sub.x Ga.sub.1-x As (x=0.53). Particularly, the grading layer 133a is disposed between the emitter 133 and the base 144, the composition of which varies continuously from n type In.sub.x Al.sub.1-x As (x=0.52) to n type In.sub.x Ga.sub.1-x As (x=0.53). It is evident from FIG. 7 which shows an energy band diagram, that a barrier V against carriers between the base 144 and the emitter 133 (i.e., electrons) becomes lower due to the presence of the grading layer 133a, so that the built-in voltage of the diode becomes smaller and the ON voltage becomes lower.
In the first prior art symmetric structure heterojunction bipolar transistor as depicted in FIG. 12, the difference between the ON voltage of the external base 24a and the emitter 23 and the ON voltage of the diode between the internal base 24 and the emitter would be as low as 0.3 V in view of the materials used therein. Therefore, the diode between the external base 24a and the emitter 23 would turn On at high collector current densities of over several 10.sup.4 A/cm.sup.2, thereby developing an abrupt drop in current gain.
To suppress Be diffusion during the step of high temperature annealing by which the crystalline statue is recovered after ion implantation, it is necessary to keep the Be doping concentration between 3 and 5.times.10.sup.18 /cm.sup.3. Should Be be doped at a higher concentration than the specified scope, Be would be diffused during the annealing step so that the n type AlGaAs 23 would turn into p type and the heterojunctions between the p type GaAs 24 and the n type AlGaAs 23 and 25 would be destroyed with the accompanying development of a homojunction between the n type AlGaAs and the p type AlGaAs with a lower efficiency of carrier injection. As a consequence, the first prior art heterojunction bipolar transistor can not sufficiently lower the base resistance as compared with the emitter top type so that it may not take full advantage of the excellent high frequency characteristics of the collector top type transistor.
As mentioned above, to make smaller the built-in voltage of the base-emitter junction, the second prior art heterojunction bipolar transistor has the grading layer the composition of which varies continuously from In.sub.x Al.sub.1-x As (x=0.53) to In.sub.x Ga.sub.1-x As (x=0.52). In essence, the manufacturing of such grading layer which matches in lattice with the InP substrate is very difficult.
To improve integration density, an I.sup.2 L gate was proposed which uses a heterojunction bipolar transistor, in an article "Double Heterojunction GaAs/GaAlAs I.sup.2 L Inverter," by P. Narozy et al, Electron. Lett., Vol. 21, P. 328, 1985. FIGS. 14(A) and 14(B) show an equivalent circuit diagram and a cross sectional view of the I.sup.2 L gate device reported therein, respectively. There is disposed an epitaxial layered structure on a semi-insulating GaAs substrate 111, which structure consists of a first contact layer 112 of highly doped n type GaAs, an emitter layer 113 of n type AlGaAs, a base layer 114 of highly doped p type GaAs, a collector layer 115 of n type GaAs and a second contact layer 116 of highly doped n type GaAs, sequentially deposited in the named order. To form a collector mesa structure, the second contact layer 116 and the collector layer 115 are removed partially for a buildup of an external base region by the wet etching technology using a solution of sulfuric acid and hydrogen peroxide or the like or the dry etching technology using chlorine gas or the like. The subsequent Be ion implantation and thermal treatment for recovery of crystalline state result in buildup of the external base region of an npn heterojunction bipolar transistor and buildup of a collector region 114a or an emitter region 114b of a lateral pnp bipolar transistor. After formation of a base mesa structure through the use of the same etching technology as mentioned above, a base electrode of the heterojunction bipolar transistor or a collector electrode 110a of the lateral bipolar transistor, an emitter electrode of the heterojunction bipolar transistor or a base electrode 110b of the lateral bipolar transistor, an emitter electrode 110c of the lateral bipolar transistor and a collector electrode 110d of the heterojunction bipolar transistor are deposited, respectively. Measurements at high collector current densities revealed that the external base-emitter diode turned ON in the above mentioned materials at high collector current densities over several 10.sup.4 A/cm.sup.2, causing a sharp drop in current gain, because the difference between the ON voltage of the external base-emitter diode and the ON voltage of the intrinsic base-emitter diode was as low as 0.2 V-0.3 V in the collector top type npn heterojunction bipolar transistor used in the prior art I.sup.2 L gate device. As discussed above, to suppress Be diffusion during the step of high temperature annealing by which the crystalline state is recovered after ion implantation, it is necessary to keep the Be dopings between 3 and 5.times.10.sup.18 /cm.sup.3. As a consequence, the prior art collector top type heterojunction bipolar transistor can not sufficiently lower the base resistance as compared with the emitter top type so that it may not take full advantage of the excellent high frequency characteristics of the collector top type transistor. The hole mobility of the AlGaAs layer which forms the base of the lateral pnp bipolar transistor is as low as 100 cm.sup.2 /V sec and the diffusion length of the minority carriers is as low as about 0.5 .mu.m. To assume sufficient current gain, the thickness of the base needs to be less than 0.1 .mu.m. The profile of the p type AlGaAs intervening between the collector and emitter regions of the n type AlGaAs corresponds to the thickness of the base and needs to be less than about 0.1 .mu.m. Such requirement is difficult to meet even when the state-of-art technology is utilized.
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