1. Field of the Invention
The invention relates to microprogrammable digital computers, particularly with regard to the basic architecture thereof.
2. Description of the Prior Art
Present day computer architectures are primarily designed utilizing random logic, i.e., providing specific logic circuits for performing the various required functions. Another approach to computer design is that of microprogramming where the macro instructions of the computer repertoire are performed via microinstruction routines stored in the computer microcontrol memory. Generally, everything else being equal, the random logic approach provides a significantly faster computer than the microprogrammed design but the microprogrammed approach tends to provide a computer that is smaller and less expensive than the computer designed utilizing random logic. This is because, in general, computers designed utilizing microprogramming require less hardware than those designed with random logic. Additionally, the microprogrammed architecture generally lends itself more to the use of large scale integrated circuits (LSI) than do random logic computers where generally small scale (SSI) and medium scale (MSI) integration is utilized. For a given functionality LSI circuits tend to be smaller and less expensive than their SSI and MSI counterparts.
The microprogrammed computer tends to be more flexible than a computer designed utilizing random logic in that the instruction repertoire of the microprogrammed machine can be conveniently altered by changing the stored micro routines utilized in effecting the macroinstructions of the computer repertoire. Microprogramming has also been utilized in the prior art for emulating an existing computer. Generally for similar construction technologies the microprogrammed emulator will be substantially slower than the emulated machine.
Independently of the above considerations, microprocessor chips and slices are coming into widespread usage in implementing low speed, small capacity computation devices such as portable calculators and small scale, special purpose computers. Microprocessor chips and slices provide a substantial amount of computation and logic functionality on a single chip for a relatively low cost. Heretofore microprocessors have not generally been utilized in implementing large scale high speed computers of the main frame type which have relatively long data and instruction words (generally 32 bits or greater) primarily because of the problems associated with the microprocessor chip inputs and outputs and interconnections thereof with respect to utilizing the chip functionality in the main frame computer environment.
Specifically, micro programmed computers have been considered in the prior art which utilize horizontal micro programming. In such computers, the ALU is constructed utilizing random logic in accordance with the basic discrete computer resources required such as an adder, gates, registers and the like. Each such computer resource is generally controlled by a single bit of the horizontal micro control word.
Although the same functionality is obtainable with present day micro processor chips and slices as is provided by the random logic ALU of the horizontally micro programmed computer, access into the discrete resources of the chip is not available utilizing commercial micro processor components since such components are generally designed for sequential performance of the various chip functions. Thus as discussed above, LSI micro processor chips and slices have not heretofore been successfully utilized in main frame computer design.
It is an object of the present invention to provide a computer architecture utilizing micro programming for effecting a high speed, high capacity, large scale computer with reduced size and cost compared to prior art arrangements.
It is a further object of the present invention to preferably utilize LSI micro processor type components in implementing the computer.
It is a further object of the present invention to provide a main frame computer design utilizing LSI implementation with significantly enchanced cost effectiveness and performance compared to prior art arrangements.
It is a further object of the present invention to provide a micro programmed emulator, utilizing LSI construction, of a main frame series computer with significantly superior cost effectiveness and performance with respect to the machine emulated.
USPTO Backgrounds
USPTO Backgrounds