(1) Field of the Invention
This invention relates to monitoring and diagnostics of line processes used for the manufacture of semiconductor devices and more particularly to the measurement of gate insulator defect densities and the plasma antenna effect.
(2) Description of Prior Art
In the manufacture of highly dense integrated circuits using Metal Oxide Semiconductor(MOS) technology with multiple metal layers, electrical charge may build up at the device gate oxide during plasma processing. The charge accumulates on large areas of metal or conductive polysilicon during pattern definition by plasma etching. The exposed metal areas act as antennas, accumulating charge from the plasma and thereby developing a high electrical potential across the gate oxide. Initial exposure occurs during the patterning of the polysilicon gate electrodes.
After the gate oxide layer is formed it is covered with a layer of polysilicon within which the gate electrode is defined. The etching of this polysilicon layer is accomplished by reactive ion etching (RIE), providing the first in a series of exposures of the edge of the polysilicon gate electrode to an rf plasma. In this instance the area of the gate electrode is covered with photoresist. As etching proceeds the large area of exposed polysilicon provides sufficient ballast to prevent local charge build-up. However, as the endpoint is approached, the polysilicon layer breaks up and the residual, now isolated, regions of polysilicon surrounding the photoresist protected gate electrode act as an antenna which accumulates charge. This results in the development of a potential sufficiently high to cause current flow through the gate oxide.
The polysilicon halos surrounding the photoresist covered gate can present a high antenna-to-gate oxide area ratio causing massive current flow in the oxide. As etching proceeds, the halos of polysilicon disappear and the antenna area is reduced to the thin edges of the gate electrode itself. After pattern formation is completed, the residual photoresist is removed by plasma ashing, again exposing the gate insulator to excessive current flow. This scenario is repeated during subsequent processing steps where metal layers, electrically connected to the polysilicon gate structures, are etched with rf plasmas.
The mechanism of current flow though the gate oxide is primarily Fowler-Nordheim(FN) tunneling. FN tunneling occurs at fields in excess of 10 MV/cm. Charge build up on the gate electrode resulting in a gate electrode potential of only 10 volts is therefore sufficient to induce FN tunneling through an oxide layer of 100 Angstroms. Such potentials are readily achieved in conventional plasma reactors. Excessive FN tunneling currents eventually lead to positively charged interface traps in the oxide which may lead to subsequent dielectric breakdown.
Large area capacitors, widely used for monitoring defects in the oxide layer, seriously over-estimate the density of shorts because of oxide stressing by plasma etching and ashing. This is pointed out by Shin et.al. in "Thickness and other Effects on Oxide and Interface Damage by Plasma Processing"(published in the 1993 IEEE International Reliability Physics Proceedings, pp 272-279). It is shown that plasma damage depends upon the area of aluminum conductor exposed to the plasma and not on the area of the gate oxide involved in the discharge path. Thus the use of large area aluminum pads, exposed to plasma processing, for evaluating oxide defect densities can grossly under-state the oxide quality.
Several method have been developed which reduce the exposure of conductive antennae to plasma radiation. In one such method, Ko, et.al. U.S. Pat. No. 5,434,108, the metal conductors are grounded by connections which are severed after the plasma exposure. In Ko, et.al. U.S. Pat. No. 5,393,701, the large area metal pads are deposited but not in connection with the sensitive MOS gates. After forming an insulative layer over the pads, a second metal deposition with reduced metal to plasma exposure, makes connection between the large area pads and the polysilicon gates through vias in the insulative layer.
Hong and Ko U.S. Pat. No. 5,350,710 describe an anti-fuse element which isolates large metal pads from sensitive MOS elements during plasma processing. Afterwards the anti-fuse element is made conductive by the application of voltage pulses.
Measuring and monitoring damage to gate oxides by plasma exposure requires the use of test structures which may be formed on special test wafers or designed into regions of the wafer saw kerf area where they are tested by probing prior to dicing. Such structures are disclosed by this invention.
USPTO Backgrounds
USPTO Backgrounds