1. Technical Field
The present invention generally relates to display technology fields and, particularly to a display device and a driving method of gate control lines in which driving signals for the gate control lines are single-pulse signals.
2. Description of the Related Art
Display devices such as a liquid crystal display (LCD) and a plasma display have the advantages of high image quality, small size, light weight and a broad application range, and thus are widely applied on consumer electronic products such as a mobile phone, a notebook computer, a desktop display and a television, and have gradually replaced the traditional cathode ray tube (CRT) displays as the main trend in the display industry.
Referring to FIG. 3, a schematic partial view of a conventional display device 30 is shown. The display device 30 includes a substrate 32, a plurality of pixel rows R1˜R4, a plurality of gate control lines G0˜G4, a plurality of data lines S0˜S3, a dummy data line DUM and a plurality of dummy pixels 33. The pixel rows R1˜R4, the gate control lines G0˜G4, the data lines S0˜S3, the dummy data line DUM and the dummy pixels 33 all are formed on the substrate 32. The dummy pixels 33 respectively are formed at the outside of the heads (or tails) of the pixel rows R1˜R4. The dummy pixels 33 are located at respective intersections of the gate control lines G0˜G3 and the dummy data line DUM and each contain two neighboring sub-pixels 331, 333 electrically coupled with each other. The pixel rows R1˜R4 each include a plurality of pixels 31 located at respective intersections of the gate control lines G0˜G3 and the data lines S0˜S2. Each of the pixels 31 contains two neighboring sub-pixels 311, 313, the sub-pixel 311 is electrically coupled to a corresponding one of the data lines S0˜S3 to receive a data signal provided by the corresponding one data line, and the sub-pixel 313 is electrically coupled to the sub-pixel 311 to receive a data signal provided by the corresponding one data line through the sub-pixel 311. Each of the gate control lines G1˜G3 is for enabling the sub-pixels 311 of one pixel row and the sub-pixels 313 of the neighboring one pixel row.
Referring to FIG. 4, showing timing diagrams of driving signals respectively for driving the gate control lines G0˜G4 of the display device 30. As seen from FIGS. 3 and 4, because each of the gate control lines G1˜G3 is for enabling corresponding sub-pixels in two neighboring pixel rows, which results in the driving signals as required are multi-pulse signals.
However, since the current gate-on-array (GOA) circuit having a relatively low cost only can generate single-pulse signals and thus could not be used to generate the multi-pulse signals to meet the requirement of the display device 30. Therefore, the GOA circuit could not used in the foregoing display device 30 to replace the traditional integrated gate driver circuit so as to reduce the cost in relation to the gate driving part. From this point, the display device 30 still exists the possibility to further reduce cost.
USPTO Backgrounds
USPTO Backgrounds