Generally frame synchronization of an incoming serial bit data stream is performed by comparing a known framing pattern to the incoming data which contains periodic frame synchronization information so as to determine the frame boundary (start of frame) based upon matching the frame synchronization information to the framing pattern.
As the speed of the data stream increases, faster logic circuitry must be used to process the incoming data. For applications in which the serial bit stream is operating at frequencies above approximately 50 megahertz, emitter coupled logic (ECL) or gallium arsenide (GaAs) fabrication technologies must be used rather than complimentary metal oxide silicon (CMOS) technology due to CMOS'S inability to operate at such speeds. ECL logic typically uses approximately ten times the power that an equivalent CMOS circuit would use which consequently requires a larger power supply and further requires additional design considerations due to the heat generated by such integrated circuit components, all resulting in a larger and more expensive circuit design than that which would otherwise be achievable using equivalent CMOS circuitry. Similarly, GaAs technology is much more difficult to fabricate than CMOS technology, resulting in much higher fabrication costs.
The present invention addresses the speed limitations of CMOS circuitry to perform frame synchronization detection of an incoming high speed bit stream which otherwise would be beyond the speed capabilities of CMOS circuitry by dividing the incoming bit stream into a plurality of parallel words, each word containing "N" bits where "N" is an integer greater than 1. Thus if N equals 4, the incoming high speed data would be divided into 4-bit parallel words with the operating frequency of such 4-bit words being exactly 1/4 the incoming data bit stream.
The circuitry contains multiple (N) frame detectors. Each detector compares the bit pattern of the incoming parallel data to a known framing pattern. Each frame detector compares the incoming parallel data from a different starting bit location so that if the incoming parallel data contains a bit pattern matching the known framing pattern, it will be detected by one of the detectors during one comparison cycle. In this manner the byte boundary of the incoming data is determined.
This process is repeated for new incoming parallel data until the synchronization information is detected. If the detectors are comparing only a first portion of the synchronization information to a known bit pattern, then the remaining synchronization information is compared to a second known bit pattern immediately following detection of the first portion of the synchronization information.
This process can be repeated for as many units of synchronization information that are used per frame of data. Once a desired amount of synchronization information has been detected, the starting bit location within the incoming parallel data is used to identify the boundary for the incoming frame of data and all subsequent frames of data.
Once synchronization detection has occurred, the verification that synchronization information is received for subsequent frames is easily performed by the detectors observing the incoming parallel converted data at the precise time intervals when such data should be present.
It is this use of unsynchronized parallel data based upon an incoming high speed bit stream which distinguishes the present invention from other synchronization methods wherein a high speed data stream is observed without parallel conversion of the data prior to determining synchronization. The parallel word is generated without regard to frame or byte boundaries of the incoming data.
USPTO Backgrounds
USPTO Backgrounds