1. Field of the Invention
The present invention relates to a circuit for generating a ternary signal which receives a binary input-control signal and a binary reset signal and outputs a ternary signal from an output terminal, and in particular, relates to a circuit for generating a ternary signal which includes at least three transistors respectively controlled by different control signals.
2. Description of the Related Art
In recent years, a circuit for generating a ternary signal that outputs an output signal having three levels is for use in a multi-channel driver being in use for a flat-panel display. As a circuit for generating a ternary signal of a prior art, disclosed in FIGS. 2 and 3 of the Japanese patent laid-open publication No. 7-114361 is a circuit for generating a ternary signal having two level-shifting circuits and complementary metal-oxide semiconductor transistors of a PMOS and an NMOS.
FIG. 7 is a circuit diagram showing a configuration of the circuit for generating a ternary signal of the prior art. The circuit for generating a ternary signal of the prior art has a level-shifting circuit 95, a level-shifting circuit 96, a control circuit 87, a high-potential-side P-channel transistor 4 (hereinafter, referred to as an HTR4), a low-potential-side N-channel transistor 5 (hereinafter, referred to as an LTR5), and a low-potential-side N-channel transistor 6 (hereinafter, referred to as an LTR6).
The circuit for generating a ternary signal of the prior art receives input signals 71, 72 and 73, which are high or low binary signals, from three input terminals A, B and C, respectively. High level is of a potential level of a predetermined power supply VCC (hereinafter, referred to as VCC level); low level is of a potential level of ground (hereinafter, referred to as ground level). The respective input signals 71, 72 and 73 from the input terminals A, B and C are inputted to the control circuit 87.
The control circuit 87 has NOR circuits 82, 83 and 84, and inverters 81, 85 and 86. The NOR circuit 82 receives the input signals 71, 72 and 73. The NOR circuit 83 receives the input signals 71 and 72. The inverter 81 receives the input signal 73. The NOR circuit 84 receives the input signals 71, 72 and an output signal of the inverter 81. The inverter 85 receives an output signal of the NOR circuit 82. The inverter 86 receives an output signal of the NOR circuit 83. The control circuit 87 outputs output signals 74, 75 and 76 from output terminals of the inverters 85 and 86 and the NOR circuit 84, respectively.
The level-shifting circuit 96 receives the output signal 75. The level-shifting circuit 96 outputs a high output signal 77 of VCC level when the output signal 75 is in high level (VCC level), and outputs a low output signal 77 of a negative potential of the power supply VCC (hereinafter, referred to as −VCC level) when the output signal 75 is in low level (ground level). The output signal 75 and the output signal 77 differ from each other in voltage level.
The level-shifting circuit 95 receives the output signal 76. The level-shifting circuit 95 outputs a high output signal 78 of VCC level when the output signal 76 is in high level (VCC level), and outputs a low output signal 78 of −VCC level when the output signal 76 is in low level (ground level). The output signal 76 and the output signal 78 differ from each other in voltage level.
The output signal 74 is inputted to a gate terminal of the HTR4 to control on and off of the HTR4. A source terminal and a back-gate terminal of the HTR4 are connected to VCC level, and a drain terminal thereof is connected to an output terminal 79 (hereinafter, referred to as a COM79) and to drain terminals of the LTR5 and the LTR6. The HTR4 is turned on when the output signal 74 is low, and turned off when the output signal 74 is high.
The output signal 77 is inputted to a gate terminal of the LTR5 to control on and off of the LTR5. The drain terminal of the LTR5 is connected to the COM79, a source terminal thereof is connected to ground level, and a back-gate terminal thereof is connected to −VCC level. The LTR5 is turned on when the output signal 77 is high, and turned off when the output signal 77 is low.
The output signal 78 is inputted to a gate terminal of the LTR6 to control on and off of the LTR6. The drain terminal of the LTR6 is connected to the COM79, and a source terminal and a back-gate terminal thereof are connected to −VCC level. The LTR6 is turned on when the output signal 78 is high, and turned off when the output signal 78 is low.
Operation of the circuit for generating a ternary signal of the prior art configured as described above will be described below. FIG. 8 shows operation waveforms of respective parts of the circuit for generating a ternary signal of the prior art. In the description below, “L” and “H” stand for low and high, respectively.
At the control circuit 87, when a combination of the input signals 71, 72 and 73 is [L, L, L], the output signals 74, 75 and 76 are L, L and L, respectively.
When the combination of the input signals 71, 72 and 73 is [L, L, H], the output signals 74, 75 and 76 are H, L and H, respectively.
When the combination of the input signals 71, 72 and 73 is one of [H, H, H], [H, H, L], [H, L, L], [L, H, H], [L, H, L] and [H, L, H], the output signals 74, 75 and 76 are H, H and L, respectively.
The level-shifting circuit 96 performs level conversion on the output signal 75, and outputs the output signal 77. The level-shifting circuit 95 performs level conversion on the output signal 76, and outputs the output signal 78.
When a combination of the output signals 74, 77 and 78 is [L, L, L], the HTR4 is turned on and the LTR5 and the LTR6 are turned off. In this case, an output signal of VCC level is outputted from the COM79.
When the combination of the output signals 74, 77 and 78 is [H, H, L], the HTR4 and the LTR6 are turned off and the LTR5 is turned on. In this case, an output signal of ground level is outputted from the COM79.
When the combination of the output signals 74, 77 and 78 is [H, L, H], the HTR4 and the LTR5 are turned off and the LTR6 is turned on. In this case, an output signal of −VCC level is outputted from the COM79.
According to the operation described above, the circuit for generating a ternary signal of the prior art outputs an output signal having three levels of VCC level, ground level and −VCC level, from the COM79.
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