This invention relates to a teletext decoder employing a common memory for storing the teletext incoming data blocks. The same memory is also time-shared by a microcomputer and by a display processor displaying the information stored in the memory.
Teletext is a general term for a television-based communication technique. A horizontal line may be utilized for broadcasting textual and graphical information encoded in a digital binary representation. Teletext may be sent during the vertical blanking interval, when no other picture information is sent. The teletext binary information includes control and display digital information serially organized in data blocks. The organization of the binary information in the broadcasted signal is determined by the standard employed by the broadcaster. By way of an example only, references are made here to the proposed NABTS (North American Broadcast Teletext Specification).
In the NABTS each horizontal line containing teletext data is referred to as a packet. The binary data is divided into bytes; each byte includes eight binary units (bits). The first eight bytes of each packet are collectively known as the packet header. Three bytes of the packet header define the channel number and each channel is organized into pages. Each page is made up of a number of packets.
After its reception by the television receiver, the digital data included in the video signal is processed by the teletext decoder. Then the digital data is extracted from the video signal by a data slicer providing a stream of bits to a data processor (sometimes referred to as the prefix processor). The data processor may be made to receive user-initiated commands specifying the desired information for display. The data processor buffers in a memory the data contained in the teletext channel selected for displaying. The buffered data is processed and provided to a display processor which outputs the displaying signals. When a television picture tube (CRT) is used as an image displaying device, the display processor has to output the displaying signals periodically for maintaining the image on the television screen.
One feature of the invention is the usage of a microcomputer to control the data processor for selecting the information to be stored in the memory. The microcomputer issues control signals in response to a user-initiated command. The microcomputer also performs the required data processing of the buffered data by reading the memory to obtain the buffered data, by performing the required operations on it and by storing the processed data in the same memory, but not necessarily in the same locations where the buffered data reside. The microcomputer also uses the same memory for storage and retrieval of intermediate results and of status information.
Another feature of this invention is the usage of a time-shared common memory for buffering the incoming data, for providing a work space for the microcomputer and for providing access to the display processor. Because only one memory is used, a simplified interconnection is achieved. This lends to a cost effective utilization of the storage space required by the teletext decoder.
Another feature of the invention is a timing unit which provides the timing signals to operate the microcomputer, the data processor and the display processor and to operate a switching means which provides access to the common memory for each of the microcomputer, the data processor and the display processor. The timing unit makes the memory available for access, as required by the display processor, the microcomputer and the data processor.
The timing unit defines consecutively recurring time slots. The time slots occur in a predetermined regular time interval. An access to the common memory is accomplished by providing an address word to the memory and by transferring a data word either to or from the location defined by the address word. The timing unit may provide an access to the common memory during the time slot and only one access may occur in each time slot. The presence of sequence of consecutive time slots may be independent of real time operations in the microcomputer, the data processor and the display processor; so that if the data processor, for example, requires an access to the common memory, its access timing has to "fit" the predetermined timings of the time slot. The assignment of each time slot to the data processor, the microcomputer or the display processor, may be under the control of the timing unit.
In the prior art, access to memory occurs in response to a request by a device such as the microcomputer. Therefore, a device having a higher priority may have to wait until the access of a lower priority device such as the microcomputer is completed before it obtains access to the common memory.
As a feature of the decoder of the invention, the timing unit allocates a predetermined order of time slots for the exclusive usage of the display processor. The timing unit provides the timing signals to the display processor such that its timings for access coincide with the time slots allocated exclusively for its usage.
Another feature of the invention is the arrangement in which a digital word stored in the common memory for the display processor includes more than one pixel word. A pixel word provides information to the display processor for displaying one picture element called pixel. The display processor reads the pixel words included in the digital word during the display processor access time slot.
In accordance with one aspect of the invention, an unallocated time slot is given according to a priority scheme. Simultaneous requests for an access to the common memory are handled by the priority scheme which determines the assignment of each time slot prior to the beginning of that time slot. Therefore, the arbitration in this decoder is accomplished synchronously with those time slots not preassigned to the display processor.
USPTO Backgrounds
USPTO Backgrounds