This invention relates to forming a solder bump on an integrated circuit die. More particularly, this invention relates to such method that includes reflowing the solder alloy onto a terminal formed of an electrically conductive, solder-wettable composite material composed of copper particles and a polymeric binder.
In the manufacture of a microelectronic device, it is known to mount an integrated circuit die to a printed circuit board or the like by a plurality of solder bump interconnections that not only physically attach the die, but also electrically connect a circuit on the die to a circuit on the board for conducting electrical signals to and from the die for processing. For this purpose, a metal pad is formed on the die. A body of solder alloy, such as a preformed microball, is placed onto the pad, heated and cooled to reflow the solder to form a bump that is attached to the die. The area about the pad is covered by a material that is not wet by the solder to prevent the solder from spreading across the surface. The die is then assembled with the board such that the bump rests upon a terminal on the board, whereafter the assembly is heated to reflow the solder, thereby bonding the bump to the board to complete the interconnection.
The design of an integrated circuit die is relatively costly and includes the expense of designing and fabricate numerous masks to arrange and build up the many electrical features. In the past, terminals have been placed adjacent to the perimeter to facilitate wire bonding. Frequently, it is desired to utilize a conventional die, which features perimeter terminals for wire bonding, in a package that includes solder bump interconnections. However, the crowding of the terminals about the perimeter restricts the size of each bump, thereby making it more difficult to handle and accurately position the solder on the terminals and interfering with the formation of discrete bumps. Thus, it is desired to redistribute the terminal pads across the die surface to permit larger bumps to be employed. common processes for applying and patterning additional metallic layers significantly contribute to the cost of the die. Accordingly, it is desired to provide a relatively simple and inexpensive method for redistributing terminal pads on an integrated circuit die to facilitate solder bump interconnections, while avoiding the expense of redesigning the die.
USPTO Backgrounds
USPTO Backgrounds