This invention relates to a noise cancelling circuit for cancelling noise contained in a signal.
Circuits as shown in FIGS. 1 to 3 are known as noise cancelling circuits. These circuits are disclosed on page 738 of the "Tokkyo Pulse Kairo Gijitsu Jiten" Dictionary, which is co-edited by Y. Suzuki and T. Higuchi, and issued by Ohm Co., Ltd. These circuits are suitable in the case where a noise to be cancelled out is known beforehand as being either high ("H") or low ("L") level, and is comprised of delay circuit 11 and AND gate 12, as is shown, for example, in FIG. 1. When, in the circuit arrangement shown in FIG. 1, an input signal Si is supplied to input terminal 13, it is delivered to one input terminal of AND gate 12 and to delay circuit 11, the output signal of which is supplied to the other input terminal of AND gate 12 through delay circuit 11, where it is delayed a predetermined period of time. An output signal So is obtained from output terminal 14, which is connected to the output of AND gate 12. AND gate 12 produces an "H" output signal when it receives an "H" input signal Si, and the "H" output signal Sa of delay circuit 11 and an "L" output signal when it receives the other combination of these signals Sa and Si. As a result, delay circuit 11 can eliminate a positive noise level if the delay time is set longer than the duration of the noise. Where, on the other hand, a negative noise level is to be eliminated, an OR gate is employed in place of AND gate 12.
In this type of noise cancelling circuits, two such circuits have to be selectively employed, depending on whether an "H" or an "L" level noise is to be cancelled. However, the circuit arrangement of FIG. 1 cannot be employed in the situation where, as in the case of recent microcomputers, a meaningful signal can be set, by means of a program, at either an "H" or an "L" level.
In order that the aforementioned drawback can be eliminated and hence to perform a function with respect to both the positive and negative noise levels, a 2-stage circuit arrangement is employed, using two delay circuits, 11A and 11B, AND gate 12A, and OR gate 12B, as shown in FIG. 2. With this circuit arrangement, it is only necessary to, after eliminating a positive noise level at the preceding stage, cancel a negative noise level at the following stage. Alternatively, use can be made of majority decision logic circuit 17 which is comprised of AND gates 15A to 15C and NOR gate 16, as shown in FIG. 3, whereby the majority decision logic may be taken among the input signal Si, output signal Sa of delay circuit 11A, and output signal Sb of delay circuit 11B. However, the circuit arrangements as shown in FIGS. 2 and 3 are quite complex, and result in an increase in the number of elements required and in the amount of space taken up by the circuit pattern.
USPTO Backgrounds
USPTO Backgrounds