VCOs are important circuit elements for a wide range of applications, including function generators, phase-locked loops and frequency synthesizers. VCOs produce an oscillating output with a frequency that is controlled by an applied DC voltage. One of the challenges associated with VCOs is phase noise. It is well known that bias transistors are a significant contributor of 1/f3 phase noise for complimentary metal-oxide semiconductor (CMOS) VCOs. It is also known that an optimum bias current exists for each VCO to minimize the 1/f3 phase noise. However, due to variations in the operating frequency, voltage, temperature and processing of a VCO, it is quite difficult to identify this optimum bias current.
Prior art attempts to identify the optimum bias current for calibrating a VCO to minimize phase noise have focused on the use of peak-detection circuits and control loops. This approach has several disadvantages. First, the addition of a peak-detection circuit and a control loop add significant cost and overhead to a VCO. In addition, peak-detection circuits introduce additional capacitance and lower the tuning range of a VCO.
USPTO Backgrounds
USPTO Backgrounds