The present invention is generally directed to low power integrated circuits and, more specifically, to systems for adjusting a power supply level of a digital processing component and methods of operating the same.
In recent years, there have been great advancements in the speed, power, and complexity of integrated circuits (ICs), such as application specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, digital signal processor (DSP) chips and the like. These advancements have made possible the development of system-on-a-chip (SOC) devices, among other things. A SOC device integrates into a single chip all (or nearly all) of the components of a complex electronic system, such as a wireless receiver (i.e., cell phone, a television receiver, and the like).
An important criteria in evaluating the performance of an electronic device is power consumption. Minimizing power consumption has long been an important design consideration in portable devices that operate on battery power. Since maximizing battery life is a critical objective in a portable device, it is essential to minimize the power consumption of ICs used in the portable device. More recently, minimizing power consumption has also become more important in electronic devices that are not portable. The increased use of a wide variety of electronic products by consumers and businesses has caused corresponding increases in the electrical utility bills of homeowners and business operators. The increased use of electronic products also is a major contributor to the increased electrical demand that has caused highly publicized power shortages in the United States, particularly California.
Many complex electronic components, such as CPUs and DSPs, are capable of operating a number of different clock speeds. Generally speaking, if an electronic component operates at a slower speed, it uses less power because there are less signal level transitions in a given time period during which power is consumed. The speed at which logic gates switch in a DPU and DSP is directly affected by the level of the power supply, VDD, connected to the gates. As VDD gets larger, there is greater voltage and current to drive gates, so rise times and propagation delays across gates decrease. Conversely, as VDD gets smaller, rise times and propagation delays across gates increase. Thus, if a CPU or DSP must operate a relatively high clock frequency, such as 800 MHz, VDD is set to a high level, such as +3.3 volts or +2.4 volts. If a CPU or DSP can operate a relatively slow clock frequency, such as 50 MHz, VDD may be set to a low level, such as +1.2 volts.
Unfortunately, prior art applications do not provide any means for finely adjusting the level of VDD to a wide number of clock speeds. Typically, a DSP or CPU may operate in only two modes: a +3.3 volt high power mode and a +1.2 volt low power mode, for example. Thus, in the example above, if the CPU or DSP must operate at 100 MHz instead of 50 MHz, the +1.2 volt VDD level used at 50 MHz may not be sufficient to operate at 100 MHz. Thus, the DSP or CPU will be required to operate at VDD of +3.3 volts. However, at a VDD level of +3.3 volts, the CPU or DSP may consume far more power that is necessary to operate at 100 MHz.
Therefore, there is a need in the art for circuits and methods for finely adjusting the level of VDD in a large scale digital integrated circuit (e.g., DSP, CPU) to match a wide number of clock speeds. In particular, there is a need for circuits and methods that finely adjust VDD to an optimum level to ensure that the rise times and propagation delays of the large scale digital integrated circuit are closely matched to the clock speed at which the large scale digital integrated circuit operates.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an adaptive voltage power supply that finely adjusts VDD to an optimum level. According to an advantageous embodiment of the present invention, the adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.
According to one embodiment of the present invention, the first charging circuit comprises a first current source and a first switch capable of coupling the first current source to the charge capacitor.
According to another embodiment of the present invention, the first switch is controlled by the first VDD control signal.
According to still another embodiment of the present invention, the second charging circuit comprises a second current source and a second switch capable of coupling the second current source to the charge capacitor.
According to yet another embodiment of the present invention, the second switch is controlled by the second VDD control signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccircuitryxe2x80x9d means any circuit, device, component or part thereof that controls at least one operation, such circuitry may, if appropriate, be implemented in hardware, firmware or software, or some combination of at least two of the same, as the case may be. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
USPTO Backgrounds
USPTO Backgrounds