This invention relates to semiconductor processes for connecting one layer of a semiconductor wafer to another layer of a semiconductor wafer, and, more particularly, to a method for reducing the number of photolithographic steps in processes connecting one layer of a semiconductor wafer to an upper layer of the semiconductor wafer.
Semiconductor devices, also called integrated circuits, are mass produced by fabricating hundreds of identical circuit patterns on a single semiconductor wafer. During the process, the wafer is sawed into identical dies or "chips". Although commonly referred to as semiconductor devices, the devices are fabricated from various materials, including conductors (e.g., aluminum, tungsten), non-conductors (e.g., silicon dioxide) and semiconductors (e.g., silicon). Silicon is the most commonly used semiconductor, and is used in either its single crystal or polycrystalline form. Polycrystalline silicon is often referred to as polysilicon or simply "poly". The conductivity of the silicon is adjusted by adding impurities--a process commonly referred to as "doping".
Within an integrated circuit, thousands of devices (e.g., transistors, diodes) are formed. Typically, contacts are formed where a device interfaces to an area of doped silicon. Specifically, plugs typically are formed to connect metal 1 layers with device active regions. Vias typically are formed to connect metal 2 and metal 1 layers. Also, interconnects typically are formed to serve as wiring lines interconnecting the many devices on the IC and the many regions within an individual device. These contacts and interconnects are formed using conductive materials.
The integrated circuit devices with their various conductive layers, semiconductive layers, insulating layers, contacts and interconnects are formed by fabrication processes, including doping processes, deposition processes, photolithographic processes, etching processes and other processes. The term "photolithographic process" is of significance here, and refers to a process in which a pattern is delineated in a layer of material (e.g., photoresist) sensitive to photons, electrons or ions. The principle is similar to that of a photo-camera in which an object is imaged on a photo-sensitive emulsion film. While with a photo-camera the "final product" is the printed image, the image in the semiconductor process context typically is an intermediate pattern which defines regions where material is deposited or removed. The photolithographic process typically involves multiple exposing and developing steps, wherein, at a given step the photoresist is exposed to photons, electrons or ions, then developed to remove one of either the exposed or unexposed portions of photoresist. Complex patterns typically require multiple exposure and development steps.
One ongoing goal of semiconductor design and fabrication is to reduce costs. Cost reduction is essential to ongoing success in the field. One manner of reducing costs is to eliminate or optimize steps in the semiconductor fabrication process. In doing so, it is important to maintain or improve device and process efficiency and effectiveness.
USPTO Backgrounds
USPTO Backgrounds