1. Field of the Invention
The present invention relates to a semiconductor device utilizing silicon on insulator technology (hereinafter referred to as SOI semiconductor device) and a fabricating method therefor, and more particularly to a SOI semiconductor device and a method for fabricating the SOI semiconductor device which minimizes current leakage at junctions occurring at the lateral sides of diffusion regions to be used for diodes or well resistors.
2. Description of the Prior Art
Recently, great attention has been drawn to the SOI technique, in which a single crystal silicon layer is formed on an insulating layer in order to more deeply integrate elements. When the aforementioned SOI technique is applied to fabricating a semiconductor device, it can reduce parastic capacitance in driving the device to thereby improve operational speed and reduce power consumption, as compared to a general bulk silicon device.
However, arising form the structural characteristics of the SOI semiconductor device, a silicon substrate and an element formed thereon are completely separated by an insulating layer (named a BOX (buried oxide) layer), thereby making it impossible to provide an element like a diode into a lateral device for integrating electronic circuits onto the SOI substrate. In addition, there is a limitation in use of a well-structured element as a resistor in the integrated circuits. Therefore, it becomes impossible to make the diode in the vertical NPN (or PNP) structure which, for example, has been commonly deployed in electrostatic discharge (ESD) circuits, and the like.
There has been a great deal of difficulty in fabricating an integrated circuit having a limitation in area to be formed as a lateral-type device. If a vertical NPN (or PNP) diode is replaced with a lateral NPN (or PNP) diode, its actuated driving capacity is known to drop to approximately half. Therefore, it is necessary to fabricate the element (diode) of the lateral NPN structure twice as large as that of the vertical NPN structure, in order to compensate for this limitation. Accordingly, a larger circuit area is also proportionally required for fabricating a larger element, resulting in a negative effect on the integration level of the highly integrated circuit.
Therefore, in order to fabricate an element in the same structure within the same area as used for the conventional semiconductor device, the SOI semiconductor device is fabricated, rather than as a lateral structure of the NPN (or PNP) diode or a well-structured resistor of the ESD circuit, by selectively etching a predetermined portion of the upper silicon layer and the BOX layer, and by forming the element in a lower silicon layer.
FIG. 1 is a cross-sectional view for illustrating a conventional structure of a SOI semiconductor device fabricated in the prior art. A semiconductor device having a diode will be described as an embodiment of the prior art.
According to FIG. 1, the conventional SOI device comprises: a SOI substrate 10 having a surface silicon layer 10c formed by inserting an insulating layer 10b onto a P-type semiconductor substrate 10a; an element isolating layer 12 formed at a predetermined portion (an element-separating region) of the surface silicon layer 10c with its bottom surface contacting the insulating layer 10b; a gate electrode 16 formed by inserting a gate insulating layer 14 at a predetermined portion of the surface silicon layer 10c; insulating spacers 20 formed at both lateral walls of the gate electrode; source/drain regions 22 formed in the surface silicon layer 10c at both edges of the gate electrode 16 with their lower portiond contacting the insulating layer 10b; a first groove (g1) formed at one side of the gate electrode 16 by etching the surface silicon layer 10c and the insulating layer 10b to expose a predetermined portion of an active region of an N well 24 formed inside the semiconductor substrate 10a; a P type of a first diffusion region 26 formed in the N well 24 under the first groove (g1); a second groove (g2) formed at one side of the first diffusion region 26 by etching the surface silicon layer 10c and the insulating layer 10b to expose a predetermined portion of the active region of the silicon substrate 10; an N+ type of a second diffusion region 28 formed in the silicon substrate 10a under the second groove (g2); an interlevel insulating layer 30 with a plurality of contact holes (h) formed on the resultant structure to expose predetermined portions of the first and second diffusion regions 26, 28; and metal wires 32 formed for separately connecting the first and second diffusion regions 26, 28. Reference numeral 18 represents a silicide layer formed to reduce voltage levels of gate electrodes and contact wires, as is known in the art.
Accordingly, in the case of an SOI device thus constructed, the surface silicon layer 10c surrounded by the insulating layer 10b and the element isolating layer 12 is used as a transistor channel region, the first diffusion region 26 and the N well 24 for a P+/N diode, and the second diffusion region 28 and the P type silicon substrate 10a for a N+/P diode.
Design and manufacture of the aforementioned SOI device carries with it a number of difficulties and limitations. Since the silicide layer 18 is generally fabricated with a rough bordering surface, it is very likely that the length l1 (designated by reference symbol I in FIG. 1) between the silicide layer 18 and the diffusion regions 26, 28 at the both edges of the diffusion regions 26, 28 becomes partially smaller. Therefore, there is a problem in the aforementioned structure of the SOI semiconductor device in that the relatively short length between the silicide layer 18 and the diffusion regions 26, 28 results in an increase of current leakage at junctions flowing toward the P type semiconductor substrate 10a for the backward-oriented diodes, and not in the forward diodes.
Therefore, the reduction in characteristics of the backward diode also leads to reduction in functional characteristics of the driving semiconductor device. Even worse, if the diffusion regions 26, 28 and the silicide layer 18 become too close, or contact each other, in the region designated by reference symbol I, there may be an electric short between the first diffusion region 26 and the N well 24, or between the second diffusion region 28 and the semiconductor substrate 10a. As a consequence, the first and second diffusion regions 26, 28 will not properly operate as diodes, leading to device malfunction.
Therefore, it is an object of the present invention to address the aforementioned limitations by providing an SOI semiconductor device designed in a double-junction structure (for instance, a Pxe2x88x92 or Nxe2x88x92 layer surrounding a P+ or N+ layer) of different density of diffusion regions with spacers to be used for diodes (or well resistors) and a method for fabricating the SOI semiconductor device, in which silicide layers are formed only on the high density impurity layers, that is, on the surface of P+ and/or N+ layers, to secure a sufficient length between the silicide layers and the diffusion regions. This configuration prevents deterioration of the functional characteristics of the semiconductor device due to current leakage at the junctions.
It is another object of the present invention to provide an SOI semiconductor device designed in a single junction structure of diffusion regions to be used for diodes (or well resistors) and a method for fabricating the SOI semiconductor device, in which parts to form silicide layers are restricted on the diffusion regions with spacers to establish and secure a sufficient length between the silicide layers and the diffusion regions, thereby preventing the semiconductor device from reducing in its operational characteristics due to current leakage at junctions.
In order to accomplish the aforementioned objects of the present invention, there is provided a SOI semiconductor device comprising: a first conductivity type semiconductor substrate; a surface silicon layer formed on an insulating layer applied to the semiconductor substrate; an element isolating layer formed at predetermined portions of the surface silicon layer; a transistor formed on the surface silicon layer with a central gate electrode, gate spacers at both lateral walls and a source/drain region in the surface silicon layer at both edges of the spacers; a groove formed at one side of the transistor by sequentially etching the element isolating layer and the insulating layer in the surface silicon layer to expose a predetermined portion of a second conductivity type well formed in the semiconductor substrate; groove spacers formed at both lateral walls of the groove; a first conductivity type of a diode diffusion region formed in the second conductivity type well under the groove; and a silicide layer respectively formed on the gate electrode, the surface exposing parts of the source/drain region and the diode diffusion regions between spacers.
At this time, the diode diffusion regions are preferably constructed in a single junction structure of a high density of impurity or in a double junction structure where a low density of an impurity layer surrounds a high density of an impurity layer. If the diode diffusion regions are constructed in a single junction structure, the spacers to be formed in the transistor should be designed in a double structure.
In order to accomplish the first object of the present invention, there is provided a method for fabricating a first embodiment of a SOI semiconductor device comprising the steps of: forming a surface silicon layer in an insulating layer on a first conductivity type of a semiconductor substrate; forming an element isolating layer at predetermined portions of the surface silicon layer; selectively ion-implanting a second conductivity type of impurity at a transistor forming portion to dope a predetermined portion of the surface silicon layer and to form a second conductivity type of a well in the semiconductor substrate at the same time; forming a gate electrode by inserting a gate insulating layer onto the surface silicon layer doped with impurity; forming a groove by sequentially etching the element isolating layer and the insulating layer of the surface silicon layer with a mask pattern that restricts a diode forming part, to expose a predetermined surface portion of the second conductivity type well at one side of the gate electrode; forming an LLD region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the first conductivity type of a low density of impurity to a transistor forming part and, then, forming a low density impurity layer in the second conductivity type well under the groove; forming gate spacers at both lateral walls of the gate electrode and forming groove spacers at the lateral walls of the groove; forming a source/drain region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the high density of the first conductivity type of impurity only to the transistor forming part and, then, forming in the second conductivity type of a well under the groove a double junction structure of the diode diffusion region where the first conductivity type of a low density of an impurity layer surrounds the same type of a high density of an impurity layer; and forming a self-aligned silicide layer on the diode diffusion regions between the surface exposing parts of the source/drain region having the gate electrode and the spacers.
In order to accomplish the second object of the present invention, there is provided a method for fabricating the second embodiment of a SOI semiconductor device comprising the steps of: forming a surface silicon layer on an insulating layer applied to a first conductivity type semiconductor substrate; forming an element isolating layer at a predetermined portion of the surface silicon layer; selectively ion-implanting a second conductivity type of impurity only to a transistor forming part to dope a predetermined portion of the surface silicon layer and, at the same time, forming a second conductivity type of a well in the semiconductor substrate; forming a gate electrode by inserting a gate insulating layer to the surface silicon layer doped with impurity; forming an LLD region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the first conductivity type of a low density of impurity to the transistor forming part; forming first spacers at both lateral walls of the gate electrode and at those of the groove; forming a groove by sequentially etching the element isolating layer and insulating layer of the surface silicon layer with a mask pattern that restricts a diode forming part, to expose a predetermined surface portion of the second conductivity type of a well at one side of the gate electrode; forming a source/drain region in the surface silicon layer at both edges of the gate electrode by selectively ion-implanting the first conductivity type of a high density of impurity only to the transistor forming part and, then, forming a single junction structure of the diode diffusion region in the second conductivity type well under the groove; forming second spacers at external sides of the first spacers and at both lateral walls of the groove; and forming a self-aligned silicide layer on the diode diffusion region between the surface exposing part of the source/drain region having the gate electrode and the second spacers.
With the SOI semiconductor device thus constructed, the extent of the silicide layer portion is restricted to a range of space defined between spacers. As a result, it is possible to ensure that the resulting minimum length between the silicide layer and the diode diffusion region is much greater in the present invention than in the prior art. This serves to minimize current leakage at both lateral sides of the diode diffusion region, so as to prevent deterioration of the backward diode characteristics in driving the device.
USPTO Backgrounds
USPTO Backgrounds