The present invention relates generally to the electronic arts and, more particularly, to field-effect transistors and their fabrication.
There is a trade-off between source/drain series resistance and gate to source/drain capacitance in the design of symmetric planar metal oxide semiconductor field-effect transistors (MOSFETs). Specifically, FET saturated currents are more sensitive to source resistance and less sensitive to drain resistance. FET drive current improves more with reduced source resistance than with reduced drain resistance. Additionally, circuit delay is more sensitive to gate to drain capacitance than gate to source capacitance. That is, due to the Miller effect, the gate to drain capacitance can impact circuit delay significantly more than gate to source capacitance. However, some techniques associated with reducing source/drain resistance to improve drive current often simultaneously increase the gate to drain capacitance, thereby increasing circuit delay. Similarly, some techniques associated with reducing gate to source/drain capacitance often simultaneously increase source resistance, thereby degrading drive current. Thus, there is often an intrinsic trade-off between decreasing source resistance to improve drive current and decreasing gate to drain capacitance to minimize circuit delay.
Asymmetric transistors are attractive for some applications. An asymmetric MOSFET, for example, may have asymmetric source/drain regions to address problems relating to the Miller effect. Source/drain regions that have different heights and/or widths or be different distances from the gate electrode are among the elements that may be found in an asymmetric MOSFET.
USPTO Backgrounds
USPTO Backgrounds