Without limiting the scope of the invention, its background is described in connection with monolithic circuits with integrated heterojunction bipolar transistors (HBTs) and junction field effect transistors (JFETs), as an example.
Heretofore, in this field, efforts to combine bipolar and field effect transistor technologies have been undertaken because of the attractive combination of the high power of bipolar and the low power switching and logic made possible with field effect devices together on a monolithic chip. These past attempts have met with limited success primarily because the field effect devices had to be designed to be accomodated within a process and material structure better suited for bipolar transistors. Additionally, the additional process steps required to include field effect devices increased the complexity of the process and contributed to poor producibility and yield. Solutions that overcome the limitations of these past methods would be desirable.
USPTO Backgrounds
USPTO Backgrounds