A typical DRAM (Dynamic Random Access Memory) includes addressable memory cells arranged in rows and columns. One of the major determinants of the cost of producing memory chips is wafer yield, which is defined as the ratio of non-defective chips and the total chips fabricated on a given wafer. In general, the higher the integration density of the memory chip, the higher the probability that one or more memory cells thereof will be defective. Thus, the higher the integration density of the chips fabricated on a given wafer, the lower the wafer yield. Accordingly, the need for a method for correcting defects in order to enhance wafer yield became more acute with the advent of high-density memory chips.
The single most effective method in which to correct memory cell defects in order to enhance wafer yield is the provision of a redundant memory circuit in which one or more redundant rows and/or columns of memory cells are provided in order to replace rows and/or columns of the main memory array which are found to be defective, during testing, e.g., during wafer sort.
In operation, when a memory read or write cycle is executed, access to the defective rows and/or columns is prevented, and redundant decoders are responsive to only the addresses of the defective rows and/or columns, to thereby effectively replace the defective rows and/or columns with the redundant rows and/or columns, which are sometimes, referred to as spare rows and/or columns. This technique of replacing defective rows and/or columns with redundant rows and/or columns is oftentimes referred to as repairing defective memory cells.
According to the conventional technology of semiconductor memories, a wafer yield can not be enhanced sufficiently. Such a problem is remarkable for DRAMs that are mounted in an LSI.
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