The known production of high-voltage transistors (field-effect transistors) in integrated circuits regularly leads to optimized transistors for the desired voltage range. This can extend from more than 10 V up to 150 V and beyond. Typical use is automotive technology, in which, in addition to logical circuit elements, switches for the battery-voltage levels and for controlling spikes must also be provided. These high-voltage transistors can be fabricated, in principle, with processes such as those for CMOS circuits with operating conditions of 3.3 V or 5 V. This fabrication, however, is complicated and expensive, because a plurality of additional masks and processing steps are necessary and/or a large space required for the high-voltage transistor result.
Vertical high-voltage transistors are often generated with the aid of an epitaxial layer, whose thickness and concentration must be optimized for the desired voltage range. The layer thicknesses that are used can reach 10 μm or above, which can be realized only with a very complicated epitaxial deposition. The necessary buried layer, its doping and contact through the epitaxial layer (sinker) require several special processing steps necessary for the high-voltage transistor. In order to optimize the transistor surface area, i.e., its lateral extent, the thickness of the epitaxial layer must be adapted to the desired voltage level.
The attempt to produce high-voltage transistors as lateral transistors in connection with a low-voltage process for logic transistors leads to other difficulties. For example, the electrical field strengths are controlled so that at the positions of greatest field-strength concentration, breakdown does not occur, which could lead to malfunctions or to the destruction of the integrated circuit. Normally, this requirement leads to a large spatial requirement for the high-voltage transistors and thus to high chip costs.
From U.S. Pat. No. 6,455,893 B1, a lateral high-voltage transistor is known which requires less space because the electrical field strength occurring on the highly doped drain is reduced by means of a lower doped drain extension and a field plate. The described transistor can also be used for CMOS processes with less than a 1-μm structure width. However, the document asserts that the dielectric strength of the transistor is limited because the retrograde implantation profile in the edge regions of the drain extension leads to a less suitable doping pattern.
From U.S. Pat. No. 6,677,210 B1, another HV transistor is known, which has a drift region, within which the concentration of the majority charge carriers continuously increases through a combination of different doped wells toward the drain region in the lateral direction.
USPTO Backgrounds
USPTO Backgrounds