1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to a semiconductor memory device in which bit lines are coupled to data bus lines in response to column selection and write/read selection.
2. Description of the Related Art
In a semiconductor memory device carrying out a data-read operation, the data of a plurality of memory cells corresponding to a selected word address are read to a plurality of pairs of bit lines, and the data of one of the bit-line pairs corresponding to a selected column address is output to an exterior of the device via the read data bus. When data is provided from the exterior, the data is supplied to one of the bit-line pairs corresponding to a selected column address via the write data bus, and is written in the memory cell corresponding to a selected word address among the plurality of memory cells connected to this bit line pair. Coupling between the bit lines and the read data bus and coupling between the bit lines and the write data bus are controlled by column switches.
FIG. 1 is an illustrative drawing showing an example of the configuration of a related-art semiconductor memory device. A semiconductor memory device 10 of FIG. 1 includes a control circuit 11, a word driver 12, a word driver 13, a block control circuit 14, memory cell arrays 15-1 through 15-n, memory cell arrays 16-1 through 16-n, sense amplifiers (S/A) 17-1 through 17-n, column switches 18-1 through 18-n, column switches 19-1 through 19-n, and write-data generating units 20-1 through 20-n. The control circuit 11 receives a clock signal CK, a write-enable signal WE, and an address data signal from the exterior, and generates control signals for controlling each part of the device according to these received signals. A column signal and write-control signal supplied from the control circuit 11 control the column switches 18-1 through 18-n and 19-1 through 19-n.
FIG. 2 is a circuit diagram showing the configuration of the column switches 19-1 through 19-n and surrounding circuit portions. The column switches 18-1 through 18-n have the same configuration as shown in FIG. 2.
Memory cells 21-1 through 21-n each include PMOS transistors 31 and 32 and NMOS transistors 33 through 36. The PMOS transistors 31 and 32 and the NMOS transistors 33 and 34 constitute a latch for storing data. When a word line WL is set to HIGH, the NMOS transistors 35 and 36 become conductive, thereby coupling the memory cell to bit lines BL and /BL. Precharge units 22-1 through 22-n each include PMOS transistor 41 through 43, and an inverter 44. When a precharge signal is set to HIGH, the bit lines BL and /BL are precharged and equalized.
A column switch 19-x (1<=×<=n) includes NMOS transistors 51 and 52, a NAND gate 53, a NOR gate 54, an inverter 55, and PMOS transistors 56 and 57. The NAND gate 53 receives two column signals corresponding to its local column address among column signals (column selection signals) responsive to a column address entered from the exterior of the semiconductor memory device. When these two column signals are set to HIGH, the NAND gate 53 outputs a LOW signal. In response, the PMOS transistors 56 and 57 become conductive, thereby coupling the bit lines BL and /BL to a read-data bus RDB and RDBX. If the write-control signal is HIGH at this time, the output of the inverter 55 is LOW, so that the output of the NOR gate 54 becomes HIGH. In response, the NMOS transistors 51 and 52 become conductive, thereby coupling the bit lines BL and /BL to a write-data bus WDB and WDBX. In this manner, when a correspondence column signal is HIGH, the bit-line pair is chosen and coupled to the read-data bus. If the write-control signal is HIGH, the bit-line pair is also coupled to the write-data bus. If the write-control signal is LOW, the bit-line pair is not coupled to the write-data bus.
As described above, the operation of the column switch is controlled based on the column signal and the write-control signal. In order to perform a write operation properly, the three signals, i.e., the write data, the column signal, and the write-control signal, are supplied at optimum timing.
FIG. 3 is a timing chart showing an example of proper timing relationships between the write data, the column signal, and the write-control signal. As shown in FIG. 3, it is preferable that write data WDB and WDBX are supplied before the column signal and write-control signal are set to HIGH to couple the write-data bus to the bit lines. Moreover, it is preferable that the selection of read operation or write operation in response to the write-control signal is made prior to column selection by the column signal. In order to provide a predetermined time period required for the write operation, these three signals need to be determined before predetermined timing. If these timing relationships are undermined, causes of malfunction may be created, such as noises occurring in other circuits, the lack of time necessary for the write operation, the lack of time for driving the bit lines, etc.
In the semiconductor memory device of FIG. 1, signal lines to supply the write-control signal extend in both the X direction and the Y direction from the control circuit 11. The signal line in the X direction serves to control the write-data generating units 20-1 through 20-n, and the signal line in the Y direction serve to control the column switches 18-1 through 18-n and 19-1 through 19-n. In response to the write-control signal propagating in the X direction from the control circuit 11, the write-data generating units 20-1 through 20-n generate write data, which then propagate in the Y direction. The write-control signal propagating in the Y direction from the control circuit 11 is buffered, and then changes its direction to propagate in the X direction. Moreover, the column signal transmitted from the control circuit 11 propagates in the Y direction first, and then changes its direction to propagate in the X direction. With the control circuit 11 serving as the signal source, the write-data signal, the write-control signal, and the column signal all propagate substantially the same distance on signal lines before they reach the position of the destination column switch.
In the related art, Patent Document 1 discloses a technology for increasing the speed of column-system operations. [Patent Document 1] Japanese Patent Application Publication No. 2000-30447
The write-data signal, the write-control signal, and the column signal propagate through different signal lines. The load of the transistors connected to these signal lines and the load of the actually laid-out signal lines may differ from line to line. As shown in FIG. 1, the column switches are positioned at respective, different locations in the layout of the semiconductor memory device. Depending on its position, a signal reaching a given column switch may have timing that is deviated from the desired timing. It is not easy to ensure desired timing at all the locations where the column switches are situated. The adjustment of buffering, modification of the layout, insertion of a timing adjusting circuit, or the like is thus necessary to ensure proper timing margins.
Further, in addition to the write-control signal and the column signal, the control circuit 11 transmits various signals such as a row selection signal, an S/A signal, and a block selection signal in the Y direction. The control circuit 11 has buffers provided therein for transmitting these signals. The longer the propagation distance in the Y direction, the larger the drive capacity and size of the buffers need to be. Since a large number of buffers are crowded, the efficiency of layout drops.
Accordingly, there is a need for simplification of the mechanism to supply signals necessary for the control of column switches.
USPTO Backgrounds
USPTO Backgrounds