The present invention relates to a current mirror circuit that provides linear output with low headroom requirements.
Current mirrors are well known but they suffer from known disadvantages. Two basic current mirrors are shown in FIGS. 1 and 2. The current mirror of FIG. 1 is called a diode current mirror. It includes a pair of transistors Q1 and Q2 in which the input transistor Q1 is connected as a diode. The base and collector of Q1 are connected to the base of Q2. The input current signal is fed at an input node N1.1 which creates an input potential drop of V1.1=VBE1+VRE1. The base-to-emitter voltages of each transistor Q1, Q2 (VBE1 and VBE2) vary together with the input current signal; thus, VBE non-linearities tend to cancel out. The input current IIN generates a corresponding output current IOUT at the same level. Although the diode current mirror provides an output current that has a linear response to a changing input current (IIN=IIN(t)), it imposes an input headroom requirement of VBE1+VRE1. In practice, this can be as high as 1V.
The current mirror of FIG. 2 is called an emitter follower mirror. The circuit also includes a pair of transistors Q1, Q2. This circuit requires a bias current (IBIAS) provided at node N2.2. The input current IIN is fed directly to the resistor RE1, creating a voltage at the input terminal of V2.1=IIN*R (assume RE1=RE2=R). At node N2.2, the input and bias currents create a voltage V2.2=VIN+VBE1. At the emitter of Q2, the current mirror generates a voltage V2.3=VIN+VBE1−VBE2, which results in an output current of IOUT=V2.3/R=1/R*(IIN*R+VBE1−VBE2) if base current errors are ignored. In all known emitter follower mirrors, the bias current IBIAS is provided as a constant current.
The emitter follower mirror possesses a disadvantage because IOUT varies non-linearly with IIN. The input current to the mirror IIN is a time varying signal (IIN=IIN(t)), which causes VBE2 to vary over time (VBE2=VBE2(t)). VBE1 does not vary, due to the constant bias current IBIAS. This configuration generates an output current as follows:IOUT=V2.3/R=1/R*(IIN*R+VBE1−VBE2(t))Although the VBE1−VBE2 term in IOUT ideally would cancel out, it does not over most conditions. This leads to the non-linear response of the emitter follower mirror.
By way of example, consider a use case in which the input current IIN doubles over time. The voltage at node N2.1 will double, and the voltage across RE2 will roughly double. As a result, the output current will roughly double which causes a change in VBE2 of about 18 mv. Since IBIAS does not change, VBE1 will not change. This behavior would induce an error in the output current IOUT of about 18 mv/RE2=18 mV/R.
There is no known current mirror circuit that provides a linear output while requiring low input headroom requirements for the input current signal.
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