1. Field of the Invention
The present invention relates to systems and methods of verifying signal propagation delays in electronic equipment, and particularly to a system and method for verifying propagation delays of circuit traces of a printed circuit board (PCB) layout.
2. Related Art of the Invention
A PCB of a typical computer connects chip devices together, and also connects the chip devices to external components such as a keyboard and storage devices. The PCB generally utilizes circuit traces thereof to fulfill the connections. Some chip devices have multiple traces that send and/or receive data bits substantially simultaneously. The time that it takes for data to traverse a trace is known as propagation delay.
Computer chip sizes are continuing to be miniaturized, and electrical signals are being clocked at ever increasing frequencies. Even more that previously, high-speed, high-frequency signals being driven between chips via traces on a PCB are liable to detrimental impedance effects. One manifestation of these impedance effects is unwanted reflections due to impedance mismatches. The high-speed, high-frequency signals may also be prone to cross-talk and electromagnetic interference (EMI).
EMI is an electrical disturbance in an electronics-based system. EMI can be caused by natural phenomena such as lightning, by low-frequency waves emitted from electromechanical devices such as motors, or by high-frequency waves emitted from integrated circuits and other electronic devices such as routers.
The distance between two adjacent traces, trace width, and trace length on a PCB are parameters affecting EMI emissions and propagation delays. In particular, the shorter the distance between adjacent traces, the more intense the EMI emissions are. The wider the trace, the more intense the EMI emissions are. The longer the trace, the more intense the EMI emissions are. Furthermore, EMI emissions also generate propagation delay. If the propagation delay is very long, the speed of transmission of signals in the traces is slow, and the performance and quality of the PCB may be unsatisfactory. Indeed, there are legal requirements as to propagation delay which apply in many countries in which PCBs are marketed. Therefore, when constructing a PCB layout, it is necessary to verify propagation delay to insure that the propagation delay meets the requirements that apply in relevant countries in which the PCB is marketed. Additionally, such verification should be performed before the final physical layout of the PCB is determined, in order to avoid or minimize the difficult and expensive process of rectifying a layout.
Accordingly, there is a need for a system and method for verifying propagation delay of a PCB layout, in which verification is fast and inexpensive, and can be performed as early as possible in the design process.
USPTO Backgrounds
USPTO Backgrounds