1. Field of the Invention
The present invention relates to a shift register unit provided in a display device like a liquid crystal display, which supplies a scanning signal, and a display device using the shift register unit.
2. Description of the Related Art
In an active-matrix liquid-crystal display device, a matrix of picture signal lines (source lines) and scanning signal lines (gate lines) is formed, and switching devices, such as thin film transistors (TFTs), for activating the liquid crystal of pixels are formed where both lines cross. A scanning signal that successively scans the signal lines so that all the switching devices on one scanning line are temporarily in conduction is supplied to the scanning signal lines, while a picture signal is supplied to the picture signal lines so as to be synchronized with the scanning.
In this process, the function of successively supplying the scanning signal to the scanning signal lines is performed by a shift register. One example of a conventional shift register is illustrated in FIGS. 5 and 6. The shift register has a plurality of stages. FIG. 5 shows a circuit diagram of three stages. FIG. 6 shows a timing chart.
As shown in FIG. 5, the stages i-1, i and i+1 each have a combination of four transistors and one capacitor. This structure provides an advantage in that the transistor characteristics do not deteriorate since an excess stress is not exerted on the transistors. Referring to the stage i, a diode-connected input transistor 51 is connected to the output Gi-1 of the previous stage i-1, and a clamping transistor 53 and the control electrode of an output transistor 52 are connected to the output electrode of the input transistor 51. A pull-down transistor 54 is connected to the output electrode of the output transistor 52, and a capacitor 55 is inserted between the control electrode and output electrode of the output transistor 52.
In the above-described shift register, as shown in FIG. 5, a plurality of phase-shifted clock signals CKA, CKB and CKC are respectively input to the output transistors 52 of the stages i-1, i and i+1, and an output from two stages behind is input to the control electrode of the clamping transistor 53 in one stage. Accordingly, as shown in FIG. 6, in the stage i (dotted-line block in FIG. 5), when the previous stage output Gi-1 is at its "High" level, the input transistor 51 is switched "ON", whereby the control electrode potential Vbi (control signal) of the output transistor 52 rises, and in this condition the output transistor 52 is switched "ON". Thus, when the clock signal CKB is at its "High" level, the present stage output Gi is at its "High" level before being output. Subsequently, the output Gi+2 from two stages behind is at its "High" level, and when it is input to the control electrode of the clamping transistor 53, the clamping transistor 53 is switched "ON", whereby the control electrode potential Vbi of the output transistor 52 rises. In this manner, the outputs Gi-1, Gi and Gi+1 are successively output from the stages i-1, i and i+1. This can be used in, for example, a scanning circuit for a liquid crystal display device.
As can be seen in FIGS. 5 and 6, in the above-described shift register, a node, which is represented by Vbi in FIG. 5, is connected in a low impedance condition to a power supply only when the output Gi-1 input to the input transistor 51 or the output Gi+2 input to the clamping transistor 53 is at its "High" level. In other periods, all the transistors 51, 52 and 53 which cause the node Vbi to charge or discharge are in "OFF" (high impedance) condition, whereby the node Vbi is floating.
In the case where the above-described shift register is used for, e.g., gate scanning in a VGA display having 480 scanning lines, low impedance time is expressed as 2/480, and floating time is expressed as 478/480 (approximately 99.6%), which shows that the node Vbi is almost always in floating.
During the floating time, according to the essential function of the shift register, the node Vbi must maintain "Low" level potential so that the output Gi of the present stage i continues to be at its "Low" level. However, according to the above-described conventional shift register, since the node Vbi is floating, an excess of the control signal Vbi over the threshold value of the output transistor 52, caused by static and electromagnetic noise, causes a serious malfunction in which the present stage output Gi is at its "High" level when it essentially should be at its "Low" level. In addition, in the conventional structure, when the control signal voltage Vbi rises due to noise, this increased voltage condition (represented by the broken line a in FIG. 6) remains unchanged during the period in which the node Vbi is floating. Thus, output pulses (represented by the broken line b in FIG. 6) that must not be generated are continuously output at a clock cycle, which causes extremely adverse effects. Therefore, a problem occurs in that the use of the conventional shift register for gate scanning in a display rewrites a picture signal at timing at which the picture signal should not be rewritten, which is recognized as remarkably inferior display.
USPTO Backgrounds
USPTO Backgrounds