With development of the LCD display, traditional gate wiring makes it difficult to meet a requirement of an increasingly higher screen resolution. A Gate-In-Panel (GIP) technique has been widely used in industry.
FIG. 1 shows a gate wiring scheme of a GIP circuit in the related art, in which repeated units (i.e., units shown in figure, such as Un, Un+1, Un+2, Un+3, and so on) and peripheral wires can be used by the GIP circuit. In this way, space of the periphery can be saved, and a lighter and thinner screen can be developed.
However, addressing-driving for the GIP circuit is difficult since some peripheral wires have been omitted from the structure of the GIP circuit. It is difficult to manufacture an addressing circuit with good performance, especially in an Amorphous Silicon Gate (ASG) circuit.
Due to poor data retention, the ordinary LCD must be refreshed continuously for the entire screen to maintain the display, and thus there is no demand to perform the addressing and refreshing on only a certain region. However, with the development of bistable technology, a demand for the addressing-driving is increasing for certain applications, such as an electronic book (Ebook), a Memory In Pixel, etc. By refreshing a certain area of the screen, the power consumption can be reduced and the refreshing rate can be improved.
In the related art, in most addressing schemes, a selective signal output can be achieved by decoding the address lines, as shown in FIG. 2. The addressing circuit is in fact a decoder. That is to say, the decoder outputs a gate signal through each of the address lines with an independent value of 0 or 1, and only one output transmitting the Gate signal is selected.
Therefore, in the related art, in order to address the gate lines, it is required to increase a wiring space of the address lines with a bulky decoding circuit. Taking the ordinary WVGA as an example, additional 10 address lines are required for the addressing of 800 gate lines, and at least 10 PMOS or NMOS transistors are required to perform a gating for each gate line. Furthermore, there is no suitable implementation scheme in the related art for the amorphous silicon material to achieve such a decoding circuit. An ASG circuit, i.e. an ordinary amorphous silicon circuit, is not suitable to be a PMOS transistor, and has a poor circuit performance. Therefore, it is very difficult to achieve space-efficient decoding using amorphous silicon technology.
USPTO Backgrounds
USPTO Backgrounds