The present invention relates to microelectronic structures and methods of making them and more particularly to a system provided on a chip for monitoring an increase in a resistance of a conductive interconnect of a chip due to electromigration.
Electromigration has long been identified as a major failure mechanism of metal interconnects of semiconductor chips. Electromigration is indeed one of the worst reliability concerns affecting integrated circuits throughout the last 50 years. Electromigration tends to produce voids within metal conductors) due to movement of metal ions in directions parallel to high density current flow within the chip. Failure due to electromigration is caused by a positive divergence of the ionic flux leading to an accumulation of vacancies and forming a void in the metal. To the casual observer, it appears that ions are moved “downstream” by the force of “electron wind”.
For the reasons stated above, electromigration (hereinafter, “EM”) and failures that it engenders can be categorized as a wear-out mechanism. In general, the failure rate of a conductive interconnect is proportional to current density and the average temperature of the local region of the chip surrounding the conductive interconnect. EM becomes worse as the width and/or thickness of metal wiring on the chip are scaled. Current density within some conductive interconnects having small cross-sectional area can exceed 105 A/cm2.
Methods are known by which high current and/or high voltage and temperature stress are used to provide accelerated testing to screen out unreliable (defective) chips in relatively short periods of time. Several methods are described in prior art references as described herein. For example, U.S. Pat. No. 6,147,361 to Lin et al. (“the '361 Patent”) describes an EM sensor which includes a polysilicon body which is conductively connected to a monitored metal piece 400 and two electrodes 14b. In use, a linear metal “dummy” feature overlying a top surface of the EM sensor is stressed by a high voltage. When EM occurs within the dummy feature, local joule heating therein causes carrier mobility within the EM sensor to increase drastically. The test methodology in the '361 Patent is similar to that described in U.S. Pat. No. 5,264,377 to Chesire et al. in monitoring using a dummy metal feature under accelerated stress conditions. The approaches described therein poorly reflect the actual EM failure mechanism because neither the dummy feature nor the methodology used to test for electromigration are representative of actual conditions which lead to EM failures of conductive interconnects on the chip. The dummy feature fails to adequately represent real-life conductive interconnects which have topology including corners and via contact regions. Accelerated test methodology, while predictive of future failures which might occur during later use of the chip, fails to detect failures at time points during the actual useful lifetime of the chip.
U.S. Pat. No. 5,514,974 to Bouldin describes a somewhat different approach in which a dummy metal feature is also subjected to accelerated lifetime testing at wafer-level test time to determine whether a resistance of the dummy feature increases to a level which exceeds a threshold. Here, the dummy feature includes a series of metal segments which are connected together using a series of vias. When a difference between the resistance of the dummy feature and a control structure exceeds the threshold, the chip is determined to fail and is rejected during the wafer-level test.
All of the above-described approaches test for EM failure at wafer-level test time and during a specific test mode. Moreover, the dummy features tested in accordance with such approaches are bulky and are usually provided within a kerf area adjacent to a chip, or inside a specially designed test chip of the wafer. Moreover, purposes of these EM tests are usually directed to the qualification of processes and/or the screening out of unreliable (defective) chips during burn-in tests. The above-described prior art approaches do not provide for monitoring the effects of EM throughout the useful lifetime of the chip. After the chips have been diced from the wafer and packaged, the EM monitoring can no longer be performed within the chip. However, it is abundantly evident that EM degradation does not stop after the chip is installed in a system and shipped to customers.
USPTO Backgrounds
USPTO Backgrounds