It has been recognized in the art that the overall performance of conventional data processing systems depends not only upon the individual performance of the constituent components of the data processing system, but also upon the efficiency of data transfer between the components. For example, in a conventional data processing system including a processor and a memory system, many strategies have been proposed and implemented in order to improve the efficiency of data transfer between the processor and the memory system. One such strategy is referred to as store gathering.
Store gathering typically refers to a strategy of data transfer from the processor to the memory system in which the processor is equipped with a write-gather or store-gather facility that collects data associated with a number of smaller (e.g., two byte) store operations associated with multiple memory addresses in a defined address range and then outputs all of the collected data in a single larger (e.g., eight byte) store operation. More specifically, the write-gather or store-gather facility collects together multiple individual store operands so as to efficiently transfer the store operands to memory as a group. One particular such facility is a write gather pipe, which is designed for efficient transfer of noncacheable data from the processor to the external memory.
One implementation of a write gather pipe may comprise a 128-byte circular first-in, first-out (FIFO) buffer (WPB) and a special purpose register, a Write Pipe Address Register (WPAR). For a non-cacheable store instruction to the address specified in WPAR, the operand is stored sequentially in the buffer. When there are at least 32 bytes of data in the buffer, the write gather pipe executes a 32 byte burst transfer of data to the external memory. At any given time, the WPB holds from 0 to 31 bytes of data that cannot yet be written to memory. When a thread that is using the write gather pipe is interrupted, that data must be preserved so that the thread can resume from its interrupted state when control returns to it. This can be done conventionally, for example, by allowing only one thread to reserve the write gather pipe at any given time, so that the state of the WGB is maintained for that one thread across interruptions. However, since the conventional write gather pipe is configured to maintain the state of the WPB across interruptions of a thread, the facility cannot be time shared among threads.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds