1. Field of the Invention
The present invention relates to a multi-display system and a method thereof, and more particularly, to a multi-display system and a method thereof capable of displaying image signals simultaneously through a plurality of cathode ray tubes (CRTs) and a television, a plurality of liquid crystal displays (LCDs), or a plurality of CRTs and a plurality of LCDs.
2. Description of the Related Art
Some graphic controllers can control an image to be displayed on more than two different displays. For example, a personal digital assistant (PDA) can display the image on a liquid crystal display (LCD) and at the same time, on a cathode ray tube (CRT) or a television (TV). The above system is called a multi-display system.
FIG. 1 shows a schematic block diagram of a conventional multi-display system 10 which displays an image simultaneously on first and second displays 119 and 137. The multi-display system 10 includes a controller 20 which is connected with an image signal process unit 27 through a bus 25. The image process unit 27 is also connected with a memory 101 through the bus 25 so as to retrieve image data. Moreover, the image signal process unit 27 is connected with the first display 119, such as a CRT or a TV, through a bus 33, and with the second display 137, such as a LCD, through a bus 35. The image signal process unit 27 sends signals such as a data signal, a line clock signal, a frame signal, and a pixel clock signal to the buses 33 and 35 so as to operate the CRT or the TV 119, and the LCD 137. The image signal process unit 27 retrieves an image signal from the memory 101 and transmits the image signal to the LCD 137, the CRT, or the TV 119.
FIG. 2 shows a detailed block diagram illustrating the operation of the multi-display system 10 of FIG. 1. As shown in FIG. 2, the multi-display system 10 comprises the controller 20, the memory 101, a plurality of scalers 105, 115, 123, and 133, two overlays 107 and 125, two interpolation units 111 and 129, two low pass filters (LPFs) 113 and 131, two RGB converters 117 and 135, a synchronous signal generator 139, the first display 119, and the second display 137.
The controller 20 retrieves graphic data of the image signal to be displayed on the first display 119 from the memory 101 with a direct memory access (DMA) method through a separate route (bus B), and transmits the graphic data to the scaler 105. The scaler 105 transmits the graphic data to the overlay 107 after enlarging or scaling down the graphic data transmitted from the memory 101 by the controller 20.
The controller 20 retrieves video data of the image signal to be displayed on the first display 119 from the memory 101 with the DMA method through a separate route (bus C), and transmits the video data to the interpolation unit 111. The interpolation unit 111 converts a 4:2:0 format of the transmitted data to a 4:2:2 format. Here, the 4:2:0 and 4:2:2 formats are standardization frequency ratios with respect to a luminance signal Y, a digitalized signal Cb of B-Y, a digitalized signal Cr of R-Y. The 4:2:0 format means that the R-Y and the B-Y are standardized to 6.75 MHz by being skipped one line when a Y signal is standardized to 13.5 MHz for every line. The 4:2:2 format means that the R-Y and the B-Y are standardized twice when the Y signal is standardized four times. In Comite Consultatif International de Radio-communition (CCIR) 601, the 4:2:2 standardization is recommended.
The video data interpolated by the interpolation unit 111 is transmitted to the LPF 113. The LPF 113 passes image signals that are below a predetermined frequency, and eliminates the image signals that are above the predetermined frequency. Therefore, a noise element is eliminated by the LPF 113.
The video data passed through the LPF 113 is enlarged or scaled down by the scaler 115. The video data processed by the scaler 115 is transmitted to the RGB converter 117. The RGB converter 117 converts the transmitted video data into RGB data used in a monitor or the CRT. The video data that has been converted into the RGB data is transmitted to the overlay 107.
The overlay 107 receives the graphic data from the scaler 105 and the RGB converted video data from the RGB converter 117, and compounds the two transmitted signals. The overlay 107 transmits the two compounded signals to the first display 119 for displaying.
The controller 20 displays the image signal compounded by the overlay 107 on the first display 119, and at the same time, retrieves the graphic data of the image signal from the memory 101 with the DMA method through a separate route (bus D) in order to display the image signal on the second display 137. Moreover, the controller 20 retrieves the video data of the image signal from the memory 101 with the DMA method through a separate route (bus E) in order to display the image signal on the second display 137. The operation of displaying the graphic data and the video data retrieved from the memory 101 on the second display 137 is the same as the operation of displaying the graphic data and the video data on the first display 119, and the description thereof will be omitted to avoid repetition.
The image signal displayed on the second display 137 is commonly used as the image signal displayed on the first display 119. In FIG. 2, the image signal displayed on the first display 119 and the image signal displayed on the second display 137 are expressed to be stored into the same memory 101. For two image signals to be commonly used, the first display 119 and the second display 137 commonly use an image signal retrieve path (bus A: hereinbelow, referred to as a memory bus).
The second display 137 can simultaneously display an image signal which is the same image signal displayed on the first display 119. In addition, the second display 137 can display an image signal which is different from among the image signals stored in the memory 101 and commonly used. Furthermore, the image signal displayed on the first display 119, which is delayed for a predetermined time, can be displayed on the second display 137. In this case, the synchronous signal generator 139 generates various synch signals required by the displays 119 and 137.
However, as described above, the conventional multi-display system commonly uses the image signal memory bus. Therefore, a load to the memory bus increases where the size of the image signal stored in the memory 101 is large or the frame ratio of each display is great. Consequently, the performance and capability of the entire system deteriorates.
USPTO Backgrounds
USPTO Backgrounds