In recent years, electronic devices whose prevalence is rapidly spreading and that are typified by mobile telephones, notebook computers, personal digital assistants (PDAs), and digital video cameras, are becoming smaller, thinner, and lighter in weight. Further, the demand for higher performance and multifunctionality is increasing. In order to meet this demand, the density of electronic circuits is increasing by leaps and bounds through the miniaturization of semiconductor devices and circuit components, as well as technologies to package these electronic components.
The focus of this technological development is high density packaging technologies of Large Scale Integrated Circuits (LSI). For example, accompanying the rapid advancement toward high pin count and narrow pitch of electrode terminals of LSI chips, there has been the popularization of CSP (Chip Size Packaging) by flip chip packaging of bare chips, PPGA (Plastic Pin Grid Array) to external terminals, as well as BGA (Ball Grid Array) packaging. For this reason, there is a demand for new packaging technologies that accommodate the speeding up, miniaturization, and increase in number of input-output terminals of ICs that are further mounted.
In the above-described flip chip packaging, a plurality of electrode terminals first are formed on the semiconductor chip, and solder or Au bumps are formed on these electrode terminals. Next, the bumps of the semiconductor chip are made to face connecting terminals formed on the circuit board, and the above-described bumps of the electrode terminals and the connecting terminals that correspond to each bump are connected electrically. Further, in order to improve the electrical and mechanical joining with the semiconductor chip and the circuit board, the step of underfilling resin material between the semiconductor chip and the circuit board is performed.
However, in order to package a next-generation LSI with an electrode terminal number exceeding 5,000 on a circuit board, it is necessary for there to be bump formation that corresponds to a narrow pitch of 100 μm or less, but it is difficult to achieve this with current solder bump technologies.
In addition, because it is necessary to form a plurality of bumps in proportion to the number of electrode terminals, there is demand for low cost and high productivity by reduction of packaging cycle per chip.
Conventionally, plating and screen printing methods have been used as bump formation technologies. However, although the plating method is suited to narrow pitch, there is a problem in productivity as the steps become complex. In addition, although the screen printing method has superior productivity, it is difficult to achieve narrow pitch because of mask use.
In these circumstances, in recent years there has been proposed a technology in which solder bumps are formed selectively on connecting terminals of LSI chips and circuit boards. This technology is not only suitable for fine bump formation, but because bumps can be formed all at once, productivity is superior, and this technology has started to gather attention as a packaging technology for circuit boards of next-generation LSI.
In the above-described packaging technology, a solder paste made of a mixture of solder powder and resin is applied to the entire surface of the circuit board on which has been formed a connecting terminal whose surface oxidation has advanced. Next, by heating the circuit board, the solder powder is melted, and bumps are formed selectively on connecting terminals without causing short-circuiting between adjacent connecting terminals (see, for example, Patent Document 1).
In addition, first, a paste form composition (chemical reaction deposition-type solder) whose main components are organic acid lead salt and metal tin is applied to the entire surface of the circuit board on which has been formed connecting terminals. Next, there is disclosed an example of initiating a substitution reaction of Pb and Sn by heating the circuit board, and selectively depositing an alloy of Pb and Sn on a connecting terminal of a circuit board (see, for example, Patent Document 2 or Non-Patent Document 1).
Further, there is disclosed an example of, after immersing the circuit board on which has been formed connecting terminals on the surface and forming an adhesive membrane on the surface of the connecting terminals only, attaching solder powder to the adhesive membrane and selectively forming bumps on the connecting terminals (see, for example, Patent Document 3).
The above-described Patent Document 1 has as its object to maintain wettability towards metals while making short-circuiting less likely to occur between connecting terminals by controlling the surface oxidation of solder powder. However, it is difficult to control characteristics that are essentially contradictory using only oxidation levels and oxidation method.
In addition, because the material of the chemical reaction deposition-type solder used in Patent Document 2 uses a specific chemical reaction, there is a low degree of freedom in selecting the solder composition, and there also remains the problem of making it free of Pb.
On the other hand, in Patent Document 3, solder powder is applied uniformly on the electrodes, so it is possible to obtain uniform solder bumps. In addition, because there is a large degree of freedom in terms of selecting the solder composition, the technology is superior as it is easy to make it free of Pb. However, because it is necessary to perform a particular chemical treatment using a chemical reaction in the step of selectively forming an adhesive membrane on the electrode surface necessary in the method of construction of Patent Document 3, the step not only is made complex but also leads to increase in costs, and thus there are problems in terms of mass production.
In order to solve these problems, there recently has been disclosed electronically joining only a particular conducting part by heating and applying pressure after sandwiching a film comprising anisotropic conductive material including conductive particles between protruding electrode terminals of a semiconductor chip and connecting terminals on a circuit board (see, for example, Patent Document 4).
In addition, there has been proposed technologies or the like as follows: A heat-curing resin including conductive particles is supplied between a semiconductor chip and a circuit board, and pressure is applied to the semiconductor chip while at the same time conductive particles melted by heating that resin are concentrated between the respective terminals of the semiconductor chip and the circuit board to establish electrical connection. At the same time, the semiconductor chip and the circuit board are connected (see, for example, Patent Document 5).
However, in the case of automatically concentrating melted solder powder between respective terminals of a semiconductor chip and circuit board by heating and applying pressure to resin placed in between the circuit board and the semiconductor chip, in general, the degree of viscosity of the electrically conductive adhesive applied on the circuit board increases gradually by polymerization proceeding during the heating step. For this reason, there was the problem that a sufficient amount of melted solder powder could not be moved to be on the electrode terminals, leading to the curing of the resin and the persistence of a portion of solder powder on a part other than in between connecting terminals, resulting in the lowering of insulating properties.    [Patent Document 1] Japanese Patent Laid-Open No. 2000-94179    [Patent Document 2] Japanese Patent Laid-Open No. 1-157796    [Patent Document 3] Japanese Patent Laid-Open No. 7-74459    [Patent Document 4] Japanese Patent Laid-Open No. 2000-332055    [Patent Document 5] Japanese Patent Laid-Open No. 2004-260131    [Non-Patent Document 1] Electronics Packaging Technologies, September 2000, pp. 38-45
USPTO Backgrounds
USPTO Backgrounds