1. Field of the Invention
The invention relates to laser marking of workpieces, including semiconductor substrates, wafers, packages and the like. The invention is particularly adapted for, but not limited to, marking machine readable codes on a second side of semiconductor wafers which have a high density circuit patterns on a first side, for instance chip scale packages having a high density of interconnects which could be damaged by a marking beam, or where space for codes is limited.
2. Background Art
The following representative patent references relate to various aspects of laser marking of wafers and electronic assemblies, illumination, and inspection/reading marks: U.S. Pat. Nos. 4,522,656; 4,945,204; 5,329,090; 6,309,943; 6,262,388; 5,929,997; 5,690,846; 5,894,530; 5,737,122; and Japanese Patent Abstract 11135390.
The following representative references provide general information on various laser marking methods and system configurations and components: “Galvanometric and Resonant Low Inertia Scanners”, Montagu, in Laser Beam Scanning, Marcel-Dekker, 1985, pp. 214–216; “Marking Applications now Encompass Many Materials”, Hayes, in Laser Focus World, February 1997, pp. 153–160; “Commercial Fiber Lasers Take on Industrial Markets”, Laser Focus World, May 1997, pp. 143–150. Patent Publications: WO 96/16767, WO 98/53949, U.S. Pat. Nos. 5,965,042; 5,942,137; 5,932,119; 5,719,372; 5,635,976; 5,600,478; 5,521,628; 5,357,077; 4,985,780; 4,945,204; 4,922,077; 4,758,848; 4,734,558; 4,856,053; 4,323,755; 4,220,842; 4,156,124.
Published Patent Applications WO0154854, publication date 2 Aug. 2001, entitled “Laser Scanning Method and System for Marking Articles such as Printed Circuit Boards, Integrated Circuits, and the Like” and WO0161275, published on 23 Aug. 2001, entitled “Method and System for Automatically Generating Reference Height Data for use in a Three-Dimensional Inspection System” are both assigned to the assignee of the present invention. Both applications are hereby incorporated by reference in their entirety.
U.S. Pat. No. 6,309,943 relates to identifying and determining a position of a scribe grid on a front-side surface of a wafer with a camera. Based on this information, a laser is fired to form an alignment mark on the back-side surface of the wafer.
U.S. Pat. No. 6,496,270, assigned to the assignee of the present invention, describes a method and system for automatically generating reference height data for use in a 3D inspection system wherein local reference areas on an object are initially determined and then the height of these local reference areas are determined to generate the reference height data.
The WH-4100 Laser Marking System is a commercially available backside laser marking system produced by the assignee of the present invention. A fine alignment vision subsystem corrects rotational or offset errors (X, Y, Angle) which are introduced when a wafer is placed in the marking station. A manual “teach tool” allows the user to train the system to recognize three non-collinear points on the wafer that is to be used for the correction. An iterative trial and error process with various adjustments, and manual evaluation of the results is required with the system. The information is then used to determine mark locations on the bottom side of the wafer.
U.S. Pat. Nos. 5,894,530 and 5,929,997 relate to viewing systems used for inspection and/or alignment operations in microelectronics. In the '530 patent, optical elements are selectively positioned such that images of indicia fields disposed on either side of a substrate can be viewed (at the same magnification) whenever the substrate is in a given orientation, or such that images of indicia fields disposed on both sides of the substrate may be viewed at the same magnification, simultaneously.
With increasing density and complexity of circuitry on semiconductor devices, (e.g., exceeding ten-thousand die on a 300 mm wafer), multiple designs and layout of circuitry, there is an on-going need to provide advanced interactive tools for improving throughput and yield.
USPTO Backgrounds
USPTO Backgrounds