Modern electronic devices utilize integrated circuits, commonly referred to as semiconductor chips that incorporate numerous electronic elements. These chips are typically mounted on support substrates such as circuit panels or chip carriers. The substrates physically support the chips and electrically interconnect each chip with other elements of the circuit. The interconnection between the chip and the chip carrier is commonly referred to as "first level" assembly or chip interconnection, as distinguished from the interconnection between the chip carrier and the larger elements of the circuit, commonly referred to as "second level" interconnection.
The structures utilized to provide the first level connection between the chip and the substrate must accommodate all of the required electrical interconnections to the chip. The number of connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial number of I/O connections.
The size of the chip and substrate assembly is a major concern. The size of each such assembly influences the size of the overall electronic device. Moreover, the size of each assembly controls the required distance between each chip and other chips, or between each chip and other elements of the circuit. Delays in transmission of electrical signals between chips are directly related to these distances. These delays limit the speed of operation of the device. For example, in a computer where a central processing unit operates cyclically, signals must be interchanged between the central processing unit chip and other chips during each cycle. The transmission delays inherent in such interchanges often limit the cycling rate of the central processing chip. Thus, more compact interconnection assemblies, with smaller distances between chips and smaller signal transmission delays which permit faster operation of the central processing chip, can be made.
The first level interconnection structures connecting a chip to a substrate ordinarily are subject to substantial strain caused by thermal cycling as temperatures within the device change during operation. The electrical power dissipated with the chip tends to heat the chip and the substrate, so that the temperatures of the chip and the substrate rise each time the device is turned on and fall each time the device is turned off. Over a period of time, the device tends to undergo a number of heating up and cooling down cycles as the device is repeatedly turned on and off. These cycles, which cause an associated expansion and contraction of the device, are commonly referred to as "thermal cycling". As the chip and the substrate are ordinarily are formed from different materials, having different coefficients of thermal expansion, the chip and the substrate ordinarily expand and contract by different amounts. This causes the electrical contacts on the chip to move relative to the electrical contact pads on the substrate as the temperature of the chip and the chip modules change. This relative movement deforms the electrical interconnections between the chip and the substrate and places them under mechanical stress. These stresses are applied repeatedly with repeated operations of the device, and can cause breakage of the electrical interconnections. Thermal cycling stresses may occur even where the chip and the substrate are formed from like materials having similar coefficients of thermal expansion, because the temperature of the chip may increase more rapidly than the temperature of the substrate when power is first applied to the chip.
Semiconductor chips typically have been connected to electrical conductors on mounting substrates such as chip carriers or circuit panels by methods such as wire bonding, tape automated bonding, and flip-chip bonding. In wire bonding, the chip is positioned on the substrate with the bottom or back surface of the chip abutting the substrate and with the contact-bearing front or top surface of the chip facing upwardly, away from the substrate. Individual fine wires are connected between the contacts on the chip and the contact pads of the substrate. There are reliability issues with wire bonded leads breaking during thermal cycling due to the CTE mismatch. In chip on board packaging, the chip may be wire bonded directly to a printed circuit board. This is typically referred to 11/2 level packaging. One of the reliability issues in this packaging scheme is known good die. Until the chip is wire bonded to the circuit board and the circuit board is tested, it is generally difficult to determine whether the chip is defective. The cost of replacing a defective chip is generally quite substantial. It is therefore, preferable to package a chip such that it is testable prior to being incorporated into an electronic device.
In tape automated bonding, a flexible dielectric tape bearing a prefabricated array of leads is positioned over the chip and substrate, and the leads are bonded to the contacts of the chip and to pads of the substrate. Tape bonded leads suffer from reliability issues related to thermal cycling induced lead breakage.
In flip-chip bonding, contacts on the surface of the chip are provided with bumps of solder. The substrate has pads arranged in an array corresponding to the array of contacts on the chip. The chip, with the solder bumps, is inverted so that its front surface faces towards the top surface of the substrate, with each contact and solder bump on the chip being positioned on the appropriate pad of the substrate. The assembly is then heated so as to liquefy the solder and bond each contact on the chip to the confronting pad of the substrate. A compact assembly can be made using flip-chip technology because flip-chip bonding does not require the leads to be arranged in a fan-out pattern. The area of the substrate occupied by the pads is approximately the same size as the chip itself. Having a package that is approximately the same size as the chip itself is highly desirable because such packages can be used to reduce the overage size of the electronic device. Assemblies made by flip-chip bonding, however, are susceptible to thermal stresses. The problem is particularly pronounced with relatively large chips.
Packaging technologies which address the issues of package size, package speed, are thermal stress are desired. Commonly assigned U.S. Pat. Nos. 5,148,266 and 5,148,265, the disclosures of which are hereby incorporated by reference herein, provide substantial solutions to theses problems of thermal stresses and package size. Additional and/or alternative package methods to address these needs are desired. The present invention provides an alternative package addressing the problems of package size, signal speed and thermal stresses.
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