An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material that overlies a surface of the semiconductor material. Devices which may be formed within the semiconductor material include MOS transistors, bipolar transistors, diodes and diffused resistors. Devices which may be formed within the dielectric include thin-film resistors and capacitors. Typically, more than 100 integrated circuit die (IC chips) are constructed on a single 8 inch diameter silicon wafer. The devices utilized in each dice are interconnected by conductor paths formed within the dielectric. Typically, two or more levels of conductor paths, with successive levels separated by a dielectric layer, are employed as interconnections. In current practice, an aluminum alloy and silicon oxide are typically used for, respectively, the conductor and dielectric.
Delays in propagation of electrical signals between devices on a single dice limit the performance of integrated circuits. More particularly, these delays limit the speed at which an integrated circuit may process these electrical signals. Larger propagation delays reduce the speed at which the integrated circuit may process the electrical signals, while smaller propagation delays increase this speed. Accordingly, integrated circuit manufacturers seek ways in which to reduce the propagation delays.
For each interconnect path, signal propagation delay may be characterized by a time delay .tau.. See E. H. Stevens, Interconnect Technology, QMC, Inc., July 1993. An approximate expression for the time delay, .tau., as it relates to the transmission of a signal between transistors on an integrated circuit is given by the equation: EQU .tau.=RC[1+(V.sub.SAT/ /RI.sub.SAT)]
In this equation, R and C are, respectively, an equivalent resistance and capacitance for the interconnect path, and I.sub.SAT and V.sub.SAT are, respectively, the saturation (maximum) current and the drain-to-source potential at the onset of current saturation for the transistor that applies a signal to the interconnect path. The path resistance is proportional to the resistivity, .rho., of the conductor material. The path capacitance is proportional to the relative dielectric permittivity, K.sub.e, of the dielectric material. A small value of .tau. requires that the interconnect line carry a current density sufficienfly large to make the ratio V.sub.SAT/ /RI.sub.SAT small. It follows, therefore, that a low-p conductor which can carry a high current density and a low-K.sub.e dielectric should be utilized in the manufacture of high-performance integrated circuits.
To meet the foregoing criterion, copper interconnect lines within a low-K.sub.e dielectric will likely replace aluminum-alloy lines within a silicon oxide dielectric as the most preferred interconnect structure. See "Copper Goes Mainstream: Low-k to Follow", Semiconductor International, November 1997, pp. 67-70. Resistivities of copper films are in the range of 1.7 to 2.0 .mu..OMEGA.cm. while resistivities of aluminum-alloy films are higher in the range of 3.0 to 3.5 .mu..OMEGA.cm.
Despite the advantageous properties of copper, several problems must be addressed for copper interconnects to become viable in large-scale manufacturing processes.
Diffusion of copper is one such problem. Under the influence of an electric field, and at only moderately elevated temperatures, copper moves rapidly through silicon oxide. It is believed that copper also moves rapidly through low-K.sub.e dielectrics. Such copper diffusion causes failure of devices formed within the silicon.
Another problem is the propensity of copper to oxidize rapidly when immersed in aqueous solutions or when exposed an to oxygen-containing atmosphere. Oxidized surfaces of the copper are rendered non-conductive and thereby limit the current carrying capability of a given conductor path when compared to a similarly dimensioned non-oxidized copper path.
A still further problem with using copper in integrated circuits is that it is difficult to use copper in a multi-layer, integrated circuit structure with dielectric materials. Using traditional methods of copper deposition, copper adheres only weakly to dielectric materials.
Finally, because copper does not form volatile halide compounds, direct plasma etching of copper cannot be employed in fine-line patterning of copper. As such, copper is difficult to use in the increasingly small geometries required for advanced integrated circuit devices.
The semiconductor industry has addressed some of the foregoing problems and has adopted a generally standard interconnect architecture for copper interconnects. To this end, the industry has found that fine-line patterning of copper can be accomplished by etching trenches and vias in a dielectric, filling the trenches and vias with a deposition of copper, and removing copper from above the top surface of the dielectric by chemical-mechanical polishing (CMP). An interconnect architecture called dual damascene can be employed to implement such an architecture and thereby form copper lines within a dielectric. FIG. 1 illustrates the process steps generally required for implementing the dual damascene architecture.
The present inventor has found that the dual damascene architecture may often be difficult for semiconductor manufacturers to implement in large-scale manufacturing processes. It is difficult to deposit a thin silicon nitride etch-stop layer without damaging the underlying low K.sub.e material. The art of plasma etching dielectric materials is well established, but etching sub-half-micrometer features in a low-K.sub.e dielectric while maintaining selectivity to silicon nitride is difficult.
There are at least two processes in the formation of the dual-damascene architecture that are particularly troublesome. First, deposition of thin, uniform barrier and seed layers into high aspect ratio (depth/diameter) vias and high aspect ratio (depth/width) trenches is difficult. The upper portions of such trenches and vias tend to pinch-off before the respective trench and/or via is completely filled or layered with the desired material. Further, CMP and the associated cleaning procedures are especially complex and difficult to implement.
In addition to its difficulty and complexity, the dual damascene architecture imposes limitations on interconnect performance. The etch-stop layer, typically comprised of silicon nitride, has a high dielectric permittivity; thus, unless the etch-stop layer is very thin compared to the line thickness, capacitance between metal lines in the same interconnect level is dominated by coupling through the etch stop. Conductivities of known barrier materials are negligible compared to the conductivity of copper; thus the conductance of narrow interconnect lines is markedly reduced by the barrier layer that must be interposed between the copper and dielectric.
A processing tool architecture suitable for implementing the dual-damascene process steps illustrated in FIG. 1 is shown in FIG. 2. As illustrated in FIG. 2, the dual damascene architecture can be implemented with ten tool sets. Formation of each interconnect level generally requires two precision photolithographic processes, two precision etches, four dielectric depositions, barrier and seed layer depositions, a copper deposition, CMP and a post-CMP clean. Both small vias and small trenches must be etched; thus, an etch tool is required to define via features in the silicon nitride film, and a second etch tool is required to define via openings and trench features in the low-K.sub.e dielectric. Using the traditional processing tool architecture of FIG. 2, the formation of each metallization level requires at least 13 workpiece movements among the tool sets.
The substantial number of wafer movements used to form a dual-damascene interconnect metallization structure reduces the reliability and yield of the manufacturing process. As the number of wafer movements increases, so does the potential for mishandling of one or more wafers. Further, implementing a manufacturing facility for applying dual amascene interconnect metallization structures requires a substantial capital outlay for purchase of the required tool sets. Such reliability and capital equipment outlay issues are addressed by the present invention.
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