Exemplary embodiments of the present invention relate to semiconductor memory devices, and more particularly, to a semiconductor memory device, a test circuit and a test operation method thereof.
A dynamic random access memory (DRAM), which is widely used among memory devices, includes a plurality memory cells for storing data. As the number of memory cells integrated in the semiconductor memory device increases, more time and money are consumed for testing the memory cells in the semiconductor memory device. Therefore, a parallel test scheme has been developed and applied to test memory cells of a semiconductor memory device at a wafer or a package level.
According to the parallel test scheme, test data are inputted to two or more memory cells in a bank of a semiconductor memory device. The memory cells store and output the test data. The outputted test data are compared to determine whether or not the memory cells have a defect.
A conventional semiconductor memory device includes an additional test pin on a chip to output the comparison result, i.e., a test result. In order to reduce the chip size, there are demands for a circuitry that may test a semiconductor memory device without the additional test pin, and decrease a test time.
USPTO Backgrounds
USPTO Backgrounds