1. Field of the Invention
The present invention relates generally to stereolithography and, more specifically, to the use of stereolithography to form protective layers on substrates, such as semiconductor dice or wafers, and the resulting structures.
2. State of the Art
In the past decade, a manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
Essentially, stereolithography, as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries. The layer of material is selectively consolidated or fixated to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form and the material itself may be consolidated, fixed or cured, or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size. When a liquid is employed, resolution is highly dependent upon the minimum surface area of the liquid which can be fixed (cured) and the minimum thickness of a layer which can be generated, given the viscosity of the liquid and other parameters, such as transparency to radiation or particle bombardment (see below) used to effect at least a partial cure of the liquid to a structurally stable state. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for the same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques.
However, to the inventors' knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other pre-existing components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required.
In the electronics industry, computer chips are typically manufactured by configuring a large number of integrated circuits on a wafer and subdividing the wafer to form singulated devices. A coating of protective dielectric material, such as polyimide, can be formed over the wafer prior to cutting in order to prevent physical damage to each die and the circuitry thereon during handling of the die. Polyimide coatings are formed by applying a liquid polymer in a volatile carrier to the center of a spinning wafer. Thus, the polyimide layer is said to be “spun on” to the wafer. Typically, such polyimide layers have thicknesses of about 6μ. When the volatile carrier evaporates and as the polyimide layer shrinks, it warps, with the polyimide layer typically being thicker at the periphery of the wafer than at the center of the wafer, a phenomenon referred to as “dishing.” Given the required tolerances for semiconductor devices, even slight dishing may drastically reduce the yield of useable dice from the wafer. Moreover, when polyimide layers are spun onto semiconductor wafers in this manner, it is difficult to provide a repeatable thickness between wafer batches.
In addition, the cure temperature required to adequately cross-link the polyimide layer is typically about 300° C. This high cure temperature may be detrimental to the integrated circuits of the dice, as well as to the bond pads exposed at the active surface of the dice.
As conventional processes, such as spin-on techniques, form polyimide layers that substantially cover an active surface of a wafer, shrinkage or warpage of the polyimide layer during evaporation or volatilization of the carrier material or during curing can stress the wafer and may damage the circuitry of semiconductor devices on the wafer.
Moreover, the resulting cure of the polyimide layer may not be a full “hard” cure. Consequently, if a die having such a polyimide layer on the active surface thereof is packaged with a polymer filled with particles of silica, such as sand with low α particle emission, the silica particles can impinge, or pass through, the polyimide layer, which is supposed to act as a physical barrier to the silica. Such impingement of silica particles can damage the circuits of the die unless expensive round silica particles are used as a filler in the packaging material.
After disposal on the active surfaces of one or more dice and curing of the polyimide layer, each of the bond pads covered by the polyimide layer is exposed to facilitate access to the bond pads. Typically, a complex, conventional mask and etch process is employed. For example, a photoresist material may then be used to form a mask and an etchant can be employed to remove portions of the polyimide layer that overlie bond pads through apertures of the mask. As is well known in the art, slight dimensional differences between wafers, including nonflatness, can occur, causing misalignment or distortion of the mask and, thus, of structures formed therethrough, such as the bond pad openings through a protective polyimide layer.
The use of mask and etch processes to pattern polyimide protective layers is also somewhat undesirable in that these processes introduce additional fabrication steps and, thus, increase fabrication time, as well as increasing the likelihood that the die or dice being fabricated will be damaged. The use of mask and etch processing also consumes expensive dielectric materials and etchants.
Finally, as is well known to those in the art, alpha particles emitted by solders, leads, sand, and other sources can create electron-hole pairs in a semiconductor device and thereby cause “soft” errors during the operation of the semiconductor device. While not permanently damaging to the semiconductor device, “soft” errors are often a nuisance to the user of a computer or other electronic device. A 6μ layer of polyimide may act to minimize such “soft” errors.
The art does not teach methods of fabricating protective layers on the active surfaces of semiconductor devices that do not stress a wafer on which the semiconductor devices are contained or that do not require a significant number of additional fabrication steps. Nor does the art teach protective layers so fabricated that reduce the incidence of soft errors in the protected semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds