1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof.
2. Description of the Related Art
A multi chip semiconductor device wherein a plurality of semiconductor chips are mounted on the island of the lead frame, each semiconductor chip is bonded with an internal lead by wire, and the mounted plurality of semiconductor chips are resin molded entirely is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2002-368184. This semiconductor device occupies a large mounting (occupation) area, because a plurality of semiconductor chips are mounted on one lead frame resulting in a large lead frame. Also the manufacturing cost is high, because wire bonding using a lead frame is adopted.
A semiconductor device having a small mounting area is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2003-273321. This semiconductor device has a plurality of double-sided substrates on each of which a semiconductor chip or chips are mounted. The substrates are stacked or laminated by, for example, a hot pressing.
A semiconductor device disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2001-094046, has two stacked bare chips mounted on center of an upper surface of a base plate. Connecting pads provided on periphery area of the upper surface of each bare chip are connected with connecting pads provided on periphery of the upper surface of the base plate by bonding wires. To enable wire bonding of the lower-side bare chip, the size of the upper-side bare chip is smaller than that of the lower-side bare chip so that the periphery of the upper surface of the lower bare chip is exposed, and the connecting pads provided on the upper bare chip is at an inner side than the connecting pads provided on the lower bare chip. Further, because wire bonding of the upper bare chip is carried out after that of the lower bare chip, at the upper surface of the base plate, the connecting pads for the lower bare chip are arranged outside of the mounting area the lower bare chip, and the connecting pads for the upper bare chip are arranged at the outer side thereof.
The semiconductor device disclosed in above mentioned Unexamined Japanese Patent Application KOKAI Publication No. 2003-273321, has double-sided boards on which a semiconductor chip is mounted, by polymerizing a conductive connection terminal formed on each double-sided board. As for this semiconductor device, because each circuit board is thick and expensive, the entire semiconductor device is also thick and expensive. Also, because each layer is bonded, it is hard to obtain reliability of intensity, in accordance with environmental change. The semiconductor device disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2001-094946, because the connecting pads for the lower bare chip are arranged at the upper surface of the base plate, and the connecting pads for the upper bare chip are arranged at the outer side thereof, when the number of stacked semiconductor chips increase, the area occupied by pads on the base plate becomes larger. Therefore, the area of the entire semiconductor device becomes larger. Further, because the length of the wire becomes longer, the value of resistance becomes larger, and becomes inadaptable to a high frequency.
Therefore an object of the present invention is to provide a semiconductor device of which the mounting area is small and a reliability of intensity in the connecting units is secured, and a manufacturing method thereof.
USPTO Backgrounds
USPTO Backgrounds