Non-volatile memory (NVM) arrays, such as erasable, programmable read only memory (EPROM) or flash memory arrays, or electrically erasable, programmable read only memory (EEPROM) arrays, require high positive or negative voltages to program and erase memory cells of the array.
NVM cells generally comprise transistors with programmable threshold voltages. For example, one type of non-volatile cell is a nitride, read only memory (NROM) cell, described in U.S. Pat. No. 6,011,725, the disclosure of which is incorporated herein by reference. Unlike a floating gate cell, the NROM cell may have two separated and separately chargeable areas. Each chargeable area defines one bit. The separately chargeable areas are found within a nitride layer formed in an oxide-nitride-oxide (ONO) stack underneath the gate. When programming a bit of an NROM cell, channel hot electrons are injected into the nitride layer. This is generally accomplished by the application of a positive gate voltage and positive drain voltage, the magnitude and duration of which are determined by different factors related to the amount of programming required. Programming and erasing of NROM cells are also described in U.S. Pat. No. 6,011,725.
One preferred procedure for programming bits, e.g., in NROM cells, is by the application of programming pulses to word lines and bit lines so as to increase the threshold voltage of the bits to be programmed. After application of one or more sets of programming pulses, the threshold voltages of the bits that are to be programmed may be verified to check if the threshold voltages have been increased to a target programmed state. Any bit that fails the program verify operation should preferably undergo one or more extra programming pulses. The sequence of application of programming pulses followed by verification may then continue until all the bits that should be programmed have reached the target programmed state.
The circuitry that supplies and controls the programming and verification voltages generally comprises a high voltage regulator or high voltage pump (the terms being used herein interchangeably). For example, in a typical EPROM system, it may be necessary to drive the word line (WL), to which the gate of the memory transistor (or cell) is connected, to different voltage levels in order to read, program or erase it. The load to be driven includes the word line, X-decoder (XDEC) and associated N-wells. This may be a very large capacitive load for a VLSI (very large scale integrated) circuit, ranging in value from 100 pF to several nF. During program (PGM) mode, the word line and associated voltages may be typically at a programming voltage (Vpgm) in the range of 8 to 11V, whereas in read (RD) or verify (VERF) modes, the word line may be typically at a read voltage (Vrd) in the range of 3 to 5V.
FIG. 1 illustrates prior art circuitry that employs a voltage regulator 100 to drive the WL loads at their DC levels. The circuitry of FIG. 1 is described hereinbelow, but first reference is made to FIG. 2, which illustrates a typical construction of voltage regulator 100. Voltage regulator 100 may be a Class A regulator, which means that it has strong drive in one direction only.
As seen in FIG. 2, a differential stage GM1 receives an input voltage IP at one of its inputs (the negative input in the illustration). The output of differential stage GM1 is connected via a node n1 to the input or gate (designated “g” in FIG. 2) of a PMOS (p-channel metal oxide semiconductor) transistor GM2. The supply terminal or source of transistor GM2 (designated “s” in FIG. 2) is connected to a positive voltage supply Vpp. Differential stage GM1 may also receive a voltage input from Vpp. The output or drain terminal of transistor GM2 (designated “d” in FIG. 2) is connected to a current load element 5 via a node n2. In FIG. 2, the current load element is a resistive voltage divider comprising a pair of resistors 7, but in the general case it may be any element that draws current, such as but not limited to, a transistor, current source, diode, etc. The output of transistor GM2 may be connected to a capacitive load CL. The output of the current load element 5 may be connected to the second input (the positive input in the illustration) of differential stage GM1 as its feedback FB. The feedback in voltage regulator 100 may equalize the two inputs to differential stage GM1, and accordingly, the output is at a voltage determined by the resistor ratio in the current load element 5. Voltage regulator 100 may comprise a Miller compensating capacitor Cm between the gate and drain of transistor GM2, between nodes n1 and n2.
In voltage regulator 100, the PMOS transistor GM2 is capable of pulling up the load strongly, while the resistors 7 discharge the load with a fixed current, which is usually small. In EPROM systems, the transitions are required to be fast. Accordingly, it is necessary to charge and discharge the WL load quickly, while consuming minimal quiescent current. However, the voltage regulator 100 of FIG. 2 is only capable of a quick charge, but not a quick discharge. Very often, the voltage regulators that are used are characterized by a weak drive in both directions (charge and discharge). In such a case both the charging and discharging processes are problematic.
The voltage regulator 100 may serve as the supply voltage to portions of the XDEC, and as such, may be connected to the source and bulk nodes of a PMOS transistor in the XDEC (not shown). Charging quickly presents no difficulty for such PMOS as the bulk voltage is always at an equal or higher potential than the drain and source, and the drain follows the source during charging. However, a fast discharge may be problematic, since there may be a delay between the discharge of the source to the drain. This means there may be a transient wherein the drain voltage is higher than the source and bulk. This may cause parasitic latch-up, which may result in catastrophic failure of the devices. This necessitates a controlled discharge over time, that is, with controlled dV/dt slopes. Unfortunately, this requirement contradicts the speed requirement between modes of operation.
Reference is now made again to FIG. 1, which illustrates a typical application of voltage regulator 100 to drive the WL loads at their DC levels. Although in many EPROM systems separate regulators drive the different voltages in program and read/verify, for simplicity FIG. 1 illustrates only one voltage regulator 100 that drives both voltage levels.
In the circuitry of FIG. 1, voltage regulator 100 may output to a switch S1. When switch S1 is conducting, it connects the output of voltage regulator 100 to a WL load, which may be at a voltage HV. A PMOS transistor P1 may have its source connected to a positive voltage supply Vdd. The gate of transistor P1 may be connected to a discharge voltage Disch_b. The drain of transistor P1 may be connected to a switch S2. When switch S2 is conducting, it connects the drain of transistor P1 to the WL load.
As mentioned hereinabove, it is necessary to make quick transitions between the various modes in order to enhance the speed of the operation. When the word line is in an active mode (PGM or RD), switch S1 is conducting and switch S2 is non-conducting. In this active mode, voltage regulator 100 is connected to the WL load and drives it to its appropriate DC level. In order to discharge the WL load, switch S1 becomes non-conducting and switch S2 becomes conducting and Disch_b=“0”. The PMOS transistor P1 discharges the load to Vdd. This discharge is highly non-linear because the strength of the PMOS transistor P1 is the square of its Vgs, which is equal to HV in this case. At the beginning of the discharge, the change in voltage over time is much more rapid than at the end, i.e., the slope (dV/dT) is much higher than at the end. After HV is discharged to Vdd, switch S1 is made conducting and switch S2 non-conducting. The voltage regulator 100 then re-charges the load to the appropriate level. In this manner the voltage regulator 100 only charges the load between modes, while the PMOS transistor P1 does all of the discharging.
For example, during the PGM to VERF transition, the WL must be discharged from Vpgm (e.g., 9-11V) to Vrd (e.g., 3-5V). The prior art circuit of FIG. 1 would require discharging first to VDD (e.g., 1.8-3.6V) and then recharging back to Vrd. For a fixed discharge time, this prior art method has much larger slopes (dV/dT) than a direct linear discharge from Vpgm to Vrd. In addition the prior art method requires a charge from VDD to Vrd in each PGM to VERF transition. However, this is wasteful in current compared to a direct discharge.
Thus, what is desired in the art and has been absent until now is a discharge method between PRM and VERF/RD states, which discharges directly and linearly from Vpgm to Vrd with a controlled slope.
USPTO Backgrounds
USPTO Backgrounds