The present invention relates to a semiconductor memory device; more particularly, to an internal voltage generator of a semiconductor memory device.
As a semiconductor chip is more highly integrated, each of plural cells in the semiconductor chip is downsized. A voltage level for operating the semiconductor chip is also decreased. Most semiconductor chips are provided with external supply voltages for supplying a power voltage to the semiconductor device and an internal voltage generator for generating plural internal voltages from the external supply voltages. Examples of internal voltages generated by the internal voltage generator include a bit line precharge voltage (VBLP) precharged to a bit line pair and a cell plate voltage (VCP) supplied to a cell plate. The VBLP and the VCP generally have an identical voltage level.
FIG. 1 illustrates a block diagram of a conventional internal voltage generator. The internal voltage generator includes a mirror-type amplifier 100 and an output driver 110. The mirror-type amplifier 100 compares a reference voltage VREF with an internal voltage. The output driver 110 outputs the VBLP according to a comparing result. Drive control signals OFF and OFFB, input to the mirror-type amplifier 100, determine whether the mirror-type amplifier 100 operates or not. The reference voltage VREF is half of the level of a core voltage VCORE generally.
FIG. 2 illustrates a schematic circuit diagram of the internal voltage generator described in FIG. 1. The mirror-type amplifier 100, enabled by the drive control signals OFF and OFFB, generates pull up and pull down control signals by comparing the reference voltage VREF with the VBLP. The output driver 110 performs a pull up or a pull down operation according to the pull up and pull down control signals for increasing or decreasing the level of the VBLP.
The mirror-type amplifier 100 includes an NMOS transistor NM21 as a dead zone to prevent a leakage current. Because the NMOS transistor NM21 operates to reduce the level of a gate voltage of a NMOS transistor NM22, it is prevented for the NMOS transistor NM22 from being turned on abnormally at a low level of the gate voltage. Accordingly, the mirror-type amplifier 100 prevents the leakage current in the output driver 110.
However, the voltage level for turning on the NMOS transistor NM22 increases and an operation timing for turning on the NMOS transistor NM22 is delayed. Finally, a whole response of the internal voltage generator is delayed. It is difficult to generate an internal voltage capable of supporting predetermined operations required in an active mode.
A circuit operation of a semiconductor memory device may be performed in a standby mode or an active mode. The conventional internal voltage generator uses the mirror-type amplifier 100 in both the standby and active modes. Accordingly, while minimizing the leakage current generated in standby mode, the conventional internal voltage generator is inefficient to generate the VBLP capable of supporting operations, such as a precharge operation, required in the active mode.
USPTO Backgrounds
USPTO Backgrounds