The design, testing and fabrication of semiconductor circuits, such as microprocessors and microcontrollers, is often an expensive and time-consuming process. Several types of computer aided design (CAD) tools have been developed or proposed to facilitate the design and fabrication of integrated circuits. Generally, semiconductor circuits are tested following fabrication using automated test equipment (ATE).
Automated test equipment (ATE) is computer controlled test and measurement equipment arranged in a manner to automatically test a semiconductor circuit. Automated test equipment (ATE) provides predictable and repeatable testing, and generally allows the high cost of test equipment to be amortized over a high volume of semiconductor circuits that are tested. Automated test equipment (ATE) may perform limited testing of a semiconductor circuit without applying power to the semiconductor circuit being tested, to identify several common manufacturing defects, such as incorrect or missing components, and opens and shorts. Opens and shorts, for example, may be detected using well-known continuity testing techniques. In addition, once the semiconductor circuit is powered up, the automated test equipment (ATE) can functionally test the semiconductor circuit to evaluate the proper performance of a semiconductor circuit. Functional testers apply power and other required signals to the semiconductor circuit and test the semiconductor circuit using its external inputs and outputs. The testing of semiconductor circuits in this manner helps to ensure that a given semiconductor circuit will operate properly in its intended environment.
Manufacturing yields, as well as the time and expense required to test such semiconductor circuit devices, contribute to the fabrication costs associated with such devices. Since the costs associated with the automated test equipment (ATE) are amortized over all of the semiconductor circuits that are tested by the automated test equipment (ATE), the testing-related costs allocated to a given semiconductor circuit are proportional to the time required to test each semiconductor circuit. In addition, as the complexity of a given semiconductor circuit design increases, there is generally a corresponding increase in the complexity and cost of the required automated test equipment (ATE). Thus, the performance of the automated test equipment (ATE) needs to be continuously upgraded to maintain pace with the increasing speed, complexity or other performance requirements of the semiconductor circuits themselves. Specifically, automated test equipment (ATE) must constantly evolve, to provide higher performance, and increased functionality, throughput and accuracy.
Another factor that contributes to the efficiency and amortized cost of automated test equipment (ATE) is the number of pins on a semiconductor circuit that must be accessed by the automated test equipment (ATE) in order to perform functional testing. FIG. 1 illustrates a conventional tester 100 having a probe head 110 that interfaces with the pins or pads on each integrated circuit of a wafer 150. A typical semiconductor circuit has an increasing number of pins, including pins for voltage, ground, serial port, clock, reset, address and spares. In addition, since the number of address pins is proportional to memory size, the number of address pins required to fully test the memory increases in a like manner with the size of the required memory. There is a physical limitation on the number of pins that can reasonably be accessed by conventional automated test equipment (ATE). Thus, conventional automated test equipment (ATE) can only test a single semiconductor circuit at a time.
FIGS. 2A and 2B illustrate the serial testing of a particular semiconductor circuit 210-a and 210-b, respectively, on the wafer 150 by the tester 100 of FIG. 1. The serial nature of the testing in turn impacts the amortized cost that is allocated to each semiconductor circuit. As shown in FIGS. 2A and 2B, the probe head 110 is moved from semiconductor circuit 210-a to semiconductor circuit 210-b in a serial manner, performing the same tests on each semiconductor circuit. The limitation is on the number of probes possible in the probe head 110 held at the accuracy required to make individual clean connections, and hence the complexity of the supporting equipment.
A need therefore exists for a method and apparatus for testing semiconductor circuits that does not necessarily require the automated test equipment (ATE) to maintain pace with the performance requirements of the semiconductor circuits themselves. Another need exists for a method and apparatus for testing semiconductor circuits that use features and functions provided by the semiconductor circuit itself.
USPTO Backgrounds
USPTO Backgrounds