1. Technical Field
The present disclosure generally relates to integrated circuit (IC) design and manufacturing technology. More particularly, it discloses an IC layout design method and system.
2. Description of the Related Art
As semiconductor technology advances to 40 nm process node and below, redundant vias (RVs) are often inserted into a layout design. Inserting an RV into a layout design typically includes replacing a single square through hole with a rectangular through hole (also known as a through hole strip) or a double square through hole. Inserting RVs can reduce the risk of via opens and reduce interconnect resistance, thereby improving product yield. As a result, RV insertion is a key component in design for manufacturability (DFM) of semiconductor devices.
Presently, the RV insertion typically includes filling RVs in the layout (RV filling), performing a design rule check (DRC) verification, and performing a layout operation at the same time. The above functions are commonly performed by a single module. However, the RV insertion described above poses several issues during the layout design method. For example, each DRC code needs to be modified to update/change a layer name, so that the results of the RV filling can be invoked in a script. This may result in a high workload, especially when the design rules increase in complexity or are frequently upgraded.
FIG. 1 compares the changes in a DRC code before and after modification. Specifically, the top of FIG. 1 illustrates an original DRC code (before modification), and the bottom of FIG. 1 illustrates the resulting DRC code after the original DRC code has been modified (for example, after updating/changing the layer name). As previously mentioned, the modification of the DRC code may result in a high workload since the modified DRC code is longer and complicated than the original DRC code as mass variable name need be modified in order to form a single code module for the RV filling and DRC verification functions. Also, errors in the modified DRC code are often detected during quality assurance processes. These errors may cause difficulties in establishing and maintaining operation of the RV runset file.
Furthermore, the integrated RV filling and DRC verification functions often have to be performed using a same software tool from a same Electronic Design Automation (EDA) vendor. A user is usually unable to combine and use different EDA software tools to separately perform the RV filling and the DRC verification functions. For example, software compatibility and other proprietary issues may prevent a user from using one EDA software tool to perform the RV filling function and another EDA software tool to perform the DRC verification function. As a result, the layout design method is constrained by the above limitations.
USPTO Backgrounds
USPTO Backgrounds