Ion implantation is a standard technique for introducing conductivity-altering dopant materials into semiconductor wafers. In a conventional ion implantation system, a desired dopant material is ionized in an ion source, the ions accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the wafer. The energetic ions in the beam penetrate into the bulk of the semiconductor material and are embedded into the crystalline lattice of the semiconductor material. Following ion implantation, the semiconductor wafer is annealed to activate the dopant material. Annealing involves heating the semiconductor wafer to a prescribed temperature for a prescribed time.
A well-known trend in the semiconductor industry is toward smaller, higher speed devices. In particular, both the lateral dimensions and the depths of features in semiconductor devices are decreasing. State of the art semiconductor devices require junction depths less than 1000 angstroms and may eventually require junction depths on the order of 200 angstroms or less.
The implanted depth of the dopant material is determined by the energy of the ions implanted into the semiconductor wafer. Shallow junctions are obtained with low implant energies. However, the annealing process that is used for activation of the implanted dopant material causes the dopant material to diffuse from the implanted region of the semiconductor wafer. As a result of such diffusion, junction depths are increased by annealing. To counteract the increase injunction depth produced by annealing, the implant energy may be decreased, so that a desired junction depth after annealing is obtained. This approach provides satisfactory results, except in the case of very shallow junctions. A limit is reached as to the junction depth that can be obtained by decreasing implant energy, due to the diffusion of the dopant material that occurs during annealing. In addition, ion implanters typically operate inefficiently at very low - implant energies.
Rapid thermal processing can be used to minimize the diffusion that occurs during annealing. However, significant changes to the annealing process, such as reduced annealing temperatures, would reduce the amount of dopant material activated and would thereby adversely affect the operating characteristics of the semiconductor device. The positive effects of fluorine in BF.sub.2 implants in reducing the junction depth of BF.sub.2 implants as compared with equivalent energy boron implants have been reported in the prior art by K. Ohyu et al in "Advantages of Fluorine Introduction in Boron Implanted Shallow p.sup.+ /n-Junction Formation", Japanese Journal of Applied Physics, Vol. 29, 1990, pages 457-462; D.F. Downey et al "Control of BF.sub.2 Dissociation in High Current Ion Implantation", 8th International Conference on Ion Implant Technology, July 30 -Aug. 3, 1990; and M. Minondo et al "Comparison of .sup.11 B.sup.30 and .sup.49 BF.sub.2.sup.+ at Low Implantation Energy in Germanium Preamorphized Silicon", 9th International Conference on Ion Implant Technology, September 1992. The results were based on relatively high implant energies, i.e., boron equivalent energies of greater than 10 keV. The results were also mixed. In the Downey et al reference, for an 11.2 keV boron implant and a 50 keV BF.sub.2 implant, a smaller junction depth was observed for the BF.sub.2 implant after a rapid thermal processor anneal, but the reverse was observed after a furnace anneal. In the work of Ohyu et al, fluorine was separately implanted at 25 keV into a 10 keV boron implant, and reduced junction depths were observed.
Separate fluorine implants into boron implanted wafers have also been reported in the following references: T.H. Huang et al, "Influence of Fluorine Preamorphization on the Diffusion and Activation of Low-Energy Implanted Boron During Rapid Thermal Annealing", Appl. Phys. Lett. Vol. 65, No. 14, October 1994, pages 1829-1831; H.C. Mogul et al, "Advantages of LDD-Only Implanted Fluorine with Submicron CMOS Technologies", IEEE Trans. On Electron Devices, Vol. 44, No. 3, March 1997, pages 388-394; A. Hori et al, "High Speed 0.1um Dual Gate CMOS with Low Energy Phosphorus/Boron Implantation and Cobalt Salicide", IEDM96, 1996, pages 575-578; L. Y. Krasnobaev et al, "The Effect of Fluorine on the Redistribution of Boron in Ion-Implanted Silicon", J. Appl. Phys., Vol. 74, No. 10, November 1993, pages 6020-6022 and D. Fan et al, "Effect of Fluorine on the Diffusion of Through-Oxide Implanted Boron in Silicon", Appl. Phys. Lett., Vol. 50, No. 10, September 1991, pages 1212-1214. In these references, boron implants as low as 5 keV were used (the same effective energy as a 22.3 keV. BF.sub.2 implant), but high energy fluorine implants of 40 keV were used. In these references, no junction depths less than 1000 angstromns were reported, and no sheet resistance values or optimization of sheet resistance was reported. Recent work reported by S. B. Felch et al in "Fluorine Effects in BF.sub.2 Implants at Various Energies", 11th International Conference on Ion Implant Technology, June 1996, demonstrated that in low energy BF.sub.2 implants down to 2 keV, the fluorine leaves the surface of the silicon as a function of implant energy, dose and anneal conditions.
None of the prior art known to applicant has provided a satisfactory process for fabricating shallow junctions of selected junction depth and sheet resistance, particularly where the required junction depth cannot be obtained simply by reducing the implant energy. Accordingly, a need exists for improved methods for fabricating shallow junctions in semiconductor wafers.
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