The invention relates to a semiconductor device; and, more particularly, to a negative voltage supply device used for generating a negative voltage lower than a ground voltage in a variety of semiconductor devices.
Hereinafter, a negative voltage supply device will be explained in conjunction with a memory device that employs the negative voltage supply.
The reason that a memory device requires a negative voltage is to employ a negative word line driving scheme. The negative word line driving scheme is a scheme, in which, when a word line driver drives a word line, it supplies a high voltage VPP to the word line for enabling thereof, while it supplies a negative voltage VBBW below a ground voltage VSS to the word line for disabling thereof.
That is, the ground voltage VSS is usually supplied to the word line to disable the word line, but the negative voltage VBBW below the ground voltage VSS is supplied thereto for the same purpose in the negative word line driving scheme.
By using such a negative word line driving scheme, refresh characteristics as well as other AC parameters are improved. Especially, as the negative voltage VBBW below the ground voltage VSS is utilized as an electric potential to disable a word line, cell retention time is extended, resulting in an increase in a refresh cycle. Moreover, the negative word line driving scheme is employed because it can decrease a VPP burden by the use of a low Vcc and improve a write recovery time TWR.
FIG. 1 is a block diagram of a conventional negative voltage supply device.
As shown therein, the conventional negative voltage supply device includes a negative voltage detector 10 for determining whether to pump a negative voltage, and a negative voltage pumping unit having an oscillator 20, a pump controller 30, and a charge pump 40 for pumping the negative voltage.
The negative voltage detector 10 is a unit for detecting the level of the negative voltage VBBW, and outputs a detection signal bbweb for determining whether to pump the negative voltage. The oscillator 20 receives the detection signal bbweb and outputs a periodic signal OSC. The pump controller 30 outputs pump control signals p1, p2, g1, and g2 in response to the output signal OSC from the oscillator 20. Lastly, the charge pump 40 pumps the negative voltage VBBW in response to the pump control signals p1, p2, g1, and g2. The negative voltage pumping unit 20, 30 and 40 may be designed and implemented in various configurations in a manner that it does not includes the pump controller 30 by allowing the oscillator 20 to directly control the charge pump 40 as the case may be.
That is, the negative voltage pumping unit 20, 30 and 40 stops the pumping operation when the level of the negative voltage VBBW detected by the negative voltage detector 10 is sufficiently low (i.e., its absolute value is large). However, when the level of the negative voltage VBBW detected by the negative voltage detector 10 is high (i.e., its absolute value is small), the charge pump 40 performs the negative voltage VBBW pumping operation.
FIG. 2 is a detailed circuit diagram of the negative voltage detector 10 of FIG. 1.
As shown, a ground voltage VSS and a negative voltage VBBW are applied to the gate of a transistor P01 and the gate of a transistor P02, respectively. The transistors P01 and P02 are operative in a linear region, and function as a resistor, which distribute a high potential VCORE and a low potential VSS. For instance, when the negative voltage VBBW is high (i.e., its absolute value is small) and thus resistance of the transistor P02 increases, an electric potential of DET node increases, thereby outputting a detection signal bbweb as a ‘low’ signal bbweb from an inverter I03. On the contrary, when the negative voltage VBBW is low (i.e., its absolute value is large) and thus resistance of the transistor P02 decreases, an electric potential of DET node is lowered, thereby outputting a detection signal bbweb as a ‘high’ signal bbweb from the inverter I03.
That is to say, the negative voltage detector 10 detects the level of the negative voltage VBBW by voltage distribution of the transistors P01 and P02 taking the ground voltage VSS and the negative voltage VBBW, respectively.
FIG. 3 is a detailed circuit diagram of the oscillator 20 of FIG. 1.
As depicted in the drawing, the oscillator 20 may be configured in the shape of a ring oscillator composed of a NOR gate 21 accepting the detection signal bbweb, and inverters I04 to I09.
When a ‘high’ sensing signal bbweb is inputted to the NOR gate 21, the NOR gate 21 always outputs a ‘low’ signal. However, when a ‘low’ sensing signal bbweb is inputted, the NOR gate 21 serves as an inverter, so that a signal with a regular period is outputted by the inverters I04 to I09 connected in a ring shape.
FIG. 4 is a detailed circuit diagram of the pump controller 30 of FIG. 1, and FIG. 5 is an operation timing diagram of the pump controller 30.
As shown therein, the pump controller 30 is provided with NAND gates 31 and 32 and a plurality of inverters I10 to I19, and outputs control signals p1, p2, g1, and g2 for control of the charge pump 40. The control signals p1 and p2 are signals for the charge pump 40 to pump, and the control signals g1 and g2 are sort of precharge signals.
FIG. 6 is a detailed circuit diagram of the charge pump 40 of FIG. 1.
The charge pump 40 functions to generate the negative voltage VBBW and is provided with PMOS transistors 41, 42, 43, and 44 which receive the control signals p1, p2, g1, and g2 at nodes where its sources and drains are connected, respectively, and operate as capacitors, as shown in FIG. 6.
Briefly explaining the operation, the charge pump 40 pumps the negative voltage VBBW upon receipt of the control signals p1 and p2, and makes electric potentials at ‘a’ and ‘b’ nodes fall to the ground voltage VSS upon receipt of the control signals g1 and g2.
As described earlier, the memory device is provided with the negative voltage supply device, which generates the negative voltage VBBW and is used as an electric potential for turning a cell transistor off, i.e., a word line disabling potential, thereby enabling negative word line driving.
Meanwhile, leakage current of a cell transistor is characterized by increasing as temperature rises. Thus, the value of the negative voltage VBBW at a high temperature needs to be decreased considerably, but does not need to do so if the temperature is lowered from room temperature to a lower temperature. Accordingly, using the prior art negative voltage supply device which generates a fixed negative voltage VBBW regardless of temperature causes an excessive current consumption in pumping the negative voltage VBBW at room and low temperatures.
USPTO Backgrounds
USPTO Backgrounds