As is known, to read data cells of nonvolatile, particularly flash, memories, a row and a column to which a data cell to be read is connected are appropriately biased and current flowing through the data cell is detected. If the data cell is written, its threshold voltage is higher than a read voltage and the data cell conducts no current. If the data cell is erased, its threshold voltage is lower than the read voltage, and the data cell conducts current. Written and erased data cells are discriminated by comparing the current flowing in the data cell with a reference current generated by a reference cell.
As such, reading accuracy depends largely on an efficient operation of the reference cells and, more specifically, on having characteristics of the reference cells being as similar as possible to those of the data cells (i.e., a spread of the electrical characteristics of the reference cells is undesirable).
However, since the need to minimize spread conflicts with other design requirements, two different approaches exist in the design of reference cells. In a first approach, the data cells and the respective reference cells with which they are compared are located as close as possible to one another. In a second approach, the reference cells are located outside a memory array of data cells.
The first approach is used, for example, in EPROM memories, in which a column of an array for each output bit is used as a reference. Such a solution is shown by way of example in FIG. 1, in which a memory array is divided into two subarrays 2a and 2b, connected to a row decoder 3 for addressing several word lines 4, which are in turn connected to gate terminals of a plurality of data cells 5 and reference cells 9. Each data cell 5 and each reference cell 9 includes a drain terminal and a source terminal. The drain terminals of the data cells 5 are connected to respective bit lines 7 (one for each column in the array not used as a reference), which are in turn connected by two column decoders 6a and 6b to a plurality of sense amplifiers 10. Each sense amplifier 10 includes a first input connected to one bit line 7 addressed by the column decoders 6a and 6b; and a second input connected to a respective reference line 8, to which the reference cells 9 in the same reference column are connected.
This first approach presents several advantages. In particular, spread is minimized because each data cell 5 is located close to a respective reference cell 9. The reference cell 9 is turned on together with the data cell 5 to be read as both are connected to the same word line to eliminate any timing problems. Further, load transistors (not shown) in the data and reference branches connected to the inputs of the sense amplifiers 10 are the same. On the other hand, the first approach also presents disadvantages. The reference cells 9 are subjected to stress by undergoing the same operations as the data cells 5. The first approach is also particularly bulky in that one column of the array for each output bit cannot be used for storing data.
When applied to flash memories, further disadvantages of the first approach are encountered. First of all, a ground of the reference columns must be separate from the rest of the subarray to which they belong, otherwise their data cells 5 would become depleted when erasing via the source terminal. Furthermore, the reference columns are subjected to stress which may lead to cycling problems in multiple erase and write cycle operations. Finally, in the event of an undesirable UV threshold being obtained during fabrication, it is not feasible to match the threshold voltages of individual reference cells, e.g., to correct the threshold voltages of all the cells in the same column.
The second approach provides for a writing and erasing of reference cells during testing so as to obtain the best possible reference. On the other hand, the characteristic spread of the reference cells assumes greater importance because of the physical distance between the reference cells and respective data cells and between the reference cells themselves. One solution to the problem is to use a single reference cell, e.g., a single reference branch connected to a plurality of sense amplifiers as shown in FIG. 2. Two sense amplifiers 10 each have a first input connected to a common reference branch 16, and a second input connected to a respective array branch 17. A column decoder 18 is interposed between two bit lines 7 and two respective biasing circuits 19. A current/voltage converter 20 for converting current flowing in two data cells 5 and in a single reference cell 22 is shown. The converter 20 comprises a PMOS load transistor 23 for each array branch 17, and a diode-connected PMOS load transistor 24 for a common reference branch 16.
In the circuit shown in FIG. 2, two capacitors 25 represent a parasitic capacitance between a gate terminal 27 and a drain terminal 28 of each load transistor 23. Two capacitors 26 represent capacitances of the other bit lines (not shown) connected to the array branches 17 via the column decoder 18. The capacitors 25 and 26 form capacitive couplings between the array branches 17 and the common reference branch 16 so that when outputs of the sense amplifiers 10 switch, a voltage shift in the array branch 17 of each sense amplifier 10 may result in read problems by disturbing the common reference branch 16.
The above drawback may be overcome by modifying the current/voltage converter 20 as shown in FIG. 3, in which a load transistor 23' of the array branch 17 and a load transistor 24' of the common reference branch 16 are diode-connected and do not have gate terminals connected to one another. As a result of the modification shown in FIG. 3, the transistors 23 and 24 shown in FIG. 2 are replaced by two transistors 23' and the transistor 24' each having a gate terminal, a drain terminal, and a source terminal. Such a solution, however, impairs the dynamic performance of the circuit because the terminals 28 of the array branches 17 reach at most a voltage of V.sub.CC -V.sub.TH, where V.sub.CC is a supply voltage along a line 30 to which the source terminals of the transistors 23' and 24' are connected, and V.sub.TH is a threshold voltage of the transistors 23', which is a minimum voltage drop between the source and gate terminals of the transistors 23' for them to be turned on. A reduction in dynamic performance, on the other hand, is to be avoided, and is by no means negligible when the circuit operates at low supply voltage.
USPTO Backgrounds
USPTO Backgrounds