Comparison of a plurality of digital input words has been accomplished in the prior art through the use of an iterative comparison of pairs of the input words or a binary tree configuration also known as binary decimation. Significant ripple delay is inherent in either of these two comparison methods. In the first prior art approach, the first digital word is compared with the second word and the larger (or smaller) word is selected for comparison with the third input word. This process is continued with a selection of the larger word at each step until all of the inputs have been sampled.
The second prior art approach simultaneously compares pairs of inputs selecting the larger or smaller input of each pair which is then in turn compared with the selection from the adjacent pair. This approach is demonstrated in FIG. 1 of the drawings. Implementation is accomplished by providing each pair of inputs to a digital comparator. The output of each comparator provides a selection signal for a multiplexer which also receives the input pair. The output of the multiplexer is paired with the output of a second multiplexer and provided to an additional digital comparator, the output of which selects from a second level multiplexer to transmit the selected second level choice. As can be appreciated from the four word comparator shown in FIG. 1, significant quantities of hardware are required for implementation of comparison of larger numbers of inputs.
With either of the two prior art methods, the large number of logic gates required for implementation results in high power requirements. The combination of power and size for architectures implementing these prior art methods significantly limits the number of inputs which may be compared if the comparator architecture is to be implemented monolithically. Power and size problems limit the practical comparison to about six words.
Even with monolithic implementation, the critical path delay created by the architecture requirement significantly limits the allowable bandwidth for the system in which the comparator is used. In many modern communication systems where algorithms require rapid comparison of multiple digital words, this limitation is unacceptable.
It is therefore desirable to provide a comparator for a plurality of digital input words which will simultaneously compare all of the input words for minimum delay.
USPTO Backgrounds
USPTO Backgrounds