1. Field of the Invention
The present invention generally relates to testing of computer memory cells and more particularly to an improved method and system for testing multi-port SRAM cells that tests the situation where multiple ports are accessed within a critical time.
2. Description of the Related Art
Multi-port static random access memory SRAM cells are well known in the art. For example, as shown in FIG. 1, a conventional 2-port SRAM cell includes cross-coupled inverters 100 connected to NFET transistors 101-104. The 2-port SRAM cell is bordered by the port A wordline select 125, the port B wordline select 126, the port A bitline true and complement 115, 116 and the port B bitline true and complement 120, 121. All wordlines 125, 126 and bitlines 115, 116, 120, 121 are connected to an addressing unit and a read/write controller which controls the writing to and reading from the selected SRAM cell. FIG. 1 also illustrates bitline restore devices 105.varies.108 (PFET transistors) that are connected to voltage sources 130 and the port A bitline restore select line 110 and the port B bitline restore select line 111.
In operation, a read cycle begins with bitline restore control lines 110 and 111 in the low state (voltage at ground) and bitline pairs 115, 116 and 120, 121, respectively, in the precharged high state (voltage at Vdd). Wordlines 125 and 126 also start in the low state. The internal storage nodes start in a state where one of them (150 or 151) is in the high state and the other (151 or 150) is in the low state. For example, assume that node 150 (complement node) starts in the low state and node 151 (true node) starts in the high state. This would reflect a logical "one" stored in the cell.
For a port A read operation, node "Restore A"(110) switches to the high state, turning off PFETs 105, 107 and 141 and tri-stating port A's true and complement bitlines 115, 116. Port A's wordline125 switches to the high state, turning on NFETs 101 and 103 and connecting port A true and complement bitlines (115 and 116) to the internal storage nodes of the cell. In this example, bitline115 will remain in the high state while bitline116's capacitance discharges into the cell node (150) that is in the low state. This causes the voltage on node 150 to rise "slightly" until the bitline116 is fully discharged, at which point, node 150's voltage returns to ground. If this low internal node (150) rises significantly, it can cause the cell nodes to fully switch, thereby causing the cell's stored data to change it's logical value from a "one" to a "zero". This problem is commonly referred to, by those skilled in the art, as "read instability". A static SRAM cell must be designed to be "read stable". Furthermore, an adequate test for an SRAM cell will stress the "read instability" condition.
To complete the cycle, the port A wordline (125) switches to the low state, thereby disconnecting the bitlines from the cell's internal storage nodes (150, 151). The port A restore line (110) then switches to the low state, turning on PFETs 105, 107 and 141, which in turn precharges the bitlines 115 and 116. The cell data has been read, and all nodes have returned to their original starting state.
For a Port B read operation, the circuit would behave similarly, utilizing restore select line 111, wordline 126 and bitlines 120, 121. Read stability for a Port B read operation will be equally important. As important as this is for a single port read operation, the read stability of the SRAM cell becomes even more important for multi-port memories.
In the illustrated dual-port SRAM cell, one must consider the read stability of the internal storage nodes 150, 151 when accessing data through both ports A and B simultaneously. For example, when both ports A and B in the dual-port static random access memory (SRAM) cell (containing a logical "one") are read simultaneous, both bitlines (e.g., 116, 121) discharge simultaneously into the same "low state" internal storage node (i.e., 150) of the cell. As a result, the increased current into the cell causes the internal "low state" node (150) to rise significantly more than during the previously described single port read access. The maximum read instability will occur when both ports are accessed at precisely the same time.
A dual-port memory cell of such a design must be designed such that, given the absence of any manufacturing defects, the cell will retain it's data for the worst case "read instability" read operation. To those skilled in the art, it is readily apparent that such a design may be achieved by utilizing transistor sizes within the cell, such that the read stability is optimized. Furthermore, it is also understood that process variation must be taken into account when deciding upon transistor sizes.
However, regardless of how well a cell is designed with respect to "read instability", a manufacturing process defect mechanism may occur within the cell, such that the "read stability" of the cell is compromised. It is important to test all cells for the presence of such a defect, prior to delivering products containing the above-mentioned cell design.
Therefore, it is important during testing to determine whether the 2-port SRAM cell will remain stable when both ports are simultaneously accessed. One might attempt to test the cell for read stability by actually accessing the cell from both ports simultaneously. However, performing a test which activates both ports simultaneously has posed a unique challenge to the test community in the past.
More specifically, it is very difficult to match the activation of bitline pair A 115-116 and bitline pair B 120-121, principally because of the different delay paths which precede the different bitline pairs. This is especially true because the bitlines will be activated for a very short period (e.g., picoseconds). Therefore, if the bitlines are not activated within picoseconds of each other, there will not be simultaneous activation.
Only tester clock edge schmooing techniques have been able to conventionally test the read stability of 2-port SRAM cell. Such techniques involve repeatedly adjusting one bitline's clock signal over a range while holding the other bitline's clock signal consistent. In this way, the schmooing technique hopes to simultaneously activate the different bitlines. However, due to time-step granularity limitations, even with such techniques, a simultaneous activation is not guaranteed.
Further, such schmooing techniques have certain limitations, one of which is the difficulty or impracticality of applying clock schmooing when built-in self-test (BIST) methods are employed to test the array at manufacturing test. This is because BIST utilizes only one clock path to access the cell from either port A or B. With only one clock during BIST, it is fundamentally impractical to use a schmooing technique.
Another serious limitation of this technique, and perhaps the most significant, is the prohibitive test time and associated cost involved with schmooing techniques. Schmooing techniques require multiple passes of reading each cell, perhaps as many as several hundred or more passes. Additionally, such techniques do not lend themselves to gathering the large amounts of data required for adequate bit fail mapping.
The invention described below provides an alternative to schmooing that is less time intensive and less expensive.
USPTO Backgrounds
USPTO Backgrounds