The present invention relates generally to the field of semiconductor devices, and more particularly to non-planar semiconductor devices.
As electronic components become smaller, control over electron flow across an integrated circuit is diminished. The current complimentary metal-oxide semiconductor (CMOS) technology roadmap calls for the size of integrated circuit components to be cut in half every two years. To maintain this roadmap, non-planar architectures have been developed including the use of trigates and finFETs. While new CMOS architectures have proven to be efficient, challenges still exist in integrating 3-dimensional elements onto an integrated circuit chip.
USPTO Backgrounds
USPTO Backgrounds