The present invention concerns the formation of a thin gate oxide beneath a gate electrode overlying a source-drain channel of a field effect transistor. The gate oxide is extremely thin (on the order of only Angstroms in thickness) and must be at least nearly free of defects in its amorphous silicon dioxide structure, such as dangling silicon or oxygen bonds. Such dangling bonds create quasi-mobile charge in the gate oxide, leading to two problems. One problem is that the electric fields associated with such charge perturb carrier motion in the source-drain channel, preventing a smooth current flow. Another problem is that such charge, to the extent it is mobile, may contribute to leakage between the gate electrode and the source-drain channel. Therefore, processes for forming the gate oxide must be free of any tendency to form defects in the gate oxide. Currently, only thermal oxide growth processes meet such criteria.
Thermal processes for forming the gate oxide layer have worked well in fabrication of semiconductor devices of the larger feature sizes used in the past. Such thermal processes tend to form high quality gate oxide layers that are free of defects such as dangling bonds or contaminant particles. Moreover, the gate oxide thickness tends to be uniform across the gate area. Unfortunately, as feature sizes are becoming much smaller and different gate oxides are employed in the next generation of advanced technologies, the high wafer temperatures required in thermal oxidation processes are problematic in that the sharp junction definitions which are now required become diffused at the higher temperatures (e.g., above 700° C.). Such a distortion of junction definitions and other features can lead to device failure.
One possible solution to this problem is to employ low temperature plasma processing to form the gate oxide layer. In attempting to do this, other problems have been encountered that render plasma processing apparently useless for gate oxide formation. First, at high chamber pressure (e.g., 100 mT), contaminants tend to accumulate in the gate oxide layer during formation, leading to fatal defects in the gate oxide structure such as dangling bonds or mobile charge. In order to reduce such defects, the chamber pressure can be reduce (e.g., down to tens of mT) by increasing the evacuation rate. While this approach can reduce contamination, it suffers from a tendency to increase plasma ion energy so that the gate oxide layer suffers ion bombardment damage, creating the same type of defects that were sought to be avoided, including dangling bonds and mobile charge. Also, the gate oxide thickness is non-uniform. Thus, it would seem that plasma processing is not feasible, and there has appeared to be no way in which a high quality gate oxide could be formed without raising the wafer temperature beyond allowable limits for the latest generation of devices.
Accordingly, what is needed is a low temperature process for forming a very high quality (defect-free) thin gate oxide layer of uniform thickness.
USPTO Backgrounds
USPTO Backgrounds