Duobinary modulation is an interesting scheme for high data rate communication as it can use a channel's limited bandwidth advantageously to shape the signal thus requiring less equalization compared to NRZ modulation. However, designers face speed limitation problems in high-speed receivers for duobinary signals.
The reception of duobinary modulation involves decoding bit values from a received multilevel signal. This may be realized by an analog to digital converter (ADC) which directly decodes the signal level into bit values. However, circuit implementations of a high-speed ADC are characterized by high power consumption and limited analog bandwidth, making them unsuitable for interconnects operating in range of multi-ten-Gbps.
Another proposed solution is a receiver comprising a wideband amplifier followed by a wideband signal splitter. Two copies of a X Gbps signal are compared with threshold voltages corresponding to upper and lower eye levels. Subsequently a D-type flip-flop is used to hold signal values when triggered by a clock signal and values are compared in an XOR circuit. The result of the logical operation is the decoded NRZ data stream which is further processed to demultiplexed low speed (X/2 Gbps) data streams. The problem of this implementation is that the receiver chain operates at the rate corresponding to the symbol rate of the incoming signal (X Gbps). This puts a stringent limitation on the XOR logic gate settling time and effectively limits the maximum achievable symbol rate of the receiver.
USPTO Backgrounds
USPTO Backgrounds