1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a static semiconductor memory device (Static Random Access Memory; SRAM) of which memory cells include inverter latches. More particularly, the invention relates to a configuration for stably writing and reading data even under a low power supply voltage condition in a static semiconductor memory device.
2. Description of the Background Art
When transistors are miniaturized with development of miniaturization technology, voltage scaling according to the miniaturization is required from the viewpoint of reliability and power consumption. However, an influence by variations in manufacturing parameters increases in accordance with miniaturization, and accordingly, threshold voltages of transistors forming memory cells vary increasingly so that an operation margin of a memory lowers, and it becomes difficult to perform stable reading and writing with a low power supply voltage.
Various configurations have been proposed aiming to stably write and read data in the SRAM (Static Random Access Memory) even with such a low power supply voltage.
For example, a prior art reference 1 (Japanese Patent Laying-Open No. 2002-042476) has disclosed such a configuration that a voltage at the same level as an external power supply voltage is supplied to SRAM cells as an operation power supply voltage in a data read operation, and a voltage (VCC−VTH) lower than the external power supply voltage is supplied to the memory cells as the operation power supply voltage in a data write operation. In the data write operation, a Static Noise Margin (SNM) of the memory cell selected by a word line decreases so that data held in the memory cell can be easily inverted, and a write margin is improved.
A prior art reference (Japanese Patent Laying-Open No. 2004-303340) has disclosed a configuration in which substrate (back gate) potentials are controlled in units of SRAM cell columns so that the back gate potentials of the memory cells in a selected column are made different between the data writing and the data reading, to speed up the data writing. In the data writing, the source to the back gate is deeply reverse-biased, to reduce the static noise margin of the memory cell for performing fast data writing. In the read operation, the source to the back gate of the memory cell transistor is shallowly reverse-biased, to increase the static noise margin for holding the data stably.
Further, a prior art reference 3 (Japanese Patent Laying-Open No. 2004-362695) has disclosed a configuration in which voltage levels of VDD and VSS source lines supplying high and low-power supply voltages to the memory cells are controlled in units of SRAM cell columns. In the standby state and the data write operation, levels of power supply voltages VDD/VSS are set to a level at which an absolute value of a gate-source voltage of a memory cell transistor is reduced so that a gate leakage current is suppressed, and a current consumption in the write operation and standby state is reduced. In a read operation, the VDD/VSS source line potential in the selected column are set to a level at which the absolute value of the gate to source voltage of the memory cell transistor is increased to increase a current drive power of the memory cell transistor for achieving fast data reading.
In the configuration disclosed by the prior art reference 1, a common voltage is supplied from a voltage supply circuit to the memory cells in the memory cell array as an internal power supply voltage of the memory cells. Therefore, the write margin can be improved by lowering the internal voltage (operation power supply voltage) of the memory cells in the write cycle. All the memory cells connected to the word line that is selected and activated by a row decoder have the internal voltage lowered. Therefore, the static noise margin decreases in the memory cell on the column that is selected by a column decoder as a write target, allowing easy writing. At the same time, however, the static noise margins similarly lower in the memory cells of non-write-target on an unselected column and the selected row, and writing of data (inversion of held data) is liable to occur in these memory cells. Therefore, read margins (static noise margins) decrease in these memory cells on the selected row and the unselected column, and a bit line current (column current) may invert the data to cause destruction of stored data.
The configuration disclosed in the prior art reference 2 changes the substrate potentials on a column-by-column basis for improving the write margin. A column address signal is used for controlling the setting of substrate potentials of a selected column and unselected columns. For controlling the voltage on a column-by-column basis, the substrate region is formed of a well region common to the memory cells in one column, and has relatively large resistance and capacitance. In particular, when the memory cell capacity is increased, an increased number of memory cells are arranged in one column. For suppressing the interconnection resistance and capacitance of the substrate region in such a state, it is desired to arrange switching elements in a plurality of positions of each column for selecting a substrate potential. For selecting the substrate potential in this case, a column address signal interconnection for the column selection must be made for the switching elements provided for selecting the substrate potential. This increases the number of interconnection lines to increase an interconnection layout area, resulting in an increased area of a memory cell array. Further, a drive circuit and others are additionally required for fast transmission of a column address signal (column select signal) to the switching elements provided for the substrate potential selection, and this configuration increases a circuit scale as well as current consumption. Further, the above configuration increases lengths of interconnection lines that transmit signals for controlling the switching elements provided for the substrate potential selection, which increases the charge/discharge currents on the interconnection lines transmitting the switching element control signals, and thus increases power consumption.
It is necessary to make an adjustment between timing of change of the substrate potential and timing of change of the column address signal so that data writing into the memory cell may be performed in such a state that the static noise margin of the memory cell is lowered. This results in a problem that timing design is difficult.
In the configuration disclosed by the prior art reference 3, the potentials of the VDD/VSS source lines are controlled in units of memory cell columns. Although high-side power supply potential (VDD source potential) of the memory cells or the low-side power supply voltage (VSS source potential) of the memory cells is controlled, this prior art reference 3 aims at reducing the power consumption by reducing the gate leakage current of the memory cell on the unselected column or in the standby state and reducing the charging/discharging currents of the bit lines on the selected column. The prior art reference 3 fails to disclose a configuration for improving the write margin in the data writing. Since the column select signal is used for controlling the potentials of the VDD and VSS source lines, problems similar to those in the prior art reference 2 may occur depending on arrangements of the potential control switches.
USPTO Backgrounds
USPTO Backgrounds