1. Field of the Invention
The present disclosure relates to the organic light emitting diode display and the fabricating method thereof.
2. Discussion of the Related Art
Recently, various flat panel display devices are actively and widely spread to the display applications for overcoming the heavy weight and large volume of the cathode ray tube. For these flat panel display devices, there are liquid crystal display (or “LCD”) device, field emission display (or “FED”) device, plasma display panel (or “PDP”), electroluminescence device and so on.
The electroluminescence devices are classified into the inorganic light emitting diode display and the organic light emitting diode display, according to the material of the light emitting layer. As adapting the self-light-emitting material, the electroluminescence device has various merits such as fast response speed, excellent light emitting efficiency, high brightness and wide view angle.
The active matrix type organic light emitting diode display (or “AMOLED”) represents images by controlling the electric current flowing to the organic light emitting diode (or “OLED”) using thin film transistor. The organic light emitting diode display is classified into the top emission type and the bottom emission type according to the structure of the OLED including the anode electrode, the cathode electrode and the organic layer. The bottom emission type irradiates the visible light generated from the organic layer to the lower part of the substrate having TFT. In the interim, the top emission type irradiates the visible light to the upper part of the substrate having TFT.
FIG. 1 illustrates a cross-sectional structure of a pixel in the top emission type organic light emitting diode display device. FIG. 2 is a plan view illustrating the switch TFT of the FIG. 1.
Referring to FIG. 1, the OLED according to the related art comprises the data line and the gate line formed on substrate 10, switch TFT (SWTFT), drive TFT (DRTFT), storage capacitor, overcoat 18, buffer layer 19, cathode electrode 20, bank pattern 21, organic layer 22, and anode electrode 23.
On the substrate 10, the gate metal pattern is formed, including gate line, switch TFT (SWTFT) connecting to the gate line, and the gate electrodes 11a and 11b of the drive TFT (DRTFT). The gate insulating layer 12 is formed on the substrate 10 having the gate metal pattern for covering the gate metal pattern. The active layers 13a and 13b of the switch TFT (SWTFT) and the drive TFT (DRTFT) is formed on the gate insulating layer 12 by the semiconductor pattern. The source/drain metal pattern including source electrodes 14a and 14b and the drain electrodes 15a and 15b of the switch TFT (SWTFT) and the drive TFT (DRTFT) is formed on the semiconductor pattern and the gate insulating layer 12. The passivation layer 16 is formed on the source/drain metal pattern and the gate insulating layer 12. Some portion of the drain electrode 15 of the switch TFT (SWTFT) is exposed through the contact hole penetrating the passivation layer 16. In addition, some portion of the gate electrode 11b of the drive TFT (DRTFT) is exposed through the contact hole penetrating the passivation layer 16 and the gate insulating layer 12. On the passivation layer 16, the contact electrode pattern 17 made of a transparent conductive material is formed. The contact electrode pattern 17 contacts to the drain electrode of the switch TFT (SWTFT) through the contact hole penetrating the passivation layer 16, and to the gate electrode 11b of the drive TFT (DRTFT) through the contact hole penetrating the passivation layer 16 and the gate insulating layer 12 so that the switch TFT (SWTFT) and the drive TFT (DRTFT) are electrically connected. The overcoat layer 18 including the organic insulating material such as polyimide or photoacrylic is formed on the passivation layer 16 and the contact electrode pattern 17. Some portion of the drain electrode 15b of the drive TFT (DRTFT) is exposed through the drain contact hole (DH) penetrating the overcoat layer 18. On the overcoat layer 18, the buffer layer 19 made of silicon nitride (SiNx) is formed. On the some portion of the buffer layer 19 and the exposed drain electrode 15b of the drive TFT (DRTFT), the cathode electrode 20 made of aluminum (Al) is formed. The bank pattern 21 including inorganic material such as silicon nitride (SiNx) is formed on some portion of the cathode electrode 20 and the buffer layer 19 to design the aperture area (EA) of pixel. On the bank pattern 21 and the cathode electrode 20, the organic layer 22 and the anode electrode 23 including ITO (indium tin oxide) are formed sequentially. The anode electrode 23 is supplied with a high voltage.
In the OLED as shown in FIG. 1, the drain contact hole (DH) penetrating the overcoat layer 18 having uniform thickness is formed within the aperture area (EA). Therefore, the thickness of the organic layer 22 within the aperture area (EA) has not uniform thickness because the area (A) of drain contact hole (DH) has thinner organic layer 22 than other areas due to the step shape of the drain contact hole (DH). Generally, the brightness of the pixel is reversely proportional to the thickness of the organic layer per unit area. Therefore, the brightness of one pixel can be varied according to the position. That is, the brightness at the area (A) of the drain contact hole (DH) is higher than other areas. Like this, if the brightness of some area (A) in one pixel is high, the organic layer of the area (A) can easily be degraded due to the stress focused thereon. If some area portion (A) of the organic layer in one aperture area (EA) is degraded, this portion is acknowledged as an error point of brightness. Due to this fault of organic layer around the drain contact hole (DH), the OLED according to the related art has inferior image quality and short life time of the display panel.
When the TFTs are formed with the n type semiconductor layer in the OLED shown in FIG. 1, the semiconductor layer of the TFT includes the silicon layer and the n+ ion-dopped layer on the silicon layer. The n+ ion-dopped layer plays role of ohmic contact between the silicon layer and the metal layer thereon. The n+ ion-dopped layer should be removed on the channel layer using the dry etching method. At designing the TFT, if the semiconductor layer 13a is misaligned with the gate electrode 11a with amount “B” based on the edges of the channel as shown in FIG. 2, then the semiconductor layer 13a has the step difference at the misaligned portion (B) as shown in FIG. 1. In this case, the n+ ion-dopped layer of the semiconductor layer 13a at this stepped portion cannot be easily removed unlike other plane portions. If the n+ ion-dopped layer is not properly removed at the channel of TFT, an unwanted leakage current may be occurred at the off level of TFT.
FIG. 3 is the graph illustrating the TFT leakage current amount at the Off-level due to the residual n+ ion-dopped layer at the channel portion. As shown in FIG. 3, the maximum TFT leakage current amount at the Off-level due to the residual n+ ion-dopped layer at the channel portion according to a plurality experiment result is about 1×10−9 A. It is very large electric current. Like this, when the TFT leakage current amount is so high, the voltage keeping performance of the storage capacitor may be lowered. It causes the defects on display quality such as flicker or lowered contrast ratio due to degraded black gray-scale characteristics.
USPTO Backgrounds
USPTO Backgrounds