Technical Field
The present disclosure relates to the field of integrated circuit technology. The present disclosure relates more particularly to transistors formed in integrated circuit dies.
Description of the Related Art
The transistor is a fundamental component of many integrated circuits. A single integrated circuit die can include billions of transistors formed in a semiconductor substrate. In order to decrease the cost and increase the complexity of integrated circuits, integrated circuit technology is continually scaling downward. In particular, the dimensions of the transistors are decreased in order to fit more transistors in a given area of a semiconductor substrate.
Ultra Thin Body and Box (UTBB) Fully Depleted Silicon On Insulator (FDSOI) technology provides many benefits to transistor functionality. These benefits can include adding the ability to adjust the threshold voltage Vth of a transistor and improving electrostatics in the channel region by back biasing the channel region via application of a voltage to a bulk layer of semiconductor material separated from the channel region by a dielectric layer.
FIGS. 1A-1C illustrate an integrated circuit die 100 including a transistor 101 implementing UTBB FDSOI technology. FIGS. 1A, 1B are cross-sections of the transistor 101 in the integrated circuit die 100, while FIG. 1C is a top view of the transistor in the integrated circuit die.
With reference to FIG. 1A, the integrated circuit die 100 includes the transistor 101 formed on an FDSOI substrate 102. The FDSOI substrate 102 includes a first layer of semiconductor material 104, a buried oxide layer (BOX) 106, and a second layer of semiconductor material 108. A raised source region 110 and a raised drain region 112 extend from the second layer of semiconductor material 108. A gate structure 114 overlies a channel region 116 positioned in the second layer of semiconductor material 108. The gate structure 114 includes a gate dielectric 118 positioned directly over the channel region 116 of the transistor 101, a metal gate positioned on the gate dielectric 118. The metal gate includes a conductive liner 120 and a gate electrode 122 positioned on the gate dielectric. Sidewall spacers 124 are positioned between the raised source and drain regions 110, 112 and the gate dielectric 118. A dielectric cap 126 is positioned on the gate electrode 122. A shallow trench isolation region 128 is formed in the substrate 102 on each side of the second layer of semiconductor material 108.
The cross-sectional view of FIG. 1B shows many of the same layers and structures as shown in FIG. 1A, but from a view perpendicular to the view shown in FIG. 1A as can be more clearly understood with reference to the cross section lines 1A, 1B indicated in FIG. 1C. In particular, the cross-section of FIG. 1B does not pass through the source and drain regions 110, 112 of the transistor 101. Thus, the raised source and drain regions 110, 112 are not apparent in FIG. 1B. FIG. 1B illustrates that the sidewall spacers 124 are positioned over the trench isolation 128 at either end of the gate structure 114.
The transistor 101 allows a drain current ID to flow from the drain 112 to the source 110 through the channel region 116 in the second layer of semiconductor material 108 below the gate dielectric 118. The drain current ID can be controlled by applying a voltage to the gate electrode 122. In CMOS applications, the transistor 101 is typically used as a simple switch having an on mode and an off mode. When the transistor 101 is off, the drain current ID is substantially zero. When the transistor 101 is on, the transistor operates in saturation mode and the drain current ID flows between the drain region 112 and the source region 110. The magnitude of the drain current ID is approximated by the following formula:
      I    D    =                    μ        n            ⁡              (                              C            ox                    2                )              ⁢          (              W        L            )        ⁢                            (                                    V              gs                        -                          V              th                                )                2            .      
As can be seen from the expression above, the drain current ID depends on many factors, including the carrier mobility (μn for n-channel devices, μp for p-channel devices), the gate oxide capacitance Cox, the ratio of the channel width W to the channel length L, the threshold voltage Vth of the transistor, and the gate to source voltage Vgs. Thus, a selected value for the drain current ID can be achieved by selecting particular values for Vgs, the width to length ratio W/L, the carrier mobility μn, and the gate oxide capacitance Cox.
In some applications, it is beneficial to have a relatively high current footprint, i.e., a high amount of current per surface area of a semiconductor substrate. However, as integrated circuit technology continues to scale downward, there are difficulties involved with maintaining a high current density while scaling down the dimensions of the transistors. For example, as the dimensions of the transistors continue to scale downward, the supply voltages available to the integrated circuit die typically decrease as well in order to reduce power consumption and to not damage the transistors.
As can be seen from the drain current equation above, one way to increase the drain current ID is to increase the channel width W and/or to decrease the channel length L. As seen in FIGS. 1B and 1C, the width W of the channel 116 corresponds to the portion of the gate structure 114 that is directly over the second layer of semiconductor material 108 between trench isolation regions 128. The length L of the channel region 116 corresponds to the length of the gate electrode 122 directly above the second layer of semiconductor material 108 between the source and drain regions 110, 112.
The extent to which the channel width L can be decreased is limited in part by restraints associated with photolithography techniques. Likewise, simply increasing the width W of the channel 116 in a conventional manner by extending the gate structure 114 reduces the number of transistor that can be formed in a given area of a semiconductor substrate. Thus, increasing the width to length ratio W/L in a planar transistor can be difficult.
USPTO Backgrounds
USPTO Backgrounds