Static random access memories (SRAMs) are generally used in applications requiring high speed, such as a cache memory in a data processing system. A SRAM is usually implemented as an array of memory cells organized in rows and columns. Each SRAM cell stores one bit of data and is implemented as a pair of cross-coupled inverters. The SRAM cell is only stable in one of two possible voltage levels. The logic state of the cell is determined by whichever of the two inverter outputs is a logic high, and can be made to change states by applying a voltage of sufficient magnitude and duration to the appropriate cell input. The stability of a SRAM cell is an important issue when designing a SRAM. The SRAM cell must be stable against transients, process variations, soft error, and power supply fluctuations which may cause the cell to inadvertently change logic states, yet still provide high speed and low power operation.
FIG. 1 illustrates in schematic diagram form, an array of prior art SRAM cells 10-13. SRAM cells 10-13 are conventional four transistor SRAM cells having polysilicon load elements and N-channel MOS transistors. SRAM cell 10 includes load elements 15 and 16, pull-down transistors 17 and 18, and coupling transistors 19 and 20. Each of the other cells 11-13 have load elements and transistors similar to those of cell 10. A gate of each of the coupling transistors of cells 10-13 is connected to a word line labeled "WL". Coupled to a drain/source terminal of each cell is a bit line. For example, cell 10 is coupled to bit line pair BL.sub.0 /BL.sub.0 *, and cell 11 is coupled to bit line pair BL.sub.1 /BL.sub.1 *. A bit of data is represented as a logic high voltage on one of storage nodes 101 or 102. The load elements are polysilicon load resistors, and are connected to a power supply voltage terminal labeled "V.sub.DD " for receiving a positive power supply voltage. A power supply voltage terminal labeled "V.sub.SS " is at zero volts, or ground potential. A diffusion layer is used to couple SRAM cells 10-13 to the V.sub.SS terminal. In an array including SRAM cells 10-13, V.sub.SS is provided to the diffusion layer every fourth cell as illustrated by a V.sub.SS terminal on either end. V.sub.SS is distributed across the array using a metal layer, usually aluminum. The diffusion layer has a relatively large parasitic resistance as compared to metal. As illustrated in FIG. 1, cells 10 and 13 are closer to V.sub.SS than cells 11 and 12. Resistor 43 represents the parasitic resistance of the diffusion layer between the sources of transistors 17 and 18 of cell 10. Resistor 44 represents the parasitic resistance of the ground path between the sources of pull-down transistors 23 and 24 of cell 11. Resistor 45 represents the parasitic resistance of the ground path between the sources of pull-down transistors 30 and 31 of cell 12. Resistor 46 represents the parasitic resistance of the ground path between the source of pull-down transistor 38 and V.sub.SS. The parasitic resistances cause the ground paths of the cells to be imbalanced. That is, all of the sources of the pull-down transistors may not be at ground potential. An imbalance in the ground path may also affect cell stability.
In FIG. 1 the channel width of the coupling transistors is denoted as W.sub.1 and the channel length is denoted as L.sub.1. The channel width of the pull-down transistors is denoted as W.sub.2 and the channel length is denoted as L.sub.2. A cell ratio is defined as EQU (W.sub.2 /L.sub.2)/(W.sub.1 /L.sub.1)
The cell ratio is used to describe a SRAM cell's stability against the influences of factors such as power supply fluctuations and noise. Normally, the higher the cell ratio, the greater the cell's stability. Generally, channel length L.sub.2 is equal to channel length L.sub.1, and channel width W.sub.2 is about 3 times wider than channel width W.sub.1.
To write a data bit into cell 10, word line WL is a logic high voltage, causing the coupling transistors of each of cells 10-13 to be conductive. The contents of cell 10 is over-written by applying a differential voltage to bit line pair BL.sub.0 /BL.sub.0 * that is large enough to cause storage nodes 101 and 102 to change logic states. Assume, for example, that a logic zero is to be written into cell 10. Bit line BL.sub.0 is a logic high voltage and bit line BL.sub.0 * is a logic low voltage. The logic high voltage of bit line BL.sub.0 is provided to the drain of pull-down transistor 18 at node 102, and to the gate of pull-down transistor 17. The logic low voltage of bit line BL.sub.0 * is provided to the drain of pull-down transistor 17 and to the gate of pull-down transistor 18. Pull-down transistor 17 is conductive, causing node 101 to be coupled to V.sub.SS. Pull-down transistor 18 is substantially non-conductive, causing node 102 to be at a logic high voltage. The logic high at node 102 keeps the gate of pull-down transistor 17 at a logic high voltage, so that cell 10 is intended to be latched in a relatively stable state until over-written with another write cycle.
To read cell 10, word line WL is a logic high voltage to select all of the cells coupled to word line WL. When word line WL becomes a logic high, all of the cells connected to word line WL provide their contents to their respective bit line pairs, however, only the bit line pair that is selected will provide its contents to output circuitry. The bit line pairs are generally precharged and equalized to a predetermined voltage at the beginning of a read cycle. When word line WL is selected, coupling transistors 19 and 20 are conductive. If storage node 101 is a logic high voltage, bit line BL.sub.0 is pulled low through transistor 18, and bit line BL.sub.0 * remains at a logic high voltage, causing a logic one to be read. The conductance of pull-down transistor 18 is higher than the conductance of coupling transistor 19, since channel width W.sub.2 is wider than channel width W.sub.1. This prevents the drain voltage of transistor 18 from rising above the threshold voltage (V.sub.T) of transistor 17, thereby preventing transistor 17 from becoming conductive. However, because of the imbalance in the ground path caused by parasitic resistor 43 in cell 10, the gate-to-source voltage (V.sub.GS) of transistor 18 is lower than the V.sub.GS of transistor 17. Non-conductive transistor 17 may become conductive as a result of the precharge on bit line BL.sub.0. This may reduce the voltage of the high node, which in this case is node 101, and cause the cell to inadvertently change logic states during a read cycle. This is less of a problem for cells 11 and 12 because there is less imbalance in their ground path through the diffusion layer to V.sub.SS. The cells that are adjacent to V.sub.SS, such as cells 10 and 13, are most likely to fail during a read cycle.
One solution to this problem is to provide more metal V.sub.SS lines across the SRAM array, since metal has a lower resistance than a diffusion layer, however this solution may significantly increase the size of the memory array.
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