The present invention relates to a scan-out system having a simple circuit arrangement including a shift register formed by a memory or register file.
The fabrication of a circuit such as an LSI introduces difficulties in directly detecting the state of the LSI because the number of input/output pins is limited. The scan-out method is effective for directly detecting the state of the internal circuit through the limited number of input/output pins.
FIG. 1 shows the outline of a scan-out system. Reference numerals 1-0 to 1-2 indicate logical blocks; 2 designates a scan address register; 3-0 to 3-5 identify flip-flops; and 4-A and 4-B denote multiplexers. The flip-flops are respectively assigned addresses which are called scan addresses. The scan addresses are each set in the scan address register 2, the low-order address represents a scan address in the logical block and the high-order address identifies the logical block. In the illustrated example, the low-order address of the scan address is provided in common to the multiplexer 4-A and each logical block 1-0 to 1-2 and the status of one flip-flop in each logical block 1-0 to 1-2 is read out in parallel. Data read out from the logical blocks 1-0, 1-1 and 1-2 are input to the multiplexer 4-B. The high-order address in the scan address register 2 is applied to the multiplexer 4-B and, in accordance with the high-order address, the multiplexer 4-B selects and outputs one of the input data. The output of the multiplexer 4-B is provided, for instance, to a service processor. To output the status of a desired flip-flop or gate in an apparatus to the outside is called "scan-out".
Since a part formed by a memory element, such as a register file, calls for a memory readout operation, it cannot perform a scan-out operation given the circuit arrangement as illustrated. But a memory can be scanned out through utilization of an arrangement as shown in FIG. 2. In FIG. 2, reference numeral 5 indicates a register file (a memory); 6 designates a read address register; 7 identifies a write address register; 8 denotes a readout register; and 9 and 10 represent multiplexers. In FIG. 2 the multiplexer 9 is provided in a memory address input part. An address from a logical circuit for inputting and outputting data to the register file 5, and a scan address x (corresponding to the afoementioned low-order address) from a service processor or the like, is input to the multiplexer 9. When a scan enable signal is OFF, the multiplexer 9 is used as a readout address. Usually, while the system is in operation, the memory address is supplied from the logical circuit for inputting and outputting data to the register file 5, but, while the system is out of operation, the scan address is provided from the service processor or the like and the content of an address location identified by the scan address is output as read-out data. At this time, since the system is not in operation, data read out from the memory 5 is not input to the readout register 8. What is meant by "when the system is not in operation" is the period in which the system is in a stop-check state and a clock is stopped or a manual clock state and no clock is supplied. During scan-out, the data read out from the memory 5 is input to the multiplexer 10. Read-out data from other circuit blocks are input to the multiplexer 10, though not shown, and the multiplexer 10uses the scan address y input thereto as control information to select and output one of the input data.
FIG. 3 is a shift register formed by a register file. In FIG. 3, reference numeral 11 indicates a register file; 12 designates a counter; 13 identifies a subtractor; 14 and 15 denote multiplexers; 16 represents a preceding-stage register; and 17 is a following-stage register. The register file in one that is capable of concurrent execution of both write and read operations during the same cycle. The counter 12 designates a write address for the register file 11 and the subtractor 13 subtracts an arbitrary number k from the value of the counter 12 to produce a read address. Since the shift register permits the construction of a shift register having a desired number of stages with the same circuit arrangement, it is often employed as a control shift register for a pipeline or the like.
Now, a description will be given of forming five stages of shift registers by the register file 11 having eight registers as shown in FIG. 3. When the value of the counter 12 is "5", the write address of the register file 11 indicates the register having an address 5, but the read address indicates the register having an address 0 because of the subtractor 13. By the shift operation, the content of the register of the address 0 is read out at the same time as data is written into the shift register having the address 5 and, thereafter, the value of the counter 12 is incremented by one and the write address indicates a register having an address 6 and the read address indicates a register having an address 1. When the shift operation has been carried out five times by sequentially repeating the above-mentioned operations, the read address indicates a fifth address and the content of the register having the address 5 is read out after the shift operation has been effected five times. The values of the other registers are respectively read out after the shift operation takes place five times. In this way, there are shift registers having stages equal in number to the constant provided to the input of the subtractor.
For scanning out the content of the register file 11, the multiplexer 14 is provided in the read address input part of the register file 11, as in FIG. 2, by which the output of the subtractor 13 is normally selected as the read address and the scan address x is selected as the read address during the scan-out. The multiplexer 15 is controlled by the high-order address y.
A scan-out method as described above with respect to FIG. 2 is very convenient when the memory read addresses and the scan addresses have a one-to-one correspondence but, with regard to a shift register formed by the register file as shown in FIG. 3, the following point should be taken into account. FIG. 4 explains the scan-out of an ordinary shift register. Reference numerals 18-0 to 18-5 indicate flip-flops; and 19 designates a multiplexer. In the case where the shift register is formed by serial connection of the flip-flops 18-0 to 18-5 as shown in FIG. 4, scanning of (j-5)th to jth stages of the shift register can be performed using scan addresses applies to the flip-flops 18-0 to 18-5. For example, when the (j-5)th stage of the shift register is to be scanned, the flip-flop 18-0 is scanned and when the jth stage of the shift register is to be scanned, the flip-flop 18-5 is scanned. When the shift register comprises the register file as shown in FIG. 3, however, the positions of the stages of the shift register do not have a one-to-one correspondence with the numbers of the registers in the register file but bear a relative correspondence to the value of the counter. For instance when data is written into the fifth register and data is read out from the 0th register, the jth stage of the shift register is the 0th register and the (j-5)th stage corresponds to the fifth register. When the next shift operation takes place, the fifth register becomes the (j-4)th stage; namely, the correspondence differs from that in the immediately preceding cycle. In this way, the correspondence between the stages of the shift register and the numbers of the registers always differ, so that when a desired number of stages of the shift register is to be scanned, it is customary in the prior art to determine the numbers of the registers, noting the value of the counter which determines the write address of the register file. Such a system is inconvenient because the scan address becomes floating since the correspondence between the stages of the shift register and the numbers of the registers differ.
USPTO Backgrounds
USPTO Backgrounds