The present invention is directed to serial communication systems, and is more particularly directed to serial link circuits designed to be replicated and integrated with one another on a silicon chip to enable a large number of independent input/output operations to be conducted simultaneously.
Prior art serial links such as CMOS serial links intended to operate at multi-gigabit signaling rates over several meters of cable have been developed; however, such links typically require large amounts of power and chip area. This makes them unsuitable for applications such as high bandwidth switch fabrics, multicomputer routers and telecommunication crossbar chips which require hundreds of simultaneous, independent input/output operations per chip. For example, the best known power and size figures for serial links operating above 4 Gb/s are 310 mW and 0.6. mm2. The integration of 100 such serial links on a chip would create a device which consumes more than 30 Watts and occupies 60 mm2 of chip area.
For these reasons, there is a need in the art for a serial link circuit design which occupies only a small amount of area on a semiconductor chip.
There is an additional need for a serial link circuit design which consumes a minimum amount of power.
There is a further need for a chip exhibiting these properties which is relatively insensitive to power supply jitter and the like.
There is also a need for a chip exhibiting these properties which is more sensitive than chips employing receivers without offset cancellation.
There is an additional need for a chip exhibiting these properties which has better cancellation characteristics than circuits employing receivers with current trimming.
Various embodiments are disclosed which address one or more of the above advantages. One example embodiment of the present invention is directed to providing a serial link circuit that includes a transmitter which multiplexes the circuit""s input signals together and uses a single processing circuit to generate a multiplexed output to be transmitted. This is in contrast to prior art designs which duplicatively process a number of separate input signals and then multiplex the processed signals together at their output.
The objects are further achieved by providing a serial link circuit in which the transmitter multiplexes its input signals with a limited voltage swing prior to preamplification. In this way, clock loading (and hence clock buffer area), power and jitter are significantly reduced compared to prior art circuits which preamplify unmultiplexed input signals.
These objects are additionally achieved by implementing a serial link receiver using very small elements, thereby leading to a high input offset voltage which is then cancelled using capacitive trimming.
USPTO Backgrounds
USPTO Backgrounds