The construction of field effect devices in CMOS technologies involves the use of sequential implant processes to form conductive and semiconductive regions within the outer surface of a semiconductor substrate. These implant processes are optimized to enable the field effect devices to function in complimentary fashion. P-channel devices and n-channel devices are formed on the same substrate using photolithographic processes to cover certain of the devices while implant processes are performed on the remaining devices.
State of the art bipolar transistors require different implant and photolithographic masking processes. Many integrated architectures require or may be optimized if the integrated system can utilize both field effect and bipolar devices on the same integrated substrate. Unfortunately, the use of implant processes to form field effect devices and then subsequent implant processes to form bipolar devices greatly increases the cost and complexity of the formation of the device. As such, designers have attempted to use the same implant processes for the field effect devices to create various bipolar structures within the integrated system. These techniques have been somewhat successful but they have been limited principally because bipolar devices require two junctions. In this regard, many of the bipolar devices that have been integrated with field effect devices have used the substrate itself as one of the active regions of the bipolar device. While this technique can create a functioning bipolar transistor, this technique is limited because the substrate voltage is automatically applied to one terminal of the bipolar device. This greatly limits the operational parameters of such a bipolar device and can reduce the effectiveness of the device in the integrated architecture.
USPTO Backgrounds
USPTO Backgrounds