The present invention relates to a memory cell circuit and method for making it, and more particularly, to such a cell that is radiation hard.
It is known from U.S. Pat. No. 4,760,557, to have a memory cell comprising a pair of cross-coupled inverters, wherein one of the inverters has a much higher output impedance than the other inverter. The time constant of such a cell is relatively high so that the cell resists a change in its logic state during transient radiation. However, the high output impedance is achieved using a high length to width ratio for the transistors of one inverter. This results in a large cell area and a corresponding low memory array packing density.
It is, therefore, desirable to have a radiation hard memory cell that has a small area and a method for making same.
USPTO Backgrounds
USPTO Backgrounds