1. Field of the Invention
Embodiments of the invention relate to a semiconductor memory device and a test apparatus for testing the semiconductor memory device. More particularly, embodiments of the invention relate to a method and system for generating a high-frequency test pattern from a low-frequency test pattern output to perform high-speed test operations.
2. Discussion of Related Art
Semiconductor memory devices are tested using an external test apparatus. To test the memory cells of a semiconductor memory device, a method of recording a test pattern is recorded in a memory cell; the test pattern is read from the memory cell and compared. When the read test pattern is identical to the recorded test pattern, the semiconductor memory device is defect free. When the read test pattern is not identical to the recorded test pattern, the semiconductor memory device has a defect. Automatic test equipment (ATE) is generally used as the test apparatus.
However, operating frequencies of semiconductor memory devices are increasing and sometimes exceed the test pattern frequency generated by a test apparatus, thereby making the test apparatus ineffective. An additional drawback occurs when the maximum frequency that can be measured by a test apparatus is 200 MHz and the operating frequency of a semiconductor memory device that will be tested is 800 MHz rendering it impossible to correctly test whether the semiconductor memory device is defective. This problem is magnified in DDR (Double Data Rate), QDR (Quadrature Data Rate) and ODR (Octagon Data Rate) memory devices that transmit a larger quantity of data using a clock signal having the same frequency as that of the clock signal of conventional memory devices. Accordingly, there is a need for a test apparatus to accommodate memory devices operating at high frequencies.
USPTO Backgrounds
USPTO Backgrounds