The present invention relates to fin-based semiconductor devices, and more specifically, to decoupling extension resistance and parasitic capacitance.
Fin-based semiconductor devices require raised source/drain structures that are fabricated using an epitaxial silicon layer (epi/raised S/D). The epi/raised S/D has a drawback of increased parasitic capacitance between the epitaxial layer and the gate. Also, in some fin-based devices, the extension resistance becomes the dominant component of total resistance. This extension resistance can be lowered by thickening the epitaxial layer. However, a thicker epitaxial layer has a consequence of a larger capacitor area (increased capacitance).
USPTO Backgrounds
USPTO Backgrounds