1. Field of the Invention
This invention relates to nonsaturating, bipolar digital electrical logic circuits, and particularly to such circuits having a separate Schottky diode as part of the input circuit for each of several variables.
2. Prior Art
Two forms of nonsaturating digital logic in common use are current mode logic (CML, see FIG. 1) and emitter-coupled logic (ECL, see FIG. 2). Both forms of logic employ current steering approaches. FIG. 1 shows the basic CML circuit 10 including two input transistors 12 and 14 each having their emitter coupled to the emitter of transistor 16. As is well known, when the voltage to input A or B slightly exceeds the reference voltage V.sub.r input to the base of transistor 16, the current I.sub.H switches or is steered from a path through transistor 16 to a path through any input transistor (such as transistors 12 or 14) having an input voltage exceeding V.sub.r. The CML circuit provides two outputs 18 and 20 with the output at 18 representing the OR logic function and outputs at 20 the complement thereof (i.e., the NOR function).
The basic ECL circuit 22 of FIG. 2 operates in essentially the same manner as the CML circuit 10 except two emitter follower transistors 24 and 26 are now provided to shift the output voltage levels of outputs 18 and 20 to facilitate logic compatibility, to provide further current gain and serve as buffers for the output signals.
FIG. 3 and circuit 28 therein illustrates a variation of ECL called feedback emitter coupled logic (FECL). FECL provides the same basic structure as CML circuit 10 except a feedback path 30 is provided from transistor 32 to transistors 34 and 36, so that the voltage gain in the transient region of the transfer function is increased by positive feedback. Emitter resistors 38 and 40, when chosen properly, reduce a strong hysteresis in the transfer function which become troublesome when circuit 28 is employed with relatively large voltage swings. Qualitatively, emitter resistors 38 and 40 reduce the loop gain thereby substantially controlling the hysteresis. The basic FECL circuit and its improved form with emitter resistors is discussed in "Improved Feedback ECL Gate with Low Delay-Power Product for the Subnanosecond Region", H. M. Reinn and R. Ranfft, IEEE Journal of Solid State Circuits, February 1977, pages 80-82.
Problems remain with all the above prior art digital logic circuits. CML and ECL include extra voltage references (i.e., V.sub.r and -V.sub.r in FIGS. 1 and 2). This reduces packing density and provides parasitic coupling between gates via a common reference source. Further, reference voltages reduce noise margins due to reference voltage tolerances. Also, CML suffers from the lack of emitter followers to help drive long metal lines (i.e., quickly charge the relatively large capacitances associated with long lines) which may be connected to the outputs, and the lack of emitter followers reduces the current gain by not providing an additional amplification stage. A major concern with CML and ECL is response delays caused by the Miller capacitance of the input transistors in common emitter configuration.
FECL eliminates the extra voltage reference (or voltage regulator) but lacks emitter followers, and the logic inputs are still provided through transistors in common emitter configuration.
USPTO Backgrounds
USPTO Backgrounds