The present invention relates to a signal processing apparatus having one or plural memories built in an LSI.
In a conventional signal processing apparatus, one way to utilize the bus information such as data and address appearing in the bus of the apparatus in system operation as fault analysis data in the event of fault taking place in the system of the apparatus is that the apparatus stores the bus information in an analyzing device such as logic analyzer. Other way is that the apparatus adds a tracing mechanism to the system, as disclosed in the Japanese Laid-open Patent No. 6-187256.
However, the recent advancement in the semiconductor technology is promoting development of LSI integrating various function blocks and memories on one chip by large scale, and therefore the conventional constitution of signal processing apparatus as mentioned above has the following problems.
Firstly, since memory interface signal is not issued outside of the LSI, the analyzer cannot be connected to the apparatus, and in the event of fault, the system cannot obtain necessary information for fault analysis. Secondly, to form the tracing mechanism inside the LSI, it gives rise to increase in the area of LSI and the cost because of requiring an exclusive control circuit for fault analysis and an exclusive trace memory.
To solve the above problems, the signal processing apparatus of the invention comprises plural memories provided in the LSI, plural memory access blocks for accessing the plural memories, plural arbitration blocks for arbitrating the access right of the memories, and one or plural trace control blocks for issuing a memory request signal for storing the access history of the memories. The arbitration block of this signal processing apparatus arbitrates the access right of each memory when the memory access request signals issued from the plural memory access blocks are entered in the arbitration blocks. The memory access request signal defined herein is the memory access request signal including attribute information to each memory, and the apparatus of the invention also can be achieved by comprising plural arbitration blocks. The trace control block issues a memory request signal for storing the access history of the memory on the basis of the result of arbitration by the arbitration block in other memory than the memory executing the requested access according to the memory access request signals issued from the plural memory access blocks. The signal processing apparatus can obtain easily necessary information for fault analysis, in the event of fault, without requiring any particular additional means such as exclusive control circuit for fault analysis or exclusive trace memory.
Thus, the signal processing apparatus of the invention does not require any exclusive trace memory for access history data in the system, and realizes to obtain information only by addition of a small control circuit such as trace control block. Moreover, this signal processing apparatus can obtain necessary information for fault analysis in the event of fault under the same condition as when trace processing is not executed, without increasing the load of the memory bus.
The signal processing apparatus stores the access history of the memory in other memory than the memory executing the requested access issued from the memory access block. In the event of fault, the signal processing apparatus reads out the access history from the other memory, so that the person in charge can analyze the cause of the fault easily.
USPTO Backgrounds
USPTO Backgrounds