1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device having circuits formed by thin film transistors (hereafter abbreviated as TFTs) and by MOS transistors. As examples of semiconductor devices, there are electro-optical devices structured by TFTs, such as liquid crystal displays and EL (electroluminescence) displays, and LSIs structured by MOS transistors.
2. Description of the Related Art
Techniques of utilizing TFTs for active matrix liquid crystal displays have been in the spotlight in recent years. Active matrix displays are advantageous compared to passive matrix displays in response time, in angle of view, and in contrast, and therefore active matrix displays are in the mainstream at present in devices such as notebook computers and liquid crystal televisions.
In general, amorphous silicon or polycrystalline silicon is made into a channel layer (channel forming region) in a TFT. In particular, a polysilicon TFT manufactured by using only low temperature processes (generally equal to or less than 60° C.) can be made low cost, can have a large surface area, and at the same time can have electric field mobility with a large electron or hole. Consequently, not only pixel transistors, but also integration of driver circuits in the periphery of the pixel transistors can be achieved when polysilicon TFTs are used in liquid crystal displays. Manufacturers of liquid crystal displays have been making advances in the development of such uses.
However, when polycrystalline silicon TFTs are used, phenomena such as a reduction in the mobility and on current (the electric current flowing when a TFT is in an on state), and an increase in the off current (the electric current flowing when the TFT is in an off state) are observed as deterioration of reliability, and there are times when these phenomena become large problems with respect to reliability. These phenomena are referred to as hot carrier phenomena, and are known to be the work of hot carriers generated by a high electric field in the vicinity of a drain.
The hot carrier phenomena are phenomena which were first discovered in MOS transistors. Various types of basic examinations have been performed as ways of overcoming hot carriers, and with MOS transistors having a design rule equal to or less than 1.5 μm, an LDD (lightly doped drain) structure is employed as a measure against the hot carrier phenomena due to a high electric field in the vicinity of the drain. With an LDD structure, low concentration impurity regions (n−regions or p−regions) are formed in edge portions of a drain region by utilizing the sidewalls of gate sidewalls, and the electric field concentration in the vicinity of the drain is relaxed in a contact portion between the channel forming region and the drain region by making the contact portion possess a is sloped impurity concentration.
However, the voltage resistance of the drain increases greatly for the LDD structure case compared with a single drain structure, and the resistance of the low concentration impurity regions (n−regions or p−regions) large, and thus a disadvantage of a reduction in the drain current exists. Further, a high electric field region exists directly beneath the sidewalls, the impact ionization becomes large there, and hot electrons are injected into the sidewalls. The low concentration impurity regions (n−regions or p−regions) are depleted, and a degradation mode in which there is an additional increase in resistance, peculiar to the LDD, becomes a problem. The above problem becomes more tangible as the channel length decreases, and GOLD (gate-drain overlapped LDD) structure in which a low concentration impurity region (n−region) is formed overlapping with edge portions of the gate electrode has been proposed to be employed with MOS transistors having a channel length equal to or less than 0.5 μm in order to overcome this problem.
The employment of LDD structures and GOLD structures have also been considered in polycrystalline silicon TFTs as well, with an aim similar to that in MOS transistors, relieving the high electric field in the vicinity of the drain. With the LDD structure, a low concentration impurity region (n−region or p−region) is formed in a polycrystalline silicon layer corresponding to a region on the outside of a gate electrode, and a high concentration impurity regions (n+region or p+region) which becomes a source region and a drain region are formed on the outside of the low concentration impurity region. This is highly effective in suppressing the value of the off current, but there is only a small effect against hot carriers due to the reduction in the electric field near the drain. On the other hand, a low concentration impurity region (n−region or p−region) of the LDD structure is formed overlapping with edge portions of the gate electrode with the GOLD structure, and although it is a larger effect against hot carriers compared to the LDD structure, it also has a disadvantage in that the value of the off current becomes large.
The formation of high concentration impurity regions (n+region or p+region) which become source regions and drain regions of LDD structures and GOLD structures in a polycrystalline silicon TFT and in a MOS transistor, and the formation of low concentration impurity regions (n−region or p−region) on the inside of the high impurity concentration regions, have conventionally been performed in a self aligning manner with the gate electrode as a mask, and these have the advantage of being able to prevent an increase in the number of photolithography process steps. If the gate electrode is formed as a two layer structure, then it can be manufactured more easily than with a single layer structure, and the two layer structure is often used. However, there is a problem in that the film formation processes and the etching processes become complex if a two layer gate electrode structure is used.
Further, there are various circuits inside semiconductor devices, and there are times when a GOLD structure, superior for its hot carrier handling effect, is appropriate, while there are times when a low off current value LDD structure is suitable. There are also cases in which a single drain structure is appropriate. The formation of LDD structures and GOLD structures is performed by using processes such as dry etching only, and all of the transistors in the semiconductor device have the same structure; therefore there is a problem in that single drain structures, LDD structures and GOLD structures cannot be formed separately for each circuit.
In addition, the length of the low concentration impurity region (n−region or p−region) in a GOLD structure is basically determined by a region in which only the first layer of the gate electrode film, formed by an etching technique such as side etching, exists. Problems such as a restriction developing in the length of the low concentration impurity region (n−region or p−region), and an inability to sufficiently secure the length, therefore develop.
USPTO Backgrounds
USPTO Backgrounds