This invention relates to semiconductor devices and, more particularly, to a method of fabricating very-large-scale-integrated (VLSI) devices of the complementary metal-oxide-semiconductor (CMOS) type.
It is known to utilize a refractory metal silicide on polysilicon to achieve a high-conductivity gate-level metallization for MOS devices. Specific examples of such silicide-on-polysilicon composite structures suitable for MOS devices are described in U.S. Pat. No. 4,276,557 of H. J. Levinstein, S. P. Murarka and A. K. Sinha, issued June 30, 1981. Additional details concerning the use of silicide-on-polysilicon composites in such devices are contained in an article by S. P. Murarka, D. B. Fraser, A. K. Sinha and H. J. Levinstein entitled, "Refractory Silicides of Titanium and Tantalum for Low-Resistivity Gates and Interconnects," IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 4, Aug. 1980, pp. 474-482.
Increasingly, for many circuit applications of practical importance which require reduced power dissipation, devices of the CMOS type are being regarded as the preferred way to implement VLSI devices. Specific examples of CMOS devices suitable for such implementation are described in, for example, articles by R. Jerdonek, M. Ghezzo, J. Weaver and S. Combs, entitled "Reduced Geometry CMOS Technology," in the International Electron Devices Meeting Digest, page 451 (1982); and by L. C. Parrillo, L. K. Wang, R. D. Swenumson, R. L. Field, R. C. Melin and R. A. Levy, entitled "Twin Tub CMOS II--An Advanced VLSI Technology," in International Electron Devices Meeting Digest, page 706 (1982).
To achieve optimal performance of a CMOS circuit, it is known that the threshold voltages of the constituent p- and n-channel transistors of the device should be the respective complements of each other. In a polysilicon-gate VLSI CMOS device, complementary threshold voltages (V.sub.TP, V.sub.TN) are typically achieved by utilizing a so-called double-doped-polysilicon process in which the polysilicon gate work function is adjusted by utilizing appropriately doped p.sup.+ and n.sup.+ polysilicon.
In the course of trying to improve the performance of VLSI CMOS devices made by the double-doped-polysilicon process, it was natural to attempt to incorporate in the devices the speed advantages inherent in utilizing silicide-on-polysilicon composites as the gate-level metallization. Such attempts, however, revealed that the resulting devices, when the constituent transistors thereof were interconnected in a common circuit configuration, exhibited a serious problem, namely, an anomalously large negative V.sub.TP.
Accordingly, workers in the art have expended efforts directed at trying to understand and solve the aforespecified problem. It was recognized that, unless solved, the problem posed a serious threat to the successful development of high-performance VLSI CMOS devices.
USPTO Backgrounds
USPTO Backgrounds