1. Field of the Invention
The present invention relates to a method of fabricating semiconductor device provided with a plurality of unit cells each of which includes an impurity doped region.
2. Description of the related art
JP-A-2001-267528 discloses a method of manufacturing a semiconductor memory provided with trench capacitor DRAM cells, for example. In the disclosed method, a trench is filled with a polycrystalline silicon film doped with As (impurity). Thereafter, As is diffused from the polycrystalline silicon film filling the trench into the semiconductor substrate by heat treatment in the forming of a silicon oxide film to fill shallow trench isolation (STI), whereby a buried contact (strap) is formed. This can suppress an increase in resistance in a boundary between the polycrystalline silicon film and the substrate and accordingly an electrical resistance value between the polycrystalline silicon film and the substrate. Consequently, a capacitor charge/discharge speed can be prevented from being reduced, and the resultant data write/read failure can be prevented.
However, a cutoff characteristic of the cell transistor is deteriorated when the impurity is diffused thereby to reach a substrate region under a cell transistor. Accordingly, a strict adjustment is required for diffusion in the periphery of boundary from both sides of the boundary resistance and cutoff characteristic.
High integration and refinement have recently been more remarkable as compared with the prior art and accordingly, it has been desired to further densify the unit cell. As a result, the following drawback would be caused. When the unit cells are arranged in a high-density order, even an active area of a unit cell proximal to each unit cell would adversely be affected in a fabrication process of each unit cell.
In the aforesaid DRAM semiconductor storage, a distance between an active area and trench of memory cells adjacent to each other is reduced with high integration and refinement. Accordingly, when a DRAM semiconductor storage is manufactured by the aforementioned method disclosed by the foregoing Japanese patent application publication gazette, impurity diffused into an outer periphery of the trench for suppression of electrical resistance reaches an active area of an adjacent memory cell, whereupon the adjacent memory cell is adversely affected.
In particular, a region into which impurity is diffused in order to suppress electrical resistance is sometimes an active area located under a gate electrode of the adjacent cell transistor. Furthermore, part of the impurity located under the gate electrode is passivated when impurity to be diffused is of reverse conduction type relative to a channel region of the active area. As a result, the cutoff characteristic of the adjacent cell transistor is deteriorated and/or resistance to punch-through is deteriorated.
USPTO Backgrounds
USPTO Backgrounds