Although the invention in principle can be applied to any semiconductor device, the invention and its underlying problem hereinafter will be explained with regard to double sided capacitors used in memory devices.
A typical memory device comprises a plurality of memory cells which each consists of a single transistor and a storage capacitor. Information is stored as electric charges within the storage capacitor and may be accessed through the transistor. The transistor itself is addressable via bit lines and word lines. In order to increase the number of memory cells on a reasonable chip area lateral dimensions of the transistor and the storage capacitor has to be reduced.
The storage capacitor must be able to store a minimal amount of charge for a reliable operation of the memory cell. The charge which may be stored in a capacitor essentially depends on the size of the capacitor electrodes. Therefore, sufficiently large capacitor plates must be provided despite a reduction of the lateral structure sizes of the memory cells.
U.S. Pat. No. 6,507,064 B1 discloses a double sided capacitor having a cup shaped first electrode which inner and outer surfaces are covered by a dielectric layer on which a second electrode is deposited. Thus the size of the capacitor plate is defined by the inner and outer surfaces of the first electrode.
The method of manufacturing these double sided capacitors includes steps wherein the first electrode stands freely without mechanical support during at least one manufacturing step. A common problem is that tips of these free standing first electrodes can come into close contact and then stick together permanently. Therefore, additional structures must be provided between neighbouring first electrodes in order to avoid such contacts during a manufacturing process. The formation of these additional structures increases the complexity of the manufacturing process of the capacitor. Further, the additional structures are covering at least a part of the outer surfaces of the first electrode thus reducing the surface of the capacitor plates.
USPTO Backgrounds
USPTO Backgrounds