1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device in which a gate electrode is located so as to surround the entire circumference of a channel region, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, with the improved functions and integration of semiconductor integrated circuits, MOS transistors have been increasingly miniaturized. However, conventional MOS transistors have a small current on/off ratio. Thus, in order to provide a desired on current, the MOS transistor needs to be configured such that a gate electrode has an increased width or a plurality of gate electrodes are formed on the same plane. The increase in width and the formation of a plurality of gate electrodes on the same plane increase the area occupied by field effect transistors, disadvantageously hindering an increase in circuit density.
Thus, as a structure for obtaining the desired on current, for example, a gate-all-around (GAA) transistor has been proposed (see, for example, Jpn. Pat. Appln. KOKAI Application No. 2005-229107).
In the GAA transistor, the gate electrode is formed so as to wrap around a channel region. Thus, when a voltage is applied to the gate electrode, electric fields are likely to concentrate in the channel region. Thus, the on/off ratio of a switching current can be set to a large value. Furthermore, a large number of channels can be formed on the same plane, enabling an increase in on current.
However, in the conventional GAA transistor, a parasitic capacitance is produced on the side surfaces (the end surfaces of the gate in the longitudinal direction) and bottom surface of the gate electrode. In particular, a large parasitic capacitance is produced on the side surfaces of the gate electrode. In operation, this disadvantageously slows the speed at which the voltage of the gate electrode is increased or reduced in response to an applied voltage.
USPTO Backgrounds
USPTO Backgrounds