This invention relates to a synchronization tracking circuit for causing the phase of a despreading code sequence on a receiving side to follow up the phase of a spreading code sequence on a transmitting side. More particularly, the invention relates to a synchronization tracking circuit, which is used in the field of CDMA mobile communications employing spread spectrum, for exercising DLL (Delay Locked Loop) control in such a manner that a despreading code sequence on the receiving side will not shift in time with respect to a receive signal for which acquisition of synchronization has succeeded.
In a CDMA (Code Division Multiple Access) mobile communications system using spread spectrum, the transmitting side transmits information upon spreading the information using a spreading code sequence, and the receiving side demodulates the transmit information upon despreading the signal from the transmitting side using a despreading code sequence that is identical with the spreading code sequence.
FIG. 12 is a block diagram illustrating the construction of a CDMA receiver. The receiver includes a radio unit 1 that subjects a high-frequency signal received by an antenna ANT to a frequency conversion (RF→IF conversion) to obtain baseband signals. A quadrature detector 2 subjects the baseband signals to quadrature detection and outputs in-phase component (I component) data and quadrature component (Q component) data. The quadrature detector 2 includes a receive carrier generator 2a, a phase shifter 2b for shifting the phase of the receive carrier by π/2, and multipliers 2c, 2d for multiplying the baseband signals by the receive carrier and outputting the I-component and Q-component signals. Low-pass filters (LPF) 3a, 3b limit the bands of the output signals and A/D converters 4a, 4b convert the I- and Q-component signals, respectively, to digital signals. The digital signals are input to a searcher 5 and to each of fingers 61 to 64. 
If a direct sequence signal (DS signal) that has experienced multipath effects is input to the searcher 5, the latter executes autocorrelation processing using a matched filter (not shown), detects multipath and inputs, to the fingers 61 to 64, despreading-start timing data τ0 to τ3, respectively, and delay-time adjustment data for the respective paths. Each of the fingers 61 to 64 has a despreading code generator 6a for generating a code sequence identical with the spreading code sequence on the transmitting side based upon the timing data τ0 to τ3 that enters from the searcher 5. More specifically, the searcher 5 detects the phase of the transmitting-side spreading code (referred to as “synchronization capture”) at a precision of within one chip, and the despreading code generator 6a generates a despreading code sequence, which is for performing despreading on the receiving side, in sync with the detected phase. A DLL (Delay Locked Loop) circuit 6b exercises control (referred to as “synchronization tracking”) in such a manner that the despreading code sequence on the receiving side will not develop a time shift with respect to a receive signal for which synchronization has been captured even if the receive signal undergoes a change in phase owing to the effects of modulation and noise, etc.
Each finger further includes a despreader/delay-time adjustment unit 6c for performing dump integration by subjecting a direct wave or a delayed wave that arrives via a prescribed path to despread processing using a code identical with the spreading code, and for subsequently applying delay processing that conforms to the path and outputting a pilot signal (reference signal) and information signal; a phase compensator (channel estimation unit) 6d for averaging voltages of the I and Q components of the pilot signal over a prescribed number of slots and outputting channel estimation signals It, Qt; and a synchronous detector 6e for restoring the phases of despread information signals I′, Q′ to the original phases based upon a phase difference θ between a pilot signal contained in a receive signal and an already existing pilot signal. More specifically, the channel estimation signals It, Qt are cosine and sine components of the phase difference θ, and therefore the synchronous detector 6e demodulates the receive information signal (I,Q) (performs synchronous detection) by applying phase rotation processing to the receive information signal (I′,Q′) in accordance with the following equation using the channel estimation signal (It,Qt):
      (                            I                                      Q                      )    =            (                                    It                                Qt                                                              -              Qt                                            It                              )        ⁢          (                                                  I              ′                                                                          Q              ′                                          )      A rake combiner 7 combines signals output from the fingers 61 to 64 and outputs the combined signals to an error correction decoder 8 as a soft-decision data sequence. The error correction decoder 8 applies error correction processing, demodulates the transmit information and outputs the demodulated signal.
DLL Circuit
As mentioned above, a CDMA receiver has a searcher for detecting the phase of the transmitting-side spreading code (referred to as “synchronization capture”) at a precision of within one chip, after which a despreading code sequence, which is for performing despreading on the receiving side, is generated in sync with the detected phase. The DLL carries out control (synchronization tracking) in such a manner that the despreading code sequence on the receiving side will not develop a time shift with respect to a receive signal for which synchronization has been captured even if the receive signal undergoes a change in phase owing to the effects of modulation and noise, etc.
FIG. 13 is a diagram illustrating the construction of a DLL circuit 6b to which a despreading code generator 6a is connected. The despreading code generator 6a includes a PN generator 6a-1 for generating a despreading code sequence (first PN sequence) A1, which is an M sequence. The first PN sequence A1 is composed of N chips and is generated cyclically at the symbol period T (=N×TC, where TC represents the chip cycle). The PN generator 6a-1 further includes a voltage-controlled oscillator (VCO) 6a-2 that is capable of varying the clock frequency (chip frequency) based upon the output of the DLL circuit 6b. The latter includes a delay circuit 6b-1 for delaying the first PN sequence A1 by one chip cycle and outputting a second PN sequence A2; a despreader (multiplier) 6b-2 for multiplying, chip by chip, the first PN sequence A1 output by the PN generator 6a-1 and a receive spread-spectrum data sequence B to thereby effect despreading; a despreader (multiplier) 6b-3 for multiplying, chip by chip, the second PN sequence A2 delayed by one chip and the receive spread-spectrum data sequence B to thereby effect despreading; and adder 6b-4 for adding the output of the despreader 6b-2 and a signal obtained by inverting the code output by the despreader 6b-3; and an integrating circuit (low-pass filter) 6b-5.
The DLL circuit shown in FIG. 13 delays the despreading code sequence A1 to generate the despreading code sequence A2 the phase whereof differs by one chip, and uses the despreading code sequences A1, A2 to apply despread processing to the receive data sequence B. However, the DLL circuit can be constructed as shown in FIG. 14. Here the DLL circuit is constructed in such a manner that the receive data sequence B is delayed by a delay circuit 6b-1′ to generate receive data sequence B′ the phase whereof differs by one chip, and the despreading code sequence A is used to apply despread processing to the receive data sequence B, B′.
The despreader 6b-2 and low-pass filter 6b-5 in FIG. 13 function to calculate the correlation between the first PN sequence A1 and the receive data sequence B. If the phase of the first PN sequence A1 and the phase of the receive data sequence B match, the maximum output is obtained and, as shown in FIG. 15A, a correlation value R(τ)=1 having the width of one chip cycle is output every symbol. If the phase shifts by one chip cycle or more, the correlation value R(τ) becomes 1/N. The despreader 6b-3 and low-pass filter 6b-5 function to calculate the correlation between the second PN sequence A2 delayed by one chip cycle and the receive data sequence B. If the phase of the second PN sequence and the phase of the receive data sequence B match, the maximum output is obtained and a correlation value R(τ) shown in FIG. 15B is output. If the phase shifts by one chip cycle or more, the correlation value R(τ) becomes 1/N. The adder 6b-4 adds the output of the despreader 6b-2 and a signal obtained by inverting the code output by the despreader 6b-3. As a result, a signal having an S-curve characteristic shown in FIG. 15C with respect to a phase difference T is output via the low-pass filter 6b-5.
On the basis of the output of the low-pass filter, the voltage-controlled oscillator 6a-2 of the despreading code generator 6a controls the clock frequency in such a manner that the phase difference T becomes zero. For example, if the phase of the PN sequence (despreading code) leads that of the transmitting-side spreading code contained in the receive data sequence, control is performed so as to make the phase difference zero by lowering the clock frequency. If the phase of the PN sequence (despreading code) lags behind that of the transmitting-side spreading code, control is performed so as to make the phase difference zero by raising the clock frequency.
The DLL circuit 6b in this spread-spectrum system performs despreading at a timing equivalent to the phase difference τ of ±0.5 chip (=±Tc/2) with respect to the timing of the desired signal (the spreading code sequence on the transmitting side), obtains the power difference between the signals despread at the respective timings and decides phase advance/delay of the PN sequence (despreading code) based upon the sign (positive or negative) of the power difference, thereby performing path tracking. The timing equivalent to τ=−Tc/2 shall be referred to as “early timing” and the timing equivalent to τ=+Tc/2 shall be referred to as “late timing”.
In the DLL circuits described above, the receive data sequence is described separately for I and Q channels. In actuality, however, the receive data sequence is divided into the I and Q channels and then input to the DLL circuit. FIG. 16 illustrates an example of the construction of a DLL circuit that takes both the I and Q channels into consideration. Components in FIG. 16 identical with those shown in FIG. 12 are designated by like reference characters. The DLL circuit 6b includes delay circuits 6b-1i, 6b-1q for delaying receive data sequences BI, BQ of I and Q channels, respectively, by one chip cycle and outputting delayed receive data sequences BI′, BQ′; despreaders (multipliers) 6b-2i, 6b-2q for multiplying, chip by chip, I- and Q-channel despreading code sequences AI, AQ, which are output by the despreading code generator 6a, by the receive data sequences BI′, BQ′ to thereby effect despreading; and despreaders (multipliers) 6b-3i, 6b-3q for multiplying, chip by chip, the I- and Q-channel despreading code sequences AI, AQ by the delayed receive data sequences BI′, BQ′, which are output from the delay circuits, to thereby effect despreading.
A power calculation unit 6b-6 integrates the despread signals from the despreaders 6b-2i, 2b-2q over one symbol period, squares the outputs of the integrators and sums the squares to calculate the power value of the despread signals at the early timing. Similarly, a power calculation unit 6b-7 integrates the despread signals from the despreaders 6b-3i, 6b-3q over one symbol period, squares the outputs of the integrators and sums the squares to calculate the power value of the despread signals at the late timing.
An adder 6b-4 calculates the difference between the power value of the despread signals at the early timing and the power value of the despread signals at the late timing, and an advance/delay decision unit 6b-5 instructs the despreading code generator 6a to advance/delay the phase of the despreading code sequence based upon an output X from the adder 64-b. For example, let TH represent a threshold value. If the adder output X is positive and |X|>TH holds, the despreading code generator 6a is instructed to advance the phase of the despreading code sequence; if the adder output X is negative and |X|>TH holds, the despreading code generator 6a is instructed to delay the phase of the despreading code sequence.
FIG. 17 is a diagram expressing FIG. 16 in simplified form. In the description that follows, the DLL circuit will be expressed using this diagram. Furthermore, the despreader 6b-2 performs despreading at the early timing and the despreader 6b-3 performs despreading at the late timing.
An example of the DLL will be described for a case where an M sequence of one symbol period is used and the phase difference τ is ±0.5 chip. However, this is not the only arrangement that is possible.
In a multipath environment, one path interferes with another path if the delay between the paths (the delay time difference between the paths) is too small. As a consequence, the power of a signal despread at whichever of the early and late timings is nearer the timing of the other path becomes too large and results in a DLL control malfunction.
By way of example, if a path PT1 at timing 0 in (a) of FIG. 18 is not interfered with by another path, the despread signals at the early timing (=−Tc/2) and late timing (=+Tc/2) become as shown at (b) and (c) of FIG. 18, respectively, and the S curve becomes zero at time t =0 as indicated at (d) in FIG. 18. Accordingly, if DLL control is carried out so as to eliminate the difference between the despread signal at the early timing and the despread signal at the late timing, synchronization tracking can be achieved at a precision of within one chip. However, if the path PT1 at timing 0 is interfered with by another nearby path PT2, as shown in (a) of FIG. 19, the despread signals at the early timing (=−Tc/2) and late timing (=+Tc/2) become as shown at (b) and (c) of FIG. 19, respectively. The result is a distorted S curve, which becomes zero at time t=td and not at t=0, as indicated at (d) in FIG. 19. Consequently, if DLL control is performed so as to eliminate the difference between the despread signal at the early timing and the despread signal at the late timing, the despreading code sequence will be generated at a timing offset from the original timing by td. The result is a malfunction.
USPTO Backgrounds
USPTO Backgrounds