(1) Field of the Invention
The invention relates to the general field of electrical capacitors, more particularly to low voltage-coefficient capacitors in integrated circuits.
(2) Description of the Prior Art
As is well known, the capacitance of a parallel plate capacitor is normally a function only of the area of the electrodes, the dielectric constant of the dielectric and the thickness of the dielectric. This assumes that both electrodes are metallic conductors. If one of the electrodes is a semiconductor, a depletion region, extending into the semiconductor, is formed at the semiconductor-dielectric interface, even in the absence of any externally applied voltage bias, thereby rendering the capacitance of such a structure somewhat lower than if both electrodes had been metallic.
An important consequence of this phenomenon is that when voltage is applied across the above described device's plates, the depletion layer in the semiconductor grows or shrinks, depending on the polarity, thereby reducing or increasing the measured capacitance. In other words, such a device has a high voltage coefficient, in some cases as high as 120 ppm/volt. In many integrated circuits this is not a problem but in many analog circuits (such as analog to digital converters, for example) this cannot be tolerated.
During the manufacture of integrated circuits where capacitors must be included it is obviously an advantage if such capacitors do not take up real estate needed for other devices, notably transistors. Fortunately, the areas of field oxide that are used to electrically isolate active devices from one another, are available for this. It is also particularly advantageous if the capacitors can be formed without introducing any additional steps into an existing process, other than the modification of the etch masks. With this in mind, it has been common practice to form capacitors in integrated circuits by sandwiching a layer of the silicon oxide known as IPO (or inter-poly oxide) between two layers of polysilicon.
In earlier processes such as the standard 0.5 micron mixed-mode process, the two polysilicon layers used for the capacitors were sufficiently heavily doped so that they were electrically degenerate (that is, they exhibited metallic conductivity) and any depletion layer formed at the silicon-dielectric interface would be negligibly thin. More recently, with the development of the 0.35 micron process, changes in processing parameters make the polysilicon layers less heavily doped. This is unimportant for the first layer of polysilicon (polyl) because a layer of tungsten silicide, which is a metallic conductor, is formed on polyl so it has a depletion free interface with the IPO.
There is no corresponding layer of tungsten silicide between poly2 and the IPO, so a depletion layer forms within the poly2 and the resulting capacitor has a high voltage coefficient. Referring now to FIG. 1, we show a schematic cross-section of such a capacitor. Bottom electrode 3, comprising poly1, has been formed on an area 2 of field oxide on silicon substrate 1. Dielectric layer 4, comprising IPO, lies on top of 3 and layer 5, comprising poly2, forms the top electrode.
FIG. 2 shows a schematic plot of the normalized capacitance value of the device of FIG. 1 as a function of applied voltage V. Typically, V covers the range of from -5 to +5 volts, with V applied to the poly2 layer and the poly1 layer being grounded. The voltage coefficient of capacitance, as defined by the slope of curve 21 is generally about -120 ppm/volt.
A number of prior art references describe capacitors for incorporation within integrated circuits but most do not address the voltage coefficient issue. Boerstler et al. (U.S. Pat. No. 5,389,832 February 1995) describe capacitors formed from forward biassed diodes. Sundaresan (U.S. Pat. No. 5,016,070 May 1991) describes a stacked CMOS SRAM with cross-coupled capacitors. Sato (U.S. Pat. No. 5,521,111 May 1996) teaches use of a trench-stacked capacitor.
Himes et al. (U.S. Pat. No. 4,731,696 March 1988) address the voltage coefficient issue and disclose a three plate capacitor structure wherein two layers of dielectric are sandwiched between three conductive plates, the center plate being the semiconductor. Voltage is applied between the center plate and the two outer plates (which are connected to each other). Since the upper and lower capacitors always see opposed electric vectors the voltage coefficients in the upper and lower dielectric layers will always carry opposite signs and will thus tend to cancel one another.
While this structure should exhibit low voltage coefficient, it requires three separate deposition steps for the electrodes and two separately deposited dielectric layers. The latter limitation can lead to serious problems in the absence of precise thickness and process control during deposition of the two dielectric layers. It also means that the standard manufacturing process will have to be modified if this structure is to be made part of an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds