This invention relates to a vertical cell configuration for dynamic RAM memories and to a device for coupling charges between vertically disposed potential wells.
In monolithic integrated circuits, it is often desirable to reduce the size of the individual devices in the circuits for greater economy, because the smaller the size of the circuit, the more economical is the manufacture of the circuit. In the last few years, there has been increased emphasis on new semiconductor devices which utilize vertical structures in order to increase the device density in the circuits. An example of such vertical structures are V-groove MOS transistors (VMOS) described in "VMOS Memory Technology" by T. J. Rodgers et al, ISSCC Digest of Technical Papers, February 1976, pp. 74-75, and static induction field effect transistors (SIT) described in "Static Induction Transistor Cell", Electronics, September 1977, pp. 64. However, the VMOS device requires complicated manufacturing techniques which include epitaxial layer growth and V-groove anisotropic etching and the SIT device also requires complex manufacturing techniques which include epitaxial layer growth and deep isolation diffusions which occupy relatively large chip area. These complexities increase the cost of these devices even though achieving a smaller size device.
In the dynamic random access semiconductor memory (RAM) field, the one-transistor memory cell disclosed in U.S. Pat. No. 3,387,386, which issued to R. H. Denard for "Field Effect Transistor Memory" on June 4, 1968, is widely used presently and can almost be regarded as the industry standard for 4K-bit and 16K-bit memories. This one-transistor memory cell has four physical elements, namely a storage capacitor, a select gate, a diffused bit line and an isolation element, all arranged side-by-side which results in a relatively large lateral cell area. To increase the capacity of such memories without substantially increasing the cost per bit of stored information, the size or area of the memory should remain substantially the same which requires a cell of smaller size.
There have been a number of attempts made to decrease the individual cell area by combining one or more of these four elements with varying degrees of success. In the charge coupled RAM cells described in "The Charge-Coupled RAM Cell Concept" by A. Tasch et al, IEEE Journal of Solid State Circuits, Vol. SC-11, No. 1, February 1976, pp. 58-63, one element of the storage capacitor is combined with the select gate into a single electrode to reduce the lateral extent of the cell. But this reduction is accomplished at the cost of considerable reduction of the individual cell charge storage capacity and a considerable increase in the alignment sensitivity if compared to the standard cell. In the merged charge memory cell (MCM) described in "Merged Charge Memory (MCM), A New Random Access Cell" by H. S. Lee and W. D. Pricer, Digest of Technical Papers, IEDM, December 1976, pp. 15-20, the storage capacitor is combined with the bit line, thus reducing the lateral extent of the cell. However, this cell suffers from inflexible capacitance division ratio between the bit line and the storage capacitor, from signal pattern sensitivity, and limited speed of operation.
In the SIT memory cell, the storage capacitor is combined with the bit line and the select gate is a vertical field effect transistor. This results also in inflexible capacitance division ratio between the bit line and the storage capacitor and signal pattern sensitivity. Also the use of p+ isolation diffusion as select gate results in a relatively large cell area. In the three-dimensional dual dielectric insulator memory cell described by P. C. Arnett in "Three-Dimensional Dual Insulator Memory", IBM Technical Disclosure Bulletin, Vol. 16, No. ll, April 1974, a stack of memory cells is formed, each cell including deposited word lines in one direction and deposited bit lines perpendicular thereto with a dual insulator separating the lines which is capable of storing charge at its interface. This arrangement results in most satisfactory device density but requires relatively large voltages to force current to flow through the dual insulator making the write operation rather slow.
USPTO Backgrounds
USPTO Backgrounds