The present disclosure relates to memory devices, and more particularly, to a semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit.
Semiconductor memory devices are being continuously developed to increase their degree of integration and operating speed. Synchronous memory devices have been developed to operate in synchronization with a clock signal applied from outside a memory chip of the synchronous memory devices so that the operating speed is enhanced.
In a synchronous memory device, when data is synchronized with an external clock signal and is output, a data valid window is reduced, thus causing errors when the synchronous memory device is operated at a high frequency. Thus, a DLL circuit is used to delay the external clock signal during a predetermined period to allow the data to be exactly synchronized with the rising edge and the falling edge of the clock signal and to be output. That is, the DLL circuit generates an internal clock signal for compensating delay components in a dynamic random access memory (DRAM), and this clock generating procedure is referred to as a ‘locking operation ’.
USPTO Backgrounds
USPTO Backgrounds