1. Field of the Invention
The present invention relates to electrically-erasable, electrically programmable read-only memories (EEPROMs) and Flash EEPROMS, and more particularly, but not by way of limitation, to an EEPROM and a Flash EEPROM that incorporate multiple erase modes to facilitate more efficient write operations.
2. Discussion of the Prior Art
EEPROMs and Flash EEPROMs commonly contain an array of rows and columns of semiconductor field effect transistors incorporating floating gate structures. Each intersection of a row and a column in the array is designated as a memory cell and can be programmed to indefinitely store a logic value ("0" or "1"). The memory cell is programmed by applying the proper voltages to the memory cell source, drain, control gate, and other signal lines, resulting in electrically charging the floating gate. Depending on the construction of the memory cells, the other signal lines may provide access to a memory cell erase gate, a well region, or substrate Once programmed, the memory cell charged floating gate inhibits current flow when the memory cell is activated as part of a read operation. This allows sensing and decoding circuitry to identify the logic state of the memory cell.
A memory cell is erased by applying the proper voltages to the source, drain, control gate, and other signal lines, resulting in depletion of the charge on the floating gate and a return of the memory cell to an unprogrammed state.
A conventional EEPROM generally allows simultaneous erase of one or multiple bytes of cells (8, 16, 32, etc.). A Flash EEPROM, which is a particular type of EEPROM, allows simultaneous erase of sectors of cells. A sector generally consists of one or more rows of the Flash EEPROM memory array. For the purpose of this patent, a "section" will be referred to as a set of memory cells grouped so as to be erased simultaneously, whether in a conventional EEPROM or a Flash EEPROM. For a conventional EEPROM, a section is a byte or multiple bytes of cells, depending on the configuration of the device. For a Flash EEPROM, a section is a sector, which could be a single row, multiple rows, or portions of a row, depending on the configuration of the Flash EEPROM. In addition, for the purposes of this patent, the term EEPROM will generally refer to both conventional, byte erasable EEPROMs and Flash EEPROMs.
It is generally desirable that an EEPROM memory cell be in an erased state prior to programming. Common EEPROM write operations, during which selected memory cells in the array are programmed, first erase the selected memory cells and then write data to the memory cells.
For a conventional EEPROM, the time required to erase memory cells is commonly about 5-10 ms and the time required to write data to memory cells is commonly about 5-10 ms. Thus, the time required to perform a conventional EEPROM write operation is commonly about 10-20 ms. For some classes of Flash EEPROMs that use hot electron programming, the time required to write data to a memory cell is commonly about 10-50 .mu.s, whereas, the time required to erase a memory cell is about 100-500 ms. For both conventional EEPROMs and Flash EEPROMs, erasure of unprogrammed memory cells prior to writing data to the cells is an unnecessary, time-consuming operation.
The time required to perform a write operation can be significantly reduced if the unprogrammed memory cells are not erased before writing. There is a need, therefore, for an EEPROM that can significantly reduce the time required to perform a write operation by identifying the programmed status of the memory cells in a selected section and inhibiting an unnecessary erase operation if the memory cells in the selected section have not been programmed since the last erasure of the memory cells in the section.
USPTO Backgrounds
USPTO Backgrounds