1. Field of the Invention
The invention relates to apparatus and method for burn-in testing of integrated circuits and semiconductors at the wafer level.
2. Description of the Related Art
Semiconductor manufacturers make integrated circuit chips in batch on what is typically referred to as wafers or semiconductor wafers. These wafers are generally flat circular disks, between 100 millimeters to 300 millimeters or greater in diameter and may contain one to upwards of several hundred integrated circuit chips. When manufacture of the wafer is completed, the individual chips or die are cut or xe2x80x9cdicedxe2x80x9d from the wafer and are later mounted into single chip or multiple chip packages for implementation in a printed circuit board or other application for electronic uses.
It is customary practice to test each chip, either individually or as part of a multiple chip package to determine if each chip as manufactured, electrically matches design criteria, matches performance criteria of a system in which the chip is to be implemented, and will be reliable in operation. If a chip fails reliability testing, the chip is not suitable for implementation in a system without repairing the chip or exercising redundancy features which may have been designed into the chip.
The integrated circuit chips are assembled into packages for protection and convenience in handling as well as for further assembly into equipment. These latter processing stages contribute a major portion of the manufacturing cost of the finished products utilizing semiconductor chip. If failure is detected after the chips are packaged, significant costs can be incurred due to failure of electronic systems into which the multiple chip packages are incorporated. Thus, before packaging, integrated circuit chips must be tested thoroughly.
Performance testing of chips is used to speed-sort chips into different categories suitable for different applications and sale at different prices. Reliability testing is used to screen out chips having an undesirably short life span. Typically, a significant percentage of a group of chips will fail early in their lifetime due to marginal conditions during manufacture. Subsequently, a very low percentage of the group will fail during an extended period of use of the chips. Reliability screening of a semiconductor chip is typically performed by a process of supplying test signal patterns to chips under test to repeatedly stimulate all devices and wires on a chip, and is typically performed at elevated temperatures to simulate the first six months of operation. This screening process is commonly referred to as burn-in or burn-in testing.
Burning in chips tends to induce accelerated failures. While very valuable, the process of burn-in has historically been time consuming and expensive for semiconductor manufacturers, particularly if testing is performed on individual chips or after chips are incorporated into a package. Existing bum-in is typically performed on integrated circuits at temperatures between 90xc2x0 C. to 125xc2x0 C., for anywhere between 24 to 168 hours. Obviously, this slow rate of reliability testing impedes volume production of functional semiconductors and adds tremendous cost. Generally, manufacturers have attempted to reduce these costs by burn-in testing of semiconductor wafers at the wafer level.
In wafer level burn-in, electrical terminals from a test apparatus or test board are brought into contact with contact pads of the individual chips on a semiconductor wafer to test the chips for electrical performance. The wafer is typically mounted in a wafer chuck, a holder for the wafer, having electrical probes or pins that align with contact pads of the integrated circuit chips on the wafer. Through the use of automatic computerized testing, power sources provide required test voltages and electronic signals for communication between the integrated circuit chips of the wafer and the computerized test equipment. The equipment automatically records the results for all of the integrated circuit chips on the wafer. The number, sequence, and types of test specified have been programmed into the equipment, and the test is carried out generally without operator assistance. The equipment records the characteristics of all integrated circuit chips tested, passes as well as failures, by wafer and production lot. Rejects are marked with a visible ink spot for identification, and some equipment also generates maps of the wafers to record the location of the rejects on the wafer. Depending upon their performance, the integrated circuit chips can be sorted for disposal, if rejected, or for specified uses and applications appropriate to the design and performance criteria they meet.
There are numerous wafer chucks of various configurations that are known for use in wafer level burn-in testing. For example, U.S. Pat. No. 6,910,254 to Wood et al. discloses a wafer chuck consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer and the second half establishes electrical communication between the wafer and the electrical test equipment. U.S. Pat. No. 5,929,651 to Leas et al. discloses an apparatus and method for simultaneously testing or burning in integrated circuit chips on a wafer. This apparatus comprises a glass ceramic carrier having test chips and means for connection to paths of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips with at least one voltage regulator for each product chip. The test chips can provide test functions such as test patterns and registers for storing test results.
U.S. Pat. No. 4,531,146 to Cutchaw discloses an apparatus for cooling a high-density integrated circuit package. The apparatus includes a base in which the circuit package or wafer is mounted and a heat exchanger which mounts on the base to enclose the wafer and carry away the heat generated during testing by means of a fluid coolant which is passed through the heat exchanger. The heat exchanger includes a housing having a cooling chamber, one surface of which is formed of a pliable thin wall diaphragm of thermally conductive material. Heat generated by burn-in testing of the integrated circuits is exchanged across the diaphragm of thermally conductive material. A liquid coolant is passed through the chamber of the heat exchanger under pressure but does not come into direct contact with the device under test.
U.S. Pat. No. 6,108,937 to Raaijmakers discloses apparatus and method for cooling semiconductor wafers. In one embodiment a wafer and its supporting structure is lifted after high temperature testing to a position in close proximity to a cold wall of a thermal processing chamber which acts as a heat sink. Conductive heat transfer across a small gap from the wafer to the heat sink facilitates the cooling of the wafer. Other embodiments are disclosed but generally involve the concept of bringing the heated wafer under test into close proximity with a cooling station or plate to accomplish the heat transfer and cooling of the wafer.
U.S. Pat. No. 5,168,348 to Chu et al. discloses a heat transfer mechanism for removing heat generated in electronic circuit modules. Chu et al. utilize an impingement cooled compliant heat sink to extract heat from an array of computer chips in an electric module. Though various embodiments are disclosed, the most basic utilizes a metal sheet brought into contact with chips or a multi-chip module with the metal sheet acting as a spreader plate for jet impingement immersion cooling with fluorocarbon, liquid nitrogen or other dielectric liquids.
Known methods and apparatus for testing of integrated circuits generally rely upon an element in the testing apparatus that acts as a heat sink or heat exchanger to receive heat from the wafer under test after the wafer has been run through a test cycle. Further, known apparatus generally are not utilized to regulate the temperature of the wafer under test or to maintain the wafer at a desired or target test temperature throughout a test cycle.
If burn-in testing is performed in ambient air, an oxygen-containing environment, the metal parts and contacts of the testing system and associated electronics are susceptible to oxidation. Over time, these oxygen-sensitive parts contacts may be oxidized, requiring replacement of the parts or the entire system. For some applications, testing of integrated circuit chips may be conducted at high or low temperatures. When testing is conducted at low temperatures, moisture in an ambient air environment may condense on the sensitive electronics, metal parts, and contacts of testing apparatus. This condensation can lead to shorting and failure of the sensitive parts of the testing apparatus or functional failure of the apparatus as whole. Such shorting or failure would lead to unwanted manufacturing and processing downtime.
It is desirable to provide apparatus and a testing system that will allow for both high and low temperature burn-in testing without the aforementioned disadvantages.
In one embodiment, the oven has one or more wafer chucks for holding wafers during wafer burn-in testing, a first temperature control circuit for providing a heat transfer gas to the wafer chucks to control the temperature of the wafers held within the chucks, and a second temperature control circuit for providing heat transfer gas to regulate the environment around the wafer chucks and the first temperature control circuit as the wafers are cycled between temperature extremes by the first temperature control circuit. The first temperature control circuit and second temperature control circuit are adapted to receive heat transfer gas from a heat transfer gas source. The oven may include a heat transfer gas source or may be adapted to connect to a heat transfer gas source located at the test facility.
In another embodiment, the invention is directed to an oven for wafer level burn-in testing of electronics/semi-conductor wafers. The oven has an oven unit which includes a chamber defining a chamber environment. The oven further includes a cascade heat control system with a first heat transfer circuit for providing a heat transfer gas to a wafer chuck module and a second heat transfer circuit for providing heat transfer gas to the chamber environment. The two circuits are connected by a pressure release conduit by a first venting valve for venting of heat transfer gas from the first heat transfer circuit into the second heat transfer circuit. The second heat transfer circuit also has a second venting valve for venting of heat transfer gas from the second circuit to the outside environment. The oven includes at least one wafer chuck module including a test board and at least one wafer chuck for holding at least one electronic wafer for burn-in testing. The module further includes an inlet conduit and outlet conduit, and is in integral flow-through communication with the first heat transfer circuit connected thereto by the inlet and outlet conduits. The wafer chuck module is disposed within the chamber environment of the oven unit.
In another embodiment, the invention is directed to a method of wafer level burn-in testing. In accordance with a method of the invention, an oven is provided, the oven having an oven unit including a chamber defining a chamber environment, a cascade heat control system having a first heat transfer circuit for providing heat transfer gas to a wafer chuck module, and a second heat transfer circuit for providing heat transfer gas to the chamber environment. The two circuits are connected by a pressure release conduit having a first venting valve for venting of heat transfer gas from the first heat transfer circuit into the second heat transfer circuit and the second heat transfer circuit has a second venting valve for venting of heat transfer gas from the second circuit to the outside environment. The oven has at least one wafer chuck module, including a test board, and at least one wafer chuck for holding at least one electronic or semiconductor wafer for burn-in testing and an inlet conduit and outlet conduit. The module is disposed within the chamber environment, and is in integral part of the first heat transfer circuit being connected thereto by the inlet and outlet conduits. An electronic or semiconductor wafer is placed into at least one wafer chuck. A cooled inert gas is circulated through the first heat transfer circuit to bring the temperature of the wafer from a target wafer test temperature. The cooled inert gas is also circulated through the second heat transfer circuit to bring the temperature of the chamber environment to a target chamber test temperature. The temperature of the wafer is then maintained at the target wafer test temperature for the duration of the test and the temperature of the chamber environment is maintained at the target chamber test temperature for the duration of the test. Required test signals are provided to the wafer for the duration of the test.
In another embodiment, the invention is directed to a method of wafer level burn-in testing. In accordance with a method of the invention, an oven is provided, the oven having an oven unit including a chamber defining a chamber environment, a cascade heat control system having a first heat transfer circuit for providing heat transfer gas to a wafer chuck module, and a second heat transfer circuit for providing heat transfer gas to the chamber environment. The two circuits are connected by a pressure release conduit having a first venting valve for venting of heat transfer gas from the first heat transfer circuit into the second heat transfer circuit and the second heat transfer circuit has a second venting valve for venting of heat transfer gas from the second circuit to the outside environment. The oven has at least one wafer chuck module, including a test board, and at least one wafer chuck for holding at least one electronic or semiconductor wafer for burn-in testing and an inlet conduit and outlet conduit. The module is disposed within the chamber environment and is an integral part of the first heat transfer circuit being connected thereto by the inlet and outlet conduits. An electronic or semiconductor wafer is placed into at least one wafer chuck. A heated inert gas is circulated through the first heat transfer circuit to bring the temperature of the wafer to a target wafer test temperature. The heated inert gas is also circulated through the second heat transfer circuit to bring the temperature of the chamber environment to a target chamber test temperature. The temperature of the wafer is then maintained at the target wafer test temperature for the duration of the test and the temperature of the chamber environment is maintained at the target chamber test temperature for the duration of the test. Required test signals are provided to the wafer for the duration of the test.
In another embodiment, the invention is directed to an apparatus for burn-in testing of semiconductor wafers. The apparatus or wafer chuck of the invention has a housing for holding a semiconductor wafer. The housing has an upper portion and a lower portion that are connected. The upper portion can be moved relative to the lower portion between open and closed positions. The upper portion of the housing is a heat exchanger that contacts the surface of a semiconductor wafer under test when the housing is in the closed position. The heat exchanger has an inlet port and an outlet port through which a heat transfer gas for heating and cooling of a semiconductor wafer under test passes. The inlet and outlet ports are of sufficient size to permit high volume flow of heat transfer gas through the heat exchanger. The lower portion of the apparatus has a base adapted for connection to a test circuit board and a wafer support upon which a semiconductor wafer can be placed for burn-in testing. Through the base, the wafer support is in electrical communication with the test circuit board and is capable of providing electrical connection between the semiconductor wafer and the test circuit board so that test signals can be received and transmitted.
USPTO Backgrounds
USPTO Backgrounds