1. Field of the Invention
The present invention relates generally to methods for fabricating microelectronic structures and microelectronic layers within microelectronic fabrications. More particularly, the present invention relates to methods for fabricating with reduced dimension microelectronic structures and microelectronic layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased, it has become increasingly important within the art of microelectronic fabrication to form microelectronic device structures and patterned microelectronic layers, such as but not limited to patterned microelectronic conductor layers, with continuing decreased dimensions such that increased microelectronic fabrication functionality, which is typically realized incident to increased microelectronic fabrication integration, may be effected with limited, if any, increase in overall microelectronic fabrication package size.
While continued decreases in dimension of microelectronic device structures and patterned microelectronic layers are thus essential within the fabrication of advanced microelectronic fabrications, such decreases in dimensions of microelectronic device structures and patterned microelectronic layers are often not obtained entirely without problems within the art of microelectronic fabrication. In that regard, it is often difficult to provide decreased dimensions of microelectronic device structures and patterned microelectronic layers, such as, in particular, patterned microelectronic conductor stud layers, within microelectronic fabrications without incurring expenditure for advanced microelectronic fabrication tooling, in particular advanced microelectronic fabrication photolithographic tooling.
It is thus towards the goal of forming within microelectronic fabrications microelectronic device structures and patterned microelectronic layers with decreased dimensions without employing advanced microelectronic fabrication tooling, in particular advanced microelectronic fabrication photolithographic tooling, that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic device structures and patterned microelectronic layers with desirable properties within microelectronic fabrications.
For example, Ho, in U.S. Pat. No. 5,096,802, discloses a method for reducing feature width of a microelectronic device structure or patterned microelectronic layer within a microelectronic fabrication while not employing advanced microelectronic fabrication photolithographic tooling when forming a patterned positive photoresist layer which is employed in fabricating the microelectronic device structure or patterned microelectronic layer within the microelectronic fabrication. The method employs, when forming the patterned microelectronic device structure or patterned microelectronic layer, a high temperature reflow of the patterned positive photoresist layer employed for forming the microelectronic device structure or patterned microelectronic layer to form a reflowed patterned photoresist layer, followed by an ultraviolet stabilization of the reflowed patterned positive photoresist layer to form an ultraviolet stabilized reflowed patterned positive photoresist layer having a narrower aperture width than the patterned positive photoresist layer. The ultraviolet stabilized reflowed patterned positive photoresist layer is then employed for fabricating a microelectronic device structure or patterned microelectronic layer from a microelectronics layer formed beneath the ultraviolet stabilized reflowed patterned positive photoresist layer within the microelectronic fabrication.
In addition, Haraguchi et al., in U.S. Pat. No. 5,320,932, discloses a method for forming within a microelectronics fabrication, while employing a single photoexposed blanket photoresist layer as an etch mask layer, a series of vias through a microelectronics layer (typically a microelectronics dielectric layer) to underlying microelectronics structures of different depths beneath the microelectronics layer, without overetching the microelectronics structures formed at a limited depth beneath the microelectronics layer. To realize the foregoing object, there is employed a sequential and partial development of the photoexposed blanket photoresist layer such that a first series of vias extending to lower lying microelectronics structures beneath the microelectronics layer may be at least partially etched prior to completely etching the first series of vias extending to the lower lying microelectronics structures beneath the microelectronic layer in conjunction with simultaneous etching of a second series of vias extending to the upper lying microelectronics structures of limited depth beneath the microelectronics layer.
Finally, Nogami, in U.S. Pat. No. 5,763,324, discloses a method for forming within a microelectronic fabrication, with improved uniformity across a substrate employed within the microelectronic fabrication, a series of etchback planar conductor stud layers within a series of vias through a dielectric layer employed within the microelectronics fabrication. To realize that object, there is employed when etchback planarizing the series of conductor stud layers within the series of vias through the dielectric layer within the microelectronic fabrication a series of at least two sacrificial etch back planarizing photoresist layers rather than a single sacrificial etchback planarizing photoresist layer.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed for forming within microelectronic fabrications microelectronic device structures and patterned microelectronic layers while avoiding the use of advanced microelectronic fabrication photolithographic tooling when forming the microelectronic device structures and patterned microelectronics layers within the microelectronic fabrications.
It is towards that goal that the present invention is directed.
A first object of the present invention is to provide a method for forming a microelectronic device structure within a microelectronic fabrication.
A second object of the present invention is to provide a method for forming a patterned microelectronic layer within a microelectronic fabrication.
A third object of the present invention is to provide a method in accord with the first object of the present invention or the second object of the present invention, where there is avoided use of advanced microelectronic fabrication photolithographic tooling when forming the microelectronic device structure or patterned microelectronic layer within the microelectronic fabrication.
A fourth object of the present invention is to provide a method in accord with the first object of the present invention, the second object of the present invention or the third object of the present invention, which method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a microelectronic layer for use within a microelectronic fabrication. To practice the method of the present invention, there is first provided a substrate. There is then formed over the substrate a target layer. There is then formed upon the target layer a patterned photoresist layer which defines a first aperture. The first aperture has a first aperture width which exposes a first portion of the target layer. There is then reflowed thermally the patterned photoresist layer to form a reflowed patterned photoresist layer which defines a substantially straight sided second aperture. The second aperture has a second aperture width less than the first aperture width, and the second aperture thus exposes a second portion of the blanket target layer of areal dimension less than the first portion of the blanket target layer. Finally, there is then fabricated the target layer to form a fabricated target layer while employing the reflowed patterned photoresist layer as a mask layer.
There is provided by the present invention a method for forming a microelectronic device structure or a patterned microelectronic layer within a microelectronic fabrication, where there is avoided use of advanced microelectronic fabrication photolithographic tooling when forming the microelectronic device structure or patterned microelectronic layer within the microelectronic fabrication. The method of the present invention realizes the foregoing object by employing when forming the microelectronic device structure or patterned microelectronic layer while fabricating a target layer formed beneath a patterned photoresist layer within the microelectronic fabrication a thermal reflow processing of the patterned photoresist layer, which has a first aperture defined by a first aperture width, to form a reflowed patterned photoresist layer having a second aperture defined by a second aperture width less than the first aperture width. The reflowed patterned photoresist layer is then employed for fabricating the target layer. Since the second aperture width is defined as less than the first aperture width while employing a thermal reflow process, there may be avoided when: (1) forming the patterned photoresist layer; (2) forming the reflowed patterned photoresist layer; and (3) fabricating the target layer, advanced microelectronic fabrication photolithographic tooling.
The method of the present invention is readily commercially implemented. The method of the present invention may be practiced employing photoresist materials and thermal reflow annealing methods as are generally known in the art of microelectronics fabrication. Since it is a process control and materials selection which provides at least in part the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
USPTO Backgrounds
USPTO Backgrounds