1. Field of the Invention
The invention relates to a method for producing a semiconductor wafer. In particular, the invention is intended for polishing semiconductor wafers of the next technology generations, primarily wafers which have a diameter of 300 mm or more, in particular a diameter of 450 mm.
2. Background Art
At present, polished or epitaxially coated semiconductor wafers with a diameter of 300 mm are used for the most demanding applications in the electronics industry. Silicon wafers with a substrate diameter of 450 mm are in development.
An essential reason why the electronics industry desires larger substrates for the production of their components, whether microprocessors or memory chips, resides in the enormous economic advantage which they promise. In the semiconductor industry it has for a long time been customary to focus on the available substrate area, or in other words to consider how great a number of components, i.e. logic chips or memory chips, can be accommodated on an individual substrate. This is related to the fact that a multiplicity of the component manufacturer's processing steps are aimed at the entire substrate, but there are also the individual steps for structuring the substrates, i.e. producing the component structures which subsequently lead to the individual chips, and therefore the production costs for both groups of processing steps are determined very particularly by the substrate size.
The substrate size thus influences the production costs per component to a very considerable extent, and is therefore of immense economic importance. However, increasing the substrate diameter entails great and sometimes entirely new, hitherto unknown technical problems. In particular, all the processing steps, whether they are purely mechanical (sawing, grinding, lapping), chemical (etching, cleaning) or chemical-mechanical in nature (polishing) as well as the thermal processes (epitaxy, annealing), require thorough revision, in particular with respect to the machines and systems (equipment) used for them.
The present invention focuses on the polishing of a semiconductor wafer as the last essential processing step when the wafer is intended for the production of highly integrated circuits such as memory chips, or in principle as the penultimate essential processing step which precedes epitaxy of the wafer, when the wafer is intended to be used as a so-called epi-wafer for the production of modern microprocessors.
The Inventor has discovered that the process of polishing 450 mm wafers requires a fundamental change. Those polishing methods known in the prior art which will be taken into consideration for defining the new polishing process will be presented below. This essentially involves modifications of the conventionally used methods of double sided polishing (DSP) and chemical-mechanical polishing (CMP), which in one case comprise polishing both sides of a semiconductor wafer by means of a polishing pad while supplying a polishing agent as a stock polishing (DSP step) and in the other case final polishing only of the frontside (the “component side”) by using a softer polishing pad as so-called finish polishing (CMP step), but also relatively new so-called “fixed-abrasive polishing” (FAP) technologies in which the semiconductor wafer is polished on a polishing pad which, however, contains an abrasive substance bound in the polishing pad (“fixed-abrasive pad”). A polishing step in which such an FAP polishing pad is used will be referred to below as an FAP step for brevity.
Besides DSP, in the prior art so-called CMP polishing is also necessary in order to eliminate defects and reduce the surface roughness. In CMP, a softer polishing pad is used than in DSP. Furthermore only one side of the semiconductor wafer is polished by means of CMP, namely the side on which components are subsequently intended to be fabricated. The prior art also refers to this as finish polishing. CMP methods are disclosed, for example, in US 2002/0077039 and in US 2008/0305722.
WO 99/55491 A1 describes a two-stage polishing method with a first FAP polishing step and a subsequent second CMP polishing step. In CMP, the polishing pad contains no fixed abrasive substance. Here, as in a DSP step, an abrasive substance in the form of a suspension is introduced between the silicon wafer and the polishing pad. Such a two-stage polishing method is used in particular to eliminate scratches which the FAP step has left behind on the polished surface of the substrate.
EP 1 717 001 A1 is an example of FAP steps also being used for polishing semiconductor wafers, on the surface of which component structures have not yet been formed. Polishing such semiconductor wafers is primarily intended to generate at least one surface which is particularly flat and has the least possible microroughness and nanotopography.
US 2002/00609967 A1 relates to CMP methods for planarizing topographical surfaces during the production of electronic components. The main aim is to mitigate the disadvantages of low material removal rates when using FAP polishing pads. A sequence of polishing steps is proposed, in which polishing is carried out first with an FAP pad in conjunction with a polishing agent suspension and subsequently with an FAP pad in conjunction with a polishing agent solution. The series of steps is deliberately selected in order to increase the material removal rate. Polishing wafers of material with a homogeneous composition, for example semiconductor wafers, is not disclosed therein.
Likewise, WO 03/074228 A1 also discloses a method for planarizing topographical surfaces during the production of electronic components. Here, the key point of the invention is the endpoint recognition in CMP methods. As is known, endpoint recognition involves terminating the polishing and therefore the material removal promptly before material is removed from regions which are specifically not intended to be polished. To this end, a two-stage method is proposed for polishing a copper layer. In a first step it is polished with an FAP polishing pad, in which case the polishing agent optionally may or may not contain free abrasive particles. In the second polishing step in which it is likewise polished with an FAP pad, however, the use of a polishing agent with free abrasive particles is essential.
German Patent Application DE 102 007 035 266 A1 describes a method for polishing a substrate of silicon material, comprising two polishing steps of the FAP type which differ in that a polishing agent suspension which contains unbound abrasive substance as a solid is introduced between the substrate and the polishing pad in one polishing step, while in the second polishing step the polishing agent suspension is replaced by a polishing agent solution which is free of solids.
The expression “polishing agent” will be used below as an umbrella term for polishing agent suspensions and polishing agent solutions.
In connection with the fabrication of semiconductor wafers, particularly semiconductor wafers with a diameter of greater than or equal to 300 mm, semiconductor wafers with a diameter of 450 mm in particular, the handling properties, transport of the semiconductor wafers between the systems, the crucial storing, supporting and final processing properties in the process sequences are increasingly critical. This also applies to further processing of the semiconductor wafers on the part of the wafer manufacturers' customers in the processes for fabricating semiconductor components.
Here, in particular the backside of the semiconductor wafer is a crucial factor, especially since the various handling systems, in particular the devices which come in contact with the semiconductor wafer, necessitate particular backside properties of the semiconductor wafer. Such devices are for example chucks, i.e. wafer holders which hold the semiconductor wafer firmly on its backside, for example by means of vacuum suction, while the frontside is being processed, for example being ground. For systems in which the semiconductor wafer is held in its edge region, it is also important to configure the semiconductor wafer in the backside edge region so that deformation of the semiconductor wafer can be excluded. Particularly for semiconductor wafers of the next generation with a diameter of 450 mm, the properties of the wafer backside and the wafer edge will thus be crucial.
On the other hand, the backside of the semiconductor wafer is the supporting surface—for example during transport in boxes (FOUP, FOSB) or during storage or mounting in particular fabrication processes (for example coating chambers, oven processes etc.). Uncontrolled slipping of the semiconductor wafer needs to be avoided, whether during transport, loading or during the coating process.
Lastly, the requirements on the part of the customer should also be mentioned besides the process management by the wafer manufacturer: particularly critical in this regard are component production processes in which the properties of the backside of the wafers to be processed have a great influence on the success of the process step per se. This applies for example to all types of oven processes. The adhesion of the layers to be applied, for example oxide layers, depends very substantially on the surface properties, especially since the degree of reflectivity of a surface to be coated co-determines its emission and absorption behavior and therefore also the level of heat radiation absorbed and the process management per se, for example in the form of long or short coating times. The properties of the wafer backside have hitherto been ignored in this regard.
USPTO Backgrounds
USPTO Backgrounds