With higher integration of semiconductor devices, a pattern of a wiring or a separation width required for a manufacturing process tends to be miniaturized. Such a miniaturized pattern is formed by etching an underlayer with a resist pattern as an etching mask (see, e.g., Japanese Patent Laid-Open Publication No. 2011-060916).
The resist pattern is formed, for example, by forming a resist layer on the underlayer, patterning the resist layer into a predetermined shape by a photolithography technique, and then smoothing the surface using, for example, plasma etching.
Further, as a method of smoothing the surface of the resist layer patterned into a predetermined shape, a method of cleaving the main chain of a resist material contained in the resist layer by, for example, irradiation with electron beams or vacuum ultraviolet rays instead of the plasma etching, may be used in some cases.
USPTO Backgrounds
USPTO Backgrounds