The present application relates to a semiconductor device, particularly to that of double heterojunction bipolar transistor.
Among high-power high-voltage amplifier devices are double heterojunction bipolar transistors (D-HBT for short hereinafter). They are classified into InGaAs/InP type and GaAs/InGaP or GaAs/AlGaAs type. The former is composed of the substrate of InP, the emitter and collector layers of InP, and the base layer of InGaAs, with lattice matching between the substrate and the layer placed thereon. The latter employs a substrate of GaAs, with lattice matching between the substrate and the layer placed thereon. The former is expected to excel the latter in performance (high speed operation and high voltage) because InP (for the emitter and collector layers) has a large band gap and a great carrier mobility (in the high field region) and InGaAs (for the base layer) has a greater carrier mobility than GaAs.
In the D-HBT of InGaAs/InP type constructed as mentioned above, the InGaAs base layer contains as much In as about 53% for lattice matching with the InP substrate. This makes the conduction band discontinuous between the emitter layer and the base layer or between the base layer and the collector layer, resulting in a spike-like energy barrier in their respective interfaces. The barrier existing in the emitter-base interface causes an offset voltage in the collector current-voltage characteristics, resulting in a dull rise current. In addition, the spike-like barrier existing in the base-collector interface limits the collector current, which leads to an increased power consumption at the time of operation with a large output.
One way to eliminate the discontinuity of conduction band between the emitter layer and the base layer and between the base layer and the collector layer, thereby removing the spike-like barrier, is to insert a transition layer between the emitter layer and the base layer and between the base layer and the collector layer, thereby making the conduction band continuous. An example of D-HBT of InGaAs/InP type with a transition layer is shown in FIG. 9 (which is a schematic sectional view). The D-HBT of InGaAs/InP type shown in FIG. 9 consists of InP substrate 101, InP sub-collector layer 102, InP collector layer 103, InGaAs base layer 104, transition layer 201, InP emitter layer 105, and InGaAs contact layer 106, which are arranged sequentially on top of the other.
The transition layer 201 is composed of alternately arranged layers of InGaAs and InAlAs. Alternatively, it is a layer of InGaAlAs with graded composition. The foregoing structure may be modified such that a thin sheet of dopant atoms is interposed between the emitter layer 105 and the transition layer 201, for example, Japanese Patent Laid-open No. 2004-88107.
There is another idea of improving operation speed and reducing offset voltage by forming a contact area from InP and InGaAs in superlattice structure between the collector layer and the base layer; the contact area produces a pseudo smooth connection between the conduction bands for example, Japanese Patent Laid-open No. Hei-4-251934.
In the case of D-HBT of InGaAs/InP type having lattice matching with the InP substrate as mentioned above, the base layer (InGaAs) contains as much In as about 53%, and the InGaAs compound of such a composition has an Auger recombination coefficient of 7×10−29 cm6/s, which is larger than that of GaAs (1×10−30 cm6/s). Therefore, the heavily doped InGaAs base layer has a higher recombination probability than the GaAs base layer.
The result of the foregoing is that the D-HBT of InGaAs/InP type with the InGaAs base layer has a smaller current gain than the D-HBT of GaAs/InGaP type or GaAs/AlGaAs type with the GaAs base layer.
Moreover, in the case of D-HBT of InGaAs/InP type having lattice matching with the InP substrate, the available wafer for the InP substrate is not so large as that for the GaAs substrate, and hence the D-HBT of InGaAs/InP type is more expensive than that of GaAs/InGaP type. For solution to these problems, there has been proposed a D-HBT of InGaAs/InP type which is formed on a GaAs substrate, with a metamorphic buffer layer interposed between them.
The disadvantage of this D-HBT is that forming the InGaAs/InP layer on the GaAs substrate in such a way as to achieve lattice matching with the InP substrate results in a large number of crystal defects at the time of crystal growing due to the large difference in lattice constant. This leads to the low yields and poor reliability of the semiconductor device formed thereon.
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