A variety of packaging techniques are offered today for integrated circuits (ICs). Packaging an integrated circuit allows it to be mountable to a circuit board, and more particularly a printed circuit board (PCB). In addition, packaging allows an IC to be electrically isolated from other IC packages on a PCB. The packaging itself also provides a measure of protection against exposure to direct physical contact with the IC during assembly and operation.
Packaged ICs are available in a variety of packaging schemes that include a Dual Inline Package (DIP), Small Outline Integrated Circuit package (SOIC), Thin Shrink Small Outline Package (TSSOP), or Shrink Small Outline Package (SSOP) to name a few. These packages include interconnects that are coupled with an IC. The IC itself is surrounded, housed, molded, or encapsulated in a dielectric material such as plastic or ceramic. A DIP encapsulated in plastic may be referred to as a Plastic Dual Inline Package (PDIP). Alternatively, if a DIP is encapsulated in a ceramic material it may be referred to as a Ceramic Dual Inline Package (CDIP).
An example DIP 10 is illustrated in FIG. 1a. DIP 10 includes an IC 12 and a dielectric housing 14. The IC 12 is laterally mounted within the dielectric housing 14. Upon mounting the IC 12, the dielectric housing 14 is sealed. Prior to the dielectric housing 14 being sealed, however, conductive interconnects, such as interconnect 16, made up of a material such as aluminum or copper are wire bonded to the IC 12 via wire and bump bonds 20.
The profile of DIP 10 is illustrated in FIG. 1b. DIP 10 is offset from a PCB 24 by an offset height 26. One drawback to DIP 10 is that its offset height 26 may not be suitable for modem electronics. Many modem electronics devices, such as cell-phones and personal digital assistants (PDAs), have stringent offset height requirements for IC packages. Primarily these stringent offset height requirements are due to the drive to make modem electronic devices more compact. By minimizing the offset height of IC packages, a PCB and its mounted IC packages become more compact and thereby make an electronic device more compact.
One IC package that is capable of being more compact is an SOIC package. One such SOIC package 28 is illustrated in FIG. 1c. The interconnects, such as interconnect 30, in this configuration allow the SOIC package to be mounted closer to the PCB 24, thereby reducing the offset height 32. One problem still inherent to this configuration is that a layer of dielectric material 34 still contributes to the offset height 32.
Additionally, another problem associated with conventional IC packages is that they are not easily vertically, or perpendicularly mountable. One application that some modem electronic devices include is compassing. These compassing applications use axis sensors to sense a magnetic field. X and Y-axis (or 2-axis) magnet field sensors may be placed laterally in an IC package (and in turn a PCB) and operate appropriately. X, Y, and Z-axis (or 3-axis) sensors, however, require that one of the sensors be orthogonally placed in relation to the other two sensors.
When a conventional third axis of a 3-axis sensor is mounted, it is difficult to meet the stringent offset height requirement that modem electronic devices require. The offset height of the third axis sensor is increased because the IC and the IC package is mounted perpendicularly, the interconnects are not easily bondable to a PCB, and the dielectric housing contributes to the offset height.
Therefore, an IC package is presented that allows an IC within an IC package to be mounted perpendicularly and minimizes the offset height of the IC package.
USPTO Backgrounds
USPTO Backgrounds