A conventional method for forming a semiconductor device in the prior art comprises the following steps: forming a gate 14 and sidewall spacers 16 on a semiconductor substrate 10 (as shown in FIG. 1); the gate 14 is formed on the semiconductor substrate 10 with a gate dielectric layer 12 therebetween, and the sidewall spacers 16 cover the opposite side surfaces of the gate 14; then forming source/drain regions 20 and contact regions 18 (e.g. a metal silicide layer); forming a planarized dielectric layer 22 which covers the gate 14 and sidewall spacers 16 (as shown FIG. 2); and then, etching the dielectric layer 22 with a mask, so as to form contacts.
In the above method, the step for forming the contacts comprises: first, forming contact vias 30 in the dielectric layer 22 (as shown in FIG. 3), wherein the contact vias 30 expose a portion of the contact regions 18; next, forming a contact layer 32 which covers the bottom and sidewalls of contact vias 30 (as shown in FIG. 4); then, forming a conductive layer 34 which is formed on the contact layer 32 and fills the contact vias 30 (as shown in FIG. 5). As shown in FIG. 6, after the conductive layer 34 and the contact layer 32 are planarized to expose the dielectric layer 22, subsequent operations will be continually performed.
However, as pitches between semiconductor devices are being scaled down, process windows in the formation of contacts also become progressively smaller. Accordingly, there is a need to propose a new process for fabricating semiconductor devices, in order to extend the process windows.
USPTO Backgrounds
USPTO Backgrounds