1. Field of the Invention
The present invention relates generally to methods for forming gate dielectric layers within semiconductor integrated circuit microelectronic fabrications. More particularly, the present invention relates to methods for forming multiple gate dielectric layers with multiple thicknesses within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Semiconductor integrated circuit microelectronic fabrications are formed from semiconductor substrates over which are formed patterned conductor layers which are separated by dielectric layers.
As semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor integrated circuit microelectronic fabrication functionality levels have increased, it has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses. Within the context of the present invention, gate dielectric layers are intended as dielectric layers which are formed directly upon silicon semiconductor substrates, whether or not they are employed within field effect transistor (FET) devices, although gate dielectric layers are most typically employed within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications. Similarly, although gate dielectric layers within semiconductor integrated circuit microelectronic fabrications are most commonly formed employing thermal oxidation methods, gate dielectric layers within semiconductor integrated circuit microelectronic fabrications may also be formed employing various combinations of thermal oxidation methods, deposition methods and nitridation methods.
It has become increasingly common in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices which are formed with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses insofar as the functional requirements and operational requirements of the pluralities of semiconductor devices formed within the semiconductor integrated circuit microelectronic fabrications often demand the plurality of gate dielectric layers having the plurality of gate dielectric layer thicknesses. For example and without limitation, within embedded semiconductor integrated circuit microelectronic fabrications (i.e., semiconductor integrated circuit microelectronic fabrications which perform both a logic function and a memory function), it is common to employ comparatively thin gate dielectric layers within field effect transistor (FET) devices which perform the logic function, such as to enhance operating speed of the field effect transistor (FET) devices which perform the logic function, while employing comparatively thick gate dielectric layers within field effect transistor (FET) devices which perform memory functions or other peripheral functions, wherein the field effect transistor (FET) devices which perform the memory function or other peripheral function are subject to comparatively high operating voltages.
While it is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, and often unavoidable in the art of semiconductor integrated circuit microelectronic fabrication to provide pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, forming within semiconductor integrated circuit microelectronic fabrications such semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses is not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, it is often difficult to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses with enhanced reliability of the semiconductor integrated circuit microelectronic fabrications.
It is thus desirable in the art of semiconductor integrated circuit microelectronic fabrication to form within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layers thicknesses, with enhanced reliability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication for forming, with corresponding pluralities of gate dielectric layers having corresponding pluralities of gate dielectric layer thicknesses, pluralities of semiconductor devices within semiconductor integrated circuit microelectronic fabrications.
Included among the methods, but not limiting among the methods, are methods disclosed within: (1) Barsan et al., in U.S. Pat. No. 5,672,521 (a method which employs implanting into a first region of a silicon semiconductor substrate a dose of a dopant which enhances thermal oxidation of the silicon semiconductor substrate and implanting into a second region of the silicon semiconductor substrate a dose of a nitrogen dopant which inhibits thermal oxidation of the silicon semiconductor substrate, such that upon thermal oxidation of the silicon semiconductor substrate including the first region, the second region and an unimplanted third region there is formed upon the silicon semiconductor substrate a gate dielectric layer having three thickness regions); (2) Chwa et al., in U.S. Pat. No. 6,147,008 (a method which employs implanting through a gate dielectric layer formed upon a silicon semiconductor substrate a dose of a nitrogen implanting ion which inhibits thermal oxidation of the silicon semiconductor and then patterning the gate dielectric layer to form a patterned gate dielectric layer which leaves exposed implanted and unimplanted portions of the silicon semiconductor substrate, prior to thermally oxidizing the silicon semiconductor substrate to reform a gate dielectric layer having three thickness regions); and (3) Sung, in U.S. Pat. No. 6,184,093 (a method for forming differential gate oxide layer thicknesses within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications by forming a first gate dielectric layer having a first thickness in both a central memory region and a peripheral region of a silicon semiconductor substrate and forming a pair of gate electrodes thereupon, followed by forming a second gate dielectric layer with a second thickness within both the central memory region and the peripheral region of the silicon semiconductor substrate and forming a pair of gate electrodes thereupon).
Desirable in the art of semiconductor integrated circuit microelectronic fabrication are additional methods for forming within semiconductor integrated circuit microelectronic fabrications pluralities of semiconductor devices having corresponding pluralities of gate dielectric layers in turn having corresponding pluralities of gate dielectric layer thicknesses, with enhanced reliability of the semiconductor integrated circuit microelectronic fabrications.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability.
A third object of the present invention is to provide a method in accord with the first object of the present invention and the second object of the present invention, wherein the method is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming a plurality of gate dielectric layers within a microelectronic fabrication. To practice the method of the present invention, there is first provided a semiconductor substrate having formed therein at least a pair of isolation regions which defines a series of at least three active regions of the semiconductor substrate. There is then formed, while employing a first thermal oxidation method, a series of at least three first gate dielectric layers formed to a first thickness upon the series of at least three active regions of the semiconductor substrate. There is then masked the semiconductor substrate to leave uncovered only a second of the at least three first gate dielectric layers and stripped from only a second of the at least three active regions of the semiconductor substrate only the second of the at least three first gate dielectric layers. There is then formed, while employing a second thermal oxidation method, a second gate dielectric layer upon only the second of the at least three active regions of the semiconductor substrate. There is then masked the semiconductor substrate to leave uncovered only a third of the at least three first gate dielectric layers and stripped from only a third of the at least three active regions of the semiconductor substrate only the third of the at least three first gate dielectric layers. Finally, there is then formed, while employing a third thermal oxidation method, a third gate dielectric layer having a third thickness upon only the third of the at least three active regions of the semiconductor substrate.
Within the present invention, by selectively stripping from only the second of the at least three active regions of the semiconductor substrate only the second of the at least three gate dielectric layers and selectively stripping from only the third of the at least three active regions of the semiconductor substrate only the third of the at least three gate dielectric layers, a remaining first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are formed with attenuated etching of the pair of isolation regions.
There is provided by the present invention a method for forming within a semiconductor integrated circuit microelectronic fabrication a plurality of semiconductor devices having a corresponding plurality of gate dielectric layers having a corresponding plurality of gate dielectric layer thicknesses, wherein the semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability.
The present invention realizes the foregoing object incident to having formed a series of at least three first gate dielectric layers upon a series of at least three active regions of a semiconductor substrate separated by at least a pair of isolation regions within the semiconductor substrate by: (1) selectively stripping from only a second of the at least three active regions of the semiconductor substrate only a second of the at least three gate dielectric layers prior to forming a second gate dielectric layer upon the second of the at least three active regions of the semiconductor substrate; and (2) selectively stripping from only a third of the at least three active regions of the semiconductor substrate only a third of the at least three gate dielectric layers prior to forming a third gate dielectric layer upon the third of the at least three active regions of the semiconductor substrate. By employing such a selective sequential stripping method, a remaining first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are formed with attenuated etching of the pair of isolation regions, and the semiconductor integrated circuit microelectronic fabrication is thus formed with enhanced reliability.
The method of the present invention is readily commercially implemented.
The present invention employs methods and materials as are otherwise generally conventional in the art of semiconductor integrated circuit microelectronic fabrication, but employed within the context of a specific process ordering and specific materials limitations to provide the present invention. Since it is thus at least in part a specific process ordering and specific materials limitations which provide the present invention, rather than the existence of methods and materials which provides the present invention, the method of the present invention is readily commercially implemented.
USPTO Backgrounds
USPTO Backgrounds