Devices in a network use large switching fabrics capable of supporting traffic with a variety of quality of service (QoS) requirements. A high performance, multiple QoS (MQoS) device achieves high throughput and fair resource allocation while providing control over cell loss and delay for individual flows or groups of flows.
Although many scheduling mechanisms suited for an output buffered switch architecture have been shown to provide MQoS support, the cost and complexity of the output buffered fabric is prohibitive for large switch sizes. The crossbar switch fabric used in input buffered switches scales to terabit per second (Tbps) speeds; however, the scheduling control required to match input and output links over a small time interval (internal cell slot) is complex. While recent reductions in matching process complexity have increased throughput, QoS is still an issue.
A hybrid architecture provides a compromise between a costly output buffered switch fabric and the scheduling complexity and QoS management difficulty associated with the input buffered switch. A hybrid architecture typically contains a small amount memory in the switch fabric/outputs with additional memory at the inputs. The memory is used to buffer data flows passing through the switch.
USPTO Backgrounds
USPTO Backgrounds