1. Field of the Invention
The present invention relates to processes for making a multilayer printed wiring board. The present invention also relates to multilayer printed wiring boards produced by such a process.
2. Discussion of the Background
As a technique for producing a multilayer printed wiring board, a production method using a build-up process of alternately layering an insulating layer and a conductive layer on a core substrate is conventionally known. For formation of an insulating layer, an adhesive film is exclusively used, which is formed by forming a thermosetting resin layer on a plastic film, where an insulating layer is formed by laminating the adhesive film on an internal-layer circuit substrate, detaching the plastic film and thermally curing the thermosetting resin. On the other hand, in view of the recent demand for downsizing of electronic device and electronic parts, for example, multilayer printed wiring boards tend to be made thinner, since a thinner core substrate and omission of a substrate are desired and the like. In such attempt to provide a thinner multilayer printed wiring board by producing a thinner core substrate, omitting a substrate and the like, the use of a prepreg as a material to form an interlayer insulating layer is effective for maintaining the mechanical strength of the multilayer printed wiring board.
FIGS. 4(a)-(e) and FIGS. 5(a) and (b) are sectional views of steps showing production steps of a multilayer printed wiring board comprising an interlayer insulating layer formed using a prepreg comprised of a sheet-like glass cloth fiber substrate impregnated with a thermosetting resin.
First, a circuit substrate 10 and a prepreg 3 comprised of a glass cloth 1 impregnated with a thermosetting resin composition 2 are prepared (FIGS. 4(a) and 4(b)), the prepreg 3 is laminated on a circuit substrate 10 to cover a conductor pattern (pad) 11 on the surface of the circuit substrate 10, and the thermosetting resin composition 2 is cured to form an insulating layer 4 (FIG. 4(c)). Then, as shown in FIG. 4(d), a via hole (blind via) 5 is formed by laser irradiation on the insulating layer 4. Due to the difference in the processability between the glass cloth 1 and the insulating layer 4 (cured product of thermosetting resin composition 2), the glass cloth 1 protrudes from the wall surface of the via hole 5 (see, FIG. 4(d)). When, after the laser processing, a desmear treatment to remove the residue produced by the laser processing is applied, the glass cloth 1 further protrudes from the wall surface of via hole 5 (see, FIG. 4(e)). However, when the glass cloth 1 protruding from the wall surface of the via hole is left as it is, the glass cloth may impede the flow (flowability) of a plating solution in the next plating process, thereby producing an uneven plating in the via hole. As a result, formation of a via with high conduction reliability becomes difficult. To prevent this, the glass cloth protruding from the sidewall surface of the via hole needs to be treated and, for example, JP-A-2002-100866 suggests an etching treatment with fluoride and the like. Moreover, JP-A-2005-86164 points out a problem that, when the method described in the above-mentioned JP-A-2002-100866 is applied to the actual production of a multilayer circuit substrate, a matrix resin melted by laser irradiation attaches to a glass cloth and prevents contact of fluoride with the glass cloth, whereby the glass cloth cannot be effectively removed by etching. To solve the problem, the resin residue is removed using an alkaline potassium permanganate solution after formation of a via hole, and the glass cloth is then subjected to an etching treatment. After the etching treatment of the glass cloth, the glass cloth 1 does not protrude from the wall surface of the via hole 5 (see, FIG. 5(a)). In this state, a via 20 is generally formed in the via hole 5 by plating and the like (see, FIG. 5(b)), whereby the interlayer conduction is achieved.
USPTO Backgrounds
USPTO Backgrounds