1. Field of the Invention
The present invention relates to the field of digital data processing. More specifically, the present invention relates to the design of high speed floating point unit in a digital data processor.
2. Background Information
Floating point operation is one of the essential tasks repeatedly performed by many digital data processors. As a result, the floating point unit (FPU) is an essential part of a digital data processor. Much effort has been expanded to try to maximize the speed of FPUs, nevertheless, any further improvement on the speed of FPUs is still desirable.
During floating point operations, it is often necessary to determine the amount of right shift for a mantissa of a floating point number. The amount of right shift is equal to the difference between the exponents of the two floating point input operands. Thus, it is often necessary to perform a rapid addition/subtraction operation, and then followed by a shifting operation. Conventional FPU typically includes an adder to perform the addition/subtraction operation, and a separate barrel shifter to perform the shifting operation. Conventional FPU typically also attempts to maximize the performance of the FPU by maximizing the performance of the individual components. Thus, typically a high speed parallel adder and any one of a number of high speed barrel shifter would be employed.
This conventional approach suffers from at least one disadvantage in that high speed parallel adders typically achieve their improvement in performance by focusing on the critical paths. As a result, the generation speed for the lower sum bits are sacrificed in favor of the generation speed of the higher order sum bits that are on the critical paths. Since the shifting operation serially depends on the output sum bits of the adder, the conventional approach actually leads to less than optimal combined performance for the addition and shifting operations when viewed in totality.
Thus, an alternate approach that yields better overall combined performance for the addition and shifting operations is desired.
USPTO Backgrounds
USPTO Backgrounds