When designing an integrated circuit, memory devices in a customer design are mapped to memory resources within an integrated circuit layout pattern. It is customary for the integrated circuit manufacturer to provide the customer with various tools and models for assisting the customer in designing or customizing an integrated circuit for a particular application. Some integrated circuits have different types of memory resources and can include large arrays or matrices of standard memory elements. For example, in LSI Logic Corporations' RapidChip® Technology, tens or even hundreds of memories in a customer design can be mapped into matrices of standard Random Access Memories (e.g., RRAM) that are pre-defined in the layout pattern.
From a timing point of view, when a customer memory is mapped to a memory matrix, the memory is essentially substituted with a “mapped memory wrapper.” The mapped memory wrapper includes a model of the memory itself and models of any input or output delays caused by mapping the memory into the memory matrix and by the particular tiling of the memory in that matrix. For example, the mapped memory wrapper can model delays introduced by any additional logic in the memory matrix and can model differences in delay caused by the manner in which the memory was tiled into the matrix. These delays and appropriate timing constraints can be generated by appropriate tools that perform the mapping procedure or are associated with such tools.
The straightforward usage of existing tools that provide memory timing models for timing stimulation are, however, often inconvenient under such conditions and somehow become even cumbersome because they are generally aimed at the memory module itself rather than its wrapper indicated above. Due to the size and complexity of large memory matrices, it can become difficult to generate accurate timing models and apply constraints for each input and output path through the matrix.
Improved memory timing models and methods of generating such models are therefore desired.
USPTO Backgrounds
USPTO Backgrounds