This invention relates to digital signal processing (“DSP”) circuitry, and more particularly to arrays of DSP circuit modules or blocks that can individually and/or collectively perform DSP operations such as multiplications that are larger than the individual multiplier components in those blocks. Another possible aspect of the invention is to employ redundancy so that when two or more DSP blocks must work together, that can still be accomplished even if there is a circuit defect that makes some DSP block(s) unusable.
Various circumstances may call for an integrated circuit to be fabricated with multiple instances of blocks or modules of DSP circuitry. An example of such an integrated circuit is a programmable logic device (“PLD”) or a field-programmable gate array (“FPGA”). Such a device may have a plurality of rows of various kinds of circuitry, such as relatively general-purpose logic. Each such row may also include a block of DSP circuitry (i.e., circuitry that is hard-wired to at least some degree to perform a particular DSP function or a particular set of DSP functions). It can be desirable in such a situation to size the DSP blocks so that they fit within the (row) boundaries of the other circuitry in the row. This may mean that a DSP block is too small, by itself, to perform some DSP functions that it may be desired for the integrated circuit to perform. In such cases it would be desirable to facilitate optimal “stitching together” of multiple DSP blocks in various ways so that larger DSP functions can be efficiently performed in two or more DSP blocks. However, a countervailing concern may be that if any portion of the circuitry associated with DSP blocks that need to be stitched together is not usable (e.g., because of a manufacturing defect in the integrated circuit), that can make it much more difficult or impossible to stitch together those DSP blocks. This may greatly increase the chances that a partly defective integrated circuit cannot be used at all.
Another possible consequence of trying to make a DSP block no larger than will fit within the (row) boundaries of other circuitry in a row on an integrated circuit device like a PLD is that this can make it more difficult for the integrated circuit device to meet the growing need for arithmetic operations having greater arithmetic precision. Greater arithmetic precision means performing arithmetic operations that extend to a greater number of numerical “places,” i.e., that include more digits. For example, the multiplication of an 18-bit multiplicand by an 18-bit multiplier (a so-called 18×18 multiplication) nominally produces a 36-bit product. But a 27×27 multiplication nominally produces a 54-bit product. If DSP blocks on an integrated circuit are designed to perform 18×18 multiplication, it can take several such blocks, working together, to perform a 27×27 multiplication. This can be relatively inefficient and “expensive” in terms of resources consumed. Even if full 54-bit products from such 27×27 multiplications are not needed, there can still be inefficient and expensive use of DSP resources involved in producing “truncated” products of such larger multiplications in multiple DSP blocks that are designed to individually fit within one row of other circuitry.
USPTO Backgrounds
USPTO Backgrounds