The present invention relates to microprocessor cores with power gating, and more specifically, to predictively turning off charge pump supplying voltage to gates of the power switch header connected to a power gated microprocessor core.
Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the flow of current to blocks of the circuit that are not currently in use. Power gating also reduces stand-by or leakage power.
Power gating affects design architecture of the integrated circuit, and increases time delays, as power gated modes have to be safely entered and exited. Architectural trade-offs exist between designing for the amount of leakage power saving in low power modes and the energy dissipation to enter and exit the low power modes. Shutting down the blocks can be accomplished either by software or hardware. Driver software can schedule the power down operations, or hardware timers can be utilized. A dedicated power management controller is another option.
USPTO Backgrounds
USPTO Backgrounds