Integrated circuits (ICs) are often designed at a high-level of abstraction. For example, ICs may be described in a C++ code, in a RTL (register transfer level) hardware description language such as Verilog HDL or VHDL, or, indeed, in any other programming or hardware description languages. The IC designed at a high-level of abstraction has to be synthesized logically. The gate-level synthesis is a process of generating a logic circuit according to the high-level description. Often, this is a costly and lengthy process.
One of the most important problems during IC development is to reduce the timing and area characteristics of the IC. To save the IC real estate and improve the efficiency, it is a priority to reduce the number of AND/OR switches in a logic circuit that evaluates a logic function defined in a high-level description. An AND/OR switch is a situation in which two neighboring gates on a path from an input of a logic circuit to an output of the logic circuit are of different types. The maximal number of AND/OR switches included on considered paths is called the number of AND/OR switches.
The logic function to be evaluated may be a Boolean function. It is well known that each Boolean function may be presented as a disjunction of conjunctions, which may be referred to as a disjunction normal form (DNF), and thus may be evaluated by the Boolean circuit having only AND/OR switches. However, this Boolean circuit may have a large complexity and the creation of this circuit is a NP-hard problem. NP-hard (Non-deterministic Polynomial-time hard) refers to the class of decision problems that contains all problems H such that for all decision problems L in NP there is a polynomial-time many-one reduction to H. Informally this class may be described as containing the decision problems that are at least as hard as any problem in NP. This intuition may be supported by the fact that if we can find an algorithm A that solves one of these problems H in polynomial time, then we may construct a polynomial time algorithm for every problem in NP by first executing the reduction from this problem to H and then executing the algorithm A.
Therefore, it would be desirable to provide a method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description.
USPTO Backgrounds
USPTO Backgrounds