An attempt to decrease the operating voltage, the power consumption, the area, or the like of an SRAM (Static Random Access Memory) included in a semiconductor device is made. For example, a technique for decreasing ON-state threshold voltage by using a DT (Dynamic Threshold voltage) MOS transistor in which a gate electrode and a well region (body) are short-circuited as a determined MOS (Metal Oxide Semiconductor) transistor included in an SRAM cell is known. Furthermore, for example, a technique for controlling threshold voltage by applying a bias to a body on the basis of a bit line signal or by applying potential corresponding to stored data as a substrate bias is known.
Japanese Laid-open Patent Publication No. 2009-110594
Japanese Laid-open Patent Publication No. 2002-353340
Japanese Laid-open Patent Publication No. 2000-114399
IEEE TRANSACTIONS ON ELECTRON DEVICE, Vol. 55, No. 1, pp. 365-371 (January 2008)
IEEE International Electron Devices Meeting 1994, pp. 809-812 (1994)
If the above DTMOS is adopted in an SRAM, then a process for fabricating the SRAM in which the DTMOS is adopted and a semiconductor device including the SRAM may become complex, the costs may rise, and so on. Furthermore, to control threshold voltage for the purpose of decreasing voltage or power consumption by applying determined potential to a well region (body) may make it impossible to, for example, decrease the area of an SRAM cell, depending on circuit structure.
USPTO Backgrounds
USPTO Backgrounds