1. Field of the Invention
The present invention relates to a differential amplifier device, a 2-stage amplifier device, and an analog/digital converter device.
2. Description of Related Art
Recent years, an analog/digital converter device for converting an analog signal to a digital signal has been wildly adopted along with the progress of digital devices.
In this analog/digital converter device, an analog signal is converted to a digital signal by comparing an inputted analog signal with plural steps of reference voltages, so that a plurality of amplifier devices are employed.
Accordingly in the analog/digital converter device, it is considered to use amplifier devices having good quality, and particularly, a 2-stage amplifier device having offset compressing function is employed in order to reduce an offset voltage which is important as a quality of an amplifier device.
This 2-stage amplifier device is configured by connecting a variable gain differential amplifier device to a fixed gain differential amplifier device in series, and is set to apparently reduce the offset voltage of the differential amplifier device in the previous stage by increasing or decreasing the gain of the differential amplifier device in the subsequent stage.
There has been proposed a differential amplifier device such as disclosed in FIG. 16 as a differential amplifier device 101 employed in the subsequent stage, in which a load circuit 103 is connected to a differential amplifier circuit 102, and a change-over switch 104 is connected to the load circuit 103, and it becomes able to perform increasing or decreasing of the gain of the differential amplifier circuit 102 by switching between the full load where a whole of the load circuit 103 is set to be the load of the differential amplifier circuit 102 and the partial load where a part of the load circuit 103 is set to be the load of the differential amplifier circuit 102 with the change-over switch 104.
In the differential amplifier device 101, the differential amplifier circuit 102 is configured by differentially connecting P-channel type transistors T102, T103 to a P-channel type transistor T101, and further the load circuit 103 is configured with N-channel type transistors T104, T105 connected to the differential amplifier circuit 102. In addition, switching transistors T106, T107 are connected between a drain terminal and a gate terminal of the N-channel type transistors T104, T105 configuring the load circuit 103 as a change-over switch 104. Further, each of condensers C1, C2 is connected between gate terminals of the transistors T104, T105 and the ground GND, respectively.
When the switching transistors T106, T107 are set to an off state, a whole of the load circuit 103 becomes a load (full load) in the differential amplifier device 101. In this case, the load circuit 103 becomes a current source type load by the transistors T104, T105, and increases an output impedance, so that the gain of the differential amplifier device 101 also increases. On the contrary, when the switching transistors T106, T107 are set to an on state, a part of the load circuit 103 becomes a load (partial load) in the differential amplifier device 101. In this case, the load circuit 103 becomes a diode-type load by the transistors T104, T105, and decreases an output impedance, so that the gain of the differential amplifier device 101 also decreases.
Further if the offset voltage of the amplifier circuit connected to the previous stage side of the differential amplifier device 101 is Vos, the gain in the partial load is Gr, the gain in the full load is Gc, and the input voltage is Vin, then the output voltage Vout in the partial load is designated as Vout=Gr×Vos, and the output voltage Vout in the full load is designated as Vout=Gc×Vin, so that when it is changed from the partial load to the full load, an equation Gr×Vos=Gc×Vin is establised, and accordingly, the input voltage Vin is to be designated as Vin=Vos×Gr/Gc.
That is, in the 2-stage amplifier device employing differential amplifier device 101 as described above, the offset voltage is compressed by Gr/Gc, and the input conversion offset is to be designated as Vos×Gr/Gc.
In this case, a trans-conductance of the transistors T102, T103 configuring the differential amplifier circuit 102 is gm1, a trans-conductance of the transistors T104, T105 configuring the load circuit 103 is gm2, a load capacitance is C, and an operation time is t, then the gain Gr in the partial load is designated as Gr=gm1/gm2, and the gain Gcin the full load is designated as Gc=gm1/C×t, so that the input conversion offset is to be designated as Vin=Vos×C/(gm2×t).
Accordingly, in the differential amplifier device 101 having above-mentioned configuration, in order to further reduce the input conversion offset, it is only necessary to make the load capacitance C smaller, or to make the trans-conductance gm2 and the operation time t of the transistors T104, T105 larger.
Patent Document: Japanese Laid-Open Patent Application OPH3-70382
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