Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
A flash memory is a type of memory that can be erased and reprogrammed in blocks instead of one byte at a time. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. Each of the cells can be electrically programmed on a random basis by charging the floating gate. The data in a cell is determined by the presence or absence of the charge in the floating gate. The charge can be removed from the floating gate by a block erase operation.
FIG. 1 illustrates a simplified cross-sectional view of a typical flash memory device substrate. The substrate 100 is comprised of p-type silicon in which a plurality of n-wells 103, 104 are formed. A deep n-layer 101, in conjunction with the n-wells 103, 104, can produce an isolated p region 105 in which n-channel memory cells can be formed. For example, n+ source lines 106-109 are illustrated in FIG. 1.
This large p area 105 has a large capacitance, typically on the order of 5 to 10 nF, depending on the size of the memory device. During an erase operation, this capacitance has to be charged to 20V and back to 0V many times with verify operations performed in between the charge and discharge cycles. This requires a relatively large amount of current and time.
In addition to the large capacitance problem, memory devices can also experience an erase disturb condition that may eventually limit the number of times that a cell can be erased. Since all of the memory blocks of an array share the same substrate, unselected memory blocks also experience the 20V on their substrate during an erase operation. The unselected word lines are typically left floating during the erase operation such that coupling from the substrate causes these word lines to charge up to a high state. This can create a potential disturb condition. In a substantially similar way, the memory blocks can experience a program disturb condition in the memory substrate of FIG. 1.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device that requires reduced current for memory operations and experiences reduced disturb conditions.
USPTO Backgrounds
USPTO Backgrounds