Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFET or MOS), in which a gate is energized to create an electric field in an underlying channel region of a semiconductor body, by which electrons are allowed to travel through the channel between a source region and a drain region of the semiconductor body. Complementary MOS (CMOS) devices have become widely used in the semiconductor industry, wherein both n-channel and p-channel (NMOS and PMOS) transistors are used to fabricate logic and other circuitry.
The source and drain are typically formed by adding dopants to targeted regions of a semiconductor body on either side of the channel. A gate structure is formed above the channel, having a gate dielectric formed over the channel and a gate electrode above the gate dielectric. The gate dielectric is an insulator material, which prevents large currents from flowing into the channel when a voltage is applied to the gate electrode, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. Conventional MOS transistors typically include a gate dielectric formed by depositing or growing silicon dioxide (SiO2) over a silicon wafer surface, with doped polysilicon formed over the SiO2 to act as the gate electrode.
Continuing trends in semiconductor device manufacturing include reduction in electrical device feature sizes (scaling), as well as improvements in device performance in terms of device switching speed and power consumption. As transistor devices are scaled to reduce the dimensions, a number of problems have been presented. For example, use of a very thin gate dielectric causes high gate current leakage, which reduces device performance. Additionally, as a transistor device is scaled, a higher doping level is required in channel regions to mitigate short channel effects. In turn, such a high doping level decreases drive current and can yield undesired drain to channel tunneling current.
Currently, polysilicon gate structures are commonly employed in transistor devices because such devices have a fixed work function defined by a level of doping of a particular species or type. For example, an n-type transistor wherein the gate, source, and drain are doped with n-type dopant results in a work function of approximately 4.1 eV. As another example, a p-type transistor wherein the gate, source, and drain are doped with boron results in a work function of about 5.1 eV. The work function for transistor devices with polysilicon gate structures can be at least partly adjusted and/or selected by controlling the dopant levels within the gate. For example, decreasing the dopant levels for an n-type transistor device with a polysilicon gate increases the work function whereas decreasing the dopant levels for a p-type transistor device with a polysilicon gate decreases the work function. However, the use of polysilicon as a gate material also introduces problems. For example, polysilicon gate structures tend to suffer from polysilicon depletion and/or boron penetration effects, thereby degrading transistor device performance.
Metal gate structures can be employed in place of polysilicon in order to overcome or mitigate the problems associated with using polysilicon as a gate material. Metal gate structures do not suffer from polysilicon depletion and/or boron penetration effects. However, the work functions for metal gate structures are generally not as easily tuned as with polysilicon gate structures.
USPTO Backgrounds
USPTO Backgrounds