1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a dynamic semiconductor memory device having information stored in the form of charges in a capacitor.
2. Description of the Background Art
A system LSI (Large-Scale Integrated circuit) is an integrated circuit device in which a logic and a memory are integrated on a single die (chip) to form a system. In the system LSI, memories such as an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a flash EEPROM (Electrically Erasable Programmable ROM) are used according to application purposes.
Since an SRAM statically operates and therefore operates at high speed, it is generally used for high speed processing.
In a DRAM, a memory cell is constructed by one transistor and one capacitor, so that the layout area of a memory cell is small. The DRAM is therefore generally used for a large storage capacity application.
A flash EEPROM can store information in a nonvolatile manner and is generally used in an application requiring to store information even when the power is shut down.
In an SRAM, a memory cell is constructed by a flip flop. When a power voltage is lowered for lower power consumption and higher processing speed, the threshold voltage of an MOS transistor (insulated gate field effect transistor) used for a memory cell has to be lowered in absolute value, so that a sub-threshold leak current increases. Consequently, a leak current in a standby mode becomes large, and the specification condition of a small current consumption in the standby mode, which is required for a portable equipment or the like cannot be satisfied.
In a DRAM, operating conditions required for a memory array section and those for a peripheral circuit section are different from each other. Usually, the level of a power source voltage in the memory array section and that in the peripheral circuit section are different from each other. The memory array section requires voltages of different levels, such as a power source voltage (sense power source voltage) supplied to a sense amplifier for sensing and amplifying memory cell data, a negative substrate bias voltage for biasing the substrate region of a memory array, a high voltage transmitted onto a selected word line to prevent a loss by a threshold voltage of an access transistor, and an intermediate voltage for precharging a bit line. The voltages of different levels have to be internally generated, so that the current is additionally consumed to generate those internal voltages. A problem of large current consumption arises. For example, in the case of generating a high voltage through a charge pumping operation, the pump efficiency is lower than 1. In order to generate a high voltage of a necessary level, a current larger than a current consumed by a circuit using the high voltage has to be consumed to generate the high voltage.
Besides, the DRAM has to perform a refreshing operation of periodically restoring stored data. In the standby mode in a portable equipment or the like requiring ultra-low current consumption, therefore, a refresh current is consumed, and the specification of the ultra-low current consumption cannot be satisfied.
There is a problem such that current consumption in the DRAM is large, and a specification value of a low current consumption required for a portable equipment or the like cannot be sufficiently achieved.
An object of the present invention is to provide a semiconductor memory device achieving low current consumption in a standby mode without exerting an adverse influence on access operation.
Another object of the present invention is to provide a semiconductor memory device consuming a small current in the standby mode, suited for a system LSI.
A semiconductor memory device according to the invention includes: a plurality of memory cells arranged in a matrix of rows and columns; a plurality of bit lines, arranged in correspondence to the columns of the memory cells, each having the memory cells in a corresponding column connected; a plurality of word lines, arranged in correspondence to rows of the memory cells, each having the memory cells in a corresponding row connected; a plurality of first sense amplifiers each disposed in correspondence to a set of a predetermined number of bit lines, for sensing and amplifying data of the memory cells in the corresponding column when activated; a plurality of first transfer gates each disposed in correspondence to each of the bit lines, for connecting a corresponding bit line and the first sense amplifier when made conductive; and connection control circuitry for selectively making the plurality of first transfer gates conductive in response to an operation mode instruction signal.
By switching connection between a bit line and a sense amplifier according to an operation mode, the data storing form can be switch between a one-bit-per-cell (1 bit/cell) mode and a one-bit-per-two-cells (1 bit/2 cells) mode. In the case of storing data in the one-bit-per-cell mode, the device can operate in a manner similar to a normal DRAM. In the case of the one-bit-per-two-cells mode, complementary data is read onto a pair of bit lines. Consequently, a read voltage sensed and amplified by a sense amplifier is made large. Even when charges flow out from a memory cell capacitor due to a leak current, data can be satisfactory sensed and amplified, and a refresh interval can be made longer. Therefore, by using the one-bit-per-two-cells mode in the standby mode, the current amount consumed for the refreshing operation in the standby mode can be reduced. Thus, the current in the standby mode can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds