1. Field of the Invention
The present invention relates to the visual display of a computer graphics image and, in particular, to a graphics display system that integrates both a graphics accelerator engine and a portion of the graphics frame buffer memory on the same monolithic chip.
2. Discussion of the Prior Art
A video graphics system typically uses either VRAM or DRAM frame buffers to store the pixel display data utilized in displaying a graphics or video image an a display element such as a CRT.
A VRAM frame buffer includes two ports that are available for the pixel data to flow from the memory to the display. One port is known as the serial port and is totally dedicated to refreshing the display screen image. The other port is a random access port that is used for receiving pixel updates generated by a CPU or a graphics accelerator engine. A typical VRAM arrangement allocates 99% of the available bandwidth to the random port thereby allowing the system to display fast moving objects and to support large display CRTs.
However, in a DRAM-based video system, the pixel data updates and the screen refresh data contend for a single frame buffer memory port. This contention reduces the amount of bandwidth available for pixel data updates by the CPU and the graphics engine, resulting in a lower performance graphics display system.
However, in most applications the DRAM solution is preferable to the VRAM solution at the expense of lower performance, because DRAMs are cheaper than VRAMs.
FIG. 1 shows a conventional graphics display system 10 wherein a CPU 12 writes pixel display data on data bus 11 to be displayed on the CRT screen 14 through a graphics accelerator (GXX) 16 onto a DRAM frame buffer 18 via data bus 19. The CPU 12 also provides certain higher level graphics command signals 20 to the graphics accelerator 16 to manipulate the display data stored in the DRAM frame buffer 18.
The graphics accelerator 16 retrieves display data from the frame buffer 18 via data bus 19 utilizing reference address bus 21, processes the retrieved display data based on the CPU command signals 20 and writes the new pixel data back to the frame buffer 18.
The pixel data is displayed on the CRT 14 through a random access memory digital-to-analog converter (RAMDAC) 22 that receives the data via a data display bus 24.
The graphics accelerator 16 also constantly reads display data from the frame buffer 18 via data bus 19 and sends it to the RAMDAC 22 via the data display bus 24 to meet the refresh requirements of the CRT display 14.
Thus, as illustrated in FIG. 1, the bandwidth of the data bus 19 is shared by three functions: display refresh, CPU display data update, and graphics accelerator display manipulation. As the display size (i.e., the number of pixels to be displayed on the CRT screen 14) increases, the display updates and display manipulation functions are reduced because of the bandwidth limitations of the data bus 19 caused by the fixed refresh requirements of the CRT 14.
While these limitations can be addressed by increasing the data bus width or by increasing its speed, both of these solutions have either physical or practical limitations. Increasing the bus width increases the silicon area and the package pin count. Increasing the speed of the bus requires utilization of more complex silicon process technology.
USPTO Backgrounds
USPTO Backgrounds