1. Field of the Invention
The present invention relates to a gate driving circuit, and more particularly, to a high-reliability gate driving circuit having alternating and auxiliary pull-down mechanisms.
2. Description of the Prior Art
Because the liquid crystal display (LCD) has advantages of thin appearance, low power consumption, and low radiation, the liquid crystal display has been widely applied in various electronic products for panel displaying. The operation of a liquid crystal display is featured by varying voltage drops between opposite sides of a liquid crystal layer for twisting the angles of the liquid crystal molecules in the liquid crystal layer so that the transmittance of the liquid crystal layer can be controlled for illustrating images with the aid of the light source provided by a backlight module.
In general, the liquid crystal display comprises a plurality of pixel units, a gate driving circuit, and a source driving circuit. The source driving circuit is utilized for providing a plurality of data signals to be written into the pixel units. The gate driving circuit comprises a plurality of shift register stages and functions to provide a plurality of gate driving signals for controlling the operations of writing the data signals into the pixel units. That is, the gate driving circuit is a crucial device for providing a control of writing the data signals into the pixel units.
FIG. 1 is a schematic diagram showing a prior-art gate driving circuit. As shown in FIG. 1, the gate driving circuit 100 comprises a first shift register module 105 and a second shift register module 106. The first shift register module 105 includes a plurality of odd shift register stages and the second shift register module 106 includes a plurality of even shift register stages. For ease of explanation, the first shift register module 105 illustrates only an Nth shift register stage 181 and an (N+2)th shift register stage 183; and the second shift register module 106 illustrates only an (N+1)th shift register stage 182 and an (N+3)th shift register stage 184. The number N is a positive odd integer. The odd shift register stages are employed to generate a plurality of gate signals furnished to the odd gate lines of a pixel array 101 according to a first clock CK1 and a second clock CK2 having a phase opposite to the first clock CK1. The even shift register stages are employed to generate a plurality of gate signals furnished to the even gate lines of the pixel array 101 according to a third clock CK3 and a fourth clock CK4 having a phase opposite to the third clock CK3.
For instance, the Nth shift register stage 181 is put in use for generating a gate signal SGn based on the first clock CK1 and the second clock CK2. The gate signal SGn is then furnished to an odd gate line GLn of the pixel array 101 for providing a control of writing the data signal delivered by a data line DLi into a corresponding pixel unit 103. However, in the operation of the gate driving circuit 100, except for the interval during which the Nth shift register stage 181 is activated for generating the gate signal SGn having high voltage level, the gate signal SGn of the gate line GLn is required to be pulled down to low voltage level. That is, the gate signal SGn is held at low voltage level in most of operating time. According to the architecture of the gate driving circuit 100, the circuit operation for pulling down the gate signal SGn of the gate line GLn is carried out only through the pull-down unit 191 of the Nth shift register stage 181. For that reason, if the channel lengths of transistors therein are devised to be substantially fixed, the channel width of a transistor 192 used in the pull-down unit 191 is demanded to be wide enough for efficiently pulling down the gate signal SGn of the Gate line GLn. Nevertheless, as the channel width of the transistor 192 is wider, it is likely to incur an occurrence of greater threshold voltage drift and degrade the reliability and lifetime of the gate driving circuit 100.
USPTO Backgrounds
USPTO Backgrounds