1. Field of the Invention
The present invention relates to an inverter for high voltage full swing output, and more particularly, to an inverter circuit which generates a full swing output in the range of zero volt (ground voltage) to a value of a high voltage source.
2. Discussion of the Related Art
As shown in FIG. 1, a high voltage inverter of related art includes a first super transistor SP and a second super transistor SN. The first super transistor SP consists of PMOS transistors P1 and P2. The second super transistor SN consists of NMOS transistors N1 and N2. The high voltage inverter is connected between a high voltage source HVDD and ground voltage GND (which is normally zero), and is operated by the high voltage source HVDD and a shield voltage source VSHLD (VSHLD=HVDD/2). The high voltage inverter received an input voltage HVin and generates an output voltage HVout.
More specifically, the inverter includes a PMOS P2 connecting Vp (see FIG. 1) and HVDD to its drain terminal and bulk terminal, respectively. A PMOS P3 connects Vp, HVout, and Vp to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N2 connects GND, Vn, and GND to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N3 connects Vn, HVout, and Vn to its source terminal, drain terminal, and bulk terminal, respectively. A PMOS P1 connects HVin, a gate input of the PMOS P2, and the same gate input of the PMOS P2 to its source terminal, drain terminal, and bulk terminal, respectively. An NMOS N1 connects HVin, a gate input of the NMOS N2, and the same gate input of the NMOS N2 to its source terminal, drain terminal and bulk terminal, wherein gates of the PMOS P1 and P3, and NMOS N3 and N1 are connected to VSHLD. The structure formed of P1 and P2 with drain of the P1 connected to gate input of the P2 consists the first super transistor SP, while the structure formed of N1 and N2 with drain of the N1 connected to gate input of the N2 consists the second super transistor SN.
In the high voltage inverter described above, the shield voltage source VSHLD has to be supplied with a voltage of 3.3 V when a voltage of 6.6 V is applied to the high voltage source HVDD. Once a high voltage of 6.6 V is applied to HVin, the P1 with its gate terminal connected to VSHLD becomes turned on while the N1 becomes turned off. Thus, drain terminal of the P1 is supplied with 6.6 V and source terminal of the N1 is supplied with 3.3 V-Vtn (where Vtn is a threshold voltage of n-type MOS transistor), turning off the P2 and P3 and turning on the N2 and N3. Therefore, 0 V is ouputted from the output terminal.
In this case, although a high voltage of 6.6 V is applied between the high voltage source and output terminal, each transistor operates within a low voltage level as the voltage of Vp is biased to 3.3+Vtp (where Vtp is a threshold voltage of p-type MOS transistor) by the shield voltage source VSHLD.
Otherwise, when 0 V is applied to the HVin, the P1 with its gate terminal connected to VSHLD becomes turned off while the N1 becomes turned on. Thus, a high voltage of 6.6 V is outputted from the output terminal by turning on the P2 and P3 but turning off the N2 and N3. In addition, the voltage of the drain terminal of the P1 and the voltage of Vn are biased to low voltage level by the shield voltage source VSHLD.
As a result, each of the transistors operates stably within the low voltage level due to the super transistors SP and SN and the shield voltage source VSHLD and enables a full-swing output between the high voltage source HVDD and ground GND.
However, the high voltage inverter of the related art as described above has the following disadvantages. The voltage level of the high voltage source (HVDD) of the inverter circuit can only be extended two times as high as the limit bias voltage of low voltage transistors used in the inverter circuit.
USPTO Backgrounds
USPTO Backgrounds