1. Field of the Invention
The present invention relates generally to techniques for improving power distribution for electrical and electronic devices, and more particularly relates to techniques for distributing power for use by high speed integrated circuit devices.
2. Background Art
As frequencies in high speed electronic devices increase, it becomes more challenging to provide effective power supply decoupling. Integrated circuit devices (ICs) require high frequency current for their operation. The current requirements for such IC devices must be identified to properly assess the decoupling and power distribution requirements.
High speed ICs are typically mounted on printed circuit boards (PCBs). Sufficient current must be distributed to the devices within required switching times, while maintaining a relatively constant input supply voltage. To achieve this, discrete capacitors are often placed near the devices. These capacitors are connected between the voltage and ground planes of a carrier such as a printed circuit board to provide the necessary charge current to the devices. Decoupling capacitors release charge to the device at a rate that is proportional to the device's switching frequency. As device switching frequency increases, the window of time between switching events decreases. For this reason, the circuit designer must minimize the distance or time that it takes the charge to travel between the decoupling capacitor and the device. This is accomplished by placing decoupling capacitors as close to the device power pins as possible. Decoupling capacitors must recharge from energy stored in slower discharging capacitors and power supplies prior to the next required discharge. At high frequencies, power-ground planes, ceramic decoupling capacitors and bulk decoupling capacitors are often used in combination.
For the circuit designer, providing high speed devices with adequate current in the time required becomes more challenging as switching speeds increase. This is usually accomplished by mounting the capacitors on the opposite side of the board, next to the vias which connect to the device power pins. There are several circumstances, however, that eliminate this option. For example, ball grid array (BGA) devices have ever-increasing pin-counts and decreasing ball pitches. This combination translates into very dense via fields on the underside of the card, leaving little or no room for decoupling capacitors. Consequently, too few capacitors are used to provide adequate current to all the power pins or the capacitors are placed too far away from the power pins to effectively provide current to the device. Another situation that eliminates the possibility of mounting decoupling capacitors on the opposite side of the card is when blind vias are used to connect the device to power and ground planes. Since blind vias do not penetrate all the way through the board, there are no vias on the other side to pair up with decoupling capacitors. In this situation, the designer is forced to place the decoupling capacitors around the perimeter of the part on the same side of the board. The distance between power pin and capacitor is further increased by a manufacturing keep-out area, which prevents the designer from placing capacitors adjacent to the device in order to provide a physical space or area for re-work.
These examples demonstrate the physical constraints that increase the distance a charge must propagate between a decoupling capacitor and an associated IC power pin. However, the material structure of the PCB determines the velocity at which charge propagates between a decoupling capacitor and an associated IC power pin. The velocity of propagation, Vp, is defined as the speed of light, c, divided by the square root of the dielectric constant, Er.
      v    p    =      c                  ɛ        τ            
As Er is reduced, the velocity of propagation increases. Therefore, if the dielectric constant of the core material between power and ground layers of the PCB is minimized, the time required for charge to propagate from decoupling capacitors to power pins will be minimized. Thus, decoupling capacitors can be further away from the IC and still provide effective decoupling. However, there is a price for achieving higher propagation velocities. As the dielectric constant of the material between power and ground planes is decreased, the effective radius from which a given power pin is able to draw current is increased. In other words, electrical perturbations generated by IC switching are able to propagate further distances on the PCB. Consequently, decoupling capacitors meant to provide power to one IC may also provide power to several other nearby ICs. This overlap in decoupling regions results in higher noise levels in the power being provided to each IC. A new PCB structure is needed that will enable current to reach ICs in shorter time periods, while isolating high-speed switching noise to individual IC decoupling regions
USPTO Backgrounds
USPTO Backgrounds