This invention relates to power semiconductor devices, particularly but not exclusively a power semiconductor switch, having a main current carrying transistor section and a sense current carrying transistor section.
The invention also relates to circuit configurations comprised with such a device. The circuit may be used for measuring or modifying or controlling the conduction of the main current carrying section of the device, in relation to an output from the sense current carrying section.
The invention further relates to switching circuits, switching arrangements and switching schemes comprising such a semiconductor device and/or control circuit, particularly but not exclusively as a low-side switch.
The device is typically an insulated-gate field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT). The device is usually cellular with, for example a close-packed hexagonal, or square or stripe geometry, and so the main current carrying section and the sense current carrying section are generally referred to in terms of main cells and sense cells. The control circuit may be integrated monolithically in the same device body (chip) as the transistor, or it may be in a separate circuit body (IC chip) mounted beside the transistor chip, for example in the same device package (encapsulation).
Power MOSFET devices with monolithically integrated control circuits are known. Thus, such devices commercially available from Philips Semiconductors under the trade mark TOPFET include temperature and overload protection functions. TOPFET devices are designed for either high-side or low-side operation, depending on whether used between a power line and the load or the ground line and the load. Such devices are described in the Philips Semiconductors Power MOS Transistors Data Handbook 1997, for example, and on the web-site http://www.semiconductors.philips.com.
In low-side configured MOSFET designs, current limit and current measure functions have difficulty performing well because of the poor tracking between the MOSFET cells that perform the sensing function (sense cells) and the majority of the MOSFET cells (main cells) that are not monitored. This results from the connection of a small measurement resistor to the source of the sense cells, which thereby makes the sense cells non-representative of the main population.
In high side technologies this problem can be resolved by feeding the sense cells into a xe2x80x9cvirtual earthxe2x80x9d node, and hence reducing the difference in source voltages between sense cells and non-sensing main cells of the MOSFET. However, the use of a virtual earth technique in a fast current limit control application is particularly challenging from a stability standpoint.
A virtual earth solution cannot be implemented for low-side MOSFET devices, because there is no means to sink the significant sense current, below source potential. The only strategy believed to be available in low-side technology was to reduce the magnitude of the signal developed across the sense resistor.
U.S. Pat. No. 5,621,601 discloses apparatus designed to prevent the oscillation which often occurs in an over-current protection apparatus for an insulated gate controlled transistor. The apparatus improves the response in current detection, to prevent oscillation, and improves protection speed against over-current. This is accomplished by separating the gates of the main transistor and the current detector transistor, by setting a shorter time constant for the gate circuit of the current detector transistor than that of the gate circuit of the main transistor; by feeding the detection signal obtained from a current detecting resistor which detects the current of the current detector transistor to a control circuit; and by controlling the gate potentials of both transistors to protect the main transistor from the over-current by feeding the comparison output from a comparator circuit, which compares the voltage of the detection signal with a reference voltage, to the control circuit.
One disadvantage of the apparatus disclosed in U.S. Pat. No. 5,621,601 is that it does not take account of the drive impedance presented by the drive circuit acting on the main transistor. For slow switching time devices where the real value of the gate resistor for the main transistor is high compared to the source impedance that can be released in the drive circuit, this arrangement will produce a useful benefit in stability; but for fast switching time devices where this is not the case, the stability advantages will be limited.
However, more important in relation to the present invention is that the disclosure of U.S. Pat. No. 5,621,601 in no way addresses the problem that as a result of connection of the current detecting resistor (the measurement resistor) to the current detector transistor (the sense cells), this detector transistor is not fully representative of the main transistor (the main cells).
According to the present invention there is provided a power semiconductor device having a main current carrying transistor section integrated with a sense current carrying transistor section for carrying a current which is smaller than and indicative of the current carried by the main current carrying section, wherein the main transistor section and the sense transistor section have a common first main electrode connected to a first main terminal of the device, wherein the main transistor section and the sense transistor section have separate second main electrodes with the second main electrode of the main transistor section connected to a second main terminal of the device and the second main electrode of the sense transistor section connected through a current sensing resistance to said second main terminal of the device, wherein the main transistor section and the sense transistor section have separate control electrodes, wherein control means includes comparison means for comparing a reference voltage defining a current limit value with the voltage across the current sensing resistance and providing a first control signal, wherein the first control signal is coupled to the control electrode of the sense transistor section, and wherein the first control signal is coupled to further control means which provides a second control signal coupled to the control electrode of the main transistor section. In accordance with the present invention, such a device is characterised in that the further control means comprises adjustment circuit means coupled to the first control signal and to the voltage across the current sensing resistance and arranged to provide the second control signal such that the second control signal is effective to maintain the voltage between the control electrode and the second main electrode of the main transistor section equal to the voltage between the control electrode and the second main electrode of the sense transistor section.
The characterising features of the present invention, as defined above, provide correction of the drive to the control electrode of the main transistor section for the reduction in drive voltage applied to the sense transistor section as a result of the current sensing resistance.
Thus, the control electrode of the sense transistor section is connected to the control means so as to define the voltage on this control electrode such that the current in the sense transistor section never exceeds the intended maximum value, and the maximum voltage applied to the sense transistor section control electrode is defined, this nodal connection being the first control signal. The control means compares the reference voltage (defining an intended current limit) with the voltage across the current sensing resistance and so controls the voltage across the current sensing resistance such that it never exceeds the reference voltage. The control means also defines the maximum voltage that is to be applied to the control electrode of the sense transistor section when the external condition applied between the two main electrodes of the device defines the current that is flowing. The adjustment circuit means of the further control means compares the first control signal voltage (the voltage on the control electrode of the sense transistor section) with the voltage on the second main electrode of the sense transistor section to produce the second control signal substantially equal to the voltage that actually appears between the control electrode and second main electrode of the sense transistor section but referenced to the second main electrode of the main current transistor section. It should be noted that this referencing connection relies on a physical connection between the second electrode of the main transistor section and the end of the current sensing resistance that is connected to the second main terminal of the device. This physical connection is apparent in the above definition of the present invention.
In a first, preferred, arrangement according to the present invention the second control signal provided by the adjustment circuit means is connected indirectly to the control electrode of the main transistor section as a third control signal via a buffer driver circuit. An advantage of this preferred arrangement is that a primary, critical, control loop including the comparison means, the sense transistor section and the current sensing resistance is completely isolated from design compromises which would be caused if it had to drive the large inter-electrode capacitances of the main transistor section.
In this preferred arrangement, the buffer driver circuit may include an operational amplifier, a non-inverting input of this operational amplifier being connected to the second control signal voltage, and an inverting input of this operational amplifier being connected to its output and to the control electrode of the main transistor section, and the comparison means may include an operational amplifier, a non-inverting input of this operational amplifier being connected to the current limit defining reference voltage, an inverting input of this operational amplifier being connected to the second main electrode of the sense transistor section, and the output of this operational amplifier being connected to the control electrode of the sense transistor section.
In this preferred arrangement, the adjustment circuit means is a first functional block which operates as a corrected reference voltage generator, this corrected reference voltage, with respect to the main transistor section second main terminal (source terminal for a MOSFET) being substantially equal to the actual voltage that appears between the control electrode and second main terminal (gate and source connections for a MOSFET) of the sense transistor section and will be valid either when the device current is being controlled by the potential across the device or when the device is actually limiting the current. This corrected reference voltage (the second control signal) is then utilized by the buffer driver circuit acting as a second, high-speed, functional block to drive the main transistor section. Separate driving of the control electrodes (gates) of the main and sense transistor sections has the advantage that it alters the drive requirements for the separate, primary, more critical control loop circuit including the sense transistor section, and makes the engineering of a stable current limit circuit a lot simpler. Thus, the preferred arrangement is particularly suitable for use in precision current limit and current measure functions.
In this preferred arrangement, the adjustment circuit means may include an operational amplifier, first and second equal value resistors and a transistor, wherein a non-inverting input of this operational amplifier is connected to the voltage across the current sensing resistance, wherein one end of said first resistor is connected to the second main terminal of the device and the other end of said first resistor is connected to an inverting input of this operational amplifier and to a first main electrode of this transistor, wherein one end of said second resistor is connected to the first control signal voltage and the other end of said second resistor is connected to a second main electrode of this transistor which provides the second control signal, and wherein the output of this operational amplifier is connected to a control electrode of this transistor.
In a second, non-preferred, arrangement according to the present invention the adjustment circuit means is a differential amplifier circuit, and the second control signal is provided by the differential amplifier circuit and is connected directly to the control electrode of the main transistor section. The differential amplifier circuit may include an operational amplifier, wherein a non-inverting input of this operational amplifier is connected to a junction in a first resistive divider which is provided between the first control signal voltage and the second main terminal of the device, wherein an inverting input of this operational amplifier is connected to a junction in a second resistive divider which is provided between the output of this operational amplifier and the voltage across the current sensing resistance, and wherein the output of this operational amplifier provides the second control signal. The comparison means in this second, non-preferred, arrangement may include an operational amplifier, wherein a non-inverting input of this operational amplifier is connected to the current limit defining reference voltage, wherein an inverting input of this operational amplifier is connected to the voltage across the current sensing resistance, and wherein the output of this operational amplifier provides the first control signal.
Thus in this second, non-preferred, arrangement the two functional blocks (preferably using two operational amplifiers) of the further control means of the first, preferred, arrangement can be combined into one compound functional block (preferably using one operational amplifier in a differential amplifier configuration) but the performance will be inferior because the best circuit topology is not used for either function and the hybrid topology is compromised (for example by the limited common mode rejection ratio of such circuits). The simple differential correction can be of significance where an improved current measure precision is required but a sophisticated current limit facility is not implemented.
Thus, the present invention provides a novel device architecture that is suitable, inter alia, for use in precision current limit and current measure functions. The improvement offered by this circuit, in current measure applications, is that the operating conditions pertaining to the main transistor section are a closer approximation to those being seen by the sense transistor section and therefore the current flowing in the sense resistor is more representative of the current in the whole device. This novel device architecture is realisable using either single chip technologies, for example as in the TOPFET (Trade Mark) range of devices, or using multiple chip technologies, as in the SENSEFET range of devices. Such MOSFETs are particularly beneficial for use as low-side switches.
Before describing the details of embodiments of the present invention, it may be explained that the present invention is based on an approach by the inventor which recognizes two components to the xe2x80x9csense ratioxe2x80x9d error:
(1) The difference in gate source voltage between the group of sense cells and the cells in the main section of the power MOSFET produces a non-ideal share in response to the transfer function of the component MOSFET cells. This source of error is significant under most conditions.
(2) The non-ideal resistive divider created by the introduction of a small sensing resistor in the source connection of the sense cells also directly generates an error, because it is not matched by a corresponding resistance for the main section of the power MOSFET. This source of error is significant only when the FET is operating fully saturated with a low drain source voltage.
As regards cause (1), the difference in current densities between the sense cells and the main cells can become particularly pronounced at low current densities with the power device running at low levels of enhancement. This is the case when the device is being actively current limited, when the errors from cause (2) are negligible.
As regards cause (2), these errors tend to be worse in devices for xe2x80x9ccool runningxe2x80x9d applications where the drain source operating voltage is very low (i.e. neither fault nor current limiting conditions).
In accordance with the present invention, there is provided a novel approach that facilitates a correction for errors from (1) and that is applicable generally in control applications where the sense ratio error is a problem.
USPTO Backgrounds
USPTO Backgrounds