Nonvolatile semiconductor memories use a variety of semiconductor memory cell designs. One type of memory cell is a “flash” memory cell that is electrically erasable and electrically programmable. Flash memory cells may be programmed, erased or read by a user. Once programmed, flash memory cells retain their data until erased.
For many flash memory applications data integrity is vital. Users typically want to easily load data into a specific memory block and then to “lock” out that block such that its contents cannot be modified under normal operating conditions. Prior flash memory devices include memory blocks and a flash memory cell in each memory block stores a block “lock-bit” that if programmed indicates that the block of flash memory cells may not be altered (programmed or erased).
One disadvantage with this approach is that erasing the block lock-bit in one memory block may erase all of the data stored in that memory block. For example, if the flash memory cell storing the block lock-bit shares a common source line with the other flash memory cells in the memory block, then erasing the block lock-bit may erase the entire memory block. Thus, if a user wants to unlock a memory block to program or erase bits stored in the memory block, then the entire contents of the memory block are erased. The entire memory block is then programmed regardless of the number of bits that had to be changed. This may result in undesirable delay times to change a few bits of data in a previously locked memory block.
Another disadvantage with the prior approach is that a flash memory device having defective memory blocks may draw an undesirable amount of current. For example, when a memory block is determined to contain a defective flash memory cell, the block lock-bit may then be programmed to indicate that the memory block cannot be altered or accessed. That is, the block lock-bit may block out the use of the bad memory block and the flash memory device may continue to partially function using only good memory blocks. However, including the block lock-bit in a defective memory block requires the defective memory block to be powered in order to read the block lock-bit. This may result in an undesirable amount of power drawn by the defective memory block. Additionally, if a defect in a memory block also adversely affects the corresponding block lock-bit, then the flash memory device may not be partially usable.
Another prior approach described in U.S. Pat. No. 5,513,136 of Fandrich et al., stores block lock-bits in spare rows of memory. Each spare row corresponds to a memory block. One disadvantage with this approach is that each of the spare rows are treated as an extra row of its corresponding memory block. In other words, erasing a block lock-bit in a spare row erases all of the data stored in the corresponding memory block.
Another disadvantage of the approach described in U.S. Pat. No. 5,513,136 is that it generally does not support real-time user access to the block lock-bits in each memory block. For example, a user must write a command to the flash memory device that instructs the device to upload a lock-bit state into a corresponding status register. The user must then typically poll the device until the device indicates that the upload operation was complete. The user then issues another command to read the lock-bit information from the status register. The user then has to issue subsequent read commands to read the lock-bit status from each status register corresponding to each memory block. This process may take as long as five to ten microseconds (μS).
It may be desirable to lock the states of the lock-bits themselves. One prior approach described in U.S. Pat. No. 5,513,136 uses a voltage applied on an external pin (e.g., WP#) to control whether the block lock-bits may be altered. One disadvantage with this approach is that it requires adding an extra pin to the flash memory device.
USPTO Backgrounds
USPTO Backgrounds