A charge pump circuit generates a boosted voltage required when data is written into memory cells or erasing data from memory cells. This exemplary circuit is disclosed in JP-A-5-292734. This circuit uses an oscillation circuit so that, even when the supply voltage of a charge pump circuit fluctuates, the DC-DC conversion efficiency do not vary or the time it takes for the output voltage to reach a certain level of boosted voltage does not vary.
In a semiconductor device containing a charge pump circuit or memory cells, it is considerably possible that the leakage of a current occurs even in transistors connected externally of the charge pump circuit, memory cells or the like. When current leakage occurs, the time required for the output voltage of the charge pump circuit to rise to a certain boosted voltage can become longer than expected.
When the rise time to the boosted voltage becomes longer, for example, the time of boosted voltage application is shortened and data can be inadequately written at the time of writing data into memory cells. Such a memory IC is inevitably determined defective.
One of possible countermeasures for coping with such a problem is to proactively set the boosted voltage to be a little higher than normal. However, when the boosted voltage is set to be a little higher, the withstand voltage of transistors must be accordingly set to be a little higher. With respect to supply voltage fluctuation the in charge pump circuit, this is effective and can suppress its influence. However, this means cannot cope at all with cases where current leakage occurs in components external to the charge pump circuit.
USPTO Backgrounds
USPTO Backgrounds