The present invention relates generally to integrated circuit (IC) designs, and more particularly to a capacitor device with a metal-insulator-metal (MIM) capacitor region, metal-oxide-metal (MOM) capacitor region, or varactor region vertically arranged on the same layout area.
The construction of passive electronic circuit elements, such as capacitors, on an IC can be tedious, time consuming, and costly. It is therefore important to assemble such IC elements using the processes, materials, and designs that are relevant to the technology and that are already in production.
Capacitors occur naturally, whether intended, or not. Such capacitors can be useful. Active IC elements, such as bipolar and metal-oxide-semiconductor (MOS) transistors, and some resistors contain electrical junctions with capacitance. A depletion region of an electrical junction is, by nature, a small parallel plate capacitor. That capacitor can be used as a fixed-value capacitor, or it can be used as a variable capacitor, since its value changes as the voltage applied to the junction changes. Passive IC elements, such as polycrystalline silicon (polysilicon) and metal lines, have inherent capacitance, with respect to each other and to any other conductors.
The effort of a designer can be to use available characteristics of IC elements. The difficulty with such effort is that the resulting structures exhibit capacitance values only on the order of femtofarads/micron squared. Achieving functional capacitance values in an IC element requires structures that typically are much larger than the active elements, especially when used in mixed signal and/or radio frequency (RF) circuits. This imbalance is uneconomical, since it forces the circuit designer to dedicated space for capacitors and produce IC chips that are too large. The designer can choose among several structural types of capacitors, but no one type offers a convenient balance of performance and space economy.
In one example, the voltage-variable capacitance of an electrical junction can be applied in the construction of a variable capacitor, or a varactor. In another example, the dual-damascene techniques typically used with copper multilevel interconnection metallization on ICs can be used to construct stacks of copper-filled vias and trenches. Two or more such copper-filled vias or trenches, separated by oxide dielectrics, form a capacitor, which is called a MOM capacitor. This MOM capacitor requires a complex design, but the form is efficient and the process steps required are usually already involved in the a standard semiconductor device fabrication process. In yet another example, simple horizontal parallel plates of metal, separated by dielectrics, form a capacitor, which is called a MIM capacitor. The horizontal form of this MIM capacitor occupies relatively more lateral layout space, but is simple to construct.
Since a single type of capacitor does not always provide sufficient capacitance per unit, it is desirable in the art of integrated circuit designs that additional devices are provided to combine various types of capacitors in the same layout area for increasing the capacitance per unit of the same.
USPTO Backgrounds
USPTO Backgrounds