As complex electronic systems develop towards to microminiaturization, high integration and multifunction, the SoC has been created and widely applied in the fields of aviation and aerospace, rail transportation, nuclear power and other technical fields requiring high reliability. However, as the feature size of semiconductor devices is constantly scaling down, the thickness of the gate oxide is continually thinned, whereas the supply voltage should not be reduced, so the gate oxide reliability of transistors in the SoC under high electric intensity has become a prominent problem. The degradation of the gate oxide will cause a threshold voltage shift, a decrease in transconductance, and an increase in leakage current, which may further cause a failure caused by breakdown of the gate oxide, is the so-called time dependent dielectric breakdown (TDDB) failure. Therefore, it is crucial to guarantee reliability of SoC effectively.
Traditional off-line reliability assessment methods, such as reliability simulation, process online detection, reliability test and failure analysis, etc., cannot predict the service life of the device in real time. The on-chip prognostic method based on prognostic cells can add a vulnerable unit into a host circuit according to a circuit failure mechanism, so that the vulnerable unit fails prior to the host circuit to provide a warning to ensure the security of the host circuit. That is, the failure early warning for the host circuit can be generated in real-time.
An existing TDDB failure prognostic circuit, as shown in FIG. 1, includes a charge pump made up of diodes D1 and D2, a start-up bypass circuit, a stress voltage circuit and a capacitor C1. In an initial state, a switch S2 is switched on and a test capacitor Ctest is in an overvoltage condition. If the test capacitor Ctest fails, a comparator outputs a low level voltage, and then outputs an early warning signal, while a feedback loop controls to be switched off a switch S3 to cut off the charge pump.
However, such circuit has the following drawbacks.
(1) It is only applicable to a CMOS hybrid integrated circuit.
(2) The output module of the comparator is also under stress, which may cause stress TDDB failure breakdown, and cause false alarm.
(3) The output of the circuit has only the warning function from “0” to “1” or from “1” to “0”, therefore the degradation process of the performance cannot be monitored.
In summary, the above-mentioned TDDB failure prognostic circuit has a risk that the accuracy of the early warning is poor, and the degradation process of the performance cannot be monitored.
USPTO Backgrounds
USPTO Backgrounds