1. Field of the Invention
The present invention relates to a method of manufacturing a bipolar semiconductor device and a semiconductor integrated circuit device in which bipolar type and MIS type semiconductor devices are formed on the same substrate, and relates to a semiconductor integrated circuit device including a power supply semiconductor integrated circuit device having a constant voltage output function or constant current output function.
2. Description of the Related Art
Conventionally, in the whole region or part of a semiconductor substrate using an epitaxial growth film, a buried layer is provided under the epitaxial growth film. The buried layer is used for lowering the on resistance of a device formed over the buried layer and for improving a soft error and latch-up resistance. When NPN and PNP vertical bipolar transistors are formed on the same semiconductor substrate, for the purpose of electrically isolating a PNP type collector region from a substrate region, there is a case where an N-type buried layer region is additionally formed between the collector region and the substrate region. By doing so, the collector of the vertical PNP bipolar transistor can have an arbitrary potential.
Here, as a step of forming the N-type region for isolation, there are two methods, one of which is to use, as shown in FIGS. 4A to 4C, a step of introducing an N-type impurity having a high concentration, originally carried out for forming a collector region of the NPN bipolar transistor, and the other of which is to add a step of forming an N-type region having a relatively low concentration in addition to the former step.
However, when the N-type buried layer region formed to electrically isolate the PNP type collector region from the substrate region is used also as the NPN type collector region as shown in FIGS. 4A to 4C, since this N-type region has a high concentration, it is difficult to raise the concentration of a P-type region 3 formed on this region in a subsequent step. That is, the resistance of the PNP type collector region becomes high. If the concentration of the N-type region is made low, the resistance of the NPN type collector region becomes high reversely. On the other hand, when the N-type region is formed through the additional step, the number of masks and process steps is increased.
The present invention has been made in view of the above, and an object of the invention is to provide a method of manufacturing a semiconductor device, which enables a bipolar transistor with higher performance than the prior art, without an increase in the cost, and with high additional value to be formed.
USPTO Backgrounds
USPTO Backgrounds