1. Field of the Invention
The present invention relates to semiconductor memories, and especially those including select gates and floating gates.
2. Description of the Background Art
Semiconductor memories include a memory array block in which a plurality of memory cells are arranged in a matrix of rows and columns.
Regarding the top surface layout of a memory array block, conventional semiconductor memories include a select gate extending in the row direction and a plurality of floating gates spaced from each other and parallel to the select gate. That is, in conventional semiconductor memories, a plurality of floating gates are spaced from each other in a straight line.
The structures of and control techniques for those semiconductor memories are disclosed, for example, in the following patent documents: Japanese Patent Application Laid-open Nos. 5-326886 (1993), 2002-329398, and 2001-156275.
However, in the above conventional semiconductor memories, since the plurality of floating gates are placed side by side in a straight line, a space of more than the design rule must be left between each two adjacent floating gates, which results in the problem of increased area of the memory array block.
Further, if the gate widths of the floating gates are reduced in order to reduce the area of the memory array block, the amount of current outputted from memory cells in data read operations is reduced. This results in another problem of difficulty of judgment by a sense amplifier.
USPTO Backgrounds
USPTO Backgrounds