On one of the surfaces of a semiconductor component, such as a chip, there is an arrangement of pads, each with a solder ball (hereinafter referred to as C-4 solder ball pads or just C-4s) which are adapted to provide connection between the chip and a substrate, such as a ceramic substrate. This is done by means of bonding of the solder balls which are heated to a temperature above the melting temperature of the solder balls thereby permitting solder bonding of the solder balls to pads carried on the mating surface of the substrate. Connected between the solder pad areas and other sites on or in the substrate are so-called fan-out lines which extend along the mating surface of the substrate beneath a layer of insulation. At certain locations on the surface of the substrate, it is necessary to make pads available for engineering change (EC) wiring to be connected to the fan-out metallurgy. The engineering change wiring, however, is usually connected to the pads by the process of wire bonding, either by ultrasonic vibration or by thermo-compression techniques, or by solder bonding. The metallurgical requirements for solder bonding as contrasted with the requirements for wire bonding techniques differ.
In Bhattacharya et al. U.S. Pat. No. 4,463,059, the metallurgical requirements for solder bonding and wire bonding were discussed in the context of the top surface metallurgy of a ceramic substrate. Several metallurgical structures were proposed. For solder bonding, one proposed structure consisted of fan-out lines of chromium and gold, then a barrier layer of cobalt or chromium over the gold followed by a top layer of nickel or copper. For wire bonding, the nickel or copper top layer was eliminated. In other structures, Bhattacharya et al. suggested the use of gold where solder bonding was to occur.
Merrin et al. U.S. Pat. Re. 27,934 discussed the requirements of ball limiting metallurgy (BLM), i.e., the pads on the bottom of the chip which serve to limit the flow of the solder balls upon heating. The particular ball limiting metallurgy proposed by Merrin et al. comprises subsequent layers of chromium, copper and then gold.
Similarly, Research Disclosure 26726, Number 267, (July 1986), discloses a backside preparation and metallization of silicon wafers for die-bonding comprising coating the backside of a semiconductor chip with subsequent layers of chromium or titanium, nickel or copper followed by a top layer of gold, and which is followed by a coating of tin.
U.S. Pat. No. 4,772,523 (Mace et al.), discloses a composite metallization structure on a glass substrate consisting of Cr/Au/Ni/Au/solder layers for a silicon capacitive pressure sensor. The interm gold layer does not bond strongly to chromium because of a lack of mutual solubility, but it appears that the interm gold layer will diffuse into the grain boundaries of the nickel and chrome metallization layer during the anodic bonding process. This anodic bonding process is done prior to the solder application, and the composite metallization layers are subjected to anodic-bonding temperatures under an electric potential to diffuse gold into nickel and chromium.
The present day top surface metallurgy for ceramic substrates may comprise a multilayered metallurgical structure of chromium or titanium, copper and then gold or, alternatively, molybdenum, nickel and then gold. The currently favored ball limiting metallurgy comprises chromium, copper and gold. Both the top surface metallurgy (hereinafter TSM) and the ball Iimiting metallurgy (hereinafter BLM) undergo many solder reflow operations during the process of joining the chips to the ceramic substrate. The gold in the TSM and BLM quickly dissolves in the solder, leaving the underlying copper (or nickel) to react with the solder which is usually of a lead/tin composition. The solder and the underlying copper (or nickel) have been chosen because they form a good solder joint.
The reaction of the copper and the solder, however, causes the formation of copper/tin intermetallics. Ordinarily, this would not be a problem but due to the multiple solder reflows necessary to join the chips to the ceramic substrate, the copper/tin intermetallics, eventually build up to the point where they spall off the underlying metallization, resulting in the loss of BLM conduction as well as the loss of a reaction barrier between the solder and the underlying chip metallization. Further, the spalling of these intermetallics can lead to early failure of the solder joint.
It would thus be an important step to be able to eliminate copper/tin intermetallics and their accompanying problems, and to be able to provide corrosion and stress-resistant interconnecting metallurgy.
USPTO Backgrounds
USPTO Backgrounds