A multi-time programming nonvolatile memory (also referred as a MTP memory) has a memory array with plural cells. Generally, each cell has a floating gate transistor. According to the amount of the hot carriers injected into the floating gate of the floating gate transistor, a threshold voltage of the floating gate transistor is changed and a corresponding state of the cell is determined.
FIG. 1 schematically illustrates the threshold voltage distribution curves of a floating gate transistor of a nonvolatile memory in different states. In case that no hot carriers are injected into the floating gate of the floating gate transistor, the threshold voltage of the floating gate transistor is about Vth1. Whereas, in case that the hot carriers are injected into the floating gate of the floating gate transistor, the threshold voltage of the floating gate transistor is about Vth2. Moreover, the state of the floating gate transistor (or the cell) is determined by applying a control voltage Vc to the floating gate transistor and judging whether the floating gate transistor is turned on. The control voltage Vc is in the range between the threshold voltage Vth1 and the threshold voltage Vth2.
For example, the floating gate transistors of the cells are P-type floating gate transistors. After the control voltage Vc is provided to all P-type floating gate transistors, the P-type floating gate transistors with the threshold values higher than the control voltage Vc are turned on and higher cell currents (i.e., on currents) are generated. In addition, the P-type floating gate transistors with the threshold values lower than the control voltage Vc are turned off and lower cell currents (i.e., off currents) are generated. As shown in FIG. 1, the P-type floating gate transistor that is turned off is in an off state, and the P-type floating gate transistor that is turned on is in an on state, when the control voltage Vc is provided to P-type floating gate transistors.
On the other hand, the floating gate transistors of the cells are N-type floating gate transistors. After the control voltage Vc is provided to all N-type floating gate transistors, the N-type floating gate transistors with the threshold values lower than the control voltage Vc are turned on and higher cell currents are generated. In addition, the N-type floating gate transistors with the threshold values higher than the control voltage Vc are turned off and lower cell currents are generated. Consequently, the state of the N-type floating gate transistor can be determined.
Hereinafter, the cells with the P-type floating gate transistors are illustrated as examples. The features of the cells with the N-type floating gate transistors are similar to those of the cells with the P-type floating gate transistors, and are not redundantly described herein.
FIGS. 2A, 2B and 2C are schematic circuit block diagrams illustrating the operations of the conventional MTP nonvolatile memory. As shown in FIG. 2A, the MTP nonvolatile memory comprises a memory array 210 and a sensing circuit 220. The memory array 210 comprises plural cells c11˜cmn, which are arranged in an m×n array. Moreover, m word lines WL1˜WLm are connected with corresponding m rows of n cells, and n bit lines BL1˜BLn are connected with corresponding n columns of m cells. The sensing circuit 220 comprises n sense amplifiers SA1˜SAn. The n sense amplifiers SA1˜SAn are connected with the n bit lines BL1˜BLn, respectively.
While a read action is performed, one of the m word lines WL1˜WLm is activated, and a selected row corresponding to the activated word line is determined. The n cells in the selected row generate corresponding cell currents Ic1˜Icn. The cell currents Ic1˜Icn are transmitted to the n sense amplifiers SA1˜SAn through the n bit lines BL1˜BLn. According to the magnitudes of the cell currents Ic1˜Icn, the n sense amplifiers SA1˜SAn determine n storage states of the n cells of the selected row.
For example, the n sense amplifiers SA1˜SAn are current comparators. The positive input terminals of the n sense amplifiers SA1˜SAn receive a reference current Iref. The negative input terminals of the n sense amplifiers SA1˜SAn receive the corresponding cell currents Ic1˜Icn from the n bit lines BL1˜BLn. The magnitude of the reference current Iref is in the range between the on current Ion and the off current Ioff. Take the first sense amplifier SA1 as an example. In case that the cell is in the off state, the received cell current Ic1 is the off current Ioff. Since the reference current Iref is higher than the off current Ioff, a data signal D1 outputted from the first sense amplifier SA1 is “1”, indicating a first storage state of the cell. Whereas, in case that the cell is in the on state, the received cell current Ic1 is the on current Ion. Since the reference current Iref is lower than the on current Ion, the data signal D1 outputted from the first sense amplifier SA1 is “0”, indicating a second storage state of the cell.
After an erase action of the MTP nonvolatile memory is performed, the stored data of all cells are erased. Consequently, the hot carriers are ejected from the floating gates of all cells. Under this circumstance, the cells are in the off state. As shown in FIG. 2B, after a sector erase or chip erase, all cells of the memory array 210 are in the off state. The cells in the off state are indicated by solid dots.
After the erase action of the MTP nonvolatile memory is completed, an erase verification process (or a read operation) is performed. During the erase verification process, the sensing circuit 220 sequentially read the storage states of the plural rows of cells. Since the data signals D1˜Dn outputted from the sensing circuit 220 for each selected row are all “1”, all cells of the memory array 210 are in the first storage state. Under this circumstance, the sensing circuit 220 confirms that the erase action is completed.
After the completion of the erase action is confirmed, a program action is performed on the memory array 210. During the program cycle, the n memory cells in the selected row are selectively programmed to the on state. Generally, the data are written into the memory array 210 in rows. For example, the data amount of one row is 1024 bits. As shown in FIG. 2C, two rows of cells have been programmed. The cells c11˜c1n of the first row and the cells c21˜c2n of the second row have corresponding states. Since the cells from the third row to the m-th row are in the off state, it means that the cells are not programmed. If desired, the non-programmed cells of the memory array 210 can be programmed.
After the program action is completed, a read action is performed to read the storage states of the cells of the programmed rows. For example, if the word line WL2 is activated, the second row is the selected row. The n cells c21˜c2n of the second row generate corresponding cell currents Ic1˜Icn. The cell currents Ic1˜Icn are transmitted to the n sense amplifiers SA1˜SAn through the n bit lines BL1˜BLn. According to the magnitudes of the cell currents Ic1˜Icn, the n sense amplifiers SA1˜SAn determine n storage states of the n cells of the selected row. The cell current Ic1 is the on current Ion. Since the data signal D1 outputted from the first sense amplifier SA1 is “0”, the cell c21 has the second storage state. The cell current Ic2 is the off current Ioff. Since the data signal D2 outputted from the second sense amplifier SA2 is “1”, the cell c22 has the first storage state. The cell current Ic3 is the off current Ioff. Since the data signal D3 outputted from the third sense amplifier SA3 is “1”, the cell c23 has the first storage state. The cell current Ic4 is the on current Ion. Since the data signal D4 outputted from the fourth sense amplifier SA4 is “0”, the cell c24 has the second storage state. The cell current Icn is the on current Ion. Since the data signal Dn outputted from the sense amplifier SAn is “0”, the cell c2n has the second storage state.
For increasing the reliability of the MTP nonvolatile memory, the memory array is composed of differential cells. FIGS. 3A, 3B and 3C are schematic circuit block diagrams illustrating the operations of a conventional MTP nonvolatile memory having a memory array with differential cells. As shown in FIG. 3A, the MTP nonvolatile memory comprises a memory array 310 and a sensing circuit 320. The memory array 310 comprises plural differential cells c11˜cmn, which are arranged in an m×n array.
Moreover, m word lines WL1˜WLm are connected with corresponding m rows of n differential cells, and n bit line pairs (BL1, BL1b), (BL2, BL2b), . . . , and (BLn, BLnb) are connected with corresponding n columns of m differential cells. The sensing circuit 320 comprises n sense amplifiers SA1˜SAn. The n sense amplifiers SA1˜SAn are connected with the n bit line pairs, respectively. The negative input terminals of the n sense amplifiers SA1˜SAn are connected with the corresponding bit lines of the n bit line pairs. The positive input terminals of the n sense amplifiers SA1˜SAn are connected with the inverted bit lines of the n bit line pairs.
For example, the differential cells c11˜cm1 of the first column are connected with the first bit line pair (BL1, BL1b). The bit line BL1 of first bit line pair is connected with the negative terminal of the sense amplifier SA1, and the inverted bit line BL1b of first bit line pair is connected with the positive terminal of the sense amplifier SA1.
While a read action is performed, one of the m word lines WL1˜WLm is activated, and a selected row corresponding to the activated word line is determined. The n differential cells in the selected row generate corresponding cell currents (Ic1, Ic1b), (Ic2, Ic2b), . . . , and (Icn, Icnb). These cell currents are transmitted to the n sense amplifiers SA1˜SAn through the n bit line pairs. According to the magnitudes of the cell currents, the n sense amplifiers SA1˜SAn determine n storage states of the n differential cells of the selected row.
As shown in FIG. 3B, each differential cell of the memory array 310 comprises two sub-cells. The two sub-cells are connected with the corresponding bit line pair. After the program action is completed, the two sub-cells have the complementary states. For example, the first sub-cell is in the on state, the second sub-cell is in the off state. Alternatively, the first sub-cell is in the off state, the second sub-cell is in the on state. As shown in FIG. 3B, the first sub-cell of the differential cell c11 is connected with the bit line BL1, and the second sub-cell of the differential cell c11 is connected with the inverted bit line BL1b. Moreover, the first sub-cell of the differential cell c11 generates the cell current Ic1, and the second sub-cell of the differential cell c11 generates the cell current Ic1b. 
After the program action is completed, a read action is performed to read the storage states of the differential cells of each programmed row of the memory array 310. For example, if the word line WL3 is activated, the third row is the selected row. The n differential cells c31˜c3n in the third row generate the corresponding cell currents. These cell currents are transmitted to the n sense amplifiers SA1˜SAn through the n bit line pairs. According to the magnitudes of the cell currents, the n sense amplifiers SA1˜SAn determine n storage states of the n differential cells c31˜c3n of the selected row.
As shown in FIG. 3B, the cell current Ic1 is the off current Ioff, and the cell current Ic1b is the on current Ion. Since the cell current Ic1 is lower than the cell current Ic1b, the data signal D1 outputted from the sense amplifier SA1 is “1”, indicating the first storage state of the differential cell c31. The cell current Ic2 is the on current Ion, and the cell current Ic2b is the off current Ioff. Since the cell current Ic2 is higher than the cell current Ic2b, the data signal D2 outputted from the sense amplifier SA2 is “0”, indicating the second storage state of the differential cell c32. The cell current Ic3 is the on current Ion, and the cell current Ic3b is the off current Ioff. Since the cell current Ic3 is higher than the cell current Ic3b, the data signal D3 outputted from the sense amplifier SA3 is “0”, indicating the second storage state of the differential cell c33. The cell current Icn is the on current Ion, and the cell current Icnb is the off current Ioff. Since the cell current Icn is higher than the cell current Icnb, the data signal Dn outputted from the sense amplifier SAn is “0”, indicating the second storage state of the differential cell c3n. 
After an erase action of the MTP nonvolatile memory is performed, the stored data of all differential cells are erased. Consequently, the hot carriers are ejected from the floating gates of all differential cells. Under this circumstance, the sub-cells of all differential cells are in the off state. As shown in FIG. 3C, all differential cells c11˜cmn of the memory array 310 are in the off state after the erase action is completed. The differential cells in the off state are indicated by solid dots.
After the erase action of the MTP nonvolatile memory is completed, as shown in FIG. 3C, the sub-cells of all differential cells are in the off state. Due to the differences between the sub-cells, some of the data signals D1˜Dn indicate the first storage state and the others of the data signals D1˜Dn indicate the second storage state. Since the sub-cells of all erased differential cells are in the off state, the sense amplifiers SA1˜SAn of the sensing circuit 320 cannot make the accurate judgment.
USPTO Backgrounds
USPTO Backgrounds