1. Field of the Invention
The present invention relates to the field of semiconductor fabrication technique, and more particular to a method for fabricating a small-scale metal-oxide-semiconductor MOS device.
2. Description of the Related Art
With the ever increasing development of Integrated Circuit (IC) fabrication process/device technology, the degree of IC integration is becoming higher, and thus the size of MOS devices is required to be smaller.
The process for fabricating, for example, a NMOS type MOS device generally includes the following steps; (i) growing a screen oxide layer on a substrate, (ii) performing photolithography and P-type ion implantation to form a P well, (iii) growing a gate oxide layer, (iv) depositing polysilicon and performing photolithography and etching to form a gate region, (v) performing photolithography and implantation to form a N-type Lightly Doped Drain (LDD), (vi) depositing Tetraethyl Ortho Silicate (TEOS) and performing photolithography and etching to form a side wall, (vii) performing photolithography and implantation for the source/drain (S/D) regions, (viii) thermally annealing the S/D implant to form the S/D regions, (ix) depositing an Salicide Blocking (SAB) material layer, (x) performing photolithography and etch on the Salicide Blocking (SAB) material layer, and (xi) processing Silicide by metal processing to form a metal contact.
To obtain a small scale MOS device, the depth of the S/D junction must be made shallow during fabrication, which requires high performance control for the implanting apparatus used in the S/D implanting process.
An existing ion implanter is a high-current and low-energy apparatus. Thus, under low energy and high productivity, it is difficult to implement a super-shallow junction technique with this apparatus. Therefore, a shallow S/D junction is difficult to obtain with conventional implantation processing. Further, following the S/D implantation process, the thermal anneal process performed by existing fabrication techniques impedes further scaling of small-scale MOS devices.
USPTO Backgrounds
USPTO Backgrounds