One embodiment of the present invention relates to bus twisting method. In particular, one embodiment of the present invention relates to an algorithm used to twist bus lines or wiring resulting in distributed coupling, lower capacitance and low power.
Memory structures have become integral parts of modern VLSI systems, including digital line processing systems. Although typically it is desirable to incorporate as many memory cells as possible into a given area, memory cell density is usually constrained by other design factors such as layout efficiency, performance, power requirements, and noise sensitivity.
In view of the trends toward compact, high-performance, high-bandwidth integrated computer networks, portable computing, and mobile communications, the aforementioned constraints can impose severe limitations upon memory structure designs, which traditional memory systems and subcomponent implementations may fail to obviate.
One type of basic storage element is the static random access memory (hereinafter referred to as “SRAM”), which can retain its memory state without refreshing as long as power is applied to the cell. In one embodiment of a SRAM device, the memory state is usually stored as a voltage differential within a bitable functional element, such as an inverter loop. A SRAM cell is more complex than a counterpart dynamic RAM (hereinafter referred to as “DRAM”) cell, requiring a greater number of constituent elements, preferably transistors. Thus efficient lower-power SRAM device designs are particularly suitable for VLSI systems having need for high-density SRAM components, providing those memory components observe the often strict overall design constraints of the particular VLSI system.
Furthermore, the SRAM subsystems of many VLSI systems frequently are integrated relative to particular design implementations, with specific adaptations of the SRAM subsystem limiting, or even precluding, the scalability of the SRAM subsystem design. As a result SRAM memory subsystem designs, even those considered to be “scalable”, often fail to meet such design limitations once these memory subsystem designs are scaled-up for use in a VLSI system needing a greater memory cell population and/or density.
A number of such memory structures, including SRAM modules or subsystems, not to mention the VLSI systems themselves among other systems and devices, have a number of lines, bitlines for example, that physically run in parallel (alternatively referred to as a “bus”). Switching one of the bitlines up and down on the bus may cause the other lines in spaced relationship to the switching lines, lines above and below for example, to couple with the switching lines, thus increasing the capacitance and power requirements of at least the line, if not the entire bus.
It is known to twist pairs of complimentary bitlines in memory structures, so as to equalize the capacitive coupling between such complimentary bitlines and adjacent pairs of bitlines.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
USPTO Backgrounds
USPTO Backgrounds