Chip packaging is normally the final process in the long chain of processes for manufacturing semiconductor integrated circuits. Chip packaging is a multi-disciplinary technology that typically involves many steps. The technology is critically important because it has a direct impact on chip performance and reliability as well as the performance and reliability of electronic devices in which the chips are incorporated. “Packaging” as used herein encompasses any of various conventional techniques of preparing a chip (also called a “die”) for actual use in an electronic device. In many instances, packaging involves, basically, encapsulating the die in a manner that seals and protects the die from the external environment and provides the required external electrical connections (called “I/O” connections) from the die to other circuitry. Packaging also can facilitate the conduction of heat away from the die during use. Other types of packaging may simply involve mounting the die on a substrate or carrier, with which the die makes the required I/O connections, without forming a discrete capsule around the individual die beforehand. Since die encapsulation consumes space, this latter packaging method is typically used in applications in which size is critical, such as electronic watches, hearing aids and other medical devices, cellular phones and other personal communication equipment, lap-top and palm-top personal computers, and high-speed microprocessors.
The current disclosure is directed in general to the physical and electrical attachment of a die to a substrate. The electrical connections provide at least some of the required I/O connections of the die to the world outside the die.
Wire bonding has, for many years, been a “workhorse” technology for making electrical connections between I/O bond-pads on the die and I/O bond-pads on the package or other die-mounting substrate. However, wire bonding has several disadvantages. First, it typically is performed serially, pad-by-pad, which is inherently slow and thus decreases throughput. Second, as the number of I/O connections to an integrated circuit (e.g., memory or microprocessor chip) has increased, increasingly larger numbers of I/O bond-pads on the die are required. Providing a larger number of such pads without excessively increasing the size of the chip usually requires a corresponding decrease in the pitch (i.e., a finer pitch) of I/O bond-pads on the die. These factors, as well as other factors, have increased the difficulty and decreased the reliability of using wire bonds, which has led to much interest in alternative methods of making I/O connections to individual dies.
Key alternative methods are derived from the so-called “flip-chip” technology. Flip-chip involves the assembly of a die to a substrate or carrier in a face-down manner, usually by using electrically conductive “bumps” formed on the I/O bond-pads of the die. (“Face-down” means that the die surface on which the circuit layers are formed actually faces the substrate to which the die is attached. Wire-bonding, in contrast, is performed on face-up dies). Flip-chip methods made their debut in the mid-1960s but did not achieve widespread utilization for many years largely because wire-bonding was the norm. With the advent of extremely complex integrated circuits requiring large numbers of I/O connections, flip-chip methods have become attractive. Currently, flip-chip components are predominantly semiconductor devices such as integrated circuits, memories, signal processors, and microprocessors; however, flip-chip methods are also being used increasingly with other types of micro-electronic devices as well, such as passive filters, detector arrays, and MEMs devices. Flip-chip is also termed “direct chip attach” (abbreviated DCA), which is perhaps a more descriptive term because the die is attached directly to the substrate, carrier, or the like by the conductive bumps. DCA has allowed, in many instances, elimination of a conventional “package” entirely.
Among the various conventional flip-chip methods, the most common technique is the “solder-bump” technique that forms a small, individual solder bumps (typically roughly spherical in shape) on the I/O bond-pads of the die. After formation of the solder bumps, the wafer is diced into “bumped dies.” An individual bumped die is placed on a substrate or carrier (generally termed a “substrate”), with the “active” surface (on which the circuit layers were formed) of the die facing the substrate. The assembly is heated to cause the solder bumps to form solder connections between the die and the I/O bond-pads on the substrate. After forming these solder bridges, “underfill” (usually an epoxy adhesive) typically is added between the die and the substrate.
In flip-chip methods, due in part to the substantially shortened pathways of the I/O interconnections of the die with the substrate, increases in operational speed of the dies in finished micro-electronic devices have been realized. This increase in speed has unfortunately resulted in increased heat production by the die. To avoid thermal damage to the die, the heat must be removed in some manner. Some flip-chip circuits achieve heat removal by simple conduction from the die to the substrate and beyond. Whereas this method is satisfactory for some dies, it has limitations for other dies, especially large and complex dies configured for high-speed use. In addition, the substrate and die typically have substantially different coefficients of thermal expansion, which can result in concentration of large stresses on the die between the substrate and/or the solder bumps, especially after repeated thermal cycles. These stresses can result in physical damage to the die, the substrate, and/or the solder interconnections between the two.
A conventional way in which to improve heat conduction from a flip-chip die is to attach a heat-sink or “heat-spreader” (also called an “H/spreader”) to the upward-facing back-side of the die. One conventional method for doing this is shown in FIG. 7, in which the left-hand portion of the figure is a block diagram of the method, and the right-hand portion of the figure depicts the results of the respective steps. In the first step 10 (stiffener attach & spot cure) a stiffener “ring” 12 is attached to the substrate 14 using an adhesive 16. The adhesive is “spot cured,” by which is meant a curing stimulus (e.g., heat or radiation) is generally applied only to the adhesive 16 and not elsewhere on the structure. Other features shown in the top right-hand diagram are the die 18 (with active surface facing downward) connected by smaller solder balls 22 to the upper surface of the substrate 14; larger solder balls 24 intended to connect the substrate later to other structure (not shown), and underfill 26. The depicted structure is referred in the art as a “flip-chip ball grid array,” abbreviated “fcBGA.” In the next step 20 (adhesive dispense), an adhesive 28 is applied to the top surfaces of the stiffener ring 12. In the next step 30 (TIM dispense), before the adhesive 28 is cured, thermally conductive adhesive (also called a “thermal-interface material” or “TIM”) 32 is applied to the upward-facing (“top”) surface of the die 18. In the next step 40 (H/spreader attach), the heat-spreader 34 is placed on the TIM 32 and on the adhesive 28. In the last step 50 (press & cure), downward pressure is exerted on the heat-spreader 34, and the adhesive 28 is cured. (Note that the respective layer thicknesses of the TIM 32 and adhesive 28 are less in the figure corresponding to step 50 than in the figure corresponding to step 40.)
A larger image of the result of step 50 is shown in FIG. 8(A), in which also can be seen a “lower” conductive layer 36 providing I/O bond-pads (not detailed) for the larger solder balls 24 on the lower surface of the substrate 14, an “upper” conductive layer 38 providing I/O bond-pads (not detailed) for the smaller solder balls 22, vias 42 connecting the upper conductive layer 38 to the lower conductive layer 36, and the core material 44 of the substrate 14. In FIG. 8(A) the heat-spreader 34 is substantially planar (called a “Type I” heat-spreader), and is desirably attached to the substrate 14 using the stiffener ring 12. In FIG. 8(B) the heat-spreader 34a has an inverted-U profile (called a “Type II” heat-spreader, which allows its attachment to the substrate 14 using the adhesive 28 but without using the stiffener ring 12.
Another approach is disclosed in published U.S. Patent Application No. 2004/0229399 A1, incorporated herein by reference. In the '399 application, after flipping the die and attaching its solder bumps (on the active surface of the die) to the substrate, the heat-spreader is mounted to the back-side of the die using a TIM. Specifically, a dollop of TIM is applied to the back-side of the die, followed by press-placement of the heat-spreader on the dollop. The resulting bond-line thickness of the TIM depends on the particular TIM material (e.g., viscosity and pot-life) and the applied pressing force. A stiffener ring surrounding the die on the substrate can be used to provide further mechanical support for the heat-sink. If required, the TIM can be treated (e.g., cured) to facilitate adhesion of the heat-spreader to the die. Then, underfill material (epoxy resin) is applied at least to fill the space between the substrate and the die. For application of the underfill resin, the heat-spreader defines at least one through-hole through which the resin is introduced. Sufficient epoxy resin can be added not only to fill the space between the substrate and the active surface of the die but also to form an epoxy fillet around the edge of the die from the substrate to the heat-spreader. Then, the underfill adhesive is cured.
Unfortunately, the conventional methods summarized above exhibit some adverse characteristics. First, for example in the '399 application, the manner of attaching the heat-spreader to the die, namely by applying a dollop of TIM to the back-side of the die followed by press-placement of the heat-spreader onto the dollop, often entraps significant amounts of air, resulting in formation of air voids between the TIM and the heat-spreader and/or between the back-side of the die and the TIM. This entrapped air is not visible externally, is easily entrapped, and is difficult to expel, especially in automated processes. Since the rate of thermal conduction through an air void is substantially lower than the rate of thermal conduction through the TIM, the heat-removal effectiveness of the heat-spreader can be seriously compromised by this problem. Also, application of excessive pressure when press-placing the heat-spreader to the dollop of TIM can fracture or otherwise damage the die and/or the solder connections between the die and substrate. In addition, one or more particles becoming entrapped in the TIM can focus stress on the die and cause the die to crack or break. Similar problems are manifest with the other conventional method summarized above and shown in FIG. 7.
In view of the foregoing, improved methods are needed for mounting heat-spreaders to fcBGA dies.
USPTO Backgrounds
USPTO Backgrounds