1. Field of the Invention
The present invention generally relates to a method of manufacturing a lateral insulating gate type field effect transistor and, more particularly, is directed to a method of manufacturing a lateral insulating gate type field effect transistor for use in manufacturing a so-called XMOS transistor whose channel region is sandwiched by a pair of gate portions.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a schematic cross-sectional view of an example of a conventional so-called XMOS transistor. As shown in FIG. 1, first and second gate electrodes 33G.sub.1, 33G.sub.2 are respectively formed on upper and lower surfaces of a semiconductor layer 31 of a low impurity concentration type, i.e., p.sup.- type or n.sup.- type or intrinsic i-type which serves as a channel forming portion through gate portions, i.e., gate insulating films 32 in an opposing fashion. Source or drain regions 34 made by the ion implantation of n-type or p-type impurity are respectively formed on the semiconductor layer 31 across the portion where these gate portions are formed.
The XMOS transistor thus arranged has excellent characteristics that are not obtained by an ordinary MOS transistor, such as no punch-through, an excellent switching characteristic and characteristics being controllable without introducing an impurity into the channel region.
When in the XMOS transistor the first and second gate portions, i.e., the two gate electrodes 33G.sub.1 and 33G.sub.2 are independently applied with control voltages to independently control the first and second gate portions, freedom in controlling the first and second gate portions is increased and much more excellent transistor characteristics can be obtained.
Lateral solid phase epitaxy growth techniques nave heretofore been proposed as a method of manufacturing the XMOS transistor in which the upper and lower gate portions are controlled independently. According to these lateral solid phase epitaxy growth techniques, a crystalline property of the epitaxial growth layer is not perfect so that a device having an excellent carrier mobility cannot be obtained.
USPTO Backgrounds
USPTO Backgrounds