Semiconductor optoelectronic devices such as laser diodes for optical transmitters and photosensors for optical receivers can be efficiently fabricated using wafer processing techniques. Generally, wafer processing techniques simultaneously form a large number (e.g., thousands) of devices on a wafer. The wafer is then cut to separate individual chips. Simultaneous fabrication of a large number of chips keeps the cost per chip low, but each individual chip must be packaged and/or assembled into a system that protects the chip and provides both electrical and optical interfaces for use of the devices on the chip.
Assembly of a package or optical subassembly (OSA) containing a semiconductor optoelectronic device is often costly because of the need to align multiple optical elements with the semiconductor device. For example, the receiver side of an optical transceiver chip may include a sensor that receives an optical signal from an optical fiber and converts the optical signal into an electrical signal. Additional optical elements may be required between the optical fiber and the sensor to focus the optical signal on the photosensitive portion of the sensor. Alignment of the sensor, the optical fiber, and the intervening optics can be a time consuming and expensive process. Further, the alignment and assembly processes generally must be performed separately for each package.
Wafer-level packaging is a promising technology for reducing the size and the cost of the packaging for integrated circuits. With wafer-level packaging, components that conventionally have been separately formed or attached to separate packages are instead fabricated on or applied to a wafer that corresponds to multiple packages. The resulting structure can be cut up to separate individual packages. Packaging techniques and structures that can reduce the size and/or cost of packaged optoelectronic devices are sought.
USPTO Backgrounds
USPTO Backgrounds