1. Field of the Invention
The present invention relates to a semiconductor device capable of operating at high speed and a method of manufacturing the same.
2. Description of the Related Art
In an LSI with a transistor or the like of a process rule of 90 nm node and thereafter, a standby off-leak current accompanying miniaturization of elements is not negligible. Therefore, it becomes difficult to improve device performance only by simple miniaturization of a gate length of a transistor, and thus a new approach is needed for improving the device performance.
With such an ultra-miniaturized transistor, the dimension of a channel region located immediately below a gate electrode is very small as compared with conventional transistors. In such a case, it is known that the degree of movement of carriers (electrons and holes) running in the channel region is largely affected by stress applied to the channel region. Accordingly, there are attempted many times to improve the operation speed of a semiconductor device by adjusting such stress.
In general, in a transistor in which a region of its silicon substrate where an impurity is introduced is the channel, the degree of movement of holes is smaller than the degree of movement of electrons. Therefore, improvement of the operation speed of a p-channel MOS transistor using holes as carriers is an important problem when designing a semiconductor integrated circuit device. Then, in the p-channel MOS transistor, it is known that the degree of movement of carriers (holes) improves by applying uniaxial compression stress to the channel region. As a structure for applying the compression stress to the channel region there is proposed one shown in FIG. 18. FIG. 18 is a cross-sectional view showing the structure of a conventional strained silicon transistor.
As shown in FIG. 18, a gate insulating film 202 and a gate electrode 203 are sequentially formed on an n-type silicon substrate 201. In a surface of the silicon substrate 201, impurity diffused layers 207 sandwiching the gate electrode 203 in a plan view are formed. In the impurity diffused layers 207, a p-type impurity is introduced. Further, on sides of the gate electrode 203, side wall insulating films 206 are formed.
In each of the impurity diffused layers 207, a trench 208 is formed so as to match with the side wall insulating film 206, and a SiGe mixed crystal layer 209 is formed therein by an epitaxial growth method. Then, the impurity diffused layer 207 and the SiGe mixed layer 209 constitute a source-drain region. Note that a part of the impurity diffused layer 207 also functions as an extension region. Further, a region of the silicon substrate 201 sandwiched by the source-drain regions functions as the channel region. Therefore, the degree of flow of holes transported from one to the other of the impurity diffused layers 207 via the channel region is controlled by a gate voltage applied to the gate electrode 203.
Further, in this p-channel MOS transistor, the lattice constant of SiGe constituting the SiGe mixed crystal layer 209 is larger than the lattice constant of Si constituting the silicon substrate 201, so that the compression stress in a horizontal direction operates as shown by arrows “a” in the SiGe mixed crystal layer 209. Then, along with this compression stress, as shown by an arrow “b”, the SiGe mixed crystal layer 209 is strained in the vertical direction. Furthermore, since the SiGe mixed crystal layer 209 is epitaxially grown relative to the silicon substrate 201, this strain induces a vertical strain as shown by an arrow “c” in the channel region. Then, along with this strain, uniaxial compression stress is induced as shown by arrows “d” in the channel region.
In the conventional p-channel MOS transistor constructed as described above, since such uniaxial compression stress is applied in the channel region, symmetry of Si crystals constituting the channel region changes locally. In other words, a strain is generated in the channel region. Along with such a change of symmetry, degeneracy of the valence band of heavy holes and the valence band of light holes is released, and thus the degree of movement of holes in the channel region increases, thereby improving the operation speed of the transistor. Then, such increase in the degree of movement of holes and improvement in the transistor operation speed accompanying therewith appear significantly particularly in an ultra-miniaturized transistor having a gate length of 100 nm or smaller.
As described above, it has been pointed out in principle that, in a transistor in which the SiGe mixed crystal layer is embedded in the source-drain region, the larger the compression strain generated in the channel region, the more the degree of movement of holes increases (K. Mistry et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, pp. 50-51). Such increase in compression strain can be realized by increasing a Ge ratio in the epitaxially-grown SiGe mixed layer. However, when the Ge ratio in the epitaxially grown SiGe mixed layer is too high, a lattice mismatch between Si constituting the substrate and SiGe constituting the mixed crystal layer becomes too large, thereby generating dislocation. Such dislocation not only weakens the effect of the compression strain induced by the SiGe mixed crystal layer, but also increases a leak current taking the dislocation as a path. As a result, the transistor performance deteriorates.
In general, dislocation generated in a SiGe mixed crystal layer epitaxially grown on a silicon substrate occurs easier as the Ge ratio is higher or the thickness thereof is larger (R. People et al., Appl. Phys. Lett. Vol. 47 (3), 1985). In theory, the limit of a film thickness over which the dislocation occurs is referred to as a critical film thickness, and for epitaxially growing a SiGe mixed crystal layer in which no dislocation exists, it is desirable that the thickness thereof is controlled to be smaller than the critical film thickness. However, when producing transistors in practice, there exist physical damages such as damage due to ion implantation, sputtering damage due to dry etching, and plasma damage in a region (source-drain region) where the SiGe mixed crystal layer is to be formed. Accordingly, even when it is controlled to be smaller than the critical film thickness, there may still occur dislocation in SiGe mixed crystals with these damages being origins.
Therefore, in conventional silicon transistors, in order to assure the normal operation, the Ge concentration is suppressed to be low. In other words, the degree of movement of carriers is suppressed more than necessary.
Further, a wiring is formed on the SiGe mixed crystal layer. Then, in order to make a favorable contact between them, a silicide layer is formed. As such a silicide layer, a Ni silicide layer is used in general in a transistor of 90 nm node or thereafter. However, when the Ni silicide layer is used, as the Ge concentration (Ge ratio) in SiGe mixed crystals becomes higher, its heat stability more easily decreases, and also a NiSi2 phase with high resistivity is more easily formed. The NiSi2 phase has high resistance as compared to a NiSi phase, and easily forms a spike surrounded by {111} planes. Consequently, when the NiSi2 layer exists, current driving performance of the transistor easily deteriorates, and also the leak current easily increases.
Related art is disclosed in Japanese Patent Application Laid-open No. 2006-13428.
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