1. Field of the Invention
The present invention relates, in general, to semiconductor devices and, more particularly, to an internal voltage generator and a semiconductor memory device having the same, and a method of generating an internal voltage.
2. Discussion of Related Art
In general, a semiconductor memory device includes an internal voltage generator for generating internal voltages based on external voltages. The internal voltage generator generates internal voltages with various levels and supplies the internal voltages to several circuits within the semiconductor memory device. Of the internal voltages, voltages that are mainly supplied to an internal core circuit of the semiconductor memory device include a boosting voltage VPP and a back bias voltage VBB. The boosting voltage VPP is higher than an external voltage VDD and is supplies to a word line driver and a bit line isolation circuit within the semiconductor memory device. The back bias voltage VBB is lower than the external voltage VDD. The back bias voltage VBB is supplied to a transistor in order to compensate for the loss of the threshold voltage of the transistor included in an internal circuit (in particular, a memory cell array) of the semiconductor memory device. Meanwhile, the boosting voltage VPP is used to power the word line driver. Accordingly, if the number of word line drivers that operate at once (that is, the number of word lines that are enabled at the same time) is increased, the boosting voltage VPP may temporarily drop. This phenomenon may occur in a word line test process (i.e., one of test processes performed in, for example, a wafer burn-in (WFBI) test mode). The word line test process can be performed in such a manner that stress is applied to word lines connected to a memory cell array by alternately enabling the word lines or enabling all the word lines at the same time. If all the word lines are enabled at one time in the word line test process, however, current consumption is increased due to the word line drivers, which may temporarily drop the boosting voltage VPP. This will be described in more detail with reference to FIG. 1. Word line drivers (not shown) enable word lines WL0 to WLK (K is an integer) at the same time in response to a test signal TALLWD. At a point of time P at which the word lines WL0 to WLK are enabled, the boosting voltage VPP abruptly drops and, therefore, becomes lower than the external voltage VDD despite the fact that the boosting voltage VPP must be higher than the external voltage VDD. If the boosting voltage VPP is lower the external voltage VDD as described above, the internal circuits of the semiconductor memory device may malfunction. Meanwhile, the back bias voltage VBB is generally dependent on the external voltage VDD. Accordingly, during a power-up period of the semiconductor memory device (that is, a time in which the external voltage VDD begins rising and then become a stable voltage), it is difficult to shorten the time D1 (refer to FIG. 2) taken for the back bias voltage VBB to become a stable voltage level. This is because the internal voltage generator generates the back bias voltage VBB on the basis of the external voltage VDD. That is, as shown in FIG. 2, the internal voltage generator does not generate a stable back bias voltage VBB until the external voltage VDD becomes a set voltage VL1. Accordingly, if the time D1 taken for the back bias voltage VBB to become a stable voltage level during the power-up period is shortened, the operational performance of the semiconductor memory device will become further improved.
USPTO Backgrounds
USPTO Backgrounds