1. Field of the Invention
This invention relates generally to semiconductor devices and fabrication methods thereof and, more particularly, to trench DMOS type semiconductor devices and fabrication methods thereof.
2. Description of the Prior Art
DMOS transistors (double diffused metal-oxide-semiconductor field effect transistors) (also referred to herein as DMOSFETs) are a type of MOSFET that use diffusion to form the transistor regions. These DMOS type devices took on various shapes and configurations. A typical discrete DMOS circuit includes one or more individual DMOS transistor cells which are fabricated in parallel. The individual DMOS transistor cells share a common drain contact (the substrate), while their sources are all shorted together with metal and their gates are shorted together by polysilicon. Thus, even though the discrete DMOS circuit is constructed from a matrix of smaller transistors, it behaves as if it were a single large transistor.
U.S. Pat. No. 4,344,081 disclosed a DMOS type of semiconductor device that can also operate as a bipolar transistor and a fabrication method thereof. Referring to FIG. 1, a combined (N channel) DMOS and lateral NPN integrated structure is shown. An epitaxial layer 12 of N type conductivity is grown on the starting N+ semiconductor substrate. The DMOS device has a source region 22 and a drain region 24B of, for example, N+ conductivity, and the source region 22 is surrounded by a P type base region 20, thus providing a channel. A gate electrode 24 is disposed over the channel with an insulating layer 14 therebetween. A gate electrode contact 30 is provided to the gate electrode 24 through an opening in an insulating layer substantially enclosing the gate electrode 24. The source region 22 has its own electrode 28. The drain region 24B has its own electrode 28B at the same side of the gate electrode 24 and the electrode 28. A separate electrode 26A is provided to the P type base region 20 that surrounds the N+ source region 22. Accordingly, a lateral NPN transistor structure is provided by the N+ emitter region 22, the P type base region 20, and the N+ collector region 24B, and the (N channel) DMOS device structure is provided by the N+ source region 22, the P type channel portion 20 (beneath the spaced doped polysilicon gate 24), and the N+ drain region 24B. However, the area between the source region and the drain region for the electric current path is still large, on-resistance (Ron) is still high.
Another type of DMOS transistor is a “trench DMOS transistor” in which the channel is formed vertically and the gate is formed in a trench extending between the source and drain. The trench, which is lined with a thin oxide layer and filled with polysilicon, allows less constricted current flow and thereby provides lower values of specific on-resistance (forward-biased voltage drop). FIG. 2 illustrates a conventional trench DMOS structure in which the individual cells are rectangular in shape in a horizontal cross-section. The structure includes, in this embodiment, an N+ substrate 31 on which is grown a lightly n-doped epitaxial layer 32. Within doped epitaxial layer 32, a body region 33 of opposite conductivity is provided. An n-doped epitaxial layer 34 that overlies much of the body region 33 serves as the source. A rectangularly shaped trench 35 is provided in the epitaxial layers, which is open at the upper surface of the structure and defines the perimeter of the transistor cell. A gate oxide layer 36 lines the bottom and sidewalls of the trench 35. The trench 35 is filled with polysilicon, i.e., polycrystalline silicon. A drain electrode is connected to the back surface of the semiconductor substrate 31, a source electrode 37 is connected to the source regions 34 and the body region 33, and a gate electrode is connected to the polysilicon that fills the trench 35.
As indicated, the DMOS transistor shown in FIG. 2 has its gate positioned in a vertically oriented trench. This structure is often called a trench vertical DMOS. It is “vertical” because the drain contact appears on the back or underside of the substrate and because the channel flow of current from source to drain is approximately vertical. This minimizes the higher resistance associated with bent or curved current paths or with parasitic field effect construction. The device is also doubly diffused (denoted by the prefix “D”) because the source region is diffused into the epitaxial material on top of a portion of the earlier-diffused body region of opposite conductivity type. This structure uses the trench sidewall area for current control by the gate and has a substantially vertical current flow associated with it. As previously mentioned, this device is particularly appropriate for use as a power switching transistor where the current carried through a given transverse silicon area is to be maximized. However, such structure has disadvantages that the gate oxide obtained from the silicon oxidation of trench sidewall after etching has a relatively poor properties, as well as it is only suitably used as a discrete element but not suitably used in an IC for the drain region is formed at the back side of the substrate.
Therefore, there is still a need for a novel trench DMOS having a small Ron and being suitable for an integrated circuit (IC) process, while without the problem of poor gate oxide.
USPTO Backgrounds
USPTO Backgrounds