FIG. 1 illustrates, by example, a block diagram of a conventional radio communication transceiver 100 (hereinafter referred to as "transceiver"). The transceiver 100 enables a mobile or portable subscriber unit to communicate with a base station (not shown), for example, over radio frequency (RF) channels in a radio communication system (not shown). The base station thereafter provides communications with a landline telephone system (not shown) and other subscriber units. An example of a subscriber unit having the transceiver 100 is a cellular radiotelephone.
The transceiver 100 of FIG. 1 generally includes an antenna 101, a duplex filter 102, a receiver 103, a transmitter 105, a reference frequency signal source 107, a receive (Rx) phase locked loop (PLL) frequency synthesizer 108, a transmit (Tx) PLL frequency synthesizer 109, a processor 110, an information source 106, and an information sink 104.
The interconnection of the blocks of the transceiver 100 and operation thereof is described as follows. The antenna 101 receives a RF signal 119 from the base station for filtering by the duplex filter 102 to produce an RF received signal at line 111. The duplex filter 102 provides frequency selectivity to separate the RF received signal at line 111 and the RF transmit signal at line 113. The receiver 103 is coupled to receive the RF received signal at line 111 and operative to produce a received baseband signal at line 112 for the information sink 104. The reference frequency signal source 107 provides a reference frequency signal at line 115. The Rx PLL frequency synthesizer 108 is coupled to receive the reference frequency signal at line 115 and information on a data bus 118 and operative to produce a receiver tune signal at line 116 to tune the receiver 103 to a particular RF channel. Likewise, the Tx PLL frequency synthesizer 109 is coupled to receive the reference frequency signal at line 115 and information on the data bus 118 and operative to produce a transceiver tune signal at line 117 to tune the transmitter 105 to a particular RF channel. The processor 110 controls the operation of the Rx PLL frequency synthesizer 108, the Tx PLL frequency synthesizer 109, the receiver 103, and the transmitter 105 via the data bus 118. The information source 106 produces a baseband transmit signal at line 114. The transmitter 105 is coupled to receive the baseband transmit signal at line 114 and operative to produce the RF transmit signal at line 113. The duplex filter 102 filters the RF transmit signal at line 113 for radiation by the antenna 101 as a RF signal 120.
The RF channels in a cellular radiotelephone system, for example, include voice and signaling channels for transmitting and receiving (hereinafter referred to as "transceiving") information between the base station and the subscriber units. The voice channels are allocated for transceiving voice information. The signaling channels, also referred to as control channels, are allocated for transceiving data and signaling information. It is through these signaling channels that the subscriber units gain access to the cellular radiotelephone system and are assigned a voice channel for further communication with the landline telephone system. In cellular radiotelephone systems capable of transceiving wideband data on the signaling channels, the frequency spacing of the signaling channels may be a multiple of the frequency spacing of the voice channels.
In some cellular radiotelephone systems, the transceiver 100 and the base station intermittently transceive information therebetween on the signaling channel. One such system, for example, an interleaved data signaling method to synchronize the intermittent information. In this type of system, keeping the transceiver 100 fully powered during the entire time that the transceiver 100 is tuned to the signaling channel unnecessarily drains the transceiver's battery during those times when the information is not received. Therefore, portions of the transceiver 100 can be powered off to prolong battery life when the transceiver is not transceiving information. Further, portions of the transceiver 100 can be powered off to prolong battery life when the signal quality is good enough such that further repetition of the same information is not needed. Intermittently powering on and off, i.e. enabling and disabling, the transceiver 100 during its receive operation is called discontinuous receive (DRX) mode of operation. In the DRX mode of operation, quickly enabling and disabling the portions of transceiver 100 increases the savings in battery life.
FIG. 2 illustrates, by example, a block diagram of a conventional phase locked loop (PLL) frequency synthesizer for use in the transceiver 100 of FIG. 1. The general structure of the PLL frequency synthesizer of FIG. 2 is the same for both the Rx PLL frequency synthesizer 108 and the Tx PLL frequency synthesizer 109.
The PLL frequency synthesizer 108 or 109 of FIG. 2 generally includes a reference divider 201, for discussion purposes, and a PLL 212. The PLL 212 generally includes a phase detector 202, a loop filter 203, a voltage controlled oscillator 204, and a loop divider 205. The reference divider 201 receives a reference frequency signal on line 115.
The interconnection of the blocks of the PLL frequency synthesizer 108 or 109 is described as follows. The reference divider 201 is coupled to receive the reference signal at line 115 and the data bus 118 and operative to produce a divided reference frequency signal at line 206. The phase detector 202 is coupled to receive a divided reference frequency signal at line 206 and a feedback signal at line 209, and operative to produce a phase; error signal at line 207. The loop filter 203 is coupled to receive the phase error signal 207, and operative to produce a filtered signal at line 208. The voltage controlled oscillator 204 is coupled to receive the filtered signal at line 208 and operative to produce an output frequency signal at line 116 or 117. The loop divider 205 is coupled to receive the output frequency signal at line 116 or 117, and operative to produce the feedback signal at line 209. The loop divider 205 and the reference divider 201 are coupled to receive programming information at the data bus 118.
The operation of the PLL frequency synthesizer 108 or 109 of FIG. 2 is described as follows. The PLL 212 is a circuit which produces the output frequency signal at line 116 or 117 synchronized to the reference frequency signal at line 115. The output frequency signal at line 116 or 117 is synchronized or "locked" to the reference frequency signal at line 115 when the frequency of the output frequency signal at line 116 or 117 has a predetermined frequency relationship to the frequency of the reference frequency signal at line 115. Under locked conditions, the 212 PLL typically provide a constant phase difference between the reference frequency signal at line 115 and the output frequency signal at line 116 or 117. The constant phase difference may assume any desired value including zero. Should a deviation in the desired phase difference of such signals develop, i.e., should a phase error at line 207 develop due to, e.g., variation in either the frequency of the reference frequency signal at line 115 or programmable parameters of the PLL via the data bus 118, the PLL adjusts the frequency of the output frequency signal at line 116 or 117 to drive the phase error at line 207 toward the value of the constant phase difference.
The PLL frequency synthesizer 108 or 109 may be classified as belonging to one of at least two categories based on the predetermined frequency relationship of the output signal frequency at line 116 or 117 to the frequency of the reference frequency signal at line 115. The first category is classified as an "integer division" PLL frequency synthesizer wherein the relationship between the output frequency signal at line 116 or 117 and reference frequency signal at line 115 is an integer. The second category is classified as a "fractional division" PLL frequency synthesizer in which the relationship between the output frequency signal at line 116 or 117 and reference frequency signal at line 115 is a rational, non-integer number, consisting of an integer and a fraction.
PLL's are characterized by a loop bandwidth. For some applications it is desirable to vary the loop bandwidth of the PLL under certain conditions such as, for example, when the frequency of the reference frequency signal at line 115 changes or when the programmable parameters of the PLL via the data bus 118 changes. Appropriately varying the loop bandwidth advantageously provides shorter locktime, improved noise, and lower spurious signals.
There is a problem caused by phase drift when a PLL frequency synthesizer is used in the DRX mode. Since the PLL is not active during the disabled portion of the DRX mode, the phase of the VCO can drift relative to the phase of the reference frequency signal source. When the PLL is re-enabled this phase drift will be translated by the action of the PLL into a change in the VCO frequency to provide the needed phase adjustment. The PLL will require extra time to lock because this induced frequency error will also have to be eventually eliminated by the PLL action before lock can occur. If the PLL is not locked, no data can be received by the transceiver. To guarantee that the PLL is locked by the time the data is present, the transceiver would have to allow extra time for the PLL to lock by enabling the PLL early. However, then the PLL would have to be enabled, and thereby consume power which would lower battery life, before any data was present to be received.
One solution, provided by the prior art, is to minimize the phase drift by using two phase locked loops. After enabling the main PLL functional blocks, but prior to closing the loop in the main PLL, a secondary PLL was activated which phase locked the reference frequency signal source to the main PLL VCO. Once the reference frequency signal source was locked to the main PLL VCO, the secondary PLL was disconnected and the loop in the main PLL was closed. This solution does provide a fast lock time for the main PLL, however, a disadvantage of this solution is the significant additional hardware for the secondary PLL to phase lock the reference frequency signal source to the main PLL VCO. In addition, the phase characteristics of both loops must be identical or a phase error can still exist in the main PLL at the time that its loop is closed.
Another solution, provided by the prior art, is to modify the value of the loop divider for its first complete divide cycle after it has been re-enabled. The second and subsequent divide cycles use the nominal divide value. A disadvantage of this solution is that it requires an independent feedback processor to adjust the first cycle divider value as environmental conditions change since one value will not be optimum for all conditions of supply and temperature.
Yet another solution, provided by the prior art, is to reset the reference divider and loop divider after they have been re-enabled but before closing the loop in the PLL. A disadvantage of this solution is that it does not provide accurate correction for the phase drift of the VCO relative to the reference frequency signal source when the PLL was disabled. Therefore the PLL will require extra time to lock because of the inaccurate phase correction.
Yet another solution, provided by the prior art, is to use the output of the phase detector to provide a phase error indication of the PLL when the PLL is re-enabled but before closing the loop in the PLL. The loop in the PLL is typically closed with a switch between the phase detector and the loop filter. The phase error indication is used to gate the clock signals to the reference frequency divider and a variable frequency (loop) divider to initially phase lock the PLL. However, a disadvantage of this solution is the length of time required for initial phase adjustment of the clock signals of the reference frequency divider and the variable frequency (loop) divider. A further disadvantage of this solution is that, after the initial phase adjustment is completed, phase error is introduced into the PLL when the loop in the PLL is closed using the switch.
Accordingly, there is a need for an improved phase synchronization circuit and method therefor for a PLL that provides a rapid and accurate phase adjustment for the PLL with minimum hardware and minimum introduction of phase error to the PLL.
USPTO Backgrounds
USPTO Backgrounds