1. Field of the Invention
The present invention relates to a semiconductor memory capable of improving soft error resistance.
2. Description of Related Art
FIG. 5 is a circuit diagram showing a configuration of a memory core of an SRAM as an example of a conventional semiconductor memory. In this figure, reference symbols INV11 and INV12 each designate an inverter, and a and b each designate a memory node. FIG. 6 is a circuit diagram showing a configuration in which the inverters INV11 and INV12 of FIG. 5 are constructed by MOS transistors. In FIG. 6, the reference symbol PM11 designates a PMOS transistor, NM11 designates an nMOS transistor, IN designates an input terminal and OUT designates an output terminal.
Next, the operation of the conventional semiconductor memory will be described.
In FIG. 6, when the input terminal IN is placed at the logically high level (that is, at a voltage VDD), the pMOS transistor PM11 is brought out of conduction and the nMOS transistor NM11 is brought into conduction. Thus, the output terminal OUT is connected to the ground GND by the nMOS transistor NM11, thereby being placed at the logically low level. On the contrary, when the input terminal IN is placed at the logically low level (that is, at the ground GND), the pMOS transistor PM11 is brought into conduction and the nMOS transistor NM11 is brought out of conduction. Therefore, the output terminal OUT is connected to the supply voltage VDD via the pMOS transistor PM11, thereby being placed at the logically high level. Thus, the input and output logical levels of the inverters have a complementary relation.
In FIG. 5, since the memory nodes a and b have the complementary relation, when the memory node a is placed at the logically high level, the other memory node b is maintained at the logically low level. On the contrary, when the memory node a is placed at the logically low level, the other memory node b is maintained at the logically high level. Thus, the two memory nodes a and b maintain the opposite levels, thereby providing the two stable states to hold the memory data.
Recently, multi-processor technique has been introduced as one of means to implement high speed computers, and it requires that the multiple CPUs share one common memory area. In other words, the need intensifies for the multi-port memory that allows access to a single memory via multiple ports.
FIG. 7 is a circuit diagram showing a configuration of a conventional two-port RAM that utilizes two inverters INV11 and INV12 as shown in FIG. 5 whose memory nodes a and b are complementary to each other, and that is accessible from two CPUs. In this figure, the reference symbol NA11 designates an nMOS transistor connected to the memory node a; NA12 designates an nMOS transistor connected to the memory node b; INV13 designates an inverter whose input is connected to the memory node a; NR11 designates an nMOS transistor connected to the output of the inverter INV13; WL11 designates a word line connected to the gates of the nMOS transistors NA11 and NA12; BL11 and BL12 designate bit lines connected to the nMOS transistors NA11 and NA12; RL11 designates a read control line connected to the gate of the nMOS transistor NR11; and RBL11 designates a read bit line connected to the nMOS transistor NR11.
Next, the operation of the conventional two-port RAM will be described.
When the word line WL11 is placed at the high level, the nMOS transistors NA11 and NA12 are both brought into conduction. Accordingly, the memory node a is connected to the bit line BL11 and the memory node b is connected to the bit line BL12. In this case, when the read control line RL11 is placed at the high level, the memory data at the memory node a is supplied to the read bit line RBL11 via the inverter INV13.
The semiconductor memories such as SRAM and multi-port RAM composed of the CMOS inverters are very stable, and have no problem of noise as long as their memory capacity and chip size are in a certain range.
With the foregoing configuration, the conventional semiconductor memory has a problem of causing a soft error when increasing a memory capacity with restricting a chip size. One of external factors causing the soft error in the semiconductor memory, there is a soft error brought about by xcex1 rays emanating from a trace quantity of radioactive substance contained in the package. When the xcex1 rays enter the memory cell, they generate many electron-hole pairs that can cause data changes (data inversion) in the memory data.
The soft error is apt to occur as the node capacity of the memory node reduces with scale down. In FIG. 7, for example, since the memory node a is connected to the inverter INV13, its node capacity is greater than the node capacity of the memory node b. To increase the memory capacity without increasing the size of the two-port RAM, it is necessary to make the size of the MOS transistor extremely fine. As a result, the node capacity of the memory node b is further reduced, thereby increasing the probability of bringing about the soft error.
As a measure taken to prevent the soft error, a proposition is put forward for preventing the data inversion of the memory data, which is caused by the electron-hole pairs generated by the a rays, by increasing the node capacity of the memory node. For example, Japanese patent application laid-open No. 9-270469/1997 discloses a technique of increasing the node capacity of the memory node by forming a capacitor between the memory node and the semiconductor substrate by interposing a thin active region between them.
The method, however, offers a new problem of requiring an extra manufacturing process of forming the capacitors, thereby increasing its cost. In addition, an increase in the number of process steps can reduce its yield.
The present invention is implemented to solve the foregoing problem. It is therefore an object of the present invention to provide a semiconductor memory capable of improving the soft error resistance without increasing the number of steps of the manufacturing process.
According to one, aspect of the present invention, there is provided a semiconductor memory comprising: a first inverter having its input terminal connected to a first memory node that is connected to a first bit line when a first word line is active, and its output terminal connected to a second memory node that is connected to a second bit line when a second word line is active; a second inverter having its input terminal connected to the second memory node, and its output terminal connected to the first memory node; and a first read circuit having its input terminals connected to the first memory node and the second memory node, and its output terminal connected to a read bit line, wherein the first read circuit includes: a first MOS transistor having its gate connected to the first memory node; a second MOS transistor having its gate connected to the second memory node, and its drain connected to the drain of the first MOS transistor; and a third MOS transistor having its source and drain brought into conduction when a read control line connected to its gate is active, thereby connecting the read bit line to the drains of the first MOS transistor and the second MOS transistor.
Here, the first MOS transistor may consist of an nMOS transistor having its source grounded, and the second MOS transistor may consist of a pMOS transistor having its source grounded.
The third MOS transistor may consist of an nMOS transistor.
The first MOS transistor may consist of an nMOS transistor having its source connected to a supply voltage, and the second MOS transistor may consist of a pMOS transistor having its source connected to the supply voltage.
The third MOS transistor may consist of a pMOS transistor.
The semiconductor memory may further comprise at least one second read circuit that has a same configuration as the first read circuit, and has its input terminals connected to the first memory node and the second memory node, and its output terminal connected to a second read bit line, wherein a third MOS transistor of the second read circuit has its source and drain brought into conduction when a read control line connected to its gate is active, thereby connecting the second read bit line to the drains of a first MOS transistor and a second MOS transistor of the second read circuit.
Each first MOS transistor may consist of an nMOS transistor having its source grounded, and each second MOS transistor may consist of a pMOS transistor having its source grounded.
Each third MOS transistor may consist of an nMOS transistor.
Each first MOS transistor may consist of an nMOS transistor having its source connected to a supply voltage, and each second MOS transistor may consist of a pMOS transistor having its source connected to the supply voltage.
Each third MOS transistor may consist of a PMOS transistor.
USPTO Backgrounds
USPTO Backgrounds