Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et at, in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al, describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002, IEEE International Solid, State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Various signal processing methods are used for storing data in memory devices and for retrieving data from memory devices. For example, PCT International Publication WO 2007/132453, whose disclosure is incorporated herein by reference, describes various methods and systems for estimating and canceling distortion in memory devices. Methods for estimating and canceling non-linear distortion effects are described, for example, in PCT International Publication WO 2008/026203, whose disclosure is incorporated herein by reference.
U.S. Pat. No. 7,321,509, whose disclosure is incorporated herein by reference, addresses shifts in the apparent charge stored on a floating gate of a non-volatile memory cell, which can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. A read process for a given memory cell takes into account the programmed state of an adjacent memory cell, in order to compensate for the coupling. U.S. Pat. No. 7,289,344, whose disclosure is incorporated herein by reference, describes another read process, which takes into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell.
U.S. Pat. No. 7,177,195, whose disclosure is incorporated herein by reference, describes methods in which storage elements are read multiple times and the results are accumulated and averaged to reduce the effects of noise or other transients that may adversely affect the quality of the read. Some methods perform full read and transfer of the data from the storage device to the controller device, with averaging performed by the controller. Other methods perform a full read of the data, with the averaging performed by the storage device. Other methods perform one full read followed by a number of faster re-reads exploiting the already established state information. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics.
In some applications, the data stored in a memory device is encoded with an Error Correction Code (ECC). PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method, in which data is encoded using an ECC and stored as first analog values in respective analog memory cells of a memory device. After storing the encoded data, second analog values are read from the respective memory cells. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.
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