Wafer level chip scale packages (WLCSP), thermal leadless array (TLA) packages and leadframe-based packages, such as high density leadframe array (HLA) packages, are popular packaging solutions for high I/O devices in the industry. However, existing WLCSP, TLA and leadframe-based packages suffer from several disadvantages. For example, the size of WLCSP is limited due to board level reliability, particularly for the larger size dies which face warpage issue. The die warpage weakens the connection structure between the bumps and printed circuit board (PCB) pads. Fine pitch bumping is also desired for these packages. However, current PCB module technology is not prepared to accommodate smaller pitch size. Therefore, the size of the die may not be reduced too much for warpage control. On the other hand, there is a need to increase the robustness of the TLA and HLA packages.
From the foregoing discussion, there is a desire to provide an improved package having higher I/O counts, fine pitch and flexible fan-out routings and with enhanced package level and PCB level reliability. It is desirable to provide simplified methods to produce a reliable package with better process-ability and which are able to bridge the conflict between the shrinking bump pitch and PCB large pitch issues. It is also desirable to have methods for forming semiconductor packages which are relatively low cost and which offer the flexibility for customization according to design requirements.
USPTO Backgrounds
USPTO Backgrounds