1. Field of the Invention
The present invention relates to the electronics field. More specifically, the present invention relates to flash memory devices.
2. Discussion of the Related Art
Flash memory devices are non-volatile memories wherein each single cell may be programmed electrically, but a large number of cells, forming a block, have to be erased at the same time. Typically, each cell consists of a floating gate MOS transistor, which stores a logic value defined by its threshold voltage (which depends on the electric charge stored on the floating gate). Particularly, in a flash memory device with NAND architecture, the cells are grouped in strings (or stacks), each one consisting of a set of cells that are connected in series. The main advantage of such architecture is the reduced area occupation, essentially due to the reduction of both the contacts number and the cells size. This makes the NAND memory devices particularly advantageous in a number of applications such as memory cards, memories of digital video-cameras and of audio recorders.
The cells are generally erased by applying a single blind erasing pulse to the whole block, which erasing pulse reduces the threshold voltages of the cells below an erase reference value (e.g., 0V). The erasing pulse has to be dimensioned in order to guarantee the erasing of all the cells of the block in the worst conditions, so that it normally brings the threshold voltages of some erased cells to very low values. In such a way, it is obtained a statistical distribution of the threshold voltages of the erased cells (typically, having a roughly Gaussian shape) with a long tail due to the cells having the lowest threshold voltages; this erased distribution is then very large (for example, with a width ranging from 4V to 5V), typically of an order of magnitude higher than each distribution of the threshold voltage of the cells when programmed.
The width of the erased distribution is a problem because of the capacitive coupling between the floating gates of adjacent cells. Indeed, the threshold voltage of each cell dependents non-uniquely on the electric charge stored in its floating gate but also on the electric charges stored in the floating gates of the adjacent cells. Such effect modifies the threshold voltage of the cell whenever the adjacent cells are programmed (being more evident in the NAND memory devices because of their high integration). The suffered variation increases with the amplitude of the gap of the threshold voltages of the adjacent cells. Therefore, the problem is particularly acute when the cells that are programmed start from a very low original threshold voltage. The above-described variation of the threshold voltage can cause an undesired change of the logic value stored in the cell.
Such problem is experienced in standard NAND memory devices but it is more and more limiting in multi-level NAND memory devices wherein each cell stores multiple bits (since the margins that are used for discriminating the different stored logic values are reduced).
In the state of the art, in order to limit the capacitive coupling effect, the cells undergo a so-called “soft-compacting” operation (also known as soft-compression operation) after being erased. For this purpose, a reduced program pulse is indiscriminately applied to all the cells of the block until a predetermined guard value (such as −1V), lower than the erase reference value, is reached. This verification is typically performed at the string level; therefore, as soon as the threshold voltage of at least one cell of each string reaches the guard value, the whole string is not conductive and its soft-compacting operation is stopped. As a result, the threshold voltages of the cells of each string as a whole are shifted accordingly; this causes a shifting and a slight compacting of the whole erased distribution.
However, this solution is not satisfactory. Indeed, the erased distribution substantially maintains the same shape and remains too large with a width (e.g., of 3V) of the same order of magnitude as beforehand, thus leaving unchanged the effects due to the capacitive coupling.
For obtaining a significant reduction of the width of the erased distribution, the above-mentioned verification should have to be applied at the level of every single cell; indeed, in this way its threshold voltage could be brought to the desired value, so as to compact the erased distribution within a suitable range.
However, this solution is untenable in practice, since it would require the verification of all the cells of the block individually, with a detrimental impact on the erasing time of the flash memory device.
USPTO Backgrounds
USPTO Backgrounds