This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2000-367585 filed on Dec. 1, 2000; the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a hybrid integrated circuit with an ASIC and an FPGA and an electronic circuit device.
2. Description of the Related Art
In the recent years, the semiconductor integrated circuits have been broadly utilized which are called ASICs (Application Specific Circuits) in contrast with general purpose LSIs (Large Scale Integrated Circuits). Conventionally, there are two primary approaches, as employed for the purpose of reducing the development time, to developing integrated circuits called ASICs, i.e., the use of gate arrays and the use of standard cells.
Gate arrays are integrated circuits having a fixed number of identical sites arranged in a regular manner, each site comprising a number of simple circuit elements. The circuit elements are configured in a manner which enables easy implementation of common logic circuits such as transfer gates, inverters, NAND gates, etc., depending upon how they are connected. A gate array can then be used to implement a specific circuit design simply by specifying the interconnection between the otherwise standard circuit elements. The particular interconnections of the circuit elements that are necessary to achieve a design are typically expressed as a netlist. Another approach to the design of ASIC integrated circuits is the use of standard cells. Like gate arrays, standard cell designs rely on a set of predefined circuit elements called standard cells with which to implement the design. Standard cells have been stored in a library set and are retrieved from the library set as specified by the netlist of the design. Unlike gate arrays, however, the complexity of standard cells can range from simple logic gates such as those found in gate arrays to block-level components such as RAMs, ROMs, PLAs and Maga-cells such as CPU cores.
Generally speaking, the packing density of ASIC is high to accommodate high performance hardware macrocells resulting in a higher cost performance and a shorter development time.
On the other hand, FPGAs (Field Programmable Gate Arrays) have attracted interests of engineers since FPGAs are designed to be configurable by a user while they are slower and more expensive than ASICs but require less development time and cost dispensing fabrication of a prototype (ES). Other advantages of FPGAs are quick implement of a specification, lower inventory risks, easy design changes and faster delivery of functional units to market. However, in the case of ASICs, the user must design or obtain masks for a small number of prototype samples requiring substantial development time and costs while, in the case of FPGAs, the general purpose device is generally not as fast as an ASIC with a number of useless elements and tends to be costly with quantity production.
An aspect of the present invention provides a hybrid integrated circuit comprising: a common substrate on which an electrode pattern is formed; a first monolithic semiconductor integrated circuit designed by the use of an ASIC technology and mounted on said common substrate; a second monolithic semiconductor integrated circuit designed by the use of an FPGA technology and mounted on said common substrate; and external terminals provided for said common substrate; wherein said first monolithic semiconductor integrated circuit and said second monolithic semiconductor integrated circuit cooperate with each other by exchanging signals through the electrode pattern of said common substrate in order to implement a predetermined operational specification, wherein said second monolithic semiconductor integrated circuit is provided with a storage element which is rewritable by means of a control signal given through said external terminal in order to store circuit configuration data with which internal connections of said second monolithic semiconductor integrated circuit are modified to form a hardware configuration within said second monolithic semiconductor integrated circuit corresponding to said predetermined operational specification, and wherein said first monolithic semiconductor integrated circuit operates by using part of the storage element of said second monolithic semiconductor integrated circuit as a storage area for storing data required for operation of said first monolithic semiconductor integrated circuit.
Another aspect of the present invention provides an electronic circuit device provided with a plurality of electric elements including a hybrid integrated circuit mounted on a circuit board on which an electrode pattern is formed, wherein said hybrid integrated circuit comprises a common substrate on which an electrode pattern is formed; a first monolithic semiconductor integrated circuit designed by the use of an ASIC technology and mounted on said common substrate; a second monolithic semiconductor integrated circuit designed by the use of an FPGA technology and mounted on said common substrate; external terminals provided for said common substrate; and an insulating material encapsulating said first monolithic semiconductor integrated circuit and said second monolithic semiconductor integrated circuit, wherein said second monolithic semiconductor integrated circuit is provided with a storage element which is rewritable by means of a control signal given through said external terminal in order to store first circuit configuration data with which internal connections of said second monolithic semiconductor integrated circuit are modified to form a hardware configuration within said second monolithic semiconductor integrated circuit corresponding to a basic operational specification for supporting a basic function, wherein said first monolithic semiconductor integrated circuit and said second monolithic semiconductor integrated circuit cooperate with each other by exchanging signals through the electrode pattern of said common substrate in order to implement said basic operational specification, wherein said circuit board is further provided with an extended electrode pattern for accommodating an optional electric element which can be used in order to implement an optional function and said second monolithic semiconductor integrated circuit is capable of storing second circuit configuration data with which internal connections of said second monolithic semiconductor integrated circuit are modified to form a hardware configuration within said second monolithic semiconductor integrated circuit corresponding to an extended operational specification supporting said optional function in addition to said basic function, and wherein, in the condition that said optional electric element has been mounted on said extended electrode pattern and that said second circuit configuration data has been stored in said storage element of said second monolithic semiconductor integrated circuit, said electronic circuit device is capable of operating in accordance with said extended operational specification.
A further aspect of the present invention provides a hybrid integrated circuit comprising: a common substrate on which an electrode pattern is formed;
a first monolithic semiconductor chip designed by the use of an ASIC technology and mounted on said common substrate; a second monolithic semiconductor chip designed by the use of an FPGA technology and mounted on said common substrate; and external terminals provided for said common substrate; and an insulating material encapsulating said first monolithic semiconductor chip and said second monolithic semiconductor chip, wherein said second monolithic semiconductor chip is provided with a storage element which is rewritable by means of a control signal given through said external terminal in order to store circuit configuration data with which internal connections of said second monolithic semiconductor chip are modified to form a hardware configuration within said second monolithic semiconductor chip corresponding to a predetermined operational specification, and wherein said first monolithic semiconductor chip and said second monolithic semiconductor chip cooperate with each other by exchanging signals through the electrode pattern of said common substrate in order to implement said predetermined operational specification.
USPTO Backgrounds
USPTO Backgrounds