Recently, there is a precipitous demand for miniaturization, reduction in thickness and increase in density of electronic equipment. On the other hand, an operating speed as well as an increase of terminals due to advanced functions of the semiconductor element is enhanced, as a result of which the reduction in thickness and increase in density, in particular, are required of the semiconductor element. To achieve the reduction in thickness and size of the electronic equipment, attention is focused on having component parts, so far arranged on the wiring substrate surface, embedded within the interior of the wiring substrate, so as to reduce the thickness of the electronic equipment.
In Patent Document 1, there is disclosed a substrate technique that uses a vacuum press. A semiconductor element is enclosed in a lower layer wiring substrate formed of an epoxy resin and glass fibers. A pre-preg of substantially the same composition as that of the lower layer wiring substrate and the semiconductor element is used. For enclosing the semiconductor element, the portion of the pre-preg accepting the semiconductor element has been removed.
In Patent Document 2, there is disclosed a structure of a wiring substrate in which the semiconductor chip is enclosed. A reinforcement unit is embedded in an insulation layer in which the semiconductor chip is embedded.
In Patent Document 3, there is disclosed a substrate technique in which a semiconductor element is bonded to a first sheet, a second sheet having an opening is placed thereon, and an electrically conductive third sheet is further placed thereon. The resulting product is thermally pressed together in a lump to get the semiconductor element enclosed in the resulting structure.
In Patent Document 4, a work sheet composed of a glass cloth impregnated with synthetic resin is used. The glass cloth is formed by weaving glass fibers in a lattice shape. The work sheet is cut into a plurality of separated pieces of insulation substrates so that the lateral side of each piece of insulation substrate extends for intersecting the placement direction of the glass fibers. The through-holes that are to become side through-holes and a conductor circuit are formed on each piece of insulation substrate. Each piece of insulation substrate is cut out in the direction intersecting the glass giber placement direction of the glass cloth, such as at 40° to 50°, in such a manner that each of the through-holes is halved, in order to complete the separated pieces of insulation substrate.
[Patent Document 1]    JP Patent Kokai Publication No. JP-P2002-270712A
[Patent Document 2]    JP Patent Kokai Publication No. JP-P2006-261246A
[Patent Document 3]    JP Patent Kokai Publication No. JP-P2004-335641A
[Patent Document 4]    JP Patent Kokai Publication No. JP-A-8-139424
[Patent Document 5]    JP Patent Kokai Publication No. JP-A-10-51105
[Patent Document 6]    JP Patent Kokai Publication No. JP-A-9-64493
[Patent Document 7]    JP Patent Kokai Publication No. JP-A-6-334334
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