A half-flash type analog/digital converter is equipped with a comparator, encoder, voltage divider, etc.
FIG. 1 is a constitutional diagram showing an example of a conventional half-flash type analog/digital converter.
The half-flash type analog/digital converter has: a voltage divider that receives voltages V.sub.RS and V.sub.RT and generates reference voltages for comparison by dividing the differential voltage; chopper type comparator groups 106-108 for comparing reference voltages from the voltage divider 105 and analog input signals A.sub.IN ; an encoder 103 for outputting digital signals D.sub.LSB0 of the least significant bit side based on the output result of the chopper type comparator group 106; an encoder 102 for outputting digital signals D.sub.LSB1 of the least significant bit side based on the output result of the chopper type comparator group 107; and digital signals D.sub.MSB of the most significant bit side based on the output result of the chopper type comparator group 108.
The voltage divider 105 has resistors R.sub.1 -R.sub.m connected in series for dividing the voltages V.sub.RB and V.sub.RT.
Resistors r.sub.11 -r.sub.1n and r.sub.1n+1, connected in series for further dividing the terminal voltage of the resistor R.sub.1, are connected in parallel with resistor R.sub.1.
Resistors r.sub.21 -r.sub.2n and r.sub.2n+1, connected in series for further dividing the terminal voltage of the resistor R.sub.2, are connected in parallel with resistor R.sub.2.
The resistors R.sub.3 -R.sub.m-1 are also similar.
Resistors r.sub.m1-r.sub.mn and r.sub.mn+1, connected in series for further dividing the terminal voltage of the resistor R.sub.m, are connected in parallel with resistor R.sub.m.
One terminal of the resistor r.sub.M1 is connected to one terminal of the resistor R.sub.M, and the other terminal of the resistor r.sub.M1 is connected to the inverting input terminal of a chopper type comparator C.sub.11 via a switching means S.sub.M1.
One terminal of the resistor r.sub.M2 is connected to the other terminal of the resistor R.sub.M1, and the other terminal of the resistor r.sub.M2 is connected to the inverting input terminal of a chopper type comparator C.sub.12 via a switching means S.sub.M2.
The resistors r.sub.M3 -r.sub.Mn-1 are also similar.
One terminal of the resistor r.sub.Mn is connected to the other terminal of the resistor r.sub.Mn-1, and the other terminal of the resistor r.sub.Mn is connected to the inverting input terminal of the chopper type comparator C.sub.1n via the switching means S.sub.Mn, where 1.ltoreq.M.ltoreq.m, and M and m are integers of 2 or higher.
The inverting input terminals of the chopper type comparators C.sub.11 -C.sub.1n and the inverting input terminals of the chopper type comparators C.sub.m1 -C.sub.mn are respectively connected.
The analog input signal A.sub.IN is supplied to the non-inverting input terminal of the chopper type comparators C.sub.11 -C.sub.1n, C.sub.m1 -C.sub.mn, and C.sub.R1 -C.sub.Rm.
One terminal of the resistors R.sub.1 -R.sub.m is respectively connected to the inverting input terminals of the chopper type comparators C.sub.R1 -C.sub.Rm.
The chopper type comparator groups 106 and 107 respectively have the chopper type comparators C.sub.11 -C.sub.1n and C.sub.m1-C.sub.mn of the least significant bit side.
The chopper type comparator group 108 has the chopper type comparator C.sub.R1 -C.sub.Rm of the most significant bit side.
The switching means S.sub.11 -S.sub.1n, etc., S.sub.m1 -S.sub.mn of the voltage divider 105 are controlled based on the outputs of the chopper type comparators C.sub.R1 -C.sub.Rm of the most significant bit side.
For example, in case the output of the chopper type comparator C.sub.R1 is low and the outputs of the chopper type comparators C.sub.R2 -C.sub.Rm are high, the switching means S.sub.11 -S.sub.1n are conductive, and the digital signal D.sub.LSB0 of the least significant bit side is generated.
For example, in case the outputs of the chopper type comparator C.sub.R1 -C.sub.Rm are low, the switching means S.sub.m1 -S.sub.mn are in a conductive means, and the digital signal D.sub.LSB0 of the least significant bit side is generated.
In the half-flash type analog/digital converter of FIG. 1, the digital signal D.sub.LSB0 and the digital signal D.sub.LSB1 of the least significant bit side are used in alternating fashion for high-speed processing, and one of the digital signals of the least significant bit side and the digital signal D.sub.MSB of the most significant bit side are simultaneously output, so that an output signal of the half-flash type analog/digital converter is obtained.
FIG. 2 is a circuit diagram showing a conventional chopper type comparator used in the half-flash type analog/digital converter of FIG. 1. FIG. 3 is a circuit diagram showing a detailed example of the chopper type comparator of FIG. 2.
23 is the supply terminal for a power supply voltage V.sub.CC. 22 is an output terminal. GND is ground potential. PTr is a P channel type field-effect transistor. NTr is a N-channel type field-effect transistor.
The reference voltage V.sub.REF is supplied to the input terminal 21, and the analog input signal A.sub.IN is supplied to the input terminal 20.
The chopper type comparator has: a first switching means SW1 for interrupting the reference voltage V.sub.REF ; a second switching means SW2 which is connected in parallel with said first switching means SW1 and interrupts the analog input signal A.sub.IN in comparative symmetry; a first capacitor C1 in which one terminal is connected to a connecting point P with the above-mentioned second switching means SW2; a first inverter INV1 in which the input terminal is connected to the other terminal of the above-mentioned first capacitor C1; a third switching means SW3 interposed between the output terminal and the input terminal of the above-mentioned first inverter INV1; a second capacitor C2 in which one terminal is connected to the output terminal of the above-mentioned first inverter INV1; a second inverter INV2 in which the input terminal is connected to the other terminal of the above-mentioned second capacitor C2; a fourth switching means SW4 interposed between the output terminal and the input terminal of the above-mentioned second inverter INV2; and a third inverter INV3 in which the input terminal is connected to the output terminal of the above-mentioned second inverter INV2.
The third inverter INV3 outputs an output signal V.sub.OUT.
FIG. 4 is a timing diagram explaining an example of the operation of each switching means SW1-SW4 of the chopper type comparator of FIG. 2.
First, when the analog input period T.sub.A of the timing diagram starts, the switching means SW2 and SW3 are set to conductive, and an analog input signal A.sub.IN is input. Then, the capacitor C1 is charged, and the switching means SW4 is set to conductive with a slight delay.
In case the switching means SW2 and SW3 are conductive, since the input and output terminals of the inverters INV1 and INV2 are short-circuited, the voltage of the input and output terminals is 1/2 of the power supply voltage V.sub.CC of the inverters INV1 and INV2.
When the analog input period T.sub.A has ended, the switching means SW2 is nonconductive.
Next, the switching means SW3 is set to conductive from nonconductive for the holding period T.sub.H, and the switching means SW4 is then set to nonconductive from conductive, so that all the switching means SW1-SW4 are set to nonconductive. In this way, the voltage level of the analog input signal A.sub.IN is held to the capacitor C1.
Next, the switching means SW1 is set to conductive for a reference voltage input period T.sub.V, and the reference voltage V.sub.REF is input.
Thus, a prescribed voltage corresponding to the difference of the voltage level of the analog input signal A.sub.IN and the reference voltage V.sub.REF is applied to the capacitor C1, so that the prescribed voltage is amplified by the inverter INV1.
Then, the comparison result is output as the output signal V.sub.OUT to the output terminal 22 via the next capacitor C2 and inverters INV2 and INV3.
The analog input period T.sub.A, holding period T.sub.H, and reference voltage input period T.sub.V are repeated in order, and the analog input signal A.sub.IN and the reference voltage V.sub.REF are successively compared. The output signal V.sub.OUT showing the comparison result is then output.
Since the chopper type comparator has a capacitor and charges and discharges the capacitor, a prescribed time is required charging and discharging in terms of the relationship of the time constant.
For this reason, in case the period is short, that is, in case a high-speed operation is carried out, the time for charging the capacitor C1 by the analog input signal A.sub.IN is insufficient, and the voltage level different from the voltage level of the analog input signal A.sub.IN is held.
Also, the output voltage V.sub.OUT is output in a state in which the charging and discharging time of the capacitor C2 is insufficient.
Furthermore, it is necessary to input the analog input signal A.sub.IN after the comparison in terms of operation of the chopper type comparator, and if the operation period is shortened, the analog input signal A.sub.IN is input before the voltage corresponding to the comparison result is held by the capacitor C2, that is, before the capacitor C2 is completely reset. In this case, the voltage being held by the capacitor C1 is a voltage different from the voltage of the analog input signal A.sub.IN.
Thus, an offset voltage is generated in the chopper type comparator, so that the offset voltage is also generated in the half-flash type analog/digital converter.
In particular, in the half-flash type analog/digital converter, the reference voltage of the chopper type comparator of the least significant bit side is changed by switching the switching means of the voltage divider.
For example, in FIG. 1, case switching means S.sub.11 -S.sub.1n of the voltage divider 105 are set to nonconductive from conductive and the switching means S.sub.m1 -S.sub.mn are set to conductive from nonconductive, the reference voltage of the chopper type comparators C.sub.11 -C.sub.1n of the least significant bit side is changed.
FIG. 5 is a voltage waveform diagram showing the voltage waveform of each of the chopper type comparators of FIG. 2. It shows an example of the voltage waveform of the input terminal 21 of the reference voltage V.sub.REF of the chopper type comparator and the connecting point P between the switching means SW1 and SW2.
In the voltage waveform diagram, for convenience of explanation, the analog input signal A.sub.IN is set to a fixed value of 1.6 V, and the reference voltage V.sub.REF varies.
The reference voltage V.sub.REF varies from 1.46 V to 1.74 V when the time T is 250 nS.
V.sub.R is the input terminal voltage of the reference voltage V.sub.REF of the chopper type comparator, and V.sub.P is the voltage of the connecting point P.
In the voltage waveform diagram of FIG. 5, when the analog input signal A.sub.IN is input and the voltage level is held, the step difference of the voltage corresponding to about 1.3 LSB is generated in the voltage V.sub.P before and after switching the reference voltage V.sub.REF.
An incomplete reset of the capacitor 2 is considered to be the largest cause of the step difference (noise) of the voltage. In case the operation period of the chopper type comparator is short, if the holding operation of the analog input signal A.sub.IN is carried out before the reset operation of the capacitor 2 is completed, the holding voltage of the capacitor C1 is changed by electric charges remaining in the capacitor C2.
As shown in FIG. 5, when the reference voltage V.sub.REF varies, since the output of the chopper type comparator is reversed, the voltage (charge) held to both terminals of the capacitor C2 is also reversed. Therefore, in case the operation period of the chopper type comparator is short, since the analog input signal A.sub.IN is held in a state in which the reset operation of the capacitor C2 is not completely carried out, the reversed voltage (charge) remaining in the above-mentioned capacitor C2 has an influence on the holding voltage, and a shift (step difference) of the holding voltage as shown in FIG. 5 is generated.
In other words, since the size of the reference voltage V.sub.REF varies before and after switching of the switching means of the voltage divider 105, the size of the offset varies according the influence so that it is difficult to operate the half-flash type analog/digital converter at high speed.
The purpose of the present invention is to provide a chopper type comparator that can be operated at higher speed, compared with the conventional type.
USPTO Backgrounds
USPTO Backgrounds