A significant trend throughout integrated circuit (IC) development is the downsizing of IC components. These integration improvements are two-dimensional (2D) in nature where the ICs are integrated on a surface of a semiconductor wafer. Although dramatic improvement in lithography has enabled greater results in 2D IC formation, there are physical limits to the density that can be achieved in two dimensions. Also, when more devices are put into one chip, more complex design costs are required.
In an attempt to further increase circuit density, three-dimensional (3D) ICs have been developed. For example, flip-chip packaging utilizes conductive bumps or conductive pillars to establish electrical contact between a chip and a semiconductor substrate. However, under a thermal cycle or a stress testing, an interface between the conductive pillars and other materials is subject to delamination or cracks. The interface is split by the stress and forms a crack, which extends to the conductive pillars or underlying wirings. The crack will affect the electrical performance and reliability of devices.
USPTO Backgrounds
USPTO Backgrounds