1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly, to an Electrically Erasable Programmable Read-Only Memory (EEPROM) and to methods of operating and fabricating the same.
A claim of priority is made to Korean Patent Application No. 10-2005-0127770, filed on Dec. 22, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
Semiconductor memory devices are generally classified as either volatile memory devices which lose stored data when the supply of power is interrupted, or non-volatile memory devices which retain stored data even when the supply of power is interrupted. Electrically erasable and programmable read-only memories (EEPROMs) are one kind of non-volatile memory device.
An EEPROM generally adopts a stacked gate structure within each unit memory cell, where the stacked gate structure includes a floating gate and a control gate formed over the floating gate.
In the meantime, different manufacturing techniques may be used to form a semiconductor device. One such technique includes a System on Chip (SOC). In a SOC, a logic device, a memory device, and other such components of a semiconductor device, are embodied in a single chip. Because all the functions of these components are integrated on a single chip, the size of the device may be reduced significantly. Furthermore, the manufacturing costs of the semiconductor device may also be reduced since all the functionality of these components is present in one chip.
Because the SOC includes a number of devices, it would be preferable if the component devices on the SOC could be fabricated using identical processing techniques. For example, when the SOC includes a logic device and an EEPROM memory device, it would be advantageous if both the logic device and the EEPROM were fabricated using identical processing techniques. However, there may be problems associated with using the same processing techniques for different components on a SOC. This is primarily due to the differing structures of the components on the SOC. For example, a logic device utilizes a transistor having a single gate structure, while an EEPROM utilizes a transistor having a stacked gate structure. These different structures can significantly complicate manufacturing of a SOC.
In an effort to overcome this problem, an EEPROM having a single gate structure has been studied. By adopting an EEPROM with the single gate structure, the SOC can be manufactured using the same CMOS process that is also used to fabricate the logic device.
FIGS. 1A and 1B illustrate a conventional technique for data writing and data erasing of an EEPROM having a single gate structure. Referring to FIG. 1A, a P-type semiconductor substrate 100 is provided. Furthermore, N-type source/drain regions 117 and an N-well contact region (115) are formed in the semiconductor substrate 100. In addition, an N-well 110 is formed in the semiconductor substrate 100. Furthermore, P-type source/drain regions 113 are formed in the N-well 110. Finally, an N-gate 127 and a P-gate 123 are formed on the semiconductor substrate 100. In the EEPROM shown in FIG. 1A, the N-gate 127 and the P-gate 123 are portions of a single floating gate.
Data is written on the EEPROM device as follows. First, a programming voltage Vp that is a positively high voltage is applied to the P-type source/drain regions 113 and the N-well contact region 115. By doing so, the programming voltage Vp is supplied to the N-well 110, and is then capacitively coupled to the P-gate 123, i.e., the floating gate. Furthermore, the N-type source/drain regions 117 and the semiconductor substrate 100 are grounded. Accordingly, a high electric field is formed between the N-gate 127 and the semiconductor substrate 100. Therefore, electrons of the semiconductor substrate 100 are subjected to Fowler-Nordheim (F-N) tunneling to the N gate 127, i.e., the floating gate, and are stored in the floating gate.
Referring to FIG. 1B, the erasing of the data from the EEPROM will now be described. An N-well contact region 115 and the P-type source/drain regions 113 are grounded. By doing so, a ground voltage is supplied to the N-well 110, and is then capacitively coupled to the P-gate 123, i.e., the floating gate. In addition, an erasing voltage Ve that is a positively high voltage is applied to the N-type source/drain regions 117. Furthermore, the semiconductor substrate 100 is grounded. As a result, a high electric field is formed between the N-type source/drain regions 117 and the N-gate 127. Therefore, the electrons of the N-gate 127, i.e., the floating gate, are subjected to F-N tunneling to the N-type source/drain regions 117. This F-N tunneling erases the charges stored in the floating gate.
While the above-mentioned techniques may be used to program data to and erase data from an EEPROM having a single gate structure, these techniques have several shortcomings. For example, the high voltage applied to the N-type source/drain regions 117 during the erasing of the data may break down a junction between the N-type source/drain regions 117 and the semiconductor substrate 100. This problem is especially acute when the EEPROM having the single gate structure is formed by CMOS processing, i.e., the junction breakdown voltage between the N-type source/drain regions 117 and the semiconductor substrate 100 may be as low as 10V or less.
USPTO Backgrounds
USPTO Backgrounds