1. Technical Field
The present disclosure relates to a power supply voltage stabilization technique for a three-dimensional integrated circuit which includes a plurality of stacked semiconductor chips.
2. Related Art
A circuit which is made of a plurality of semiconductor chips stacked and connected to each other by using TSVs (Through Silicon Vias), microbumps, and the like is called “three-dimensional integrated circuit”. Since the three-dimensional integrated circuit has a plurality of semiconductor chips stacked, it has a shorter total wiring length and less power consumption per operation frequency than a circuit of a plane structure does. Therefore, the three-dimensional integrated circuit is a useful technique particularly for a general purpose processor of a high operation frequency and the like.
On the other hand, the three-dimensional integrated circuit has a risk of having the power supply voltage dropped in some semiconductor chips when load to the other semiconductor chips changes. Particularly in an advanced general purpose processor which consumes a high current, the power supply voltage tends to drop. Therefore, in ordinary cases, in order to stabilize the voltage applied to the load, a capacitor is installed on a substrate on which the three-dimensional integrated circuit is stacked so that the charge capacity of the capacitor compensates for the voltage drop. That kind of capacitor is called “decoupling capacitor”.
The nearer to the load the capacitor is installed, the lower the inductor value is required for the wiring and the more the amount of charge is allowed to flow into the capacitor, therefore, the capacitor installed near to the load is effective as a decoupling capacitor (for example, see Chapter 3, “EMC architecture of printed circuit board” by Mark I. Montrose, published by Ohmsha Ltd.
Techniques of installing a decoupling capacitor near to the load are disclosed (for example, see Japanese Patent Laid-Open Publication No. 2005-244068). That semiconductor device is a stacked semiconductor device which has a plurality of semiconductor chips stacked and has a decoupling capacitor formed near to each of the semiconductor chips by having a film capacitor interposed between the chips.
However, the semiconductor device disclosed in Japanese Patent Laid-Open Publication No. 2005-244068 needs film capacitors and also requires an additional process step of interposing the film capacitor between the chips. Those factors increase the cost of the semiconductor device. Further, since the semiconductor device disclosed in Japanese Patent Laid-Open Publication No. 2005-244068 has additional contacts between each of the chips and the film as compared to the case where the chips are directly connected, the yield of the semiconductor device is deteriorated, which is another factor of increasing the cost.
On the other hand, techniques of reducing the cost by using wiring material in a semiconductor chip as an electrode of a capacitor are proposed. For example, there is a technique of forming a decoupling capacitor of high capacity by arranging metal wiring layers of the semiconductor chips, which are to be stacked, opposite to each other and bonding the semiconductor chips by an adhesive made of high dielectric material (for example, see WO 2005-122257).
However, since the method disclosed in WO 2005-122257 forms a capacitor of high capacity by having a high dielectric film between the semiconductor chips, the method needs materials and process steps different from those needed in ordinary three-dimensional stacking. Also, since an ordinary signal line is also arranged between the semiconductor chips in addition to a power supply and a ground in the three-dimensional integrated circuit, the arrangement of the high dielectric film increases a parasitic capacitance of the signal line between the semiconductor chips, which results in a greater signal delay.
USPTO Backgrounds
USPTO Backgrounds