The invention relates generally to universal shift registers. More specifically, the invention concerns high speed shift registers with a plurality of selectable operating modes implemented by an array of high speed transmission gates.
Conventional "universal shift registers" provide a plurality of different and individually selectable operating modes, including, for example, parallel input, shift-right, shift-left, and hold, each mode selected in accordance with a user-selectable code input to the register via a decoder associated with the universal shift register. To effect the various operating modes, conventional universal shift registers have utilized combinatorial logic gates to direct data among the register stages and into and out of the register in accordance with the desired register operating mode. Use of such conventional shift register operating mode logic leads to disadvantages including increased propagation delay, complex random layouts for integrated circuit implementation, long interconnect line lengths between components adding to propagation delay and reduced testability and increased probability of deleterious race conditions.
Digital transmission gate switch matrixes for high speed data systems are known. See, for example, A GaAs Data Switching IC for a Gigabits Per Second Communication System, Nakayama et al., IEEE Journal of Solid State Circuits, Vol. SC-21, Number 1, Feb. 1986. However, use of such matrices in implementing various modes of shift register operation is believed heretofore unknown.
USPTO Backgrounds
USPTO Backgrounds