1. Field of the Invention
This invention relates generally to semiconductors and fabrication methods therefor, and more particularly, to a semiconductor device and a fabrication method therefor with the use of CMP.
2. Description of the Related Art
In order to enhance the performance of semiconductor devices and reduce the costs thereof, development of the layout rule is in progress for the purposes of reducing the size. In this development, planarization technique plays an important role. For instance, if poor planarization is provided on a plane on which the lithography process is performed, there will cause problems of misaligned focus, difficulty in the formation of a minute pattern, and the like. As a representative planarization method, polishing with the use of Chemical Mechanical Polishing (CMP) is known.
With reference to FIG. 1A (Prior Art) through FIG. 3C (Prior Art), a description will be given of a planarization method with the use of a conventional CMP technique. FIG. 1A (Prior Art) through FIG. 1C (Prior Art) show a case where a silicon oxide film is embedded for element isolation (conventional technique 1), and an insulating film is planarized by using a silicon nitride film as a stop layer. Referring now to FIG. 1A (Prior Art), a silicon nitride film is formed on a semiconductor substrate 10 as a stop layer 12 used for polishing. A given region of the stop layer 12 is removed, and a trench is formed in the semiconductor substrate 10. A silicon oxide film is formed in the trench and on the stop layer 12 as a cover film 16. Referring to FIG. 1B (Prior Art), the cover film 16 is polished to the stop layer 12 by CMP. Referring to FIG. 1C (Prior Art), the stop layer 12 is removed and an embedded silicon oxide film 18 is provided in the trench formed in the semiconductor substrate 10.
FIG. 2A (Prior Art) and FIG. 2B (Prior Art) show a case where an insulating film provided between metal layers on the substrate is planarized by using the metal layers as a stopper (conventional technique 2). Referring now to FIG. 2A (Prior Art), metal layers 30 made of polysilicon films are formed on the semiconductor substrate 10, and a cover film 34 of, for example, a silicon oxide film or the like is formed so as to cover the metal layers 30. Referring to FIG. 2B (Prior Art), the insulating film 34 is polished by CMP, and insulating film layers 36 are formed between the metal layers 30.
FIG. 3A (Prior Art) through FIG. 3C (Prior Art) show a case where a multilayer interconnection is formed and the insulating film is planarized without the stop layer (conventional technique 3). Referring now to FIG. 3A (Prior Art), wiring layers 50 made of aluminum are formed on the semiconductor substrate 10, and an interlayer insulating film 52 is formed. Referring to FIG. 3B (Prior Art), wiring layers 60 are formed on the interlayer insulating film 52. An interlayer insulating film 65 of a silicon oxide film or the like is formed to cover the wiring layers 60. Referring to FIG. 3C (Prior Art), the interlayer insulating film 65 is polished by CMP. Subsequently, on the interlayer insulating film 65, the wiring layer and the interlayer insulating film are provided on an upper layer, thereby making it possible to form a desired multilayer interconnection.
Also, Japanese Patent Application Publication No. 2004-146582, Japanese Patent Application Publication No. 2004-228519, and Japanese Patent Application Publication No. 2001-85373 disclose polishing methods in which a silicon nitride film is employed as a stop layer with the use of an abrasive that includes abrasive grains of cerium oxide, also known as ceria slurry.
The conventional planarization techniques, however, have the following drawbacks. In the conventional technique 1, as shown in FIG. 1C (Prior Art), the silicon oxide film 18 is polished more than the stop layer 12 is polished. In addition, in the conventional technique 2, as shown in FIG. 2B (Prior Art), a middle portion of the insulating film 36 provided between the metal layers 30 becomes thinner. This phenomenon is called dishing. In the conventional technique 3, as shown in FIG. 3C (Prior Art), the interlayer insulating film 65 does not exhibit excellent planarization. As stated, in the conventional techniques, there is room to improve planarization properties.
USPTO Backgrounds
USPTO Backgrounds