1. Field of the Invention
The present invention relates to an electrically erasable nonvolatile semiconductor memory of the batch erasure type (hereinafter referred to as a flash memory), particularly to a flash memory in which an erasing level of each memory cell can be precisely controlled within a narrow range.
2. Description of the Related Art
An electrically erasable programable read only memory (E.sup.2 PROM) is a typical electrically erasable nonvolatile memory. In an E.sup.2 PROM, each memory cell is composed of two transistors, one of which is a selection transistor, and the other is a memory transistor having a floating gate. A threshold level with which the memory transistor turns ON when predetermined voltages are applied to the memory transistor changes whether electrons are filled in the floating gate, therefore, the ON and OFF conditions of each memory cell respectively correspond to logic values of "0" and "1". Generally, the logic value "0" corresponds to the OFF condition and the logic value "1" corresponds to the ON condition, and, in this specification, it is assumed that this relation is available. In a typical E.sup.2 PROM, an N-channel transistor is used as a memory cell. In this case, electrons are injected into the floating gate when the logic value "0" is written in the E.sup.2 PROM, and electrons are not injected into the floating gate when the logic value "1" is written, namely, no operation is carried out when the logic value "1" is stored. Usually, an operation to inject the electrons into the floating gate is called a writing operation. Conversely, electrons are withdrawn from the floating gate when stored data are erased. An operation to withdraw the electrons from the floating gate is called an erasing operation.
In the E.sup.2 PROM, each memory cell can be independently read, written and erased. However, since each memory cell is composed of two transistors, an integration of the E.sup.2 PROM is lower than that of a EPROM. A flash-type E.sup.2 PROM was proposed as a new E.sup.2 PROM having a better integration. In the following, the flash-type E.sup.2 PROM is called "flash memory".
Each memory cell of the flash memory is composed of one transistor which has a control gate, a floating gate, a drain region and a source region. In the flash memory, memory cells are arranged in a matrix, and word lines and bit lines are respectively arranged to correspond to rows and columns of the matrix. The control gates of the memory cells included in one row of the matrix are connected to the corresponding word line, and drain regions of the memory cells included in one column of the matrix are connected to the corresponding bit line. Source regions of all memory cells are connected to source lines which are commonly connected.
In the flash memory, when a memory cell is read or written, voltages corresponding to read and write operations are applied to a word line and a bit line connected to the selected memory cell, and other voltages are applied to other word lines and bit lines.
Then, all source lines are grounded whether or not they are selected. Therefore, a reading operation and a writing operation to each memory cell can be independently carried out. However, when the memory cell is erased, a selected word line is grounded and a voltage such as 6 V is applied to other word lines, a high volatge is commonly applied to the source areas via the commonly connected source lines, and all bit lines are opened whether or not they are selected. Therefore, memory cells are erased by at least a unit of the word line. In a typical flash memory, memory cells are erased by a block unit larger than a word line unit. Generally, an erasing operation requires a longer time than another operations, therefore, a total erasing time of the flash memory becomes very long if all memory cells are erased one by one. In an application of the flash memory, the total erasing time is important and it is required to be reduced, therefore, the erasing operation by a block unit can become an advantage.
In the reading operation, a sense amplifier detects a current in a bit line connected to the selected memory cell. A current flows from the selected bit line to the selected memory cell when the selected memory cell is ON, and a current does not flow when the selected memory cell is OFF. However, if one or more memory cells connected to the selected bit lines except the selected memory cell are ON, the current flows through those memory cells whether the selected memory cell is ON or OFF, therefore, the selected memory cell cannot be correctly read. Consequently, the erased memory cells are required to be ON when it is selected and also required to be OFF when it is not selected. This means that thrshold levels of the erased memory cell are required to be within a predetermined range.
Each memory cell has production variations of the characteristics of the erasing operation. The characteristic variations in the erasing operation cause differences of threshold levels of memory cells after the erasing operation because the erasing operation is carried out by a block unit. Namely, after the erasing operation, the memory cell of a high erase efficiency has a low threshold level and the memory cell of a low erasing efficiency has a high threshold level.
Therefore, there may exist erased memory cells having threshold levels over the predetermined range after the erasing operation. In the conventional flash memory, a verify operation is carried out to confirm the erasing operation. In the verify operation, a voltage less than a normal reading voltage is applied to the selected word line. When there exist unsufficiently erased memory cells, the erasing operation is repeated.
By this verify operation, it is confirmed that all erased memory cells turn ON when they are selected, namely, it is confirmed that all erased memory cells have threshold levels less than the upper level of the predetermined range. However, by the above verify operation, it is not confirmed that all erased memory cells do not turn ON when they are not to be selected, namely, it is not confirmed that all erased memory cells have threshold levels more than the lower level of the predetermined range. The erased memory cell having a threshold level less than the lower level of the predetermined range is called an over-erased memory cell. If there exist over-erased memory cells, the reading operation is disturbed.
In the writing operation, threshold levels of the written memory cells have variations. However, the written memory cell is only required to be OFF whether or not they are selected, therefore, there is no problem when all written memory cells have threshold levels more than a predetermined level.
In electrically erasable nonvolatile memories disclosed in Japanese Unexamined Patent Publication (Kokai) Nos. 1-294297, 4-3395, 4-13295 and 4-21998, levels of the bit lines or a channel current are detected during the erasing operation, and the erasing operation are stopped when those detecting values become predetermined values. In these ways, the erased levels can be more precisely controlled, however, counterplans to reduce the variations of the erased levels are not disclosed.
In electrically erasable nonvolatile memories disclosed in Japanese Unexamined Patent Publication (Kokai) No. 4-6698, the erased memory cells are discriminated whether their threshold levels are within a predetermined range, and when there exist over-erased memory cells, the writing operation and the erasing operation are carried out in a period shorter than those of the normal operations. In this way, the variation of the erased levels is reduced. However, because the erasing operation is carried out to all memory cells and a writing characteristic does not always correspond to an erasing characteristic, it is difficult to reduce the variation of the erased levels to within a narrow range. Further, the device of this document requires circuits for reading operations at different threshold levels.
In the electrically erasable nonvolatile memories disclosed in the above documents, the memory cells of the whole device or the memory cells of the whole erasing block unit are simultaneously erased. Namely, memory cells cannot be erased one by one. However, if memory cells can be erased one by one, it is easy to control the erased levels of all memory cells within a narrow range.
In Japanese Unexamined Patent Publication (Kokai) Nos. 1-259556 and 4-275457, new types of erectrically erasable nonvolatile memories are disclosed. In these memories, each memory cell includes only one memory transistor, and memory cells can be read, written and erased one by one. These memories have word lines, pairs of bit lines and source lines arranged perpendicular to said word lines, and a matrix of memory cells arranged at intersections of the word lines and the pairs of the bit lines and the source lines. Each of the memory cells includes a control gate, a floating gate, a drain region and a source region. The control gate is connected to one of the word lines, a drain region is connected to one of the bit lines, and a source region is connected to one of the source lines.
The source lines are not commonly connected, and an erasing voltage can be selectively applied to the source lines. Therefore, the memory cells can be erased one by one. Although the above documents does not disclose the reduction of the variation of the erased levels, the erased levels of the memory cells can be easily controlled within a predetermined range by respectively controling each erased level of the memory cells.
However, as described above, the erasing operation requires a longer time than another operations. Therefore, when all memory cells are erased one by one, there arises a problem that a total erasing time of these memories becomes very long. In an application of the flash memory, the total erasing time is important.
USPTO Backgrounds
USPTO Backgrounds