The present invention generally relates to semiconductor memory devices and more particularly to an improvement of a semiconductor memory device wherein bipolar transistors, p-channel metal-oxide-silicon (MOS) transistors and n-channel MOS transistors are provided on a common semiconductor substrate.
There is a semiconductor device of the type known as "BiCMOS" wherein bipolar transistors, p-channel MOS transistors and n-channel MOS transistors are provided as an integrated circuit on a common semiconductor substrate. Using such BiCMOS memory devices, versatile operational characteristic merging the advantageous feature of complementary MOS (CMOS) circuits and the advantageous feature of bipolar transistors are obtained.
In the case of semiconductor memory devices provided on a BiCMOS integrated circuit, MOS transistors are used for the memory cells and other driving circuits while bipolar transistors are used for the sense amplifiers. By adopting such a construction, an increased integration density and decreased power consumption can be achieved together with enhanced writing and reading speed.
In such a conventional semiconductor device, the writing of data into an addressed memory cell is made by causing a voltage change on a bit line connected to the addressed memory cell, while the reading of data from the addressed memory cell is made by detecting the voltage change on the bit line by the sense amplifier connected to the bit line. Thus, there is a chance that a large voltage change may occur at the input of the sense amplifier at the time of writing the data. In the case of the conventional semiconductor memory device of the BiCMOS construction, such a large voltage change at the input of the sense amplifier raises a problem in that the bipolar transistors used in the sense amplifier may be reversely biased in response to the large voltage change. In other words, there is a risk that the bipolar transistors used in the sense amplifier may be damaged or destroyed permanently because of the excessive reverse biasing applied at the time of writing the data.
Thus, there is a demand of BiCMOS semiconductor memory device wherein the risk of damaging the bipolar transistors used therein is eliminated and yet capable of operating at a high speed.
USPTO Backgrounds
USPTO Backgrounds