1. Field of the Invention
Embodiments of the invention relate to DC voltage conversion circuits that switch semiconductor switching devices to convert a DC voltage into a DC voltage having a predetermined magnitude.
2. Related Art
FIG. 7 shows a first background-art technique of this kind of DC voltage conversion circuit.
In FIG. 7, one end of an inductor 2 is connected to a positive electrode of a DC power supply 1, and a semiconductor switching device 3 such as an MOSFET is connected between the other end of the inductor 2 and a negative electrode of the DC power supply 1. A diode 4 and a capacitor 5 are connected in series to two ends (between a drain electrode d and a source electrode s) of the switching device 3. A load 6 is connected to two ends of the capacitor 5. Incidentally, in FIG. 7, the reference sign P designates a positive terminal of the DC voltage conversion circuit; N, a negative terminal thereof; and A, a parasitic inductance caused by a wiring of the circuit as will be described later.
The DC voltage conversion circuit shown in FIG. 7 is a so-called step-up chopper which converts a DC input voltage into a DC voltage higher than the DC input voltage. Operation of the circuit will be described below. Incidentally, in the following description, assume that a forward voltage drop in a PN junction of the diode etc. is neglected.
When the switching device 3 turns ON, a current flows from the DC power supply 1 back to the DC power supply 1 through the inductor 2 and the switching device 3. An input current Iin increases due to a voltage (input voltage) Vi of the DC power supply 1 added to the inductor 2. When the switching device 3 turns OFF, the current flows from the DC power supply 1 back to the DC power supply 1 through the inductor 2, the diode 4 and the capacitor 5. On this occasion, a differential voltage between a voltage (output voltage) Vo of the capacitor 5 and the input voltage Vi is applied to the inductor 2. Accordingly, as will be described later, Iin decreases due to Vo which is kept higher than Vi.
When a ratio of ON time to OFF time in the switching device 3 is controlled, the magnitude of the input current Iin can be controlled desirably. When the input current Iin is controlled in accordance with the power consumption of the load 6, the output voltage Vo can be kept at a desired value.
In addition, when the ratio of the ON time in the switching device 3 is increased, the input current Iin and further input electric power (Vi×Iin) can be theoretically increased unlimitedly. Therefore, the output voltage Vo can be controlled to have any value in a range higher than the input voltage Vi. When the ratio of the ON time in the switching device 3 is 0, i.e. when the switching device 3 does not turn ON at all, the output voltage Vo is substantially equal to the input voltage Vi.
Generally, an unintended parasitic inductance A is present on a wiring in an electric circuit. A parasitic inductance A existing in a loop circuit from the switching device 3 back to the switching device 3 via the diode 4 and the capacitor 5 is shown in FIG. 7.
FIG. 8 shows voltage and current waveforms when a current flowing into the switching device 3 is commutated to the capacitor 5 through the diode 4.
In FIG. 8, when the switching device 3 starts to turn OFF at a time instant t0, the impedance of the switching device 3 increases and a drain-to-source voltage Vds increases accordingly. When the voltage Vds exceeds the output voltage Vo at a time instant t1, the diode 4 in FIG. 7 conducts electricity so that a current i starts to flow from the switching device 3 back to the switching device 3 through the diode 4, the parasitic inductance A and the capacitor 5.
On this occasion, a voltage (so-called surge voltage) in Mathematical Expression 1 proportional to a change rate of the current i occurs in the parasitic inductance A.ΔV=L·(di/dt)  {Math. 1}
wherein the reference sign L designates an inductance value of the parasitic inductance A.
When Id designates a drain current of the switching device 3, i=Iin−Id is established. Iin may be regarded as constant in a short period of time when the surge voltage ΔV occurs. Accordingly, (di/dt) is substantially equal to a rate of decrease in Id, i.e. (−dld/dt). The surge voltage ΔV which is added to Vo is applied between the drain and the source of the switching device 3. Accordingly, the drain-to-source voltage Vds is higher than the output voltage Vo in a brief period of time after the time instant t1, as shown in FIG. 8.
When the surge voltage ΔV is large to exceed the withstanding voltage of the switching device 3, there is a risk that the switching device 3 may be broken down. Therefore, there has been heretofore taken a countermeasure, for example, to contrive a circuit configuration such as a wiring length to make the inductance value L of the parasitic inductance A as small as possible.
On the other hand, higher speed switching can be performed with recent improvement in performance of semiconductor devices. In order to reduce a switching loss, it is desirable that switching is performed in a time as short as possible. However, so-called high speed switching leads to the increase of (di/dt). In such a high speed switching condition, the contrivance on the circuit configuration may have a limit on the reduction of the inductance value L.
Next, FIG. 9 shows a second background-art technique of the DC voltage conversion circuit. In FIG. 9, a different point from the circuit shown in FIG. 7 is that a snubber capacitor 7 is connected in parallel with the diode 4. Thus, the drain-to-source voltage Vds of the switching device 3 can be reduced.
In FIG. 9, in a period of time when the switching device 3 is ON, the snubber capacitor 7 is charged so that a voltage Vc of the snubber capacitor 7 is substantially equal to the output voltage Vo.
FIG. 10 shows voltage and current waveforms when a current flowing into the switching device 3 is commutated to the capacitor 5 through the diode 4.
When the switching device 3 starts to turn OFF at a time instant t0 and the drain-to-source voltage Vds becomes slightly larger than 0 [V], a P-to-N voltage VPN (=Vds+Vc) exceeds Vo so that a current starts to flow from the inductor 2 to the capacitor 5 through the capacitor 7 and the parasitic inductance A. That is, commutation starts before Vds exceeds Vo.
A surge voltage ΔV occurring in the circuit shown in FIG. 9 is equivalent to that in FIG. 7. However, since Vds=Vo+ΔV−Vc is established in FIG. 9, the peak value of Vds in FIG. 10 is smaller than that in FIG. 8, as apparent from comparison between FIG. 10 and FIG. 8.
A technique in which Vds is suppressed based on the same principle as that in FIGS. 9 and 10 so as to protect a switching device has been described, for example, in JP-A-10-136637 (Paragraphs [0014] to [0016], FIG. 1, etc.).
According to the circuit in FIG. 9, the surge voltage ΔV can be suppressed to be lower than that in the circuit in FIG. 7. However, when the switching device 3 turns ON and the snubber capacitor 7 is charged up to a value equal to the output voltage Vo, a loss (charging loss) is generated in the switching device 3 because a charging current flows from the capacitor 5 back to the capacitor 5 through the snubber capacitor 7 and the switching device 3. This power loss reaches (½)CVo2 (the references sign C designates the capacitance value of the capacitor 7) regardless of the resistance value of the charging circuit. Even when a charging resistor is placed in the charging circuit of the snubber capacitor 7, the same loss is generated due to that resistor.
In addition, when the switching device 3 is operated at a frequency f, a power loss Ps expressed by Mathematical Expression 2 occurs.Ps=(½)CVo2·f  {Math. 2}
Accordingly, when the switching frequency f is increased, that is, when the DC voltage conversion circuit is operated at a higher frequency, there is a problem that the aforementioned power loss Ps increases to thereby decrease the overall efficiency of the apparatus.
USPTO Backgrounds
USPTO Backgrounds