1. Field of the Invention
The present invention relates generally to integrated circuits and, more particularly, to sensing offsets in an integrated circuit configuration susceptible to data-dependent creep in device characteristics.
2. Description of the Related Art
Typically, modern semiconductor memories (whether embodied in a memory integrated circuit or incorporated in larger designs, e.g., as cache memory of a processor integrated circuit) employ differential bit lines and some sort of differential amplifier or sensing circuit in their design. Such differential amplifier and sensing circuits are commonly known as sense amplifiers (sense amps) and a wide variety of sense amplifier designs are known in the art, including current sensing and voltage sensing variations.
Generally, when designing memory sense amplifiers, great care is taken to optimize timing and balance. Typically, a signal such as a strobe or equalization signal (EQ) is used to time sense amplifier operation. For, example, transitions in an EQ signal are often used to equalize the sense amplifier nodes (SA and SA_L) for a period that allows opposing bit-lines (BL and BL_L) to develop sufficient voltage differential to support sensing. Once the BL & BL_L have developed sufficient differential, EQ is transitioned to cause the sense amplifier to actually sense the developed differential.
Particular care is taken in design and fabrication to achieve balance between device and parasitic parameters on either side of the amplifier. Differential sense-amplifiers are designed to detect very small differences in either voltage or current signals from information read from a memory cell (typically, via a differential pair). Accordingly, a mismatch between the sides of the sense amplifier (or the circuit to which it is coupled), can result in a sense amplifier output that incorrectly flips (i.e., is sensed) in a direction opposite to that of the stored value. In other words, the sense amplifier may sense a value of ‘1’ instead of the actual ‘0,’ that is stored in an addressed cell, or vice-versa. One way to address this problem is to introduce more delay into the signal which evaluates the sense-amplifier, thus causing a reduction in performance.
Generally, if the period defined by an EQ transition is too short, then the bit-lines may not develop sufficient differential for the sense amplifier to correctly sense the data being read from an addressed memory cell. On the other hand, if too much time is allowed for EQ, then access time of the memory circuit is increased and achievable operating frequency (or at least memory access bandwidth) may be reduced. Therefore, in high-speed designs, the EQ signal delay path is designed to deliver the EQ transition at just the right time to ensure that correct data is being read, while aiming to minimize shortest cycle time.
The “right time” is typically a function of variations, potentially wafer-to-wafer variations or chip-to-chip variations, in the fixed electrical characteristics of fabricated circuits. To compensate for such variations, metal options may be added to a design to allow an EQ signal delay path to be tuned to the particular requirements of an integrated circuit. For example, a focused ion bean (FIB) fix may be employed to cut the EQ metal and insert additional buffering into the EQ signal path. Unfortunately, such a fix is both costly and only ensures that the EQ signal is appropriate at the time of the FIB fix. Furthermore, as noted above, additional delay can result in reduced performance.
Unfortunately, in certain very-small device technologies, data-dependent effects have begun to present themselves and circuits developed to accommodate variations in supply voltage or to tune timing paths to temperature or supply voltage variables do not adequately address these data-dependent effects. One such effect is Negative Bias Temperature Instability (NBTI). Accordingly, new techniques are desired to address NBTI and other similar or related effects. In addition, techniques are desired whereby NBTI and other similar or related effects may be advantageously exploited to address various sources of mismatch (including, but not limited to, NBTI and other similar or related effects).
USPTO Backgrounds
USPTO Backgrounds