Complex system-on-chip (SoC) designs, such as ASIC chips, and the like, typically contain large amounts of embedded memory. The embedded memory may be static random access memory (SRAM), dynamic random access memory (DRAM), cache, register files, and even FLASH memory. The embedded memories of the SoC chips are located internally and hence cannot be easily accessed externally for testing. As a result, MBIST systems, located on the SoC, are a common way to test the embedded memory arrays on a SoC.
A conventional MBIST design typically includes address generators, data generators, logic to sequence the addresses and write and read a test memory array to the memory being tested, and a comparator to compare the written and read test memory arrays and report the results. Typically, prior MBIST designs require some external test sequence or instruction to initiate the MBIST test, which causes the address generator and sequencer to generate and sequence addresses of a desired test data pattern which is written and read to every location of the memory being tested. The written and read data (expected data) are compared and the results are reported by a simple pass/fail status, or in more complex designs, more elaborate logic is implemented for diagnosing, debugging, and the like.
Conventional MBIST systems and methods to generate the test data patterns (also known as background patterns) include hardwiring the actual data pattern(s) with logic, storing the desired test data patterns in read only memory (ROM), and algorithmic generation of the test data patterns.
The simplest and easiest method to create a test data pattern is to hardwire logic into the MBIST controller engine to generate the desired test pattern, e.g., a checkerboard pattern of 1's and 0's, or similar data pattern(s). Logic is typically employed to write the memory address of the test data pattern generated by the hardwired logic to the memory under test. The hardwiring design requires gate logic for each desired memory test data pattern to be hardwired into the MBIST controller engine, hence, the hardwired MBIST design cannot be re-programmed or changed for different test data patterns after the SoC is manufactured.
If a large number of memory test data patterns are required, the test data patterns can be encoded in a read-only memory (ROM), which may or may not be part of the MBIST controller. The sequencer logic of the MBIST loads the test memory data pattern from the ROM to the memory being tested until all the ROM locations are exhausted. Although this design can increase the number of memory test patterns, the ROM design requires the desired test data patterns to be pre-programmed and similarly cannot be re-programmed to change the test data patterns.
Conventional MBIST algorithmic generation designs generate test data patterns by utilizing logic gates to generate the desired test data or background patterns when the MBIST is activated. Specific combinations of test data patterns can be selected at the time of MBIST activation. When the MBIST is running, the desired background patterns are dynamically generated to produce a write of the test data patterns into the memory under test. The algorithmic generation technique suffers from the distinct drawback that the desired test data patterns must be pre-generated or pre-programmed. The design is also limited to test data patterns defined by the logic gates.
One example of a more elaborate algorithmic generation design is disclosed in U.S. Pat. No. 6,452,848 entitled “Programmable Built-in Self-Test (BIST) Data Generation For Semiconductor Memory Devices”, incorporated by reference herein. The '848 patent uses additional logic to generate data background patterns based on the row and column address of the memory being tested. Although the '848 patent appears to disclose a programmable memory test pattern generator, the design is limited to the test data patterns which can be generated by the extensive hardwired XOR logic gates. The design is also incapable of receiving external programming (e.g., external to the MBIST controller) to generate test data patterns. Moreover, extensive hardwired logic gates, address scramble registers, and data word registers must be incremented and/or decremented. Hence, the MBIST design of the '848 patent cannot operate at the same speed as the memory under test because of the delays created by the extensive logic gates and the delays associated with incrementing or decrementing the address and data word registers, which require at least one clock cycle.
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