In a complementary metal oxide semiconductor (CMOS) Integrated circuit differential amplifier wherein two CMOS amplifier transistors are employed in the two branch circuits of the differential amplifier circuit, it is desired that the load circuit for each amplifier transistor be of very high impedance so that very large voltage changes at the output will result from small current changes. Such a high impedance load is obtained in each branch by utilizing CMOS transistors as current sources in the two branches of the amplifier to produce the desired high gain amplifier stage. A current source is desirable for the load in order to give high gain over a large range of output voltage. When utilizing current sourcing transistors in the two branches it is desirable to provide a current sinking or limiting CMOS transistor coupled in common to the two amplifier branches so that the current sink will manage as much current as is coming down through the two load circuits. This is necessary in order to be sure that the two amplifier transistors will be in their saturated region of operation when the two input voltages are equal and in order to maximize the common voltage range over which the circuit will operate. To accomplish this, it is desirable that the current sinking transistor be designed so as to match the current sourcing transistors so that the current sinking transistor will operate to manage about twice the maximum current expected from either of the two amplifier branches. In designing a typical form of CMOS differential amplifier, the current sources in the two branches coupled to the V.sub.DD voltage source are typically P channel devices whereas the current sinking CMOS transistor, with its source to drain circuit coupled to ground, is typically an N channel device. It is very difficult to fabricate N channel devices and P channel devices on a common semiconductor substrate so that the devices are matching. For example, characteristics that tend to make P channel transistors have a high gain in many cases result in N channel transistors having low gain. As the P channel threshold decreases, the N channel threshold increases and thus the P channel and N channel devices are working in opposition. As stated above, the N channel device can be over designed so that it operates satisfactorily with the two P channel devices, but this gives degraded performance.
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