The present invention relates to a semiconductor integrated circuit and an operation method thereof and, in particular, relates to a technique that is effective for reducing the amount of computation to be performed by a central processing unit (CPU) or the required amount of storage space in a built-in memory for timing adjustment of a pulse output signal.
Lately, ultrasonic motors (USMs) or hypersonic motors (HSMs) having features such as high torque at low speed, fast response, and high positioning accuracy are used in the fields of automatic focusing control and zooming control for camera lenses, actuators of robots, and actuators of positioning devices. An ultrasonic motor produces a flexural wave motion in a vibrating body (stator) by using ultrasonic vibration generated by piezoelectric elements and drives a moving body (rotor or slider) by using a traveling wave resulting from the flexural wave motion. To transfer the traveling wave originating from the stator to the rotor, some pressurized contact is needed.
Patent Document 1 listed below describes an ultrasonic motor called a “wedge type” in which one end of the vibrating body vibrated by an ultrasonic transducer and one end face of the moving body are positioned to face each other and a plate-like or rod-like vibrating piece is inserted between both. By tilting the vibrating piece at a suitable angle, a reciprocating motion of the ultrasonic transducer is converted to a unidirectional motion of the moving body.
Besides, Patent Document 2 listed below describes an ultrasonic motor called a “traveling wave type” that produces a flexural wave motion in the stator and drives the rotor by using a traveling wave resulting from the flexural wave motion. According to this document, the moving body is brought in pressured contact with the surface of an elastic body of the ultrasonic transducer, the elastic body having a plurality of electrostrictive elements fixed thereto. Application of a high-frequency voltage with different phases in time to the electrostrictive elements being in parallel produces a traveling wave generating elliptical vibration on the surface of the elastic body of the ultrasonic transducer, thus driving the moving body by friction drive. Thereby, this provides a solution to the drawbacks of the “wedge type” ultrasonic motor described in Patent Document 1 listed below, that is, its durability and limitation of its rotational direction to one direction.
Moreover, in FIG. 8 in Patent Document 3 listed below and its related disclosure, there is described a pulse generator comprised of one delay circuit, six inverters, three latch circuits, six AND circuits, one OR circuit, and one selector. The delay circuit responding to a pulse input signal generates a 1st delayed pulse output signal which is delayed by a ⅙ period of one cycle of the pulse input signal (delayed by a phase of 60 degrees) and a 2nd delayed pulse output signal which is delayed by a 2/6 period of one cycle of the pulse input signal (delayed by a phase of 120 degrees). The pulse input signal is supplied to the input terminals of a 1st inverter and a 4th inverter, the 1st delayed pulse output signal is supplied to the input terminals of a 2nd inverter and a 5th inverter, and the 2nd delayed pulse output signal is supplied to the input terminals of a 3rd inverter and a 6th inverter.
An output signal of the 4th inverter, an output signal of the 5th inverter, and an output signal of the 6th inverter are supplied to 1st, 2nd, and 3rd S input terminals of a 1st latch circuit, respectively. The pulse input signal, the 1st delayed pulse output signal, and the 2nd delayed pulse output signal are supplied to 1st, 2nd, and 3rd S input terminals of a 2nd latch circuit, respectively. The input terminal and output terminal of the 1st inverter are coupled to a 1st input terminal of a 1st AND circuit and a 1st input terminal of a 2nd AND circuit, respectively. The input terminal and output terminal of the 2nd inverter are coupled to a 1st input terminal of a 3rd AND circuit and a 1st input terminal of a 4th AND circuit, respectively. The input terminal and output terminal of the 3rd inverter are coupled to a 1st input terminal of a 5th AND circuit and a 1st input terminal of a 6th AND circuit, respectively.
A 1st Q output terminal of the 1st latch circuit and a 1st Q output terminal of the 2nd latch circuit are coupled to a 2nd input terminal of the 1st AND circuit and a 2nd input terminal of the 2nd AND circuit, respectively. A 2nd Q output terminal of the 1st latch circuit and a 2nd Q output terminal of the 2nd latch circuit are coupled to a 2nd input terminal of the 3rd AND circuit and a 2nd input terminal of the 4th AND circuit, respectively. Further, a 3rd Q output terminal of the 1st latch circuit and a 3rd Q output terminal of the 2nd latch circuit are coupled to a 2nd input terminal of the 5th AND circuit and a 2nd input terminal of the 6th AND circuit, respectively.
The input terminal and output terminal of the 1st inverter, the input terminal and output terminal of the 2nd inverter, and the input terminal and output terminal of the 3rd inverter are coupled to 1st, 2nd, 3rd, 4th, 5th, and 6th input terminals of the selector, respectively. An output terminal of the 1st AND circuit, an output terminal of the 2nd AND circuit, and an output terminal of the 3rd AND circuit are coupled to 1st, 2nd, and 3rd input terminals of the OR circuit, respectively. An output terminal of the 4th AND circuit, an output terminal of the 5th AND circuit, and an output terminal of the 6th AND circuit are coupled to 4th, 5th, and 6th input terminals of the OR circuit, respectively.
The 1st Q output terminals, 2nd Q output terminals, and 3rd Q output terminals of the 1st and 2nd latch circuits are coupled to 1st, 2nd, 3rd, 4th, 5th, and 6th input terminals of a third latch circuit, respectively. An output terminal of the OR circuit is coupled to a sync input terminal of the 3rd latch circuit and a pulse select signal is generated which is supplied from an output terminal of the 3rd latch circuit to the selector.
Six pulse input signals with their phases shifted 60 degrees from each other are supplied to 1st, 2nd, 3rd, 4th, 5th, and 6th input terminals of the selector. Thereby, one selected pulse input signal out of the six pulse input signals can be output as an output signal from an output terminal of the selector.
USPTO Backgrounds
USPTO Backgrounds