1. Field of the Invention
The present invention relates generally to timing in semiconductor memory devices and, more particularly, to signal sensing and level-shifting within semiconductor memory devices.
2. State of the Art
Semiconductor memory devices are used in a myriad of applications. Such memory devices receive data for storage during a write operation and provide stored data to devices or systems external to the memory device during a read operation. Typically, a memory device is accessed through a bus which is controlled by a microprocessor or other digital control mechanism.
As the density of fast memory devices, such as static MOS random access memories (SRAM), increases, it becomes increasingly more difficult to utilize existing memory components. FIG. 1 illustrates a block diagram of an exemplary prior art circuit which includes various componentry utilized in a memory application. FIG. 1 illustrates a memory cell 10 which may be a portion of a generally inclusive memory array of memory cells 10. By way of simplification, the associated timing and control as well as other routing signals associated with a memory array are not depicted in FIG. 1 so as to better isolate the shortcomings of the prior art. Memory cell 10 outputs differential output signals DIN and /DIN to a conventional sense amplifier 12. The sense amplifier depicted in FIG. 1 is typical of a sense amplifier resident on a memory module or system which utilizes lower voltages, illustrated as VCCR, due to the reduced architecture dimensions of memory cell 10. Therefore, sense amplifier 12 receives the data signals and, upon sensing the respective differential relationship of the input signals, generates output signals, illustrated in FIG. 1 as DOUT and /DOUT.
Because the data information retrieved from memory cell 10 is utilized by external devices operating at typically higher voltage levels, the system as illustrated in FIG. 1 further includes a level shifter 14 for receiving the DOUT, /DOUT signals from sense amplifier 12 and converting those signals into compatible voltage output signals illustrated as DOUT′ and /DOUT′. In order to perform the level-shifting, level shifter 14 is coupled to an external voltage which is generally a higher voltage illustrated in FIG. 1 as VCCX. In order to make the data available to a computing device, a latch 16 retains the data as retrieved from the memory cell and shifted to the higher voltage level for utilization by a processor or other computational device, illustrated in FIG. 1 as processor 18.
While the architecture illustrated in FIG. 1 accomplishes the objective of retrieving data from a memory cell and presenting the data to a processor for consumption, such an architecture does not lend itself to current speeds associated with both the capability of the memory cell as well as the capability of the processor. For example, there is a finite latency associated with the switching of sense amplifier 12. Additionally, level shifter 14 requires a significant amount of time for boosting the signal level. It is not uncommon for memory access times to be on the order of 4 nanoseconds, with separate level-shifting alone requiring more than 10% of that time. Accordingly, there exists a need to minimize the overall latency associated with the identification and signal level translation resident within a memory module or system.
USPTO Backgrounds
USPTO Backgrounds