1. Field of the Invention
The present invention relates generally to the design of multi-task processors and particularly to the design of processors employing hardware-assisted context switching to perform a plurality of tasks.
2. Description of the Prior Art
Modern electronic devices such as integrated circuit devices often include systems for performing a multiplicity of tasks. For example, a system on an integrated circuit device may perform audio and video compression and decompression. Alternatively, an electronic device such as a personal computer may include a processor for performing a multiplicity of tasks. In general, such electronic devices include one or more processors representing a multi-task system.
Conventional multi-task systems operate by switching between the tasks, a process known as context switching. For example, a task may constitute compression of video data, which is a time-critical task, wherein the video engine performing the compression may only wait for time intervals of less than 2 microseconds (1 microsecond=10−6 seconds) before requiring additional data. On the other hand, tasks such as user menu display or on-screen display are non-critical tasks wherein up to 2 seconds may lapse before additional data is provided without adversely affecting the quality of display. The processor employed in multi-task systems performs context switching between the tasks with different response time requirements.
Performing context switching includes saving the contents of registers of the hardware (hw) units and the status of resources employed in executing a task. The processor may subsequently perform a completely different task and, upon completion thereof, reinitialize all the saved registers and restore the status of the resources to continue executing the original task.
Hardware units requiring service generally send an interrupt command to the processor. If the interrupt command sent by the hw unit requires performing a time-critical task, the processor performs context switching to provide service to the hw unit. After providing the service, the processor resumes executing the same task that was being executed prior to the arrival of the interrupt command.
In modern electronic devices there are two conventional approaches to executing multiple tasks. In one approach, a single processor is employed to perform both the time-critical and non-time-critical tasks. As some time-critical tasks require a very short response time, a powerful processor operating at high speeds as well as a high-speed real-time operating system are required. However, a more powerful processor is larger and often too expensive for use in an electronic device.
In an alternative approach conventional electronic devices employ two different processors. One processor executes time-critical tasks and the other processor executes non-time-critical tasks. Utilizing two processors, however, requires more extensive hw in the electronic device. In addition, due to differences in speed and power of the processors, two different software (sw) development environments are needed thereby increasing the cost of the electronic device.
Referring now to FIG. 1, a flowchart for executing an interrupt command by a prior art system having a single processor is shown. In a multi-task system a processor executes a plurality of tasks simultaneously wherein each of the tasks is referred to as a thread. Execution of a non-critical thread starts at step 10. The processor receives a hw interrupt 12 from one of the hw units. The hw interrupt 12, alerting the processor to execute a time-critical task causes the processor to stop thread execution and to perform context switching by saving the status of all the registers as well as the real-time operating system (RTOS) resources such as message queue or memory management, as indicated in step 14.
Step 16 indicates interrupt service wherein the processor provides service to the hw unit issuing the interrupt command. For example, interrupt service 16 may include providing additional data to the hw unit by the processor. After providing the service, the processor performs context restore, as indicated in step 18, by reinitializing all the registers and restoring all the RTOS resources to the conditions prevailing prior to the arrival of the hw interrupt 12. Context restore 18 enables the processor to continue thread execution in the same manner as was done before the arrival of the hw interrupt 12, as indicated in step 19.
Context save step 14 and context restore step 18 each may require up to 50 machine cycles for completion. Therefore, context switching requires approximately 100 machine cycles with a typical processor speed of 80 megahertz (1 megahertz=106 hertz, where 1 hertz is 1 cycle/second) or 1.25×106 seconds.
In light of the foregoing it is desirable to design a single processor to execute both time-critical and non-critical tasks without requiring considerable power and speed. In addition, the processor should operate with a conventional real-time operating system without requiring extensive sw development environment.
USPTO Backgrounds
USPTO Backgrounds