1. Field of the Invention
The present invention relates to a semiconductor manufacturing device and more particularly to a polishing apparatus for polishing a semiconductor substrate to be flattened.
2. Description of the Related Art
FIG. 10 shows a conventional polishing apparatus. A guide ring 12 is provided around the back face of a top plate 11, and an interlayer material 13 is provided on the back face of the top plate 11, which is positioned at the inside of the guide ring 12. The interlayer material 13 is a cloth to which water penetrates, for example. A semiconductor substrate (wafer) 14 is attracted to the back face of the top plate 11 by the interlayer material 13. As a method for absorbing the wafer 14 to the top plate 11, wax or vacuum chuck can be used. In the case where wax is used, wax is applied on the back surface of the top plate 11, whereby the wafer is attracted to the top plate 11. In the case where vacuum chuck is used, a plurality of intake paths are provided. The wafer, which is attracted to the top plate 11, has a diameter larger than the top plate 11, and is mounted on a polishing plate (not shown) having a polishing cloth is provided on its surface. The polishing plate and the top plate 11 are rotated in a fixed direction, and the wafer is polished by polishing material, which is applied on the polishing cloth.
According to the conventional polishing apparatus, it was difficult to control the temperature of the wafer when polishing. In other words, the temperature of the wafer is increased by friction of the polishing cloth on the wafer and a chemical reaction between the wafer and the polishing material. Due to this, each surface temperature of respective portions of the wafer is not constant. Moreover, a plurality of the wafers are mounted on the polishing plate at one time, and polished simultaneously. However, each temperature of the respective wafers, which are simultaneously polished, was not able to set to be constant. The polishing rate (film thickness/minute: nm/min) depends on the temperature at the time of polishing. Due to this, the polishing rate of each surface of the respective portions of the wafer cannot be equalized. Moreover, the polishing rate of each of the wafers, which are simultaneously polished, and the polishing rate of each batch were not able to be equalized.
USPTO Backgrounds
USPTO Backgrounds