1. Field of the Invention
The present invention relates to a data transfer method of interconnecting electronic chips, such as IC chips, and a data transfer device.
2. Description of the Related Art
To enable configuration or the like of registers of a plurality of slave chips to be performed between one master chip and the slave chips, the master chip is connected to the slave chips by respective signal lines of address buses, signal lines of writing data buses, signal lines of reading data buses, and chip-selecting signal lines, for configuration of the registers (see Japanese Laid-Open Patent Publication (Kokai) No. 2001-142735).
Further, for resetting as well, reset pins are provided separately for the respective slave chips, and a plurality of signal lines for resetting signals are separately connected to the respective reset pins on a circuit board.
In this case, all the signal lines of the buses and the resetting signal lines need to be connected to the respective slave chips on the circuit board into which the slave chips are integrated.
This increases the numbers of signal lines of the address buses, the writing data buses, the reading data buses, the chip-selecting signals, and the resetting signals, in proportion to the number of slave chips to which they are connected.
Further, each slave chip needs to be provided with input and output pins for configuration of its registers, and a resetting pin, which increases the number of pins of the slave chip.
The initial settings of the slave chip, such as register settings, and various settings before execution of data processing need not be frequently changed, compared with the settings during execution of data processing, and can be sufficiently made at low setting speed.
Therefore, to make register settings between the master chip and the slave chips, the signal lines therefor need not be signal lines of buses, but in most cases, signal lines for serial communication are sufficient for this use.
Actually, however, signal lines of the buses are often used to connect the master chip and the slave chips, causing an increase in the number of lines of wiring and complication of the wiring.
Therefore, by minimizing the number of lines of wiring between the master chip and the slave chips in view of ease of wiring therebetween, the total number of lines of wiring of the whole system can be reduced and the whole system can be designed with ease.
Further, to reset the slave chips, it is necessary to provide resetting signal lines individually for the respective slave chips. Normally, resetting control is provided such that all the slave chips on the same circuit board are reset, but not such that only a selected specific chip is reset.
To control the resetting signals by a chip other than the master chip and the slave chips, resetting signal lines need to be provided separately for the respective slave chips to which the resetting signals are to be supplied, and the other chip needs to control the resetting signals supplied to the slave chips.
This necessitates provision of as many resetting signal lines as the slave chips to be reset, which causes an increase in the number of lines of wiring and complication of the wiring.
If the master chip can reset required one or more of the slave chips connected to the master chip, or all the slave chips, this enables reduction of the number of resetting signal lines and enables resetting only selected one or more of the slave chips.
Further, to serially transfer data from the master chip to the slave chips, the master chip needs to be connected to each slave chip, in one-to-one relationship, for the transfer of data.
In this case, to carry out writing of data into a register of each slave chip and reading of data therefrom, two signal lines i.e. one for transfer of data from the master chip to the slave chip, and the other for transfer of data from the slave chip to the master chip, are required at the minimum.
To transfer data directly from one master chip to all slave chips, it is necessary to provide as many signal lines for transfer of data from the master chip to the slave chips, and as many signal lines for transfer of data from the slave chips to the master chip as the number of the slave chips, and the master chip needs to control the transfer of data to each slave chip. Further, as many chip-selecting signal lines as the slave chips need to be connected from the master chip to the slave chips, to select which of the slave chips the master chip should access for writing or reading of data.
That is, for one master chip to transfer serial data to a plurality of slave chips, it is necessary to additionally provide a signal for selecting a slave chip (hereinafter referred to as “the chip select signal”) used for discrimination of a slave chip to which the data is to be transferred, and assert the chip select signal in accessing the intended slave chip.
Further, as many signal lines for the chip select signal as the slave chips are required, which results in an increase in the number of signal lines.
The master chip cannot know the state of a signal level of each signal line via which the data is transferred from the master chip to the associated slave chip, and there is a possibility that noise is added to the signal line depending on the conditions of the circuit board and the wiring conditions of the signal line, whereby the signal level is changed due to the influence of the noise, causing an error in transfer of the data.
To overcome the problem of an error caused by noise in the data received by each slave chip, it is envisaged that the slave chip carries out parity error processing on the received data. In this case, depending on the setting of a parity bit, the processing can sometimes detect an error in the data, but the reliability of the processing is low.
More specifically, when communication by serial data is performed between the master chip and each slave chip, the slave chip determines an error condition of the serial data by parity check or the like, but depending on the bit position of an error, the error cannot be detected. Further, even when it is configured such that an interruption is caused to occur based on a parity error, if the parity error occurs frequently, the performance of a control section, such as a CPU, connected to the slave chip can be degraded due to the control section being interrupted each time the parity error occurs.
To overcome the problem, when the serial communication is executed between the master chip and each slave chip, to post the occurrence of an error to the master chip, there have been used a method of outputting an interruption signal from each slave chip to the master chip and a method of sending back the signal sent from the master chip to each slave chip as it is to the master chip.
In the case of the former method, an interruption signal is output from each slave chip to the master chip, and therefore it is necessary to provide as many interruption signal lines as the slave chips, which results in an increase in the number of signal lines and an increase in the number of pins.
In the case of the latter method, the status of the signal line transferring data from the master chip to the slave chips and the status of the signal line transferring data from the slave chip to the master chip are not the same. Therefore, an error occurs in the data being transferred from the master chip to the slave chip, and when the same data is sent back to the master chip, an error is caused by the influence of noise superposed on the data.
USPTO Backgrounds
USPTO Backgrounds