In conventional photolithographic processing, an integrated circuit (IC) is created by printing a pattern of features defined on a mask or reticle onto a semiconductor wafer that is coated with photosensitive materials. The printed wafer is then chemically and mechanically processed to create various circuit components having shapes corresponding to those of the printed features. The wafer is then re-coated with another layer of photosensitive materials and the process continues to build various layers of the integrated circuit.
As the size or spacing of the features to be printed on the wafer becomes smaller than the wavelength of light used to print a pattern of features onto the semiconductor wafer, optical and other process distortions occur such that the pattern that is actually printed on the wafer may not match the desired target pattern. As a result, numerous resolution enhancement techniques have been developed to improve the fidelity with which a target pattern of features can be printed on a wafer. Examples of resolution enhancement techniques include optical and process correction (OPC), sub-resolution assist features (SRAFs) and phase shift masks.
Additional techniques can be used to verify that a desired target pattern will print on a wafer. These techniques, sometimes called design for manufacturing (DFM) techniques, sometimes called “hotspot” detection techniques, or sometimes referred to as lithography friendly design (LFD) methods, analyze a proposed circuit layout to ensure that the features will print correctly under a variety of different process conditions. These conditions will be specific for the manufacturing process selected, and can include variations in the dose and focus of the light that will be used to expose the pattern onto a wafer. After such an analysis, a circuit designer is alerted to the areas or particular features within the design that may not be properly manufactured.
One approach to this analysis is to use a process model of some sort to estimate the appearance of the pattern on the wafer. This model is often calibrated to the behavior of a particular process or tool set, and encoded into software that allows rapid computation of the pattern on the wafer under the many variations of process conditions that may be reasonably expected.
If the model used in this approach is accurate, this can be almost assured of finding all the locations which may prove to be a problem for manufacturing. This rigorous analysis therefore represents a very reliable approach to detecting problems areas in an IC layout. However, although advances have been made in massively parallel computing that may allow simultaneous computation for many process conditions, this still remains a massive computation job, especially as IC dimensions grow smaller and the sensitivity to process variations grows. To complete a reasonable assessment of a layout in a reasonable amount of time with this full model-based treatment remains a challenge.
One approach to improve the speed of analysis is to use “libraries” of known problems. Here, the proposed circuit layout is analyzed by comparing the feature pattern of a target layout to a database library of known patterns that do not print correctly. The defective patterns are most often detected by a fabrication facility based on test patterns that are printed or from actual experience printing other similar circuits, but can also be simulated using a calibrated process model. As more defective patterns are detected under a variety of conditions, the database becomes increasingly large and the time required to confirm the manufacturability of a layout by comparison against this ever growing library can be take several days or longer using a high speed or networked computer system. Furthermore, it is possible that a new circuit layout will include features that will fail, but have not previously been detected and included in the database library. Therefore, even if a “hotspot” analysis is performed on a circuit layout, there is no guarantee that all errors can be found, and that all the features in the layout will print as desired.
USPTO Backgrounds
USPTO Backgrounds