1. Field of the Invention
The present invention generally relates to a method and an apparatus for producing a ceramic electronic component, and more specifically to a method and an apparatus for producing a chip-type ceramic electronic component such as a laminated ceramic capacitor.
2. Description of the Related Art
Conventionally, a laminated ceramic capacitor is produced, for example, in the following manner.
First, a slurry containing a ceramic source material powder is prepared. This slurry is molded into a sheet so as to prepare a ceramic green sheet. On the surface of the ceramic green sheet, an electrically conductive paste serving as a source material of an internal electrode layer is applied according to a predetermined pattern. This conductive paste is composed of a metal powder, a solvent, and a varnish.
Next, a plurality of ceramic green sheets on which the conductive paste has been applied are laminated and thermally pressed to fabricate an integrated crude laminate body. By sintering this crude laminate body, a ceramic laminate body is fabricated. In the inside of this ceramic laminate body, a plurality of internal electrode layers are formed. End surfaces of a portion of the internal electrode layers are exposed to the outside surface of the ceramic laminate body.
Next, an electrically conductive paste serving as a source material of an external electrode layer is applied onto the outside surface of the ceramic laminate body at which the end surfaces of a portion of the internal electrode layers are exposed, followed by firing the ceramic laminate body. This conductive paste is composed of a metal powder, a glass frit, a solvent, and a varnish. By this process, an external electrode layer is formed on the outside surface of the ceramic laminate body so as to be electrically connected to specific internal electrode layers.
Finally, a plated layer is formed on the surface of the external electrode layer in accordance with the needs in order to enhance the soldering performance.
FIG. 12 is a cross-sectional view illustrating a conventional laminated ceramic capacitor.
Referring to FIG. 12, a laminated ceramic capacitor 5 serving as one example of a ceramic electronic component includes a ceramic laminate body 50 having a rectangular parallelepiped shape. One end surface of each of the plurality of internal electrode layers 51 is formed so as to extend up to the outside surface of the ceramic laminate body 50. On both side surfaces of the ceramic laminate body 50, end surfaces of the plurality of internal electrode layers 51 are arranged so as to be alternately exposed. The external electrode layer 52 is formed on both side surfaces of the ceramic laminate body 50 so as to be electrically connected to specific internal electrode layers 51. The wrap-around ends 53 of the external electrode layer 52 are formed to extend to or wrap around to both ends of the upper and lower surfaces of the ceramic laminate body 50.
In the meantime, in recent years, scale reduction and capacitance increase of a laminate ceramic capacitor are demanded. However, according to the above-described production method, the external electrode layer is formed by applying an electrically conductive paste, so that the thickness of the external electrode layer is several tens to several hundreds of μm. For this reason, a thick external electrode layer is an obstacle preventing a larger capacitance with a smaller volume from being obtained in a laminated ceramic capacitor. Therefore, thickness reduction of the external electrode layer serving as an external conductor layer is demanded.
For example, Japanese Patent Application Laid-open (JP-A) No. 63-169014 discloses two methods of a conventional example and an inventive example as a method of forming an external electrode terminal of a chip capacitor.
According to one method disclosed as a conventional example in JP-A No. 63-169014, an activated layer is attached to the whole surface of a chip capacitor element, and an electrically conductive metal layer is deposited on the whole surface of the chip capacitor element by non-electrolytic plating. Then, with use of an etching-resistant layer formed on a portion of the conductive metal layer as a mask, the conductive metal layer is selectively removed by etching, so as to form an external electrode.
According to the other method disclosed as an inventive example in JP-A No. 63-169014, an electrically conductive metal layer is deposited on the whole side wall surfaces at both opposite ends of a chip capacitor element by non-electrolytic plating so that the internal electrode layers exposed to the side wall surfaces will be short-circuited, so as to form an external electrode.
As shown in FIG. 12, in order to perform surface mounting of a laminated ceramic capacitor 5 onto a substrate or the like, the external electrode layer 52 is formed to extend not only to both side surfaces of the ceramic laminate body 50 but also to both ends of the upper and lower surfaces of the ceramic laminate body 50. In this case, the length of the wrap-around ends 53 of the external electrode layer 52 formed on both ends of the upper and lower surfaces of the ceramic laminate body 50 must be controlled to be an almost constant length.
According to the one method of forming an external electrode terminal disclosed in JP-A No. 63-169014, the external electrode is formed by selectively removing the conductive metal layer by etching with the use of a mask. By this forming method, the length of the wrap-around ends 53 of the external electrode layer 52 such as shown in FIG. 12 can be controlled to be an almost constant length. However, this causes a problem in that, for the control, cumbersome production steps of a masking step and an etching step are needed. Also, since such cumbersome production steps must be carried out, it will be extremely difficult to control the length of the wrap-around ends 53 of the external electrode layer 52 to be an almost constant length when the scale of the chip capacitor element is reduced.
Also, according to the other method of forming an external electrode terminal disclosed in JP-A No. 63-169014, non-electrolytic plating is carried out by using an internal electrode layer exposed to the side wall surfaces at both ends of the chip capacitor element, so that the external electrode layer 52 can be formed on both side surfaces of the ceramic laminate body 50 as shown in FIG. 12. However, it is not possible to form the wrap-around ends 53 of the external electrode layer 52 so as to extend to both ends of the upper and lower surfaces of the ceramic laminate body 50. In order to form the wrap-around ends 53 of the external electrode layer 52 so as to extend to both ends of the upper and lower surfaces of the ceramic laminate body 50, an activated layer must be formed in a region in which the wrap-around ends 53 are to be formed. In this case, a problem is caused such that cumbersome production steps of a masking step and an etching step are needed for selectively forming an activated layer for the purpose of controlling the length of the wrap-around ends 53 of the external electrode layer 52 such as shown in FIG. 12 to be an almost constant length. Also, since such cumbersome production steps must be carried out, it will be extremely difficult to control the length of the wrap-around ends 53 of the external electrode layer 52 to be an almost constant length when the scale of the chip capacitor element is reduced.
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