1. Field of the Invention
The present invention relates to a digital signal processing apparatus and a digital signal processing method, and more particularly to a digital signal processing apparatus comprising a plurality of digital signal processing units each having a storage means wherein the digital signal processing units share respective storage means as a shared memory, and the method of controlling the same.
2. Description of the Related Art
Up until now, there have been provided a wide variety of digital signal processing apparatuses, one of which comprises a shared memory and is adapted to process data stored in the shared memory. One of the conventional digital signal processing apparatuses of this type is shown in FIG. 26 as comprising a digital signal processing group 5, consisting of a plurality of digital signal processing units, for example, digital signal processing units 1, 2, 3, and 4, respectively bearing reference legends “DSP #1”, “DSP #2”, “DSP #3”, and “DSP #4”, a shared memory 6 for storing data to be processed by the digital signal processing units 1, 2, 3, and 4, an address bus 7 through which the digital signal processing units 1, 2, 3, and 4 are operative to specify addresses of data stored in the shared memory 6, a data bus 8 through which the digital signal processing units 1, 2, 3, and 4 are operative to read and write the data with the specified addresses in the shared memory 6, and a control bus 9 through which the digital signal processing units 1, 2, 3, and 4 are operative to receive control signals wherein the digital signal processing units 1, 2, 3, and 4 are operative to process the data stored in the shared memory 6 with reference to the control signals so as to prevent two or more digital signal processing units of the digital signal processing group 5 from requesting the data stored in the shared memory 6 at the same time.
One digital signal processing unit of the digital signal processing group 5, for example, a digital signal processing unit 1, is operated to receive a control signal from the control bus 9, and to judge whether or not the address bus 7 and the data bus 8 are occupied by the other digital signal processing unit 2, 3, or 4 with reference to the control signal thus received. The digital signal processing unit 1 can read and write the data stored in the shared memory 6 through the address bus 7 and the data bus 8 when it is judged that the address bus 7 and the data bus 8 are not occupied by the other digital signal processing unit 2, 3, or 4. The digital signal processing unit 1, on the other hand, can not read or write the data stored in the shared memory 6 through the address bus 7 and the data bus 8 when it is judged that the address bus 7 and the data bus 8 are occupied by the other digital signal processing unit 2, 3, or 4. The conventional digital signal processing apparatus thus constructed is operative to have only one digital signal processing unit of the digital signal processing group 5, i.e., the digital signal processing unit 1, 2, 3, or 4 read and write the data stored in the shared memory 6 through the address bus 7 and the data bus 8 at a time, thereby preventing a bus contention from arising when two or more digital signal processing units of the digital signal processing group 5 request the data stored in the shared memory 6 at the same time.
The conventional digital signal processing apparatus, in which any one digital signal processing unit of the digital signal processing group 5 can not read or write the data stored in the shared memory 6 through the address bus 7 and the data bus 8 when it is judged that the address bus 7 and the data bus 8 are occupied by the other digital signal processing unit 2, 3, or 4, however, encounters a drawback that two or more digital signal processing units of the digital signal processing group 5 can not read or write the data stored in the shared memory 6 through the address bus 7 and the data bus 8 when the two or more digital signal processing units of the digital signal processing group 5 request the data stored in the shared memory 6 at the same time. This makes it difficult for the conventional digital signal processing apparatus to carry out real-time signal processing.
Each digital signal processing unit of the digital signal processing group 5, i.e., the digital signal processing unit 1, 2, 3, or 4 is required to carry out a signal processing process on acoustic signal data for every one audio sample period defined on the basis of an audio sampling frequency. Some digital signal processing units, however, may fail to carry out signal processing processes in synchronous with the audio sample period while the address bus 7 and the data bus 8 are occupied by the other digital signal processing unit. Failure to carry out a signal processing process on acoustic signal data within one audio sample period may generate discontinuous acoustic signals, thereby resulting in acoustic noises. The conventional digital signal processing apparatus encounters another drawback that remaining digital signal processing units may not carry out a signal processing process on the acoustic signal data while one digital signal processing unit occupies the address bus 7 and the data bus 8. The present invention contemplates resolution of such problems.
USPTO Backgrounds
USPTO Backgrounds