The present invention relates to a system and method for data capture and clock recovery and, more particularly, to a phase locked loop with a multiple-bit capture latch controlled by multiple phases of a sample clock.
Phase detectors and phase locked loops are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization and recovery of serial data streams. Because of variations in the fabrication process, operating temperature, power supply levels, interconnects and routings, individual clock delays may be different from one integrated circuit to the next. These differences may create a clock skew between each integrated circuit and a system clock. Clock skew can significantly degrade system performance and make it difficult to synchronize an individual clock edge with the system clock edge.
Initially, an on-chip clock may be faster or slower than the system clock or incoming serial data stream and probably out of phase. To minimize clock skew and achieve synchronization, a phase locked loop is used to track the system clock or incoming serial data stream, compare it with the on-chip clock, detect any phase or frequency difference and then make any necessary adjustments to the on-chip clock until the on-chip clock matches the system clock. The phase locked loop has then "locked-on" to the system clock. Once every integrated circuit in the system is synchronized with the system clock, the entire system works in unison. If for any reason the operating conditions in the system should change, such as a temperature increase that degrades performance, the phase locked loop continues to track the system clock to restore normal operation.
A typical phase locked loop includes a phase detector, a charge pump, a loop filter and a voltage-controlled oscillator ("VCO"). The VCO generates the on-chip clock with a phase and frequency that is a function of the voltage applied to the oscillator. The phase detector detects a phase or frequency difference between the system clock (or the serial data stream) and the VCO output. The phase detector generates a phase control signal as a function of the difference and applies the phase control signal to the charge pump, which increases or decreases a voltage across the loop filter. The oscillation frequency of the VCO increases or decreases as a function of the voltage across the loop filter.
When the system clock or serial data stream transitions are leading the VCO output transitions, the phase detector generates a phase control signal which causes the VCO to increase the frequency of the VCO output (and vice versa when the system clock or serial data stream transitions lag, or trail, the VCO output). When the VCO output matches the system clock in phase and frequency, the phase detector stops sending the control signal to the charge pump and the voltage across the loop filter stabilizes. The VCO output frequency then stabilizes and the phase locked loop has locked on to the system clock or serial data stream.
Phase locked loops are used to recover data from serial data streams by locking a local clock signal on to the phase and frequency of the data transitions. The local clock signal is then used to clock a single capture flip-flop or latch having a data input connected to the serial data stream, often through a data amplifier. A disadvantage of this approach is that the local oscillator must operate at a very high frequency equal to the input data rate.
Many techniques have been used for phase comparison between transitions of the local clock signal and the incoming data. One common technique uses two resettable D-type flip-flops. The output of the flip-flops form "up" and "down" signals which control a charge pump. With this approach, it is difficult to eliminate systematic phase error from the phase detector and charge pump. Even when the phase error is reduced to a low level, there is still a problem of uncontrolled setup time in the flip-flops that capture the incoming data, which is another source of phase error. This severely limits the maximum rate at which data can be successfully amplified and captured.
Another technique is disclosed in B. Kim et al., "A 30 MHz High-Speed Analog/Digital PLL in 2 .mu.m CMOS," IEEE Int'l Solid State Circuits Convention Digest of Technical Papers, pp. 104-105 (1990). The PLL has a 32-stage ring oscillator which is permanently frequency-locked to a reference frequency at the data window rate. Each tap on the ring oscillator is used to latch data samples into one of 32 latches, so that at the end of one round trip (one bit time) 32 samples spaced one gate delay apart are stored in 32 data latches. The bit pattern is evaluated by digital signal processing to determine the location of valid transitions in the data window using digital transition detectors. The center of the current window is held in a current-phase tap register, and this register is updated by a phase error signal. The phase error signal is the difference in tap location between the current window center and the occurrence of a valid data transition.
USPTO Backgrounds
USPTO Backgrounds