1. Field of the Invention
Embodiments of the present invention relate to a redistribution layer for a semiconductor device and methods of forming same.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted and interconnected on a small footprint substrate. The substrate may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. Electrical connections are formed between the die and the conductive layer(s), and the conductive layer(s) provide an electric lead structure for connection of the die to a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
A top view of a conventional semiconductor package 20 (without molding compound) is shown in FIG. 1. Typical packages include a plurality of semiconductor die, such as die 22 and 24, affixed to a substrate 26. A plurality of die bond pads 28 may be formed on the semiconductor die 22, 24 during the die fabrication process. Similarly, a plurality of contact pads 30 may be formed on the substrate 26. Die 22 may be affixed to the substrate 26, and then die 24 may be mounted on die 22. Both die are then electrically coupled to the substrate by affixing wire bonds 32 between respective die bond pad 28 and contact pad 30 pairs.
Space within the semiconductor package is at a premium. Semiconductor die are often formed with bond pads along two adjacent sides, such as shown on die 24 in FIG. 1. However, owing to the significant real estate limitations, there may only be room on the substrate for a wire bond connection along one edge of the die. Thus, in FIG. 1, there are no contact pads along edge 34 of substrate 26 for connecting with die bond pads 28a. 
One known method of handling this situation is through the use of a redistribution layer formed on a semiconductor die. After a semiconductor die is fabricated and singulated from the wafer, the die may undergo a process where electrically conductive traces and bond pads (traces 38 and bond pads 40, FIG. 1) are formed on the top surface of the die. Once formed, the traces 38 and bond pads 28a may be covered with an insulator, leaving only the newly formed die bond pads 40 exposed. The traces 38 connect the existing die bond pads 28a with the newly formed die bond pads 40 to effectively relocate the die bond pads to an edge of the die having a pin-out connection to the substrate. Additional contact pads 30 may be formed on the substrate to allow electrical connection between the substrate and the bond pads 28a. The additional contact pads 30 may be formed in-line with the remaining contact pads 30 as shown in prior art FIG. 1. Alternatively, where there is available space, the additional contact pads 30 may be staggered with the remaining contact pads as shown in prior art FIG. 2.
Current photolithography and other methods for forming a redistribution layer on semiconductor die are cumbersome, adding large numbers of process steps and expense to the fabrication process. There is therefore a need for a streamlined process for forming a redistribution layer.
USPTO Backgrounds
USPTO Backgrounds