As one type of package module using a film substrate, the one employing a COF structure has been known. FIG. 14 is a cross-sectional view showing a part of one example of a package module with a COF structure. The COF package module includes a semiconductor chip 21 mounted on an insulating flexible tape carrier substrate 20 and is protected by an encapsulation resin 22. Such a COF package module mainly is used as a driver for operating a flat panel display. The tape carrier substrate 20 includes as main components an insulating film substrate 23 and wiring layers 24 formed on a surface of the film substrate 23. A metal coating 25 formed by plating and a layer of a solder resist 26 as an insulating resin are formed on the wiring layers 24, if necessary. In general, polyimide is used as a material of the film substrate 23 and copper is used as a material of the wiring layers 24.
The wiring layers 24 formed on the tape carrier substrate 20 and electrode pads 27 formed on the semiconductor chip 21 are connected to each other via bumps 28. The bumps 28 are provided either by previously forming them on the wiring layers 24 on the tape carrier substrate 20 or by previously forming them on the electrode pads 27 on the semiconductor chip 21.
When forming the bumps 28 on the wiring layers 24 on the tape carrier substrate 20, a method as disclosed in JP 2001-168129 A is used, for example. Major aspects of this method will be described with reference to FIGS. 15A1 to 15F1 and FIGS. 15A2 to 15F2. FIGS. 15A1 to 15F1 are plan views showing a part of the film substrate in a series of processes in the conventional method. FIGS. 15A2 to 15F2 are cross-sectional views of FIGS. 15A1 to 15F1, respectively. Each of the cross-sectional views is taken along the line C-C in FIG. 15A1. These processes are directed to an example where the bumps are formed by metal plating.
First, on the film substrate 23 on which the wiring layers 24 are formed as shown in FIG. 15A1, a photoresist 29 is formed so as to cover the entire surface of the film substrate 23 as shown in FIG. 15B1. Next, as shown in FIG. 15C1, using an exposure mask 30 for forming the bumps, the photoresist 29 is exposed to light through light-transmitting regions 30a of the exposure mask 30. Subsequently, as shown in FIG. 15D1, the photoresist 29 is developed to form opening patterns 29a. Thereafter, as shown in FIG. 15E1, a metal is plated on the wiring layers 24 through these opening patterns 29a. By removing the photoresist 29, the tape carrier substrate 20 provided with the wiring layers 24 on which the bumps 28 are formed is obtained as shown in FIG. 15F1. In general, the bumps 28 are arranged along four sides of the rectangular film substrate 23 as shown in FIG. 15F1. However, instead of a single row arrangement along each side of the film substrate 23 as shown in FIG. 15F1, the bumps 28 may be arranged in a plurality of rows along each side of the film substrate 23.
When forming the bumps 28 on the wiring layers 24 formed on the tape carrier substrate 20 in the above-described manner, accurate positioning of the exposure mask 30 is difficult owing to the characteristics of the film substrate 23. If the exposure mask 30 is not placed in proper position, favorable bumps 28 cannot be formed. On this account, the bumps 28 generally are formed on the electrode pads 27 on the semiconductor chip 21. On the other hand, forming the bumps 28 on the wiring layers 24 on the tape carrier substrate 20 is advantageous in that it requires a smaller number of processes than forming the bumps 28 on the electrode pads 27 on the semiconductor chip 21 and thus can reduce manufacturing cost.
However, the bumps 28 formed by the above-described conventional method have a problem in that the shape thereof is not favorable. FIGS. 16A and 16B are cross-sectional views of the tape carrier substrate obtained through the processes described above. FIG. 16A is a cross-sectional view taken in the longitudinal direction of the wiring layers 24, which is the same cross-sectional view as FIG. 15F2. On the other hand, FIG. 16B is a cross-sectional view taken along the line D-D in FIG. 16A, i.e., taken in the transverse direction of the wiring layers 24.
As shown in FIGS. 16A and 16B, each of the bumps 28 is formed to be joined to an upper surface of the corresponding wiring layer 24. Thus, the bump 28 is held on the wiring layer 24 only by joining a portion with an extremely small area to the upper surface of the wiring layer 24. Accordingly, when the bump 28 receives a force in the lateral direction, it is liable to come off from the upper surface of the wiring layer 24. For example, when a force in the lateral direction is applied between the semiconductor chip 21 and the tape carrier substrate 20 when the bumps 28 are joined to the electrode pads 27 (see FIG. 14) on the semiconductor chip 21, there is a risk that the bumps 28 might come off from the wiring layers 24, which renders the connection after the semiconductor chip is mounted unstable.
Furthermore, the bumps 28 have flat upper surfaces because they are formed only on the upper surfaces of the wiring layers 24 by carrying out plating through the minute opening patterns 29a shown in FIG. 15D1. The flat upper surfaces of the bumps 28 may bring about the following problems when connecting the bumps 28 to the electrode pads 27 on the semiconductor chip 21.
First, if there is a displacement in positioning between the bumps 28 and the electrode pads 27, each of the bumps 28 with the flat upper surfaces is prone to be in contact with the electrode pad 27 that is adjacent to the electrode pad 27 to which the bump 28 actually is to be connected. This brings about the risk that the bumps 28 might be connected to incorrect electrode pads 27.
Second, when connecting the bumps 28 to the electrode pads 27, it is difficult to break natural oxide films formed on the surfaces of the electrode pads 27. Usually, the oxide films formed on the electrode pads 27 are broken by the contact of the bumps 28 against the electrode pads 27 so that the bumps 28 are electrically connected to metal portions of the electrode pads 27 that are not oxidized. However, with the flat upper surfaces of the bumps 28, it is difficult to break the oxide films.
Thirdly, it is difficult to connect the bumps 28 to the electrode pads 27 in the state where the resin layer 22 intervenes between the semiconductor chip 21 and the tape carrier substrate 20 as shown in FIG. 17. When mounting the semiconductor chip 21 on the tape carrier substrate 20, the bumps 28 are brought into contact with the respective electrode pads 27 by displacing the resin layer 22 with their heads. However, the bumps 28 with the flat upper surfaces cannot displace the resin layer 22 sufficiently.
Moreover, when forming the bumps 28 by the conventional method illustrated in FIGS. 15A1 to 15F1 and FIGS. 15A2 to 15F2, if the positioning accuracy of the exposure mask 30 for forming the bumps relative to the wiring layers 24 is not sufficient, an area of the portions where the opening patterns 29a overlap with the respective wiring layers 24 becomes smaller. As a result, as shown in FIG. 18, the bumps 28 formed on the respective wiring layers 24 cannot attain the designed size. The problem of such defect in size of the bumps 28 will become more serious as the pitch of the electrode pads 27 becomes narrower in accordance with the demand for higher output power from COF package modules.
Although the above-describe problems are particularly noticeable when using tape carrier substrates, these problems are common to similar kinds of circuit boards.
USPTO Backgrounds
USPTO Backgrounds