This invention relates to a circuit for implementing programming of an array of floating-gate, avalanche-injection, metal-oxide-semiconductor (FAMOS) transistors formed on an integrated circuit chip.
A circuit for controlling and optimizing the source-drain current flow during programming of an array of floating-gate memory cells is described application Ser. No. 786,981, now U.S. Pat. No. 4,723,225, issued on Feb. 2, 1988 to Jeffrey K. Kaszubinski, et al, and assigned to Texas Instruments Incorporated. The circuit disclosed and claimed in the foregoing patent provides an optimized voltage level to be applied during programming to the gates of control transistors in series with bit lines. The control transistors in turn allow optimum levels of current to flow through the bit lines and the source-drain paths of the FAMOS transistors during programming.
Output signals from decoder circuits are used during normal operation of memory cells to facilitate connection of bit lines of memory cells to sense amplifiers for the purpose of reading voltage status. Ideally, the same decoder circuit signal output could also be used to activate the output of the current-limiting circuit referenced above during programming. However, the output of the decoder circuits must generally be altered in some manner to facilitate programming and to facilitate reading because different voltage levels are required and/or because different types of transistors are used for electrical access to the bit lines of memory cell arrays.
Accordingly, there is a need for a relatively simple programming implementation circuit in which one output of a decoder circuit may be adapted for use in programming memory cells and also for use in reading the status of memory cells.
USPTO Backgrounds
USPTO Backgrounds