1. Field of the Invention
The present invention relates to an interrupt control system, and more specifically to a computer system capable of dynamically determining the delay time, for example, from an external input of an interrupt event to an output of an interrupt request of an interrupt request output unit in a computer system to a processor depending on the load status of the processor.
2. Description of the Related Art
When an interrupt event requiring external interrupt processing by a processor is input to a computer system, for example, an I/O device which receives the interrupt event issues an interrupt (request) signal to the processor, and the processor performs corresponding interrupt processing. For example, when the I/O device is a network interface, an interrupt signal is issued from the I/O device to the processor when communications data such as a packet is received.
FIG. 16 is a block diagram showing the configuration of the computer system to which the present invention is applied. In FIG. 16, the computer system includes a processor 50, main memory 51, an I/O bus bridge 53, and a plurality of I/O devices 54 and 55.
In FIG. 16, the I/O bus bridge 53 connects the processor 50, the main memory 51, and an I/O bus 52, and provides an access function from the processor 50 to the main memory 51 and the I/O bus 52. The I/O devices 54 and 55 are connected to the I/O bus 52, and function as interfaces between various devices such as a network, a disk, etc. and the computer system.
For example, in the case of a network interface, when communications data is received by the I/O device, an interrupt (request) signal is issued to the processor 50, the processor 50 checks inside the I/O device 54, for example, the contents of an interrupt factor register in correspondence with the signal.
In this example, the conventional technology is described by referring to a PCI (peripheral component interconnect) system bus currently used as a major high-speed bus for personal computers, and a PCI bus device, but the present invention can be applied to any similar system.
In the system as shown in FIG. 16, the timing and the frequency of an I/O device issuing an interrupt (request) signal to a processor have considerable influence on the performance of a system. For example, when an I/O device is an interface corresponding to the Gigabit Ethernet, the transfer performance of 125 MB/sec can be realized for transmission/reception, but the minimum length of a packet is approximately 60 bytes. Therefore, if a notification is issued to the processor each time a packet is received, an interrupt is made to the processor every 0.5 μs.
FIG. 17 is an explanatory view of a conventional technology of the interrupt processing performed in the above-mentioned case. In FIG. 17, for example, an interrupt event 1 is externally applied to the computer system, the processor immediately performs interrupt processing, then an interrupt event k is externally applied, and the processor immediately performs interrupt processing.
When the processor performs interrupt processing, a predetermined processing load is required for saving and restoring an current process state, designating a interrupt factor, etc. When interrupts frequently occur, and the interrupt intervals become shorter, the interrupt processing load of a processor increases, thereby possibly reducing the performance of the system.
Thus, to avoid the increase in the load of the processor by frequent occurrence of interrupt, the conventional technology called “interrupt coalescing” is widely used. In the interrupt coalescing, the time from the occurrence of an event requiring an interrupt, that is, an interrupt event, to an issue of an actual interrupt request to the processor is delayed on a predetermined condition. For example, since interrupt events are collectively input, a processing load such as the current process state to be saved and restored, the designation of an interrupt factor, etc. can be collectively processed, thereby reducing the processing load of the processor.
FIG. 18 is an explanatory view of the above-mentioned interrupt coalescing. In FIG. 18, a plurality of interrupts from the interrupt event 1 to the interrupt event K are collected, and an interrupt request is issued from the I/O device to the processor.
As a typical condition up to an interrupt request in the interrupt coalescing, the conditions such as “the passage of a predetermined time”, “a predetermined number of occurrences of interrupt events”, etc. are applied. For example, in the case of a network interface, an interrupt request is issued if a predetermined time has passed after a packet is received. In this method, when a total of K packets are received while the interrupt is being delayed, the number of interrupts to the processor can be reduced to 1/K. Using the condition of the frequency of interrupt events, the frequency of interrupt events can also be decreased.
Described below is the conventional configuration of the device of the interrupt request circuit in the I/O device. FIG. 19 is a block diagram of the configuration of the device. In FIG. 19, for example, an interrupt request circuit 58 is provided in the I/O device 54, and an interrupt factor register 59 is provided in the interrupt request circuit 58.
The interrupt request circuit 58 issues an interrupt (request) signal to the processor 50 through the I/O bus 52 and the I/O bus bridge 53 when an interrupt event occurs by, for example, externally receiving a packet, and simultaneously the information for determination of the contents of the interrupt event is set in the interrupt factor register 59.
The contents of the interrupt factor register 59 is read from the processor 50 through the I/O bus 52, and can be written. The processor 50 identifies the contents of an interrupt event by checking the contents of the interrupt factor register 59. The processor 50 can notify the interrupt request circuit 58 of the end of the interrupt processing by clearing the contents of the interrupt factor register 59. Corresponding to this notification, the interrupt request circuit 58 negates an interrupt signal, thereby completing the process on the interrupt.
FIG. 20 is an explanatory view of a flow of the interrupt processing shown in FIG. 19. When an interrupt event is applied to the I/O device, an interrupt signal is immediately issued to the processor, and the processor starts in <1> the interrupt processing by checking the interrupt factor with the contents of the interrupt factor register 59, fundamentally terminates the interrupt processing and clears the contents of the interrupt factor register 59, and performs the process of releasing the work area for the interrupt processing, etc. in <2>, and terminates the interrupt processing in <3>.
FIG. 21 is a block diagram of another example of the configuration of the conventional I/O device. FIG. 22 is an explanatory view of the flow of the interrupt processing shown in FIG. 21. In FIG. 21, a condition register 61 storing a predetermined fixed delay condition is provided in the interrupt request circuit 58, and an interrupt delay circuit 62 determines a delay time from the occurrence of an interrupt event to the issue of an interrupt signal to the processor. The storage contents of the condition register 61 can be the above-mentioned predetermined time, or a predetermined frequency of interrupt events, and the interrupt delay circuit 62 determines the delay time from the occurrence of an interrupt event corresponding to the contents, and outputs an interrupt signal.
In FIG. 22, an interrupt signal is issued to the processor if a predetermined delay time has passed after an interrupt event is applied to the I/O device. Then, as in the case as shown in FIG. 20, <1> the interrupt factor is checked, <2> the interrupt factor is cleared, and <3> the interrupt processing is terminated.
There are three problems with the interrupt coalescing as the above-mentioned conventional technology. The first problem is that the response from the occurrence of an interrupt event is constantly delayed because an interrupt is delayed on a constant condition from the occurrence of an interrupt event. For example, in the case of an network interface, and in the case only a packet is received, the interrupt processing cannot be performed until a predetermined time has passed since the packet is actually received.
The second problem is that since the load status of a processor is not considered, an adaptive process cannot be performed by, for example, immediately performing an interrupt when the load of a processor is small, and delaying an interrupt when the load of the processor is large.
The third problem is that although an I/O device is used with a card, etc. inserted, and the optimum condition for the interrupt delay between the card and the processor depends on a card, etc., the conventional technology uses fixed delay conditions without adjustments.
The present invention aims at providing a computer capable of dynamically determining the delay condition from the occurrence of an interrupt event to the issue of an interrupt request signal from an I/O device to a processor depending on the performance and the load status of a processor and the frequency of occurrence of interrupt events.
USPTO Backgrounds
USPTO Backgrounds