1. Field of the Invention
The present invention relates to an analytical method of Auger Electron Spectroscopy (hereinafter referred to "AES") for a sample having an insulating layer, and more particularly, to an analytical method of Auger Electron Spectroscopy for an insulating sample for which charge accumulation effects are prevented.
2. Background of the Related Art
In general, semiconductor devices include various elements such as memories, LCD's and the like. Normally a number of analyses are performed for a sample, which was produced in the course of the fabrication of the semiconductor device, for the purpose of increasing yields and enhancing performance.
One typical analytical apparatus for such purposes is an Auger Electron Spectroscopy (AES) system that is used to analyze contamination or composition of the surface and depth of a sample's layers. AES analyzes the elements in a sample by shooting an electron beam onto a selected atom on the surface of the sample and scanning the kinetic energy of an auger electron resulting from the impact of the electron beam. Due to its excellent analytical performance on minute areas, AES is chiefly used to analyze the particles on the surface of a wafer, damaged parts of a semiconductor structure, and the composition of thin layers, e.g., Si.sub.3 N.sub.4, WSi.sub.2, TiN, PSG, or BPSG. In particular, AES is characterized by its high resolution due to the application of the electron beam.
A conventional AES system is incapable of analyzing an insulating layer through the use of an electron beam because of the charge accumulation effect of the insulating layer. Thus, the analysis is limited to a conductive sample that does not experience a charging effect.
The AES analysis may be performed using a method of depositing conductive materials such as gold on a sample for a scanning electron microscopic analysis. However, with a device such as a diode sputtering apparatus that is used for a general deposition, it is not easy to deposit a conductive layer with a thickness of less than 100 .ANG. to 150 .ANG., or to regulate the deposited layer to have a precise thickness of a desired level. When using an AES system that is restricted to operating with a conductive layer of about 30 .ANG. to 50 .ANG. in thickness, it is therefore impossible to perform an analysis for the surface of a sample on which a conductive layer of at least 100 .ANG. to 150 .ANG. in thickness was deposited.
USPTO Backgrounds
USPTO Backgrounds