1. Field of the Invention
The present invention relates in general to electronic devices. In one aspect, the present invention relates to a method and apparatus for designing electronic devices.
2. Description of the Related Art
Because of the increasing computational intensity (and the associated power consumption by the processor(s)) for electronic devices, it is an important goal in the design of electronic devices to minimize circuit operations and the associated power consumption. It is particularly crucial for electronic devices targeted for low-power applications (e.g., for wireless and portable electronics) in order to extend battery life. Generally speaking, power reduction efforts will seek to reduce the overall power consumption of the device by identifying portions of a design that consume relatively high amounts of power as compared to other portions of the design, and then further optimizing their design or layout characteristics to reduce power consumption in the identified portion(s). In this analysis, the amount of power consumed by a block or portion of a device may be estimated using dynamic or static techniques, though such techniques are often applied late in the design process of a device at significant computational cost. Once a block or portion of the device is identified as a high power consumer, its dynamic power consumption may be optimized by reducing the relevant circuit's power supply voltage, load capacitance, clocking activity, switching activity, etc. An example optimization technique will add sequential clock gating logic at the RTL design level to reduce power consumption by controlling device clocking so that a clock signal in a block or an array is disabled when the internal circuitry from the block/array is not required to perform work for an extended amount of time. Later, when the period of inactivity has ended, the clock signal is enabled again. An enable signal may be routed to a clock-gating circuit in order to perform this power-saving technique. While RTL clock gating is a common optimization technique for improving energy efficiency, it must still be determined how well a design is clock gated. Various design tools are available for computing predetermined efficiency estimation metrics for the inserted gates, such as the percentage of flops gated, the percentage of flops killed, the percentage in reduction of Q toggle (provided in PwrLite's CooolGate tool), and “average percentage of time each register is gated for a given test bench” (provided in Calypto's PowerProCG tool). However, it is computationally cumbersome to track these metrics, and it is also difficult to understand how the different metrics affect each other. For example, using the percentage of registers clock gated as a metric does not indicate the energy efficiency because it does not take into account switching activity. And while an average clock-gating efficiency metric is a better energy consumption metric since it measures both the number of registers gated and the duration they are turned off, neither the “percentage of registers gated” metric nor the “average clock-gating efficiency” is sufficient to determine where power is being wasted.
Accordingly, a need exists for an improved method and apparatus for designing low power electronic devices which addresses various problems in the art that have been discovered by the above-named inventors where various limitations and disadvantages of conventional solutions and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow, though it should be understood that this description of the related art section is not intended to serve as an admission that the described subject matter is prior art.
USPTO Backgrounds
USPTO Backgrounds