When making an integrated circuit (which may also be referred to as a chip or device), photolithography is used to transfer features from a reticle or mask to a semiconductor wafer. Since photolithography is typically not able to faithfully reproduce the reticle design on the wafer, the reticle design is adjusted or optimized so that the features on the semiconductor wafer are created at the desired dimensions. To determine and form the optimized reticle design, the area around a feature on the reticle design must be considered. Techniques such as optical proximity correction (OPC) may be used. The OPC procedure is used to compensate for such optical effects as diffraction, for instance. Such effects may lead to rounded corners of features on the final silicon wafer or to a reduction in gaps between adjacent features which are outside of process tolerances. The optical influence that features have on their neighbours falls off rapidly as the distance between the features increases.
The OPC procedure is usually carried out after the design and layout of the integrated circuit has been determined and so is carried out as one of the final steps before the reticle is produced. The OPC procedure is typically carried out using a powerful computer system. Execution times range from several hours to several days depending on the size of the design and the computing power available.
The OPC stage may include a rule based procedure, for instance. Such rules may enlarge the ends of tracks to form hammerheads and extend the outer portions of corners while reducing the inner portions, for instance. Model based techniques may also follow. These simulate the resultant optical image formed by the reticle exposure onto the wafer and iteratively correct any difference between the simulated and the desired wafer images. Normally, model based OPC run parameters are defined and then several iterations of OPC calculations are required in order to sufficiently optimize a reticle design, i.e. such that features on the semiconductor wafer are created at the correct dimensions. Unfortunately, the run time increases linearly with the number of OPC iterations.
The reticle design after completion of OPC optimization is typically analyzed or simulated to ensure that the OPC has been performed correctly. If an error in the reticle design after OPC is detected, model based OPC run parameters may be changed manually and a new OPC job started. For each different OPC job run, the OPC calculations are restarted with the original design as the staring point for the OPC iterations. Thus, if one line edge is moved outwards to enlarge a feature in the first OPC job, the second OPC job is begun with this edge unmoved (i.e., without the feature enlarged). There is no methodology to reuse the edge location of the edge that was previously moved in the first OPC job. Instead, each OPC job is begun from the same original design. This process increase the overall time required to obtain correct OPC results.
As the OPC procedure must be carried out at the end of the design stage, the computer runtime used to perform it adds to the overall delivery time of the final integrated circuit. As the need to increase the number of features on an integrated circuit grows, so too will the OPC calculation runtime. The execution runtime problem will continue to get worse as OPC calculations must be carried out on current computers, which must be used to optimize tomorrow's processors.
It is therefore desirable to provide a method for making an integrated circuit that minimizes the overall time required for OPC optimization.
USPTO Backgrounds
USPTO Backgrounds