1. Field of the Invention
The present invention relates generally to an upgradeable/downgradeable computer and specifically to a computer having circuits capable of connecting to more than one type of central processing unit (CPU).
2. Description of the Related Art
As prices of CPUs decrease, the cost of a CPU as portion of the total cost of the whole system decreases. And as introduction of new types of central processors is becoming faster and faster (for example, within a span of only a few years, the Intel Corporation has introduced models 8086, 80286, 80386 and 80486), it is now feasible to have a computer system that can be upgraded/downgraded by simply replacing processors. Specifically, it is desirable to have a computer system with circuit (motherboard) that can accept different types of cental processors without alteration. While upgradeable/downgradeable computer systems are known in the art, tire prior art systems require changing of the whole motherboard.
FIG. 1 is a block diagram of a prior art system. As shown in FIG. 1, this prior art system is designed with two distinct sockets, the first socket 1 for 80486SX (80P23), and the second socket 2 for 80487SX (80P23N). As is known, these processors operate with the same external clock signal; all other signals of the 80486SX are tied to the corresponding signals of the 80487SX. The MP# signal of the 80487SX is tied high to allow the system to function normally when the 80487SX is not present. When the 80487SX is inserted in the first socket 1, the MP# signal of the 80487SX drives the BOFF# signal and the FLUSH# signal of the 80486SX active, thus tri-stating it. The 80487SX then takes charge of the buses and the system works normally.
USPTO Backgrounds
USPTO Backgrounds