The present invention relates to very large scale semiconductor integrated (VLSI) circuits and technology, and more particularly relates to VLSI circuitry designed with the back-gated MOSFET devices in such a way that their threshold voltages are dynamically modulated during circuit operation to realize improved logic state capture, reduced leakage current and improved noise immunity at the back-gated devices.
The need for low-power VLSI circuitry for use in numerous electronic applications is ever growing. To reduce power consumption, lower operating voltages (Vdd) and minimized device dimensions are the constant aim of IC designers. To lower the threshold voltage (VTh) and the operational voltage for IC devices, silicon-on-oxide (SOI) MOSFETs have been developed and are known. Fuse, et al., “0.5 V SOI CMOS Pass-Gate Logic,” DIGEST OF TECHNICAL PAPERS, IEEE International Solid-State Circuits Conference; vol. 39, February 1996; pp. 88-89.
SOI metal oxide field effect transistors (MOSFETs) can be fabricated into two distinct modes of operation: 1) fully depleted (FD), and 2) partially depleted (PD) channel region (i.e., body). In conventional fully depleted SOI devices, the silicon film thickness is usually less than or equal to half the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and substrate through the front-gate dielectric and the buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By using the substrate as a back-gate, the device can be operated as a dual-gated device. A back-gate may or may not have a discrete gate plate which is physically insulated from the conduction layer. Devices may be back-gated by merely contacting the device body.
Dynamic threshold metal oxide semiconductor (DTMOS) devices can be fabricated on silicon-on insulator (SOI) substrates as described, for example, in U.S. Pat. No. 5,559,368, to Hu, et al., issued Sep. 24, 1996, and incorporated by reference (“the '368 patent”). The '368 patent discloses a DTMOS device (MOSFET) fabricated on a silicon-on-insulator substrate to include a four-terminal layout comprising source, drain, gate and body contacts. The DTMOS device comprises a substrate with a buried oxide layer formed therein, and a P-SI film disposed on the oxide layer. N+ sources and drains are formed in the film. A gate electrode is formed on a gate insulation layer on the film between the source and drain of the MOSFET device. The gate and film are interconnected (gate to body) to reduce the threshold or gate turn-on voltage (VTh) when the gate voltage is high.
The reduced threshold or turn-on voltage (V.sub.t) improves MOSFET device performance in numerous respects. When the FET is OFF, the threshold voltage is increased, reducing sub-threshold leakage currents. Applications which use DTCMOS devices provide for lower leakage currents while the MOSFET device is off, and lower threshold voltages when the device is on. In non-DTCMOS structures, the bulk silicon material from which the channel of the MOSFET device is formed is either grounded, or in many applications connected to the source region of the device.
U.S. Pat. No. 6,326,666, to Bernstein, et al., issued Dec. 4, 2001, and incorporated by reference (the '666 patent), discloses a DTCMOS circuit implemented in SOI that includes a plurality of input transistors with threshold voltages controlled by early arriving logic signals. The DTCMOS transistors have body contacts connected to the monocrystalline silicon film of the device. Use is made of the body contact for controlling the voltage threshold (VTh) of a device that receives a respective logic signal. Earlier arriving logic signals are coupled to the gate of one input transistor, as well as to the body contact of another transistor receiving a later arriving logic signal. A data transition on the earlier arriving logic signal will lower the voltage threshold of the input transistor receiving the later arriving signal. Thus, a dynamic lowering of the voltage threshold occurs permitting an increase in speed for the logic circuit.
U.S. Pat. No. 6,462,585, to Bernstein, et al., issued Oct. 8, 2002, and incorporated by reference (“the '585 patent”), discloses an asymmetric-double-gate complementary metal oxide semiconductor (DGCMOS) device that includes a cross-coupled latch circuit to improve effective Vdd/VTh. The cross-coupled latch circuit substantially reduces body-to-source/drain parasitic capacitances as well as structural body resistance parasitics of the asymmetric-DGCMOS device and improves the effective Vdd/VTh ratio without causing any substantial body-to-source/drain parasitic capacitances or structural body resistance parasitics. The DGCMOS device is scalable below about 0.1 mm, while being able to operate at voltages below about 1 V.
Delay variation and process tolerance, however, negatively affect the timing precision in deep submicron VLSI logic circuitry, even in the above-mentioned DGCMOS and DTCMOS designs. For example, complementary pass gate logic (CPL) circuits that include NFET gates in an evaluate tree tend to result in incomplete transition voltages presented at the output buffers. Incomplete transition voltages at the output buffers cause excessive crowbar current in the buffer side when it is pulled low. The excessive crowbar current tends to complicate and limit the CPL circuit family use by designers. And while dynamic logic circuits constructed with DTCMOS and DGMOS technology are very fast, the circuits are typically very large and very sensitive to leakage current. For example, in domino-based designs, separate keepers are typically used (required) to replace leakage current that could otherwise lead to corrupted logic states.
What would be desirable, therefore, in the field of DGMOS and DTCMOS IC design is a device constructed with back-gated MOSFETs to positively capture logic states, reduce leakage currents and improve noise immunity by dynamically modulating threshold voltages. Such devices would preferably be utilized in circuits whose power supply voltages exceed 0.5 V, the approximate limitation of conventional DTCMOS technologies. The skilled IC designer would further welcome such back-gated devices to comprise complementary pass-gate logic (CPL) elements to dramatically reduce crowbar currents in NFET pass gates when the buffer side is pulled low. For that matter, such a device would be further desirable in dynamic logic circuits to eliminate the need for a separate keeper device and improve overall performance.
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