This relates generally to imaging systems, and more particularly to clocking methods for coupled device (CCD) image sensors that improve horizontal CCD transfer rates during binning and that provide better noise performance.
Electronic devices such as cellular telephones, cameras, and computers often include imaging systems that include digital image sensors for capturing images. Image sensors may be formed having a two-dimensional array of image pixels that contain photodiodes that convert incident photons (light) into electrical signals. Electronic devices often include displays for displaying captured image data.
Conventional interline CCD imagers are provided with multiple photodiodes that are formed below a pinning layer. In a conventional imager, the photodiodes are typically n-type doped regions in a semiconductor substrate. The pinning layer formed over the photodiodes is usually a p-type doped layer. The pinning layer formed over the photodiodes is conventionally coupled to ground and serves as a ground for the photodiode. The potential of the photodiode remains constant as long as the voltage provided at the pinning layer is constant, and there is no net global current flow throughout the device.
Light incident on the imager results in the accumulation of photo-generated electrons in the n-type photodiode region. Some of these photo-generated electrons are read out into a vertical CCD (VCCD) by applying a read-out voltage (sometimes referred to as the “third-level voltage”) to a transfer gate that is formed over the VCCD and a region between the photodiode and the VCCD.
The “third-level voltage” conventionally used in the readout of photo-generated charges from photodiodes to the VCCD is usually a large voltage greater than 7 V. The photo-generated electrons are then read out from each VCCD to a horizontal CCD (HCCD), where they are then stored in a floating diffusion node before being transferred to an associated output.
In some conventional CCD image sensors, binning operations are performed on charges before they are read out from the associated output. This binning is traditionally performed only at a summing gate at the output of the HCCD. This summing gate is provided with a control signal having a 75% duty cycle that is clocked at half the frequency of the HCCD. This requires the HCCD to be clocked at twice the frequency of non-binning methods in order to achieve the same output sampling frequency. This traditional binning method only allows two charges to be binned together and all charges must be binned in the summing gate. Because of the high duty cycle used in the traditional binning method, the time window during which charge is available to be sampled from the floating diffusion node (i.e., sampling window) is half the size of the corresponding sampling window of traditional non-binning CCD read out methods. This decrease in the size of the sampling window results in increased noise and requires higher bandwidth electronics that increase the cost of the system.
Accordingly, what is needed is a technique that allows charges to be binned together in a CCD image sensor while avoiding the disadvantages associated with the above-noted conventional techniques.
USPTO Backgrounds
USPTO Backgrounds