1. Field of the Invention
The present invention generally relates to the full speed testing of semiconductor memory chips. More particularly, this invention relates to a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM).
2. Description of the Prior Art
FIG. 1 shows a high-level block diagram of the interface between a memory controller 110 and a double data rate (DDR) synchronous dynamic random access memory (SDRAM) 120. The strobe signal, DQS, 130 strobe data at the proper time into the memory. The data or DQ 140 represents the data bus into the memory.
DQ means Data and Quest. In other words, “Data” means the controller sends any input data to memory and “Quest” means memory drives out any output data for the controller's pursuit. DQS means Data Quest Strobe. It works as a synchronous clock signal between the controller and memory to align and sample DQ.
FIG. 2 shows the prior art timing diagram for the interface between the controller and the DDR SDRAM memory. The clock 210 is shown with four edges of the clock labeled P, N, P, N & 1, 2, 3. 0. This represents the positive and negative bits of data being accessed to & from the memory. The command window of time is shown 220. This time window shows a write command and the column address 230 occurring simultaneously. The DQS, data strobe occurs in a burst of 4 clock pulses on the clock cycle after the write command. The burst length, BL=4 (215) is labeled in FIG. 2. The data bus, DQ, shows the 4 bits D0, D1, D2, and D3 250 to be written into memory by the above write command 220. The column address 260 has a low order bit B0 270, 280 which is shown in FIG. 2. A B0=0 (270) results in a data_p 275 and a data_n 276.
A B0=1 280 results in a data_p 285 and a data_n 286 as shown in FIG. 2. If B0=0 270, data_p 275 transmits two positive bits D0, D2 into internal even data path and data_n transmits two odd bytes D1, D3 into internal odd data path. If B0=1 280, data_n 286 transmits two negative bits D1, D3 into internal even data path and data_p 285 transmits two positive bits D0, D2 into internal odd data path. To employ B0 address bit as a switch control bit to transfer the external input data of positive/negative system into the internal data of even/odd system.
FIG. 3 shows the write command at internally doubling clock testing mode. The clock 310 is shown. The write command 320 is shown twice during two successive clock cycles. This indicates that the external burst length, BL=2 (315). The data bus DQ shows the 4 data bytes D0, D1, D2, D3 340 being strobed in on both the rising & falling edges of the DQS signal. An internal clock, 350 is shown. Its frequency is two that of the regular clock 310. This double speed internal clock 350 allows the normal internal burst length, BL=4 (325). The B0_sel 351 is shown when the B0 of the column address goes high. The data_even line 352 is shown with the two bytes D0 and D3. The data_odd line 353 is shown with the two bytes D1 & D2 shown.
For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. In the prior art during high speed test, this causes the data to be written or presented to the data path two times. Therefore in the prior art a full double speed stress test does not completely test the double speed data transition circuit paths.
U.S. Pat. No. 6,337,830 (Faue) “Integrated clocking latency and multiplexer control technique for double data rate (DDR) synchronous dynamic random access memory (SDRAM) device data paths” describes an integrated clocking latency and multiplexer control technique for double data rate (DDR) synchronous dynamic random access memory (SDRAM) device data paths.
U.S. Pat. No. 6,154,419 (Shakkarwar) “Method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory” describes a method and an apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory.
U.S. Pat. No. 6,043,694 (Dortu) “Lock arrangement for a calibrated DLL in DDR SDRAM applications” describes a lock arrangement for a calibrated DLL in DDR SDRAM applications.
USPTO Backgrounds
USPTO Backgrounds