The present invention relates to manufacturing technology for a semiconductor integrated circuit device, and particularly to a technology effectively applied to an electrical testing of a semiconductor integrated circuit device, wherein probes of a probe-card are pressed onto electrode pads of the semiconductor integrated circuit device.
Regarding probing of a semiconductor chip with bump electrodes of a semiconductor wafer, Japanese patent laid-open No. 2006-49599 discloses technology wherein an image of a state on each bump electrode is captured by a camera just after contact thereof with each probe, and a peripheral shape of each bump electrode (whether deformed or not), foreign material (bump chips) generation between bump electrodes, and the like are detected by comparing with reference data, so that contact system failures or defective appearances caused by probing can be identified rapidly.
USPTO Backgrounds
USPTO Backgrounds