The present invention relates to a method for interpolating an image signal in a processing apparatus of a digital image signal and a circuit thereof, and more particularly to a method for interpolating an image signal by using a slope correlation in two dimensions and a circuit thereof, in order to improve a picture quality by enhancing a vertical resolution.
In a processing of an image signal, it is a widely known fact that a digital processing method is superior to an analog processing method. Recently, in a television set or a video tape recorder (VTR), etc., an analog image signal is digitally processed by the analog to digital conversion and then the image signal is displayed on a screen by the digital to analog conversion. In this case, in order to improve a picture quality of the image signal, various interpolation methods are used. For example, an interlaced scanning method of 262.5 lines/field (525 lines/frame) is used in an NTSC, and a time difference between an odd field and an even field is 1/60 seconds. In the above time difference, the larger a screen is provided, the less vertical resolution is produced. This is because viewers come to sense a flicker phenomenon between lines. As a method for removing the flicker phenomenon, a line interpolation and a field interpolation have been used.
FIG. 1 is a block diagram of a conventional line interpolation circuit. A line interpolator 40 receiving an input image signal through an input terminal, generates a line interpolated signal. A scanning rate converter 80 receiving the line interpolated signal output from the line interpolator 40 and an input image signal, performs a non-interlace scanning. In this case, the image signal supplied through the input terminal is a digitally converted image signal. The line interpolator 40 delays the input image signal by one horizontal line and produces an interpolated image signal by averaging the delayed image signal and a next one horizontal line. That is, a 1H delay 40a is for delaying the input image signal by one horizontal line, an adder 40b is for adding the image signal of a current horizontal line to the image signal of a previous horizontal line and a multiplier 40c is for multiplying the added image signal by 1/2, to thereby perform a line interpolation. For example, if the image signal supplied to the 1H delay 40a in the line interpolator 40 is 8 bits data, the adder 40b produces 9 bits data. Therefore, the multiplier 40c multiplies the 9 bits data by 1/2, to thereby produce a line interpolated data of 8 bits. The input image signal of the input terminal and the line interpolated image signal output from the line interpolator 40 are applied to the scanning rate converter 80 to perform a non-interlace scanning. In this case, if the scanning period of one horizontal line is 63.5 .mu.sec., the input image signal is produced for 63.5/2(31.75).mu.sec, and the line interpolated image signal is produced for 63.5/2(31.75).mu.sec.
However, the above-described line interpolation method has a problem in that a vertical resolution is deteriorated since the current horizontal line and the previous horizontal line are interpolated by averaging the lines. To solve the above problem, in case of a still picture, a field interpolation is performed by selecting a previous field value as an interpolation value. However, since the field interpolation necessitates a field memory, it has a disadvantage that hardware is increased. Moreover, in case of a motion picture, a line interpolation is performed by using an adaptive interpolation. However, it cannot sufficiently decrease the deterioration of the vertical resolution.
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