1. Technical Field
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor device having semiconductor chips, which are stacked using through-electrodes.
2. Related Art
Packaging technologies for a semiconductor device have been developed to satisfy demands for miniaturization and high capacity. Recently, various techniques for stacked semiconductor packages capable of satisfying the demands toward miniaturization, high capacity and mounting efficiency have been developed. The term “stacking” as used in the semiconductor industry means to vertically place at least two semiconductor chips or packages. In the case of a memory device, it is possible with the stacking technology to realize a product having a larger memory capacity than obtainable through a semiconductor integration process as well as to increase efficiency in usage of the mounting area.
As an example of a stacked semiconductor package, a structure using through-silicon vias (hereinafter referred to as “through-electrodes”) has been suggested. The stacked semiconductor package using the through-electrodes provides advantages in that since an electrical connection between the semiconductor chips is made through the through-electrodes, it is possible to realize a semiconductor device with improved operation speed and with a miniaturized size.
However, the semiconductor chips stacked using the through-electrodes are venerable to physical impact and thus defects such as damage of the semiconductor chip are frequently occurred in a process of packaging the stacked semiconductor chips.
USPTO Backgrounds
USPTO Backgrounds