1. Field of the Invention
The invention relates to a method and to a circuit arrangement for controlling the serial bit streams through a microprocessor-controlled, serial interface circuit.
2. Description of the Prior Art
The performance capability of a microprocessor unit contained in a microprocessor-controlled, serial interface circuit arrangement is limited to a greater or lesser degree by numerous control jobs. For a data transmission, for example, a receiver must be synchronized so that a defined bit pattern is continuously supplied to it. Considerable outlay is needed for this function alone. Another example is monitoring messages that are received at the interface circuit arrangement. The messages must be checked repeatedly for changes and a determination must be made whether a new reaction by the microprocessor unit has become necessary. The microprocessor unit is not available for more difficult jobs, such as handling protocols of higher ISO levels during such monitoring jobs. Overload of the microprocessor unit and, as a result, loss of time can occur merely on the basis of the control and monitoring jobs high line speeds. Time losses also occur when the microprocessor unit can only conditionally consider different time conditions as a consequence of different data transmission rates. These losses occur because the microprocessor unit has no chronological information indicating when the transmission of a serial bit stream has ended. A bit stream can be transmitted with different BAUD rates. A succeeding bit stream can only be transmitted when the preceding bit stream has been transmitted. So that no time problems arise, the microprocessor unit usually assumes that a bit stream was transmitted with the slowest BAUD rate.
USPTO Backgrounds
USPTO Backgrounds