In the semiconductor manufacturing, as very-large-scale integration (VLSI) becomes a development trend, the feature size of integrated circuits (ICs) continuously decreases. In order to accommodate the reduction of the feature size, the channel length in metal-oxide-semiconductor field-effect transistors (MOSFETs) is correspondingly reduced. However, as the channel length of a device decreases, the distance between the source and the drain in the device is shortened, which leads to deteriorated gate-to-channel control ability. Therefore, it is more difficult for the gate voltage to pinch off the channel, and the subthreshold leakage phenomenon, i.e. the short-channel effects (SCEs), more likely occur.
In order to better accommodate the reduction of the feature size, the semiconductor technology begins a gradual transition from planar MOSFET transistors to more efficient three-dimensional transistors, such as fin field-effect transistors (Fin-FETs). In a Fin-FET device, the gate electrode is able to control an ultra-thin structure (i.e. fin structure) at least from the both sides of the ultra-thin structure. Therefore, compared to traditional planar MOSFET devices, Fin-FET devices may demonstrate better gate-to-channel control ability, and thus may suppress the SCEs effectively.
However, it is still desirable to improve the electrical performance and the stability of conventional Fin-FET devices. The disclosed Fin-FET devices and fabrication methods thereof are directed to solve one or more problems set forth above and other problems in the art.
USPTO Backgrounds
USPTO Backgrounds