This invention pertains to electronic circuits and more particularly to high speed auto zero comparators used in charge balancing approximation A/D converters. The circuits of this invention are capable of operating at high speed in the auto zero mode to cancel the first order of offset voltage prior to performing comparisons.
One example of a prior art comparator circuit is shown in FIG. 1. Comparator circuit 10 of FIG. 1 is formed of three comparators 11, 12, and 13 connected in cascade to provide greater gain with minimal delay time. Two input signals to be compared are applied to non-inverting input lead 101 and inverting input lead 102 which are then capacitively coupled via capacitors 115 and 116 to non-inverting input lead 111 and inverting input lead 112, respectively, of comparator 11. Comparator 11 provides a complementary output signal on inverting output lead 113 and non-inverting output lead 114 which are capacitively coupled via capacitors 125 and 126 to non-inverting input lead 121 and inverting input lead 122, respectively, of comparator 12. The complementary output signals on output leads 123 and 124 of comparator 12 are similarly capacitively coupled to the input leads of comparator 13, and the differential output signals from comparator 13 are provided on output terminals 103 and 104.
Each comparator 11, 12, and 13 have associated switches 117, 118; 127, 128; 137, 138 which serve to connect the inverting output lead of a comparator to its non-inverting input lead, and its non-inverting output lead to its inverting input lead during an auto-zero mode of operation.
The substrates of switches 117, 118, 127, 128, 137, 138 are connected to ground. In charge balancing successive approximation A/D conversion, during phase one of the clock, VIN and VREF voltages are sampled on input terminals 101, 102 of capacitors 115 and 116, respectively. At the same time, switches 117, 118, 127, 128, 137, and 138 are turned on, which puts the comparators in the auto zero mode. The effective input referred offset voltage which is stored at node 111 and 112 is ##EQU1## where V.sub.OS1, V.sub.OS2, V.sub.OS3 and G.sub.1, G.sub.2, G.sub.3 are the intrinsic offset voltages and gains of comparators 11, 12, 13, respectively.
During phase two of the clock, switches 117, and 118 are opened first, then switches 127 and 128 are opened, then switches 137 and 138 are opened, and then node 101 is connected to VREF/2; node 102 is always kept at VREF. The order of switching sequence serves to minimize the effective residual offset voltage and imbalanced charge injection seen at nodes 111 and 112. Thus, VIN is compared with VREF/2 while VOS is kept at minimum.
For phase one of next clock cycle, VIN and VREF are again sampled on capacitors 115 and 116, respectively, and in phase two VIN is compared with VREF/4 or with 3VREF/4, depending on the previous result. For completeness, comparator 10 is usually followed by a clocked regeneration latch (not shown) which converts the analog signal at output nodes 103 and 104 to digital levels which are subsequently stored in a register (not shown). For an n bit A/D converter, n cycles conversion time is required.
To reduce conversion time, a cascade of comparators as described above can be used to minimize the time required to complete phase two. To minimize the time required to complete phase one without losing accuracy, the novel high speed auto zero technique of this invention is incorporated in the comparator design.
FIG. 2 is a schematic diagram of a typical comparator which may be used as comparators 11, 12, and 13 of FIG. 1. Reference numerals in FIG. 2 are shown referred to comparator 11 of FIG. 1. As shown in FIG. 2, comparator 11 includes non-inverting input terminal 111 and inverting input terminal 112. Comparator 11 of FIG. 2 is shown in the auto-zero mode. For AC analysis, input capacitors 115 and 116 are shown connected from input nodes 111 and 112, respectively, to ground. Comparator 11 also includes inverting output terminal 113, and non-inverting output terminal 114. Output load capacitances 125 and 126 are shown connected between output terminals 113 and 114, respectively, and ground. Switch 117 is provided by transistor M4A, having current handling terminals connected between inverting output terminal 113 and non-inverting input terminal 111. Similarly, switch 118 is provided by transistor M4B having its current handling terminals connected between non-inverting output terminal 114 and inverting input terminal 112. Transistors M2A and M2B provide a differential transistor pair having their sources connected in common to current source I2 and their drains connected to load devices M1A and M1B, respectively. Connected to the drain of transistor M2A is parasitic capacitance 413A, which is due to the drain junctions of transistors M1A and M2A, and the gate of transistor M3A. Connected to the drain of transistor M2B is parasitic capacitance 413B, which is due to the drain junctions of transistors M1B and M2B, and the gate of transistor M3B. Transistors M3A and M3B serve as source followers connecting the drains of differential transistors M2A and M2B to output terminals 113 and 114, respectively. Current sources Il and I3 serve as pull down loads for transistors M3A and M3B, respectively.
Unfortunately, the prior art circuit of FIG. 2 is unstable during the auto-zero mode of operation, causing its voltages not to settle to 0.2% or better for an 8 bit A/D converter and higher accuracy converter during the auto-zero mode. The gain of comparator 11 is EQU G.apprxeq.-g.sub.M2A R.sub.out where (1) ##EQU2##
The dominant pole of comparator 11 is ##EQU3##
The unity frequency P.sub.u, i.e. the frequency where the gain is equal to one is EQU P.sub.u =G.multidot.P.sub.d (3)
Then combining equations 1, 2, 3: ##EQU4##
The non-dominant poles are ##EQU5##
It is well known that the necessary condition for comparator 11 in the auto-zero mode to be stable is EQU P.sub.nd2 &gt;1.7P.sub.u (7)
Combining equation 7 with equations 6 and 4 gives ##EQU6## which yields ##EQU7## Thus ##EQU8## the ratio of the channel width to channel length of transmission gate M4A, must be made large since its on resistance R.sub.on is proportional to its channel length and inversely proportional to its channel width. Unfortunately, increasing the ratio of the channel width to channel length of transmission gate M4A results in a large charge injection into node 111 and node 112 after switching off transmission gates M4A and M4B, thereby reducing the accuracy of the comparator.
Furthermore, comparator 11 is not very effective at operating at low supply voltages and at high temperature because R.sub.on of transistor M4A is increased with lower supply voltages and with increasing temperature (i.e. transistor M4A is not turned on as hard).
Other prior art is known. U.S. Pat. No. 4,513,212 describes a circuit for automatically clamping the P wells of a CMOS integrated circuit to the most negative potential of the integrated circuit as a whole. U.S. Pat. No. 4,665,326 describes a voltage comparator including offset correction circuits including a digital to analog converter error register for providing correction voltages to a set of capacitors contained within the error circuit. U.S. Pat. No. 4,417,160 describes a comparator including offset compensation in which a potential offset means is included in the auto-zero feedback loop having an offset comparable to the input offset of the threshold detector, thereby allowing the offset correction voltage to track the input offset voltage over time and temperature. U.S. Pat. No. 4,587,443 describes an auto-zero sample and hold circuit including switches for, during the hold period, minimizing the effect of offset voltages by connecting the output of the comparator to its input and reversing the interstage connections between two cascaded differential amplifiers. Patentscrift DD. No. 233898A1 describes a comparator including a feedback loop between the output of the comparator and the input of the first amplifier. Offset is further reduced by the use of a dummy transistor. European Patent Application No. 001 555 4A1 describes a comparator circuit including switch means for shorting out the differential input leads prior to reading an input signal. U.S. Pat. No. 3,585,510 pertains to a comparator circuit and more particularly the threshold setting circuit connected to the input leads of the comparator circuit. The threshold voltage is maintained at a desired level regardless of changes in the duty cycle of an AC input signal. U.S. Pat. No. 4,163,947 describes an auto-zeroing integrator in which, during an auto-zero mode, the current flowing into the input of the integrator is measured and a charge is stored which thereafter provides an equal but opposite current to the input of the integrator. U.S. Pat. No. 4,542,305 pertains to an impedance buffer, and U.S. Pat. No. 4,739,192 pertains to a digital to analog converter bit switch. "MOS Transistor Electronic Stablization of Thresholds," IBM Technical Disclosure Bulletin, Vol. 10, #3, August 1967, pp. 336-337 describes a circuit for allowing a first transistor to provide a bias current to a second transistor, with the current flowing through the second transistor setting the level of the substrate voltage of the second transistor. This substrate voltage is maintained relatively constant over a wide number of devices, regardless of process variations and the like. This allows a large number of devices to be manufactured having similar threshold voltage levels, regardless of process variations.
USPTO Backgrounds
USPTO Backgrounds