1. Field of the Invention
The present invention relates to a three-dimensional multi-chip module comprising a plurality of semiconductor chips, and more particularly to a multi-chip module having a structure whereby higher integration density and high power output is achieved.
2. Description of the Related Art
The most typical three-dimensional multi-chip module of the prior art is schematically illustrated in FIG. 1. A plurality of semiconductor elements (chips) 10 are arranged on both surfaces of a substrate 2. Wiring patterns and electrode terminals (not shown) are formed in advance on the surfaces of the substrate 2, and bonding pads formed on each semiconductor element 10 are operatively connected to electrode terminals of the wiring patterns by bonding wires 13. The substrate 2 with semiconductor elements 10 thereon is disposed on a stage 11a of a lead frame 11, and electrode terminals of the wiring pattern are operatively connected by bonding wires 15 to inner leads 11b of the lead frame 11. The sub-assembly thus formed is molded in a mold package 18 of epoxy resin.
In order to obtain a higher integration density in a multi-chip module, a wireless bonding method has been utilized. As the wireless bonding method, flip-chip, beam lead and TAB (tape automated bonding) methods are widely known. Among these methods, the flip-chip method is most effective for saving bonding area on the surface of a substrate.
When the multi-chip module includes a semiconductor element which generates a lot of heat during operation, a problem of dissipating such heat from the multi-chip module arises. FIG. 2 shows an example of a multi-chip module of the prior art, in which the multi-chip module comprises two high power output semiconductor elements 10a. The multi-chip module further comprises two semiconductor elements 10b which have comparatively small heat generating characteristics. The semiconductor elements 10a and 10b are all bonded facedown to a substrate 2 using a flip-chip bonding method, wherein, bumps 14 of solder are formed in advance on the major surfaces of the semiconductor elements, and the semiconductor elements are disposed on the substrate 2 so that the bumps are brought into contact with electrode terminals of a wiring pattern (not shown) on the substrate 2 and bonded thereto. The wiring pattern is connected to outer leads 12. The back surfaces of the high power semiconductor elements 10a are held in contact with a heat conductive base 4 using heat conductive paste 16 disposed therebetween. After affixing a heat sink 5 to the above package, the multi-chip module is finally completed.
The package structure of the prior art of FIG. 2 encloses semiconductor elements which are arranged two-dimensionally on a front surface of the substrate 2 only. Therefore, integration density can not be increased to the level of three-dimensional multi-chip modules. Further, there is a problem that mixed attachment of the semiconductor elements is difficult, in which one semiconductor element requires wire bonding and an other semiconductor element requires flip-chip bonding.
USPTO Backgrounds
USPTO Backgrounds