The present invention relates to the improvement of a power supply circuit having a temporary backup function.
In general, a semiconductor integrated circuit such as a TTL control logic circuit requires a continuous supply of low voltage power (e.g., 5 V). To protect the integrated circuit against damage resulting from a sudden loss of power supply, the main power supply source normally includes a large capacitance capacitor or a rechargeable battery serving as a backup power source.
FIG. 3 shows a schematic circuit diagram of a prior art power supply circuit having a backup function.
Power supply 10 includes an electronic voltage regulator. Unregulated DC input voltage V1 of power supply 10 is obtained from a conventional AC rectifier circuit (not shown). Power supply 10 outputs regulated voltage V2. A load such as a RAM and/or TTL logic board (not shown) is coupled to the output circuit of power supply 10, via forwardly-biased diode 13. Power supply voltage V3 is applied to the load. (V3=V2-VF13; VF13 is a forward voltage drop of diode 13).
Resistor 11 and capacitor 12 together constitute a series circuit which is parallel coupled to the voltage V3 circuit. Diode 14 is parallel connected to resistor 11 such that it is reversed biased by voltage V3 when power supply 10 is in operation. The resistance of resistor 11 can be, for example, anywhere from several ohms to several tens of ohms. Diode 13 prevents discharging from capacitor 12 to power supply 10. Diode 14 equivalently reduces the parallel resistance of resistor 11 and diode 14 when power supply 10 is shut down and when the load is supplied with current from capacitor 12.
Assume that diodes 13 and 14 are Schottky barrier diodes each of whose respective forward voltage drops VF13 and VF14 is 0.4 V, that an allowable range of load voltage V3 is 5 V.+-.5% (4.75 V to 5.25 V), and that a nominal value of voltage V3 is 5.2 V. Based on this assumption, regulated voltage V2 from power supply 10 is to be 5.6 V (=5.2 V+0.4 V of diode 13).
FIG. 4 shows an output voltage characteristic of the circuit of FIG. 3. When a fault develops in power supply 10 and voltage V2 comes down zero (time t1), load voltage V3 is correspondingly reduced from 5.2 V (charged-up voltage of capacitor 12) to 4.8 V (=5.2 V-0.4 V of diode 14). Whereupon, capacitor 12 is discharged by the load, chiefly via diode 14. With this discharging, load voltage V3 is gradually reduced from 4.8 V to the underlimit load voltage of 4.75 V (from time t1 to time t2 in FIG. 4).
Assume that the capacitance of capacitor 12 is C, the load current is I, the allowable variation range of voltage V3 is .DELTA.V, and the voltage compensation period for ensuring V3.gtoreq.4.75 V is T. Then, the following equation can be obtained: EQU C=(I.times.T)/.DELTA.V (1)
When equation (1) is applied to the above assumption, we obtain EQU C=(I.times.T)/(0.05)=20(I.times.T) (2)
The coefficient "20" in equation (2) indicates that a large capacitance is required for capacitor 12. (Conventionally, T is 0.1 second or more.) This is a disadvantage of the prior art as is shown in FIG. 3.
USPTO Backgrounds
USPTO Backgrounds