1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly to a semiconductor package with a structure capable of eliminating the use of a lead frame and metal wires, thereby simplifying the manufacture and construction of semiconductor devices and achieving an application to multi-pin constructions of integrated circuits, a simplification, a lightness, a thinness, a compactness in construction and an improvement in the degree of dense integration.
2. Description of the Prior Art
Referring to FIGS. 1 and 2, there is illustrated a general semiconductor package. As shown in the drawings, the semiconductor package comprises a lead frame having a paddle 1 to which a semiconductor chip 3 is fixedly attached by means of an adhesive 2. The lead frame also has a plurality of inner leads 4 which are electrically connected to a plurality of bonding pads 3a formed at opposite side edges of the semiconductor chip 3 by means of metal wires, respectively. The semiconductor chip 3 and the inner leads 4 of lead frame are molded with an epoxy molding compound 6, to form a sealed mold body. The lead frame also has a plurality of outer leads 7 which are protruded outwardly of the mold body and bent to have a certain shape.
According to the recent tendency of providing packages having more light, thin, simple and compact structures, there have been proposed semiconductor packages comprising a lead frame having no paddle. In such semiconductor packages, a semiconductor chip 3 is attached to inner leads 4 of the lead frame, by means of an insulating tape 8, as shown in FIGS. 3 and 4. These semiconductor packages are classified into semiconductor packages of a chip on lead (COL) type wherein the semiconductor chip 3 is laid on the inner leads 4 of lead frame as shown in FIG. 3 and semiconductor packages of a lead on chip (LOC) type wherein the inner leads 4 of lead frame are laid on the semiconductor chip 3 as shown in FIG. 4.
In FIGS. 3 and 4, the same constituting elements as those of the general package shown in FIG. 1 are denoted by the same reference numerals and their detailed description is omitted.
However, all of the above-mentioned various semiconductor packages are manufactured by using a lead frame. That is, they should have inner leads and require a bonding work using metal wires 5. As a result, they have a disadvantage of an increase in size, namely, occupation area. Additional troubles may also occur due to the materials used for constructing the structure of semiconductor package. For example, a breakage of semiconductor package may occur due to the thermal expansion coefficient difference among constituting materials such as a silicon, an adhesive, a metal for lead frame and an epoxy molding compound. Due to the bonding work using metal wires, a degradation in electrical characteristic of the semiconductor chip and a difficulty in wire bonding may occur. Consequently, the above-mentioned conventional constructions have a difficulty in manufacture.
USPTO Backgrounds
USPTO Backgrounds