1. Field of the Invention
This invention relates to a debug circuit for a multi-mode circuit driven by a clock signal, and a method of debugging a multi-mode circuit using such a debug circuit.
Multi-mode circuits, such as for example Track and Hold, Acquire and Transfer, and Reset and Sample circuits, are commonly controlled by a clock signal. An example of the operation of a Track and Hold circuit is shown in FIG. 6. The circuit takes an input signal S and a clock signal C, and gives an output signal O. When the clock signal is in the high state, as for example between times t1 and t2, the output signal O of the circuit tracks the input signal S. When the clock signal switches to the low state, the output signal O holds at the level of the input signal S when the switch occurred. So for example between times t2 and t3 the output signal O is maintained at the level of the input signal at time t2. Such a circuit is used for example with an analogue-to-digital converter (ADC), which requires a steady input when it is performing the analogue-to-digital conversion.
The output signal O in FIG. 6 shows the ideal output of a Track and Hold circuit; however, in practice such an ideal signal will not be achievable. A Track and Hold circuit is prone to two main types of errors, which are shown in FIG. 7.
The first type of error is known as “hold mode settling”. At time t100, when the clock signal C switches from the high state to the low state, the output signal O should be maintained at the level of the input signal S. As shown, however, the output signal O will in fact take a certain amount of time to settle onto the correct signal level. If the clock speed is high then the output signal may fluctuate for a large fraction of the duration of the Hold mode, which could for example prevent an ADC from making a correct conversion.
The second type of error is known as “imperfect acquisition”. At time t101, when the clock signal C switches from the low state to the high state, the output signal O should move from the level it has been maintaining to the level of the input signal S, which it tracks. Ideally this movement would be instantaneous, but as shown the output signal O will in fact take a certain amount of time to reach and track input signal level S. If the output signal O has not yet begun to correctly track the input signal S when the clock signal C switches from the high state to the low state, then the level maintained during the next Hold mode will be incorrect.
At slow clock speeds these errors are unlikely to affect the operation of a circuit, but as clock speeds are increased one or other error is likely to become a problem. However, often the only available output will be that of a circuit as a whole, for example the output of an ADC. Although it can be seen that output errors occur, there is no indication as to whether the errors are caused by hold mode settling or imperfect acquisition.
2. Description of Related Art
A known solution to this problem is to include a circuit to allow the durations of the high and low states of the clock cycle to be continuously varied. If errors are occurring, the duration of (say) the low state can be increased while keeping the duration of the high state constant. If the output errors stop, then the errors must occur while the clock is in the low state, so in other words are most likely due to hold mode settling. If on the other hand the output errors remain when the duration of the low state is increased, but stop when the duration of the high state is increased, then the errors must occur while the clock is in the high state, so are most likely due to imperfect acquisition.
Although this solution is effective at identifying the mode in which errors occur, such a circuit to vary the clock state durations is complex to implement and requires a high component overhead. It is also applicable to only dual-mode circuits. A simple circuit that allowed debugging of multi-mode circuits would be advantageous.
USPTO Backgrounds
USPTO Backgrounds