The present invention relates to a discharge circuit for a capacitive load, in particular for a programming and read line in an EEPROM memory.
EEPROM memories contain, in a sufficiently known manner, a number of memory cells which in each case have, as memory element, a MOSFET component with an additional gate electrode arranged in floating fashion. Memory cells of this type are described for example in Sze: “Semiconductor Devices, Physics and Technology”, 2nd Edition, Wiley, 2002, pages 216-218. During the programming operation, the gate connections of the memory MOSFETs are put at a high potential, for example a potential of between 15 V and 20 V, it being possible for the gate connections of a plurality of cells to be connected to a common line. The individual cells are then programmed in a manner dependent on whether a high potential is present at the source connections of the individual cells, so that no programming is effected, or a low potential is present, so that programming is effected.
After the programming operation, the programming line has to be discharged from the high potential to a low potential, for example to a potential which is applied to the gate connections for the read-out of the individual cells and which usually lies in the range of between 2 V and 5 V. The discharge of the programming and read line, which constitutes a capacitive load, is intended to be effected as rapidly as possible, on the one hand, and, on the other hand, it is necessary to limit the maximum discharge current in order to prevent destruction of the circuit. Furthermore, it should be ensured that a potential source that prescribes the potential for the read operation is loaded as little as possible by the discharge of the programming and read line.
Furthermore, there are EEPROM memories in which the memory content is erased by application of a large positive voltage and which are programmed by application of a negative voltage. In these memories, too, there is the problem of discharging a line acting as a capacitive load, in the present case the “erase and read line” of the memory, from a high potential still present after the erasure to a low potential.
USPTO Backgrounds
USPTO Backgrounds