1. Field of the Invention
This invention relates in general to the field of semiconductor memories and, more specifically, the read-out circuits implemented in these memories for detecting the logic programming state of the storage cells.
The invention will be described in reference to magnetic random access memories (MRAM), although it can be applied to other types of memory.
2. Discussion of the Related Art
MRAMs are non-volatile memories. Typically, a magnetic random access memory device includes a matrix of cells arranged in rows and columns, through which metal tracks are routed. The metal tracks extending along the memory cell rows are called word lines and the metal tracks extending along the memory cell columns are called bit lines. Each memory cell thus located at the intersection of a word line and a bit line stores a data bit in the form of a magnetization orientation.
Each of the memory cells indeed consists of two magnetic layers, separated by a dielectric layer. Each magnetic layer has a specific magnetization orientation. The magnetization orientation of one of the layers, a so-called free layer, can be modified, while the magnetization orientation of the other, so-called fixed layer, is fixed in a particular orientation. The magnetization orientations of the two layers can be found in two situations: either parallel, i.e. aligned in the same directions, or anti-parallel, i.e. aligned in opposite directions. These two orientations, parallel and anti-parallel, represent the logic values “1” and “0”, respectively. Alternatively, the parallel state can be interpreted as a logic “0” and the anti-parallel state as a logic “1”.
Consequently, the writing for such a memory cell involves positioning the magnetization orientation in the free layer according to the desired logic state, in either a parallel state or an anti-parallel state, with respect to the magnetization orientation of the fixed layer, by imposing a sufficient magnetic field on the tunnel junction.
Typically, external magnetic fields are applied to a cell selected to switch the magnetization orientation in the free layer of this cell from one state to the other. To do this, a writing current is applied respectively to the word line and the bit line intersecting at the location of the selected memory cell. The writing currents thus applied to the selected word line and bit line create magnetic fields that, when they are combined at the intersection of the word line and the bit line, enable the magnetization orientation of the free layer of the selected memory cell to be switched from the parallel to the anti-parallel state, or the reverse, according to the data that is to be written into the cell.
In the reading, a voltage is applied to the terminals of the memory cell concerned by means of a CMOS control transistor, and the current circulating through the read bit line is measured, its value representing the tunnel junction resistance. The read bit line therefore enables information on the state of a memory cell located at the intersection of this bit line and a selected word line to be transmitted. The read-out circuits are connected to the bit lines, optionally by means of a multiplexer if there is a plurality of bit lines for a single read-out circuit. The constitution of a single read-out circuit, considered to be connected to a single bit line, will be described below so as to simplify the explanations.
The resistance of the junction is dependent on the respective magnetization orientation of the two magnetic layers. The resistance changes from a lower resistance value, corresponding, for example, to the low logic state, when the magnetization orientation of the two layers is aligned in the same direction, to a higher resistance value, corresponding, for example, to the high logic state, when the magnetization orientation of the two layers is in opposite directions. The general principle of a read-out circuit is therefore to detect this difference in value so as to read the information stored by the memory cell concerned. It is routine in the prior art to detect the programming state of a memory cell by comparing the value of the tunnel junction resistance of this cell with a reference value corresponding to the mean value of the resistances of a reference memory cell in the high logic state and a reference memory cell in the low logic state.
U.S. Pat. No. 6,600,690 describes a read-out circuit implementing this principle. FIG. 1 shows a simplified example of a read-out circuit according to the teaching of this document.
A memory cell, represented by the resistor Bit, can be selected and delivers information on the bit line BL. To do this, the bit line BL is polarized at a fixed reading voltage, by an NMOS control transistor N2, which is intended to provide a current Ibit to the bit line while limiting the potential at the terminals of the memory cell to a predetermined constant value, enabling the very low thickness of the oxide on which the magnetic tunnel junction of the memory cell is based to be taken into account. Then, the actual reading phase takes place and the current Ibit of the bit line is compared to a reference current, so as to determine the programming state of the selected cell.
Two reference lines LR1 and LR2, with characteristics very similar to the bit line, are also therefore polarized for the reading, while being limited in voltage by means of an NMOS control transistor N1 and an NMOS control transistor N3. During the reading phase, these two reference lines consume a current equivalent to that, Ilow, which is consumed by a memory cell programmed to the low logic state, represented by the resistor Reflow placed in the low impedance state, and that, Ihigh, which is consumed by a memory cell programmed to the high logic state, represented by the resistor Refhigh placed in the high impedance state.
To read the state of the memory cell, a comparison will be made between the current consumed by the bit line and a reference current. More specifically, the current consumed by the bit line will be compared to a reference current which is an average of the currents consumed by a cell programmed to the high logic state and a cell programmed to the low logic state.
To do this, in a first branch, the drain of the NMOS transistor N2 is connected to the resistor Bit. The gate of the transistor N2 is connected to a control voltage Vsacg generated so as to maintain a constant potential on the bit line, taking into account the aforementioned constraint. The source of the transistor N2 is connected to the drain of a PMOS transistor P2, of which the source is connected to a supply voltage Vdd. An output node Out is provided at the level of the drain of the transistor P2 so as to provide the output signal of the read-out circuit.
In a second branch, the drain of the NMOS transistor N1 is connected to the reference memory cell Reflow placed in the low logic state. The gate of N1 is connected to the gate of the transistor N2 and the source is connected to the drain of a PMOS transistor P1, of which the source is connected to the supply voltage Vdd. The gate of the transistor P1 is connected to its drain and to the gate of the PMOS transistor P2.
In a third branch, the drain of the NMOS transistor N3 is connected to the reference memory cell Refhigh placed in the high logic state and to the drain of the transistor N1 of the second branch, thus placing the two reference memory cells Reflow and Refhigh in short circuit. The gate of N3 is connected to the gate of transistor N2 and its source is connected to the drain of a PMOS transistor P3, the source of which is connected to the supply voltage Vdd and the gate of which is connected to the gate of transistor P1. A reference output node Outref is provided at the level of the drain of transistor P3 so as to provide a reference output signal of the read-out circuit.
A reference current Iref is thus generated by the two PMOS transistors P1 and P3, and the two NMOS transistors N1 and N3, with Iref=(Ilow+Ihigh)/2. The two transistors P1 and P3 form a current mirror with transistor P2. To simplify the explanation, we will now describe FIG. 2, which is a simplified representation of the stage of the read-out circuit of FIG. 1 with only one PMOS transistor P1 and only one NMOS transistor N1 for generating the reference current Iref.
Transistors P1 and P2 are therefore in a current mirror configuration. The first branch of the mirror includes the write transistor P2; the second branch includes the reference transistor P1. Thus, the write transistor P2 tends to copy the reference current Iref which circulates in the reference transistor P1. The potential at the level of the output node Out of the read-out circuit then varies according to the difference of currents Iref−Ibit, making it possible to determine, by comparison with the reference node Outref providing a potential representative of a cell in the intermediate logic state between the high and low logic states, whether the selected cell is in a programming state corresponding to the high or low logic state.
The problems of such an architecture are described in reference to FIG. 3, showing the reference branch of FIG. 2, and are essentially associated with the low supply voltage Vdd used, typically of around 900 mV.
The polarization voltage Vbitline of the reference bit line required by transistor N1 must also be sufficiently high. Indeed, in view of the resistance values to be considered, of around ten kiloOhms, a polarization of the bit line at an excessively low voltage would result in circulation of an excessively low current in the bit line. Therefore, the Vbitline is selected at around 300 mV, which is a good compromise between the need to have sufficiently high bit line currents and the need to preserve the thin oxide of the tunnel junction.
In addition, as the NMOS transistor N1 operates in the saturated zone, a drain-source saturation voltage Vdssat above 100 mV must be maintained at the terminals of the transistor.
All that remains is 500 mV for the gate-source voltage Vsg of the PMOS reference transistor P1. The PMOS transistor in the current mirror therefore has only a small amount of voltage Vsg available for its polarization.
As will be seen, this limitation becomes very important when considering the mismatch problem in the current mirror circuits. The mismatch is caused by variations in the characteristics of transistors inherent to the production method. Indeed, problems of repeatability in the transistor production method, for example at the level of the implantation of dopants, can cause the MOS transistors, which are intended to be strictly identical, to nevertheless have differing characteristics. Thus, the mismatch is misleading in the current mirror ratio, which is capable of falsifying the write current and, therefore, the variation in potential at the level of the output node OUT on which the reading is dependent.
The mismatch in a current mirror can be modelled by the following simplified equation, which corresponds to a low polarization condition (Vsg−Vt):o2(ΔIsd/Isd)≅4*A(Vt)2/[(W*L)*(Vsg−Vt)2]wherein Isd is the drain-source current of the transistors in the current mirror, Vt is their threshold voltage, Vsg is their gate-source voltage and W*L is their size.
The variation on the saturation current drawn by the PMOS transistor is therefore dependent on three main factors according to the simplified equation: A(Vt)2, W*L and (Vsg−Vt)2. The term A(Vt)2 is a factor that cannot be altered and that is dependent on the production method. It is representative of the quality of the method in its capability to produce MOS transistors that are as similar as possible.
As regards the second term W*L, the greater the size of the MOS transmitters in the current mirror, the more limited the mismatch will be.
However, given the aforementioned constraint in the reading system with regard to the low voltage Vsg available for the polarization of the PMOS transistor in the current mirror, the term (Vsg−Vt)2 will clearly have a very negative impact on the mismatch in the current mirror. Thus, there is a high probability that the variation on the saturation current drawn by the current mirror will be such that the reading is impossible. Indeed, since the differences in tunnel resistance to be measured, which enable the stored logic data to be provided, are small, the available signal to be detected for the reading, which is dependent on the difference between the reference current provided by the current mirror and the current circulating in the read bit line, is also relatively small. Thus, if the PMOS transistors cause too great a mismatch in the current mirror as explained above, the signal available for reading the information will not be operable.
It is possible to consider compensating for the negative impact of the term (Vsg−Vt)2 by increasing the size W*L of the PMOS transistors of the current mirror and therefore their width W so as to achieve an acceptable mismatch. The drain capacity of the transistors will, however, increase in proportion to the W of the transistor. However, as this drain capacity is directly associated with the nodes Out and Outref of the circuit, the latter will be rendered more capacitive, which is disadvantageous in terms of reading speed. Indeed, the potentials will need more time to reach the level of the nodes Out and Outref in reading phase.
USPTO Backgrounds
USPTO Backgrounds