1. Field of the Invention
This invention relates to an electrically data rewritable non-volatile semiconductor memory device. More particularly, it relates to a multi-value flash memory adapted to store a multi-valued data in a memory cell.
2. Description of the Related Art
In a flash memory, the accumulated electric charge of the floating gate of a memory cell transistor is changed as the stored data is erased and a new data is written there. Then, as a result, the threshold value is changed to store the data. For instance, the negative threshold value may be made to corresponds to a “1” data, whereas the positive threshold value may be made to corresponds to a “0” data.
In recent years, multi-value flash memories adapted to store a plurality of bits in a single memory cell have been developed to reduce the cost per bit and/or increase the storage capacity. In a memory device adapted to store two bits in a single memory cell, the memory cell has four threshold values depending on the data to be stored there.
A highly reliable memory device can be obtained by accurately controlling the threshold values of each memory cell. “Fast and Accurate Programming Method for Multi-level NAND EEPROMs, pp. 129-130, Digest of 1995 Symposium on VLSI Technology” proposes a method of writing data, raising the write voltage Vpgm at a rate, in order to precisely control the threshold values of each memory cell.
With the method proposed in the above cited document, the width of distribution of each threshold value can be controlled theoretically to as small as 0.2V by raising the write voltage Vpgm at a rate of 0.2V/10 μsec. Normally, the write voltage Vpgm is divided into a plurality of write pulses and the voltage Vpgm of the pulses is raised stepwise at a predetermined rate. This technique provides an effect similar to that of continuously raising the write voltage Vpgm. The threshold value is checked after applying each pulse to the memory cell and the write operation is terminated when the threshold value has got to a predetermined verification level.
Meanwhile, micronization of processing dimensions is in progress. This means that the gaps separating memory cells are made smaller and smaller to consequently give rise to various problems from the viewpoint of multi-valued flash memories. For instance, the distance separating floating gates is reduced to produce problems as pointed out below as a result of micronization.
Imagine two memory cells A and B arranged side by side. Assume that the data of the two memory cells are erased simultaneously and they are made to have a threshold value of −3V. Then, firstly a data is written into the memory cell A. As a result, its threshold value may be raised to 0.5V to 1V. Subsequently, another data that is different from the data written into the memory cell A is written into the memory cell B. As the threshold value of the memory cell B is raised to 1.5V to 2V, the electric potential of the floating gate of the memory cell A falls and its threshold value is raised, say, to 1V to 1.5V as a result of the capacitive coupling of the floating gates of the two memory cells.
In the above described instance, the difference of the threshold values of the memory cells A and B (read out margin) should be at least 0.5V. However, it is reduced to 0V as a result of the capacitive coupling of the floating gates of the two memory cells. Thus, the difference of the threshold values necessary for discriminating two different data is reduced and the read out margin disappears.
How the threshold value of a memory cell storing a data written in advance in a manner described above changes under the influence of a write operation of another memory cell will be described below by referring to FIGS. 1A through 1C of the accompanying drawing.
FIG. 1A shows the electric charge of the floating gate FG1 of a memory cell where the data stored there is erased and subsequently a new data is written. Electrons are accumulated in the floating gate FG1 of the memory cell where a data is written. In FIG. 1A, “- -” indicates electrons. Subsequently, data are written in the memory cells located respectively at the two sides of the first memory cell and having respective floating gates FG2, FG3. Then, a change occurs at the floating gate FG1 of the first memory cell as shown in FIG. 1B. The electric potential of the memory cell where a data is written first falls and its threshold value rises as shown in FIG. 1C because of the electrostatic capacitive coupling of the neighboring floating gates FG2, FG3. Then, as a result, the threshold value of the memory cell having the floating gate FG1 shows a wide distribution. In FIGS. 1A and 1B, reference symbol WL denotes the word line (control gate) arranged commonly for the memory cells having the floating gates FG1, FG2, FG3.
Thus, the technological development for reducing the distribution width of the threshold value of a memory will become increasingly important in the future in order to cope with this problem.
It may be conceivable to reduce the stepwise increment Dvpgm of the write voltage Vpgm in order to avoid this problem. For example, the distribution width of the threshold value is reduced from 0.5V to 0.1V to increase the write out margin by 0.4V by reducing the stepwise increment Dvpgm from 0.5V to 0.1V.
However, as the stepwise increment is reduced to ⅕ of the original value, the number of pulses becomes five times as many as the original number. Then, the write time will become five times as long as the original value to give rise to a new problem.
Therefore, so far, any attempt at securing a write out margin and raising the reliability of a memory device is accompanied by the problem of an increased write time.
USPTO Backgrounds
USPTO Backgrounds