The present invention generally relates to packaging of semiconductor devices, and more particularly to a method of forming a multi-chip module with a non-embedded silicon bridge chip.
A multi-chip module typically refers to an electronic assembly including multiple integrated circuits (ICs or chips). Some multi-chip modules may include multiple integrated circuits arranged two dimensionally across a substrate, such as, for example, a laminated substrate (e.g. PCB) or a ceramic substrate. Such technologies are commonly referred to in the industry as two-dimensional or 2D packages.
Building from two-dimensional technology, some multi-chip modules include a silicon interposer between and separating the multiple integrate circuits and the substrate. Such technologies are commonly referred to in the industry as two and a half dimensional or 2.5D packages. 2.5D packages are particularly advantageous for their tremendous increased capacity and performance.
Lastly, other multi-chip modules may include chip-stack packages which have multiple chips arranged three dimensionally, or stacked vertically. 3D chip-stack packages are particularly advantageous for their increased package density, smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through silicon vias. Such technologies are commonly referred to in the industry as three-dimensional or 3D packages.
USPTO Backgrounds
USPTO Backgrounds