For example, in semiconductor device manufacturing processes, a plasma etching process, which performs etching with a plasma using a resist as a mask, is frequently employed in order to form a predetermined pattern on a predetermined layer formed on a semiconductor wafer, which is an object of processing.
HARC (High Aspect Ratio Contact) etching of an aspect ratio of 20 or more has been demanded by recent progress in the microfabrication of semiconductor devices. Recently, high aspect ratio etching of an aspect ratio higher than 40 has been demanded as the next generation HARC.
In such HARC etching, an etching mask such as a photoresist is negatively charged, and electric charge is neutralized on the etched surface in the beginning of etching. When the aspect ratio becomes higher with the progress of etching, positive ions collect at the bottom of the hole, so that the etched surface becomes positively charged. Therefore, the positive ions are bent by repulsion in the hole, so that the etched shape is bent or distorted. Furthermore, shading damage may be caused by the bottom of the hole thus being positively charged. Furthermore, positive ions become less likely to reach the bottom of the hole, thus causing a decrease in the etch rate.
Therefore, Patent Document 1 or the like discloses a technique to neutralize the positively charged bottom of the hole by applying high frequency electric power for plasma generation in a pulsed manner and feeding as many secondary electrons as possible to the bottom of the hole.
USPTO Backgrounds
USPTO Backgrounds