VLIW (very long instruction word) processors are characterized by their ability to process multiple instructions in parallel using different functional units within the processor. Other processors, such as dual-path processors have a similar capability. A VLIW instruction comprises a number of sub-words or fields, each of which controls a functional unit within the processor. Fully parallel operation, in which all functional units are used at each time step, is rare. More commonly, many instructions contain “NOP” instructions in several of the sub-words or fields, indicating that the corresponding functional unit is not operated at that time step.
Power reduction in processors controlled by VLIWs or other multiple-instruction words is very important in handheld computing devices, such as PDAs, digital cameras, navigation devices and cellular telephone handsets that rely on battery power. Power reduction can be used to reduce the weight and/or increase the operating time of a device. Two techniques for power saving are (i) reducing memory accesses by reducing the size of the program of instructions (compression), and (ii) disabling hardware resources (memory and functional units) when they are not required.
VLIW compression schemes are used in many VLIW architectures (e.g., IA-64, StarCore, TI DSPs). The goal of these schemes is the elimination of all NOPs from the instruction stream. This reduces the memory requirements for the code, and it reduces the memory bandwidth required to fetch instructions.
In one method of power saving, special instructions are added to a processor to shut down the datapath elements under program control. In a further method, datapath elements are disabled based on an instruction pre-decode stage. The instruction words are examined and the datapath is dynamically disabled on an instruction-by-instruction basis. A disadvantage of these approaches is that they add to dataflow graph complexity.
In one method of compression, NOPs are eliminated from the code by rearranging the slices within VLIW words, so that NOP fields in sequential VLIWs line up (are at the same location in the VLIW word). This allows banks of memory to be powered off for periods of time, saving power. A disadvantage of this method is the complexity associated with rearranging the slices within VLIW words.
USPTO Backgrounds
USPTO Backgrounds