The invention relates to a computer system which includes a plurality of independently operating local processor systems that are combined into a plurality of processor subsystems, a central system bus decision logic unit, and a system bus which connects the processor subsystems with the central system bus decision logic unit, with at least two of the processor subsystems including at least two independently operating local processor systems which can be selectively connected with the system bus through a coupling element.
In the computer art, the working of parallel processes and the optimum utilization of time increasingly requires the combination of several processors into multi-processor systems. The processors included in these systems are usually adapted to special applications and are able to operate essentially independently of one another. However, it is absolutely necessary for these processors to communicate with one another within the system. Generally, this is accomplished by standardized parallel system bus architectures which operate in a time-sharing mode (e.g. VME [Versa Module Europe] bus). With an increasing number of processors, the required communication between these processors becomes more and more extensive. This raises the danger of the system bus becoming a bottleneck for data communications.
EP-A1-0,311,705 discloses a computer system which includes mutually independently operating processor systems each having two mutually independently operating local processor systems, a coupling element and a memory, a decision logic unit, several main memories and a system bus. The system bus connects the decision logic unit, the coupling elements and the main memories with one another.
The local processor systems of a processor system can be connected with the system bus by way of the coupling element.
EP-A2-0,318,270 discloses the networking of multi-processor systems as it is customary for larger computer systems.
The multi-processor system disclosed here includes several groups of processors. The processors of one group are connected with the memory control unit. The individual groups may have further associated memory and service units which are likewise connected with the memory control unit. All memory control units of the individual groups are again connected with a higher order control unit which coordinates the connections between individual groups.
USPTO Backgrounds
USPTO Backgrounds