1. Field of the Invention
The present invention relates to a semiconductor memory device which is suitable for a dynamic random access memory having a bit line structure of a hierarchic type, and more particularly to a semiconductor memory device whose chip size has been reduced.
2. Description of the Related Art
A memory capacity of a dynamic random access memory (DRAM) is increasing year after year, and a prototype of a DRAM having a capacity of 4 Gb has been manufactured and made public. Such an increase in memory capacity can be realized by reducing of an area of each memory cell and decreasing pitches of word lines and bit lines. Along with this, a demand is made to reduce the size of a sense amplifier.
In order to meet this demand, there has been proposed a DRAM having a bit line structure of a hierarchic type and a shared sub sense amplifier. FIG. 1 is a circuit diagram showing a conventional semiconductor memory device.
In the conventional semiconductor memory device, two main bit lines MBLN11 and MBLT11 are connected to a main sense amplifier MSA11. A sub sense amplifier SSA11-0 is connected between the main bit lines MBLT11 and MBLN11. A signal line WSL11 for a writing switch signal, a signal line RSL11 for a reading switch signal, a signal line PDL11 for a precharge balance signal and a middle potential signal line HVCL11 through which a middle potential between a high potential and a low potential is transmitted are connected to the sub sense amplifier SSA11-0. A precharge circuit PCC11 attached with the signal line PDL11 for the precharge balance signal and the middle potential signal line HVCL11 is provided in the sub sense amplifier SSA11-0.
Also, eight sub bit lines SBLT10, SBLT11, SBLT12, SBLT13, SBLN10, SBLN11, SBLN12 and SBLN13 are connected to the sub sense amplifier SSA11-0. The four sub bit lines SBLT10, SBLT11, SBLT12 and SBLT13A are intersected by a word line WL10. A memory cell connected to each of the sub bit lines and the word line WL10 is provided on each of these intersection points. Similarly, the four sub bit lines SBLN10, SBLN11, SBLN12 and SBLN13a are intersected by a word line WL11. A memory cell connected to each of the sub bit lines and the word line WL11 is provided on each of these intersection points. One MOS transistor is connected between each of these eight memory cells and the sub sense amplifier SSA11-0.
Signal lines TGL10 for a signal for a sub bit line separation signal are respectively connected to the gates of the respective MOS transistors connected to the sub bit line SBLT10 or SBLN10. Signal lines TGL11 for a sub bit line separation signal are respectively connected to the gates of the respective MOS transistors connected to the sub bit line SBLT11 or SBLN11. Signal lines TGL12 for a sub bit line separation signal are respectively connected to the gates of the respective MOS transistors connected to the sub bit line SBLT12 or SBLN12. Signal lines TGL13 for a sub bit line separation signal are respectively connected to the gates of the respective MOS transistors connected to the sub bit line SBLT13 or SBLN13.
The main sense amplifier MSA11 is shared by a plurality of sub sense amplifiers such as the sub sense amplifier SSA11-0. As a consequence, DRAM has a bit line structure of a hierarchic type. Thus, the sense amplifier is reduced in size as a whole.
In the conventional semiconductor memory device thus constituted, the sub sense amplifier is precharged by a precharge circuit provided in each of the sub sense amplifiers. For example, the sub sense amplifier SSA11-0 is precharged by the precharge circuit PCC11.
Furthermore, there has been proposed a semiconductor memory device in which noises have been reduced and stability in operation has been improved (Japanese Unexamined Patent Application Laid-Open No. Hei 4-274081). FIG. 2 is a block diagram showing a conventional semiconductor memory device disclosed in the Japanese Patent Application Laid-Open No. Hei 4-274081.
In the conventional semiconductor memory device disclosed in the Japanese Patent Application Laid-Open No. Hei 4-274081, two main bit lines MBLN21 and MBLT21 are connected to main sense amplifiers MSA21 and MSA22. Sub sense amplifiers SSA21, SSA22 and a precharge circuit PCC21 are connected between the main bit lines MBLT21 and MBLN21. A signal line PDL21 to which a precharge balance signal for controlling operation of the precharge circuit PCC21 is transmitted from the outside is connected to the precharge circuit PCC21. Furthermore, a middle potential signal line HVCL21 to which a potential between the high potential and the low potential is transmitted is connected to the precharge circuit PCC21. A pair of sub bit lines (not shown) are connected to the sub sense amplifiers SSA21 and SSA22. A plurality of word lines (not shown) intersect the pair of sub bit lines. Then, on an intersection point of each sub bit line and each word line, a memory cell (not shown) connected to the bit lines and the word line is provided.
In the conventional semiconductor memory device disclosed in the Japanese Patent Application Laid-Open No. Hei 4-274081, the main sense amplifiers MSA21 and MSA22 are precharged and the sub sense amplifiers SSA21 and SSA22 are also precharged with a change in the potential of the precharge balance.
However, in the conventional semiconductor memory device in which the precharge circuit PCC11 is provided in the sub sense amplifier SSA11-0, the sub sense amplifier is not sufficiently reduced in size.
Also, the conventional semiconductor memory device disclosed in the Japanese Patent Application Laid-Open No. Hei 4-274081, has attained its expected purpose, but it is not sufficiently applicable to a further fine structure in these days.
USPTO Backgrounds
USPTO Backgrounds