1. Field of the Invention
This invention relates generally to structures and methods for confining E-fields in high-density ferroelectric memory applications, so that unwanted dispersion of the E-field into regions surrounding the ferroelectric material is avoided.
2. Description of the Related Art
There is a major effort by semiconductor companies throughout the world to commercialize ferroelectric thin films in advanced dynamic random access memories (DRAMs) and ferroelectric random access memories (FeRAMs), respectively.
Ferroelectric thin film materials of interest for such FeRAM applications include PbZrTiO3 (PZT) and SrBi2Ta2O9 (SBT). While the majority of current efforts are directed to the commercial development of relatively large capacitors (e.g. 5 xcexcm2 area), the ultimate goal is to adapt ferroelectric random access memory technology for future generations of integrated circuit devices in which capacitor areas, cell sizes and voltages are scaled downward as the technology evolves.
In high-density memory arrays, storage of adequate charge will in some cases require 3-dimensional capacitors utilizing the sidewalls of the capacitor structure to increase capacitor area in a given xe2x80x9cfootprint.xe2x80x9d That is a proposed path for implementation of SBT in FeRAM device applications, because of its relatively low switched ferroelectric polarization (PSW) characteristic, typically less than 20 xcexcC/cm2. PZT thin films have higher PSW ( greater than 40 xcexcC/cm2), and for that reason planar capacitors based on PZT thin films may be extended to higher integration densities. Planar capacitors are attractive to avoid the complications of controlling composition, crystalline orientation and ferroelectric characteristics on capacitor sidewalls.
By way of example, device technology in the F=0.18 xcexcm regime is expected to target capacitors with 0.1 xcexcm2 projected area, which corresponds to a circular capacitor with diameter (d)=0.36 xcexcm. (Another shape would be a rectangular capacitor with dimensions 0.2xc3x970.5 xcexcm.) In such cases, wherein the lateral dimensions (such as d) begin to approach the thickness of the ferroelectric thin film layer (t), the E-field due to an applied voltage at the capacitor plate tends to be driven out of the high permittivity ferroelectric, into the low permittivity surroundings.
This phenomenon of E-field dispersion is described by Scott (Scott, James F., xe2x80x9cLayered perovskite thin films and memory devices,xe2x80x9d Thin film Ferroelectric Materials and Devices, R. Ramesh, Ed. Kluwer Academic Publishers, Boston, 1997, pp. 138). Scott refers to the circular capacitor aspect ratio d/t, to illustrate the effect on losses in switched charge, which would be the direct consequence of reduction of switching E-field within the ferroelectric. Scott states that for capacitors with d/t as low as 5, PSW may be decreased by about 20%. In the case of a 0.1 xcexcm2 capacitor, d/t≈3.6, so the effect is expected to be even larger.
In general the reduction of field in the high xcex5 ferroelectric layer has been solved for the static case, but we are not aware that any solution has been found for the dynamic case, involving a nonlinear high xcex5 layer such as in a ferroelectric or paraelectric layer, with time-varying E-fields.
This effect of losses in switched charge will tend to increase the voltage needed to switch the ferroelectric, and it will also project the applied E-fields into adjacent memory cells, with the potential result of undesired interference. Such effect may also distribute the E-fields non-uniformly within the ferroelectric layer, with deleterious effects.
It would therefore be a significant advance in the art and is accordingly an object of the present invention to provide a ferroelectric device architecture that will efficiently confine the E-field (at a given voltage characteristic) within the ferroelectric layer that is to be switched.
Other objects and advantages of the invention will be more fully apparent from the ensuing disclosure and appended claims.
The present invention relates generally to structures and methods for confining E-fields in high-density ferroelectric memory applications to minimize unwanted dispersion of the E-field into regions surrounding the ferroelectric material.
In one aspect, the invention relates to a method of fabricating a ferroelectric capacitor device structure, including forming a ferroelectric stack capacitor comprising a ferroelectric material capacitor element on a substrate containing buried transistor circuitry beneath an insulator layer having a via therein containing a conductive plug to the transistor circuitry, wherein E-fields are confined to the ferroelectric capacitor material element in said structure by a fabrication process step selected from the group consisting of:
(a) patterning the stack capacitor, and depositing a non-ferroelectric, high ∈ insulating layer over and on the sides of the stack capacitor;
(b) patterning the stack capacitor, depositing an insulating capping layer on the patterned stack capacitor to prevent electrical short-circuiting between top and bottom electrodes of the stack capacitor, and depositing a conducting layer over and on the sides of the stack capacitor;
(c) forming the stack capacitor without patterning the ferroelectric material so that deposited ferroelectric material comprises a region aligned with top and bottom electrodes of the stack capacitor defining the ferroelectric capacitor material element and ferroelectric material outside of said region, and rendering the ferroelectric material outside of said region non-ferroelectric in character, by at least one of the steps of:
(1) growing the ferroelectric material outside of said region on a different surface;
(2) chemically modifying the ferroelectric material outside of said region by in-diffusion of a sacrificial layer thereinto;
(3) ion implanting the ferroelectric material outside of said region with an ionic species rendering said region non-ferroelectric in character;
(4) damaging the crystal lattice of the ferroelectric material outside of said region by ion or electron bombardment thereof; and
(5) heat treating the ferroelectric to remove volatile constituents (i.e. Pb, or Bi). This may be accelerated in a reducing environment (i.e. H2, forming gas or ammonia).
(d) forming the ferroelectric stack capacitor with an aspect ratio, of effective lateral dimension d of the ferroelectric capacitor material element to thickness t of the ferroelectric capacitor material element, that is greater than 5, with d and t being measured in same dimensional units.
Another aspect of the invention relates to a method of fabricating a stack capacitor array on a substrate containing buried transistor circuitry beneath a insulator layer having vias therein containing conductive plugs to the transistor circuitry, said method comprising the steps of:
forming a conductive barrier layer on the substrate;
forming a stack capacitor structure on the conductive barrier layer, by the steps including:
depositing a bottom electrode layer on the conductive barrier layer;
depositing a ferroelectric material layer on the bottom electrode layer;
depositing a top electrode layer on the ferroelectric material layer; and
etching the multilayer structure comprising the bottom electrode layer, ferroelectric material layer and top electrode layer, to define a stack capacitor structure;
conformally depositing over the stack capacitor structure including top and sides thereof an E-field confinement layer;
depositing on the E-field confinement layer an interlayer dielectric; and
forming metallization contacts to the top electrode layer through the interlayer dielectric and E-field confinement layer.
The E-field confinement layer in such method may be either an insulative material, or alternatively a conductive material deposited over an interposed insulative capping layer to prevent short-circuiting between the respective electrodes.
A further aspect of the invention relates to a method of fabricating a stack capacitor array on a substrate containing buried transistor circuitry beneath a insulator layer having vias therein containing conductive plugs to the transistor circuitry, said method comprising the steps of:
forming a conductive barrier layer embedded in the insulator layer on the substrate;
forming a stack capacitor structure on the conductive barrier layer, by the steps including:
depositing a bottom electrode layer on the conductive barrier layer so that the bottom electrode layer is also embedded in the insulator layer on the substrate;
depositing a ferroelectric material layer on the bottom electrode layer; and
depositing a top electrode layer on the ferroelectric material layer;
depositing on the stack capacitor structure an interlayer dielectric; and
forming metallization contacts to the top electrode layer through the interlayer dielectric;
wherein the stack capacitor is formed without patterning the ferroelectric material layer so that the deposited ferroelectric material layer comprises a layer including (i) a region aligned with top and bottom electrodes of the stack capacitor defining a ferroelectric capacitor material element and (ii) material of said layer outside of said region, further comprising rendering the material outside of said region non-ferroelectric in character, by at least one of the steps of:
(1) growing the ferroelectric material outside of said region on a different surface;
(2) chemically modifying the ferroelectric material outside of said region by in-diffusion of a sacrificial layer thereinto;
(3) ion implanting the ferroelectric material outside of said region with an ionic species rendering said region non-ferroelectric in character;
(4) damaging the crystal lattice of the ferroelectric material outside of said region by ion or electron bombardment thereof; and
(5) heat treating the ferroelectric to remove volatile constituents (i.e. Pb, or Bi). This may be accelerated in a reducing environment (i.e. H2, forming gas or ammonia).
The invention relates in another aspect to a ferroelectric capacitor device structure, including a ferroelectric stack capacitor comprising a ferroelectric material capacitor element on a substrate containing buried transistor circuitry beneath an insulator layer having a via therein containing a conductive plug to the transistor circuitry, wherein E-fields are structurally confined to the ferroelectric capacitor material element.
A further aspect of the invention relates to a ferroelectric device structure including a stack capacitor array on a substrate containing buried transistor circuitry beneath a insulator layer having vias therein containing conductive plugs to the transistor circuitry, said structure comprising:
a conductive barrier layer on the substrate;
a stack capacitor structure on the conductive barrier layer, including:
a bottom electrode layer on the conductive barrier layer;
a ferroelectric material layer on the bottom electrode layer;
a top electrode layer on the ferroelectric material layer; and
a high ∈ material layer conformally coated on the top and sides of the stack capacitor structure;
an interlayer dielectric overlying the high C material layer; and
metallization contacts to the top electrode layer through the interlayer dielectric and high ∈ material layer.
Yet another aspect of the invention relates to a ferroelectric device structure including a stack capacitor array on a substrate containing buried transistor circuitry beneath a insulator layer having vias therein containing conductive plugs to the transistor circuitry, said device structure comprising:
a conductive barrier layer embedded in the insulator layer on the substrate;
a stack capacitor structure on the conductive barrier layer, including:
a bottom electrode layer on the conductive barrier layer so that the bottom electrode layer is also embedded in the insulator layer on the substrate;
a ferroelectric material layer on the bottom electrode layer;
a top electrode layer on the ferroelectric material layer;
depositing on the stack capacitor structure an interlayer dielectric; and
forming metallization contacts to the top electrode layer through the interlayer dielectric;
wherein the stack capacitor is formed without patterning the ferroelectric material layer so that the ferroelectric material layer comprises a continuous layer including (i) a region of the continuous layer that is aligned with the top and bottom electrodes of the stack capacitor to define a ferroelectric capacitor material element and (ii) a portion of the continuous layer outside of said region that is non-ferroelectric in character, and has at least one of the characteristics of:
(1) having been grown on a different surface than the region (i) of the continuous layer;
(2) having a sacrificial layer in-diffused therein;
(3) being implanted with an ionic species rendering said portion of the continuous layer non-ferroelectric in character;
(4) having a crystal lattice that has been damaged by ion or electron bombardment thereof; and
(5) heat treating the ferroelectric to remove volatile constituents (i.e. Pb, or Bi). This may be accelerated in a reducing environment (i.e. H2, forming gas or ammonia).
Other aspects, features and embodiments of the invention will be more fully apparent from the ensuing disclosure and appended claims.
USPTO Backgrounds
USPTO Backgrounds