1. Field of the Invention
The present invention relates to an address pattern generator for testing a memory, etc. which are accessed by two addresses (two-dimensions).
2. Prior Art
An arrangement of a conventional address pattern generator will be described with reference to FIG. 4.
The conventional address pattern generator comprises a control circuit 1, first and second maximum value registers 2 and 3, a column address generator 8, a row address generator 9 and a memory 10 which is to be tested. A column address signal 20 issued by the column address generator 8 is supplied to the memory 10 as a column address. A row address signal 21 issued by the row address generator 9 is supplied to the memory 10 as a row address. A memory cell in the memory 10 is accessed by supplying a column address and a row address to the memory 10.
The arrangement of the memory cells in the memory 10 will be described with reference to FIG. 5. In FIG. 5. the memory cells A0 to A15 are arranged as a matrix. In case of accessing a memory cell A10 of the memory 10, a column address signal 20 representing a column address "010" is supplied from the column address generator 8 to the memory 10 while a row address signal 21 representing a row address "010" is supplied from the row address generator 9 to the memory 10.
The arrangement of the conventional column address generator 8 will be described with reference to FIG. 6. The arrangement of the column address generator 8 is the same as that of the row address generator 9. The column address generator 8 comprises an operation register 8A, an adder 8B and an address register 8G. When a control circuit 1 supplies an add signal 19 to the adder 8B, the adder 8B adds the content of the address register 8G and the content of the operation register 8A. The result of addition is stored in the address register 8G and it is output from the address register 8G as the address signal 20. An address value 17 is the signal output from the first maximum value register 2 which stores therein the maximum value of the address register 8G.
The number of address bits of the memory cell to be tested is generally used as the maximum value. For example, in case of the memory having 64 capacity, 6 bits are used as the address bit wherein 3 bits are used for the row address and 3 bits are used for the column address. Since the address generator has a surplus number of bits compared with the capacity bit of the memory (address bit) to be tested, the number of bits to be used should be limited.
When the memory cells A0 to A15 in FIG. 5 are accessed sequentially, the column address "011" and the row address "011" are respectively stored in the first and second maximum value registers 2 and 3. The column address "000" is stored in the address register 8G of the column address generator 8 as the initial value thereof while the column address "001" is stored in the operation register 8A and thereafter the add signal 19 is supplied to the adder 8B so that the column addresses "000", "001", "010" and "011" are sequentially supplied from the address register 8G to the memory 10 as the column address signal 20. The row address "000" is stored in the address register 9G of the row address generator 9 as the initial value thereof while the column address "000" is stored in the operation register 9A so that the row address "000" is supplied fixedly from the row address register 9G to the memory 10 as the row address signal 21.
The memory cells A0, A1, A2 and A3 are sequentially accessed when the column and row address signals 20 and 21 are supplied to the memory 10. When the memory cells A4 to A15 are sequentially accessed after the accesses of the memory cells A0 to A3, it is necessary that the column address signal 20 should automatically represent the column address "000" and the row address signal 21 should automatically represent the row address "001". If the content of the first maximum value register 2 is supplied to the column address generator 8 and the content of the second maximum value register 3 is supplied to the row address generator 9, an add value 27, which is obtained by carrying out the logical OR between a value representing the content of the operation register 8A and the value to be obtained by inverting the content of the first maximum value register 2, is supplied to the adder 8B wherein the add value 27, the add signal 19 and the output of the address register 8G are added while the upper bits are masked.
If the result of addition in the adder 8B exceeds the content of the first maximum value register 2, a carry is generated to thereby issue a carry signal 22. The carry signal 22 is supplied to the adder 9B of the row address generator 9 whereby the output of the row address generator 9 is rendered to be +1. The masked upper bits can be removed by carrying out the logical AND between an address signal 26, which is the result of operation in the adder 8B, and a value representing the content of the first maximum value register 2. In this case, since the add value 27 of the address becomes "101", if the next add signal 19 is supplied to the adder 8B in case the content of the address register 8G is "011", there is produced "000" as the result of the operation as an address signal 26 and at the same time a carry is generated. As a result, the row address generator 9 carries out an addition in the adder 8B including the carry signal 22 whereby the row address signal 21 is rendered to be +1.
Accordingly, the column address signal 20 is output from the column address register 8 in the order of "000", "001", "010" and "011" and is returned again to "000". The row address signal 21 is increased by +1 starting at the initial-value "000" every time the column address signal 20 returns to "000" again so that the row address signal 21 is output in the order of "001", "010" and "011". With the operations set forth above, the memory cells A0 to A15 can be sequentially accessed when the the address signals 20 and 21 are supplied to the memory 10.
However, it is impossible to specify the test area of the memory by an arbitrary address value since the test area of the memory is specified by limiting the number of bits to be used in the address register 8G in case of generating the regular addresses in the circuits as shown in FIGS. 4 and 6.
USPTO Backgrounds
USPTO Backgrounds