Implantable neurostimulator devices are devices that generate and deliver electrical stimuli to body nerves and tissues for the therapy of various biological disorders, such as pacemakers to treat cardiac arrhythmia, defibrillators to treat cardiac fibrillation, cochlear stimulators to treat deafness, retinal stimulators to treat blindness, muscle stimulators to produce coordinated limb movement, spinal cord stimulators to treat chronic pain, cortical and deep brain stimulators to treat motor and psychological disorders, and other neural stimulators to treat urinary incontinence, sleep apnea, shoulder subluxation, etc. The description that follows will generally focus on the use of the invention within a Spinal Cord Stimulation (SCS) system, such as that disclosed in U.S. Pat. No. 6,516,227. However, the present invention may find applicability in any implantable neurostimulator.
As shown in FIGS. 1A and 1B, a SCS system typically includes an Implantable Pulse Generator (IPG) 100, which includes a biocompatible device case 30 formed of a conductive material such as titanium for example. The case 30 typically holds the circuitry and battery 26 necessary for the IPG to function, although IPGs can also be powered via external RF energy and without a battery. The IPG 100 includes one or more electrode arrays (two such arrays 102 and 104 are shown), each containing several electrodes 106. The electrodes 106 are carried on a flexible body 108, which also houses the individual electrode leads 112 and 114 coupled to each electrode. In the illustrated embodiment, there are eight electrodes on array 102, labeled E1-E8, and eight electrodes on array 104, labeled E9-E16, although the number of arrays and electrodes is application specific and therefore can vary. The arrays 102, 104 couple to the IPG 100 using lead connectors 38a and 38b, which are fixed in a non-conductive header material 36, which can comprise an epoxy for example.
As shown in FIG. 2, the IPG 100 typically includes an electronic substrate assembly 14 including a printed circuit board (PCB) 16, along with various electronic components 20, such as microprocessors, integrated circuits, and capacitors mounted to the PCB 16. Two coils (more generally, antennas) are generally present in the IPG 100: a telemetry coil 13 used to transmit/receive data to/from an external controller 12; and a charging coil 18 for charging or recharging the IPG's battery 26 using an external charger 50. The telemetry coil 13 is typically mounted within the header 36 of the IPG 100 as shown, and may be wrapped around a ferrite core 13′.
As just noted, an external controller 12, such as a hand-held programmer or a clinician's programmer, is used to wirelessly send data to and receive data from the IPG 100. For example, the external controller 12 can send programming data to the IPG 100 to dictate the therapy the IPG 100 will provide to the patient. Also, the external controller 12 can act as a receiver of data from the IPG 100, such as various data reporting on the IPG's status. The external controller 12, like the IPG 100, also contains a PCB 70 on which electronic components 72 are placed to control operation of the external controller 12. A user interface 74 similar to that used for a computer, cell phone, or other hand held electronic device, and including touchable buttons and a display for example, allows a patient or clinician to operate the external controller 12. The communication of data to and from the external controller 12 is enabled by a coil (antenna) 17.
The external charger 50, also typically a hand-held device, is used to wirelessly convey power to the IPG 100, which power can be used to recharge the IPG's battery 26. The transfer of power from the external charger 50 is enabled by a coil (antenna) 17′. The external charger 50 is depicted as having a similar construction to the external controller 12, but in reality they will differ in accordance with their functionalities as one skilled in the art will appreciate.
Wireless data telemetry and power transfer between the external devices 12 and 50 and the IPG 100 takes place via inductive coupling, and specifically magnetic inductive coupling. To implement such functionality, both the IPG 100 and the external devices 12 and 50 have coils which act together as a pair. In case of the external controller 12, the relevant pair of coils comprises coil 17 from the controller and coil 13 from the IPG 100. In case of the external charger 50, the relevant pair of coils comprises coil 17′ from the charger and coil 18 from the IPG 100. As is well known, inductive transmission of data or power can occur transcutaneously, i.e., through the patient's tissue 25, making it particularly useful in a medical implantable device system. During the transmission of data or power, the coils 17 and 13, or 17′ and 18, preferably lie in planes that are parallel, along collinear axes, and with the coils as close as possible to each other. Such an orientation between the coils 17 and 13 will generally improve the coupling between them, but deviation from ideal orientations can still result in suitably reliable data or power transfer.
U.S. Patent Application Publication 2008/0319497 (“the '497 application”), owned by the present assignee and which is incorporated herein by reference in its entirety, discloses an improved architecture 150 for an IPG 100, which is shown in FIGS. 3A-3C. Because of its pertinence to the present disclosure, some time is spent discussing pertinent aspects of the '497 application's architecture.
The improved IPG architecture 150 of FIG. 3A involves integration of various IPG functional circuit blocks on a single integrated circuit (IC) 200 via a bus 190 governed by a communication protocol, discussed further below. The centralized bus 190 is a parallel bus containing a plurality of multiplexed address and data lines operating in parallel. However, this is not strictly necessary, and instead bus 190 can comprise a serial bus as well. To communicate with the bus 190 and to adhere to the protocol, each circuit block includes bus interface circuitry 215 adherent with that protocol. Because each circuit block complies with the protocol, any given circuit block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus 190 can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG, a point discussed further below.
Each of the circuit blocks performs standard functions in an IPG. For example, telemetry block 62 couples to the IPG telemetry coil 13, and includes transceiver circuitry for communicating with the external controller 12 (FIG. 2). The charging/protection block 64 couples to the IPG charging coil 18, and contains circuitry for rectifying power received from the external charger 50 (FIG. 2), and for charging the power source (battery) 26 in a controlled fashion. Stimulation circuit block 175 is coupled to the electrodes E1-E16 and includes circuitry for setting the program (magnitude, and polarity) for the stimulation pulses appearing at those electrodes. Block 175 also includes the drivers for the electrodes, with a Digital-to-Analog Converter (DAC) 82 being responsive to the stimulation program to supply the specified electrodes currents. Notice that the electrodes E1-E16 are connected to off-chip decoupling capacitors C1-CN prior to connection to the corresponding electrodes 106 on the leads 102 and 104 (FIG. 1A); such decoupling capacitors C1-CN prevents direct DC current injection from the IPG into the patient, which is advisable for safety, but otherwise such decoupling capacitors don't effect stimulation performance. EPROM block 177 caches any relevant data in the system (such as log data), and additional memory 66 can also be provided off-chip via a serial interface block 167. Analog-to-Digital (A/D) block 74 digitizes various analog signals for interpretation by the IPG 100, such as the battery voltage Vbat or voltages appearing at the electrodes, and is coupled to an analog bus 192 containing such voltages. Interrupt controller block 173 receives various interrupts from other circuit blocks, which because of their immediate importance are received independent of the bus 190 and its communication protocol. Note that because it handles both analog and digital signals, IC 200 comprises a mixed mode chip.
Stimulation circuit block 175 is coupled to the electrodes E1-E16 and includes circuitry for setting the program (magnitude, and polarity) for the stimulation pulses appearing at those electrodes. Block 175 also includes the drivers for the electrodes, with a Digital-to-Analog Converter (DAC) 82 being responsive to the stimulation program to supply the specified electrodes currents. Notice that the electrodes E1-E16 are connected to off-chip decoupling capacitors C1-CN prior to connection to the corresponding electrodes 106 on the leads 102 and 104 (FIG. 1A); such decoupling capacitors C1-CN prevent direct DC current injection from the IPG into the patient, which is advisable for safety, but otherwise such decoupling capacitors don't significantly affect stimulation performance.
Internal controller 160 acts as the master controller for all other circuit blocks. Specifically, each of the other circuit blocks contains set-up and status registers (not shown). The set-up registers are written to by the controller 160 upon initialization to configure and enable each block. Each circuit block can then write pertinent data at its status register, which can in turn be read by the controller 160 as necessary. Aside from such control imposed by the master controller 160, the circuit blocks outside of the controller 160 can employ simple state machines to manage their operation, which state machines are enabled and modified via the set-up registers.
As can be seen in FIG. 3A, the IC 200 contains several external terminals 202 (e.g., pins, bond pads, solder bumps, etc.), such as those necessary to connect the power source 26, to connect the coils 18, 13, to connect the external memory 66, and to connect the stimulation electrodes. Other external terminals 202 are dedicated to the various signals that comprise the centralized bus 190 to allow this bus to communicate with other devices outside of the IC 200.
The various signals comprising the bus 190 can be seen in FIG. 3B, which also discloses the protocol for communications on the bus. As shown, the centralized bus 190 comprises a clock signal (CLK) for synchronization, time-multiplexed address and data signals (A/Dx); an address latch enable signal (ALE); an active-low write enable signal (*W/E), and an active-low read enable signal (*R/E). The frequency for the clock signal, CLK, can be in the range of 32 kHz to 1 MHz, which is generally slow for a computerized protocol, but is suitably fast for operation of the IPG, which typically provides stimulation pulses on the order of tens of microseconds to milliseconds. As shown, the protocol uses a fairly simple address-before-data scheme in which an address is followed by pertinent data for that address. To discern between address and data, the address latch enable signal (ALE) is active only upon the issuance of an address, which allows the address to be latched upon the falling edge of the clock. Whether the data corresponding to a particular address is to be written or read on the next falling clock edge depends on the assertion of the write and read enable signals (*W/E; *R/E).
The nature of this protocol means that all functional blocks coupled to the centralized bus 190 are designated an address, or more likely, a range of addresses. For example, the address for a data register holding the value for the compliance voltage (in A/D block 74) might be ADDR[3401], while the address for the magnitude and duration of stimulation to be provided by electrode E6 (in stimulation circuitry block 175) may be ADDR[7655] and ADDR[7656] respectively. To assist the various functional blocks in recognizing pertinent addresses, and to ensure each block's ability to function in accordance with the centralized bus 190's protocol, each block contains bus interface circuitry 215. As this bus interface circuitry was described in detail in the above-incorporated '497 application, such details are not repeated here.
As noted in the '497 application, when the circuit blocks are coupled via the bus 190 and communicate using the protocol, it becomes a relatively simple matter to make changes to any particular block to fix circuit errors, and/or to upgrade the IC 200 for use in next-generation IPGs. Additionally, because the bus 190 is provided outside of the IC 200, it is easy to modify or add functionality to the IPG 100 outside of the IC 200. For example, and as shown in FIG. 3C, more memory 300 (preferably, nonvolatile memory) can be added. Or, systemic control can be added outside of the IC 200, for example, via an external microcontroller 240. Should an external microcontroller 240 be used in conjunction with the IC 200, the '497 application discusses manners in which control is arbitrated between the microcontroller 204 and the internal controller 160 in the IC 200. Again, such details are not repeated here.
In another off-chip extension of the architecture noted in the '497 application, and as particularly pertinent to the present disclosure, another IC 200′ can be added which is similarly constructed to the first IC 200. This allows the IPG 100 in which the IC 200 and 200′ are placed to provide 32 stimulation electrodes, i.e., 16 each from both of the ICs. In other words, the capacity of the IPG can be increased by “daisy chaining” a plurality of stimulation ICs together. In such an embodiment, the internal controller 160 in one of the ICs 200 or 200′ can be inactivated so only one controller 160 acts as the master controller for the system.
Practical concerns arising from the use of electrode drivers in two different ICs 200 are addressed in this disclosure.
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