1. Field of the Invention
The present invention relates to a charge pump (CP) circuit, and more particularly, to a CP circuit having a balanced charge current and discharge current.
2. Description of the Related Art
A Phase Lock Loop (PLL) is a feedback system for comparing an output phase and an input phase. The PLL is applicable in frequency generators, wireless receivers, and communication devices to control the frequency of operation. FIG. 1 is a schematic block diagram of a typical PLL 10. As shown in FIG. 1, a phase detector 12 generates an UP signal UP and a DOWN signal DN according to a phase difference (or a frequency difference) between a reference clock signal FREF and a feedback clock signal FBK. When the UP signal UP is enabled, an UP current IUP flows out from a CP circuit 14 to a loop filter 16. When the DOWN signal DN is enabled, a DOWN current IDN is drawn from the loop filter 16 by the CP circuit 14. The loop filter 16 performs charge and discharge actions according to the UP current IUP and the DOWN current IDN to generate a loop filter voltage VC.
As shown in FIG. 1, a voltage controlled oscillator (VCO) 18 generates a feedback clock signal FBK according to the loop filter voltage VC. In the foregoing operation mode, through the generation of the UP signal UP and the DOWN signal DN, a phase difference (or frequency difference) between the reference clock signal FREF and the feedback clock signal FBK gradually decreases.
The performance of the CP circuit 14 has a direct relation with the effect of the PLL 10. When the UP current IUP does not exactly match the DOWN current IDN, a continuous ripple may be generated when the PLL 10 is locked. Furthermore, due to deterioration of track characteristics, jitter may occur at an output end of the PLL 10.
FIG. 2 is a schematic circuit diagram of a conventional CP circuit 14. As shown in FIG. 2, the conventional CP circuit 14 includes an UP current source IU, a DOWN current source ID, p-Mental-Oxide-Semiconductor (PMOS) transistors MPS1 and MPS2, n-Mental-Oxide-Semiconductor (NMOS) transistors MNS1 and MNS2 and an operational amplifier 22. The PMOS transistors MPS1 and MPS2 are alternately turned on according to a signal UP and a complementary signal UPB applied on a gate, and the NMOS transistors MNS1 and MNS2 are alternately turned on according to a signal DN and a complementary signal DNB applied on the gate. The operational amplifier 22 is connected between a node N3 and a node N4 through a unity gain buffer. That is to say, the gain of the operational amplifier 22 is 1, and an output end voltage of operational amplifier 22 is equal to an input end voltage thereof constantly.
In operation, an input end voltage VC of the operational amplifier 22 changes according to the signal UP and the signal DN. For example, when the signal UP=1, the signal UPB=0, the signal DN=0, and the signal DNB=1, the PMOS transistor MPS1 and the NMOS transistor MNS2 are turned on, while the PMOS transistor MPS2 and the NMOS transistor MNS1 are turned off, so that the voltage VC increases to a voltage on a node N1. When the signal UP=0, the signal UPB=1, the signal DN=1, the signal DNB=0, the PMOS transistor MPS2 and the NMOS transistor MNS1 are turned on, while the PMOS transistor MPS1 and the NMOS transistor MNS2 are turned off, so that the voltage VC decreases to a voltage of a node N2. When the voltage VC changes, head voltages of the UP current source IU and the DOWN current source ID of the channel length modulation are affected, so that the current values of the UP current source IU and the DOWN current source ID are not exactly equal to each other. This situation becomes more severe in a sub-micron process and under a low supply voltage.
FIG. 3A is a schematic circuit diagram of another conventional CP circuit 14′. As shown in FIG. 3, the conventional CP circuit 14′ includes a first current mirror circuit 32, PMOS transistors MPS1 to MPS3, NMOS transistors MNS1 to MNS3, NMOS transistors MN1 and MN2, and an operational amplifier 22. The first current mirror circuit 32 includes PMOS transistors MP1, MP2 and MP3.
In operation, the operational amplifier 32 forces a voltage of an output end OUT1 of the first current mirror circuit 32 to be equal to a voltage of an output end OUT2, and force a drain voltage of the NMOS transistor MN1 to be equal to a drain voltage of the NMOS transistor MN2. Therefore, a current flowing through the PMOS transistor MP3 of the first current mirror circuit 32 matches a current flowing through the PMOS transistor MP2, and a current flowing through the NMOS transistor MN1 matches a current flowing through the NMOS transistor MN2. As the current flowing through the PMOS transistor MP3 is equal to the current flowing through the NMOS transistor MN2, the current flowing through the PMOS transistor MP2 is substantially the same as the current flowing through the NMOS transistor MN2.
However, the conventional structures have the following disadvantages in operation. First, as the CP circuit 14′ has a large loop gain value, a capacitor C having a large capacitance is required to improve loop stability. Second, the value of the current flowing through the PMOS transistor MP2 and the value of the current flowing through the NMOS transistor MN2 depend on the voltage of an output end of the operational amplifier 22, so the current values of the PMOS transistor MP2 and NMOS transistor MN2 are not absolute values. Furthermore, the CP circuit 14′ requires a start circuit to solve the bias problem occurring when the operational amplifier 22 is on.
FIG. 3B is a schematic circuit diagram of another conventional CP circuit. As shown in FIG. 3B, the conventional CP circuit 36 includes a main CP, a voltage to current converter VI, and a floating current source IBIAS. The conventional CP circuit 36 monitors uplink and downlink currents and rectifies any non-matching states, for example, non-matching of operating points. The conventional CP circuit 36 detects a voltage difference between Vsense and Vdump by using the voltage-current converter VI and rectifies any non-matching states. The problems of the conventional CP circuit 36 lie in that the minimal VDD voltage is 2Vt+3Vdsat, so the conventional CP circuit 36 cannot be applied on a system with a low-voltage design.
Accordingly, it is necessary to provide an improved CP circuit to solve the problems above.
USPTO Backgrounds
USPTO Backgrounds