Split-gate type memory cell arrays are known. For example, U.S. Pat. No. 5,029,130, which is incorporated herein by reference for all purposes, discloses a split gate memory cell, and its formation, which includes forming source and drain regions in the substrate with a channel region there between, a floating gate over one portion of the channel region, and the control gate over the other portion of the channel region, where the control gate extends up and over the floating gate.
It is also known to form logic devices on the same wafer as the split-gate memory cell array. See for example U.S. Pat. No. 9,276,005, which is incorporated herein by reference for all purposes. However, as device critical dimensions shrink, it becomes more difficult the shrink the height of the split gate memory cell to match the height of the logic devices, especially for those memory cell configurations where the control gate extends up and over the floating gate. There is a further need to reduce the height of the memory cells to better match the low profile of logic devices, and to accommodate multiple metal lines for the memory array and logic devices with tight design rules.
USPTO Backgrounds
USPTO Backgrounds