Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
ICs have been electrically connected to their packages using wire bonds. Automatic bonding machines are available to quickly and reliably stitch very fine metal wire from bonding pads on the IC to bonding pads on the package base. The bonding pads are usually located on or near the perimeter of the IC to avoid crossing one wire bond with another. While this approach has worked very well for many ICs, including CPLDs, alternative packaging techniques have been developed.
Another type of packing technique is commonly referred to as “flip-chip” bonding. One advantage of flip-chip packaging techniques over wire-bond packaging techniques is that the solder bumps on the IC are not limited to its perimeter. Small solder bumps are formed on the top of the IC in lieu of wire bonding pads around the perimeter of the chip.
Corresponding bump lands are on the top surface of the base of a package. The IC is flipped over and aligned so that the solder bumps match the bump lands. The assembly is then heated to re-flow the solder bumps, which electrically and mechanically attach the flip-chip IC to the base of the package.
The base of the package typically has metal traces that electrically connect the solder targets on the top of the base with contacts on the bottom of the base. In some applications, the traces essentially “spread out” the spacing between the solder targets on the top to another set of solder bumps or pins on the bottom of the package base. This is done to accommodate the generally higher critical dimension (i.e. minimum spacing) of the printed wiring board that the packaged IC is assembled on. In other words, the processes and materials used to fabricate the package base reliably produce more closely spaced solder targets and metal traces than the processes and materials used to fabricate the printed wiring board.
FIG. 1A is a plan view of a prior art flip chip packaged IC 100 without a lid. The lid is omitted in order to show the underlying features of the packaged IC. An IC 102 is mounted on a package substrate 104 with a solder ball array (see FIG. 1B, ref. num. 134) on the IC 102 that mechanically and electrically connects to a corresponding solder land array (see FIG. 1B, ref. num. 136) on the package substrate 104. The package substrate 104 also has solder pads (solder lands) 106, 108 for mounting chip capacitors 110 or other components on the surface of the package substrate 104
Exposed test points (test pads) 112, 114, 116, 118 on the surface of the package substrate 104 provide electrical access to corresponding terminals of the IC 102 through traces 120, 122 for electrical testing of the packaged IC 100. The package substrate 104 has multiple patterned metal layers, and the traces associated with exposed test points 114, 118 are in a lower metal layer, and are not shown. Solder mask 126, 128 is optionally included on spans of the exposed traces 120, 122 to avoid inadvertent shorting to the traces.
FIG. 1B is a cross section of the flip-chip packaged IC 100 of FIG. 1A taken along section line A-A. A metal lid (not shown) is typically attached to the perimeter of the package substrate 104 using any of a variety of techniques (e.g., gluing). The lid protects the surface-mount components and other exposed features from physical damage or inadvertent electrical shorting. A lid can also provide thermal sinking or spreading, and provide additional mechanical strength to the final packaged IC.
In order to reveal the test points on the surface of the package substrate, the metal lid is partially or entirely removed. For example, a glue joint is heated to soften the glue, allowing removal of the lid, or the lid is milled to a thin section that allows peeling of the remaining lid material off, or a window is milled into the lid, allowing electrical test probe access to the exposed test points on the surface of the substrate.
An electronic test probe 130 makes contact to the exposed test point 112, and is electrically coupled through the trace 120 to a solder ball 132 in a solder ball array 134 of the IC 102 to electrically test the IC.
The solder ball array 134 of the IC 102 is mechanically and electrically connected to a corresponding solder land array 136 on the package substrate 104. Patterned metal layers and conductive vias (not shown) in the package substrate 104 electrically connect terminals (i.e., solder balls) of the IC 104 to a second solder ball array 138 on the opposite side of the package substrate 104. The solder ball array 138 of the package substrate is typically connected to a corresponding pattern on a printed wiring board (not shown).
An alternative packaging technique uses a plastic-based molding compound (also commonly called encapsulant) to provide mechanical and environmental protection to packaged ICs. Molded packages are commonly used on relatively small, low-power ICs; however, they are less common on large ICs, such as FPGAs, because the molding compound does not conduct heat as well as a metal lid and does not have as great a thermal capacity, thus providing reduced thermal sinking and thermal spreading compared to a conventional metal lid. Heat sinking and heat spreading are particularly desirable for FPGA and other physically large ICs having high power consumption, such as microprocessors and digital signal processors (“DSPs”).
Unfortunately, a molded lid is not removable like a metal lid for contacting the test points on the surface of the package substrate. While it may be possible to selectively mill away the molding compound overlying the test points, it presents practical difficulties in controlling the depth and position of the milling apparatus so as to not damage the surface conductive traces, including surface traces not associated with the test points, and surface components on the package substrate.
What is needed is a means of providing access to test points of a packaged integrated circuit. Such a means should easily allow for such access without damaging the integrated circuit.
USPTO Backgrounds
USPTO Backgrounds