It is known that in a large memory array, some memory cells may be defective. It is, of course, possible to discard an entire memory array if one or more cells in the array are defective. On the other hand, it is known in the art that if the number of memory cells which are defective in a given array are few in number, it may be possible to replace these memory cells with usable memory cells on the chip which are not defective.
FIG. 1 shows a memory array having redundant memory cells according to one configuration as used in the prior art. According to this configuration, the array contains main memory blocks, in this instance labeled blocks 1-4. Associated with the main memory block is a row address circuitry and a column address circuitry which can also support defective rows and columns.
One of the blocks may contain a row having two or more defective memory cells, thus causing the entire row to be defective. Further, the memory array may include two or more defective memory cells in a column, causing the entire column to be indicated as defective. According to one prior art technique, the address of the respective defective row or defective column is programmed into the address circuitry of the memory array to prevent access the defective row or column. This programming can take place by blowing fuses in the address circuitry for the defective memory line, thus prohibiting the line being addressed by either the row address circuitry or the column address circuitry.
In one prior art technique, it may be desired to replace the defective memory line with an extra line positioned in a different location on the chip, usually called a redundant line. In such an instance, the address of the redundant line may be stored in the respective row and column address circuitry as a substitute for the defective line. When an attempt is made to address a defective line, the address for a redundant line is substituted by the address circuitry so that data is stored in or retrieved from the redundant line rather than the defective line.
The prior art technique provides the advantage that the entire memory chip does not need to be discarded if there are only a few defective lines in the chip. However, a significant disadvantage is that longer access time is required to access the redundant line than is required for accessing a line in the main memory. This is because of the time required to determine that an attempt has been made to address a defective line and to substitute therefor the address of the redundant line and then to address this redundant line.
There are a number of schemes for providing redundant memory cells to replace defective memory cells in a large array. See, for example, any one of the following U.S. Pat. Nos. 5,574,688; 5,572,470; 5,566,114; 5,659,509; 5,602,786; and 5,559,743. These above patents describe various schemes for replacing defective memory cells with redundant memory cells and then providing addressing to the redundant memory cells.
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