1. Field of the Invention
The present invention relates to a semiconductor device having floating gate electrodes isolated from one another by element isolation films and a method of fabricating the same.
2. Description of the Related Art
Fabrication of semiconductor devices such as flash memories has recently employed a process in which a gate electrode layer or floating gate electrode layer is formed prior to the forming of element isolation regions of the shallow trench isolation (STI) structure. For example, JP-A-2002-110822 discloses one of such processes in which a gate insulating film is formed on an upper surface of the semiconductor substrate. A gate electrode layer or floating gate electrode layer is formed on the gate insulating film. Subsequently, a trench is formed in the surface of the substrate in a predetermined direction, whereby a gate insulating film and gate electrode layer of each transistor are formed. According to the process disclosed in the above-referenced publication, a tunnel insulating film is formed on the silicon substrate by a thermal oxidation method, and a polycrystalline silicon layer doped with impurities is formed as a floating gate electrode layer. Furthermore, a silicon nitride film is formed to serve as a stopper film in a planarizing process by the chemical mechanical polishing (CMP). Additionally, a silicon oxide film is formed by the low pressure chemical vapor deposition (LPCVD) method to serve as a mask material in an etching process by the reactive ion etching (RIE) method. Thereafter, the silicon oxide film, silicon nitride film, polycrystalline silicon layer and tunnel insulating film are sequentially etched by the RIE method and the silicon substrate is further etched, so that the trench is formed.
Subsequently, a silicon oxide film is deposited in the trench by the plasma CVD method after several steps, whereupon the element isolation trench is completely buried. The silicon oxide film is planarized on the upper surface of the silicon nitride film by the CMP method. Thereafter, the silicon nitride film to be formed into the stopper film is removed. As a result, a floating gate electrode, gate insulating film and element isolation insulating film are processed and formed.
When the fabricating method disclosed in JP-A-2002-110822 is applied, each film with a predetermined film thickness is deposited on the upper surface of the substrate, and a trench is formed in the upper surface of the substrate in a predetermined direction. The element isolation insulating film is buried in the trench. The polycrystalline silicon layer doped with high electrically conductive impurities is removed in a direction intersecting a predetermined direction. The polycrystalline silicon layers adjacent to each other are separated from each other, so that a floating gate electrode is two-dimensionally formed on the upper surface of the substrate. Thus, the floating gate electrode can be formed on the upper surface of the substrate with high area efficiency.
When the above-described method is applied to fabrication of semiconductor devices, the floating gate electrode is two-dimensionally arranged on the upper surface of the substrate in the predetermined direction and the direction intersecting the predetermined direction by dividing the polycrystalline silicon layer on the upper surface of the substrate. However, the upper surface of the element isolation film needs to be located higher than a forming face of the upper surface of the gate insulating film. Accordingly, even when treated to be removed, the polycrystalline silicon layer formed between the element isolation insulating films adjacent to each other remains in the forming direction of the trench along the sidewall of the element isolation insulating film. As a result, the floating gate electrodes adjacent to each other in the predetermined direction are rendered electrically conductive, resulting in failure. In particular, the width of a floating gate electrode layer formed between the element isolation insulating films has been reduced with recent reduction in the circuit design rules. Consequently, an aspect ratio has been increased such that the conditions for dividing the floating gate electrode layer have been more and more severe.
USPTO Backgrounds
USPTO Backgrounds