1. Field of the Invention
The present invention relates to a printed (wiring) substrate or board and, in particular, to a multilayered wiring substrate or board having a plurality of multilayered wiring layers. The invention involves a technique of improving the difference in propagation delay time (hereinafter also referred to simply as xe2x80x9cdelay timexe2x80x9d) between signals propagating along a plurality of wirings that form the respective wiring layers.
2. Description of the Background Art
FIG. 15 shows appearances of a conventional memory module 200P (i.e., its top plan view and side view). In FIG. 15, the illustration of detailed wiring is omitted.
Referring to FIG. 15, in the memory module 200P a plurality of (nine in the figure) DRAMs (Dynamic Random Access Memory) 51 are mounted on a conventional multilayered wiring substrate 100P. The substrate 100P is provided with a plurality of external terminals 60, through which sending and/or receiving of signals and supply of power are performed between the DRAMs 51 and an external system or external circuit (not shown).
FIG. 16 is a schematic longitudinal section of the multilayered wiring substrate 100P taken along the line Axe2x80x94A of FIG. 15. The substrate 100P has six multilayered wiring layers, and wirings that form their respective wiring layers are isolated by an insulating material 2, such as glass epoxy material. Specifically, signal wiring groups 31 and 32, each forming a signal wiring layer, are disposed on both surfaces (main surfaces) of the multilayered wiring substrate 100P, respectively. Signal wiring groups 33 and 34, each forming a signal wiring layer, and a ground wiring (layer) 35, and a power supply wiring (layer) 36 are disposed inside the multilayered wiring substrate 100P. The signal wiring groups 31 to 34 are used for transferring, for example, an address signal relative to the operation of the DRAM 51. The ground wiring 35 and power supply wiring 36 are used for supplying a ground potential and a power supply potential to a ground terminal and a power supply terminal of the DRAM 51, respectively.
FIG. 17 is a schematic top plan view of a signal wiring layer formed from a signal wiring group 31, as an example of wiring layers. As shown in FIG. 17, the signal wiring group 31 is composed of n strip-like signal wirings 31a to 31n which transfer, for example, an address signal of the DRAM 51. The signal wirings 31a to 31n are disposed in this order, so as to be parallel with one another.
In general, the signal wirings that form the signal wiring groups 31 and 32 on the surface of the multilayered wiring substrate 100P, are composed of a copper foil having a thickness of about 20 xcexcm, and a copper plating film that has a thickness of about 20 microns and is disposed on the copper foil surface. The signal wirings that form the signal wiring groups 33 and 34 in the multilayered wiring substrate 100P, are composed of a copper foil having a thickness of about 40 xcexcm. The signal wirings that form the signal wiring groups 31 to 34 have a width of about 100 to 200 xcexcm, and the wiring interval of a wiring pattern is about 100 to 200 xcexcm. On the other hand, the ground wiring 35 and power supply wiring 36 are composed of a plane copper foil having a thickness of about 40 xcexcm. The length of the signal wirings that form the signal wiring groups 31 to 34 is about the same as the lateral width of the memory module 200P (i.e., the dimension in right-to-left direction in FIG. 15), and it is usually about ten and several centimeters.
FIG. 18 is a schematic longitudinal section of the multilayered wiring substrate 100P or memory module 200P taken along the line Bxe2x80x94B of FIG. 15. As shown in FIG. 18, there is formed a through hole 40 extending through in the direction of thickness of the multilayered wiring substrate 100P. The through hole 40 has a diameter of about 250 xcexcm, and is bored by means such as a drill. A conductive layer 41 having a thickness of about 20 xcexcm is formed on the inner wall or side wall 40S of the through hole 40. The conductive layer 41 is formed at the same time that the signal wiring groups 31 and 32 on the surface of the multilayered wiring substrate 100P are formed by copper plating. Referring again to FIG. 17, through holes 40ab to 40mn are interposed among the signal wirings 31a to 31n. 
The through hole 40 and conductive layer 41 establish a connection between predetermined layers selected from the wiring layers formed from the signal wiring groups 31 to 34, the ground wiring layer 35, and the power supply wiring layer 36. For instance, as shown in FIG. 18, the wiring layers made by the signal wiring groups 33 and 34, respectively, are connected to the wiring layer made by the signal wiring group 31. The pad of one signal wiring in the signal wiring group 31 is connected via a solder 52 to an external lead 51a of the DRAM 51. Thereby, the DRAM 51 is connected to the wiring layers made by the signal wiring groups 33 and 34, or to each signal wiring.
The timing that the DRAM 51 receives an address signal SA will be described by referring to FIG. 19, which illustrates timing charts of a clock signal CL and address signal SA. The DRAM 51 receives the address signal SA at a rise (or fall) t0 of the clock signal CL as a reference time. In order that the address signal SA is surely received and the internal circuit of the DRAM 51 is operated stably, a set up time T1 and hold time T2, each having a predetermined period of time, are provided before and after time t0. For achieving high speed and stable operation of the DRAM 51, it is preferable to provide a greater operation margin to the set up time T1 and to the hold time T2.
When a plurality of address signals SA are transferred on different wirings, it is desirable that all the address signals SA propagate simultaneously on the multilayered wiring substrate 100P, and that the DRAM 51 receives them at the same time. By establishing this transfer condition, the above-mentioned margin can be set at a large value, and a high operational stability of the DRAM 51 is obtainable even at high speed operation.
However, the conventional memory module 200P has the following problems in signal propagation. Description will now be made by taking, as an example, a wiring layer made by the above-mentioned signal wiring group 31. The same is true for other wiring layers.
It is well known that when a plurality of wirings are disposed in close proximity, these wirings are capacitively coupled via the capacitance (or capacitor) component formed between the wirings. This condition will be described by referring to FIG. 20, which is a schematic longitudinal section of the multilayered wiring substrate 100P taken along the line CPxe2x80x94CP of FIG. 17. As shown in FIG. 20, all the signal wirings 31a to 31n can be schematically illustrated as being in a capacitive coupling in series via a capacitance (or capacitor) CSW between two adjacent signal wirings.
Likewise, when the through holes 40ab to 40mn are interposed among the signal wirings 31a to 31n, as shown in FIG. 17, all the signal wirings 31a to 31n and all the through holes 40ab to 40mn (specifically, all the conductive layers 41ab to 41mn) can be illustrated as shown in FIG. 21, which is a schematic longitudinal section taken along the line DPxe2x80x94DP of FIG. 17. That is, all the signal wirings 31a to 31n and all the conductive layers 41ab to 41mn are capacitively coupled in series via a capacitance (or capacitor) CST between one signal wiring and the conductive layer of one through hole.
Referring again to FIG. 17, one signal wiring and one through hole are disposed on both sides of the signal wirings 31b to 31m except for the outermost signal wirings 31a and 31n. Whereas one signal wiring and one through hole are disposed only on one side of the outermost signal wirings 31a and 31n. Specifically, as shown in FIGS. 20 and 21, two capacitance CSW or two capacitance CST are coupled to the signal wirings 31b to 31m, whereas only one capacitance CSW or capacitance CST is coupled to the outermost signal wirings 31a and 31n. 
A propagation delay time per unit of length of wiring tpd is expressed by the following Equation (1):
tpd={square root over ((Lxc2x7C))}xe2x80x83xe2x80x83(1) 
where L and C represent inductance and capacitance per unit of length of wiring, respectively.
Since the capacitance C contains the capacitance CST or CSW as described above, it can be seen from Equation (1) that a delay time tpd1 of the signal wiring 31a or 31n is smaller than a delay time tpd2 of any of other signal wirings 31b to 31m. Further, in view of the fact that Equation (1) is a relational expression of per unit of length of wiring, it can be seen that these delay time tpd1, tpd2, and a difference therebetween xcex94 tpd depend on the length of wiring, and their values increase as the length of wiring increases.
Referring to timing charts of FIG. 22, it can be seen that since the delay time tpd1 is shorter than the delay time tpd2, address signals SAa and SAn that propagate along the signal wirings 31a and 31n propagate faster than address signals SAb to SAm that propagate along the signal wirings 31b to 31m, by the amount of time xcex94t (corresponding to the value obtained by multiplying a delay time difference xcex94tpd by the length of a signal wiring). For obtaining a stable operation of the DRAM 51, it is necessary to set the operating timing of the DRAM 51 by taking into consideration a difference xcex94t in propagation delay time among the address signals SAa to SAn. That is, a hold time T3 to the address signal SAa and SAn is required to be shorter than a hold time T2 to the address signals SAb to SAm, by the amount of time xcex94t. This time setting will narrow each margin to the set up time and hold time, thus lowering the stability of the DRAM 51 at high speed operation.
According to a first aspect of the invention, a multilayered wiring substrate comprising: a plurality of multilayered wiring layers, at least one of the multilayered wiring layers containing a signal wiring group made by a plurality of signal wirings disposed in parallel with one another; and dummy wirings disposed outside said signal group in parallel to the signal wirings, at least one of the dummy wirings being disposed at each side of the signal wiring group.
According to a second aspect, the multilayered wiring substrate of the first aspect further comprises: through holes formed in a stacking direction of the wiring layers and disposed in each clearance between the signal wirings; a dummy through hole extending in the stacking direction, disposed adjacent to the dummy wiring on the side on which the signal wiring group is present; and conductive layers disposed inside the through holes and the dummy through hole, respectively.
According to a third aspect, the multilayered wiring substrate of the second aspect is characterized in that the conductive layer in the dummy through hole is electrically connected to the conductive layer in any one of the through holes.
According to a fourth aspect, the multilayered wiring substrate of the second aspect is characterized in that the conductive layer in the dummy through hole is electrically connected to the dummy wiring.
According to a fifth aspect, the multilayered wiring substrate of the first aspect further comprises at least one resistance having approximately the same impedance as a characteristic impedance of the dummy wiring, and being electrically connected to an end or central part of the dummy wiring.
According to a sixth aspect, the multilayered wiring substrate of the first aspect further comprises at least one terminal for connecting a terminating resistance connected electrically to an end or central part of the dummy wiring.
In the first aspect, the line capacitance of the outermost signal wiring of the signal wiring group can be made equal to that of other signal wirings. Therefore, since the propagation velocity of signals can be made identical, the propagation delay time difference of the signals can be considerably reduced or eliminated. It is therefore able to operate a DRAM stably and reliably even at high speed operation, by taking, for example, such a construction that the multilayered wiring substrate is applied to a memory module and the access signal inputted to the DRAM is transferred by the respective signal wirings.
In the second aspect, the effect resulting from the first aspect can be further improved by the presence of the conductive layer in the dummy through hole.
In the third aspect, electrical influences, such as the field distribution of the conductive layer in the dummy through hole, can be made equal to that of the conductive layer in the through hole to which the conductive layer of the dummy through hole is electrically connected. Thereby, the electrical influence between the dummy through hole and through hole can be made equal to that of the signal wiring between other through holes. This more ensures the effect of the first aspect.
In the fourth aspect, the conductive layer of the dummy through hole is not directly connected to the conductive layer of the through hole, unlike the multilayered wiring substrate of the third aspect. Therefore, when the conductive layer of the through hole is electrically connected to the signal wiring, the conductive layer of the dummy through hole does not serve as load of a signal that propagates along the signal wiring. As a result, the effect of the first aspect is obtained reliably while suppressing an increase in delay of the signal and in its waveform distortion.
In the fifth aspect, the dummy wiring is brought into an impedance matching by the resistance. When signal wirings are used in their impedance matching conditions, the electrical connecting condition of the dummy wiring can be made equal to that of the signal wirings. This more ensures the effect of the first aspect.
In the sixth aspect, since the terminating resistance connected electrically to a terminal for terminating resistance is disposed outside the multilayered wiring substrate, it is easy to set or change the resistance value of the terminating resistance. Hereat, in the above-mentioned memory module, a further reduction in power consumption is attainable, as compared to the case with the multilayered wiring substrate of the fifth aspect.
It is an object of the present invention to provide a multilayered wiring substrate capable of considerably reduce or eliminate the difference in propagation delay time between signals.
USPTO Backgrounds
USPTO Backgrounds