One embodiment of the present invention relates to a memory cell with a gated fuse element. More specifically, one embodiment of the present invention relates to high voltage switch circuitry used to program or set the state of a gated fuse element used with a one-time programmable CMOS memory cell in a memory device.
There are two main types of memory devices used in the field of data storage. The first type is volatile memory that has the information stored in a particular memory device, where the information is lost the instant power is removed. The second type is a non-volatile memory device in which the information is preserved even with the power removed. Of the second type, some designs provide for multiple programming while other designs provide for one-time programming. Typically, the manufacturing techniques used to form such non-volatile memories are quite different from standard logic processes, thereby dramatically increasing the complexity and chip size of such memories.
One-time programmable (alternatively referred to as “OTP”) memory cells and devices have numerous applications, specifically long-term applications. For example, OTP memory devices may be used in post package programming to store security codes, keys or identifiers. These codes, keys or identifiers cannot be electrically altered or decoded without destroying the circuitry. Further, such OTP memory devices may be used to make a device unique for a specific application. Alternatively, such memory devices may be used as memory elements in programmable logic and read only memory devices.
Known OTP memory devices use storage elements combined with poly fuses. One disadvantage of poly fuses is that the resistance ratio is fairly close together, having only about one order of magnitude difference in value. In other words, the resistance of the poly fuses before they are blown and the resistance after they are blown is fairly close. Therefore, sensing the difference between a blown and un-blown poly fuse is difficult. Yet another disadvantage of conventional poly fuses is the instability of their programmed state resistance. Specifically, the resistance of programmed poly fuses tends to decrease over time. In the worst case, the programmed poly fuses may actually switch from the programmed state to the unprogrammed state resulting in circuit failure.
Thick oxide gated transistors or fuses (i.e., fuses fabricated according to 0.35 μm, 0.28 μm or other thick process technologies) have been used in place of poly fuse memory devices. U.S. Pat. No. 6,044,012, the complete subject matter of which is incorporated herein by reference discloses a technique for rupturing the gate oxide transistor, where the oxide is about 40 to 70 Å thick. It is contemplated that the voltage required to rupture this thick oxide is substantially high and requires using a charge pump circuit. Furthermore, it is believed that the final programmed resistance is in the high kilo ohms range.
One alternative to using thick oxide gated fuses is to use thin-gated oxide transistors or fuses. Commonly assigned application Ser. No. 09/739,752, the complete subject matter of which is incorporated herein by reference, discloses the physical current used to rupture, breakdown or blow a gate-ox fuse, where the oxide is about 2.5 nm thick or less (alternatively referred to as “thin oxide transistor or fuse” or “thin gate-ox transistor or fuse”). Such thin gate-ox transistors or fuses integrate both NMOS and PMOS transistors on a silicon substrate. The NMOS transistor consists of a N-type doped polysilicon gate, a channel conduction region, and source/drain regions formed by diffusion of N-type dopant in the silicon substrate. The channel region separates the source from the drain in the lateral direction, whereas a layer of dielectric material that prevents electrical current flow separates the polysilicon gate from the channel. Similarly, the PMOS transistor architecture is the same as the NMOS transistor provided previously but using a P-type dopant.
The dielectric material separating the polysilicon gate from the channel region usually consists of thermally grown oxide material, silicon dioxide (SiO2) for example, where the oxide is about 2.5 nm thick or less. Here the thin oxide leaks very little current, through a mechanism called Fowler-Nordheim tunneling, under voltage stress. When this thin gate-ox transistor or fuse is stressed beyond a critical electrical field (applied voltage divided by the thickness of the oxide) the oxide ruptures, destroying (alternatively referred to as “blowing”) the transistor or fuse. If the fuse is connected or coupled to a storage element as part of a memory cell as disclosed in commonly assigned application Ser. No. 10/025,132 filed Dec. 18, 2001, titled “Memory Cell with Fuse Element”, now U.S. Pat. No. 6,525,955 issued Feb. 25, 2003, the complete subject matter of which is incorporated herein by reference, blowing the transistor or fuse sets the state or programs the storage element and thus the memory cell.
Generally a high voltage is used to blow one of the fuses to set the state or program the memory cell. It is possible to utilize high voltage devices or a charge pump using a small amount of current to supply the high voltage required to blow the fuse and set the state of the memory cell. However, such a high voltage might affect or damage parts of the memory cells in the memory devices. It is therefore advantageous to set the state of the memory cell in the memory device by switching in a high voltage without using such high voltage devices. It is further advantageous to protect specific parts of the memory cell, including parts of the gated fuse or transistor, from the high voltage yet still use such high voltage to blow the fuse and set the state of the memory cell.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
USPTO Backgrounds
USPTO Backgrounds