1. Technical Field
Embodiments of the present disclosure may generally relate to a refresh time detection circuit and a semiconductor device including the same, and more particularly to a technology for testing refresh characteristics according to a stress temperature condition.
2. Related Art
Generally, test methods may be classified into a product test and a proving method. The product test may detect defective or failed parts in a manufacturing procedure including a wafer process, an assembly process, etc. The product test removes (or screens) the detected defective or failed parts, resulting in selection of only normal products. In addition, the product test may confirm whether functions or performances of the DRAMs are identical to the predetermined design characteristics.
Therefore, the product test is applied to a large amount of products in a manufacturing process, and needs to be carried out with high productivity (or high throughput). The proving test must be very carefully carried out in a research and development (R&D) process to increase a high degree of completion as well as to reduce a development period.
If defective or failed parts are discovered in the manufacturing process through the above-mentioned tests or if a difference or inconsistency between the design and the function is detected through the above-mentioned tests, the analysis or failure detection method is used to investigate why the defective or failed parts were discovered. Specifically, a method for investigating the correct position of the defective or failed parts generated in DRAMs is of importance.
Generally, as a representative example of the functional tests, a semiconductor chip is first packaged and a burn-in test is then applied to the semiconductor chip. In order to discover defective or failed parts of DRAMs at an early stage, a voltage and a peripheral temperature to be applied to all DRAMs during the burn-in test must have a higher condition (or a higher stress) than the actual usage condition.
As a result, the defective or failed cells discovered by the above-mentioned tests are replaced with redundant cells to normally operate the semiconductor device. In addition, the operational condition arbitrarily established by experimental data is applied to a plurality of pass cells (available cells) through the above-mentioned tests, such that DRAMs can operate.
USPTO Backgrounds
USPTO Backgrounds