As the density of semiconductor devices continues to increase, the need for smaller interconnections also increases. Historically, the semiconductor industry has used a subtractive etching process to pattern metal interconnect layers of the semiconductor. This metal processing technique, however, has limitations including poor step coverage, non-planarity, shorts and other fabrication problems. To address these problems, a dual damascene technique has been developed. This process, as explained in "Dual Damascene: A ULSI Wiring Technology", Kaanta et al., 1991 VMIC Conference, 144-150 (Jun. 11-12, 1991) and incorporated herein by reference, involves the deposition of a metal into contact vias and conductor trenches which are patterned in the semiconductor. The semiconductor is then subjected to a known CMP (chemical-mechanical polish) process to both planarize the semiconductor and to remove excess metal from all but the patterned areas.
The metal layer can be fabricated using known CVD (chemical vapor deposition) or PVD (physical vapor deposition) techniques. Filling the patterned structures formed during the dual damascene technique, however, has proved difficult. This difficulty is enhanced as the aspect ratio (depth to width) of the patterns increase. As such, the use of high pressure to achieve improved fill in sub-micron conductor processing for ULSI integrated circuits has received considerable attention recently. One of the problems encountered is that high temperatures must be combined with high pressure to achieve conditions where sufficient metal flow will take place to fill the narrow troughs in the damascene process.
During the metal deposition process, an aluminum alloy which may contain such elements as copper and silicon, is deposited on the integrated circuit wafer. Aluminum has been typically used due to its low resistance and good adhesion to SiO.sub.2 and Si. Silicon is usually added as an alloying element to alleviate junction spiking in Al contacts to Si. Further, electromigration and hillocks (spike-like formations) can be reduced by adding Cu, Ti, Pd or Si to aluminum to form alloys. These alloying elements precipitate at the grain boundaries. Thus, the grain boundaries are "plugged" and vacancy migration is inhibited.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alloy which can be used to fill high aspect ration structures in an integrated circuit without requiring high temperatures or pressures. Specifically, an alloy and alloy system is needed which will enable force fill to be achieved at lower temperatures and/or lower pressures than can be obtained with the standard Al-0.5% Cu alloy which is used by much of the industry.
USPTO Backgrounds
USPTO Backgrounds