1. Field of Invention
The present invention generally relates to the memory device, and more particularly to the word line driver circuit of the memory device.
2. Description of Prior Art
The memory device has a plurality of memory cells. When there are a plurality of data being to be stored (or read), the memory device must receive the word line selected signal of each of the data, so as to store the plurality of the data in the corresponding memory cells (or read the plurality of the data from the corresponding memory cells) according to the word line selected signals. Accordingly, the word line driver circuit is adapted in the memory device to generate the word line selected signals.
Referring to U.S. Pat. No. 6,388,472 B1 disclosed by Kang, Kang provided a word line driver circuit to generate the voltage of the decoder signal on the selected word line when the global word line is selected. On the other hands, the selected word line is pulled down to the ground when the global word line is not selected.
Referring to FIG. 1, FIG. 1 is a circuit diagram showing one sector 10 of the word line driver circuit provided by Kang.
When the sector 10 of the word line driver circuit is selected (i.e. the global line signal GWL is low) in the reading or programming procedure, the voltage of the word line signal WL0 is equal to that of the decoder signal VXPRE0 approximately. When the sector 10 of the word line driver circuit is unselected (i.e. the global line signal GWL is high) in the reading or programming procedure, the voltage of the word line signal WL0 is equal to that of the power supply VEEX approximately. In general, the power supply VEEX is ground terminal, and thus the voltage of the word line signal WL0 is pulled down the ground when the sector 10 of the word line driver circuit is unselected.
It is noted that, the inversed global line signal GWLb serves as a reset signal to control the row driver 12˜15. In the memory device, there are many sectors of the word line decoder inside, and the inversed global line signal GWLb is coupled to each sector of the word line decoder. Since there are many sectors inside, the loading for the inversed global line signal GWLb may increase. Thus in order to drive the NMOS transistors of all sectors inside, the driving capability of the inversed global line signal GWLb must be strong. However the power consumption increases when increasing the driving capability of the inversed global line signal GWLb. Although laying a wires to provide the inversed global line signal GWLb to all sectors does not make the die area efficiency poor in the 0.25 or 0.16 micron meter semiconductor process, laying a wires to provide the inversed global line signal GWLb to all sectors will make the die area efficiency poor the 90 nano-meter semiconductor process.
Referring to U.S. Pub. No. 2006/0077717 A1 disclosed by Park et al., Park et al. provided a word line driver circuit to generate the voltage. Please see FIG. 2, FIG. 2 is a circuit diagram showing one sector 100 of the word line driver circuit provided by Park et al. The sector 100 of the word line driver circuit includes a word line decoder 109 and a plurality of row drivers DRV0˜DRVi.
When the sector 100 of the word line driver circuit is selected (i.e. the global line signal GWL_1 and the sector selection signal SS are high) in the reading or programming procedure, the power supplies Vpx and Vpgate are high and the power supply Vexen is low. Now the node ND10 is low and the word line signal WL<k> is controlled by the decoder signals PWL<k> and nPWL<k>, wherein the nPWL<k> is the inversion of the decoder signal PWL<k>, and k is an integer from 1 to i. While sector 100 of the word line driver circuit is unselected (i.e. the global line signal GWL_1 and the sector selection signal SS are low) in the reading or programming procedure, the power supplies Vpx and Vexen are high and the power supply Vpgate is low. Now the node ND10 is high and the word line signal WL<k> is pulled down to the ground Vex.
It is noted that, the global line signal GWL_1 serves as a reset signal to control the row driver DRV0˜DRVi, and the power supply Vpx is used to control the NMOS transistors of the row driver DRV0˜DRVi, so as to pull down the word line signal WL<k>. As stated above, in the memory device, there are many sectors of the word line decoder inside. The power supply Vpx is coupled to the gates of the NMOS transistors of all sectors. Since there are many sectors inside, the loading for the power supply Vpx may increase. In order to drive the NMOS transistors of all sectors inside, the driving capability of the power supply Vpx must be strong. Thus the power efficiency is low. Furthermore, the problem of laying a long wire in 90 nano-meter process will occur as stated above, so the die area efficiency is still poor.
Referring to U.S. Pat. No. 6,930,923 B2 disclosed by Chen et al., Chen et al. provided a word line driver circuit to generate the voltage. Please see FIG. 3, FIG. 3 is a circuit diagram showing one sector 72a of the word line driver circuit provided by Chen et al. The sector 72a of the word line driver circuit includes a word line decoder 82a and a plurality of row drivers 83a˜83c. 
When the sector 72a is unselected in the reading or programming procedure, the output of the NAND gate 84 is high, and the transistors 86b, 86d and 86e turn on. Now the voltage of node A is high, the voltage of the node B is low, and the reset signal (Vrst)i is high, wherein i is an integer from 1 to 7. Thus the voltage of the word line signal WLi is pulled down to the ground (i.e. the power supply Vin′ is low with zero voltage).
As stated above, in the memory device, there are many sectors of the word line decoder inside. The reset signal (Vrst)i is coupled to the gates of the NMOS transistors of all sectors. Since there are many sectors inside, the loading for the reset signal (Vrst)i i may increase. In order to drive the NMOS transistors of all sectors inside, the driving capability of the reset signal (Vrst)i i must be strong. Thus the power efficiency is low. Furthermore, the problem of laying a long wire in 90 nano-meter process will occur as stated above, so the die area efficiency is still poor.
USPTO Backgrounds
USPTO Backgrounds