1. Technical Field
Embodiments of the invention relate to methods of manufacturing semiconductor devices.
2. Related Art
In recent years, a technique has been proposed which reduces the thickness of a semiconductor wafer to reduce energy loss or improve the radiation performance in a power device, such as an IGBT (Insulated Gate Bipolar Transistor). However, for example, when the thickness of the semiconductor wafer with a diameter of 6 inches is reduced to about 80 μm, the semiconductor wafer can be broken or cracked. In order to solve the problems, a handling technique has been proposed which adjusts the deposition conditions of a metal thin film formed on the surface of the semiconductor wafer or is used in a semiconductor wafer manufacturing facility.
To increase the diameter of the semiconductor wafer to, for example, 8 inches or further reduce the thickness of the semiconductor wafer, the following techniques have been proposed: a TAIKO (registered trademark) technique in which the outer circumferential end of the rear surface of the semiconductor wafer remains as a reinforcing portion (rib portion) and the thickness of a central portion is reduced; and a WSS (Wafer Support System) technique which reinforces an integrated circuit or a MEMS (Micro Electro Mechanical Systems) with other members in order to reduce the thickness thereof.
A method of manufacturing a semiconductor device using the TAIKO technique will be described (hereinafter, referred to as “Conventional example 1”). FIG. 7 is a flowchart illustrating a method of manufacturing a semiconductor device according to the related art. FIGS. 8 to 11 are diagrams sequentially illustrating the method of manufacturing the semiconductor device according to the related art. First, a front surface structure 2 is formed on the front surface of a semiconductor wafer 1 (Step S101 and FIG. 8). In this case, marks (alignment marks) 3 for aligning the position of the semiconductor wafer 1 in the horizontal direction with the position of a photomask are formed on the front surface of the semiconductor wafer 1.
Then, a resist (hereinafter, referred to as a “front surface protective resist”) 111 which protects the front surface structure 2 is applied onto the front surface of the semiconductor wafer 1 (Step S102 and FIG. 9). Then, the outer circumferential end of the rear surface of the semiconductor wafer 1 remains as a reinforcing portion (rib portion) 102 and only a central portion of the semiconductor wafer 1 is grounded to be thinned. In this way, a wafer (hereinafter, referred to as a “rib wafer”) 101 in which a concave portion is provided in the rear surface of the semiconductor wafer 1 is manufactured (Step S103 and FIG. 9). Then, a resist (hereinafter, referred to as a “rear surface resist”) 113 is applied onto the rear surface of the rib wafer 101 (Step S104 and FIG. 10).
Then, a circuit pattern is formed in the rear surface resist 113. In the patterning process, first, the position of a camera 22 which is provided below a stage 21 of an exposure apparatus is aligned with the position of a photomask 24 which is provided above the stage 21. Then, the rib wafer 101 is mounted on the stage 21 of the exposure apparatus, with the front surface down (FIG. 11).
Then, the alignment mark 3 formed on the front surface of the rib wafer 101 is recognized by the camera 22 from the lower side of the stage 21 and the positions of the camera 22 and the rib wafer 101 are aligned with each other. In this way, the positions of the rib wafer 101 and the photomask 24 are accurately aligned with each other. Openings 23 are provided in the stage 21 at positions corresponding to the alignment marks 3 which are formed on the front surface of the rib wafer 101. Therefore, the camera 22 observes the rib wafer 101 through the opening 23 of the stage 21.
Then, exposure and development are performed to transfer the mask pattern of the photomask 24 to the rear surface resist 113 (Step S105 and FIG. 11). Openings 25 corresponding to the circuit pattern of a rear surface structure of the rib wafer 101 are formed in the photomask 24. Then, the rear surface resist 113 is baked and the patterning process ends.
Then, ion implantation and thermal diffusion are performed using the rear surface resist 113 as a mask to form the rear surface structure (not illustrated) on the rear surface of the rib wafer 101 (Step S106). Then, the rear surface resist 113 is removed. Then, the rib wafer 101 is diced into chips and a dicing tape peels off. In this way, a semiconductor device is completed.
Next, a method of manufacturing a semiconductor device using the WSS technique will be described (hereinafter, referred to as “Conventional example 2”). FIGS. 12 to 14 are diagrams sequentially illustrating another example of the method of manufacturing the semiconductor device according to the related art. First, Step S101 is performed, similarly to Conventional example 1 (see FIGS. 7 and 8). Then, a supporting substrate 143 is attached to the front surface of a semiconductor wafer 1 by, for example, an ultraviolet (UV)-curable adhesive 141 (FIG. 12). A black layer 142 which is made of a material absorbing laser light is coated on a surface of the supporting substrate 143 which is bonded by the adhesive 141 in order to facilitate the peeling of the supporting substrate from the semiconductor wafer 1.
Then, the entire rear surface of the semiconductor wafer 1 is ground to reduce the thickness of the semiconductor wafer 1 (FIG. 12). Then, a resist (hereinafter, referred to as a rear surface resist) 144 is applied onto the rear surface of the semiconductor wafer 1 (FIG. 13). Then, a circuit pattern is formed in the rear surface resist 144 (FIG. 14). In the patterning process, first, the position of an infrared camera 152 which is provided above a stage 151 of an exposure apparatus is aligned with the position of a photomask 153 which is provided between the stage 151 and the infrared camera 152. Then, the semiconductor wafer 1 is mounted on the stage 151 of the exposure apparatus, with the front surface down.
Then, alignment mark 3 which is formed on the front surface of the semiconductor wafer 1 is recognized by the infrared camera 152 through the semiconductor wafer 1 from the upper side of the photomask 153 and the positions of the infrared camera 152 and the semiconductor wafer 1 are aligned with each other. In this way, the positions of the infrared camera 152 and the semiconductor wafer 1 are aligned with each other and the positions of the semiconductor wafer 1 and the photomask 153 are accurately aligned with each other.
Openings 154 which correspond to the circuit pattern of a rear surface structure of the semiconductor wafer 1 are formed in the photomask 153. In addition, openings 155 are formed in the photomask 153 at positions corresponding to the alignment marks 3 which are formed on the front surface of the semiconductor wafer 1. Therefore, the infrared camera 152 emits laser light to the semiconductor wafer 1 through the opening 155 of the photomask 153 and observes the semiconductor wafer 1.
Then, exposure and development are performed to transfer the mask pattern of the photomask 153 to the rear surface resist 144 (FIG. 14). Then, the rear surface resist 144 is baked and the patterning process ends. Then, similarly to Conventional example 1, ion implantation and thermal diffusion are performed using the rear surface resist 144 as a mask to form the rear surface structure (not illustrated) on the rear surface of the semiconductor wafer 1. Then, the rear surface resist 144 is removed.
Then, for example, a dicing tape is attached to the rear surface of the semiconductor wafer 1. Then, laser light is emitted from the front surface of the semiconductor wafer 1 to sublimate the adhesive 141 and the supporting substrate 143 peels off from the semiconductor wafer 1. Then, the semiconductor wafer 1 is diced into chips and the dicing tape peels off. In this way, a semiconductor device is completed.
As such, as a method of attaching the semiconductor wafer to, for example, the dicing tape after the supporting substrate is attached to the semiconductor wafer, the following method has been proposed: the surface of the semiconductor wafer is attached to a plate-shaped object supporting substrate, with an adhesive tape having an adhesive layer whose adhesion is reduced by an external factor interposed therebetween; the rear surface of the semiconductor wafer is ground in this state; a dicing tape is attached to the ground rear surface of the semiconductor wafer; the outer circumference of the dicing tape is supported by a dicing frame; an external factor is applied to the adhesive layer to reduce the adhesion of the adhesive layer, thereby detaching the plate-shaped object supporting substrate from the adhesive tape without damaging the semiconductor wafer or the semiconductor chip. See, for example, Pamphlet of PCT International Publication No. WO03/049164 (also referred to herein as “Patent Literature 1”).
However, in Conventional example 1, since the concave portion is formed in the rear surface of the semiconductor wafer 1 by the rib portion 102, it is difficult to uniformly apply the rear surface resist 113. Therefore, as illustrated in FIG. 10, the thickness of a portion of the rear surface resist 113 in the vicinity of the rib portion 102 increases. In a thick portion 131 of the rear surface resist 113, the rear surface resist 113 cannot be completely dissolved by development. Therefore, as illustrated in FIG. 11, it is difficult to transfer the circuit pattern corresponding to the openings 25 of the photomask 24 to the rear surface resist 113.
Furthermore, in Conventional example 1, as illustrated in FIG. 11, a gap 132 between the rib wafer 101 and the photomask 24 needs to be more than the height of the rib portion 102. As the gap 132 increases, resolution is reduced or the accuracy of alignment is reduced. In addition, when the TAIKO technique described above is used to increase the diameter of the semiconductor wafer 1, there is a concern that a step portion between the rib portion 102 and the central portion of the rib wafer 101 will be broken or cracked.
FIG. 15 is a diagram sequentially illustrating another example of the method of manufacturing the semiconductor device according to the related art. FIG. 15 illustrates a case in which a supporting substrate is bonded to a semiconductor wafer 1 by the WSS technique (see Conventional example 2) and exposure and development are performed by a general exposure apparatus (see Conventional example 1) including a camera 22 which is provided below a stage 21. In the WSS technique according to Conventional example 2, for example, an opaque adhesive manufactured by T-MAT (registered trademark) and a supporting substrate which is made of a glass material or silicon (Si) and includes a black layer 142 manufactured by 3M Company (registered trademark) are used as an adhesive 141 and a supporting substrate 143, respectively. The adhesive 141 and the supporting substrate 143 are not transparent.
Therefore, as illustrated in FIG. 15, when the general exposure apparatus is used, the camera 22 which is provided below the stage 21 can observe only the surface 134 of the supporting substrate 143 through an opening 23 of the stage 21. That is, it is difficult to recognize an alignment mark 3 which is formed on the front surface of the semiconductor wafer 1 using the camera 22. Therefore, when the WSS technique is used, a special exposure apparatus using the infrared camera 152 is used as in Conventional example 2 (see FIG. 14). However, since the exposure apparatus is expensive, costs increase. In addition, the alignment mark 3 made of a material absorbing laser light needs to be formed on the front surface of the semiconductor wafer 1.
In addition, the openings 155 through which laser (infrared) light emitted from the infrared camera 152 passes need to be formed in the photomask 153. Therefore, when a positive resist is used as the rear surface resist 144, unnecessary patterning 133 is performed for the rear surface resist 144 due to the openings 155. In addition, since the infrared camera 152 recognizes the alignment mark 3 through an opaque member (semiconductor wafer 1), it is difficult to capture the clear image of the alignment mark 3 and the accuracy of alignment is reduced. Thus, as described above, there exists in the related art a need for an improved method of manufacturing a semiconductor device.
USPTO Backgrounds
USPTO Backgrounds