Information is typically conveyed over conventional networks in packets. FIG. 1 illustrates a conventional server 100 connected to a network 102 over a link 104 implementing the Ethernet protocol. In FIG. 1, information is transferred in packets 106 comprised of an Ethernet header 108 and an Ethernet payload 110. The Ethernet payload 110 is effectively comprised of an Internet Protocol (IP) header 112 and an IP payload 114. IP is a general protocol that works over a range of different physical networks, and allows different networks to communicate, but it is unreliable and unordered because delivery of messages is not guaranteed, or messages may be delivered out of order. The IP payload 114 is effectively comprised of a Transmission Control Protocol (TCP) header 116 and a TCP payload 118. TCP runs on top of IP and provides reliability and ordering to the IP payload. The net result is a packet 106 comprised of an Ethernet header 108, an IP header 112, and a TCP header 116, and a TCP payload 118. The TCP/IP network protocol allows the transmission of data by breaking the transmitted data into segments, transmitting the segments in a series of packets 106, and then reassembling the segments at the receiving end.
In FIG. 1, the packets 106 are received in a NIC 120 within the server 100. The NIC 120 is typically connected to a host 138 over an internal host bus 126 such as a Peripheral Component Interconnect (PCI) bus. NICs 120 typically implement the Ethernet protocol over which TCP/IP protocol is often run. The host 138 includes a host processor 122 and host memory 124, among other things. A conventional NIC 120 may include a controller 128, local memory 130 including receive buffers 132 for storing packet data, a Direct Memory Access (DMA) engine 134 to transfer data between the local memory 130 and host memory 124, and a Media Access Control (MAC) unit 136 to implement the link level protocol of the network (e.g. the Ethernet protocol). When a packet 106 is received from the network 102, it is received by the MAC unit 136 and stored in receive buffers 132 in the local memory 130. The controller 128, which may include a processor capable of executing firmware or state machine logic, then initiates DMA transfers to send the packet 106 from local memory 130 to host memory 124, and notifies the host processor 122 when the packet has been stored in host memory 124.
Generally, hardware in the NIC 120 implements the low level protocol (e.g. the Ethernet protocol) and software executed by the host processor 122 implements the higher level protocols (e.g. IP and TCP). Every time a packet is received in host memory 124 and “delivered” to the host through a notification to the host processor 122, the host software must be invoked to handle the processing of TCP and IP. Although this networking model works well in many applications, there are some applications (e.g. using storage protocols such as Internet Small Computer System Interconnect (iSCSI) over TCP/IP to displace Fibre Channel (FC) in high end storage networking) where the performance of traditional networking is insufficient due to excessive computational overhead incurred by the host processor.
Conventional hardware solutions such as expanding the NIC to handle the processing of TCP and IP by including a TCP Offload Engine (TOE) are expensive and also require rewriting the host networking software. Therefore, there is a need to reduce the computational overhead incurred by the host processor during packet processing, while minimizing the impact to the host network stack.
USPTO Backgrounds
USPTO Backgrounds