This invention relates to integrated circuits, and more particularly, to circuitry such as memory circuitry that may incorporate asymmetric transistors and stacked transistors.
There is a trend with each successive generation of integrated circuit technology to scale transistors to smaller sizes, smaller threshold voltages, and smaller power supply voltages. Made properly, these adjustments allow improved performance and lowered costs. Care must be taken, however, to avoid issues such as excessive power consumption.
One aspect of lowering power consumption on an integrated circuit relates to transistor leakage currents. Leakage currents are undesired currents that flow between the terminals of a transistor during normal operation. An ideal transistor would exhibit no leakage. In the real world, however, leakage currents are unavoidable and must be minimized as best possible. If leakage currents are too high, a circuit may exhibit unacceptably large static power consumption. Particularly in circuits with large numbers of transistors, such as modern integrated circuits that include memory cells, leakage current minimization can be highly beneficial. Although leakage currents can be reduced by limiting power supply voltages and using less leaky transistors such as transistors with increased threshold voltages and reduced gate widths, these approaches tend to slow circuit speed and may not be acceptable for many designs.
It would therefore be desirable to be able to provide transistor structures that help improve the tradeoffs that exist between transistor performance and leakage current reduction.
USPTO Backgrounds
USPTO Backgrounds