1. Field of the Invention
The present invention relates generally to the field of integrated circuits, and specifically, to fuse circuits used to increase the production yield of flash memory integrated circuits.
2. Background Information
Particle defects due to fabrication environments can cause flash memory integrated circuits, especially those with high density memory arrays, to fail. As a result, a yield loss in production test is realized, thereby causing the final satisfactory product to cost substantially more in order to cover the cost of the faulty parts. To help increase production yield, a technique, commonly known as redundancy repair (row, column, or block), is used to avoid use of the failed memory portion in favor of a corresponding redundant memory portion included on the integrated circuit just for such purposes.
Redundancy circuits typically store the addresses of the failed memory portion by using fuse circuits which compare the incoming addresses versus the stored redundancy addresses for a match. If a match is found, the redundancy array is enabled and the main array is disabled. An enable fuse is typically included to enable or disable the redundancy addresses.
In addition to the storage of redundancy addresses, the fuse circuit can be used to store the settings for other circuits, such as voltage references, precision oscillators, etc. At production test, these circuits can be trimmed by the fuse circuit in order to increase the production yield. In one embodiment, fuse circuits are referred to as trim circuits and flash memory fuses are referred to as flash memory trimcells.
Some conventional implementations use a resistor fuse as a programmable element to store the failed addresses. The fuse is blown by applying a high current through the fuse by a test enabling circuit. However, such a fuse is one-time programmable only. Since the current required to blow the fuse is usually high, the transfer switch has to be large, and requires a correspondingly large chip area.
Other implementations use erasable programmable read-only memory ("EPROM") technology. However, as implemented, an EPROM fuse is also one-time programmable. Furthermore, an EPROM requires complicated shielding over the fuse after programming in order to retain the programming charge.
In yet other implementations, an electrically erasable programmable read only memory ("EEPROM") is used in an inverter mode (as commonly known), i.e., the cell in the read mode acts as a current sink for some loading elements such as a PMOS, NMOS, or a resistor. The device gate is typically held at 2 V and its source at ground, with its drain coupled to the load. The voltage at the loading element is the output of the memory cell.
Conventional methods of generating trim bits are by placing the EEPROM cells on an area away from the array. Reading and programming is done in parallel. However, the problem with this method is that the EEPROM cells will not properly match the cells in the array. Also, the parallel read and programming modes require extensive circuits when large trimbit quantities are used.
In prior art U.S. Pat. No. 4,617,651 by W. Ip and G. Perlegos and U.S. Pat. No. 4,538,245 by G. Smarandolu and G. Perlegos, the fuse element is a one time programmable fuse as opposed to the many times programmable flash memory fuse of the present invention. The flash memory fuse enables the redundancy and trimable circuits to be programmable many times and does not require high currents to drive the fuse. Furthermore, in '651 and '245 patents, the programming of the fuse elements is done in parallel in contrast to the serial loading and programming of the present invention. The serial loading saves a considerable amount of space, especially when large trimbit quantities are used.
In prior art U.S. Pat. No. 5,148,395 by David Sowards, EEPROM fuses are stand alone and outside of the array. Additionally, large support circuits are required to operate it.
In prior art U.S. Pat. No. 5,642,316 by Hieu Van Tran and Trevor Blyth, the EEPROM fuses are programmed by the same column drivers as the main array. Therefore, a column redundancy scheme is not allowed. Also, the EEPROM fuses first have to be programmed in order to use the trimbits for characterization of the performance of the integrated circuit. This is not the case in the present invention, since the trimbits can be serially loaded in a latch where they are stored and used for characterization of the integrated circuit. Also, programming, erasing, and reading of the flash memory fuses is done by means of separate drivers. Therefore, a column redundancy scheme is allowed. The flash memory fuses are embedded in the array and thus match the flash memory cells in the array.
USPTO Backgrounds
USPTO Backgrounds