Computer arrangements and complex circuits are often designed as a plurality of functional units, or modules, interconnected by digital data communications paths. Each functional unit processes data, and transmits/receives data to/from other functional units for additional data manipulations. Data packets in large and small quantities are communicated between functional units, for example, between individual discrete circuits, between integrated circuits on a common chip, or between remotely located circuits coupled to or within various parts of a system or subsystem. A typical digital-data path is implemented in various forms, including a cable, a backplane circuit, one or more printed circuit board (PCB) traces, a bus structure internal to a chip, other interconnect, or any combination of such communication media. Regardless of the configuration, the communication typically requires closely controlled interfaces that are designed to ensure that data integrity is maintained. Circuit designs and data communication paths are sensitive to practicable limitations in terms of implementation space and available operating power. An increased demand for high-speed electronic devices must address not only performance of the functional units themselves, but also the speed and efficiency requirements by which data is passed between the functional units.
Serial data communication transmits data bits across a communication path, one information unit after another. Other high-speed communication applications are implemented using parallel data channels, or buses, in which multiple data bits are simultaneously sent across parallel communication paths. However, implementing parallel communication paths use up more area than a single (i.e., serial) data path. Area is a valuable commodity in some applications. In a parallel communication scheme, a transmitting module transmits data over the parallel bus synchronously with a clock from the transmitting module. In this manner, the transitions on the parallel signal lines leave the transmitting module in a synchronous relationship to each other and/or to a clock on the transmitting module. In such systems, the received signals (and where applicable, the receive clock) should have a specific relative phase relationship in order to provide proper data recovery. However, the length of the clock signal path and data signal paths must be closely controlled so that the propagation delay of each respective signal, relative to one another, does not interfere with the intended signal phase relationships. In addition, clock signal path distance is typically limited to confine clock signal “skew” effects within tolerable limits; therefore, a clock domain generally correlates with a compact geographical region of a circuit or system. Generally as clock speeds increase, the signal phase relationship margins to accommodate signal path differences decrease, thus mandating even closer signal path tolerances. For similar reasons, the geographical region correlating to a clock domain shrinks as clock frequency increases.
Frequently, functional units each operate using their own clock domain; therefore, a data-transmitting module might be operating in one clock domain at a first clock frequency, while a data-receiving module is operating in another clock domain at a different (and perhaps non-synchronous) second clock frequency. Additional data buffer circuitry is necessary to interface parallel communications between clock domains.
A method and apparatus that improves upon the aforementioned physical busing characteristics, as well as addresses other related variables, are therefore desirable.
USPTO Backgrounds
USPTO Backgrounds