The present disclosure relates generally to the field of fabrication of semiconductor devices, and more specifically to a method of fabricating a fin type field effect transistor (FinFET) or portion thereof.
As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three dimensional designs, such as a fin-like field effect transistor (FinFET). A typical FinFET is fabricated with a thin ‘fin’ extending from a substrate, for example, etched into a silicon layer of the substrate. The channel of the FET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. It is beneficial to have a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow.
There have been problems associated with fabrication of FinFETs as device structures become more dense. For example, dense structures of FinFET architecture require a lower implant tilt angle and a higher implant energy in order to provide a proper dose collection efficiency on the FinFET side wall. However, the higher implant energy may increase amorphization of the fin even under the gate which will degrade the performance of the FinFET.
As such, an improved FinFET device and fabrication method of a FinFET device is desired.
USPTO Backgrounds
USPTO Backgrounds