1. Field of the Invention
The present invention relates generally to a plating method without plating a conduction line, and more particularly, to a method for selectively processing a surface tension of a solder mask layer in a circuit board.
2. The Prior Arts
Nowadays, electronic products are fast developed with the trend toward lightness, slimness, and multifunction. Correspondingly, this demands greater I/O numbers for the chips of the electronic products. Currently, the flip-chip technology has been used in packaging many high class electronic products, and therefore the packaging densities thereof have also been increased correspondingly.
In order to increase a packing density, a distance between a chip and a pad thereof is desired to be reduced. In a packaging process, the chip is going to be stuck to a carrier board by a silver paste. However, the silver paste is likely to disperse from a flip chip area to an adjacent area, e.g., a pad, and contaminate the same. A contaminated pad may cause a false soldering or a poor soldering, thus affecting the yield and the reliability thereof.
Further, flip-chip chip size package (CSP) has become more widely used. For example, sometimes there might be a flip-chip and a wirebond simultaneously configured on a same carrier board. As such, if the silver paste for sticking the chip unfortunately disperses to and contaminates a wirebond finger, it may cause a wirebond failure.
Further, in a conventional flip-chip package on package (POP) design, because the tin ball pad is configured very close to the chip, the underfill may possibly disperse to the tin ball pad during a flip-chip underfill process. Furthermore, in a system in package (SIP) design, because of the problem of dispensing contamination on other areas, the carrier board cannot be made smaller, or loss of the electrical performance occurs.
In order to provide a solution to the aforementioned problem of silver paste disperses to adjacent area and contaminates the same, the current technology adopts: 1. Using other kinds of underfills to control the flowability of the fluid on the carrier board; 2. Providing a dam or configuring a groove on the solder mask to block underfill overflowing; 3. Increasing the distance from the dispensing position to the solder pad; or 4. Introducing a frame processing to block the underfill overflowing. However, these technologies have their own restrictions and demand a higher production cost, and have a narrow operation window.
USPTO Backgrounds
USPTO Backgrounds