The invention in general relates to a digital driver circuit, and in particular to a digital driver circuit which uses CMOS inverters.
Digital driver circuits are used in integrated circuits to recharge relatively large capacitance values, such as occur, for example, in connection with the feed-in of data and clock pulses. The driver circuits thereby adapt small capacitive loads to large capacitive loads, whilst optimising delay times. A further criterion for optimising digital driver circuits constitutes the amount of chip surface required. Examples of digital driver circuits include output driver circuits, part of which are bus drivers.
In order to reduce the delay times caused by the re-charging process, which can have a negative influence on the overall speed of a digital system, a particularly simple digital driver circuit has been proposed, which consists of a chain of CMOS inverters, where the relation of channel width (W) to channel length (L) (from here on referred to as W/L ratio, for simplicity), of the MOS FETs composing the CMOS inverters increases from chain unit to chain unit. Huang Chang Lin and Loren W. Linholm describe such a digital driver circuit in their article xc3x4An Optimised Output Stage for MOS Integrated Circuitsxc3x6in the IEEE Journal of Solid State Circuits, Vol. SC-10, No. 2, April 1975. The degree of change of the W/L ratio between the individual chain units is chosen to suit specific applications, so as to minimise the delay times caused by the re-charging processes.
FIG. 1 shows such a digital driver circuit with inverting functions, as known in accordance with contemporary technology, which consists of three successive CMOS inverters where the source of each p-channel MOS FET is connected to the supply voltage and the source of each n-channel MOS FET is connected to ground. If a digital input signal of voltage Ue, which may take the states of 0 V or Vcc, is applied to input 1 of the circuit, this appears as an inverted digital output signal of voltage Ua at the output 2 of the circuit. As illustrated in FIG. 2, the W/L ratios of the p-channel MOS FETs of the individual stages, from input 1 of the circuit to output 2 of the circuit, increase from 20/1 to 200/1 and then to 800/1, and those of the n-channel MOS FETs increase from 10/1 to 100/1 and finally to 400/1.
When in a non-active state, that is when the digital input signal Ue of the circuit is in either the H or L state, the energy consumption of the circuit is very low, since in each CMOS inverter one MOS FET is in the OFF state, therefore preventing current to flow from the supply voltage terminal to the ground terminal. When, however, the digital input signal changes its state, that is when it changes either from the H into the L state or from the L into the H state, both MOS transistors of each of the inverter stages are switched ON during a short period while the voltage Ue changes, leading to a current peak. The largest current peak will thereby be generated by the last CMOS inverter, which is the one supplying the greatest power.
These current peaks, which for circuits designed for low power applications may be well in excess of currents normally encountered, are undesirable and may be the cause of several problems. For example, reference circuits and low-noise circuits may suffer interference from these current peaks. Furthermore, when series resistors are used as a protection against electrostatic discharges, these current peaks cause a marked voltage drop at the resistors involved.
The purpose of the invention is to provide an especially compact driver circuit of simple design, whereby the current peaks originated in conventional circuits of this type, when the digital input signal changes over, are markedly reduced. This problem is solved by a digital driver circuit comprising
one or more cascading input stages, each consisting of a CMOS inverter where the source of its p-channel MOS FET is connected to the supply voltage and where the source of its n-channel MOS FET is connected to ground, whereby the ratio between channel width (w) and channel length (L) (W/L ratio) of the CMOS inverter MOS FETs increases from stage to stage by a pre-determined amount;
an intermediate stage with a first CMOS inverter, where the source of its p-channel MOS FET is connected to the supply voltage, and a second inverter where the source of its n-channel MOS FET is connected to ground, whereby the inputs of both the CMOS inverters of the intermediate stage are connected to the output of the last input stage, the source of the n-channel MOS FET of the first CMOS inverter of the intermediate stage being connected to the source of the p-channel MOS FET of the second CMOS inverter of the intermediate stage, and where the pre-determined W/L ratio of the p-channel MOS FET of the first CMOS inverter of the intermediate stage and of that of the n-channel MOS FET of the second CMOS inverter of the intermediate stage is not smaller than that of the corresponding MOS FET of the last CMOS inverter of the input stages;
a delay stage with a CMOS inverter connected between the supply voltage rail and ground, the input of which being connected o the output of the last input stage, and whose output is connected to the source of the n-channel MOS FET of the first CMOS inverter of the intermediate stage; and
an output stage with a p-channel MOS FET, the gate of which is connected to the output of the first CMOS inverter of the intermediate stage, and whose source is connected to the supply rail, and an n-channel MOS FET, the gate of which is connected to the output of the second CMOS inverter of the intermediate stage, and whose source is connected to ground, whereby the drains of both MOS FETs of the output stage are connected to each other, as well as with the output of the circuit, and where the W/L ratio of the p-channel MOS FET of the output stage and the W/L ratio of the n-channel MOS FET of the output stage exceed the W/L ratio of the p-channel MOS FET of the first CMOS inverter of the intermediate stage or, respectively, the W/L ratio of the n-channel MOS FET of the second CMOS inverter of the intermediate stage by a pre-determined value;
whereby the W/L ratio of the MOS FETs of the CMOS inverter of the delay stage, in comparison with the W/L ratios of the corresponding MOS FETs of the last CMOS inverter of the input stages, the p-channel MOS FET of the first CMOS inverter of the intermediate stage, and the n-channel MOS FET of the second CMOS inverter of the intermediate stage is made so small that the switch-over of both the MOS FETs of the output stage occurring when a change of the digital input signal at the input of the circuit takes place is offset in time with respect to each other.
The digital driver stage according to the invention achieves the reduction of current peaks in that the p-channel MOS FET and the n-channel MOS FET of the output stage of the circuit switch over at different times when the digital input signal changes, so that the current flow occurring with conventional driver circuits during switch-over between the supply voltage and ground is either absent or markedly shorter and smaller than before.
Advantageous further embodiments of the invention are characterised in the sub-claims.
USPTO Backgrounds
USPTO Backgrounds