Semiconductor devices, such as magnetic random access memory (MRAM) devices, use magnetic bits to store information. A free layer of the device serves as the magnetic bit. The information is stored as the direction of magnetization of the bit, either pointing right or left, to store “1” or “0.” When the bit is sitting in a zero applied magnetic field, its magnetization is stable, pointing either right or left. The application of a magnetic field can be used to write information to the bit by switching the magnetization of the bit from right to left, or vice versa. One of the important requirements for data storage is that the magnetization of the bit not change direction when there is a zero applied field, or only a small applied field.
Unfortunately, in practice, the magnetization of the bits does change directions unintentionally, due to thermal activation. Thermal activation occurs when thermal energy from the environment surrounding the bit overcomes an activation energy barrier to change the direction of magnetization. The occurrences of thermal activation should be minimized. The resulting error rate due to thermally activated switching is called the soft error rate (SER).
One of the objectives in designing MRAM devices is to have low operating power and small area. Low operating power and small area requires a low switching field for the bit. A low switching field uses a low switching current, which in turn uses less power. Further, lower switching currents require smaller switches, which occupy less space.
As the area of the bits becomes increasingly smaller, a process referred to as “scaling” due to the fact that the bit area is scaled down to allow for more bits in the same area, the SER becomes worse. As mentioned above, the activation energy barrier may be overcome due to thermal energy, resulting in thermal activation. Therefore, it is desirable to have a large enough activation energy barrier to prevent thermal activation and the magnetization of the bit changing direction.
According to single domain theory, the activation energy barrier of the bit is proportional to the volume of the bit. Therefore, as the area is scaled down, and if nothing else changes, the activation energy barrier decreases and the SER becomes unacceptably large. A conventional, simple solution to this problem would be to increase the thickness of the bit as the area of the bit is scaled down, to maintain a large enough volume to keep the energy activation barrier large enough. However, this technique quickly runs into problems because a greater magnetic field is required to switch the magnetization of a thicker bit. Thus, a primary goal of the scaling process becomes to make the area of the bit smaller, but to maintain the activation energy barrier and the switching field, i.e., preventing the activation energy barrier from becoming too small and preventing the switching field from becoming too large.
U.S. Pat. No. 6,545,906, issued to Savtchenko et al. (hereinafter “Savtchenko”), discloses a new type of free layer for use in MRAM devices. The free layer is composed of two magnetic layers separated by a non-magnetic spacer layer. In a zero applied magnetic field, the two magnetic layers have moments that are lined up anti-parallel to each other due to anti-ferromagnetic dipole coupling and exchange coupling.
The spacer layer may provide some exchange coupling. This exchange coupling, as described in Savtchenko, is however limited to anti-ferromagnetic exchange coupling.
It would be desirable to be able to produce semiconductor devices that allow for a reduction in area, yet maintain an activation energy barrier and a switching field, such that occurrences of thermal activation are minimized.
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