1. Field of the Invention
The present invention relates to an input circuit for a semiconductor integrated circuit device and, more particularly, to an improvement in operating characteristics of an input circuit for processing an input signal having an amplitude smaller than the amplitude of the signal outputted from an inverter circuit of the input circuit.
2. Description of the Background Art
FIG. 7 is a circuit diagram of a conventional input circuit for a semiconductor integrated circuit device. In FIG. 7, reference numeral 100 designates a PMOS transistor; 101 designates an NMOS transistor; 1 designates a power source for supplying a power supply potential V.sub.DD ; 2 designates a power source for supplying a ground potential V.sub.SS ; 3 designates an input terminal of the input circuit; and 5 designates an output terminal of the input circuit.
In operation, the PMOS transistor 100 and the NMOS transistor 101 form a CMOS inverter circuit. When a voltage V.sub.IN of a signal applied to the input terminal 3 is not more than a logical threshold voltage V.sub.T of the CMOS inverter circuit, the power supply potential V.sub.DD given through the PMOS transistor 100 is outputted to the output terminal 5 of the input circuit. Conversely, when the voltage V.sub.IN is not less than the logical threshold voltage V.sub.T, the ground potential V.sub.SS given through the NMOS transistor 101 is outputted to the output terminal 5 of the input terminal.
The logical threshold voltage V.sub.T of the CMOS inverter circuit is determined by the current driving capability ratio of the NMOS transistor 101 to the PMOS transistor 100 and, accordingly, is strongly affected by fabrication variations of semiconductor integrated circuit devices. When the voltage of the input signal is indicated as V.sub.TN .ltoreq.V.sub.IN .ltoreq.V.sub.DD +V.sub.TP (V.sub.TN is a threshold voltage of the NMOS transistor, and V.sub.TP is a threshold voltage of the PMOS transistor), neither the PMOS transistor 100 nor the NMOS transistor 101 enters the cut-off state, so that power is dissipated by the path extending from the power source 1 and through the PMOS and NMOS transistors 100 and 101 to the power source 2.
The conventional input circuit having the foregoing arrangement has the problem that the small amplitude of the input signal causes lower operating speeds and more power consumption of the input circuit.
USPTO Backgrounds
USPTO Backgrounds