1. Field of the Invention
The present invention relates to a semiconductor memory device having an error correction function and particularly to a nonvolatile semiconductor memory device having a high speed read mode as well as an error correction function.
2. Description of the Related Background Art
A nonvolatile semiconductor memory device generally has a memory cell array comprising multiple memory cells arranged in a matrix. As the storage capacity of semiconductor memory devices becomes larger, the probability of the occurrence of a bit error due to a hard error (a malfunction caused by a failure of a memory cell) or a soft error (a malfunction caused by radiation such as alpha rays) becomes higher. Since many years ago, there have been semiconductor memory devices having an ECC circuit to execute error correction on such bit errors. Further, in order to inspect the operation of the ECC circuit and whether a failure exists in a memory cell, an access test is executed which reads data from a semiconductor memory device storing data of a known test pattern under various conditions and verifies the read data pattern with the known test pattern. A conventional technique related to such an access test is disclosed in, e.g., Japanese Patent Kokai No. H05-241868 (Patent Document 1).
Meanwhile, there have been semiconductor memory devices having an operation mode in which to read data at high speed from the memory cell array. Among this type of operation modes, a page access mode and a burst mode are known. Japanese Patent Kokai No. H10-255495 (Patent Document 2) and U.S. Pat. No. 5,963,488 (Patent Document 3) disclose a semiconductor memory device having the page access mode. When operating in the page access mode, this semiconductor memory device reads one page worth of data from a predetermined number of memory cells of the memory cell array simultaneously in parallel and latches the read data and then time divides the latched data sequentially into multiple divided data to output consecutively the multiple time divided data. For example, where one page worth, 128 bits, of data is read out simultaneously in parallel and latched, the 128 bits of data is time divided into multiple 32-bit data, and these 32-bit data are output consecutively. Hence, in the page access mode, data can be read from the memory cell array at higher speed than in a normal random access mode.
USPTO Backgrounds
USPTO Backgrounds