1. Field of the Invention
The present invention generally relates to static random access memory devices and, more particularly to a high integrated and less power consuming static random access memory device.
2. Description of the Background Art
Generally, a static random access memory is used in various electronic equipments such as a computer. Less power consumption and high degree of integration are more increasingly required in the semiconductor memory as the function of those equipments improves.
FIG. 16 is a circuit diagram of a memory cell circuit and a source potential controlling circuit in a conventional SRAM. The circuit shown in FIG. 16 is disclosed in Japanese Patent Laying-Open No. 56-143587 (corresponding to U.S. Pat. No. 4,409,679). Referring to FIG. 16, one memory cell MA includes NMOS transistors QB5 and QB6, and resistances R1 and R2 constituting a data storage circuit, and NMOS transistors QB3 and QB4 as access gates. Transistors QB3 and QB4 have their gates connected to a word line WL. The sources of transistors QB5 and QB6 are connected to a source potential controlling circuit 8z through a source line SL.
Source potential controlling circuit 8z includes NMOS transistors QB7, QB8, QB9, and QB10 for generating a predetermined intermediate potential and resistors R3 and R4. An output node No of an intermediate potential generating circuit is connected to source line SL. An NMOS transistor QB11 is connected between output node No and ground. Transistor QB11 have the gate connected to receive a column selection signal Y provided from a column decoder (not shown). Bit lines B1 and B2 are connected to an IO line (not shown) through NMOS transistors QB12 and QB13 constituting a Y gate circuit.
In operation, when a column shown in FIG. 16 is selected, a high level column selection signal Y is applied from a column decoder (not shown). Accordingly, transistors QB11, QB12, and QB13 turn on. When transistor QB11 turns on, a power supply potential VDD and a ground potential VSS are applied to a memory cell MA as a power supply voltage. Additionally, when word line WL attains a high level, transistors QB3 and QB4 turn on. As a result, bit lines B1 and B2 are driven by transistors QB5 and QB6, respectively, in response to a stored data signal.
When the column shown in FIG. 16 is not selected, column selection signal Y attains a low level. Therefore, transistors QB11, QB12, and QB13 turn off. When transistor QB11 turns off, an intermediate potential between VDD and VSS provided from source line potential controlling circuit 8Z is applied to the sources of transistors QB5 and QB6 through source line SL. Consequently, the power supply consumed in the memory cells of the non-selected column is decreased.
Memory cell MA shown in FIG. 16 is constituted by 6 elements. A wide region is needed on a semiconductor substrate in order to form these 6 elements. A certain area on the substrate is occupied in order to form two transistors QB3 and QB4, particularly needed as the access gates. Additionally, since two bit lines B1 and B2, and source line SL are needed in each column, the space between interconnections in the column direction is narrow. This is an obstacle to the improvement of the degree of integration. This means that in SRAM shown in FIG. 16, in particular, the interconnection formed in the column direction becomes dense, since source line SL is needed in each column in addition to two lines B1 and B2.
SRAM including the memory cells each constituted by five elements is known to decrease the region occupied by the memory cells on the semiconductor substrate. Memory cell circuits shown in FIGS. 17, 18, and 19 show conventional examples of such SRAM. These are disclosed in Japanese Patent Laying-Open Nos. 61-24092 and/or 61-26997.
FIG. 17 is a circuit diagram of a conventional SRAM including the memory cells each constituted by five elements. Referring to FIG. 17, the SRAM includes memory cells MB1 to MB4, each constituted by three NMOS transistors and two resistances. Sources of driver transistors in memory cells MB1 and MB2 provided in kth column are connected to a write line WRk. Access transistors are connected to a bit line BLk. Memory cells MB3 and MB4 provided in k+1st column are connected to a write line WRk+1 and a bit line BLk+1 in the same manner.
The purpose of write lines WRk and WRk+1 being provided in SRAM shown in FIG. 17 is to apply a power supply potential VDD to the memory cells through the write lines in write operation. Power supply voltage VDD for data writing operation is applied through the write lines to a column where data is to be written in, namely, memory cells in a column which is to be accessed. In read operation, the write line is maintained at a ground potential Vss. It should be clear that the purpose of controlling the voltages of the write lines is not to decrease power consumption in the memory cells.
SRAM is improved as shown in FIG. 18 in order to prevent possible malfunction in SRAM shown in FIG. 17. In addition to this, SRAM shown in FIG. 19 is proposed to improve the degree of integration of SRAM shown in FIG. 17. It should be clear that the write lines WRk, WRk+1, WRi, and WRi+1 are provided to SRAMs shown in FIGS. 18 and 19 in the same manner as the SRAM shown in FIG. 17 for carrying out write operation and not for decreasing power supply consumption in the memory circuits. As a result, these write lines are brought to power supply potential VDD in write operation, and brought to ground potential Vss in read operation.
In the conventional memory cells as mentioned above, it should be clear that the gate oxide film of NMOS transistor connected to the word line may easily be destroyed, in addition to the fact that much power consumption is in the memory cell circuit. This means that the power supply potential VDD and the ground potential Vss are applied as the power supply voltages to all of the memory cells even when SRAM is at an active state, that is, even when read or write operation is carried out in SRAM. As a result, the voltage of VDD-Vss is applied across the gates-source of the access transistor in a memory cell which is not accessed. When high degree of integration is advanced in SRAM, a gate oxide film becomes thin. Consequently, the gate oxide film has a tendency to be destroyed by the voltage applied across the gate-source. It is preferable that the voltage applied across the gate-source decreases in order to prevent destruction of the gate oxide film. However, in the conventional SRAM, the gate oxide film is destroyed as time passes since a constant power supply voltage is always applied to the memory cells. It should be noted that the failure rate as time passes of destruction of the gate oxide film is high.
USPTO Backgrounds
USPTO Backgrounds