Semiconductor device designers often desire to increase the level of integration or density of features within a semiconductor device by reducing the dimensions of the individual features and by reducing the separation distance between neighboring features. In addition, semiconductor device designers often seek to design architectures that are not only compact, but offer performance advantages, as well as simplified designs
One example of a semiconductor device is a memory device. Memory devices are generally provided as internal integrated circuits in computers or other electronic devices. There are many species of memory including, but not limited to, random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), FLASH memory, and resistance variable memory. Non-limiting examples of resistance variable memory include resistive random access memory (ReRAM), conductive bridge random access memory (conductive bridge RAM), magnetic random access memory (MRAM), phase change material (PCM) memory, phase change random access memory (PCRAM), spin-torque-transfer random access memory (STTRAM), oxygen vacancy-based memory, and programmable conductor memory.
A typical memory cell of a memory device includes an access device (e.g. a transistor) and a memory storage structure (e.g., a capacitor) electrically coupled to the access device through a conductive contact. The access device generally includes a channel region between a pair of source/drain regions, and a gate electrode configured to electrically connect the source/drain regions to one another through the channel region. The access device generally includes a channel region between a pair of source/drain regions, and a gate configured to electrically connect the source/drain regions to one another through the channel region. The access devices can comprise planar access devices or vertical access devices. Planar access devices can be distinguished from vertical access devices based upon the direction of current flow between the source and drain regions thereof. Current flow between the source and drain regions of a vertical access device is primarily substantially orthogonal (e.g., perpendicular) to a primary (e.g., major) surface of a substrate or base structure thereunder, and current flow between source and drain regions of a planar access device is primarily parallel to the primary surface of the substrate or base thereunder.
Unfortunately, conventional methods of forming memory cells for memory devices can negatively impact desirable electrical properties of the memory cells and the memory devices. For example, a conductive contact included in conventional memory cell may employ cobalt disilicide (CoSi2) to decrease contact resistance, as well as a metal nitride (e.g., TiN) liner to facilitate adhesion of a conductive structure (e.g., a conductive plug) to the CoSi2. However, it can be difficult to form CoSi2 to substantially uniform thickness at relatively small contact diameters (e.g., diameters less than or equal to about 100 Angstroms (Å)), resulting in CoSi2 detachment problems (e.g., due to void creation in the CoSi2) and/or undesirable leakage currents (e.g., due to undesirable metal silicide growth into a silicon-containing region of the memory cell, such as a source/drain region of an access device thereof). CoSi2 oxidation can also undesirably increase contact resistance, requiring complex cleaning strategies (especially at relatively small contact diameters). Furthermore, conventional methods of forming the metal nitride liner can result in undesirable migration (e.g., diffusion) of metal of the metal nitride liner and/or other materials (e.g., atoms of precursor compounds used to form the metal nitride liner through chemical vapor deposition (CVD) processes) into other portions of the memory cell (e.g., a silicon-containing region of the memory cell, such as a source/drain region of an access device thereof) that can also effectuate undesirable leakage currents. Conventional methods of forming the metal nitride liner can also undesirability limit the size of the conductive structure subsequently formed thereover, which may undesirably increase contact resistance and/or may require complex alignment processes to connect other structures to the conductive structure.
A need, therefore, exists for new, simple, and cost-efficient methods of forming apparatuses that alleviate one or more of the aforementioned problems, as well as new apparatuses, semiconductor devices (e.g., memory devices, such as DRAM devices), and electronic systems.
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