The use of optical interconnects for silicon integrated circuits has been employed heretofore to take advantage of the greater capacity of optoelectronics for communications while retaining the computational advantages of silicon electronics. The integration of optoelectronic devices directly on silicon circuits offers the added advantage that such devices need not be located along the chip edge, thereby enhancing the potential for increasing the "pinout count.revreaction. of the chip. Accordingly, those skilled in the art have focused their interest upon the molecular beam epitaxial growth of gallium arsenide/aluminum gallium arsenide (GaAs/AlGaAs) multiple quantum well modulators on submicron MOS electronics.
During the growth of gallium arsenide on MOS devices by heteroepitaxy, it is necessary to protect the silicon device from the affect of gallium which readily diffuses into the silicon, so resulting in the formation of a conductive oxide. In order to obviate this limitation, the use of a silicon nitride layer over the oxide has been found to result in a diffusion barrier during molecular beam epitaxial growth. However, in order to assure success of the nitride barrier it is essential that the barrier evidence sufficient resistance to hydrofluoric acid used to clean the silicon surfaces prior to growth. Furthermore, the nitride barrier must evidence sufficient mechanical stability to withstand oxide desorption at temperatures in excess of 900 degrees Centigrade which are necessary for the successful growth of gallium arsenide on silicon without effecting cracking or loss of adhesion. The mechanical stability is especially critical for submicron MOS electronics which have as their top dielectric layer a glass which liquefies at 850 degrees Centigrade to round the edges of contact holes. It is this liquification of the reflow glass which tends to cause failure of the nitride diffusion barrier.
USPTO Backgrounds
USPTO Backgrounds