The demand for ever-faster computers requires that state-of-the-art microprocessors execute instructions in the minimum amount of time. Microprocessor speeds have been increased in a number of different ways, including increasing the speed of the clock that drives the processor, reducing the number of clock cycles required to perform a given instruction, implementing pipeline architectures, and increasing the efficiency at which internal operations are performed. This last approach usually involves reducing the number of steps required to perform an internal operation.
Efficiency is particularly important in mathematical calculations, particularly floating point calculations that are performed by a data coprocessor. The relative throughput of a processor (i.e., integer unit pipeline) that drives a coprocessor (i.e., floating point unit pipeline) may change drastically depending on the program being executed. If the floating point unit is built fast enough to handle the high-end throughput of the integer unit pipeline, then idle instructions (or “bubbles”) that cause no change in status may be inserted into the floating point unit pipeline during periods when the integer unit is supplying data and instructions to the floating point unit at the low-end rate.
Unfortunately, the bubble instructions cause circuitry to be clocked in the stages of the execution pipeline without doing any useful work, thereby wasting power. This is particularly damaging to the performance of portable devices that operate from a battery, because the wasted power reduces battery life. However, if the floating point unit is slowed down to match the low-end throughput of the integer unit, then the execution pipeline of the floating point unit cannot keep up with the high-end throughput rate of the integer unit pipeline, thereby stalling the processing system.
Therefore, there is a need in the art for an improved data processor that executes mathematical operations more rapidly. In particular, there is a need for an improved floating point unit that executes floating point instructions as rapidly as possible, with minimum power consumption. More particularly, there is a need in the art for a floating point unit that can operate at the high-end throughput rate of the integer unit pipeline without requiring the use of bubble instructions during periods when the integer unit pipeline is driving the floating point unit at the low-end throughput rate of the integer unit pipeline.
USPTO Backgrounds
USPTO Backgrounds