This invention broadly relates to a process for forming a device by selective deposition and patterning of thin film layers of insulative, semiconductive, and conductive materials. More particularly, the invention concerns an improved method of forming such a device wherein thin film layers of insulator, semiconductor, and metal are deposited in successive sequence under continuous vacuum. The invention has particular utility in the photolithographic fabrication of thin film transistors and arrays thereof. In the fabrication of such devices, single pump down formation of the semiconductor-gate insulator and semiconductor-source/drain contact interfaces minimizes the exposure of these critical interfaces to contamination during wet processing.
With increasing demand for high device density, photolithographic processes have become increasingly popular as economical means for fabricating thin film transistors. Such techniques are particularly advantageous in the preparation of high density thin film transistor drivers for high resolution, large area displays, such as those incorporating liquid crystal or electroluminescent media.
Conventional photolithographic techniques characteristically employ wet chemistry processes to selectively define patterned layers of conductive and insulative materials. These wet processes include chemical polish etching for initial substrate preparation, structural, or pattern delineation, etching to create a relief structure geometry, and photoresist processing.
The electrical performance and the stability of surface field effect transistors are critically dependent upon the quality of the semiconductor-insulator interface and upon the ohmic properties of source drain contacts to semiconductor interface. The quality of both interfaces can be impaired by impurity contamination arising from exposure from each material (i.e., conductor, insulator, and semiconductor) surface to wet processing. Such contamination increases the densities of interface states and reduces conduction modulation. Incorporation of ionic species present in the chemical solution alters the otherwise predictable threshold voltages. Charge transfer processes at interface states and field aided migration of mobile ionic species induces operational instabilities into the devices. Impurity related contact barriers degrade transconductance by limiting current and crowding transistor characteristics. These wet processing induced degradations create device characteristics problems such as non-reproducability from batch to batch and non-uniformity among devices within a single batch. These problems are particularly pernicious when a large area transistor array is being fabricated for use in a display. In this context, the demands of high quality image resolution necessitates a high degree of uniformity among transistor characteristics and an extremely high yield of operable devices.
The present invention provides a process for overcoming the disadvantages which can arise from exposure of critical surfaces of the constituent layers of the thin film device to wet processing.
USPTO Backgrounds
USPTO Backgrounds