1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device by using a dual-damascene process in which a wiring is formed while simultaneously filling a contact hole.
2. Description of the Related Art
As multi-layer wiring structures are more widely used in semiconductor memory devices, the aspect ratio of contact holes, i.e., the ratio of the diameter of the hole to its depth, increases so that various kinds of problems, such as a non-planar phenomenon, poor step coverage, shorts caused by residual metal, low yield rate, reduced reliability and the like, occur. In order to solve the above problems, a damascene process has been suggested as a new wiring technique. According to the damascene process, a trench (or a hole) is formed by partially etching an insulating layer, and a conductive layer is deposited such that the trench is completely filled. Excess insulating layer remaining on the insulating layer is removed by performing chemical mechanical polishing (CMP) process thereby forming a wiring in the trench.
In the damascene process, the wiring is engraved in a trench area of the insulating layer. The wiring is mainly formed as a line and space pattern. Recently, a damascene process for forming the wiring while simultaneously filling up a via hole or a contact hole is widely used.
A flash memory device is a kind of an EEPROM (electrically-erasable programmable read only memory) which can electrically erase data at high speed. The flash memory device electrically controls the input and output of data by using an F-N (Fowler-Nordheim) tunneling effect or hot electron injection.
Flash memory devices are typically of the NAND type, in which a plurality of cell transistors are connected in series to form a unit string and the unit strings are connected between a bit line and a ground line in a row, or the NOR type, in which each cell transistor is connected between the bit line and the ground line in a row. The NOR type is adapted for high-speed operation and the NAND type is adapted for high integration.
FIGS. 1A to 1E are sectional views showing a method for manufacturing a NAND type flash memory using a conventional dual-damascene process. Referring to FIG. 1A, an oxide material is deposited on a semiconductor substrate (not shown) formed with cell transistors having a stacked gate structure and selecting-transistors having a MOS transistor structure, thereby forming an insulating interlayer 16. Then, the insulating interlayer 16 is etched by performing a photolithography process so that a bit line contact hole 18 is formed. A doped polysilicon layer is deposited on the bit line contact hole 18 and the insulating interlayer 16. Then, a plasma dry etching process is carried out so as to etch-back the polysilicon layer to expose a surface of the insulating interlayer 16, thereby forming a bit line plug 20 in the bit line contact-hole 18.
By performing the plasma etching process, gas in a plasma state is dissociated into ions, electrons and active radicals. The ions, electrons and active radicals are combined with atoms existing in an etching area of the semiconductor substrate and disappear from the surface of the semiconductor substrate while creating new materials. At this time, a local charging occurs at the surface of the insulating interlayer 16 caused by the isotropic flux feature of electrons and the directional flux feature of ions in a plasma sheath, so a damaged layer 21 is formed.
Referring to FIG. 1B, silicon oxynitride (SiON) is deposited on the bit line plug 20 and the insulating interlayer 16 by using a plasma-enhanced chemical vapor deposition (PE-CVD) process, thereby forming an etching stop layer 22. Then, TEOS is deposited on the etching stop layer 22 by using the PE-CVD process to form a bit line insulating layer 24.
Referring to FIG. 1C, a bit line insulating layer pattern 25 and an etching stop layer pattern 23 are formed by etching the bit line insulating layer 24 and the etching stop layer 22 using a photolithography process. The bit line insulating layer pattern 25 isolates adjacent bit lines from each other, and is patterned in the same direction as in the bit line. That is, a bit line wiring area 26 is defined between insulating layer patterns 25.
Referring to FIG. 1D, after exposing the active area formed at a peripheral portion of a memory cell using the photolithography process, the exposed insulating interlayer 16 is etched so as to form a metal contact hole 28.
Referring to FIG. 1E, after performing a cleaning process using hydrofluoric acid (HF) for removing a native oxide film remaining on the bit line plug 20, a barrier metal layer 30 made of titanium/titanium nitride (Ti/TiN) is deposited on the bit line plug 20, the metal contact hole 28, the bit line insulating layer pattern 25 and the insulating interlayer 16. Then, a tungsten layer 32 having a thickness sufficient for filling up the bit line wiring area 26 and the metal contact hole 28 is deposited on the barrier metal layer 30.
Thereafter, though it is not illustrated, a bit line connected to the bit line plug 20 and a metal wiring layer for filling up the metal contact hole 28 are formed by removing the tungsten layer 32 to expose the surface of the bit line insulating layer pattern 25 by using the CMP process.
According to the above-mentioned conventional method, when the etch back process is carried out, a plate-shaped defect at an edge of a wafer (shown in FIG. 2) is shifted into an inner portion of the wafer so that an error occurs when the photolithography process is carried out. The plate-shaped defect mainly occurs at a fixing portion of the wafer to which a chuck is coupled and a bevel portion of the wafer. The plate-shaped defect, which occurs when the polysilicon etch back process is carried out, is assumed as having occurred at a polysilicon type material. Accordingly, if the plate-shaped defect remains in the wafer, the bit line insulating layer pattern 25 cannot be properly formed in the subsequent process or the metal contact hole 28 cannot be opened.
In addition, the damaged layer 21 is formed on the surface of the insulating interlayer 16 by the polysilicon etch back process and the etching stop layer 22 made of silicon oxynitride is stacked on the damage layer 21. Therefore, when the HF cleaning process is carried out before the barrier metal layer 28 is deposited, a lateral undercut (circle A of FIG. 1E) of the etching stop layer pattern 23 increases at an interfacial surface between the etching stop layer pattern 23 and the insulating interlayer 16. Sometimes, the etching stop layer pattern 23 is lifted so that the bit line insulating layer pattern 25 falls down.
To solve the above problems of the prior art, it is a first object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing a plate-shaped defect generated during a polysilicon etch back process and solving a lateral undercut problem of an upper insulating layer.
A second object of the present invention is to provide a method for fabricating a non-volatile memory device capable of forming a bit line while simultaneously filling up a metal contact hole and capable of preventing a plate-shaped defect generated during an etch back process of polysilicon for a bit line plug and solving a lateral undercut problem of an upper insulating layer.
In accordance with the invention, there is provided a method for manufacturing a semiconductor device. In accordance with the method of the invention, a polysilicon layer is deposited on an oxide layer having a contact hole or an opening. The polysilicon layer is etched back such that the polysilicon layer remains only in the contact hole or in the opening. A cleaning process is performed using a first etchant having a similar etching rate with respect to polysilicon and oxide, thereby removing a damaged layer which is created on a surface of the oxide layer when the etch back process is carried out with respect to the polysilicon layer. An insulating layer is deposited on the resulting structure.
In one embodiment, the first etchant has an etching ratio of 1:1 to 1:1.5 with respect to polysilicon and oxide. The first etchant can include a solution comprising NH4OH, H2O2 and H2O which are mixed in a ratio of about 1:4:20.
In one embodiment, the insulating layer is a composite layer including a nitride-based material layer and an oxide-based material layer.
In one embodiment, after the insulating layer is deposited on the structure, an insulating layer pattern is formed by etching the insulating layer, and a cleaning process is performed using a second etchant. The second etchant can include a diluted HF solution in which HF is diluted in a ratio of about 200:1.
In another aspect, the invention is directed to a method for fabricating a non-volatile memory device. In accordance with the method, an insulating interlayer made of oxide is deposited on a semiconductor substrate on which a plurality of active areas defined by a field area extend in a first direction and a plurality of word lines extending in a second direction are formed on the active areas. A plurality of bit line contact holes are formed to expose first regions of the active areas by partially etching the insulating interlayer. A polysilicon layer is deposited on the resulting structure, and the polysilicon layer is etched back, thereby forming bit line plugs in the bit line contact holes. A first cleaning process is performed using a first etchant having a similar etching rate with respect to polysilicon and oxide thereby removing a damaged layer which is created on a surface of the insulating interlayer when the etch back process is carried out with respect to the polysilicon layer. An etching stop layer and a bit line insulating layer are deposited on the structure. The etching stop layer and the bit line insulating layer are etched to form a plurality of bit line insulating layer patterns and etching stop layer patterns which extend in the first direction and to define a bit line wiring area between adjacent bit line insulating layer patterns. A plurality of metal contact holes are formed to expose second regions of the active areas by etching the insulating interlayer. A second cleaning process is performed using a second etchant, thereby removing a native oxide layer from a surface of the bit line plug. A metal layer is deposited on the resulted structure, and the metal layer is removed until the bit line insulating layer pattern is exposed by using a chemical mechanical polishing process, at the same time, forming a metal wiring for filling up the metal contact hole.
In one embodiment, the first etchant has an etching ratio of 1:1 to 1:1.5 with respect to polysilicon and oxide. The first etchant can include a solution comprising NH4OH, H2O2 and H2O which are mixed in a ratio of about 1:4:20.
The first cleaning process using the first etchant can be carried out for about 20 to 30 minutes. The second etchant can include a diluted HF solution in which HF is diluted in a ratio of about 200:1. The insulating interlayer can include high-density plasma oxide. The bit line insulating layer can include a material having an etching rate different from an etching rate of a material of the etching stop layer with respect to a predetermined etching process. The etching stop layer can include a nitride based material and the bit line insulating layer can include an oxide-based material.
In one embodiment, before the metal layer is deposited, a barrier metal layer is deposited on the bit line insulating layer pattern, the bit line plug, the insulating interlayer, and the metal contact hole. The barrier metal layer can be comprised of titanium/titanium nitride (Ti/TiN). The metal layer can be comprised of tungsten.
According to the present invention, a polysilicon based plate-shaped defect can be removed from an edge of a wafer by carrying out a cleaning process using an etchant, such as SC-1, after the etch- back process has been finished. At the same time, the damage layer formed at a lower insulating layer is removed, so the lateral undercut of an upper insulating layer can be reduced when a subsequent cleaning process is carried out.
USPTO Backgrounds
USPTO Backgrounds