Memory coherency is a key technology in a multiprocessor system, and in particular, in the competitive high-end server field, an efficient memory coherency protocol and its implementation are a key factor that determines performance of a high-end server. In key service fields such as banks, securities, governments, or enterprises, the high-end server is an inevitable choice.
By using a high-speed interconnect chip and an efficient interconnect topology structure and with the support of an extensible protocol, a memory-coherent multiprocessor system implemented by hardware basically dominates the entire server market. However, high performance implemented by hardware is also accompanied by a high price. A memory-coherent multiprocessor system implemented by software is limited by communication delays and subject to the constraint of a coherency module, and therefore, an efficient memory-coherent multiprocessor system can hardly be implemented.
By means of virtualization, multiple processor systems are virtualized into a large Symmetrical Multi-Processing (SMP) system provided for an operating system, and hence a memory-coherent multiprocessor system is implemented by software.
In the foregoing solution, a trap into a virtual machine monitor (VMM) is implemented by using an exception, interruption, and the like by using a memory coherency policy and a related interface based on a write-invalidate operation. However, the solution does not support a concurrent multi-write protocol.
In some scenarios, the concurrent multi-write protocol can reduce Central Processing Unit (CPU) usage by about 50% as compared with a write-invalidate protocol. Therefore, the memory coherency protocol supporting concurrent multi-write can virtualize non-coherent memory access in the system to achieve higher efficiency. However, concurrent multi-write of data may cause corresponding data to be out of synchronization between nodes.
USPTO Backgrounds
USPTO Backgrounds