The semiconductor industry currently uses different types of semiconductor-based imagers, including charge coupled devices (CCD) and CMOS imager devices. Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low-cost imaging devices.
A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photogenerated charge in a doped portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges, typically from a floating diffusion region, and produces an output signal which is periodically read-out through a row select access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the floating diffusion region or the floating diffusion region may be directly connected to or part of the photoconversion device. A transistor is also typically provided for resetting the floating diffusion region to a predetermined charge level before it receives the photoconverted charges.
In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of signals representing the reset state and a pixel charge signal. Photo-charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node through a transfer transistor. The charge at the floating diffusion node is converted to a pixel output voltage by the source follower output transistor.
A known three-transistor (3T) CMOS active pixel sensor (APS) design used in many applications contains a photodiode for producing charges which are stored at a diffusion region, a reset transistor for resetting the diffusion region charge, a source follower transistor having a gate connected to the diffusion region for producing an output signal, and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. In a four-transistor (4T) CMOS configuration, a transfer transistor is employed to transfer charges from the photodiode to the diffusion region.
A schematic top view of a semiconductor wafer fragment of an exemplary CMOS sensor pixel four-transistor (4T) cell 10 is illustrated in FIG. 1. The CMOS sensor pixel cell 10 includes a photogenerated charge collection region 21, in a doped portion of the wafer substrate, for collecting charges generated by light incident on the pixel cell 10. This region 21 is formed as a pinned photodiode 11 (FIG. 2). The photodiode 11 is “pinned” because the potential in the photodiode 11 is pinned to a constant value when the photodiode 11 is fully depleted. It should be understood, however, that the CMOS sensor pixel cell 10 may include a photogate, a photoconductor, or other photon-to-charge converting device, in lieu of a pinned photodiode 11 as the initial charge collection region 21.
The pixel cell 10 of FIG. 1 has a transfer transistor with gate 30 for transferring photoelectric charges from the charge collection region 21 to a sensing node 25, typically known as a floating diffusion region. The sensing node 25 is electrically connected to the gate 50 of an output source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 60 for selectively gating the output signal to terminal 32′. A reset transistor having gate 40 resets the sensing node 25 to a predetermined voltage before charge is transferred thereto from the charge collection region 21.
FIG. 2 illustrates a cross-sectional view of a conventionally formed pinned photodiode 11 taken along line 2–2′ of the exemplary CMOS pixel cell 10 of FIG. 1.
The exemplary pixel 10 of FIG. 2 includes pinned photodiode 11 having charge collection region 21 formed within a semiconductor substrate 2. The pinned photodiode 11 has a photosensitive p-n junction region comprising a doped p+ region 4 and a n-type photodiode region 35 within a p-type region 6. The p-type region 6 is formed within semiconductor substrate 2. The two p-type regions 4, 6 cause the n-type photodiode region 35 to be fully depleted at a pinning voltage. Impurity doped source/drain regions 5, 25 having n-type conductivity are provided about the transistor gates 30 and 40. The floating diffusion region 25 adjacent to transfer gates 30, 40 is a common source/drain region for the transfer transistor having gate 30 and the reset transistor having gate 40. FIG. 2 also illustrates optional p-well implant regions 6A and a TEOS oxide spacer layer 95 that is etched to form sidewall spacers 95A.
In a typical CMOS image sensor, trench isolation regions 8 formed in a p-type region 6 and adjacent to the charge collection region 21, are used to isolate adjacent pixels. The order of process steps in forming the various structures of pixel cell 10 may be varied as is required or convenient for a particular process flow.
A transparent insulating layer 99 is typically formed over the pixel cell 10. Conventional processing steps are then carried out to form, for example, metal conductor 15 in the insulating layer to provide an electrical connection/contact to the floating diffusion region 25, and other wiring to connect gate lines and other connections in pixel 10. For example, the entire substrate surface may be covered with a passivation layer of e.g., silicon dioxide, BSG, PSG, or BPSG, as a transparent insulating layer 99, which is planarized and etched to provide contact holes, which are then metallized to provide contacts to diffusion node 25.
In conventional CMOS image sensors, electrons are generated from incident light and are accumulated in the n-type photodiode region 35. These charges are transferred to the floating diffusion region 25 by the gate 30 of the transfer transistor. The source follower transistor 50 produces an output signal from the transferred charges.
A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 35. The maximum output signal increases with increased electron capacitance of the pinned photodiode 11. The electron capacity of the pinned photodiode 11 typically depends on the doping levels and the dopants implanted to form regions 4, 6, 35. In particular, regions 4 and 35 dominate the pinned photodiode's 11 capacitance. Accordingly, increasing the pinned photodiode's 11 capacitance is useful to allow capture of greater levels of photoconverted charges.
One major concern with conventional CMOS image pixels is reducing the generation of dark current. Dark current is generally attributed to leakage in the n-type photodiode region 35, which is strongly dependent on the doping implantation conditions of the photodiode 11. In particular, high dopant concentrations in p-type electrical connection region 23 typically increases dark current.
Other sources of dark current include unwanted electrons from peripheral circuits and electron generation from infrared photons. Dark current is also caused by current generated from trap sites inside or near the photodiode depletion region; band-to-band tunneling induced carrier generation as a result of high fields in the depletion region; junction leakage coming from the lateral sidewall of the photodiode; and leakage from isolation corners, for example, stress induced and trap assisted tunneling.
In CMOS imagers, the design of the photodiode is of particular concern in suppressing dark current. Currently, there are a number of common problems associated with conventionally formed photodiodes, such as the pinned photodiode 11 of FIG. 2. For instance, FIG. 3 illustrates a conventional structure and method of forming the pinned photodiode 11 of FIG. 2, and problems associated with such structure and method.
Conventionally, pinned photodiode 11 is formed after deposition of a spacer insulator oxide layer 95 such as TEOS. For instance, FIG. 3 illustrates deposition of a TEOS oxide spacer layer 95 and resist 96 over the transfer transistor gate 30 and reset transistor gate 40. Next, the pinned photodiode 11 would be formed with a doped p+ region 4 and an n-type region 35. The doped p+ region 4 and the n-type region 35 would be formed by implanting through the TEOS oxide layer 95.
Typically, the doped p+ region 4 was formed by a high energy vertical dose implant which places the doped p+ region 4 near the edge of the transfer gate's spacer 95. This is a fairly high-energy implant requiring an implant energy greater than 20 keV and results in implant straggle i.e., wide distribution in the p-type region profile as a result of oxidation diffusion from subsequent processes.
The n-type region 35 was typically formed with three vertical implants employing phosphorus as the n-type dopant ion. Similar to the formation of the doped p+ region 4, the n-type region 35 would also exhibit implant straggle as a result of oxidation diffusion. The doped p+ region 4 and the n-type region 35 form an area called the critical overlap region 22. This critical overlap region 22, in effect, acts as a barrier at the edge of the transfer gate 30 since the doped p+ region and n-type region 35 are not sharply defined due to diffusion. The critical overlap region 22 reduces the ability of the n-type region 35 to effectively transfer charge to the transfer gate 30.
It is well-known that the transfer gate 30 of a CMOS imager is a critical device for optimization. The transfer gate 30 is influenced by the charge transfer efficiency (CTE) and image lag due to barrier formation. As a result, barriers and wells formed in the photodiode region 11 and transfer gate overlap region 22 affect the CTE which results in image lag. Accordingly, the critical overlap region 22 is important for optimization in four transistor pixel cell designs.
One prior solution for improving the critical overlap region 22 was to vertically implant the doped p+ region 4 implant spaced away from the edge of the transfer gate 30, using the insulator 95 sidewall, thereby reducing the critical overlap region's 22 influence. However, the barrier at the transfer gate's edge 30 still blocked complete charge transfer and photographic images still suffered from low-light image lag. Moreover, diffusion of both doped p+ region 4 and n-type region 35 remained, which is undesirable. Still further, the thickness of insulator 95 also set the transistor gate's 30 spacer thickness. It would be desirable to independently set the transistor spacer width and the spacing of the p+ implant from the transfer gate's edge 30.
Another problem associated with the pinned photodiode 11 of FIG. 3 is that the n-type collection region 35 is typically formed by three deep n-type implants into p-type region 6. These deep implants are conducted with an implant energy of 45 keV, 110 keV and 210 keV, respectively. As a result, the n-type collection region 35 is formed with a long neck 24 (FIGS. 2 and 3). Since the n-type region 35 is formed deep within p-type region 6, transfer gate 30 leakage occurs due to punch-through currents. In essence, the captured electron energy from the n-type collection region 35 moves across the p-type region 6A underneath the transfer gate 30. As a result, the current flow is not completely controlled by the transfer gate 30.
Another problem associated with the conventional pinned photodiode 11 of FIG. 3 is charge capacity loss and variation from sensor to sensor. Charge capacity is the measure of the electrons storage capacity of the photodiode sensor. For instance, the doped p+ region 4 and n-type region 35 interact with each other through diffusion and implant straggle resulting from the high energy implants used to form the regions 4 and 35. This mutual compensation results in photosensor performance variation. In other words, charge capacity loss may occur when a higher concentration of p-type dopants are used in the surface of the pinned photodiode 11 and diffuse into the n-type dopant 35 region, thereby compensating it and causing a reduction in charge capacity. The mutual diffusion and implant straggle result in an uncontrolled implant region at the transfer gate's edge 30 that gives rise to barrier and lag issues.
A final problem associated with the conventional pinned photodiode 11 of FIG. 3 is that the doped p+ region 4 and the n-type region 35 set the pinning voltage (Vpin) of pixel cell 10. The sharpness of the transition from the doped p+ region 4 to the n-type region 35 ultimately sets the capacitance of the photodiode 11. The pinned photodiode 11 has two p-type regions 4, 6 having the same potential so that the n-type collection region 35 is fully depleted at a given Vpin. When the transfer gate 30 is operated, photo-generated charge is transferred from the n-type collection region 35 to the floating diffusion region 25. A complete transfer of charge is possible when a voltage on the floating diffusion region 25 remains above Vpin while the pinned photodiode 11 functions at a voltage below Vpin. An incomplete transfer of charge results in image lag. As a result, due to diffusion, high implant energies, and implant straggle, the n-type region 35 does not have a sharp profile in the substrate but rather a broad one.
There is needed, therefore, an improved active pixel photosensor for use in a CMOS imager that is resistant to dark current, has improved photodiode capacitance, eliminates or reduces barriers at an adjacent gate's edge (such as a transfer gate), eliminates or reduces image lag, and separates the optimization of the photodiode implant locations from the transistor spacer defined locations. Thus, a pinned photodiode structure and its method of formation is needed to reduce or eliminate the problems associated with the pinned photodiodes currently in the semiconductor industry.
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