The present invention relates to a semiconductor device, and more particularly to a resin-encapsulated semiconductor device having a chip structure and a package structure which are well suited for installing an oblong-shaped LSI chip of large size such as, of an elongated rectangular shape, for example, in a small-sized package.
Heretofore, a method of installing an LSI chip in a plastic package has relied on a structure wherein a tab for placing the chip thereon is arranged at the central part of the package, the chip with bonding pad portions arranged at the four lateral sides thereof is bonded and mounted on the tab by the use of a conductive paste, the tip end parts of the leads of a lead frame are arranged along the four lateral sides of the chip, the pad portions and the tip end parts of the leads are interconnected by gold wire pieces, and the resulting assembly is molded with a resin.
With this type of structure, however, the distances between the chip and the tip end parts of the leads must be set far enough so as to allow connection of the gold wire pieces and, as a result thereof, the distance from the outer end of the chip to the outer end part of the package is lengthened, so that the accommodation of a large chip in a small package has become subject to geometrical restrictions. Further, the lengths of the leads buried in the package are small, and inner leads and the resin separate at the boundaries thereof due to mechanical stresses arising during the step of bending the outer leads, so that especially in the direction of the shorter lateral sides of the chip, the pair of short sides of the package have been inevitably designed to be long.
Moreover, since the tab equal in area to the chip is arranged centrally in the package, the peeling of the resin near the boundary and under the chip attributed to a thermal stress, and resulting cracks of the resin extending toward positions below the tab are often incurred. Therefore, the above type of structure could no longer be said to be an appropriate structure which produces satisfactory results in a temperature cycle and during a reflow-proof test.
In order to cope with the problems stated above, a wire bonding structure or a so-called tabless package of the chip-on-lead type has been proposed wherein as disclosed in Japanese Patent Application Laid-open No. 167454/1985, Japanese Patent Application Laid-open No. 218139/1986 and U.S. Pat. No. 4,612,564, the tip ends of the leads of a lead frame which does not require a tab are all arranged on the shorter lateral sides of a chip, an insulator film is adhered on the leads with a binder, the chip is fixed onto the film by die bonding, and the bonding pad portions of the chip and the tip end parts of the leads are interconnected by gold wire pieces.
Further, in order to cope with similar problems, a wire bonding structure or a so-called tabless package of the lead-on-chip type has been proposed wherein as disclosed in Japanese Patent Application Laid-open No. 92556/1984 and Japanese Patent Application Laid-open No. 236130/1986, leads are bonded onto a chip with a binder, and the bonding pads of the chip and the tip end parts of the leads overlying the chip are interconnected with pieces of gold wire or the like.
USPTO Backgrounds
USPTO Backgrounds