1. Field
Various features relate to a high quality factor inductor implemented in wafer level packaging (WLP).
2. Background
Inductors that are located in integrated circuit (IC) packages are limited in their capabilities for supporting high current due to the limited real estate in IC packages. Specifically, since these inductors are located in the packaging substrate of IC packages, the size of these inductors is limited by the size of the packaging substrate of IC packages. As a result of the restricted space in the packaging substrate of IC packages, these inductors typically have a high resistance and a low quality (Q) factor. FIG. 1 conceptually illustrates a semiconductor device that includes an inductor. Specifically, FIG. 1 illustrates a die 100, a packaging substrate 102, a set of solder balls 104, a printed circuit board (PCB) 106, and an inductor 108. As shown in FIG. 1, the die 100 is coupled to the packaging substrate 102. The packaging substrate 102 is coupled to the PCB 106 through the set of solder balls 104. The inductor 108 is defined and located in the die 100.
FIG. 1 also illustrates that some solder balls have been omitted/removed in a region near the inductor 108. This is because solder balls can affect/disrupt the performance of an inductor. More specifically, solder balls that are near an inductor can disrupt the magnetic flux of an inductor, resulting in a low inductance and low Q factor for the inductor, which is why solder balls are removed in a region near an inductor. However, removing solder balls between a packaging substrate and a PCB can affect the structural stability of the packaging substrate and the PCB. Thus, current IC design must weigh the benefit of removing solder balls (e.g., better inductance and Q factor inductor) versus the disadvantage of removing solder balls (e.g., less stable packaging substrate/PCB structure), when determining how many solder balls to use and where to put solder balls when coupling a die and packaging substrate to a PCB.
Therefore, there is a need for an improved inductor design for semiconductor devices. Ideally, such an inductor will have better inductance performance, lower resistance and better quality factor value, without having to sacrifice the structural stability of the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds