1. Field of the Invention
The present invention relates to the field of static random access memories (RAMs). More specifically, the present invention relates to reading and sensing the contents of a static RAM cell.
2. Background Art
According to one known technique in static RAM arrays, in order to access and read two RAM cells, two read cycles are required. Referring to FIG. 1, two conventional and identical RAM cells 12 are shown in FIG. 1. Each RAM cell 12 consists of inverters 14 and access transistors 16. Access transistors 16 are driven by word lines 28. Complementary bit lines 24 and 26 are driven by RAM cells 12 and access transistors 16. Differential sense amp 20 receives its two inputs from complementary bit lines 24 and 26. Output 22 of differential sense amp 20 indicates whether a "1" or a "0" has been read from the particular RAM cell accessed by a particular word line 28.
RAM cells 12 are accessed and read using a conventional technique. During each read cycle, a single word line 28 is enabled (i.e., driven high). That single enabled word line turns on the two access transistors 16 belonging to a single RAM cell. When the two access transistors are turned on, one of the bit lines 24 or 26 is driven high while the other bit line is driven low (if the bit lines had been precharged in a previous clock cycle, one of the bit lines remains high while the other one goes low). The difference in voltage between the two bit lines 24 and 26 is detected by differential sense amp 20 and outputted on line 22. From the above explanation it is apparent that two read cycles are necessary in order to read from two different RAM cells. In other words, during each read cycle only a single RAM cell can be accessed and read.
A known improvement over the conventional technique of FIG. 1 is shown in FIG. 2. According to the improved RAM design shown in FIG. 2, two different RAM cells can be accessed and read simultaneously during a single read cycle. RAM cells 32 are identical and each consists of inverters 34 and access transistors 36. In each RAM cell, one access transistor 36 is driven by word lines 38 while the other access transistor 36 is driven by word lines 39. In order to access each RAM cell 32 only one of word lines 38 or 39 need be enabled. In fact, the word line drivers (not shown in any of the Figures) operate such that when word line 38 of a particular RAM cell is high, word line 39 of that same RAM cell is driven low (and vice versa, i.e. if word line 38 is low, word line 39 is driven high). Accordingly, during each read cycle, only one of the two access transistors 36 in a RAM cell of interest is enabled.
A precharge circuit consisting of transistor 42 is used so that when precharge signal 40 is high, the bit lines are precharged prior to the beginning of a read operation. The precharge voltage is between 2.0 volts and 4.0 volts corresponding to a supply voltage between 3.0 volts and 5.0 volts. During a single read cycle, while word line 38 of a particular RAM cell is enabled, word line 39 of a different RAM cell can be enabled. Referring to FIG. 2, while word line 38 of the top RAM cell is enabled, during the same read cycle, word line 39 of the bottom RAM cell is enabled. Thus, while the top RAM cell in FIG. 2 drives bit line 46, the bottom RAM cell drives bit line 44. Sense amp 56 detects any change in the voltage of bit line 46 while sense amp 54 detects changes in the voltage of bit line 44. Sense amp 56 provides the result of the read operation of the top RAM cell on output 57 while sense amp 54 provides the results of the read operation of the bottom RAM cell on output 55. It is apparent that according to the known technique described in relation to FIG. 2, during a single read cycle two different RAM cells can be simultaneously accessed and read.
It is noted that in both the conventional RAM designs shown in FIGS. 1 and 2, the sense amps are designed to work with large precharge voltages, i.e. precharge voltages of 2.0 volts and above. Moreover, the precharge circuits of the conventional RAM arrays typically produce a relatively noisy precharge voltage. Since the relatively noisy output of the conventional precharge circuits appears directly on the bit lines, the sense amps used in conventional RAM arrays cannot be designed to be very sensitive to voltage fluctuations on the bit lines.
The conventional RAM cells described in relation to FIGS. 1 and 2 and their resulting RAM arrays suffer from several shortcomings. One shortcoming of the conventional RAM arrays is that the time it takes to read data from an accessed RAM cell is too long. In other words, the time it takes for the RAM cell to cause a change in the voltage of a bit line and the time it takes for the change in the bit line voltage to be detected by the sense amp are both too long. Another shortcoming of the conventional RAM arrays is that their sense amps do not work well with low bit line voltages and, moreover, the sense amps do not readily detect very small changes in the bit line voltage. Still another shortcoming of the conventional RAM arrays is that the conventional precharge circuits that are designed to precharge RAM bit lines to a low voltage are complicated and further the precharge circuits do not provide a substantially noiseless precharge voltage.
Thus, there is serious need in the art for a RAM cell and a RAM array design that utilizes stable and substantially noiseless and low bit line precharge voltages. There is also a need for simple precharge circuits that can generate substantially noiseless and low bit line precharge voltages. Moreover, there is need in the art to reduce the time it takes for an accessed RAM cell to cause a change in the bit line voltage and there is further need to reduce the time it takes for small changes in the bit line voltage to be detected by the RAM array sense amps.
USPTO Backgrounds
USPTO Backgrounds