1. Technical Field
This disclosure relates to microprocessors, and more particularly to techniques for ordering loads with respect to other loads in a weakly-ordered out-of-order processor.
2. Description of the Related Art
Modern out-of-order processors are often configured to execute load and store instructions out-of-order, and also permit loads to access memory in a speculative manner. Speculatively-executed loads and stores are typically held in queues until necessary criteria is met to make the loads and stores architecturally visible (i.e., visible to software). In a multi-processor environment, the order rules of memory accesses by various processors is defined by the memory consistency model specified by a given instruction set architecture (ISA). The weakly-ordered model is one such memory consistency model.
The “load-load” ordering rule is one common requirement of even weakly-ordered models. Loads to the same memory address must be ordered with respect to each other, such that a younger load instruction never reads an “older” value of data from a given memory address when an older load to the same address reads a “newer” value.
USPTO Backgrounds
USPTO Backgrounds