(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a molded semiconductor device package.
(2) Description of the Prior Art
For the packaging of semiconductor devices frequent use is made of methods of encapsulation of the devices in packages that are aimed at further usage. These packages have to meet requirements of high speed processing environments and are therefore heavily influenced by such considerations as cost, usability, quality, ease and repeatability of manufacturing, throughput and others.
One of the more commonly used molding materials that is used for the purpose of creating an encapsulated semiconductor device package is resin. Resins occur freely in a natural environment, industrially applied resins are synthetically prepared and can be created with many properties that are of value for a given application. Synthetic resins (such as alkyd resins or phenolic resins) usually have high molecular weight and may have some of the properties of natural resins. Synthetic resins however are typically very different from natural resins. Synthetic resins may be thermoplastic or thermosetting, they can be made by polymerization or by condensation, and they are used mostly as plastics or the essential ingredients of plastic, in varnishes or other coatings, in adhesives and in ion exchange.
In the semiconductor industry, resins are frequently molded into particular forms or shapes that are used to house or package semiconductor chips. These completed molds then serve as chip carriers and may contain parts within the mold that facilitate or enable this function such as a die pad (to position the chip onto), metal extensions (lead fingers) that serve to interconnect the packaged chip with its surrounding electrical environment and means (such as wire bonding) for connecting the chip to metal extensions.
It is thereby also common practice to adapt plastic or resin chip carriers to a high speed semiconductor manufacturing environment, for the main reason that this is the predominant environment that is being used to produce high volumes of semiconductor chips at a competitive price. The chip carriers must thereby also be adaptable to a variety of chip sizes, again to make the chip carrier acceptable from a cost point of view. To adapt the chip carrier to a high-speed manufacturing environment, the design must be such that no parts of the carrier can interfere with the manufacturing process due to protruding parts of the carrier. This could cause deformation of the protruding parts in addition to slowing down the manufacturing process due to the required intervention to remove the offending carrier.
A mold cavity frequently consists of two sections, an upper section and a lower section. The lower section forms, after molding, the support for mounting the chip and for supporting lead fingers. These supporting components are inserted in the lower mold prior to the formation of the pre-molded plastic chip carrier.
In addition to the above considerations relating to the creation of a mold, considerations of adhesion between the epoxy mold compound and the substrate of the package play an important role in the creation of a mold-packaged semiconductor device. This concern applies to the four corners and the edges of the mold cap where stress concentrations are most likely to occur, a stress that is highly temperature dependent. Present practices to alleviate the impact of corner stress focus on substrate cleanliness, achieved by for instance surface plasma treatment, and by matching the stress related properties of physically interfacing elements of the package. Stress related adverse impact on the overall package is typically and most likely concentrated at the most exposed or weakest points of the mold cap. The invention addresses these concerns of mold cap creation and reliability.
USPTO Backgrounds
USPTO Backgrounds