In the semiconductor technology, the focus of research is shifted to a three dimensional (3D) device structure, in order to realize a full-depletion device. A 3D structure is constructed by forming a semiconductor fin (for forming a channel) on a semiconductor on insulator (SOI), forming a channel region at the middle of the semiconductor fin, forming a gate on the sidewalls of the semiconductor fin, and forming source/drain regions at both ends of the semiconductor fin.
Currently, dual fin structures appear in the 3D device structure, namely, two parallel semiconductor fins are formed on the SOI, and the two parallel semiconductor fins are taken as fin channels to form two independent semiconductor devices, wherein respective gates are formed on the sidewalls of the two semiconductor fins that are far away from each other, while the sidewalls of the two semiconductor fins that are opposite to each other are exposed. Thus, it is desirable to perform a processing to the exposed sidewalls of the two semiconductor fins, to thereby enhance the performance of the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds