This invention relates to the provision of both fixed logic portions and programmable logic portions on the same integrated circuit device. More particularly, this invention relates to a method for constructing an integrated circuit device having both fixed logic portions and programmable logic portions, as well as to a programmable logic architecture that is particularly adapted for use with such a method.
Programmable logic devices (PLDs) are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configurations may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up table-type logic operations. At some point, such devices began to be provided with embedded blocks of random access memory that could be configured by the user to act as random access memory, read-only memory, or logic (such as P-TERM logic).
PLDs allow a user to programmably create—e.g., using a personal computer with suitable software and a peripheral hardware device into which a PLD chip can be inserted—an integrated circuit device having any desired logic arrangement (within the limits of the PLD itself). In order to provide flexibility in logic design, traditional PLDs typically have a substantially rectilinear arrangement of programmable logic areas arranged generally in rows and columns. Interconnect resources are also provided, frequently including a substantially rectilinear arrangement of conductors aligned generally horizontally and vertically between the rows and columns of programmable logic areas. Connections among these conductors, and between the conductors and the programmable logic areas, are typically programmable, and sufficient conductors are provided, along with sufficient connections among them, and between them and the programmable logic areas, so that by programming those connections a signal can be conducted from any programmable logic area to or from any other programmable logic area or input/output area, as desired in order to implement a particular logic design.
Because of cost and speed penalties associated with early PLDs, those early PLDs typically were used to prove a logic design before committing it to silicon as a custom integrated circuit device for large-scale production. However, as costs decreased and speeds increased, PLDs began to be used in final products in place of custom integrated circuits. In some applications, however, it is desirable to have a single integrated circuit device that is partially fixed logic and partially programmable logic.
For example, a manufacturer of cellular telephones may provide different variants of a certain model of cellular telephone for use with different transmission standards (e.g., TDMA and CDMA). Those different variants of the same model of telephone will have certain logic that is common among the variants, and certain logic that differs from one variant to the other. One solution is to provide, in all variants of that model of telephone, an integrated circuit device having a fixed logic portion and one or more programmable logic portions that can be programmed to provide those logic portions that differ among the variants.
In order to produce such a hybrid integrated circuit device, custom logic is designed and laid out, and then a design for a programmable logic portion is produced or obtained and laid out in one or more available locations on the integrated circuit device. One drawback to this approach is that once the hybrid device has been designed, the programmable logic portion or portions are fixed in size, number and location on the device. This may require a user to use a device having more programmable logic than necessary to implement a certain design, or may require more than one variant of the device—e.g., containing different numbers of programmable logic regions—to be designed and maintained in inventory.
It would be desirable to be able to streamline the process of creating such hybrid integrated circuit devices so that it is not necessary to use a device having more programmable logic than necessary, or to maintain large inventories of different devices.
USPTO Backgrounds
USPTO Backgrounds