CMOS technology embodied as a high performance, low-power chip, has been widely used in electronic devices because of its scaleable. However, continuing this CMOS performance trend has become extremely difficult because the industry is approaching the fundamental physical limits of CMOS scaling. For this reason, the semiconductor industry has been aggressively seeking new ways to make electric charges move faster through device channels so as to increase circuit speeds and reduce power consumption.
It has been found that a way to improve CMOS performance is to increase the mobility of its positive charges, or holes, through the device channels. For PFETs, hole mobility is known to be 2.5 times higher on (110) surface-orientation compared to that on standard wafer with (100) surface-orientation. To increase hole and electron mobility, the industry has tried to incorporate Ge materials into the semiconductor processing methodologies; however, the presence of Ge causes material and process integration challenges to the semiconductor manufacturer.
More specifically, Ge has been used as a channel material to enhance electron and hole mobility for both NFET and PFET devices. However, due to the low melting point of Ge (e.g., about 938° C.), it has a tendency to fluidize during normal annealing processes, which take place at about 1000° C. This, in turn, affects the properties and characteristics of Ge and hence the device. Also, it is difficult to form an oxide on Ge, compared to Si. Moreover, the dopant diffusion of Ge is very fast and, as such, it becomes very difficult to control the dopant profiles in the source and drain regions, as well as in the halo regions. For these and other reasons, Ge has not been integrated to standard silicon technology.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds