When serial communication is performed between ports in a plurality of lanes, a transmission circuit of a connection source port divides transmission data into the number of lanes, and transmission of the divided pieces of data is performed in the lanes, respectively. A reception circuit of a connection destination port restores the pieces of data that are received in the lanes.
FIG. 1 is a configuration diagram of a conventional reception circuit.
FIG. 1 is the configuration diagram of the reception circuit that uses two lanes (a lane 0 and a lane 1).
A reception circuit 10 includes SERializer/DESerializer (SerDes) 11-i (i=0 to 1), cyclic redundancy check (CRC) checking units 12-i, dual port random access memories (RAM) 13-i, write pointers 14-i, and a read pointer 15.
The SerDes 11-i, the CRC checking units 12-i, the dual port RAM 13-i, and the write pointers 14-i process data of the lanes i.
The SerDes 11 is a circuit that performs interconverts between serial data and parallel data. In the reception circuit 10, the SerDes 11 converts the received serial data into parallel data.
The CRC checking unit 12 performs error checking of data using CRC.
The dual port RAM 13 is a storage device that stores data. The dual port RAM 13 writes data to a position that is indicated by a write pointer value, and reads data from a position that is indicated by a read pointer value.
The write pointer 14 transmits a write pointer value that indicates a writing position of data to the dual port RAM 13.
The read pointer 15 transmits a read pointer value that indicates a reading position of data to the dual port RAM 13. The read pointer 15 transmits a read pointer value to the dual port RAM 13 so that skews of the lanes are matched. Therefore, pieces of data in which skews are matched between the lanes are output from the dual port RAM 13.
In a conventional reception circuit, when any error is detected in the CRC checking unit for data that is received in the SerDes, the data becomes invalid, and write pointer value are different between the lane because a write pointer value stops in the middle.
Thus, conventionally, clear of a dual port RAM, a write pointer, and a read pointer is performed by reset, and transfer is performed again.
Conventionally, reset is performed at the time of occurrence of errors, and in a time period of the reset, reduction of performance is caused because regular transfer is not performed.    [Patent Document 1] Japanese Laid-Open Patent Publication No. 2002-223203    [Patent Document 2] Japanese Laid-Open Patent Publication No. 2002-7312
USPTO Backgrounds
USPTO Backgrounds