1. Field of the Invention
The present invention relates to a power semiconductor device, and particularly to an insulated gate semiconductor device favorably used as a power switching element.
2. Description of the Related Art
In recent years, power supply devices used in the power electronics field are strongly required to be more compact with higher performance. In accordance with this demand, power semiconductor devices have been improved to operate with lower loss and fewer noises, as well as higher breakdown voltage and larger electric current. Under the circumstances, an IEGT (Injection Enhanced Gate Transistor) obtained by improving an IGBT (Insulated Gate Bipolar Transistor) is attracting attention as a device, which can reduce the turn-off loss, as well as reducing the on-state voltage (for example, Jpn. Pat. Appln. KOKAI Publication No. 5-24356; Jpn. J. Appl. Phys. Vol. 36 (1997) pp. 3433–3437, ISSCC 2000 Digest Paper TA7.2; and M. Kitagawa et al., “A 4500V Injection Enhanced Insulated Gate Bipolar Transistor (IEGT) in a Mode Similar to a Thyristor”, IEDM '93, pp. 679–682, 1993).
FIG. 25 is a sectional view showing a conventional IEGT having a trench structure. As shown in FIG. 25, on one side of an n-base layer 101, an n-buffer layer 102 is disposed, and a p-collector layer 103 is further disposed thereon. On the other side of the n-base layer 101, a plurality of trenches 104 are formed at intervals in the n-base layer 101, such that main cells MR and dummy cells DR are alternately partitioned.
In each of the main cells MR, a p-base layer 107 is disposed on the n-base layer 101. N-emitter layers 108 are formed in the surface of the p-base layer 107. In each of the dummy cells DR, a p-buffer layer 109 is disposed on the n-base layer 101. Dividing a common p-layer by the trenches 104 forms the p-base layers 107 and p-buffer layers 109.
A collector electrode 111 is disposed on the p-collector layer 103. An emitter electrode 112 is disposed on the p-base layer 107 and n-emitter layers 108. A gate electrode 106 is buried in each of the trenches 104, while it is wrapped in a gate insulating film 105. As a consequence, an n-channel MOSFET is formed in the main cell MR, such that it selectively connects the n-emitter layer 108 to the n-base layer 101, using the p-base layer 107 as a channel region, to inject electrons.
In the sectional view shown in FIG. 25, the surface of the p-buffer layer 109 in each of the dummy cells DR is covered with an insulating film 110. However, in order to fix the potential of the p-buffer layer 109, a part of the emitter electrode 112 is also disposed on the p-buffer layer 109 at a position not shown in FIG. 25. The density of the part of the emitter electrode 112 disposed on the p-buffer layer 109 is small, so that the resistance between the p-buffer layer 109 and emitter electrode 112 is equivalently large.
In this IEGT, each of the main cells MR forms a narrow current passage connecting the n-base layer 101 to the emitter electrode 112. In the on-state of the IEGT, this arrangement provides an increase in resistance against the flow of holes from the n-base layer 101 into the emitter electrode 112 through the p-base layer 107 in the main cell MR, thereby restricting the holes being exhausted into the emitter electrode 112. As a consequence, the injection efficiency of electrons from the n-emitter layers 108 into the n-base layer 101 improves, thereby promoting conductivity modulation of the n-base layer 101, resulting in a low on-state voltage.
A CSTBT (Carrier Stored Trench-Gate Bipolar Transistor) has also been proposed as a power semiconductor device, which can reduce the on-resistance as in the IEGT (for example, H. Takahashi et al., “Carrier Stored Trench-Gate Bipolar Transistor (CSTBT)—A Novel Power Device for High Voltage Application” ISPSD '96, pp. 349–352, 1996). FIG. 26 is a sectional view showing a conventional CSTBT.
As shown in FIG. 26, on one side of an n-base layer 131, a p-collector layer 133 is disposed. On the other side of the n-base layer 131, an n-barrier layer 132 having an impurity concentration higher than that of the n-base layer 131 is disposed. A p-base layer 137 is disposed on the n-barrier layer 132. N-emitter layers 138 are formed in the surface of the p-base layer 137. A plurality of trenches 134 are formed at intervals such that they extend from the substrate surface into the n-base layer 131.
A collector electrode 141 is disposed on the p-collector layer 133. An emitter electrode 142 is disposed on the p-base layer 137 and n-emitter layers 138. A gate electrode 136 is buried in each of the trenches 134, while it is wrapped in a gate insulating film 135. As a consequence, an n-channel MOSFET is formed such that it selectively connects the n-emitter layer 138 to the n-base layer 131, using the p-base layer 137 as a channel region, to inject electrons.
In this CSTBT, the n-barrier layer 132 having a high impurity concentration provides a large resistance against flow of holes. In the on-state of the CSTBT, this arrangement provides an increase in resistance against the flow of holes from the n-base layer 131 into the emitter electrode 142 through the p-base layer 137, thereby restricting the holes being exhausted into the emitter electrode 142. As a consequence, the injection efficiency of electrons from the n-emitter layers 138 into the n-base layer 131 improves, thereby promoting conductivity modulation of the n-base layer 131, resulting in a low on-state voltage.
The conventional IEGT and CSTB, used as power semiconductor devices, have the advantage of providing a low on-state voltage. However, these conventional power semiconductor devices have a problem causing a large noise in switching, and especially being turned on, as described above. In addition, since the resistance against holes being exhausted is high, a problem arises in that a period of time (storage period) for a depletion layer to extend up from the start of voltage rising is prolonged when the devices are turned off. This increases the turn-off loss, as well as the turn-off time.
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