1. Field of the Invention
This invention relates generally to data receivers and in particular to a data receiver for communications between devices running at different clock frequencies or clock phases.
2. Description of the Related Art
In a digital electronic system, devices within the system must communicate with other devices. FIG. 1 shows a simple digital system containing a data transmitter 110 and a data receiver 120. Data transmitter 110 sends digital data in a data stream D to data receiver 120 over data lines 130. In some systems, data transmitter 110 and data receiver 120 exchange control signals over control lines 140. Data transmitter 110 and data receiver 120 can be for example, different parts of a single VLSI IC, two IC's in a system, a storage device and a computer system, two independent systems, or a digital signal processor of a CD-ROM and a CD-ROM controller chip.
If data transmitter 110 and data receiver 120 are clocked at the same phase and frequency, the transmission of data between data transmitter 110 and data receiver 120 is straight forward. However, in situations where data transmitter 110 and data receiver 120 are clocked at different phases or frequencies, data receiver 120 must capture data stream D off of data lines 130 and synchronize data stream D to the phase and frequency of data receiver 120.
A conventional solution to capture data stream D from data line 130 to the phase and frequency of data receiver 120 is to use a dual ported FIFO (not shown) in data receiver 120. One port of the dual ported FIFO is clocked by data transmitter 110 to store the data stream from data lines 130. The other port of the dual ported FIFO is clocked by data receiver 120 when data is read from the dual ported FIFO. However this solution requires a potentially expensive memory structure to be added to data receiver 120. Furthermore, a clock signal or data write signal synchronized with data stream D from data transmitter 110 must accompany the data. Therefore, in situations where data transmitter 110 does not provide a synchronized write or clock signal to data receiver 120, the conventional solution of using a dual ported FIFO is not feasible.
Hence there is a need for a method or apparatus to capture data from data transmitter 110 for use with data receiver 120, when data transmitter 110 and data receiver 120 are clocked at different phases or frequencies. Furthermore, the method or apparatus should be able to capture the data even if data transmitter 110 does not provide a clock or write signal to data receiver 120.
USPTO Backgrounds
USPTO Backgrounds