1. Field of the Invention
The present invention relates generally to methods for protecting semiconductor integrated circuits against mechanical stress or chemical agents and, more particularly, to methods for forming a passivation layer on such circuits to provide such protection.
2. Discussion of the Related Art
Semiconductor integrated circuits (hereafter referred to as chips) manufactured with Large Scale Integration technologies (LSI, VLSI, ULSI, and the like) typically are covered by a protective layer to protect against mechanical stress and aggressive chemical agents. This protective layer, referred to herein as the final passivation layer, typically is formed of silicon-based dielectric materials, such as silicon dioxide (USG), phosphorus-doped or fluorurate-doped silicon oxide (PSG or FSG), silicon nitrides and nitride oxides (SiOxNy, Si3N4).
The final passivation layer is conventionally formed by use of Chemical Vapor Deposition (CVD) techniques, either the plasma-enhanced CVD technique (PECVD) or the atmospheric pressure CVD technique (APCVD). The top surface of the final passivation layer formed by conventional techniques generally is not planar, having protrusions and depressions caused by gaps in the underlying layers (for example, gaps between metal lines of the uppermost metal interconnection layer). Such a non-planar top surface is disadvantageous because, when the chip is encapsulated in a package, the mechanical stress exerted by the package on the chip generally is not uniformly distributed over the top surface of the final passivation layer. Such non-uniform distribution of stress can lead to cracks in the final passivation layer, through which chemical agents or water molecules can penetrate and reach the underlying layers of the chip.
Therefore, what is needed is a method for protecting chips against such cracking due to non-uniform distribution of stress over the top surface of the final passivation layer.
USPTO Backgrounds
USPTO Backgrounds