(a) Field of the Invention
The present invention relates to an EEPROM cell. More particularly, the present invention relates to an EEPROM cell into which a transfer gate is inserted to reduce instability of data that is stored at the EEPROM cell during a standby operation thereof.
(b) Description of the Related Art
An electrically erasable programmable read-only memory (EEPROM) is a kind of a programmable read-only memory (PROM), and is a ROM that improves a drawback of an erasable programmable read-only memory (EPROM) that can erase contents when radiating ultraviolet rays. The EEPROM erases internal data by applying an electrical signal to a pin of a chip.
Such an EEPROM is a non-volatile storage element and is currently used for a system-on-chip (SoC) or a radio frequency identification (RFID) tag. In this case, the EEPROM has various capacities from tens of bytes to several gigabytes according to usage of a product, and particularly, when the EEPROM is used for RFID, the EEPROM should have good adherence and thus the EEPROM needs a high density and super down-sizing of a chip, and should also have a good economical efficiency.
In order to achieve the above purposes, the EEPROM needs to operate only as a complementary metal-oxide semiconductor (hereinafter, referred to as ‘CMOS’) element. When the CMOS element is not used in the EEPROM, an array of the EEPROM and a design rule of a related circuit increase, a control circuit of a chip should be manually designed, and design contents should be constructed with hard intellectual property (IP), and even if a design is changed a little, there is a problem that recycling of the EEPROM is impossible.
However, in a process at 65 nm or lower, when a CMOS element is used and an array of an existing EEPROM cell is applied, a control operation of an element becomes unstable. However, for stability of a control operation, when an array of the EEPROM cell is newly designed, an outside line is separately added and thus a control operation becomes complicated.
In order to solve a problem in the above process at 65 nm or lower, by forming a tunneling oxide film to a size of 26 Å or lower, a method of reducing a cell area of the EEPROM and simplifying a peripheral control circuit was suggested, but there is a problem that a disturbance phenomenon in which data that has been previously programmed for programming erasing standby time is erased occurs.
USPTO Backgrounds
USPTO Backgrounds