1. Technical Field
The present invention relates to data input/output circuits and methods of a semiconductor memory apparatus, in particular, to a data input/output circuit and method of a semiconductor memory apparatus that is capable of decreasing the number of global input/output lines.
2. Related Art
As semiconductor memory apparatuses migrate from SDRAM (Synchronous DRAM) into a DDR (Double Data Rate)/DDR (Double Data Rate) 2, an operation method that reads or writes data corresponding to a minimum burst length at one time for every data input/output buffer according to one read or write command in order to cope with the high frequency operation is used, which is referred to as N bit prefetch (in this case, N is the same as the minimum burst length).
For example, in the case of the DDR, the minimum burst length is 2, and 2 bit prefetch that reads or writes 2 bit data at one time for every data input buffer DQ is used. In the case of the DDR2, the minimum burst length is 4, and 4 bit prefetch that reads or writes 4 bit data at one time for every data input buffer is used.
Hereinafter, a circuit and method of inputting and outputting data of a semiconductor memory apparatus according to the related art will be described with reference to the accompanying drawing.
FIG. 1 is a block diagram of a data input/output circuit of a semiconductor memory apparatus according to the related art.
The data input/output circuit of the semiconductor memory apparatus according to the related art includes a data input/output buffer 100, a first data input/output unit 200, a first control unit 300, a second data input/output unit 400 and a second control unit 500.
The data input/output buffer 100 outputs read data to outside of the semiconductor memory apparatus or inputs write data from outside to the inside of the semiconductor memory apparatus. The first data input/output unit 200 transmits the data to be written (hereinafter write data) from the data input/output buffer 100 to a global input/output line GIO, or transmits the data to be read (hereinafter read data)_from the global input/output line GIO to the data input/output buffer 100, in response to a first control signal CTRL1. The first control unit 300 outputs the first control signal CTRL1. The second data input/output unit 400 transmits the write data from the global input/output line GIO to a local input/output line LIO, or transmits the read data from the local input/output line LIO to the global input/output line GIO, in response to a second control signal CTRL2. The second control unit 500 outputs the second control signal CTRL2.
The read data refers to data read from a memory cell during a read operation, and the write data refers to data input from the data input/output buffer during a write operation.
FIG. 2 is a block diagram of the data input/output buffer 100, the first data input/output unit 200, and the first control unit 300.
The first data input/output unit 200 includes a plurality of latch units 210-0 to 210-7, a plurality of input drivers 230-0 to 230-7, a pipe latch unit 250, and an output driver 270. The plurality of latch units 210-0 to 210-7 latch the write data input in series from the data input/output buffer 100 to output in parallel, in response to input control signals IN_CTRLO to IN_CTRL7 and an output control signal OUT_CTRL. The plurality of input drivers 230-0 to 230-7 output signals from the plurality of latch unit 210-0 to 210-7 to the global input/output lines GIO0 to GIO7 in response to an input driver control signal IN_DRV_CTRL. The pipe latch unit 250 receives the read data input in series from the global input/output lines GIO0 to GIO7. The output driver 270 outputs the read data output in parallel from the pipe latch unit 250 to the data input/output buffer 100.
The latch unit 210-i includes an input unit 211-i and an output unit 213-i. The input unit 211-i receives the write data in response to the input control signal IN_CTRLi. The output unit 213-i latches the write data input in the input unit 211-i to output to the input driver 230-i in response to the output control signal OUT_CTRL. In this case, i is an integer between 0 and 7.
The first control unit 300 outputs the input control signals IN_CTRL0 to IN_CTRL7, the output control signal OUT_CTRL and the input driver control signal IN_DRV_CTRL. The input control signals IN_CTRL0 to IN_CTRL7 control the input units 211-0 to 211-7 so that the input units 211-0 to 211-7 operate at different timings. The output control signal OUT_CTRL controls the output units 213-0 to 213-7 so that the output units 213-0 to 213-7 operate simultaneously. The input driver control signal IN_DRV_CTRL controls the input drivers 230-0 to 230-7 so that the input drivers 230-0 to 230-7 operate simultaneously.
FIG. 3 is a block diagram of the second input/output unit 400 and the second control unit 500 of the data input/output circuits shown in FIG. 1.
The second data input/output unit 400 includes a plurality of write drivers 410-0 to 410-7, a plurality of input/output sense amplifiers 430-0 to 430-7 and a plurality of read drivers 450-0 to 450-7. The plurality of write drivers 410-0 to 410-7 output the write data of the global input/output lines GIO0 to GIO7 to the local input/output lines LIO0 to LIO7 and LIOb0 to LIOb7 in response to a write driver control signal WT_DRV_CTRL. The plurality of input/output sense amplifiers 430-0 to 430-7 compare and amplify potentials of the read data of the local input/output lines LIO0 to LIO7 and LIOb0 to LIOb7 to output the results. The plurality of read drivers 450-0 to 450-7 output read data from the input/output sense amplifiers 430-0 to 430-7 to the global input/output lines GIO0 to GIO7 in response to a read driver control signal RD_DRV_CTRL.
The second control unit 500 outputs the read driver control signal RD_DRV_CTRL and the write driver control signal WT_DRV_CTRL. The read driver control signal RD_DRV_CTRL control the read drivers 450-0 to 450-7 so that the read drivers 450-0 to 450-7 are simultaneously operated. The write driver control signal WT_DRV_CTRL control the write drivers 410-0 to 410-7 so that the write drivers 410-0 to 410-7 are simultaneously operated.
The data input/output circuit is an example that is implemented in a semiconductor memory apparatus using an 8 bit prefetch.
FIG. 4 is a timing chart of a write operation of the input/output circuit shown in FIGS. 2 and 3.
When a write command WRITE0 or WRITE1 is input to the semiconductor memory apparatus, the input units 211-0 to 211-7 receive the write data from the data input/output buffer 100 in response to the input control signal IN_CTRL. The output units 213-0 to 213-7 simultaneously output the write data to the input driver 230-0 to 230-7 in response to the output control signal OUT_CTRL at a timing when the last data (for example, eighth data in the case of 8 bit prefetch) is input to the input unit 211-7. The input drivers 230-0 to 230-7 simultaneously output the write data to the global input/output lines GIO-0 to GIO-7 connected to the input drivers 230-0 to 230-7 at a rising timing of the clock signal CLOCK in response to the input driver control signal IN_DRV_CTRL. In this case, the write data changes the potential of the bit line through the write drivers 410-0 to 410-7 that operate in response to the write driver control signal WT_DRV_CTRL and the local input/output lines LIO0 to LIO7, and LIOb0 to LIOb7. The bit line sense amplifier finally stores the write data in memory cells.
FIG. 5 is a timing chart of a read operation of the data input/output circuit shown in FIGS. 2 and 3.
As shown in FIG. 5, after a read command READ0 or READ1 is input to the semiconductor memory apparatus, the input/output sense amplifiers (IOSA) 430-0 to 430-7 simultaneously operate to receive the read data from the local input/output lines LIO0 to LIO7, and LIOb0 to LIOb7, and the read drivers 450-0 to 450-7 simultaneously operate to transmit data the pipe latch unit 250 though the global input/output lines GIO-0 to GIO-7. The pipe latch unit 250 stores eight data and is synchronized with the clock signal CLOCK at a predetermined output timing to sequentially output the read data, and the output driver 270 outputs the read data to the data input/output buffer 100.
However, as described above, since the number of data that is simultaneously input to one data input/output buffer (DQ) 100 is eight, the same number of input drivers 230-0 to 230-7, write drivers 410-0 to 410-7, input/output sense amplifiers 430-0 to 430-7, read drivers 450-0 to 450-7, and global input/output lines GIO-0 to GIO-7 is required. Further, as the bit number of used prefetches is increased, the number of global input/output lines to the data input/output buffers (DQ) 100 is accordingly increased. For example, in the case of a semiconductor memory apparatus in which data is input/output to and from 16 data input/output buffers DQ from the outside of the DRAM, a total of 128 global input/output lines GIO with respect to the 8 bit prefetches and the 16 data input/output buffers DQ should be used. Further, considering development trends in semiconductor memory apparatuses, the semiconductor memory apparatus will use a larger number of prefetches needs 256 global input/output lines, which causes an increase in the total area of chips.
USPTO Backgrounds
USPTO Backgrounds