Use of an interrupt mechanism provided with a plurality of priority levels is an extremely powerful and important technology for swiftly coping with interrupt processing at a very high rate of urgency from within a program for processing a large number of interrupt causes. In the same manner, a vector interrupt mechanism whereby an interrupt reception bus cycle is executed, an interrupt vector for identifying the device requesting interrupt processing is input, and branching to a processing routine corresponding to the interrupt main cause received from this vector value occurs, after an interrupt is received, is also an important technology.
These interrupt mechanisms are currently provided in most high performance microprocessors. When an interrupt vector is not introduced into an interrupt reception bus cycle it is not possible to specify the device requesting the interrupt. In order to specify the device requesting the interrupt within the interrupt process program these devices must be polled, one at a time. This is extremely time-consuming, therefore the response time for handling an interrupt is greatly increased.
The above-mentioned interrupt mechanism provided with a plurality of priority levels and the vector interrupt mechanism, for example, are contained in the 68000 microprocessor manufactured by the Motorola Company. A general outline of the response procedures in a data processing device with a 68000 microprocessor is as follows.
(1) Interrupt request is received. PA1 (2) Interrupt receipt bus cycle (interrupt acknowledge cycle) is executed. PA1 (3) Interrupt vector is received (introduced). PA1 (4) Address of interrupt processing program is determined by referencing a table from the vector value. PA1 (5) Branching to interrupt processing program is executed.
FIG. 5 is a detailed flowchart of the above-mentioned interrupt response procedures, specifically, an interrupt processing exception sequence. In Step S102 in this diagram, the value of PC-2 indicates the lead instruction which is to be next executed when there is no external interrupt. Specifically, this value indicates the set value for the program counter. During the course of the above-mentioned processing steps (1) to (5) for the response sequence, the necessary processing for exiting the internal conditions of the microprocessor which exist immediately prior to an interrupt and the like is executed. However, this is not an essential item as far as the present invention is concerned, and explanation is therefore omitted here.
However, when a processing program corresponding to that interrupt is executed using an interrupt mechanism provided with a plurality of priority levels, it is usual for an interrupt mask level to be set automatically, depending on the priority level of the received interrupt. The above-mentioned Motorola 68000 microprocessor is provided with interrupt levels from level 0 to level 7 as shown, for example, in FIG. 6, and execution is performed in Step S104 as shown in FIG. 5.
Using an interrupt mask level, if the degree of priority is the same as the mask level, interrupt requests with a lower priority level are ignored, specifically, are masked. Accordingly, if the priority level of the interrupt request just received is set as the mask level, interrupt requests of the same priority level and interrupt requests of a lower priority level are ignored. Even in the case where the device which had received the interrupt continues to output a request, the request is ignored, therefore this is extremely convenient because multiple requests are not accepted. Also, it is extremely convenient to have the received interrupt priority level set as a mask level because the next interrupt request from among a plurality of interrupt requests of the same priority level is to be executed after the processing of the initially received interrupt request is completed.
With a 68000 microprocessor, for example, a priority level 7 only is handled as an exception, and the configuration is such that an interrupt request of a priority level the same as the interrupt mask level is only received and used as a mask impossible interrupt. This method of setting the interrupt mask level is an extremely superior method, but there is one problem. Specifically, it is necessary to return back to a microprocessor an interrupt vector corresponding to an interrupt cause which is in agreement with the received interrupt priority level.
Because the address of the interrupt processing program is calculated from the interrupt vector, the interrupt vector, which is input to the microprocessor during the interrupt reception bus cycle or is provided by an interrupt controller or an interrupt request device, is seen to be not necessarily structured to correspond to an interrupt cause in agreement with the received priority level. Rather, in the case where an interrupt request is generated with a higher priority level than the received interrupt request, an interrupt vector is input which corresponds to a newly generated interrupt request at a higher priority level. A method of responding to this newly generated, high priority level interrupt request is desired.
However, this presents a problem. This is because the interrupt vector is determined during the interrupt reception bus cycle, and the interrupt mask level used in the interrupt processing routine is used for the initially received interrupt request.
In actual practice, only a short time is available after the microprocessor receives the interrupt until the interrupt reception bus cycle is executed. As shown in FIG. 5, using the 68000 microprocessor as an example, the interrupt reception bus cycle is executed (Step S107) after the lower order two bytes of the program counter are removed to a stack (Step S105). Also, in other types of microprocessors, an instruction prefetch is executed asynchronously with the interrupt reception. In this case, the progress of the executed bus cycle is not halted when the interrupt is received. These bus cycles are normally completed within several clock cycles, but, for example, there are cases in which there is a waiting time of several tens of clock cycles or more when there is competition with a refresh operation for a dynamic memory used for the main storage and with another bus master in a multiprocessor.
In general, the interrupt request signal can be varied frequently and at any time, and there is no guarantee that the interrupt request signal at the instant when the interrupt is received will be completely in agreement with the interrupt request signal at the instant when the interrupt reception bus cycle is executed. The interrupt request from the interrupt requesting device is arbitrated by the interrupt controller to determine the interrupt with the highest interrupt level, and this can vary frequently and at any time.
In the case where the input of an interrupt vector corresponding to an interrupt of the received priority level is a prerequisite, as with the 68000 microprocessor, the interrupt controller must not merely find an interrupt of the highest priority level at a certain instant, but must find the interrupts positioned in the greatest priority sequence from among the interrupt requests of the same interrupt priority level as that received by the microprocessor, specified when the microprocessor executes the interrupt reception bus cycle (in the case of the 68000 microprocessor, output on address buses A1 to A3). (Care must be taken in the case where a plurality of interrupt causes jointly have the same interrupt priority level). This places an extremely large burden on the interrupt controller, and requires a complicated configuration.
In addition, after the instant when an interrupt is received, if an interrupt request signal is generated which has an even higher priority level, the interrupt request with this newly generated high priority level is deferred (irrespective of how high a priority level it has). Specifically, when control is shifted to an interrupt processing program corresponding to an interrupt request received a short time previously, there is a waiting period until an interrupt with a priority level higher than the mask level used at this time is received. After an interrupt is received, several tens of clock cycles are generally necessary until the start of the execution of the interrupt processing program, in order to process the withdrawal from the internal conditions of the microprocessor. Accordingly, it is desirable that the interrupt request at the highest priority level be determined immediately before this interrupt request is transmitted to the microprocessor, specifically, immediately before the interrupt vector is provided in the interrupt reception bus cycle.
In this case, the microprocessor must be provided with a configuration which can cope with the condition where the interrupt received by the microprocessor and the interrupt vector input to the interrupt reception bus cycle are not in agreement. However, this non-agreement is a fatal problem for the 68000 microprocessor, for example, because the received priority level is set as the interrupt mask level. However, this problem is not acknowledged.
As outlined in the foregoing, in a conventional data processing device provided with a mechanism for automatically setting the interrupt priority level as the interrupt mask level (used with the interrupt processing program), when the interrupt vector is provided to the microprocessor, an interrupt cause corresponding to a priority level set by the microprocessor (the received interrupt level being set) is sought, and an interrupt vector must be provided to cope with this. This results in the drawback whereby the priority ranking order mechanism of the interrupt controller becomes extremely complicated.
In addition, because the time at which the interrupt is received corresponds with an interrupt at the highest priority level, this interrupt is executed after the execution of the interrupt request with the high priority level, even if an interrupt request with a priority level higher appears immediately afterward. Specifically, because a decision must be made as to which interrupt request has the highest priority must be made in an unnecessarily short time, there is the drawback that the response time for an interrupt request with a higher priority level is delayed longer than necessary (is postponed).
USPTO Backgrounds
USPTO Backgrounds