The present invention relates to ATE systems and methods.
FIG. 1 is a block diagram illustrating a system for explaining a test method of integrated circuit or chip equipment in a conventional art. As described in U.S. Pat. No. 6,883,128, conventional test equipment includes a PC equipment 201 having a chip equipment 210, a logic analyzer 202 for trigging and obtaining a signal waveform of a terminal(pin) group of the chip equipment 210 as a certain fail information, a pattern generation equipment 203 for inputting a signal waveform data(trace data) obtained from the logic analyzer 202 and converting to a test pattern of a desired test equipment and outputting the same, an automatic test equipment(ATE) 204 for testing a chip equipment as a tested device(DUT) 204-1 using a test pattern from the pattern generation equipment 203 and judging whether an error occurs in the PC equipment, and a mass production ATE 205 for testing the products same as the chip equipment 210 mounted in the PC equipment 201 as a tested device(DUT) 205-1. A test pattern is generated based on a trace data of an operation state of a chip equipment mounted in a PC equipment for thereby testing a tested device. D data extracted from a logic analyzer is capable of only a small amount of a timing pattern which occurs in the PC. Even when a desired amount of the timing pattern is extracted, since the environments between the PC and the ATE are very different, a desired reproduction is not obtained. In addition, the system is expensive. The '128 patent solves this issue by implementing a memory pattern test using a pattern generation substrate in which a processor is designed in an EPLD for implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. To certify the performance and functionality of modern semiconductor devices, reliable Automatic Test Equipment is required to maximize its utilization. The circuitry of the DUT simulating and monitoring elements all are powered by Direct Current (DC) supplies. Historically, these DC supplies have been generated with a multitude of different individual bulk supplies with different voltage outputs to handle the requirements of the different test elements. These many varied bulk supplies are a major component to Automatic Test Equipment (ATE) failures.
USPTO Backgrounds
USPTO Backgrounds