1. Field of the Invention
This invention relates to generating frequency signals, and more particularly to a system and method for controlling the generation of frequencies in oscillator circuits such as but not limited to phase-locked loops.
2. Description of the Related Art
Phase-locked loop (PLL) circuits are found in many processing systems. They are, for example, commonly used to generate mixing signals in communications systems and clock signals for controlling the speed and synchronizing the operation of various components in microprocessor systems.
While PLL circuits have proven to be desirable in terms of their ability to generate a stable frequency output, they are not without drawbacks. For example, many conventional PLL circuits experience a condition known as deadlock which can render the PLL and its host system inoperable for all practical purposes. Deadlock arises as a result of a difference between the frequency range of the voltage-controlled oscillator (VCO) portion of the PLL and the operational limitations of one or more accompanying elements. For example, it is often the case that a VCO is used which can operate at frequencies that exceed the maximum operational frequency of the phase-frequency detector of the PLL. At these frequencies, the phase-frequency detector will become overdriven and as a result its output will become clamped to a power supply potential or ground. The same situation may arise in a frequency divider located along a feedback path of the PLL. When either of these situations arises, the PLL is said to be deadlocked and thus unusable for any practical application.
Various approaches have been taken in attempt to correct deadlock in a PLL. Most of these approaches involve the use of a counter circuit or a custom-made frequency divider designed to operate at higher-than-normal operating frequencies. Both approaches have proven undesirable. For example, the use of counter circuits increases power requirements and chip space that may otherwise be used for more functionally important purposes. The use of custom-made frequency dividers is also inefficient because it increases the cost of the overall system.
In view of the foregoing considerations, it is apparent that there is a need for an improved system and method for correcting deadlock in a phase-locked loop, and more specifically one which takes a corrective approach which does not realize any of the drawbacks of the conventional methods.
USPTO Backgrounds
USPTO Backgrounds