1. Field of the Invention
The present invention relates generally to a Digital Video Broadcasting (DVB) system. More particularly, the present invention relates to an apparatus and method for transmitting and receiving preambles among components of a frame in a DVB system.
2. Description of the Related Art
Generally, the term “digital broadcasting system” denotes a broadcasting system using a digital transmission technology, such as Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB) and Digital Multimedia Broadcasting (DMB).
Among others, the DVB system, a European digital broadcasting technology, is a transmission standard for supporting not only the existing digital broadcasting but also mobile/portable digital multimedia services.
The DVB system can multiplex Moving Picture Experts Group 2 Transport Stream (MPEG 2 TS)-based broadcast data, and transmit IP-based data streams simultaneously. In the DVB system, various services can be transmitted after being multiplexed to one IP stream. And, after receiving data of the transmitted IP stream, a terminal can demultiplex it back into individual services, demodulate the services, and output them through a screen of the user terminal. At this point, the user terminal needs information indicating types of the various services provided by the DVB system and the details that each of the services contains.
FIG. 1 is a diagram illustrating a frame structure of a physical channel in a DVB system according to prior art.
Referring to FIG. 1, the frame structure can be roughly divided into preamble parts P1 and P2, and body parts BODY. The preamble parts P1 and P2 are used for transmitting signaling information of the frame, while the body parts consist of the parts used for transmitting data or payload.
The purposes of the preamble P1 in FIG. 1 are as follows. First, the preamble P1 is used for scanning an initial signal of a frame at a receiver. Second, the preamble P1 is used for detecting a frequency offset and tuning the center frequency at the receiver. Third, the preamble P1 is used for transmitting identification information of the frame as well as transmitting Fast Fourier Transform (FFT) size and other transmission information. Finally, the preamble P1 is used for detecting and correcting frequency and time synchronization at the receiver.
Regarding the structure of the preamble P1 in FIG. 1, a part A, in which information is transmitted, is fixed to 1K Orthogonal Frequency Division Multiplexing (OFDM) symbols regardless of an FFT size of a payload where data is transmitted, and has a length of 112 μs. When the other parts B and C each consist of a ½ guard interval, they are added to both sides of the 1K symbols, with a length of 56 μs. As shown in FIG. 1, the total length of the preamble P1 is 224 μs.
FIG. 2 is a diagram illustrating locations of carriers on which a preamble sequence is transmitted in the prior art.
The drawing of FIG. 2 is given for a description of an internal structure of the 1K OFDM symbols shown in FIG. 1. As illustrated in FIG. 2, the 1K OFDM symbols include 853 carriers. Among the 853 carriers constituting the 1K OFDM symbols, only 384 carriers are used for transmission of a preamble sequence.
FIG. 3 is a block diagram illustrating a transmitter for transmitting a preamble in a DVB system according to prior art.
Locations of the carriers used for transmission of a preamble sequence among the 853 carriers can be predetermined. In FIG. 3, carrier locations are predetermined and stored in a Carrier Distribution Sequence (CDS) table 300.
An operation of a Modulation Signaling Sequence (MSS) processor 310 is as follows. The MSS processor 310 receives a first sequence (hereinafter ‘S1’) and a second sequence (hereinafter ‘S2’) and generates Complementary Sets of Sequences (CSSs). The S1 and S2 include 3-bit information and 4-bit information, respectively. The CSSs generated by the S1 and S2 have 8 and 16 combinations, respectively and CSSS1 and CSSS2 generated by the S1 and S2 have a length of 64 and 256, respectively. Such CSSs are characterized in that they are low in a Peak-to-Average Power Ratio (PAPR) and orthogonal with each other.
Signals of the S1 and S2 can be expressed as shown in Table 1, where they are expressed in hexadecimal.
TABLE 1FieldValSequence (Hexadecimal notation)S1000124721741D482E7B00147127421481D7B2E010217412472E7B1D48011742147127B2E481D1001D482E7B12472174101481D7B2E471274211102E7B1D48217412471117B2E481D74214712S20000121D4748212E747B1D1248472E217B7412E247B721D174841DED48B82EDE7B8B00014748121D747B212E48471D127B742E2147B712E2748421D148B81DED7B8B2EDE0010212E747B121D47482E217B741D12484721D1748412E247B72EDE7B8B1DED48B80011747B212E4748121D7B742E2148471D12748471D147B712E27B8B2EDE48B81DED01001D1248472E217B74121D4748212E747B1DED48B82EDE7B8B12E247B721D17484010148471D127B742E214748121D747B212E48B81DED7B8B2EDE47B712E2748421D101102E217B741D124847212E747B121D47482EDE7B8B1DED48B821D1748412E247B701117B742E2148471D12747B212E4748121D7B8B2EDE48B81DED748421D147B712E2100012E247B721D174841DED48B82EDE7B8B121D4748212E747B1D1248472E217B74100147B712E2748421D148B81DED7B8B2EDE4748121D747B212E48471D127B742E21101021D1748412E247B72EDE7B8B1DED48B8212E747B121D47482E217B741D1248471011748421D147B712E27B8B2EDE48B81DED747B212E4748121D7B742E2148471D1211001DED48B82EDE7B8B12E247B721D174841D1248472E217B74121D4748212E747B110148B81DED7B8B2EDE47B712E2748421D148471D127B742E214748121D747B212E11102EDE7B8B1DED48B821D1748412E247B72E217B741D124847212E747B121D474811117B8B2EDE48B81DED748421D147B712E27B742E2148471D12747B212E4748121D
A series of processes in which the sequences S1 and S2 are output as a modulated sequence by means of the MSS processor 310 through a phase offset processor 325 is as follows.
Equation (1) represents a sequence generated by a combination of S1 and S2 in the MSS processor 310, and the sequence is denoted by MSS_SEQ.MSS_SEQ={CSSS1, CSSS2, CSSS1}  (1)
MSS_SEQ in Equation (1) is modulated by Differential BPSK (DBPSK) in a DBPSK modulator (or DBPSK mapper) 320. Equation (2) represents the DBPSK-modulated sequence, which is denoted by MSS_DIFF.MSS_DIFF=DBPSK(MSS_SEQ)  (2)
The phase offset processor 325 outputs the finally modulated sequence by applying a 180° phase offset to 64 Most Significant Bit (MSB) bits (or cells) in the modulated sequence. The phase offset processor 325 does not apply the phase offset to the remaining bits except for the 64 MSB bits. Since the 64 MSB bits all have the same offset value, the phase offset value will not affect a demodulation process of a DBPSK demodulator in a receiver. Hence, there is no need for a reverse process of the phase offset process at the receiver. Finally, an output of the phase offset processor 325 is defined as Equation (3).MSS={−MSS_DIFF383, 382, . . . , 320, MSS_DIFF319, 318, . . . , 0}  (3)
The sequence being output through the MSS processor 310, DBPSK modulator 320 and phase offset processor 325, i.e. the modulated sequence, is allocated to 384 active carriers for P1 by the carrier allocator 330.
In structure, 2 guard intervals are added to improve robustness of symbols for P1, and operations of an Inverse Fast Fourier Transform (IFFT) processor 340 and a preamble generator 350 are substantially the same as that in FIG. 1.
FIG. 4 is a block diagram illustrating a receiver for receiving a preamble in a DVB system according to prior art.
Referring to FIG. 4, a preamble detector 400 in the receiver detects a preamble and inputs it to an FFT processor 410. The FFT processor 410 performs FFT on the detected preamble and outputs the results to a demultiplexer (DEMUX) 420. Next, the DEMUX 420 demultiplexes data on active carriers through which a preamble is transmitted, and outputs the demultiplexed data to a DBPSK demodulator 430. The DBPSK demodulator 430 performs a reverse process of the phase offset processor 325, i.e. performs DBPSK demodulation that inversely phase-shifts MSB signals of the preamble by a length of 64 at the receiver, and then outputs the results to a signaling detector 440. The signaling detector 440 outputs desired information by detecting S1 and S2 from the demodulated sequence.
FIG. 5 is a flowchart illustrating a reception method for receiving a preamble in a DVB system according to prior art.
Referring to FIG. 5, the receiver performs initialization in step 500, and performs tuning on a preamble in step 505. The receiver performs Guard Interval-Correlation (GIC) on a received signal in step 510, and determines in step 515 whether it has detected a preamble P1. When the receiver has failed to detect the preamble P1 in step 515, the receiver returns to step 510. Otherwise, when the receiver has detected the preamble P1, the receiver performs coarse time adjustment and fine frequency offset adjustment in step 520. Next, in step 525, the receiver performs power correlation to estimate power of active carriers, and determines again in step 530 whether it has detected the preamble P1. Upon failure to detect the preamble P1, the receiver returns back to step 510, and when the receiver successfully detects the preamble P1, the receiver performs coarse frequency offset adjustment in step 535. Thereafter, the receiver performs DBPSK demodulation, which is a reverse process of the differential modulation scheme at the transmitter, in step 540, calculates a correlation value between preambles in step 545, and detects signals of S1 and S2 in step 550.
As the above-stated conventional preamble structure uses the differential modulation (i.e. DBPSK), non-coherent reception is possible. However, a characteristic of the complementary sequences changes due to the execution of the differential modulation, causing an increase in the PAPR. Accordingly, there is a need for an improved apparatus and method for transmitting and receiving preambles among components of a frame in a DVB system.
USPTO Backgrounds
USPTO Backgrounds