1. Field of the Invention
The present invention relates to the design and fabrication of large scale integrated circuits including program logic array structures, and more particularly relates to a method for facilitating engineering changes during the fabrication thereof.
2. Background Art
PLAs incorporated on advanced custom LSI and VLSI semiconductor chips are designed in general for control logic implementations. This area of the overall logic design is the most susceptible to change. In the past, even minor changes, such as the addition of a single device to alter the personalization of the AND array, required a nearly complete rebuild of all process masks and, as such, resulted in large scrap costs and long lead times until the introduction of the engineering change ("EC"). The requirement for an additional input or product term causes a great deal of chip rework, and requires a completely new mask set.
It is therefore an object of the present invention to provide a method for fabricating LSI chips incorporating PLAs that do not require a completely new mask set for an engineering change.
USPTO Backgrounds
USPTO Backgrounds