1. Field of the Invention
The present invention generally relates to electrical circuits and their fabrication. More particularly, this invention relates to a process for fabricating circuit board conductors with reduced self and mutual capacitance per unit length, resulting in significantly reduced crosstalk and propagation delays for digital signal lines, and increased useful bandwidth for integral inductors.
2. Description of the Prior Art
As depicted in FIG. 1, multilayer printed circuit boards 10 typically have metal layers that are patterned to form conductors or traces 12 and 14, which may serve as digital signal lines or inductor windings of an integral inductor. Traces 12 and 14 of adjacent metal layers are separated by a dielectric layer 16 and may be electrically interconnected with a metallized via (not shown) through the dielectric layer 16. Traditional methods of patterning metal layers of a printed wiring board (PWB) require traces to be either buried within or resting on a planar dielectric layer, as traces 12 and 14, respectively, are depicted with respect to the dielectric layer 16. As a result, the dielectric layer 16 lies between the traces 12 and 14 and promotes self and mutual capacitances that are detrimental if the traces 12 and 14 are adjacent digital signal lines or inductor windings. In the case of digital signal lines, these capacitances create significant undesirable signal propagation delays and levels of crosstalk between adjacent lines. For integral inductors, parasitic capacitance between adjacent windings lowers the self resonance frequency of the inductor and hence reduces useful bandwidth.
Prior methods of minimizing parasitic capacitance between adjacent traces have involved either the use of costly, low-dielectric constant materials to form the dielectric layers between the traces, or the alteration of the line widths or spaces between the lines. The latter approach involves increasing the distance between adjacent lines and/or decreasing the line widths, with a disadvantage of the first being that additional layout area is required and a disadvantage of the second being objectionably narrow lines that produce additional electrical loss and greater sensitivity to process variations.
Accordingly, it would be desirable if a method were available for fabricating circuit board conductors and traces with reduced self and mutual capacitance per unit length, with the result that crosstalk and propagation delays are significantly reduced for digital signal lines, and useful bandwidth is significantly increased for integral inductors.
USPTO Backgrounds
USPTO Backgrounds