The present application relates to semiconductor device fabrication, and more particularly to a method of reducing etch time needed for patterning an organic planarization layer so as to minimize damages to gate structures and fin structures in a block mask patterning process.
Fin field effect transistors (FinFETs) are one of the leading candidates to replace classical planar metal-oxide-semiconductor FETs (MOSFETs) for future complementary metal oxide semiconductor (CMOS) technologies due to the multiple-gate configuration of the fin device leading to an intrinsically superior short channel effect control. Conventionally, source/drain regions in FinFETs are formed by implanting dopants into fins and during the ion implantation, one of the devices types, e.g., n-type FinFETs (nFinFETs), must be covered or masked with a layer of material, such as photoresist, so dopants are implanted only into another device type, e.g., p-type FinFETs (pFinFETs).
Photolithography and etching processes are commonly used to define the masked regions and exposed regions. A typical prior art process uses a thin photoresist layer on top of a thick organic planarization layer (OPL) as a block mask. The OPL typically has a thickness ranging from 100 to 300 nm to planarize gate structures and fin structures with high topography. Standard lithographic processes are used to pattern the top photoresist layer and the resulting pattern is then transferred into the bottom OPL by an anisotropic etch such as, for example, reactive ion etching (RIE). However, since the thick OPL requires a much longer etch time, damages to the gate structures and the fin structures may occur during the RIE of the OPL, which in turn may cause defect formation in the subsequent processes, such as the epitaxial growth process to form raised source/drain regions. Therefore, there remains a need to develop block mask patterning processes that would overcome the disadvantages of the prior art approach.
USPTO Backgrounds
USPTO Backgrounds