A process of testing a semiconductor device is performed after semiconductor chip fabrication and packaging processes. That is, whether a device that is formed after circuits and interconnections are implemented on a wafer fulfills its function is verified through the test process. Generally, a process that is performed at a wafer level before the packaging process is performed is referred to as Electrical Die Sorting (EDS). In addition, whether the device is good or not is also tested after packaging is performed.
As a design rule is reduced and complicated functions are realized in a single chip in the process of fabricating a semiconductor device, the test is performed after implementing a scan cell in a predetermined region of the chip rather than directly testing characteristic functions of the chip. The scan cell is disposed between a core or function block that takes charge of the characteristic functions of the device and input/output pads.
Generally, the scan cells are serially connected to each other to form a scan chain. The scan chain includes a shift register therein to continuously transmit a test pattern. The test pattern is applied to an input pin during the test, an output of an output pin is compared with an expected value, and finally, whether the device is defective or not is determined.
When the scan design-based test (scan test) is performed, overkill and underkill should be taken into account.
A case in which a good semiconductor device is determined to be defective is referred to as overkill, and a case when a substantially defective semiconductor device is determined to be good is referred to as underkill. Overkill and underkill are different from each other simply in view of the aspect of determination, however both are representative phenomena of a test being erroneously determined.
Generally, a switching operation of a circuit provided in the scan cell causes overkill. That is, when the number of switching operations of a circuit that is tested according to a test pattern exceeds the normal operation, an electric current supplied to the scan cell is increased. When an electric current supplied during the test is greater than that supplied during the normal operation of the semiconductor chip, a ground level is not uniformly set, and pulsating ground bouncing is generated. As a result, overkill in which a semiconductor chip operating normally in a packaged environment is determined to be defective during a test operation occurs.
In order to prevent the overkill phenomenon, a method of reducing a conventional test operating speed is used in automatic testing equipment. That is, a method of reducing the operating speed of the test pattern is used to lower transition of signals. Accordingly, the number of switching operations of a circuit in the scan cell per unit time is reduced, and thus the supplied electric current is reduced as well. The reduced electric current may minimize ground bouncing. However, the operating speed of the test pattern may not sufficiently cover the operating speed in a normal use environment. Accordingly, underkill in which a defective semiconductor device in an actual package environment is determined to be good occurs.
USPTO Backgrounds
USPTO Backgrounds