(1) Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, formed simultaneously using only one additional mask reticle to form both MIM capacitor and resistor, simultaneously.
(2) Description of Related Art
In this section a description of related Prior Art background patents follows.
U.S. Pat. No. 6,083,785 entitled xe2x80x9cMethod Of Manufacturing Semiconductor Device Having Resistor Filmxe2x80x9d granted Jul. 4, 2000 to Segawa et al. shows a MIM capacitor process with spacer over a resistor. An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film, except for contact formation regions and an upper electrode film as a second conductor member, are formed simultaneously with the formation of a gate-electrode and a gate oxide film. Silicide films of a refractory metal are formed on the respective surfaces of the gate electrode, N-type high-concentration diffusion layers, the contact formation regions of the resistor film, and the upper electrode film. By utilizing a salicide process, a resistor and an inductor each occupying a small area can be formed without lowering the resistance of the resistor film.
U.S. Pat. No. 6,284,590 entitled xe2x80x9cMethod To Eliminate Top Metal Corner Shaping During Bottom Metal Patterning For MIM Capacitorsxe2x80x9d granted Sep. 4, 2001 to Cha et al. describes a MIM capacitor process for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode, and this flowable material is anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer. The capacitor dielectric layer and the first metal layer are patterned wherein the patterned first metal layer forms a bottom metal electrode and wherein the spacers protect the top metal layer from etching during the patterning. The photoresist mask is removed, completing fabrication of a metal-insulator-metal capacitor.
U.S. Pat. No. 6,284,619 B1 entitled xe2x80x9cIntegration Scheme For Multilevel Metallization Structuresxe2x80x9d granted Sep. 4, 2001 to Seymour et al. reveals a scheme for multilevel metallization structures that improve semiconductor reliability. Multilevel metallization structures are formed through a two-step etch process which alleviates the problem of conductive etch residue forming between metal layers in multilevel structures. The resulting metallization structure has sidewall insulators on selected layers that prevent conductive etch residue from forming between the metal layers.
U.S. Pat. No. 6,271,084 B1 entitled xe2x80x9cMethod Of Fabricating A Metal-Insulator-Metal (MIM), Capacitor Structure Using A Damascene Processxe2x80x9d granted Aug. 7, 2001 to Tu et al. describes a MIM capacitor using a damascene process for forming a vertical, metal-insulator-metal (MIM), capacitor structure, for embedded DRAM devices. The process features forming a capacitor opening in a composite insulator layer comprised of a overlying insulator stop layer, a low k insulator layer, and an underlying insulator stop layer, with a lateral recess isotropically formed in the low k insulator layer. After formation of a bottom electrode structure in the capacitor opening, a high k insulator layer is deposited followed by the deposition of a conductive layer, completely filling the capacitor opening. A chemical mechanical polishing procedure is then used to remove portions of the conductive layer, and portions of the high k insulator layer, from the top surface of the overlying insulator stop layer, resulting in the formation of the vertical MIM capacitor structure, in the capacitor opening, comprised of: a top electrode structure, defined from the conductive layer; a capacitor dielectric layer, formed from the high k insulator layer; and a bottom electrode structure.
This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, formed simultaneously using damascene processing, eliminating an extra masking step.
This new method, disclosed by the present invention, has the key advantage of eliminating an extra masking step. This new method overcomes several current obstacles that exist in the fabricate MIM capacitors in the BEOL, back end of line, namely: (a) the use of two or more photo-masks to make  less than 0.13 um MIM capacitors, (b) undulated copper surfaces, when dielectrics are deposited directly upon it, resulting in poor reliability, (c) for dielectric deposition directly on the bottom copper electrode plate, there are particles generation concerns during etching, when attempting an etch stop on the bottom plate Cu/IMD layers, and finally, (d) dishing during CMP occurs when large copper MIM plates are required, with subsequent capacitance matching problems. The new integrated method over comes all the above obstacles and simultaneously forms MIM capacitors, metal resistors and metal interconnects using damascene processing throughout.
The present invention teaches a process for the formation of a MIM capacitor, a metal resistor, and copper BEOL interconnect wiring and eliminates an extra masking step by using the combination of damascene processing and chemical mechanical polishing, CMP. A brief outline of the key processing steps follows below:
a) form bottom MIM trench openings and other metal line openings in an intermetal dielectric, IMD. (MASK #1, PHOTO #1)
b) fill trenches openings with metal barrier and copper, planarizing with CMP, forming bottom MIM and interconnects
c) form shallow trench openings in a thin IMD, over existing bottom MIM and interconnects, same pattern as MASK #1. (MASK #1, PHOTO #2)
d) form bottom plate barrier layers in shallow trench openings and planarize surface by CMP.
e) form high dielectric constant insulator over thin IMD and patterned barrier layers.
f) form top metal for MIM, top interconnects, metal resistors over high dielectric constant insulator. (MASK #2, PHOTO #3) This completes the formation of the MIM capacitor, the resistor part of the metal resistor, and bottom interconnection wiring.
Therefore, in the above key processing steps, are shown the formation of high capacitance, less than 0.13 micron metal-insulator-metal capacitors, metal resistors and metal interconnects, which are all formed simultaneously using damascene processing, eliminating an extra masking step. The remainder of the processing involves encapsulation, packaging and electrical contact to the above devices. Therefore, from this point on in the process, BEOL, back end of line, processing is primarily focused on encapsulating the devices for electrical isolation and packaging, and making electrical contact through contact vias and trenches to the MIM capacitors and metal resistors. The key parts of the MIM capacitors and metal resistors have been formed with only two photo masks and three photolithography processing steps.
This invention has been summarized above and described with reference to the preferred embodiments. Some processing details have been omitted and are understood by those skilled in the art. More details of this invention are stated in the xe2x80x9cDESCRIPTION OF THE PREFERRED EMBODIMENTSxe2x80x9d section.
USPTO Backgrounds
USPTO Backgrounds