1. Technical Field
Embodiments of the present invention relate generally to a semiconductor technology, and more particularly, to a semiconductor memory apparatus and a data input/output method thereof.
2. Related Art
To obtain high-speed operation of semiconductor memory, a plurality of stacked memory banks constituting a stacked bank structure is being employed in the semiconductor memory apparatus to improve data access time. In a semiconductor memory apparatus having the stacked bank structure, memory cell regions are partitioned into a plurality of memory blocks, and each of the partitioned memory blocks comprises a plurality of stackedmemory banks.
FIG. 1 is a block diagram schematically showing a configuration of a semiconductor memory apparatus including stacked memory banks. As shown in FIG. 1, the semiconductor memory apparatus includes first and second memory banks Bank1 and Bank2, first and second column decoders 11 and 12, and first and second input/output (I/O) drivers 21 and 22. Hereinafter, it is assumed that the first and second memory banks Bank1 and Bank2 constitute the stacked bank structure.
The first column decoder 11 and the first input/output driver perform a data read or write (hereinafter, referred to as ‘read/write’) operation on the first memory bank Bank1, and the second column decoder 12 and the second input/output driver 22 perform a data read/write operation on the second memory bank Bank2. More specifically, in the data read/write operation on the first memory bank Bank1, the first column decoder 11 generates, in response to column address signal ‘Ya<2:7, 9> and a strobe signal ‘strobe<0>, a column selection signal ‘Yi_up’ to enable a column selection line ‘CSL_up’ of the first memory bank Bank1. In the data read/write operation on the second memory bank Bank2, the second column decoder 12 generates, in response to the column address signals ‘Ya<2:7, 9> and a strobe signal ‘strobe<1>, a column selection signal ‘Yi_dn’ to enable a column selection line ‘CSL_dn’ of the second memory bank Bank2. As shown in FIG. 1, the global input/output line GIO and an input/output pad DQ are shared by the memory banks Bank 1 and Bank 2. In response to their respective strobe signals ‘strobe<0:1>’, the first and second input/output drivers 21 and 22 amplify data stored in the first memory bank Bank1 and data stored in the second memory bank Bank2 respectively, and output the amplified data to outside of the semiconductor memory apparatus via the global input/output line GIO and an input/output pad DQ. During a data write operation, the first and second input/output drivers 21 and 22 amplify data received from outside via the pad DQ and the global input/output line GIO and transfer the amplified data to the first memory bank Bank1 and to the second memory bank Bank2, respectively.
Thus, as is shown in FIG. 1 and described above, the same global input/output line GIO and the same pad DQ are assigned to each of the stacked memory banks Bank1 and Bank2 constituting the stacked bank structure. However, separate column decoders 11 and 12 and separate input/output drivers 21 and 22 are required for the stacked memory banks Bank1 and Bank2. This is because the column selection line CSL_up of the first memory bank Bank1 and the column selection line CSL_dn of the second memory bank Bank2 are different from each other and the local input/output line LIO_up of the first memory bank Bank1 and the local input/output line LIO_dn of the second memory bank Bank2 are different from each other.
The requirement of separate column decoders and input/output drivers makes it difficult to secure a lay-out margin of the semiconductor memory apparatus. A technique in which stacked memory banks share a column selection line has been proposed, but the technique causes an overload on the column decoder facing the column selection line. In addition, no proper technique that allows the stacked memory banks to share the input/output driver has been proposed until now.
USPTO Backgrounds
USPTO Backgrounds