1. Field of the Invention
The present invention relates to a semiconductor device which has a capacitive element which comprises an MIS (metal-insulator-semiconductor) structure.
2. Description of Related Art
When a capacitive element is formed in a monolithic integrated circuit (IC), there is generally employed an element of an MIS structure (hereinafter referred to as MIS capacitive element) in which a metal electrode is formed with a dielectric layer on an impurity-diffused region which is formed simultaneously with an impurity region such as an emitter region on a semiconductor substrate.
Normally the MIS capacitive element is formed, as illustrated in FIG. 7, by an N-type epitaxial layer 3 which is grown on a P-type semiconductor substrate 1 and which is surrounded by a P.sup.+ element isolating region 2 to form an island. Then an N.sup.+ diffused region 4 is formed on the surface of the island region 3. An aperture 5 is then formed in an interlayer insulator film 10 of AsSG or the like on the surface of the substrate in a manner such that the N.sup.+ diffused region 4 is exposed in a predetermined area. One electrode 7 of aluminum is formed in the aperture 5 over a dielectric layer 6 which is composed of a silicon nitride (SiN) film or the like, and another electrode 9 of aluminum is formed through an aperture 8 in another exposed portion of the N.sup.+ diffused region 4. A capacitance-setting MIS segment 12 comprising the N.sup.+ diffused region 4, the dielectric layer 6 and the aluminum electrode 7 are formed; and an electrode lead segment 13 comprising the other portion of the N.sup.+ diffused region 4 and the aluminum electrode 9 is also formed. The value of capacitance is determined by the area of the aperture 5 in the MIS segment 12.
In the above-described MIS capacitive element 11, the aperture 5 in the MIS segment 12 is formed by the technique of wet etching. However, there are some disadvantages in this technique because the precision of maintaining the area of the aperture 5 is low due to difficulties in controlling the wet etching, and a high precision of the capacitance cannot be obtained since the parasitic capacitance Cp is not negligible in the portion where the aluminum electrode 7 is superposed on the N.sup.+ diffused region 4 with the interlayer insulator film 10 interposed therebetween in the periphery of the aperture 5.
In an attempt to eliminate such disadvantages, the present applicant previously proposed an MIS capacitive element 21 of an improved structure where, as illustrated in FIG. 6, the value of capacitance is determined by the aperture area in a field insulator film formed by selective oxidation (LOCOS). In such MIS capacitive element 21, an island-shaped N-type epitaxial layer 24 is formed over an N.sup.+ buried layer 23 on a P-type semiconductor substrate 22 and is surrounded by a P.sup.+ element isolating region 25. Then a field insulator film 26 is formed on the substrate surface by selective oxidation. Then an N.sup.+ diffused region 28 is formed by ion implantation or the like in the N-type island region 24 adjacent to a first aperture 27, and one electrode 30 of aluminum is deposited on such N.sup.+ diffused region 28 over a dielectric layer 29 of silicon nitride (SiN) or the like, whereby an MIS segment 37 is formed. Meanwhile, another electrode 31 of aluminum is deposited on an N.sup.+ electrode lead region 33 in a second aperture 32 in the field insulator film 26, whereby an electrode lead segment 38 is formed.
The N.sup.+ diffused region 28 and the n.sup.+ electrode lead region 33 extend to a depth so that they reach the N.sup.+ buried layer 23 through N.sup.+ plug-in regions 34 and 35 which are formed by ion implantation through the apertures 27 and 32 respectively, so that the N.sup.+ diffused region 28 of the MIS segment 37 is connected to another aluminum electrode 31 through the buried layer 23.
The dielectric layer 29 also extends onto the field insulator film 26, and an interlayer insulator film 36 of AsSG or the like is formed on the dielectric layer 29. The aluminum electrodes 30 and 31 are formed so that they are partially over the interlayer insulator film 36.
In the MIS capacitive element 21 of such a structure, the are of the MIS segment 37 is determined by the aperture 27 in the field insulator film 26, i.e., by the bird's beak which is derived from selective oxidation, so that additional enhanced precision can be expected as compared with the conventional MIS capacitative element 11 shown in FIG. 7.
On the other hand, the N.sup.+ buried layer 23 is formed over the entire distance between the N.sup.+ plug-in regions 34 and 35 so as to reduce the parasitic resistance in a portion from the N.sup.+ diffused region 28 of the MIS segment 37 to the electrode lead segment 38, so that a problem exists with regard to an increase of the parasitic capacitance (or junction capacitance) between the P-type semiconductor substrate 22 and the N.sup.+ buried layer 23.
USPTO Backgrounds
USPTO Backgrounds