1. Field of the Invention
The present invention relates to a semiconductor chip and a semiconductor device having the semiconductor chip.
2. Description of Related Art
In recent years, along with downsizing of electronic devices or the like having a semiconductor device incorporated therein, there has been a strong demand for downscaling of semiconductor devices. In connection to this demand, there has been a development of a semiconductor device in which a plurality of semiconductor chips are stacked and these semiconductor chips are connected by using through silicon vias. For example, Japanese Patent Application Laid-open No. 2011-82450 discloses a semiconductor device in which a plurality of semiconductor chips are connected by through silicon vias (TSVs) each penetrating a silicon semiconductor substrate.
In some of semiconductor devices in which a plurality of semiconductor chips are connected by through silicon vias, an area where a plurality of through silicon vias are arranged in an array manner is provided. Such an area is called as a through-silicon-via array area in the following explanation. The through-silicon-via array area includes an insulation layer or a wiring layer which has a possibility that cracks are generated therein at the time of stacking the semiconductor chips. Since such cracks can be a cause of a failure of the semiconductor device, it is necessary to detect the presence of cracks in the through-silicon-via array area before shipment of semiconductor devices as products.
As a technique of detecting cracks that are generated on semiconductor chips, there has been proposed a semiconductor device in which a wire for detecting cracks is arranged along the entire outer periphery of a semiconductor chip. Each ends of the wire is connected to a pad which an external tester is brought into contact with. According to the semiconductor device, it becomes possible to detect cracks generated on the semiconductor chips by detecting a variation of a resistance value between the pads (see, for example, Japanese Patent Application Laid-open No. 2009-54862).
However, what the method described in Japanese Patent Application Laid-open No. 2009-54862 can detect are only cracks generated on an outer periphery part of a semiconductor chip, that is, an edge part of the semiconductor chip, and the method cannot detect cracks generated at portions other than an outer periphery part of a semiconductor chip.
The above-mentioned through-silicon-via array area is occasionally formed on a position other than an outer periphery part of a semiconductor chip, such as a central part of the semiconductor chip. Therefore, there has been a demand of a technique of detecting cracks generated on a position other than an outer periphery part of the semiconductor chip in order to detect cracks generated on the through-silicon-via array area.
USPTO Backgrounds
USPTO Backgrounds