1. Field of the Invention
The invention relates to a level shifter circuit which converts the amplitude of a signal. Further, the invention relates to a display device using a level shifter circuit and a driver circuit thereof.
2. Description of the Related Art
Since it is preferable that a mobile phone and a portable device such as a PDA (Personal Digital Assistant) be easy to carry and be used for a long time with limited power, power consumption has been required to be reduced. Therefore, there are quite a few integrated circuits (LSIs) for forming such a device as described above, which drive at a power source voltage of approximately 1.8 to 5 V. On the other hand, in a display device such as an LCD or an electroluminescence (EL) display, which is driven by these LSIs, there is at least a circuit which operates at a high voltage of 10 to 20 V as an example among internal driver circuits. For such a driver circuit, a level shifter circuit is used, which converts the amplitude of a signal when a control signal to be outputted from the low power source voltage circuit interacts with a high power source voltage circuit (see Patent Document 1).    [Patent Document 1] Japanese Patent Laid-Open No. 2001-257581
As a conventional level shifter circuit, a circuit configuration shown in FIG. 4 is given as an example. Hereinafter, the configuration of a level shifter circuit shown in FIG. 4 is described. A signal which changes between a high level as a VDD potential and a low level as a GND potential (hereinafter referred to as a VDD power source potential system) is inputted to an input 401. On the other hand, an inverted signal of the signal inputted to the input 401 is inputted to an input 405. The inputs 401 and 405 become inputs of the level shifter circuit.
As the signal inputted to the input 405, a signal generated by inverting the signal inputted to the input 401 with an inverter or the like may be used.
Identical power source inputting portions which are provided with a power source which is not shown, and supplied with a potential from the same power source are denoted by the same reference numerals. A power source inputting portion 402 supplied with a VDH potential from a first power source (not shown) is connected to sources of p-channel transistors 408 and 411. Further, a drain of the p-channel transistor 408 is connected to a source of a p-channel transistor 407, a drain of the p-channel transistor 407 is connected to a drain of an n-channel transistor 406, and a source of the n-channel transistor 406 is connected to a power source inputting portion 412 supplied with a GND potential from a second power source (not shown). Further, a drain of the p-channel transistor 411 is connected to a source of a p-channel transistor 410, a drain of the p-channel transistor 410 is connected to a drain of an n-channel transistor 409, and a source of the n-channel transistor 409 is connected to the power source inputting portion 412.
A signal which changes between a high level as a VDH potential and a low level as a GND potential (hereinafter referred to as a VDH power source system) is outputted from an output 403. An inverted signal of the signal outputted from the output 403, which is a VDH power source system signal, is outputted from an output 404. The outputs 403 and 404 become outputs of the level shifter circuit. As described above, the level shifter circuit shown in FIG. 4 converts the VDD power source system signal to the VDH power source system signal and outputs it.
Note that the level shifter circuit includes a power source which supplies 3 kinds of potentials, that is, a VDH potential, a VDD potential, and a GND potential. Description is made on operation of the level shifter circuit shown in FIG. 4 under the condition that a VDH potential is 15 V, a VDD potential is 5V, and a GND potential is 0 V. In addition, a threshold voltage of a p-channel transistor is set to −1 V and a threshold voltage of an n-channel transistor is set to 1V.
In a first period, when the signal inputted to the input 401 is at a high level, the VDD potential (5 V) is inputted to each gate of the n-channel transistor 406 and the p-channel transistor 407. At this time, the n-channel transistor 406 is turned on; thereby the GND potential (0 V) is inputted to a gate of the p-channel transistor 411 and the p-channel transistor 411 is turned on. The GND potential (0 V) is outputted from the output 403.
On the other hand, since an inverted signal of the signal inputted to the input 401, which is a low level, is inputted to the input 405, the GND potential (0 V) is inputted to each gate of the n-channel transistor 409 and the p-channel transistor 410. At this time, the p-channel transistor 410 is turned on and the p-channel transistor 411 is turned on as described above, thereby the VDH potential (15 V) is inputted to the p-channel transistor 408 and the p-channel transistor 408 is turned off. The VDH potential (15V) is outputted from the output 404.
In a second period subsequent to the first period, the signal inputted to the input 401 changes from a high level to a low level. The transitional period includes at least a period in which a potential of the input 401 is around intermediate between a high level and a low level. In view of the condition of each threshold of the n-channel transistor and the p-channel transistor, in the case where the signal inputted to the input 401 changes, if the potential is between 1 V and 4 V, each of the n-channel transistor 406 and the p-channel transistor 407 is at over the threshold and turned on. On the other hand, at the input 405 side, a similar phenomenon occurs, that is, each of the n-channel transistor 409 and the p-channel transistor 410 is turned on. At this time, the p-channel transistor 411 is turned on in the first period and the gate potential is to be increased. On the contrary, the p-channel transistor 408 is turned off in the first period, and the gate potential is to be decreased. Accordingly, at least a period in which each of the n-channel transistor 409, the p-channel transistor 410, and the p-channel transistor 411 is turned on is generated. Therefore, a through current is generated between the VDH potential and the GND potential.
Subsequently, in a third period subsequent to the second period, the signal inputted to the input 401 changes from a low level to a high level. The transitional period includes a period in which each of the n-channel transistor 406, the p-channel transistor 407, and the p-channel transistor 408 is turned on because of the same reason. Therefore, a through current is generated between the VDH potential and the GND potential.
Thus, the conventional level shifter circuit has a problem that a high-voltage VDH power source system through current is generated in a moment in the transitional period in which a level of an input signal changes, which increases power consumption. The amount of the through current which is generated in the transitional period in which a level of the signal changes is smaller than that of a current consumed by a driver circuit. In the case where a plurality of level shifter circuits each having the same structure are provided, however, a total amount of the though current cannot be ignored.
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USPTO Backgrounds