Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
FIG. 1 shows a portion of a typical prior art NAND flash memory array. The selected access line (e.g., word line 100), and thus a control gate of a selected memory cell(s) being programmed is typically biased by programming pulses that start at a voltage of around 16V and may incrementally increase to more than 20V. The unselected word lines (and thus their control gates) for the remaining cells are biased at Vpass. This is typically in an approximate range of 9-10V. The data lines (e.g., bit lines) of the cells 101-103 to be programmed are biased at 0V while the other bit lines are inhibited (e.g., biased, at VCC).
As NAND flash memory is scaled, parasitic capacitance coupling between the selected word line and adjacent word lines becomes problematic. Because of the parasitic coupling, the neighboring cells are more prone to program disturb than the other cells that also share the common bit line with the cells being programmed. This can cause the cells on neighboring wordlines to experience program disturb.
The program disturb condition has two operation modes: boost mode and Vpass mode. During programming, the channels of the inhibited cells 120, 121 along the selected word line 100 are at a positive boost voltage (e.g., 6V) with respect to the control gate and their control gates are at Vpgm (e.g., 19V). During the Vpass mode, the cell's channel is at ground and the gate is at Vpass (e.g., 10V). Accordingly, the cells 120, 121 coupled to the selected word line 100 and inhibited bit lines are influenced by boost mode program disturb. The neighboring cells 110-118 that are coupled to the enabled bit lines experience Vpass mode program disturb.
Program disturb can be reduced during a program operation by biasing all of the unselected word lines of a memory block with a negative voltage followed by a positive Vpass voltage. The selected word line is biased with a programming voltage. However, this procedure can result in an erase disturb condition. For example, if a programmed memory cell's threshold voltage is low enough, the initial negative voltage might reduce that threshold voltage to the point where the memory cell is no longer considered programmed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a way to reduce the effects of erase disturb in a memory device.
USPTO Backgrounds
USPTO Backgrounds