1. Technical Field
The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count.
2. Discussion of Related Art
A time-interleaved analog-to-digital converter (ADC) is an effective system to increase the sampling frequency of an ADC. A time-interleaved ADC system has a plurality of channels in parallel each one running at a different sampling rate from each other. Environmental variation creates mismatch between channels, which further causes a degradation of the signal-to-noise and distortion ratio (SNDR). Offset and gain errors are two well-known errors in a time-interleaved ADC. Offset mismatch leads to a fixed pattern noise in the global ADC system, while the magnitude of the gain error is modulated by the input frequency (fin).
Classical estimation methods of offset and gain errors are based on the manipulation of the output code of the two channels to extract these errors. Classical cost functions needed to estimate offset and gain errors using operators, such as adders and multipliers, and an integrator to average out the signal and extract the error.
The channel output code size depends on the ADC resolution, and sometimes can be quite large (e.g. between −32768 and 32767 for a 16-bit ADC). This means that the cost function is made of very big operators with input signal size of 2res-1 (res is the ADC resolution), and an over-sized integrator with up to a few billion of low significant bit (LSB).
Therefore there is a need for a smaller sized and cost efficient system and method to offer better estimation of offset and gain errors in a time-interleaved analog-to-digital converter.
USPTO Backgrounds
USPTO Backgrounds