Advanced integrated circuit design requires precise control of beam incidence angle. While a number of different types of beam incidence angle error exist, three of the more common types are cone angle error, beam steering error and parallelism error across the wafer. Cone angle error is typically a result of cone angle effects caused by the geometry of the wafer scanning system. Cone angle error causes within wafer variation. For example the beam angle error may be about −x degrees at one edge of the wafer, be approximately zero degrees as the center of the wafer, and be about +x degrees at the opposing edge of the wafer.
Steering error, on the other hand, tends to be a fixed error across the wafer that is introduced while tuning the beam between lots, implant batches, or whenever the tuning may occur. The parallelism error, for whatever reason, leads to random beam incidence angle errors across the width of the wafer. This error is particularly difficult to correct as a result of its random nature.
Unfortunately, without precise control of beam incidence angle, various different problems degrade the transistors of the integrated circuit. As an example, transistor asymmetry, variation, and depressed MPY often result due to beam incidence angle error. The beam incidence angle error also typically leads to gate shadowing and an asymmetric dopant distribution, both of which are undesirable.
Turning to FIG. 1, illustrated is an example of gate shadowing on a transistor device 100. The transistor device 100 illustrated in FIG. 1 includes a gate structure 120, having a height (h), located over a substrate 110. The transistor device 100 illustrated in FIG. 1 is being subjected to a focused implant process 130 to form implant regions 140. As is illustrated, the combination of the focused implant beam incidence angle (θ) and gate structure 120 height (h) causes the implant regions 140 located within the substrate 110 not be placed equidistance from the gate structure 120. For example, one of the implant regions 140 is located a distance (d) from the sidewall of the gate structure 120, where the other implant region 140 is located adjacent the sidewall of the gate structure 120. While the distance (d) can be estimated using the equation d=h tan (θ), it nevertheless creates an undoped/underdoped region defined by the distance (d) that often tends to cause serious operational problems for the transistor device 100.
Accordingly, what is needed in the art is a method for implanting dopants within a substrate that does not experience the drawbacks of the prior art methods and devices.
USPTO Backgrounds
USPTO Backgrounds