1. Field of the Invention
This invention relates to a method of testing electronic circuits and/or semiconductor devices in wafer form and, more particularly, to a method of testing such circuits/devices in wafers having lead-free solder bump contacts.
2. Discussion of the Related Art
In the industry of semiconductor devices (e.g., integrated circuits and discrete devices) it is common to parametrically test the circuits/devices while they are still an integral part of a semiconductor wafer; that is, before the wafer has been diced into individual circuits or chips. To do so, the test apparatus typically includes a probe card, which has a nest of electrical probes that enable the apparatus to make electrical contact with a subset of terminals (e.g., bond pads, solder bumps) on the wafer. Once testing of a subset of terminals is complete, the wafer is moved laterally relative to the probe card (e.g., via a well known stepper machine) so that another subset of terminals can be accessed by the test apparatus. This sequential process is repeated until all of the terminals that need to be tested are in fact probed by the test apparatus.
Two of the most common types of probe cards in the industry are the vertical probe card and the cantilever probe card. FIG. 1 shows a vertical probe card 10 for parametrically testing circuits or devices in a wafer 10.1 via terminals 10.6 (e.g., solder bump contacts) located on a major surface of the wafer. The card 10 includes a printed circuit board (PCB) 10.3 coupled to a probe head 10.2 via a probe router-substrate 10.4. A wafer prober (not shown) moves the wafer 10.1 laterally (arrow 10.7) to position a particular subset of terminals 10.6 under the probe head and then moves the wafer vertically (arrow 10.9) to bring the probes 10.5 into contact with the selected subset of terminals 10.6. Test signals from a controller (not shown) are delivered to the circuits or devices in the wafer via the electrical paths formed by the PCB 10.3, the router-substrate 10.4, the probes 10.5 and the subset of terminals 10.6. Response signals from the tested circuits/devices are received by the controller, stored and then analyzed by a computer.
In contrast, FIG. 2 shows a cantilever probe card 20 for parametrically testing circuits or devices in a wafer 20.1 via terminals 20.6. The card 20 includes a printed circuit board (PCB) 20.3 having an aperture 20.8. A nest of probes 20.5 is disposed within the aperture 20.8, as shown in FIG. 3. A wafer prober (not shown) moves the wafer 20.1 laterally (arrow 20.7) to position a particular subset of terminals 20.6 under the probe head and the moves the wafer vertically (arrow 20.9) to bring the probes 20.5 into contact with the selected subset of terminals 20.6. Test signals from a controller (not shown) are delivered to the circuits or devices in the wafer via the electrical paths formed by the PCB 20.3, the probes 20.5 and the subset of terminals 20.6. As above, response signals from the tested circuits/devices are received by the controller, stored and then analyzed by a computer.
When the semiconductor devices are sensitive to contact resistance, as many are, such parametric testing apparatus has a persistent problem—the probe tips become contaminated and/or worn, necessitating frequent cleaning and/or replacement. Although the vertical probe card design can provide reliable contact resistance and an acceptable number of probe tip cleanings, it is an expensive solution; that is, complex fabrication techniques are required to manufacture the head 10.2 and the router-substrate 10.4. Illustratively, the cost of a vertical probe card is $15,000 to $30,000. On the other hand, cantilever probe cards are less expensive initially (e.g., $3,000 to $4,000), but require frequent probe tip cleanings, which reduces probe tip life. Consequently, the probe nest has to be replaced frequently.
In addition, incorrectly setting the probe cleaning interval can adversely affect yield. Cleaning intervals are usually set assuming a specific distribution of cleaning frequencies and, by inference, the terminal material properties. Yield can be adversely affected by changes in device parameters that are influenced by increased contact resistance; e.g., manufacturing variations in the composition of the terminals can potentially impact the cleaning frequency by the way material accumulates on the probes and the corresponding increase of contact resistance prior to the predicted cleaning interval.
USPTO Backgrounds
USPTO Backgrounds