(a) Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly to an LDD (Lightly Doped Drain) transistor and a fabrication method thereof.
(b) Description of the Related Art
Generally, as semiconductor devices have become more highly integrated, gate widths have become narrower so that an electric field focuses on a drain. This may increase intensity of an electric filed inside a depletion layer that is disposed in a drain of a channel. Accordingly, electrons are accelerated at a high speed, and the accelerated electrons collide with atoms so that an avalanche phenomenon occurs.
At this time, a portion of the accelerated electrons enter a gate oxide film and are captured therein, so that a critical voltage of a semiconductor device is changed. Therefore, a hot electron effect, which causes unstable operation of the semiconductor device, occurs.
Recently, in order to prevent such a hot electron effect, an LDD (Lightly Doped Drain) gate has been used, in which an oxide film or a nitride film remains in a side wall of a gate, and impurity ions are injected, and thereby a conjunction of a low concentration of impurity ions is formed.
Referring to FIGS. 1a and 1b, a method of fabricating the conventional LDD transistor will be explained.
First, a gate oxide film 2 is formed on an active area of a semiconductor substrate 1, and a poly-crystalline silicon layer is then deposited on the gate oxide film 2.
The poly-crystalline silicon layer is etched by a photolithography process to form a gate electrode 3 having a predetermined width. Then, using the gate electrode as a mask, a low concentration of impurity ions are injected into an active area of the semiconductor substrate 1 to form a low concentration impurity area 4, and thereby constituting a source and a drain.
A nitride film is deposited through a chemical vapor deposition process, and it is anisotropically etched through a method such as a reactive ion etching (RIE) method, and thereby a nitride film spacer 5 is formed on a side wall of the gate electrode 3.
Then, using the gate electrode 3 and the nitride film spacer 5 as a mask, a high concentration of impurity ions are injected into the active area of the semiconductor substrate 1, thereby forming a high concentration impurity area 6.
A thermal process is then performed in order to alleviate stress of the substrate 1 caused by the injection of impurity ions, and thereby a MOS device is formed.
However, along with a tendency of high integration of a semiconductor device, a critical dimension (CD) that is determined as a value calculated by summing a width of the gate electrode 3 and a width of the nitride film spacer 5 is also decreased.
Because of the decrease of the critical dimension, a width of a silicide that is formed over the gate electrode 3 is also decreased. Therefore, there is a problem in that resistance of the silicide becomes greater. As a semiconductor device becomes highly integrated, this problem becomes more serious. Thus, a method for decreasing the resistance of the silicide is urgently required.
Furthermore, there is another problem in that when the poly-crystalline silicon layer is etched by the photolithography process to form the gate electrode 3, a desired pattern of the gate electrode is occasionally not acquired. That is, a portion of the polycrystalline silicon (namely, a foot) in a horizontal direction at a lower portion of the side wall of the gate electrode 3 can remain, or the poly-crystalline silicon is over-etched so that a hollow portion (namely, a notch) can be formed. Because such a foot and notch may change a length of a channel, they disturb stable operation of the device.
Still furthermore, there is a problem in that it is quite difficult to regulate a width of the spacer when the nitride film is anisotropically etched in order to form the nitride film spacer.
The present invention has been made in an effort to solve the above problems.
It is a motivation of the present invention to provide an LDD MOS transistor in which resistance of a silicide has been decreased, and a fabrication method thereof.
Another motivation of the present invention is to decrease a foot or a notch in a gate electrode, in order to prevent a malfunction of a semiconductor device.
Still another motivation of the present invention is to downsize an LDD MOS transistor.
In a preferred embodiment of the present invention, the semiconductor device comprises a gate oxide film, a gate electrode, a nitride film, a low concentration impurity area, and a high concentration impurity area. The gate oxide film is formed on a semiconductor substrate. The gate electrode is formed on a predetermined region of the gate oxide film, and an upper portion thereof is wider than a lower portion thereof by a predetermined width. The nitride film is formed at a side of the lower portion of the gate electrode, and a width thereof is equal to the predetermined width. The low concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode. The high concentration impurity area is formed within the semiconductor substrate except at a portion thereof under the lower portion of the gate electrode.
It is preferable that the gate electrode is made of a poly-crystalline silicon.
It is also preferable that an upper surface of the gate electrode is level.
Preferably, a side surface of the upper portion of the gate electrode and a side surface of the nitride film form one straight line.
It is preferable that the semiconductor device is a lightly doped drain (LDD) MOS transistor.
In another preferred embodiment of the present invention, the method for fabricating a semiconductor device comprises: forming a gate oxide film on a semiconductor substrate; forming a first photo-resist film pattern having a predetermined width on the gate oxide film, and then injecting a low concentration of impurity ions into an exposed portion of the semiconductor substrate by using the photo-resist film pattern as a mask; removing the first photo-resist film pattern, and forming a nitride film pattern on the gate oxide film except at a portion where the first photo-resist film pattern was positioned so that the nitride film pattern is provided with an opened portion; forming a poly-crystalline silicon layer over all the nitride film pattern and an exposed portion of the gate oxide film; partially etching the poly-crystalline silicon layer and the nitride film pattern such that an end portion having a predetermined width of the nitride film pattern near the opened portion thereof remains, and a portion of the poly-crystalline silicon layer over the exposed gate oxide film and over the remained portion of the nitride film pattern remains; and injecting a high concentration of impurity ions into the semiconductor substrate by using the nitride film pattern and the poly-crystalline silicon layer that remain after etching, as a mask.
It is preferable that the step of partially etching the poly-crystalline silicon layer and the nitride film pattern comprises: etching the poly-crystalline silicon layer such that a portion of the poly-crystalline silicon layer on the exposed portion of the gate oxide film and a portion of the poly-crystalline silicon layer over some portion of the nitride film pattern near the opened portion thereof remain; and etching the nitride film pattern by using the remaining poly-crystalline silicon layer as a hard mask.
Preferably, in the step of etching the nitride film pattern, the etching is carried out under a condition in that the nitride film pattern is more easily etched than the polycrystalline silicon layer.
It is also preferable that after the step of etching the nitride film, an upper surface of the poly-crystalline silicon layer is leveled.
It is preferable that the nitride film pattern is formed over all the gate oxide film, a second photo-resist film pattern whose phase is opposite to that of the first photo-resist film pattern is formed, and then the exposed nitride film pattern is etched by using the second photo-resist film pattern as a mask.
Preferably, in the step of injecting a high concentration of impurity ions, a cap oxide film is formed over all the semiconductor substrate, and a high concentration of impurity ions are then injected from an upper portion of the cap oxide film.
USPTO Backgrounds
USPTO Backgrounds