Known conventional processor systems can include processors, or cores, connected via a common bus to shared memory, and to user interfaces, wireless transceivers, and other shared resources. In certain applications, power can be conserved by powering down and powering up processors in response to changing applications, tasks, and periods of non-use, e.g., time outs. Certain applications of power-down and power-up can also be referred to, respectively, as entering a “sleep state” and “wake-up” from a sleep state.
In certain applications, power-down/power-down of a processor can incur costs in terms of time to recover a processor state. In certain applications, the time cost may be incurred not only by the processor undergoing the power-down/power-up, but also by, for example, other processors and process flows within and interfacing the processor system.
Storing the processor state in a memory is one known, conventional technique directed to reducing the time lost to recovering the processor state upon wake-up.
However, such conventional techniques have various shortcomings. One shortcoming is security. If the memory is external to the processer, with shared accessibility, there may be vulnerability to unauthorized access. If the memory is internal to the processor, then flexibility may be compromised because authorized external access to the stored processor state, for example, while the processor is in a sleep state, may be difficult and/or costly to implement.
USPTO Backgrounds
USPTO Backgrounds