1. Field
Example embodiments relate to a method of programming a flash memory device, and for example, to a method of programming a flash memory device to more efficiently reduce threshold voltage dispersion in a programming state.
2. Description of Related Art
Floating gate type flash memories are commonly used as larger capacity non-volatile memories. In order to operate, the floating gate type flash memories store charges in floating gates formed of polysilicon.
A memory cell of a floating gate type flash memory may be classified into a single level cell (SLC) in which two recording states “1” and “0” are recorded and a multi-level cell (MLC) in which four or more recording states, e.g., “11,” “10,” “01,” and “00,” are recorded.
MLC technology is used to make NAND and NOR type flash memories of larger capacity.
In a MLC operation, dispersion of threshold voltages Vth of cells respectively corresponding to recording states must be relatively lower to separately recognize the recording states.
A flash memory device may use an Incremental Step Pulse Programming (ISPP) method of uniformly increasing a program voltage Vpgm and repeatedly applying the increased program voltage to reduce the threshold voltage dispersion between cells.
As is well known, in the ISPP method, program voltage pulses are applied with a progressive magnitude increase of ΔVpgm. A process of applying verifying voltage pulses to verify a threshold voltage of a memory cell is repeated to allow the threshold voltage of the memory cell to reach a desired, or alternatively, a predetermined value. A plurality of memory cells constituting a flash memory may have an initial threshold voltage dispersion. Therefore, the ISPP method has been introduced to allow the plurality of memory cells to reach desired, or alternatively, predetermined threshold voltages in consideration of the initial threshold voltage dispersion of the memory cells.
However, coupling between cells, for example, coupling between floating gates, increases with reductions in sizes of cells of a flash memory using a floating gate. Therefore, controlling the dispersion of a threshold voltage is more difficult.
In order to reduce the coupling between cells, charge trap flash (CTF) memories, which use insulating layers trapping charges instead of floating gates, e.g., Si3N4 layers configured to store charges, have been developed.
However, in a CTF memory which uses an insulating layer to trap chargers, after programming is performed, charges trapped in a charge trap layer migrate. Therefore, a threshold voltage value varies with time after programming is performed.
The variation of the threshold voltage value with time makes control of the dispersion of the threshold voltage value more difficult if programming is performed using the ISPP method.
If a threshold voltage varies with time as described above, an error occurs in an operation of performing programming and verifying a programmed state after a desired, or alternatively, a predetermined time elapses.
The dispersion of a threshold voltage value in a programming state in the ISPP method increases due to the verifying error.
For example, if the threshold voltage varies with time, the threshold voltage may reach a target value after further time elapses. However, even in this case, an error of verifying that a memory cell has not reached a target threshold voltage may occur. If the memory cell is verified to have not reached the target threshold voltage, a program voltage increased by ΔVpgm is applied to program the memory cell. Therefore, an over program in which the threshold voltage increases occurs. Accordingly, dispersion of the threshold voltage in the programming state increases.
USPTO Backgrounds
USPTO Backgrounds