1. Field of the Invention
This invention relates to a semiconductor device and to a manufacturing method of a semiconductor device, and in particular relates to a MOSFET with a three-dimensional structure in which a MOS structure portion is formed in a direction perpendicular to a semiconductor substrate.
2. Description of the Related Art
In the prior art, horizontal-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), formed in a planar manner on a substrate, and TFTs (Thin Film Transistors), in which silicon is evaporation-deposited on a substrate, are well-known. MOSFETs and TFTs have evolved, accompanying demands for device miniaturization, with smaller element pitches through reduced gate lengths (hereafter “L lengths”), as well as the ability to pass larger currents by increasing gate widths (hereafter “W lengths”). Here the gate length is the length of the gate electrode in the direction in which carriers move between source and drain, and the gate width is the length of the gate electrode in the direction perpendicular to the gate length.
However, because of the need to secure a breakdown voltage for the element, there are limits to the extent to which the L length can be reduced. And, in a planar-structure device there is a limit to the extent to which the W length can be increased. On the other hand, among discrete type MOSFETs, vertical type MOSFETs are known in which the drain and source are formed above and below the substrate, and current flows perpendicularly to the substrate.
Further, a trench lateral power MOSFET (TPLM) is known, in which a gate electrode is formed on a trench side wall, and current flows from the upper face of the substrate toward the trench bottom face (for example, see Japanese Patent Laid-open No. 2006-216863). FIG. 16 is an explanatory diagram showing the cross-sectional structure of a trench lateral power MOSFET. As shown in FIG. 16, the trench lateral power MOSFET 1600 is provided with an n-type well region 1602 in the surface region of a p-type semiconductor substrate 1601. A trench 1605 is formed from the substrate surface in the well region 1602. And, an n-type extended drain region 1603 to serve as a drift region is formed so as to surround the bottom portion of the trench 1605.
A high-concentration n-type drain region 1606 is provided in the substrate surface layer on the side of the trench 1605. Between the n-type drain region 1606 and the extended drain region 1603 is provided an n-type offset region 1608. And, on the opposite side of the trench 1605 from the n-type drain region 1606 is provided a p-type offset region 1604 to serve as the channel region, in contact with the extended drain region 1603. In the substrate surface layer of the offset region 1604 is provided a high-concentration n-type source region 1607, in contact with the trench 1605.
Further, in the trench 1605, on the side wall on the side in contact with the offset region 1604, are provided a gate oxide film 1613 to become the gate insulating film and a gate polysilicon electrode 1611 to serve as the gate electrode. In the trench 1605, on the side wall on the side in contact with the n-type drain region 1606, are provided a field plate oxide film 1614 to serve as a field plate insulating film and a field plate 1612. And, an interlayer insulating film 1615 fills between the gate polysilicon electrode 1611 and the field plate 1612.
In a trench-type MOSFET, the structure in the length direction of an ordinary MOSFET is formed perpendicularly to the substrate. Consequently in a trench-type MOSFET the element pitch can be made small compared with an ordinary MOSFET, so that the W length of the entire element can be increased. Also, because the current flowing in the element is proportional to the W length, in a trench lateral MOSFET the on resistance can be made smaller.
If it were possible to form an element with a structure in which the W length was extended in the substrate interior direction, then the W length of the overall element could be made markedly longer, and a device with a low on resistance could be formed. Based on this concept, MOSFETs with three-dimensional structures, such as Fin-gate MOSFETs and similar devices, have been developed (see for example Japanese Patent Laid-open No. 51-147269, Japanese Patent Laid-open No. 2005-136150 (corresponding to U.S. Pat. No. 6,921,942 B2), and Japanese Patent Laid-open No. 2002-26311 (corresponding to U.S. Pat. No. 6,469,349 B2 and one other)).
For example, in the case of a 20 V-class device, the pitch of a planar DMOSFET is 4 μm, and the pitch of a trench lateral power MOSFET is 2.5 μm. On the other hand, in the case of MOSFETs with a three-dimensional structure, if the two dimensions along the substrate surface are the X direction and the Y direction, and the substrate internal direction is the Z direction, then the pitch in the X direction is the same 4 μm as for a planar device, and the pitch in the Y direction is 1.5 μm. The Y-direction pitch is smaller than the pitch for a trench lateral power MOSFET because there is no need to perform ion implantation to form the source region and drain region. In this case, if the drain-gate depth (Z-direction dimension) is 1.5 μm, then the W length is the same as for a planar device. And, if the trench gate depth is 2.4 μm, then the W length is the same as for a trench lateral power MOSFET. Hence if the trench gate depth is 5 μm, then a W length twice that of a trench lateral power MOSFET can be secured.
However, a Fin gate MOSFET requires that accurate patterning be performed within the trench, and there is the problem that as the trench aspect ratio rises, fine device formation becomes impossible. Further, in order to increase the device W length, a deep trench must be formed; but in order to keep the aspect ratio from becoming high, the trench width must also be made broad. As a result, there is the problem that in a Fin gate MOSFET the density of the MOS structure which can be formed on trench side walls is decreased, and the area efficiency is worsened.
USPTO Backgrounds
USPTO Backgrounds