Semiconductor Dies; In General
Improved methods for miniaturization of semiconductor dies have permitted the integration of millions of transistor circuit elements into a single silicone embodied circuit. Such a circuit is typically referred to as an integrated circuit chip or a semiconductor die.
Semiconductor dies are created from a silicon wafer through the employment of various etching, doping and depositing steps that are well known in the art. Ultimately, the semiconductor die is encapsulated so as to form an "integrated circuit package" having a variety of pin-out or mounting and interconnection schemes. For convenience, an integrated circuit package is hereinafter referred to as an "IC package." More sophisticated IC packages have been developed for very large scale integration ("VLSI") semiconductor dies that can accommodate the increased number of external connections required with an electronic system.
PGA and BGA Packaging
VLSI integrated circuit packages having high connection capacity are, for example, pin grid array ("PGA") and ball grid array ("BGA") type packages. Both PGA and BGA type packages, including adaptations thereof for surface mount and hybrid applications, employ one or more printed wiring boards (hereinafter referred to as "PWBs"). Such PWBs consist of, for example, polyimide, glass reinforced epoxy, ceramics, or other materials known to those skilled in the art of fabricating very large scale IC packages. Some of the PWBs have material cut out from the middle which when laminated together form a cavity in which the semiconductor die may be placed.
The PGA and BGA packages differ mainly in that a PGA package utilizes conductive metal pins that may be either soldered to a system printed circuit board or inserted into a matching socket which is already soldered to the system printed circuit board. In contrast, BGA packages utilize "solder balls" instead of metal pins. The solder balls of a BGA package reflow to connection points on a system printed circuit board when heated to a certain temperature, thus, electrically connecting the circuitry within the BGA IC package to an external electronic system.
Connections are made from bond pads of a semiconductor die to contact pads of PWBs, and then to conductive metal patterns of the PWBs. Conductive metal patterns further connect to either the connection pins or connection solder balls of the PGA or BGA package, respectively. Thus, the PGA or BGA package is a miniature multi-layer printed circuit board system containing the semiconductor die and forming a housing for protection of the die. The semiconductor die is further protected by an encapsulant such as plastic or epoxy material.
Examples of semiconductor die fabrication for VLSI IC packages are more fully illustrated in co-pending U.S. patent application Ser. No. 07/917,894 entitled "Ball Bump Grid Array Semiconductor Packages" by Michael Rostoker, Chok J. Chia, Mark Schneider, Michael Steidl, Edwin Fulcher and Keith Newman, filed on Jul. 21, 1992, and assigned to LSI Logic Corporation, the disclosure of which is incorporated by reference herein for all purposes.
Single Tier Packages Formed by Plastic Molding Techniques
Currently known IC packages, which are packaged by plastic molding techniques, provide for a "single bonding tier." A typical BGA type IC package having a single bonding tier is illustrated in FIG. 1. Referring to FIG. 1, IC package 100 is illustrated. IC package 100 includes a semiconductor die as indicated by reference numeral 102.
Semiconductor die 102 is disposed on die pad 108. Die pad 108 is centrally placed upon PWB 104. Thermal vias 112 serve to dissipate the heat generated from semiconductor die 102. Semiconductor die 102 has bond pads 110 on its face for connection therewith. Bond wires 114 extend from bond pads 110 to related contact pads (not illustrated) that are disposed on PWB 104.
PWB 104 has a layer of traces disposed on its top surface. Such traces are denoted by top side layer 106. Top side layer 106 connects contact pads (not illustrated) of PWB 104 to conductive vias 116 that are located near the periphery of PWB 104. Vias 116 extend from top side layer 106, through PWB 104 to a layer of traces located on the bottom side of PWB 104. The bottom side layer is indicated by reference numeral 120. In this manner, signals to and from semiconductor die 102 are passed through bond pads 110, through bond wires 114, through contact pads of PWB 104, through top side layer 106, through vias 116, to bottom side layer 120.
Bottom side layer 120 further connects with sites (also referred to as "pads") as indicated by reference numeral 122. In turn, sites 122 are coupled to solder balls 124. Solder balls 124 are the points at which IC package 100 is connected with external circuitry. Semiconductor die 102, as well as the connections deriving therefrom, are encapsulated with molding compound 118.
Referring to FIG. 2, a bottom view of IC package 100 is illustrated. A bottom view of IC package 100 reveals bottom side layer 120. Bottom side layer 120 is composed of a series of traces. Such traces are indicated by reference numerals 202. Traces 202 originate at vias 116, which are located on the periphery of PWB 104, and terminates at sites 122. Sites 122 are arranged in a rectangular array of evenly spaced rows and columns. As best viewed in FIG. 1, each site 122 is provided with a solder ball 124. Solder balls 124 constitute the external connections for IC package 100. Bottom side layer 120 also includes ground plane 204, with connected ground vias 206, in order to supply semiconductor die 102 with a ground potential.
A package having a single PWB, as exemplified by IC package 100, only provides for connections between a semiconductor die and a PWB to be made on one surface or plane. Such a surface is referred to as a single bonding tier. Single bonding tiers are also found in IC packages having multiple PWBs. That is, multiple PWBs can be laminated directly above one another. Connections between the multiple PWBs and a semiconductor die are established on the top surface of the top level PWB.
A single bonding tier fails to satisfactorily accommodate a substantial number of connections between a semiconductor die and one or more PWBs. A single bonding tier requires contact pads, which are to be connected to a semiconductor die, to be placed in an array on a single surface that surrounds the semiconductor die. When a substantial number of contact pads are involved, however, the perimeter of this array of contact pads becomes relatively large. Consequently, long bond wires must be utilized to complete connections between the semiconductor die and the distant array of contact pads. The use of an enlarged semiconductor die, to extend to the array of contact pads, is disadvantageous and thus not a solution.
An array of contact pads can include the placement of contact pads in a single strip that surrounds a semiconductor die. Alternatively, an array of contact pads can consist of multiple strips of contact pads that are interleaved with respect to one another. The employment of multiple strips of contact pads results, however, in severe via routing constraints.
A further disadvantage is encountered with a single bonding tier. Ideally, bond wires travel from a bond pad to a corresponding contact pad in a path that is perpendicular to the periphery of the semiconductor die. That is, each bond pad ideally has a contact pad directly across from it so that all bond wires are parallel with one another. This is difficult, if not impossible, to accomplish when a substantial number of contact pads are placed in an array on a single bonding tier. Due to the width of each contact pad in the array, bond wires must "fan out" at significant angles from one another to connect the smaller bond pads with the wider contact pads. Such a significant "effective pitch" between bond wires is undesirable and preferably reduced.
Accordingly, IC packages which require a substantial number of connections between a semiconductor die and one or more PWBs, are not accommodated through a single bonding tier.
Multiple Bonding Tiers
In order to overcome the shortcomings of a single bonding tier, multiple bonding tiers have been employed. An IC package having multiple bonding tiers is constructed by indenting multiple PWBs from one another. IC packages having multiple bonding tiers have been conventionally formed by fully encapsulating the cavity, wherein the semiconductor die is disposed, with a "glob-top" encapsulant. In particular, a "glob top" encapsulant of epoxy is often employed to fully encapsulate a cavity. IC packages with multiple bonding tiers have also been formed by placing a ceramic lid over an unencapsulated (where an epoxy seal is applied to the ceramic lid ) or partially encapsulated cavities (where a conformal coating is used to coat the semiconductor die). Such unencapsulated and partially encapsulated IC packages are, however, more susceptible to reliability failure (due to the collection of moisture) and have poor thermal attributes when compared to those which are fully encapsulated with epoxy.
IC packages, which have multiple bonding tiers and are fully encapsulated with epoxy, suffer from several shortcomings which are desired to be alleviated or reduced. First, epoxy encapsulated IC packages are difficult and time consuming to manufacture. As a consequence, the cost of manufacturing IC packages that have multiple bonding tiers and an epoxy encapsulant is relatively high. Second, voids of air are difficult to remove from an epoxy encapsulant. Moisture, which tends to collect in unremoved air voids, can result in mechanical failures such as cracking and catastrophic fatigue, as well as other failures such as corrosion. Third, epoxy encapsulated IC packages lack well defined uniform geometries and dimensions. This results from the shrinking of epoxy when it is cured so that the final shape of the epoxy encapsulated IC package is difficult to control. Uniform geometries and dimensions are, however, necessary for proper handling, installation, testing and fixturing of an IC package. Fourth, the depth or thickness of IC packages is difficult to control when encapsulated with epoxy. IC package thickness is critical for applications such as memory cards and micro-miniature products, as well as for situations where metal pins and balls (of PGA and BGA packages, respectively) require certain clearances or where an IC package requires a certain elevation ("stand-off") from a system printed circuit board.
In sum, IC packages that have a single bonding tier fail to accommodate a substantial number of connections between a semiconductor die and multiple PWBs. Moreover, currently known IC packages that have multiple bonding tiers suffer from several shortcomings that are associated with epoxy encapsulants. Thus, what is needed is an IC package that can accommodate a substantial number of connections from a semiconductor die, while being readily and cost efficiently manufactured, substantially free of air voids, with uniform dimensions and geometries and in variable thicknesses.
USPTO Backgrounds
USPTO Backgrounds