1. Technical Field
This invention relates to multiprocessor systems and, more particularly, to an improved secondary interconnection network in a multiprocessor system having a plurality of processor elements, memories, and a primary interconnection network.
2. Description of the Related Art
Computer and Digital Signal Processing (DSP) Systems may be composed of multiple processing elements (PE), supporting memory (SM), data interconnection networks (IN), and input and output (I/O) interfaces. With multiple PEs available, the system may support parallel algorithms to complete tasks more quickly or to reduce the energy to complete a task. Parallel algorithms often require streaming of data at very high rates between PE and SM across the system and into and out of the system. In these systems the interconnection networks generally include at least one high bandwidth (high bit per second throughput) primary interconnection network (PIN). The PIN is optimized for high bit per second throughput of relatively large messages, but not especially low latency (point to point delivery delay).
At least one prior art multiprocessor system including a PIN has also included an additional low bandwidth secondary interconnection network (SIN). A high latency type SIN, implemented as a “serial bus” (SB) has previously been implemented on a multiprocessor IC chip referred to as the HyperX hx3100A made by Coherent Logix, Inc., the assignee of the present application. FIG. 1 illustrates the prior art serial bus (SB), also referred to as the secondary interconnection network (SIN), implemented on the HyperX hx3100A. The prior art SIN shown in FIG. 1 was designed to be embedded in a multiprocessor IC chip along with a PEs, SMs, PIN, chip I/O interfaces, power grid, and clocking network. As shown, this serial bus architecture interconnected all PEs and SMs in a long loop that meandered back and forth across the chip. This allowed the SIN to support guaranteed message delivery (GMD) with minimum area and power dissipation. The SIN was thus an on-chip serial bus (SB) first aimed at providing debug support for programmers of application and system software. In addition, the SB was capable of being used during system boot-up to load memories and perform power-on system tests. Also, the SB could be used during runtime to perform various system administration functions such as control of clock frequencies for individual PE and I/O ports, setting security barriers in the PIN, and PE message passing. Lastly, the SB could also be used in IC test and evaluation.
The prior art SIN shown in FIG. 1 had a serial bus (SB) architecture organized as a unidirectional daisy chain of links between local interface units with both ends of the chain coupled to a serial bus controller (SBC) unit. As illustrated in FIG. 1, a typical local interface unit is labeled as serial bus slave (SBS) interface unit; so called because is cannot issue commands (as described in more detail below). Each SBS interface unit is coupled to one PE, one SM unit, one SB input link, and one SB output link. Each SBS unit was assigned a unique address value so that individual messages could be sent to particular SBS units. Each SBS interface unit (SBS-IU) contained registers and logic to translate message formats between the predominately word-parallel formats of the PE and SM to the predominately bit-serial formats of the SB links. Each link between interface units was 2 parallel wires, with one wire carrying a data signal (SBDATA) and the other a clock signal (SBCLK) to capture the data at a receiver input flip-flop. The presence of a message was indicated by multiple pulses on SBCLK, one pulse for each data bit on SBDATA; and the absence of a message was indicated by a constant value on SBCLK.
In some embodiments, the SBS-IU may be configured with a buffer to receive a SB message of fixed length. Initially (upon chip reset), the SBS-IU may enter repeater mode wherein it may receive a SB message of fixed length and compare the address in the message header to its own unique address. If there is no address match, the SBS-IU may pass the message on to the next SBS-IU in the chain. In the case of an address match, the SBS-IU may enter channel mode where subsequent messages are treated as possible commands until it receives a command to return to repeater mode. The SBS-IU may be configured to decode a set of commands from properly-encoded SB messages. If an SB message is not properly encoded for one of the set of commands, then the SBS-IU ignores it. In various embodiments, the commands: Read and Write SBS-IU configuration register, (reset DMR, reset PE, set clock frequency of PE, reset I/O circuits if present, and set PIN router security barriers), Read and Write SM at a specific address or a block of addresses, Read and Write PE registers including message register under certain conditions, set PE breakpoint, force PE break, single step PE, wakeup PE (let run), and enable/disable PE participation in global break signaling. For Read commands the SBS-IU may generate a return SB message containing the read out data and sends it to the next SBS-IU in the chain. The return SB message may pass through the other SBS-IU in the chain (because they are in repeater mode); and may be forwarded by the SBC to the controller that set up the channel.
As illustrated in FIG. 1, the Serial Bus Controller (SBC) is coupled to both ends of the SB, to the Debug Access Port (DAP) Controller, and to the Boot Controller. The SBC accepts SB messages from the DAP and Boot controllers, and provides return messages back to them. The main purpose of the SBC is to prevent more than one controller at a time from gaining SB access, which may produce random mixing of commands and erroneous results. If the SB is quiescent, then either controller may initiate a channel to a SBS-IU. If a channel is already present the SBC controller will ignore any new attempts to initiate a channel until the current one ends. If two controllers attempt to initiate channels at the same time, then the SBC will arbitrate so that one gains access and the other SBC is ignored.
To permit PE 0,0, as depicted in FIG. 1, to send messages to the SBC and receive result messages back from the SBC, some registers special to DMR 0,0 are coupled to the Boot Controller. These special registers in DMR 0,0 are not accessible by the PIN, nor by any PE other than PE 0,0. When a particular register in DMR 0,0 is written by PE 0,0, a message is transferred to the SBC. Return SB message data from SBC may be copied to particular registers in DMR 0,0. The software program on PE 0,0 that makes use of the SB may need to include appropriate delays to wait for the relatively long latency of the SB message transport.
An improved secondary interconnection network (SIN) architecture is desired for use in multiprocessor systems.
USPTO Backgrounds
USPTO Backgrounds