The present invention relates to a method of fabricating an image sensor. More particularly, the invention relates to a method of fabricating an X-ray detector array including a plurality of pixels each including a storage capacitor and a switching thin film transistor (TFT).
Electronic matrix arrays find considerable application in X-ray image sensors. Such devices generally include X and Y (or row and column) address lines transversely and longitudinally spaced apart and across at an angle to one another, thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are memory cells or pixels of an electronically adjustable memory array or X-ray imaging array.
Typically, at least one switching or isolation device such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed by the application of suitable potentials between respective pairs of the X and Y address lines. Thus, the TFTs and diodes act as switching elements for energizing or otherwise addressing corresponding memory cells or storage capacitors.
Imagers including arrays of pixels are known in the art, as in U.S. Pat. Nos. 6,020,590, 6,060,714, and 6,124,606, the disclosures of which are incorporated herein by reference. For example, U.S. Pat. No. 6,060,714 discloses an X-ray imager including an array of pixels where each pixel includes a TFT and a storage capacitor including two capacitance portions Cs. See also prior art FIGS. 1, 2A, 2B and 2C.
In FIG. 1, a known X-ray detector for capturing digital radiographic images is illustrated. The X-ray detector includes a plurality of pixels 3 each including a switching thin film transistor (TFT) 5 and a storage capacitor 7. The storage capacitor 7 in each pixel includes a charge collector electrode 4 which functions as a top plate of the storage capacitor, and a pixel electrode 11 which functions as a bottom plate of the capacitor.
FIG. 2A is a top view on an X-ray detector pixel of the prior art. FIG. 2B is a sectional view taken along line C-C′ of FIG. 2A. As shown in FIGS. 2A and 2B, each pixel of the prior art includes a substrate 200, a gate electrode 205, a gate line 206, a first gate insulation layer 210, a bottom electrode (a pixel electrode) 215, a second insulation layer 220, an α-Si layer 225, an n+α-Si layer 230, a first via hole 235, a source electrode 240, a drain electrode 245, a data line 250, a common line 255, a planarization layer 260, a second via hole 265, a third via hole 270, a fourth via hole 275 and a top electrode (a charge collector electrode) 280. In addition, symbol Cs indicates a storage capacitor.
The method for fabricating the above comprises seven steps of photolithography and etching. That is, the prior art needs seven reticles or masks. The processing steps are concisely described as follows.
The first photolithography step defines the gate electrode 205 and the gate line 206.
The second photolithography step defines the bottom electrode (a pixel electrode) 215.
The third photolithography step defines the α-Si layer 225 and an n+α-Si layer 230 to obtain a semiconductor island structure.
The fourth photolithography step defines the first via hole 235.
The fifth photolithography step defines the source electrode 240, the drain electrode 245, the data line 250 and the common line 255.
The sixth photolithography step defines the second via hole 265, the third via hole 270 and the fourth via hole 275.
The seventh photolithography step defines the top electrode (a charge collector electrode) 280.
Nevertheless, the method of the prior art has some drawbacks. For example, the dielectric layer of the storage capacitor Cs is the same as the second insulation layer 220 of the TFT, thus, a difference in material thicknesses can not be attained. The storage capacitor Cs is not disposed above the common line 255, thereby wasting space. Since the bottom electrode (a pixel electrode) 215 electrically connects under the common line 255, the method of the prior art is not suitable for gray-tone photolithography of the TFT. Additionally, referring to FIG. 2C, when a passivation layer 290 is formed between the planarization layer 260 and the TFT to-protect the channel of the TFT, an extra photolithography process is needed to pattern the passivation layer 290 to form a via hole 295. Thus, the conventional method actually uses eight steps of photolithography.
USPTO Backgrounds
USPTO Backgrounds