The present invention relates to an electrically rewritable semiconductor memory device.
Conventionally, there is known an electrically erasable and programmable read only memory (EEPROM) which can be formed with relatively high density. The description with respect to a memory cell constituting this EEPROM is shown in, for example, "IEEE Journal of Solid-State Circuits", Vol. SC-17, No. 5, pp. 821-827, (1982). FIG. 1 shows an example of a memory cell of this kind. This memory cell comprises a selection MOS transistor TR1 whose drain is connected to a bit line BL, and a floating gate MOS transistor TR2, which has a floating gate FG1, and whose drain and source are respectively connected to a source of the MOS transistor TR1 and a source line SL. A selection gate SG1 of the MOS transistor TR1 is connected to a word life (not shown), while a control gate CG1 of the MOS transistor TR2 is connected to an external control circuit (not shown).
FIG. 2 schematically illustrates a cross sectional structure of a semiconductor memory device having the MOS transistors TR1 and TR2. This semiconductor memory device includes a p-type substrate 1, n.sup.+ -type regions 2 to 4 formed in the surface area of this p-type substrate 1, the floating gate FG1 formed through an insulating layer 5A over a local region 1A of the substrate 1 between the n.sup.+ -type regions 2 and 3, the control gate CG1 formed through an insulating layer 5B over the floating gate FG1, and the selection gate SG1 formed through an insulating layer 5C over a local region 1B of the substrate 1 between the n.sup.+ -type regions 3 and 4. The control gate CG1, floating gate FG1, and n.sup.+ -type regions 2 and 3 constitute the MOS transistor TR2, while the selection gate SG1 and n.sup.+ -type regions 3 and 4 constitute the MOS transistor TR1. The bit line BL is coupled to the n.sup.+ -type region 4 serving as the drain of the MOS transistor TR1 and is formed to extend over the gates CG1 and SG1. The capacitance between the gates CG1 and FG1 is set to C1; the capacitance between the floating gate FG1 and the n.sup.+ -type region 2 is set to C2; the capacitance between the floating gate FG1 and the local region 1A of the substrate 1 is set to C3; and the capacitance between the floating gate FG1 and the n.sup.+ -type region 3 is set to C4. In this case, this semiconductor memory device is formed so as to meet the following condition. EQU C1&gt;C2+C3+C4 (1)
The operation of the semiconductor memory device shown in FIGS. 1 and 2 will now be described. The erasing operation is executed by applying a high voltage VP of, e.g., 16 to 21 V to the selection gate SG1 and control gate CG1 and by setting the bit line BL and source line SL to 0 V. In this case, the MOS transistor TR1 is made conductive, the source and drain regions 2 and 3 of the MOS transistor TR2 are held to 0 V, the voltage VP is applied to the control gate CG1, and also C1&gt;C2+C3+C4; therefore, a higher voltage than the voltage between the floating gate FG1 and the control gate CG1 is applied between the floating gate FG1 and the n.sup.+ -type regions 2 and 3. Since the insulating layer 5A is formed extremely thin to about 100 .ANG., a current called a Fowler Nordheim current flows from the floating gate FG1 to the n.sup.+ -type regions 2 and 3, so that electrons are trapped in the floating gate FG1.
The writing operation is executed by applying the voltage VP to the selection gate SG1; the voltage 0 V to the control gate CG1; the voltage VP to the bit line BL; and the voltage of 5 V to the source line SL. In addition, in this case, instead of applying the voltage of 5 V to the source line SL, it may be also held in the floating state. Even in this case, a high voltage is applied between the floating gate FG1 and the n.sup.+ -type regions 2 and 3, so that the electrons stored in this floating gate FG1 are drained through the drain region or n.sup.+ -type region 3, causing the quantity of electrons in this floating gate FG1 to be reduced. Therefore, the threshold voltage of the MOS transistor TR2 decreases and has a threshold value of, e.g., -5 V. Namely, this MOS transistor TR2 operates as the depletion type MOS transistor. The reason why the voltage of 5 V was applied to the source line SL or it was held in the floating state is to interrupt the unwanted current flowing from the drain region of the MOS transistor TR2 to the source region.
In the semiconductor memory device shown in FIG. 2, since the source line SL is held to the potential of 5 V or in the floating state upon writing, a voltage is applied between this source line SL and the floating gates of the non-selected memory cells coupled to this source line SL, lowering the charge holding property of these non-selected memory cells. Namely, the electrons in this floating gate flow out gradually due to the voltage applied between the source region of the non-selected memory cell and the floating gate, thereby causing the memory data to be changed.
In addition, in the semiconductor memory device shown in FIG. 2, the thin insulating layer 5A having a thickness of 100 to 200 .ANG. can be formed by thermally oxidizing the monocrystalline silicon or substrate 1; however, since the insulating layer 5B is the oxide film of polycrystalline silicon, a thin layer cannot be formed, so it is formed to have the thickness of, e.g., 800 .ANG.. Consequently, to meet the condition (1), for example, as shown in FIG. 3, it is required to enlarge that portion of the floating gate FG1 which faces the control gate CG1 so as to increase the capacitance C1 between the floating gate FG1 and control gate CG1. Therefore, a large occupying area is necessary to form the floating gate FG1 and control gate CG1, causing difficulty in realizing higher integration.
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