A typical package for a semiconductor chip includes an internal leadframe, which functions as a substrate for the package. The leadframe includes a central metal chip pad and a plurality of leads. A body of a hardened, insulative encapsulant material covers the chip, chip pad, and an inner portion of each of the leads. The encapsulant material is provided both above and below the chip pad and leads.
The semiconductor chip is mounted on the chip pad and is electrically connected to the leads. In particular, the chip includes a plurality of bond pads, each of which is electrically connected by a conductor (e.g., a wire) to an encapsulated inner portion of one of the leads. An outer portion of each lead extends outward from the body of encapsulant material, and serves as an input/output terminal for the package. The outer portion of the leads may be bent into various configurations, such as a J lead configuration or a gull wing configuration.
Lately, practitioners have attempted to make packages thinner by providing the chip pad and leads at a bottom surface of the body of encapsulant material, rather than in the middle of the body of encapsulant material. Such packages enjoy a lower height than the standard leadframe packages mentioned above, since there is no encapsulant beneath the chip pad and leads.
In addition, there is a demand for smaller and smaller packages. Leadframes for such packages have themselves become smaller and thinner.
USPTO Backgrounds
USPTO Backgrounds