1. Field of the Invention
The invention relates to an integrated push-pull output stage for generating a pulse-like output signal in dependence upon a pulse-like input signal comprising complementary output field-effect transistors which are formed by respect first and second groups of parallel-connected subtransistors the subtransistors in each group being of the same conductivity type and opposite from that of the subtransistors in the other groups.
2. Description of the Prior Art
In integrated semiconductor circuits which have been developed specifically for obtaining high switching speeds parasitic inductances of the supply lines to the active circuit elements have proved particularly disadvantageous because they prevent implementation of the theoretically possible high switching speeds in practice. In particular, in the output stages of integrated circuits in which relatively high currents flow, in the parasitic line inductances in highspeed switching operations, thus for example in high speed switching between a high voltage level and a low voltage level, high voltage peaks are generated which lead to a strong overshooting at the pulses furnished by the respective output stage. The overshooting can lead to erroneous output signals because particularly with a low signal value, which lies in the range of ground potential, an undesired increase of the potential occurs which by the subsequent circuit stages, in the most unfavourable case, leads to the signal furnished by the output stage being interpreted as a signal with high value due to the overshoot phenomena although it should actually be a signal with low value. This phenomenon is referred to in (English usage as "ground bounce".
The overshoot can of course be reduced in that the switching edges of the pulse-like signals may be made slower but this however is contrary to the objective of achieving high switching speeds. In the book published by the company Texas Instruments "Advanced CMOS Logic, Designers Handbook", which came out in 1987, in chapter 3.1.5, page 3-9, an output stage is described in which steps are taken to reduce the unfavourable overshoot. In this output stage the output transistors are each formed from a plurality of individual transistors which are connected in parallel with each other. The gate zones of said individual transistors are connected in series and act like a resistive line. Since this line also has a certain capacitance the series circuit of the gate zones acts like a delay line so that the signal from the first transistor to the last transistor of the parallel-connected individual transistors requires a certain travelling time. However, without special measures this delay is not large enough to slow the edges of the switching pulses down to such an extent that undesirable overshoots no longer occur. The particular measure for reducing the overshoots includes in this known output stage the use of a current grounding or dissipating transistor which is connected to the series circuit of the gate zones of the output transistors of one of the two groups of individual transistors in the push-pull output stage and in the switched-on state causes a current to flow through the series circuit of the gate zones to ground.
The flowing of the current through the series circuit of the gate zones results in voltage drops occurring at the individual gate zones which act like individual resistances so that the gate voltages diminish consecutively from the first transistor of the group to the last. Due to the voltage drops occurring at the individual gate zones this additional current through the series circuit of the gate zones caused by the current grounding transistor opposes the formation of the overshoots. The current dissipating or grounding transistor must however be rendered nonconductive again after a defined time to prevent current permanently flowing through the gate zones. This blocking is carried out in dependence upon the input signal of the output stage from which by means of a delay circuit a control signal is generated which after the delay generated by the delay circuit renders the current grounding transistor nonconductive again. In the most favourable case, i.e. when the production-inherent parameters of the output stage have good values, the delay circuit must keep the current grounding transistor conductive long enough for the current to flow through the series circuit of the gate zones long enough for the desired effect of the gate voltage reduction to be maintained for an adequately long time. This current flow and the resulting voltage drop at the gate zones is the condition necessary for the undesired overshoots to be greatly reduced. If however the production-inherent parameters of the integrated output stage have unfavourable values the travelling time of the signal through the gate zones is from the start already relatively long and consequently the current additionally caused by the current grounding transistor together with the resulting further increase of the travelling time leads to excessive slowing down of the edges of the output signal of the output stage and this is extremely undesirable because the current grounding transistor, although it is intended to reduce the overshoot, should not excessively slow down the edge steepness of the output pulses.
USPTO Backgrounds
USPTO Backgrounds