1. Technical Field
The present inventions relate to circuitry to a message signaled interrupt redirection table (MRT) and to related systems.
2. Background Art
Message signaled interrupts (MSI) are a feature that enables a device function to request service by writing a system-specified data value to a system-specified address using, for example, a PCI (Peripheral Components Interconnect) DWORD (double word) memory write transaction. MSI is optional for PCI through PCI Local Bus Specification Rev 3.0, Feb. 3, 2004, but is used in PCI Express Specifications and is included in PCI-X specifications. MSI is an interrupt-generation mechanism that enables a PCI device to send an inbound memory write on its PCI bus to the front side bus (FSB), bypassing an IOxAPIC (input output advance programmable interrupt controller).
MSI-X is an enhancement to MSI. MSI and MSI-X are described in PCI Local Bus Specification, Rev. 3.0, section 6.8, pp. 231-253. MSI and MSI-X each allow a device to have multiple interrupt vectors. In MSI and MSI-X, a vector includes address and data. In MSI, the vector addresses must be contiguous. Due to the lack of support of simultaneous multi-processing (SMP) affinity in the MSI capability structure and operating systems' (OS's) non-contiguous vector scheme, OS's do not allow more than one interrupt vector per device. Consequently, Microsoft Windows and Linux OS's assign vectors contiguously as each device is encountered and limit the initial allocation to one vector per device. If the OS were to assign multiple contiguous MSI vectors per device during initialization, it may run out of interrupt vectors before all devices have been assigned interrupt vectors causing the system boot to fail. In MSI-X, the vectors do not have to be contiguous.
USPTO Backgrounds
USPTO Backgrounds