1. Field of the Invention
The present invention relates to semiconductors and transistors and more particularly to Si/SiGe strained-layer field-effect transistors.
2. Description of the Prior Art
Semiconductor Si/SiGe strained-layer MOSFETs fabricated using strained Si have potential for improved performance due to higher carrier mobility in the strained Si layer. The strain in the Si is typically achieved by first forming a relaxed SiGe layer, and then epitaxially growing the Si layer on top. Since the SiGe has a larger lattice constant than Si, the Si will be under tensile strain. The underlying relaxed SiGe layer can be formed in numerous ways, but is typically formed by growing a graded-Ge-content SiGe layer on a Si substrate, followed by a thick constant-composition SiGe layer. The SiGe relaxes by misfit dislocation formation near the original growth interface, with a fairly high density (on the order of about 106 cm−2-108 cm−2) of threading dislocations that extend to the sample surface. These threading dislocations continue to extend to the sample surface after growth of the strained Si cap layer. During high-temperature processing, additional misfit dislocations can form if the threading dislocations glide along the interface of the relaxed SiGe layer and the strained Si layer. The threading and misfit dislocations can lead to device failure in a short-channel MOSFET fabricated on these layers particularly if the dislocation extends continuously from the source implant region to the drain implant region. In this case, the dopants from the source and drain can segregate along the dislocation, causing a direct “pipe” from source to drain, resulting in device leakage. This is especially true for n-MOSFETs since the n-type dopant atoms in the source and drain (usually P and As) are larger than the p-type dopant atoms in the well region (usually B). Since larger atoms can preferentially occupy dislocation sites, n-MOSFETs are more likely to suffer from dislocation-related failures of the type described above.
FIGS. 1(a) and 1(b) depict schematic diagrams of the dislocation-induced leakage mechanism. Specifically, FIG. 1(a) illustrates a strained Si-on-relaxed-SiGe n-MOSFET device 10 formed between two dielectric isolation regions 12a, 12b. Manufactured by techniques known in the art, the n-MOSFET includes a relaxed SiGe substrate layer 15 doped p-type and including a strained Si channel layer 18 formed on top of the relaxed SiGe layer to form a Si/SiGe interface 22 between respective n-type drain and source regions 20a, 20b. On top of the grown strained Si layer is formed a gate dielectric layer 28 (e.g., an oxide such as SiO2) and a gate 30 formed thereon. As shown in FIG. 1, the n-MOSFET may form a threading dislocation 25 protruding up from the substrate 15 that glides along the Si/SiGe interface 22 and then terminates at the surface. As mentioned, the SiGe relaxes by misfit dislocation formation near the original growth interface 22, with a fairly high density of threading dislocations that extend to the sample surface. These threading dislocations continue to extend to the sample surface after growth of the strained Si cap layer. During high-temperature processing, additional misfit dislocations can form if the threading dislocations glide along the interface 22 of the relaxed SiGe layer 25 and the strained Si layer 18.
After an annealing process, the n-type dopants from the source and drain 20a, 20b may segregate along the dislocation, and if the gate length is sufficiently short, join together to form a leakage path 40 between source and drain, as shown in FIG. 1(b). FIG. 2 illustrates a plot 50 of the drain current, Id, versus the gate voltage, Vg, for a strained Si n-MOSFET with dislocation-induced leakage. The data shows that the leakage is seen to occur directly from source to drain (and not from source to body or drain to body, Ib), resulting in poor turn off behavior and high leakage 55 in the subthreshold region (Vgs<0).
To date the main methods of trying to overcome the problem of dislocation-induced leakage have been to reduce the density of initial dislocations in the relaxed SiGe material, and to ensure that the strained Si layer thickness is less than the critical thickness for thermodynamic stability. Both of these methods have been successful in reducing dislocation-induced leakage, but it is very difficult to completely eliminate the threading dislocations and process-induced misfit dislocations. As the Ge content is increased, the defect-related problems are exacerbated, since relaxed SiGe layers with higher Ge content tend to have higher densities of threading dislocations, and require thinner Si caps to prevent misfit formation. So even though improving the substrate material may reduce the number of dislocation-induced failures, these improvements may not be sufficient for applications requiring very high levels of integration, where even a very small number of devices with dislocation-induced leakage may be intolerable.
The interaction of dopant atoms with dislocations has been widely studied. It has been previously shown that heavy dopant atoms, such as In, can segregate to end-of-range dislocations in Si such as described in Noda et al., J. Appl. Phys. 88, 4980 (2000). The effect of implanting heavy neutral impurities such Sn into Si has been studied in C. Claeys et al., J. Electrochem. Soc. 148, G738 (2001), for example, and it was found that Sn acts as a vacancy getter. These results therefore suggest that Sn may also acts as a getter for dislocations. Kaplan et al. in the reference Kaplan et al., Phys. Rev. B 58, 12865 (1998) also noted that Ga impurities segregated to dislocations in Si could form quantum wire conducting paths. However, neither a structure nor a method by which dopant and/or neutral impurity atoms could be used to intentionally occupy the region in the vicinity of dislocations for the purpose of preventing dislocation-induced leakage in strained-layer MOSFETs have been proposed.
It would thus be highly desirable to provide a method and structure for reducing the leakage in strained-layer MOSFETs without the need for eliminating the defects themselves.
USPTO Backgrounds
USPTO Backgrounds