A conventional code generator of the above-indicated type has a circuit arrangement, for example, as shown in FIG. 11. In FIG. 11, SR.sub.l through SR.sub.n-1 and SR.sub.f refer to flipflops, and E.sub.l through E.sub.n indicate exclusive logic sum gates. They all form a so-called modular type shift register generator. MUX 1 designates a multiplexer which selects the final stage of operation of the modular type shift register generator to control the number of stages of the modular type shift register generator. AND.sub.2 through AND.sub.n denote AND gates which specify the presence or absence of feedback of signals from the final stage output to respective stages of the modular type shift register generator. G.sub.l through G.sub.n denote steering gates for setting the initial value of the modular type shift register generator. More specifically, the code period, code pattern and code phase are controlled independently of each other, by controlling the code period by determining the address of the multiplexer MUX 1 by means of data c.sub.l to c.sub.i and determining the number of stages of the modular type shift register generator; by controlling the code pattern by determining the feedback condition of signals from the final stage to respective stages of the modular type shift register generator by means of data a.sub.2 to a.sub.n ; and by controlling the code phase by determining the initial value of the modular type shift register generator by means of data b.sub.l to b.sub.n In this way, any desired maximal sequence code can be generated.
A feature of this system is that it includes therein GOLD code generating circuits E.sub.g and SR.sub.g which are disclosed in Japanese Patent Application No. 61-253993 filed Oct. 24, 1986, corresponding to U.S. Pat. No. 4,837,790 and GOLD codes can readily be generated by connecting two code generators of FIG. 11 as shown in FIG. 12. In FIG. 12, PNG 1 and PNG 2 denote pseudorandom noise code generators, u and v indicate maximal sequence codes, and T designates a left cyclic shift computing element. A GOLD code is obtained by adding different maximal sequence codes in modulo 2. Since GOLD codes may have much more kinds of patterns for a frequency than maximal sequence codes, the use of GOLD codes is more advantageous when a multiple signal using a number of codes must be used in application of the circuit to a spread-spectrum communication system, etc.
The existing system, however, cannot output more than one kind of GOLD code at once, using two code generators, and it therefore requires a number of code generators for a multi-channel arrangement.
USPTO Backgrounds
USPTO Backgrounds