Currently, in the field of high power amplifiers, there is a need for cost-effective techniques that aid in avoiding high voltage stress. When power semiconductors are occasionally exposed to instantaneous high levels of energy, it often results in significant damage to or destruction of the semiconductors. In addition, instantaneous high voltage often appears in applications having unclamped inductive loads or otherwise having high standing wave load mismatch conditions.
There is also a need for protection against certain voltage stress arising during continuous high-power operation. This condition often leads to a rise in the temperature of the power semiconductor junctions. The temperature rise in turn deleteriously affects various aspects of amplifier performance. In extreme circumstances, the voltage present in the output stage of the amplifier approaches or exceeds the semiconductor's breakdown voltage and inevitably leads to excessive high power dissipation and the eventual catastrophic failure of the semiconductors.
Existing protection methods include, for example, optimizing the power semiconductors and including an external diode clamping circuit. In addition, current practices may include severely limiting or reducing the supply voltage available to the output stage of the amplifier to a level between the breakdown voltage of the semiconductors and the operating voltage present at the absolute contact node of the semiconductors.
Current practices, however, fail to adequately address predicting and measuring the dynamic voltage amplitude at the absolute contact node. As the amplifier's operating frequency increases, this becomes even more difficult. For example, there is often no convenient point-of-access to the actual contact node of a semiconductor because of an interconnecting inductance situated between the actual transistor and its external connections. Thus, as the operating frequency is increased, the terminal impedance diverges from the absolute contact node impedance. Accordingly, designers are forced to surmise conservative estimates of the maximum allowable supply voltage based on a margin assigned to the semiconductor's breakdown voltage. The margin, a highly qualitative figure, includes the effects of the external circuitry and operating conditions, such as dynamic loads and temperature ranges. Therefore, by varying the degree of margin, a designer can mitigate performance, efficiency and damage risks in a manner that may also minimize cost. This balance is difficult to achieve, however, due to the qualitative assessments of dynamic voltage and circuit impedance. The protection methods invariably have adverse effects on system performance and generally increase operating costs.
USPTO Backgrounds
USPTO Backgrounds