1. Field of the Invention
The present invention generally relates to the fabrication of semiconductor devices, and more particularly, to a method of removing a spacer in the manufacturing process of a metal-oxide-semiconductor transistor device.
2. Description of the Prior Art
For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to very deep sub micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue. In order to improve device performance, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a means for getting better performance in the field of CMOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strain makes CMOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.
Generally, strain in silicon can be induced in different ways: through stresses created by films in a form of poly stressor or contact etch stop layer (CESL) and structures that surround the transistor, called process-induced strain, or by employing a strained silicon wafer, where the top layer of silicon has typically been grown on top of a crystalline lattice that is larger than that of silicon. Most leading-edge chip manufacturers employ process-induced stress in some form in production today, typically tensile nitrides to improve NMOS device performance. As known in the art, tensile stress improves electron mobility and compressive stress improves hole mobility.
Conventional MOS (metal-oxide-semiconductor) device fabrication utilizes a technique of building material spacers to help control and define the implantation of dopants in the source and drain regions of the MOS. A conventional NMOS semiconductor device is schematically illustrated in FIG. 1. The conventional NMOS transistor device generally includes a semiconductor substrate generally comprising a silicon layer 16 having a source 18 and a drain 20 separated by a channel region 22. Ordinarily, the source 18 and drain 20 further border a shallow-junction source extension 17 and a shallow-junction drain extension 19, respectively. A thin dielectric layer 14 separates a gate electrode 12, generally comprising polysilicon, from the channel region 22. The source 18 and drain 20 are N+ regions having been doped by arsenic, antimony or phosphorous. The channel region 22 is generally boron doped. A silicon nitride spacer 32 is formed on sidewalls of the gate electrode 12. A liner 30, generally comprising silicon dioxide, is interposed between the gate electrode 12 and the silicon nitride spacer 32. A metal silicide layer 42 is selectively formed on the exposed silicon surface of the device. The process known as self-aligned silicide (salicide) process has been widely utilized to fabricate metal silicide materials, in which a source/drain region is first formed, a metal layer comprised of cobalt, titanium, or nickel is disposed on the source/drain region and the gate structure, and a rapid thermal process (RTP) is performed to react the metal layer with the silicon contained within the gate structure and the drain/source region to form a metal silicide for reducing the sheet resistivity (Rs) of the drain/source region.
In the conventional MOS fabrication technique, spacers are often used in the fabrication of LDD (lightly doped drain) regions to facilitate the different levels of doping for the drain/source regions and the LDD regions. The LDD region can be controlled by the lateral spacer dimension and the thermal drive cycle, and can be independent from the source and drain implant depth. In the 65 nm technology and beyond, the channel mobility enhancement can be further achieved by deposition of a highly strained dielectric layer after spacer removal. However, removing the spacer, especially spacer SiN (silicon nitride), is critical because removal can damage adjacent structures, such as the metal silicide layer, the gate, and the underlying silicon substrate. As shown in FIG. 1, in the conventional technique, an etching process 34 is directly performed to remove the spacer after the metal silicide layer is accomplished. A dry etching, such as an etching using a carbon tetrafluoride gas mixed with oxygen gas and nitrogen gas, may be performed to remove silicon nitride. A wet etching, such as a hot H3PO4 process at a temperature of 160° C., may be performed to remove silicon nitride. However, this often leads to the erosion of metal silicide layer, and especially when the spacer is silicon nitride and the metal silicide layer is nickel silicide, nickel silicide is easily damaged in the etching process. Accordingly, the sheet resistivity, one item in the wafer acceptance test (WAT), is harmfully affected.
Therefore, there is a need for a better method to remove spacers and fabricate a metal-oxide-semiconductor transistor device to remove spacers formed in the manufacturing process and not to damage salicide layers.
USPTO Backgrounds
USPTO Backgrounds