1. Field of the Invention
This invention relates to interconnect structures for integrated circuits, and more specifically to vertical contact interfaces of interconnect structures.
2. Description of Related Art
The fabrication and connection of multiple electrical devices on a single semiconductor wafer resulted in the advent of integrated circuit ("IC") technology. Early in the development of integrated circuit technology, the interconnect structures of electrical devices typically consisted of a single level of Aluminum metal ("Al") forming a horizontal contact interface with heavily doped diffused regions in the silicon substrate. However, in order to obtain the flexibility needed to interconnect larger numbers of smaller devices and more complex circuits, it became necessary to develop and utilize multi-level interconnect structures.
FIG. 1 illustrates a cross-sectional view of a multi-level interconnect structure 100 fabricated using conventional technology. Multi-level interconnect structure 100 is composed of a contact dielectric 102, an adhesion layer (not shown for clarity), a barrier layer (not shown for clarity) between contact interfaces, tungsten ("W") vertical interconnects 108, 114, and 116, via dielectric 112, horizontal interconnects 110, 118, and 120 (shown extending into the page). During fabrication, deposition and metal masking of horizontal interconnect 110 on the surface of contact dielectric 102 follows the deposition of the W vertical interconnect 108. Because of the planarity of the surface of contact dielectric 102, a horizontal contact interface 109 exists between horizontal interconnect 110 and W vertical interconnect 108. FIG. 16 illustrates a top view of a perfectly aligned conventional horizontal contact interface between a conventional contact/via 402 and a conventional horizontal interconnect 404. Referring now to FIG. 1, the W vertical interconnect 108 provides an electrical conduction path between electrical device 106 and horizontal interconnect 110.
After the fabrication of via dielectric 112, W vertical interconnects 114 and 116 are deposited and serve as electrical conduction paths between subsequently deposited horizontal interconnects 118 and 120, respectively, and horizontal interconnect 110. W vertical interconnects 114 and 116 have horizontal contact interfaces 124 and 126, respectively, with horizontal interconnect 110 due to the surface planarity of horizontal interconnect 110. Additionally, W vertical interconnects 114 and 116 have horizontal contact interfaces 128 and 130, respectively, with horizontal interconnects 118 and 120 due to the surface planarity of via dielectric 112.
Conductors made of thin films of Al or its alloys, such as Al-Cu (i.e. an aluminum and copper alloy) or Al-Cu-Si (i.e. an aluminum, copper, and silicon alloy), are commonly used for horizontal interconnects 110, 118, and 120. Deposition of a barrier layer underneath horizontal interconnects 110, 118, and 120 (not shown for clarity) is typically included to enhance the electromigration resistance of horizontal interconnect 110. The barrier layer is typically composed of Ti-W (i.e. Titanium and Tungsten alloy) or Ti/TiN.sub.x (i.e. Titanium underlaying a Titanium and Nitrogen compound with different acceptable proportions of Nitrogen).
In order to achieve higher device packing density, conventional multi-level interconnect structure fabrication technologies rely in part on the reduction of horizontal interconnect linewidths. Referring now to FIG. 16, although horizontal interconnect linewidths, w, continue to decrease in the conventional architecture, the thicknesses of horizontal interconnects 110, 118, and 120, t.sub.1, t.sub.2, and t.sub.3, respectively, as shown in FIG. 1, remain generally the same. In FIG. 16, the linewidth dimension of horizontal interconnect 404 is comparable to the linewidths of horizontal interconnects 110, 118, and 120. The conventional multi-level interconnect structure 100 is fabricated so that the diameter of the horizontal contact interface 109 is ideally the same as the linewidth of the horizontal interconnect 110. FIG. 16 illustrates this from a top view showing the linewidth of the conventional horizontal interconnect 404 is ideally equal to the diameter of the conventional contact/via hole 402. Referring again to FIG. 1, because of the close dimensional relationship between the size of the horizontal contact interface 109 and the linewidth of the horizontal interconnect 110, the linewidth of the horizontal interconnect 110 determines the maximum size of the horizontal contact interface 109. Likewise, the linewidths of horizontal interconnects 110 and 118 determine the size of horizontal contact interfaces 124 and 128, respectively. Similarly, the linewidths of horizontal interconnects 110 and 120 determine the size of horizontal contact interfaces 126 and 130, respectively. The maximum size of the contact interface in the conventional multi-level interconnect structure 100 is given approximately by Equation [1] as follows: EQU A.sub.hci .pi.*w.sup.2 /4 [1]
where A.sub.hci and w are the size of a horizontal contact interface and the linewidth of a horizontal interconnect, respectively, and .pi. is approximately 3.14. The significance of Equation [1] is presented below.
The conventional multi-level interconnect structure 100 offers high device packing density. An even higher packing density can be achieved by preventing unnecessary overlap by the horizontal interconnects and their respective contact/via holes. However, as shown in FIG. 16, due to finite tolerances in the fabrication process some overlap 406 (as illustrated by the dashed lines) of the conventional horizontal interconnect 404 with the contact/via hole 402 and its associated horizontal contact/via interface may occur. Therefore, in FIG. 1, horizontal interconnects 110, 118, and 120 overlap the respective vertical interconnects 108, 114, and 116. However, the magnitude of the overlap may be affected by the types of materials Used for the horizontal and vertical interconnects. When both horizontal and vertical interconnects are fabricated from the same kinds of thin films, it is a non-trivial task to prevent unnecessary overlapping of the vertical interconnects 108, 114, and 116. However, by using different thin films for the horizontal and vertical interconnects which have different plasma etch characteristics, prevention of unnecessary overlap can be achieved. The plasma etch characteristics of W are different from those of Al, and a high plasma etch selectivity can be obtained i.e. the W etch rate is significantly lower than the Al etch rate. Therefore, it is typical to fabricate the horizontal and vertical interconnect structures from different materials.
While the conventional multi-level interconnect structure 100 offers high device packing density, it exhibits significant disadvantages. A first disadvantage relates to electromigration failures occurring at the horizontal contact interfaces between the W vertical interconnects 108, 114, and 116 and the horizontal interconnects 110, 118, and 120. Electromigration is the motion of conductor ions (such as Al) in response to the passage of current through the conductor. The conductor ions move "downstream" by the force of the "electron current." A positive divergence of the ionic flux leads to an accumulation of vacancies, forming a void(s) in the metal. Electromigration presents significant reliability and performance issues in that as the size and/or number of voids form, reduction in the current carrying capability of the conductor results. Because speed performance is often directly related to current carrying ability, electromigration consequentially results in the degradation of the speed performance of an integrated circuit incorporating such conductors. Furthermore, a void due to electromigration may ultimately grow to a size that results in a catastrophic open circuit failure of an affected conductor.
The contact interface between dissimilar conductors is more prone to electromigration than in each conductor alone. For example, the contact interface between W and Al is more prone to electromigration than in W and Al alone. As a result, the electromigration lifetime of the contact interface becomes the limiting factor on design-rule current density i.e. the amount of current per unit area designed to be carried by a conductor.
The electromigration lifetime (i.e. the amount of elapsed time prior to the failure of the conductor) can be approximated by Equation [2] as follows: EQU t.sub.em =K*exp [(E.sub.a /kT)]*(1/J).sup.n [ 2]
where t.sub.em is the electromigration lifetime, K is a constant, E.sub.a is the activation energy, k is Boltzmann's constant, T is the operating temperature in Kelvin, J is the current density, and n is a current-density dependent exponent greater than or equal to 2. Equation [2] infers that, for a given multi-level interconnect system and operating temperature, electromigration lifetime decreases with increasing current density.
The current density J is directly related to current I and the size of a contact interface A as expressed by Equation [3] as follows: EQU J=I/A [3]
Equation [3] infers that, for a given current, the current density at the contact interface increases as the size of the contact interface decreases. Therefore, in accordance with Equations [1], [2], and [3] electromigration lifetime decreases as the size of the contact interface decreases, and the size of the contact interface decreases as linewidth decreases. Similarly, decreases in the size of the contact interface increases the rate of degradation of the contact interface due to electromigration which in turn results in the degradation of integrated circuit speed performance.
Conventional multi-level interconnect structure fabrication technologies rely in part on the reduction of interconnect linewidths to achieve even higher device packing densities. As evident from Equation [1] and the dimensional relationship between horizontal contact interfaces and horizontal interconnect linewidths, decreases in linewidth result in parabolic decreases in the size of the contact interface. For a conventional multi-level interconnect structure to achieve higher device packing densities by decreasing the size of the contact interface, costly tradeoffs in reliability and/or integrated circuit speed performance arise. In the conventional multi-level interconnect structure, reliability tradeoffs occur when linewidths are decreased and speed performance and, thus, current density are sought to be maintained because of decreases in the electromigration lifetime of the contact interface result. Additionally, in the conventional multi-level interconnect structure, integrated circuit speed performance tradeoffs occur when electromigration lifetime is maintained by reducing the current density because a decrease in integrated speed performance results. However, neither tradeoffs in reliability nor integrated circuit speed performance are desirable.
Referring to FIG. 17, another disadvantage involves the misalignment of a conventional contact/via hole 402 and conventional horizontal interconnect 404. If there is misalignment between the contact/via hole 402 and the horizontal interconnect 404, the size of the contact interface 408, i.e. the overlapping region, reduces in accordance with Equation [1]. For the same reasons discussed above, depending on the magnitude of the contact interface size reduction, the decreased size of horizontal contact interface 408 can seriously degrade the electromigration lifetime of the horizontal contact interface 408. Referring back to FIG. 1, misalignment of the horizontal contact interfaces 109, 124, 126, 128, and 130 can result in significant degradation of the electromigration lifetime of the respective misaligned horizontal contact interfaces.
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