The present invention relates generally to the electro-static discharge (ESD) protection for integrated circuit (IC), and more particularly to a gate-equivalent-potential circuit and method for input/output (I/O) ESD protection.
Complementary metal-oxide-semiconductor (CMOS) integrated circuit devices are vulnerable to ESD induced failure. Especially, the applications of thin gate oxide, short channel and shallow junction for high integration density as well as the lightly doped drain (LDD) and self-aligned silicide (salicide) further degrade the performance of MOS devices against ESD. Various techniques have been disclosed to self-protect output buffers or other I/O pads against ESD failures. Some of these measures include diode clamps, lateral punch-through devices and guard ring collectors around an I/O pad, and these circuits are reasonably effective to protect the integrated circuit devices.
ESD protection structures are classified into two categories including structures to protect input buffers and structures to protect output buffers and I/O pads. Protection of input buffers is relatively simple because a CMOS gate does not conduct current. Accordingly, a special protection structure is implemented on the input buffer that restricts the gate voltage of a transistor to a maximum breakdown voltage. To the contrary, the other category of output buffers and I/O pads includes structures that are more difficult to protect. This difficultly results from that the output buffer may conduct current by ESD stress and thus may be damaged. The protection structure must be designed and layout constructed so that the protection structure discharges the ESD stress without self-damage while the output buffer conducts only a minimum current under ESD stress conditions. Two well-known ESD protection structures substantially utilize the transistor turn-on mechanism and the transistor snapback mechanism in the protection circuit, where the former is characteristic of the threshold voltage for channel conduction, and the latter is characteristic of the transistor breakdown voltage. The more popular snapback mechanism is the introduction of an ESD protection structure such as NMOS transistors onto the interconnection between the I/O pad and the internal or core circuit. Upon ESD event, the internal circuit is protected by bypassing of the built-in parasitic bipolar transistors. To release large amount of ESD current by the NMOS transistors without excessive gate width structure, fingers layout is employed for the ESD protection circuit. Unfortunately, the fingers of NMOS transistors are hardly to turn on uniformly due to the inherent structure difference resulted from the fingers arrangement, resulting in that the ESD current will concentrate in a small region and thus burn out the device. As such, even a large ESD protection device will not have acceptable performance.
In proposed solutions, with the gate of an NMOS transistor coupled to a positive voltage, the triggering voltage of the NMOS transistor is then reduced. However, in a multiple fingers NMOS transistor including used and unused MOS fingers, of which the used MOS finger is referred to one with its gate connected to a pre-driver and the unused MOS finger is referred to one with its gate grounded, due to the parasitic capacitance between the drain and the gate of the MOS transistor, the gate of the used finger will be coupled with a positive voltage that makes the triggering voltage of the used finger much lower than that of the unused one, and thus the used finger will be triggered first and destroyed and the unused one will not be triggered. In other words, the ESD endurance of the NMOS transistor depends on the width of the used fingers instead of the total width of the NMOS transistor. To prevent from unbalance triggering between the used and unused fingers, the gate of the unused finger is not supposed to be grounded directly, but coupled with a positive voltage during an ESD event. Some of prior arts insert a resistor between the gate of the unused finger and ground, some introduce a pass gate with its gate connected to a supply voltage, and the others employ more complicated circuit. The purpose of these prior arts is to have the gates of the used and unused fingers at an equal potential during an ESD event for them to be triggered simultaneously. However, a resister consumes a large chip area and can not ensure the gates at equal potential for the used and unused fingers, a pass gate also can not promise equivalent-gate-potential for the used and unused fingers even it occupies a smaller chip area, and a complicated circuit will complicate the design of the chip circuit.
Therefore, it is desired a circuit and method to have the gates of the used and unused fingers equivalent potential during an ESD event.
One object of the present invention is to provide a gate-equivalent-potential circuit and method for I/O ESD protection, by which the gate of used MOS finger is coupled to the gate of unused MOS finger by a switch that is turned on by an ESD detector upon an ESD event.
In a gate-equivalent-potential circuit for I/O ESD protection, according to the present invention, a switch is inserted between the gates of used and unused MOS fingers that is connected to an I/O pad, an ESD detector is connected to the switch to turn it on upon an ESD event, and a gate-modulated circuit is connected to the gate of the unused MOS finger to couple a voltage thereto. During normal operation, the switch is kept off. Once an ESD event occurred, the voltage on the I/O pad increases rapidly, the ESD detector sends a signal to turn on the switch for the gate of the unused MOS finger to be coupled to the gate of the used MOS finger such that the gates of the used and unused MOS fingers approach to a same potential, thereby the ESD fingers are triggered more uniformly.
USPTO Backgrounds
USPTO Backgrounds