Integrated circuit (IC) designers commonly describe their designs in HDL (hardware description language) such as Verilog, VHDL, SystemC, and the like. In IC design, hardware emulation may refer to the process of replicating the behavior of one or more pieces of hardware (typically a design under test) with another piece of hardware, typically a special-purpose emulation system. An emulation model is usually based on a hardware description language source code, which is compiled into the format used by emulation system. The goal is debugging and functional verification of the system being designed. Overall progress of the emulation is usually controlled by a clock signal generated on the emulator hardware.
In general, multiple types of clocks, such as a system clock, design clock, derived clocks and the like may exist in an emulation system. The system clock (that may also be referred to as an atomic clock) is the most frequent clock of the emulation system. Primary clock of a design (that may also be referred to as a design clock) is the fastest clock signal that can be used to execute the design. Behavior of the primary clock is usually defined in terms of number of system clock cycles. The derived clocks may be derived from the design clock using, for example, combinational logic.
Modern hardware designs exhibit complex clock trees. For example, a derived clock may be generated by gating and/or dividing the design clock, or multiplexing one or more clock signals. In general, evaluation of a primary clock cycle in the design involves evaluation of values of multiple clock signals that are derived from the primary clock. For example, in order to find the fastest clock signal that can be used to execute a design, the primary clock signal and all the other clocks that are derived from the primary clock signal are analyzed and the longest propagation delay in the design is identified. Based on the longest propagation delay, frequency of the design clock is determined.
In a typical emulation, each evaluation that corresponds to propagation of a primary clock in the design (so that values of the derived clock can be established) takes the same number of the system clock cycles (e.g., atomic clock cycles) of the emulation board. However, when a derived clock does not change value for a given new value of the primary clock, same number of system clock cycles are waited to propagate the derived clock even if the value of the derived clock does not change.
USPTO Backgrounds
USPTO Backgrounds