1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to the field of pattern or etch processing for semiconductor fabrication.
2. Description of the Related Art:
In typical semiconductor fabrication processes, various layers of materials formed over a semiconductor substrate are patterned or etched in accordance with various functional and/or design requirements for fabricating a desired semiconductor device. The pattern or etch process typically involves a lithography process. In a typical lithography process, photoresist is deposited over the layer to be patterned. This photoresist is then exposed to radiation such as ultraviolet radiation through a mask which defines the pattern to be created in the photoresist. Depending on whether positive or negative photoresist is used, the exposed portions of photoresist are made either soluble or insoluble, respectively, in a developer. As a result, a patterned photoresist layer remains over the underlying layer after the photoresist is developed. Those portions of the underlying layer which are not covered by photoresist may then be etched using suitable etch techniques and chemistries, generally depending on the material of the underlying layer. The pattern in the photoresist is thus replicated in the underlying layer.
The above lithography process, however, limits certain design considerations for semiconductor fabrication. In the semiconductor wafer illustrated in FIG. 1, for example, two adjacent transistors 109a and 109b have been distanced apart from one another to avoid electrical shorting. The transistors 109a and 109b have been formed over a substrate 100 which has a field oxide region 102 to electrically isolate active region 106a from active region 106b. Using the above lithography process, polycrystalline silicon (polysilicon or poly-Si) gates 108a and 108b of each transistor 109a and 109b, respectively, have been defined to extend over the edge of each active region 106a and 106b, respectively, to account for line width variation of the polysilicon gate, any misalignment of the mask in patterning the polysilicon into each gate, and for lithographic rounding effects at the end of each polysilicon gate.
Lithographic rounding occurs as a result of the diffraction of radiation around the edges and corners in the mask through which the photoresist is exposed. As illustrated in FIG. 1, the ends of each polysilicon gate 108a and 108b are rounded because of the diffraction of radiation around the edges of the mask used to define the pattern in the photoresist for each polysilicon gate 108a and 108b. When the polysilicon was etched using this patterned photoresist, then, the rounding effect became replicated in the patterned polysilicon. The lithographic rounding effect reduced the width of the polysilicon gate at its end. If the end of the polysilicon gate did not sufficiently extend over the edge of its active region so that the full width of the polysilicon gate covered this edge, the channel length of the gate would be reduced as a result of this narrowed gate end. The transistor may also be shorted if the narrowed end of the polysilicon gate did not sufficiently cover the edge of its active region.
To determine the minimum amount each polysilicon gate should be designed to extend over the edge of its active region, a so-called "endcap rule" is generally used. Under the endcap rule, for example, a polysilicon gate may be designed to extend over the edge of its active region for 0.25 .mu.m to account for line width variation and misalignment and for an additional 0.15 .mu.m to account for lithographic rounding effects, for a total extension of 0.40 .mu.m. Furthermore, the polysilicon gate must be spaced apart from other polysilicon gates to avoid shorting. This poly-poly spacing is typically constrained by the resolution limits of the lithography process. Using 0.6 .mu.m lithography, the poly-poly spacing may be as small as 0.6 .mu.m. In fabricating a semiconductor device using the above endcap rule example, then, transistors would be spaced 1.4 .mu.m apart (0.4 .mu.m first polysilicon gate extension +0.6 .mu.m poly-poly spacing +0.4 .mu.m second polysilicon gate extension). The above lithography process therefore limits the packing density of the semiconductor device being fabricated as transistors must be placed further apart from one another to avoid various defects.
Thus, what is needed is a patterning or etch process which reduces or avoids lithographic rounding effects. What is also needed is a patterning or etch process which reduces the minimum extension of a transistor gate over the edge of its active region under the endcap rule. What is still further needed is a patterning or etch process which provides for the fabrication of semiconductor devices with higher packing densities.
USPTO Backgrounds
USPTO Backgrounds