1. Field of the Invention
Generally, the present disclosure relates to methods for the manufacturing of integrated circuits, and, in particular, to methods for the manufacturing of integrated circuits wherein sidewall image transfer techniques are employed.
2. Description of the Related Art
Integrated circuits include a large number of circuit elements which include, in particular, field effect transistors. In a field effect transistor, a gate electrode is provided that may be separated from a channel region by a gate insulation layer providing an electrical insulation between the gate electrode and the channel region. Adjacent the channel region, a source region and a drain region are formed, which are doped differently than the channel region. In addition to planar transistors, transistors that can be used in integrated circuits include transistors wherein the channel region is formed in one or more elongated semiconductor regions, which are denoted as fins. Types of transistors wherein the channel region is formed in one or more fins include FinFET transistors and Tri-Gate transistors.
For improving the performance of FinFET transistors and Tri-Gate transistors, it may be desirable to reduce the dimensions of the fins in the transistors. However, the possibility of forming small features by means of conventional techniques of photolithography and etching may be limited by the resolution of the photolithography process. The resolution of a photolithography process may depend on the wavelength of light that is used in the photolithography process for projecting a photomask to a photoresist, and the numerical aperture of the lens that is used for projecting the photomask to the photoresist.
For providing small features such as fins of FinFET transistors and/or Tri-Gate transistors that have dimensions which are smaller than the resolution limits of conventional photolithography processes, multiple patterning techniques have been developed, which include sidewall image transfer (SIT) techniques.
In sidewall image transfer techniques, sacrificial features which are denoted as “mandrels” are formed from a mandrel layer which is provided over an etch stop layer. The mandrels may be formed by means of techniques of photolithography and etching, wherein the etch process stops at the etch stop layer. Then, a layer of a sidewall spacer material that may be etched selectively relative to the material of the etch stop layer may be substantially isotropically deposited over the mandrels. Thereafter, the layer of sidewall spacer material may be anisotropically etched for removing portions of the layer of sidewall spacer material over substantially horizontal portions of the semiconductor structure. Due to the anisotropy of the etch process, portions of the layer of sidewall spacer material at the sidewalls of the mandrel may remain in the semiconductor structure.
Thereafter, the mandrels may be removed by means of an etch process, wherein the sidewall spacers remain in the semiconductor structure. Thereafter, a further etch process that is adapted to selectively remove the material of the etch stop layer relative to the material of the sidewall spacers may be performed. Thus, a mask having a pattern corresponding to the arrangement of the sidewall spacers may be formed from the etch stop layer. Then, the sidewall spacers may be removed, and the patterned etch stop layer may be employed as a mask for patterning materials below the etch stop layer.
Since the dimensions of the sidewall spacers formed adjacent the mandrels are not limited by the resolution of the photolithography process, sizes of features that are formed by patterning the material below the mask formed from the etch stop layer can be smaller than feature sizes obtainable by directly patterning a material by means of a photolithography process.
For obtaining even smaller feature sizes, a double sidewall image transfer (SIT2) process may be performed wherein the mask that is formed from a first etch stop layer in a first sidewall image transfer process is used for forming mandrels for a second sidewall image transfer process from a second mandrel layer. Adjacent these mandrels, sidewall spacers may be formed. After a removal of the mandrels formed from the second mandrel layer, the sidewall spacers may be used for forming a mask from a second etch stop layer that is provided below the second mandrel layer. The mask formed from the second etch stop layer may then be used for patterning a material below the second etch stop layer, for example, a semiconductor material from which fins of FinFET transistors and/or Tri-Gate transistors are to be formed.
In semiconductor manufacturing processes, so-called overlay/alignment marks may be employed. The overlay/alignment marks may be formed in a first patterning process wherein one or more materials of a semiconductor structure are patterned, and they may be used in one or more second patterning processes for aligning the semiconductor structure and a photomask.
However, using overlay/alignment marks in combination with sidewall image transfer techniques as described above may have some issues associated therewith, in particular when a double sidewall image transfer technique is employed.
When a photolithography process that is employed for forming mandrels is also employed for forming a feature that is provided for defining an overlay/alignment mark, a plurality of fins may be formed from this feature in the later steps of the sidewall image transfer process. However, dimensions of overlay/alignment marks may be substantially different from dimensions of circuit elements, such as FinFET transistors and/or Tri-Gate transistors. Typical examples of alignment/overlay marks may include arrangements of features having dimensions in a range from about 150 nm to about 1.5 μm, whereas a pitch between adjacent fins and width of fins for FinFET transistors and/or Tri-Gate transistors may be as small as about 7 nm. Accordingly, when features provided for defining overlay/alignment marks are patterned by means of sidewall image transfer techniques, arrangements including relatively long fins that are provided at relatively large distances may be created. Since patterning conditions of the sidewall image transfer processes are typically adapted for fin patterns that are employed for providing FinFET transistors and/or Tri-Gate transistors, the fins that are formed from the overlay/alignment mark features may be vulnerable to collapsing, which can create defects in the semiconductor structure and compromise the functionality of the overlay/alignment marks in later manufacturing processes.
For addressing this issue, it has been proposed to perform a so-called “zero level patterning,” wherein overlay/alignment marks are formed in a semiconductor structure before any process steps that are performed for the formation of fins. However, in this case, the alignment/overlay marks typically include relatively deep trenches in the substrate, into which the layer stack that includes mandrel layers and etch stop layers for use in the sidewall image transfer techniques is filled, and the sidewall image transfer stack may have to be pulled out from the overlay/alignment marks by means of additional steps of the manufacturing process, which may increase the complexity of the manufacturing process.
As an alternative to the use of zero level patterning processes for the formation of alignment/overlay marks, it has been proposed to form a first set of overlay/alignment marks by means of a photolithography process that is performed for defining the mandrels of the first sidewall image transfer process of a double sidewall image transfer process and to form a second set of overlay/alignment marks by means of another photolithography process that is performed between the first and the second sidewall image transfer process of the double sidewall image transfer process. The other photolithography process can also be used for forming a large feature mask that is employed in the patterning of parts of the semiconductor structure from which transistors are formed. In later stages of the semiconductor manufacturing process, the second set of overlay/alignment marks can be used. However, in this case, the first set of overlay/alignment marks may still be a defect source in later stages of the manufacturing process due to collapsing fins, and later stages of the manufacturing process may be adversely affected by alignment errors in the formation of the second set of overlay/alignment marks.
Other techniques may include a pitch reduction in overlay/alignment marks which, however, may be insufficient for preventing a collapse of fins.
The present disclosure provides methods of manufacturing semiconductor structures that may help to overcome or at least reduce some or all of the above-mentioned issues.
USPTO Backgrounds
USPTO Backgrounds