Embodiments of the present invention relate to the fabrication of through-silicon vias used in electronic circuits.
Electronic circuits, such as, for example, integrated, display, memory, power, and photovoltaic circuits, are being developed with active and passive features which are ever smaller. Three-dimensional (3D) structures of electronic circuits are formed by vertically stacking a plurality of substrates, which each have features thereon, in a multilayer stacked structure. The features of the different substrates are connected to one another with conventional wire bonds located outside the perimeter edges of the substrates. However, the resultant 3D circuit structures cover larger areas because the wire bonds extend outside the stacked substrates, increasing the circuit size and reducing the areal density of the circuit.
Through-silicon vias (TSV) are being used to electrically connect features of circuits in vertically disposed layers to provide 3D circuit structures having higher areal densities and which are absent side wires. In TSV fabrication, vias are etched in a silicon-containing substrate, such as a silicon wafer or glass panel with a silicon layer, which can already have prefabricated circuits. The etched vias are filled with an electrical conductor, e.g., a metallic conductor comprising a metal such as copper (Cu), silver (Ag), gold (Au), tungsten (W), and solder; or doped semiconductors, e.g., polysilicon. Dielectric layers such as silicon oxide and silicon nitride layers can also be used to line the walls of the vias before depositing the metallic conductor therein to serve as diffusion barriers, hermetic seals, and other insulating, diffusion barrier or permeation-reducing layers. Multiple substrates are then stacked and vertical electrical connections are formed by the TSVs to connect overlying or underlying features and portions of the resultant three-dimensional circuit. These 3D structures are commonly known as 3D packages, System in Package, or Chip Stack MCM. TSVs allow increased functionality in a smaller areal “footprint” and can also provide faster operating speeds by substantially shortening the electrical paths between the vertically stacked, overlying circuits, as compared with wire bonding methods.
In certain TSV fabrication processes, a substrate comprising a silicon plate, such as a silicon wafer is bonded to a support panel, such as a glass panel, to protect the fragile silicon wafer during fabrication of the TSVs. However, the silicon wafer is often bonded to the support panel using a bonding adhesive which deteriorates at temperatures above 250° C. Conventional processes for the deposition of materials into the TSV features, especially dielectric deposition methods, are conducted at higher temperatures than the deterioration temperature of the adhesive bond material. As a result, the bonding adhesive thermally degrades during processing, resulting in breakage, damage, or failure of the TSV circuit being fabricated. The temperature degradation problems in the fabrication of TSVs have not been resolved by conventional processing methods.
Thus, for various reasons that include these and other deficiencies, and despite the development of various methods of depositing dielectric and other materials in TSV features, further improvements in the fabrication of TSV features are continuously being sought.
USPTO Backgrounds
USPTO Backgrounds