A computer system may include at least one master unit connected with a slave unit, for example, through a common interconnect, e.g., a Processor Local Bus (PLB). The interconnect may include a pipelined request bus to transfer requests from the master unit to the slave unit, and to transfer responses to the requests from the slave unit to the master unit; a write data bus to transfer write data from the master unit to the slave unit; and a read bus to transfer read data from the slave unit to the master unit.
The master unit initiates transactions with the slave unit by issuing transaction requests over the request bus. For example, the master unit initiates a write transaction by issuing a write request for write data over the request bus; and initiates a read transaction by issuing a read request for read data over the request bus. An interconnect controller, e.g., an arbiter, may be implemented to control transactions over the common interconnect.
An immediate transaction may be performed, for example, if the read data is immediately available at the slave unit, or if the write data is immediately available at the master unit. For example, in an immediate write transaction, the slave unit responds to the write request by sending an acknowledgment response over the request bus, and the master unit provides the write data to the slave unit over the write bus. In the immediate read transaction the slave unit responds to the write request by sending an acknowledgment response over the request bus; and the slave unit provides the read data to the master unit over the read bus. A delayed read transaction is performed, for example, if the read data is not immediately available at the slave unit. In such case the arbiter indicates to the master unit that the read request has been accepted, but that the read data associated with the read request may be available at a later time. The master unit may withdraw the read request, and repeat the read request at a later time. Accordingly, in the delayed read transaction the master unit issues at least two transaction requests over the request bus, while in the immediate transactions the master unit issues a single transaction request.
It is desired to maintain a balance between acknowledged read and write requests, e.g., in order to efficiently utilize the read and write busses. The master unit is typically configured to arbitrate between the read and write requests according to a predefined fixed arbitration scheme.
USPTO Backgrounds
USPTO Backgrounds