In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures that include active or operable portions of semiconductor devices. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material including, but not limited to, bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term “substrate” refers to any supporting structure including, but not limited to, the semiconductive substrates described above.
Semiconductor chip processing technology involves miniaturizing a plurality of semiconductive devices and placing them side-by-side upon a wafer. As miniaturization technology progresses, it has become expedient to stack semiconductive devices in order to retain a small chip footprint. It is also necessary to connect stacked devices by way of formation of an interconnect corridor and by filling of the interconnect corridor with electrically conductive material, such as a tungsten stud. Metallization lines are formed that make electrical connection to the tungsten stud. These metallization lines need to be electrically isolated from semiconductive devices that are formed above an existing layer of semiconductive devices. To this end, an interlayer dielectric (ILD) such as an oxide or nitride is formed.
FIG. 1 is a cross-sectional view of a semiconductor structure 10 that depicts interconnects 12 within a dielectric layer 14. Semiconductor structure 10 has an upper surface 16 upon which an interlayer dielectric (ILD) layer 18 has been formed. The left half of FIG. 1 depicts an initial effect of formation of ILD layer 18 according to the prior art. It can be seen that the portion of interconnect 12 that was exposed as part of upper surface 16 of semiconductor structure 10 has formed an oxide husk 20 upon interconnect 12. Oxide husk 20 is formed either after planarization to form upper surface 16, such as by chemical-mechanical planarization (CMP) or during the deposition of ILD layer 18. Where interconnect 12 is a tungsten plug, oxide husk 20 forms into tungsten oxide (WO3).
Further processing of semiconductor structure 10, including thermal processing, causes complications that arise in the prior art. The right half of FIG. 1 depicts one prior art problem. It can be seen that, due to a large stress between oxide husk 20 and interconnect 12, oxide husk 20 has delaminated from interconnect 12 due to adhesion failure, and pushed upwardly to form a void 22 immediately above interconnect 12. Void 22 causes planarity problems and can also lead to underetched trenches prior to metal fill. The delamination of oxide husk 20 is an indication of a relatively thick oxide over interconnect 12. The thickness of oxide husk 20 can range from about 10 Å to about 500 Å. Oxide husk 20 needs to be removed prior to deposition of a metal line. The presence of void 22 causes a prominence in the ILD topology. The prominence can lead to underetched trenches prior to metal fill, resulting in the metal line not making sufficient electrical contact with interconnect 12. In addition, the prominence caused by the formation of void 22 can be formed during ILD deposition. Additionally, the prominence formed due to void 22 could cause some imaging problems because of a departure from substantial planarity of the upper surface of the ILD.
The delamination of oxide husk 20 from upper surface 16 immediately above interconnect 12 creates significant yield problems and device failure both during device testing and in the field.
What is needed in the art is a method of overcoming the prior art problems. What is also needed in the art is a method of forming an ILD layer without the formation of an oxide husk and the subsequent formation of a void between the top of the interconnect and the ILD layer. What is needed in the part is a method of preventing or reducing the oxidation of the upper surface of a metallic interconnect during the formation of an interlayer dielectric.
USPTO Backgrounds
USPTO Backgrounds