The advent of Ultra Large Scale Integrated (ULSI) circuits has allowed semiconductor manufacturers worldwide to fabricate semiconductor devices to extremely compact dimensions. The formation of electric circuits involves the fabrication of effective isolations between devices. Thus, to fabricate ICs, devices isolated from one another must first be formed in the silicon substrate. Establishing effective isolation in submicron ICs in the face of decreased isolation space is a complicated and challenging task.
Trench isolation is used primarily for isolating devices in VLSI and ULSI, and hence they can be considered as replacements for conventional LOCOS isolation. It is because of this that the LOCOS suffers many problems, such as "bird's beak" structure. The bird's beak shape causes unacceptably large encroachment of the field oxide into the device active regions. In addition, the planarity of the surface topography is inadequate for submicron lithography needs.
In basic shallow trench isolation (STI) technology, shallow trenches are anisotropically etched into the silicon substrate. A CVD oxide is deposited onto the substrate and is then planarized by CMP (Chemical Mechanical Polishing) or etching back. Another approach to shallow trench isolation is called a Buried Oxide with Etch-Stop process (BOXES). The process uses a silicon-nitride etch-stop layer and a pad layer formed on the substrate before the CVD-oxide is deposited.
As shown in FIG. 1, on a silicon substrate 1 a pad oxide 5 and a silicon nitride layer 7 are respectively formed on the substrate 1. Problems associated with the formation of shallow trench isolation include a dishing effect 3 of the wide trench, the erosion of nitride on a small area, and oxide 4 remaining on large silicon nitride area 6. The dishing effect degrades the planarity of a layer and impacts the control of implantation during the implantation process. Isolated devices are fabricated in the area denoted by 2, although silicon nitride may erode the area completely. This will damage the silicon substrate 1 and devices that are fabricated here. The oxide 4 that remains on the silicon nitride layer makes wet strip of silicon nitride unlikely.
One approach to solve the aforementioned problems is to form a "reverse tone" structure over the substrate. Turning to FIG. 2, a pad oxide layer 5 and a silicon nitride layer 7 are respectively formed on a silicon substrate 1. In order to overcome the aforementioned problems, a plurality of protruding portions of the silicon oxide 9 are generated over the trench region. This structure is referred to as "reverse tone". The protruded portions can eliminate the dishing problem due to the removing rate of the CMP performed over the trench being faster than the neighboring regions.
However, a problem arises when forming the reverse tone structure by etching. Typically, the reverse tone structure is etched by using a high density plasma (HDP) etcher such as, for example, the Omega HDP oxide etcher. The etching rate on large oxide areas is slower than that on small oxide areas. This is referred to as the so-called "reverse micro loading effect". Thus, a thicker oxide 11 remains on the surface of the large silicon nitride area 6 after the reverse tone structure is formed. After a chemical mechanical polishing is completed, the unacceptably severe SiN erosion problem persists and a significant amount of oxide remain on a large area.
USPTO Backgrounds
USPTO Backgrounds