1. Field of the Invention
The invention relates to a method of fabricating a memory.
2. Description of Related Art
Generally, with the gradual reduction of the size of the memory, a self-aligned contact (SAC) process is adopted to overcome the reduction in line width and prevent the misalignment of contact holes.
In the SAC process, the thickness of the spacers on the sidewalls of the gates affects the size of the contact holes formed between the gates. However, as a memory device includes a memory region and a periphery region, and the devices in the memory region and the periphery region require different thicknesses of the spacers, the process becomes more complicated. Conventionally, the first spacers are formed on the sidewalls of the gates in the memory region and the periphery region simultaneously. Afterwards, the second spacers are usually formed on the first spacers on the gates in the periphery region. Herein, for the convenience of the process, the material of the second spacers is filled into the openings between the gates in the memory region simultaneously. The second spacers in the periphery region and the material of the second spacers between the gates in the memory region are simultaneously removed after the source and drain region is formed in the substrate in the periphery region.
Nevertheless, as the openings between the gates in the memory region have a larger depth to width ratio, the removal of the material of the second spacers between the gates is difficult and the first spacers in the memory region may be damaged during the removal. Hence, the first spacers fail to provide superior electrical insulation for the gates and affect the size of the contact holes formed subsequently using the first spacers. In addition, unfavourable removal conditions damage the substrate in the periphery region and thus lead to deterioration of device characteristics.
USPTO Backgrounds
USPTO Backgrounds