(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to create contact holes, through multi-layered insulators, to an underlying semiconductor surface.
(2) Description of Prior Art
The semiconductor industry is continually striving to reduce the cost of semiconductor devices, while still attempting to improve the performance of these same semiconductor devices. These objectives are being successfully addressed via micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features. Performance improvements are realized via reductions in performance degrading parasitic capacitance, obtained using sub-micron device features. In addition smaller chips, still offering device densities obtained with larger counterparts, allow more chips to be gained from a starting semiconductor substrate, thus reducing the processing cost for a specific semiconductor chip.
The use of sub-micron features also demand the use of contact holes with diameters as small 0.35 uM or less. In addition specific devices, such as dynamic random access memory, (DRAM), devices, are designed to use contact holes, opened to expose the surface-of the semiconductor substrate, with these contact holes opened in, thick, multi-layered, insulator materials. For example a first insulator layer may be used to passivate a storage node contact plug, while a second insulator, third and fourth insulator layer, may be used for insulating the stacked capacitor structure, used in DRAM devices. The cumulative thickness of these insulator layers, in combination with the sub-micron diameter used for contact holes to the semiconductor substrate, result in contact holes with high aspect ratios, and present difficulties when attempting to metal fill.
A stacked contact procedure features a first, or lower contact hole opening, in underlying insulator layers, with metal filling, performed at a specific stage of the DRAM procedure. After deposition of the overlying insulator layers, a second, or upper contact hole is opened, exposing the underlying, metal filled, lower contact hole. The stacked contact procedure is concluded by metal filling the upper contact hole. Since the stacked contact procedure is comprised of two contact openings and two metal fills, the aspect ratio for either contact opening is reduced, when compared to one step contact hole openings. However difficulties can arise using the stacked contact procedure, when attempting to align the upper contact hole opening, to the underlying metal filled, lower contact hole. Misalignment can result in metal plugs that are thin, or discontinuous, at the point where the contact holes meet, resulting in reliability risks, in the form of electromigration.
This invention will describe a process for fabricating a stacked contact hole opening, in which the chance of misalignment between the upper and lower contact hole openings is reduced. This invention subjects the dry etched, lower contact hole opening, to a wet etch procedure, prior to metal fill, resulting in a larger diameter opening. The placement, or alignment, of the upper contact hole opening, to the larger diameter, metal filled lower contact hole, using the identical photolithographic mask previously used for the lower contact hole opening, will now be easier to achieve. Prior art, such as Cho, in U.S. Pat. No. 5,648,298, and Koyama et al, in U.S. Pat. No. 5,200,808, describe methods for forming contacts hole openings, but not the use of the stacked contact opening, using dry etched - wet etched lower contact openings, directly underlying am upper contact hole opening.
USPTO Backgrounds
USPTO Backgrounds