1. Field of the Invention
This invention generally relates to communication interfaces and, more particularly, to a system and method for transporting asynchronous data channels through a SFI4.2 interface.
2. Description of the Related Art
FIG. 1A is a schematic diagram depicting an SFI4.2 transceiver (prior art). A serial stream, divided into 64-bit segments, is received/transmitted at a clock rate of about 10 gigahertz (10 G), and transmitted/received via four SFI4.2 traffic lanes, at about 2.5 G per lane.
FIG. 1B is a logical model of an SFI4.2 transmit interface (prior art). A serial aggregate data stream is scrambled and striped into data lanes. The data is divided into 64-bit segments and scrambled. A “gearbox” 202 splits the data into four FIFOs (buffers) 204-0 through 204-3. The first 64-bit segment received is written into the buffer 204-0 associated with SLC10G_u_SFI4P2_TX_logical_lane[3] and the last segment is written into the buffer 204-3 associated with SLC10G_u_SFI4P2TX_logical_lane[0]. The buffers act as a set of FIFOs to bridge between the input timing domain and the transmit interface (line clock) timing domain.
A 01 sync header is prepended to each 64-bit segment to construct a 66-bit block prior to transmission. Each lane is transmitted 2 bytes (16 bits) after the previous lane so that the 4 lanes can start transmission in a 66-bit time period. SFI4.2 is a four lane interface, so each lane corresponds to an output driver.
In the receive direction, each lane has a framer that looks for “01” separated by 64 bits. Once it finds that word, then it goes “InFrame”. The data from the four lanes is recombined and descrambled, recreating the original signal. The transmit (line) clock for each SFI4.2 lane is 66/64 times the data clock used to load the FIFOs. The transmit and data clocks are synchronized.
FIG. 2 is the IEEE 802.3 method of 64b/66b encoding from FIG. 49-7 Section 49.2.4.4 of IEEE802.3-2008 (prior art). The method uses a 2-bit synchronization field. When the synchronization (sync) field is “10”, the following byte defines a Block Type field as a control code.
The current 10 G interface defined by the Optical Internetworking Forum (OIF) SFI4.2 (OIF-SFI4-02.0) is a synchronous interface. It is designed for 10 G, or slightly higher signals. SFI4.2 does not have the capability of supporting asynchronous signals or combinations of asynchronous sub-rate signals. It has one clock and four data lines.
One approach to building an asynchronous SFI4.2 interface would be to map the asynchronous subrate signals to another frequency and then transport them across SFI4.2. However, this would increase the operating rate of the SFI4.2 to higher than required.
It would be advantageous if a SFI4.2 interface could be adapted to communicate with one or more asynchronous data channels.
USPTO Backgrounds
USPTO Backgrounds