A display device driven by an active matrix mode includes an element such as a transistor which functions as a switch in a pixel, a driving circuit (a source driver) which is electrically connected to the pixel and outputs an image signal to the pixel when the switch is on, and a driving circuit (a gate driver) which controls switching of the switch.
Further, a transistor not only can function as a switch in pixels but also can form a gate driver. Therefore, a display device including the switches in the pixels and the gate driver which are formed using the transistors formed using a non-single-crystal semiconductor provided over an insulating substrate is developed.
The above gate driver is provided close to a pixel portion of the display device. However, the gate driver provided close to one side of the pixel portion results in a display portion being closer to one side than to the other. Thus, a display device which has gate drivers, which are formed by dividing a gate driver, placed in both right side and left side of the pixel portion is developed (for example, see Patent Document 1).
FIG. 10 illustrates the structure of the display device disclosed in Patent Document 1. In the display device illustrated in FIG. 10, a first gate driver 1002A and a second gate driver 1002B are provided so as to face each other with a pixel portion 1001 sandwiched therebetween. An output terminal of the first gate driver 1002A is electrically connected to an odd-numbered gate line. An output terminal of the first gate driver 1002B is electrically connected to an even-numbered gate line. That is, the first gate driver 1002A controls an electrical connection between a source driver and a pixel which is placed in an odd-numbered line in the pixel portion 1001, while the second gate driver 1002B controls an electrical connection between the source driver and a pixel which is placed in an even-numbered line in the pixel portion 1001.
Further, the first gate driver 1002A and the second gate driver 1002B each include a plurality of shift registers. An output terminal of the first shift register (SRC1) is electrically connected to one of input terminals of a second shift register (SRC2) through a first gate line 10031. An output terminal of the second shift register (SRC2) is electrically connected to one of input terminals of a third shift register (SRC3) through a second gate line 10032. In a similar manner, an output terminal of a k-th shift register (SRCk) is electrically connected to one of input terminals of a (k+1)th shift register (SRCk+1) through a k-th gate line 1003k. That is, a signal for an electrical connection between a source driver and a pixel provided in one line is used as a start pulse signal of a shift register an output terminal of which is connected to a pixel provided in the next line.
USPTO Backgrounds
USPTO Backgrounds