a. Field of Invention
This invention relates to electrical packages and processes of assembly thereof. More particularly, the invention relates to electrical packages for integrated circuit devices and processes of assembly thereof.
B. Description of Prior Art
Electrical packages of the type shown in U.S. Pat. Nos. 3,648,131 or 3,340,438, both assigned to the present assignee, are sensitive to (1) thermal coefficient expansion (TCE) mismatch between the substrate or carrier and attached semiconductor devices and (2) reliability problems associated with (i) more than 100 solder pad or connections between a device and carrier and (ii) conductor personalization of the substrate to connect the integrated devices to the terminal pins or other external connections. One solution to a thermal mismatch or TCE problem is to select carrier materials that have substantially the same thermal expansion coefficient as that of the attached semiconductor devices. See, for example, U.S. Pat. No. 3,777,220, also assigned to the present assignee, which addresses the TCE mismatch problem but does not address the solder pad or conductor reliability problems. A solution for the solder pad reliability problem is to increase the number of integrated devices in a package but limit each device to less than 100 solder pads. However, a new problem is created by the large number of personalized substrates or carriers that are required to handle the various combinations of integrated devices. A circuit transposer may be interposed between the integrated devices and the carrier, as suggested in U.S. Pat. No. 3,588,616, to simplify the problem of personalizing each electrical package. However, a circuit transposer should be compatible with the carrier and semiconductor devices from a thermal coefficient expansion (TCE) standpoint. Also, the carrier conductor reliability problem should not be increased or transferred to the transposer. An electrical package that overcomes the problem of TCE mismatch between devices and carriers, part number personalization and control, and solder pad reliability for semiconductor devices and carriers should make the benefits of large scale integration technology more available to data processing systems.
USPTO Backgrounds
USPTO Backgrounds