(1) Field of the Invention
The present invention relates to a method for the production of an integrated circuit.
(2) Description of Related Art
Although applicable in principle to any desired integrated circuits, the present invention and the problem area on which it is based are explained with regard to integrated memory circuits in silicon technology. In the production of integrated circuits, in particular integrated semiconductor memory circuits, it is necessary to produce different types of contacts. In this case, it is desirable to produce these different contacts with the fewest possible lithography planes and etching steps in order to ensure a high alignment accuracy.
FIGS. 2a, b are diagrammatic illustrations of successive method stages of a known method for the production of an integrated circuit in silicon technology.
FIG. 2a shows an exemplary semiconductor substrate 1 with a memory cell arrangement that is not illustrated in any further detail. 60 designates an active region, for example a common source/drain region of two memory cells. GS1, GS2, GS3 are three gate stacks which are constructed from a polysilicon layer 10 with underlying gate oxide layer (not illustrated), a silicide layer 20 and a silicon nitride layer 30. IS is an insulation layer, for example made of silicon dioxide, in which three different contact types are to be formed, namely a first (critical) contact type CB, which makes electrical contact with the active region 60 between the two gate stacks GS1, GS2, a second contact type CD, which makes electrical contact with a further active region (not illustrated) in the substrate region between the gate stacks GS2, GS3, and a third contact type CG, which makes electrical contact with the gate terminal 20 of the third gate stack GS3.
Usually, the contact hole for the critical contact CB is etched separately, and then the two non-critical contact holes for the contacts CS and CG are etched simultaneously. This requires two lithography planes, which means that both lithography planes have to be aligned with the gate contact plane. Alignment fluctuations JS may occur as a result of this.
Since the metal plane M is subsequently aligned with CB (it cannot simultaneously be aligned with CD, CG as well), critical overlay tolerances OT result, as illustrated in FIG. 2b. In the worst case, such overlay tolerances OT may lead to short circuits in the metalization plane M (M0 to CD/CG).
The two planes CB and CD, CG cannot simply be combined since, during the etching, firstly silicon oxide IS and then silicon nitride 30 have to be etched. The silicon nitride etching would also remove the side insulation of the gate stacks (not shown in FIG. 2) and thus create a short circuit between the gate terminal and the contact CB.
USPTO Backgrounds
USPTO Backgrounds