In the fabrication of semiconductor devices, several levels of metallization are built on top of each other and separated by an insulating layer which prevents interference from one level to the next. If it is desired to provide an electrical contact between the various levels at a prescribed location, a conductor must pass through the insulating layer and make contact with each level of metallization.
In the past, a first level was fabricated and then covered with an insulating layer. A hole having vertical sidewalls was then cut through the insulating layer at the prescribed location and the next level of metallization was applied on top of the insulating layer. The conventional methods of sputtering or evaporating a conformed layer of metallization resulted in the even application of a thin layer of metal applied to all exposed surfaces. Occasionally, the metallization was applied too thinly in the hole, due to the sheer drop of the vertical sidewalls between the levels, and a reliability problem developed due to insufficient metal in the hole to carry the current.
One attempt to solve this reliability problem has been to use tapered sidewalls in the hole. The first level of metallization was covered with an insulating layer in the same manner as before, but instead of cutting a hole with vertical sidewalls, a sloping or tapered sidewall was cut. This resulted in a hole with a larger diameter at the top surface where the second level of metallization was to be applied than at the bottom surface proximate the first level of metallization. The elimination of the sheer drop through the insulating layer allowed more metal to flow into the hole, resulting in the application of a thicker conductor which reduced occurences of the previous reliability problem.
Unfortunately, this solution of one problem led to the creation of another. As semiconductor devices have become more sophisticated, surface area has become a premium. The more space utilized for nonfunctional purposes, such as tapered sidewall holes, the less space there is for an electronic circuit. Therefore, the increased use of space by tapering the sidewalls has become an undesirable waste of limited surface area. Thus, a need has arisen for an interconnection between metallization layers of a semiconductor device separated by an insulator that is reliable and yet does not waste space.
USPTO Backgrounds
USPTO Backgrounds