In semiconductor memory, proper operation of the memory is based on the correct timing of various internal command, data, and clock signals. For example, in writing data to memory internal clock signals that clock data path circuitry to latch write data may need to be provided with specific timing relationships with internal write command signals to properly enable the data path circuitry to provide the latched write data for writing to memory. If the timing of the internal write command signal is not such that the data path circuitry is enabled at the time the internal clock signal clocks the data path circuitry to provide the write data at an expected time, the write command may be inadvertently ignored or the write data provided to the memory may not be correct (e.g., the write data is associated with another read command).
Moreover, as known, a “write latency” may be programmed to set a time, typically in number of clock periods tCK, between receipt of a write command by the memory and when the write data is provided to the memory. The latency may be programmed by a user of the memory to accommodate clock signals of different frequencies (i.e., different clock periods). Internal clock, data, and write command paths should be designed to provide propagation delays for the respective signals to account for the latency, for example, write latency between receipt of a write command and receipt of the write data for the write command. Other examples of commands that may require the correct timing of internal clock, data, and command signals for proper operation include, for example, read commands and on-die termination enable commands.
Complicating the generation of correctly timed internal clock, data, and write command signals is the relatively high-frequency of memory clock signals. For example, memory clock signals can exceed 1 GHz. Further complicating the matter is that multi-data rate memories may receive data at a rate higher than the memory clock signal. An example of a multi-data rate memory is one that receives write data at a rate twice that of the clock frequency, such as receiving write data synchronized with clock edges of the memory clock signal. The frequency of the memory clock signal may be the frequency at which write commands are executed. As a result, the timing domains of write command and clock signals may need to be crossed in order to maintain proper timing of the internal clock, data, and command signals.
An example conventional approach to maintaining the timing of internal write command, data, and clock signals is modeling both the clock and data path, and the write command path to have the same propagation delay. This may require, however, that delays and/or counter circuitry run continuously during memory operation. As a result, power consumption may be higher than desirable. Additionally, the propagation delay of the various internal clock, data, and command paths can often vary due to changes in power, voltage, and temperature conditions. For clock and write command paths having relatively long propagation delay or additional delay circuitry, the variations due to changing operating conditions may negatively affect the timing of the internal signals to such a degree that the memory does not operate properly.
USPTO Backgrounds
USPTO Backgrounds