1. Field of the Invention
The present invention relates to a method of fabricating a barrier layer and more particularly to a method of fabricating a barrier layer on top surfaces of metals in damascene structures utilizing ion implantation.
2. Description of the Related Art
As the demand increases for cheaper, faster, less power consuming yet more powerful integrated circuits, such as microprocessors and memory devices, the transistor packing density of the integrated circuit must be similarly increased. Very large scale integration (VLSI) techniques are very common place and yet the demand for even more reduced scale devices is ever present. All aspects of the integrated circuit must be scaled down to fully minimize the device dimensions. In addition to minimizing transistor dimensions, one must minimize the dimensions of the electrical interconnections which connect the transistors together on a microchip to form a complete circuit.
Currently, metals such as copper, aluminum, gold and silver, as well as others, are used as conductive materials for electrical interconnections in a VLSI integrated circuit. However, aluminum alloys are most commonly used and its alloys have been fully explored and characterized for use as an electrical interconnection in an integrated circuit, and much technology has been developed to aid in the formation of aluminum interconnections. Aluminum has very attractive features for use as an integrated circuit electrical interconnection, such as low electrical resistivity and strong adhesion to silicon dioxide. However, as VLSI dimensions move into the deep-sub micron Ultra Large Scale Integration (ULSI) arena, the deficiencies of aluminum and its alloys become limiting factors in achieving superior performance. For example, as the width of electrical interconnections becomes narrower, even the low resistance of aluminum becomes non-negligible and begins to slow down the signal speed. Hence, barrier layers are necessary due to decreasing dimensions and design rules become increasingly restricted by aluminum interconnection reliability concerns such as electromigration, stress-induced void formation, hillock suppression, and current density limitations.
Also, the microelectronics industry has recently migrated towards the investigation of more robust and conductive metals for use in interconnection technology, such as Copper (Cu). Cu is approximately 40% lower in resistivity than Al and is much more resistant to reliability problems such as electromigration. Unfortunately, Cu has been known to cause other reliability problems associated with the high rate of Cu diffusion through silicon substrates and dielectric films. One such problem is electrical shorting, wherein the Cu from one Cu interconnect line diffuses into an adjacent dielectric region, forming a conductive path to another Cu interconnect line. Another problem is transistor poisoning, wherein Cu diffuses into the underlying silicon substrate and causes junction leakage along with reduced channel mobility in the transistor, thereby destroying the device. Thus, to implement Cu as an interconnect material it has become necessary to develop methods for preventing Cu from diffusing through layers of a semiconductor device. Hence, various means have been suggested to deal with the problem of copper diffusion into integrated circuit material. Several materials, especially metallic ones, have been suggested for use as barriers to prevent the copper diffusion process. Tungsten, molybdenum, and titanium nitride (TiN) have all been suggested for use as copper diffusion barriers.
However, barriers for these conductive metals cannot be deposited onto substrates, or into vias, using conventional metal deposition processes, such as sputtering, since the geometries of the selected IC features are small. It is impractical to sputter metal to fill small diameter vias, since the gap filling capability is poor. Thus, new deposition processes such as CVD, have been developed for use with these barrier materials in the lines and interconnects of an IC interlevel dielectric. In a typical CVD process, the barrier material is combined with a ligand, or organic compound, to make the barrier material volatile. That is, the barrier material is vaporized into a gas and the metal is exposed to the barrier material gas in an elevated temperature environment. When the barrier material gas compound decomposes, the barrier is left behind on the metal surface.
However, CVD involves considerable process complexity, particularly in the fabrication process for the provision of a barrier layer on top surfaces of metals in damascene structures. Hence, what is needed is a method of fabricating a barrier layer which does not employ CVD and which is cost effective and involves less complexity.
The present invention is directed to a simplified, CVD-less method of forming a barrier layer for a metal layer which prevents metal contamination in an integrated circuit. The invention utilizes a sacrificial multilayer dielectric structure and selective etching to form the barrier layer. An opening is etched in the structure and a plating layer is deposited in the opening. A first unneeded portion of the structure along with an unneeded portion of the plating layer is removed utilizing an etchant that is selective for the first unneeded structural portion. A metal layer is deposited and implanted with barrier material to form the top barrier layer. A second unneeded portion of the structure along with an unneeded portion of the top barrier layer is removed utilizing an etchant that is selective for the second unneeded structural portion.
The resulting structure is a metal interconnect structure having an overlying top barrier layer which is produced without using CVD techniques.
USPTO Backgrounds
USPTO Backgrounds