An increasing need exists for customisable and flexible solutions for implementing communications protocols, while also meeting ever-increasing speed requirements. The growing need for flexibility in implementing communications protocols stems from changes that are often made to protocol standards in order to meet the demands of technology as it evolves. In this highly competitive market, manufacturers attempt to provide solutions to the market that implement the most current protocols as soon as the standards are finalized.
To date, attempts have been made to meet speed requirements by implementing communications protocols in custom-built ASICs (Application Specific Integrated Circuits). ASIC implementations are typically very fast, low power, and, when manufactured in large enough volumes, very cost-effective. However, since ASICs have fixed hardware architectures, ASIC solutions that have been implemented for these purposes lack the flexibility that is needed to meet changes in protocol standards and technology.
In order to provide cost-effective protocol implementations that are flexible and modifiable, some designers have utilized firmware (FW) in combination with Reduced Instruction Set Computer (RISC) processors. The term firmware typically is used to denote hard coding a computer algorithm in memory. A RISC processor is a processor that uses a relatively small instruction set and that capitalizes on the instructions that are executed most often, while also utilizing optimization to maximise execution speed. Although FW/RISC solutions provide some implementation flexibility, such solutions typically are much slower in speed and higher in power consumption than ASIC solutions.
Recently, some designers have implemented protocols by interfacing a RISC processor with a block of programmable logic, such as field programmable gate arrays (FPGAs). This hybrid combination provides some implementation flexibility and relatively high processing speed because it incorporates the speed benefits associated with hardware and the flexibility benefits associated with firmware. However, the costs associated with using FPGA logic are still high when compared with the costs associated with using mass-produced ASICs. Also, FPGAs typically consume more power and run at lower speeds than ASICs. Furthermore, FPGAs are limited with respect to the speed and resolution with which they can be reprogrammed, which restrains the level of reconfigurability available at real time communications speeds.
Accordingly, a need exists for a high-speed communications protocol implementation solution that is flexible so that it can be easily and quickly modified as existing protocols change or as new protocols are adopted, and that is reconfigurable in real time to meet the needs of communications speeds.
USPTO Backgrounds
USPTO Backgrounds