1. Field of the Invention
The invention relates to a vertical DRAM and a fabrication method thereof, and more particularly, to a vertical DRAM with annular sources/drains and annular channels and a fabrication method thereof.
2. Description of the Prior Art
With the development of modern technology, integration circuits and electrical products have been pushed for size reductions to match the trend of high integration and high density. In a conventional planar trench capacitor DRAM, the source, gate, and drain of a MOS transistor are horizontally located on the surface of the substrate. The distance between the source and the drain determines the length and width of the channel of the gate, which is an important factor affecting the design of the size of the MOS transistor. In a conventional design, the distance between the source and drain occupies larger area and may limit the improvement of the integrations of the semiconductor elements. Therefore a vertical transistor structure is produced.
Generally speaking, the fabrication of a vertical transistor structure involves etching the substrate for producing a deep trench, fabricating a trench capacitor in the deep trench, and locating the drain, gate, and source vertically in the deep trench so that a vertical channel is formed in the upper portion of the deep trench to reduce the horizontal area per transistor. Since a plurality of vertical transistors arranged in a matrix form a vertical DRAM, the vertical transistor can raise the integration of the semiconductor elements. The prior-art fabrications of the vertical DRAM have been disclosed in U.S. Pat. Nos. 6,583,462 and 6,608,168.
However, the prior-art vertical DRAM has a disadvantage that the width of the channel is too narrow, especially when the size of the trench capacitor is smaller 0.1 μm. A narrow width of the channel may cause the sufficient current to be too small, resulting in a bad performance of the DRAM. According to the prior-art vertical DRAM, after fabricating the capacitor and transistor in the deep trench, most of the upper portion of the deep trench is removed for forming the shallow trench isolation (STI) and defining the active area. Therefore the gate conductive layer, drain, and source of the transistor, and even the capacitor, can only use a portion of the sidewall of the deep trench. As result, the size of the gate conductive layer, drain, and source fix the width of the channel, formed as the transistor opening, in a small portion of the sidewall of the deep trench.
USPTO Backgrounds
USPTO Backgrounds