1. Field of the Invention
This invention relates to a semiconductor memory device, a semiconductor device and methods of manufacturing them, portable electronic equipment, and an IC card. More particularly, it is well suited for applications to an electrically erasable and programmable semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
An electrically erasable and programmable memory element is, for example, a flash memory. The structural sectional view of the element of the general flash memory is shown in FIG. 25. The element has a structure wherein a floating gate 906 made of polysilicon is arranged above a semiconductor substrate 901 via a first oxide film 904, a control gate 907 made of polysilicon is arranged above the floating gate 906 via a second oxide film 905, and a pair of source and drain diffused regions 902 and 903 are arranged in and on the surface of the semiconductor substrate 901. The control gate 907 functions as the gate electrode of a field effect transistor (FET) in the flash memory. Besides, the first oxide film 904, floating gate 906 and second oxide film 905 are interposed between the control gate 907 and the semiconductor substrate 901. That is, the flash memory is a memory wherein a memory film (the floating gate) is arranged in the gate oxide film portion of the FET, thereby fulfilling the function of changing the threshold voltage of the FET in accordance with the quantity of charges stored in the memory film (refer to, for example, “Handbook of Flash Memory Technology” edited by Fujio Masuoka, published by Kabushiki Kaisha Science Forum on Aug. 15, 1993, P55–58).
The problem of so-called “over-erasure” is involved in the flash memory of the above structure. More specifically, an erasing operation of the flash memory is to lower the threshold voltage of the FET in the flash memory by extracting electrons stored in the floating gate or injecting holes into the floating gate. Since, however, the erasing operation is executed excessively, the FET turns ON under the influence of the charges stored in the floating gate locating below the gate electrode (that is, the control gate), without applying any voltage to the gate electrode of the FET, so that current flows through the source and drain diffused regions. The phenomenon is ascribable to the structural feature of the flash memory that the control gate being the gate electrode as the FET, and the floating gate being the memory film as the memory are stacked vertically, so the FET turns ON due to only the stored charges of the floating gate, without applying any voltage to the control gate. This leads to a leakage current from a non-selected memory cell. Accordingly, such defective readout occurs that the readout current from a selected memory cell fails to be detected because of the leakage current.
USPTO Backgrounds
USPTO Backgrounds