1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor device manufacturing method. The invention particularly relates to a semiconductor device and a semiconductor device manufacturing method that are suitable for application in a semiconductor device including a dynamic random access memory (DRAM) capacitor.
Priority is claimed on Japanese Patent Application No. 2007-177188, filed Jul. 5, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
Memory cells such as a DRAM include switching transistors and capacitors. With the advancement of minute work techniques, memory cells are becoming increasingly miniaturized. This has led to a problematic decrease in the amount of charge accumulated in the capacitor. To solve this problem, the height of the capacitor is increased by utilizing a capacitor over bit-line (COB) structure and forming a cup-shaped capacitor over the bit-line so that the area of the capacitor electrode is increased.
FIG. 8 is an explanatory diagram of part of a cross-sectional structure of a semiconductor device of related art. FIG. 8 is a cross-sectional view in a direction parallel to a gate wiring. A gate interlayer insulating film 1 shown in FIG. 8 is made of such as silicon oxide film. A cell contact plug 2 shown in FIG. 8 is made of such as polysilicon. A switching transistor (not shown) is provided below the gate interlayer insulating film 1. The cell contact plug 2 is electrically connected to an impurity dispersion layer of the transistor.
A first interlayer insulating film 31 is formed over the gate interlayer insulating film 1 and the cell contact plug 2. The first interlayer insulating film 31 includes a plug interlayer insulating film 3, and a bit-line interlayer insulating film 8 which is provided on the plug interlayer insulating film 3. The plug interlayer insulating film 3 is made of silicon oxide. The bit-line interlayer insulating film 8 is made of silicon oxide. A plurality of bit-lines 51 are provided on the plug interlayer insulating film 3. Each bit-line 51 includes a tungsten nitride film 5 and a metal film 6 such as tungsten film. The tungsten nitride film 5 and the metal film 6 are each covered by a bit-line insulating film 7 of silicon nitride film. The bit-line 51 that overlaps with the cell contact plug 2 is electrically connected to the cell contact plug 2 by a bit contact plug 4. The bit contact plug 4 is composed of such as metal that penetrates the plug interlayer insulating film 3.
A capacitor contact plug 112 shown in FIG. 8 is made of such as polysilicon. The capacitor contact plug 112 penetrates through a first interlayer insulating film 31. The capacitor contact plug 112 is electrically connected to an impurity dispersion layer of a transistor (not shown) arranged lower than the interlayer insulating film 1, via the cell contact plug 2.
A second interlayer insulating film 41 is provided on the first interlayer insulating film 31. The second interlayer insulating film 41 includes a silicon nitride film 13 and a silicon oxide film 14. A capacitor 119 shown in FIG. 8 includes a lower electrode 116, a capacitor insulating film 117, and an upper electrode 118. The capacitor 19 penetrates through the second interlayer insulating film 41. As shown in FIG. 8, the lower electrode 116 is formed in a cup-shape that covers a bottom face and a side face of a cylinder 15. The lower electrode 116 is made of polysilicon, titanium nitride, or the like. The lower electrode 116 is electrically connected to the capacitor contact plug 112. As shown in FIG. 8, the lower electrode 116 covers the side face and top face of a top part 112a of the capacitor contact plug 112. The top part 112a of the capacitor contact plug 112 intrudes such as to fit into a bottom wall 116a of the lower electrode 116. A capacitor insulating film 17 is formed between the upper electrode 18 and the lower electrode 116.
In the semiconductor device of related art shown in FIG. 8, when forming the capacitor contact plug 112, a capacitor contact hole for forming the capacitor contact plug 112 is provided between adjacent bit-lines 51. To form the capacitor contact hole, it is conventional to use a self-aligned contact (SAC) etching technique in which etching is executed using an etching selection ratio of the bit-line interlayer insulating film 8 of silicon oxide to the bit-line insulating film 7 of silicon nitride.
However, as semiconductor devices become more miniaturized and thinner, it is becoming difficult to employ SAC etching in forming a capacitor contact hole. To maintain a short margin between the capacitor contact plug 112 and the bit-lines 51, the diameter of the capacitor contact plug 112 is shortened, and the capacitor contact plug 112 is formed by non-SAC.
As semiconductor devices become more miniaturized and thinner, to increase the area of the lower electrode 116 of the capacitor 119, if the height of the capacitor 19 is increased, the aspect ratio (height/hole diameter) of the cylinder 15 becomes larger. As a result, the size of the bottom diameter (diameter of the bottom face) of the cylinder 15 decreases with respect to that of the top diameter (diameter of the opening) of the cylinder 15. This reduces the area of the bottom face of the lower electrode 116 of the capacitor 119 that is electrically connected to the capacitor contact plug 112.
Since the diameter of the capacitor contact plug 112 and the area of the bottom face of the lower electrode 116 are decreasing in this way, the contact area between the capacitor contact plug 112 and the lower electrode 116 is being reduced.
Japanese Unexamined Patent Application, First Publication No. 2004-207681 discloses a semiconductor device in which an impurity dispersion layer of a cell transistor and a capacitor lower electrode are connected by a T-shaped contact plug.
Japanese Unexamined Patent Application, First Publication No. 2003-28734 discloses a semiconductor device in which roughness is imparted to a connection face between a source connection electrode and a source of a data transmission transistor.
Japanese Unexamined Patent Application, First Publication No. H 10-294441 discloses a semiconductor element including a connection plug having a protruding part, a top face and side faces of the protruding part contacting a first electrode of a capacitor.
Japanese Unexamined Patent Application, First Publication No. 2002-83881 discloses a semiconductor device including a DRAM in which polysilicon pads are provided between a cell contact and a bit contact, and between a cell contact and a cylinder-type accumulation capacitor lower electrode.
Japanese Unexamined Patent Application, First Publication No. 2005-167188 discloses a semiconductor device in which a top part area of a storage node contact plug is larger than a bottom part area, and the storage node contact plug is provided for electrically contacting a capacitor lower electrode and a plug.
However, even when using these conventional techniques, since the area of contact between the capacitor lower electrode and the capacitor contact plug is decreasing as semiconductor device become more miniaturized and thinner, the following problems arise. One problem is that the contact resistance increases, due to the reduced area of contact between the capacitor lower electrode and the capacitor contact plug. Another problem is that leak current increases, due to constriction of current at the connection section of the capacitor lower electrode and the capacitor contact plug.
The following problems also arise due to the reduced area of contact between the capacitor lower electrode and the capacitor contact plug. Due to plan-view positional deviation at the time of forming the lower electrode, there are cases where the lower electrode cannot be formed over the capacitor contact plug, in other words, cases where the lower electrode misses the capacitor contact plug.
USPTO Backgrounds
USPTO Backgrounds