1. Field of the Invention
The present invention relates to a duty cycle controlling circuit, a duty cycle adjusting cell and a duty cycle detecting circuit, and particularly relates to a duty cycle controlling circuit that can utilize more than one a duty cycle adjusting cell to provide a clock signal with a precise duty cycle, a duty cycle adjusting cell and a duty cycle detecting circuit
2. Description of the Prior Art
Since the speed requirement of modern electronic device largely increases, DCC (duty cycle controlling) performance becomes more and more important. However, traditional DCC circuits always include some defects. For example, such circuits may have high power consumption, large PSS (power supply sensitivity), DCD (Duty Cycle Distortion) accuracy over PVT issues and longer clock forward path delay. Besides, such circuits have large circuit region, slower locking time and slow duty cycle calculation response/tracking time. Additionally, the trade-off between duty cycle correction accuracy and clock range must be concerned. Also, the accuracy for such circuits is limited by its duty adjuster inverter P/N ratio.
USPTO Backgrounds
USPTO Backgrounds