1. Field of the Invention
The present invention relates to a semiconductor process, and more particularly, to a method of forming a load resistor of a static random access memory on the surface of a dielectric layer of a semiconductor wafer.
2. Description of the Prior Art
In a semiconductor process, polysilicon is often positioned to function as resistors. These resistors can be used in place of load transistors. When load transistors of a static random access memory (SRAM) is replaced by polysilicon, the number of transistors in the SRAM can be reduced and thus saves cost and enhance the integration of the SRAM.
Please refer to FIG. 1. FIG. 1 is a cross-sectional view of a prior art semiconductor wafer 10. The semiconductor wafer 10 comprises a silicon substrate 12, a metal-oxide-semiconductor (MOS) transistor 14 formed on the silicon substrate 12, an inter-poly dielectric (IPD) layer 16 deposited on the silicon substrate 12, a conductive resistance layer 18 deposited on the IPD layer 16, a contact hole 24 positioned in the IPD layer 16 for electrically connecting the MOS transistor 14 and the conductive resistance layer 18, a silicon nitride (SiN) layer 20 deposited on the IPD layer 16 and the conductive resistance layer 18, and an inter-layer dielectric (ILD) layer 22 deposited on the surface of the silicon nitride layer 20. The conductive resistance layer 18 is a linearly arranged poly-silicon layer. The IPD layer 16 is formed by neutral silicate glass for isolating poly-silicon layers. The ILD layer 22 is formed by borophosphosilicate glass (BPSG) for isolating the poly-silicon layers and metallic layers positioned on the ILD layer 22.
Please refer to FIG. 2. FIG. 2 is a cross-sectional view of the semiconductor wafer 10 when contact holes 26, 28 are formed. The contact holes 26, 28 are formed above the MOS transistor 14 and the conductive resistance layer 18, respectively. The contact hole 28 is formed through the ILD layer 22 and provides an opening through which the conductive resistance layer 18 may be connected to connections and components overlying the ILD layer 22. Likewise, the contact hole 26 is formed through both the ILD layer 22 and the IPD layer 16 and similarly provides an opening through which the MOS transistor 14 may be connected to overlying components.
The ILD layer 22 is formed by performing a high-density plasma-enhanced chemical vapor deposition (HDP CVD) process. The HDP CVD is performed by using a low energy ionic plasma source with a dosage of 10.sup.12 cm.sup.-2. The plasma source with such a dosage commonly causes plasma damages by accumulating an excess amount of electrons and positive charges on the surface of the conductive resistance layer 18, and radiation damages by radiating plasma onto the conductive resistance layer 18. Both plasma and radiation damages will result in instability of the conductive resistance layer 18, destruction of the structure of the MOS transistor 14, and thus a reduced breakdown voltage of the MOS transistor 14. However, the formation of the silicon nitride layer 20 on the surface of the conductive resistance layer 18 can serve as an anti-radiation layer to prevent the above mentioned problems from occurring.
Nevertheless, etching the contact hole 26 above the MOS transistor 14 through the silicon nitride layer 20 may deform the profile of the contact hole 26. The contact hole 26 is formed by performing a dry etching process followed by a wet etching process. The wet etching process is performed by using hydrofluoric acid (HF) to clean off polymers left behind on the surface of the contact hole 26. However, the hydrofluoric acid etches silicon dioxide (SiO.sub.2) more readily than it does silicon nitride (SiN). This difference results in the silicon nitride 20 protruding from the sidewall of the IPD layer 16 and the ILD layer 22 (as seen in FIG. 2) thus creating an uneven profile of the contact hole 26.
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