1. Field of Invention
This invention relates in general to a method of forming a shallow trench isolation (STI) region, and more particularly, to a method of effectively removing a silicon nitride layer from a backside of a wafer during the manufacturing process of a shallow trench isolation region.
2. Description of Related Art
In the conventional manufacturing process of hallow trench isolation regions, silicon nitride layers are deposited using low pressure chemical vapor deposition (LPCVD) methods. The silicon nitride layers are generally used as a photoresist layer, and as a polishing end point layer in chemical mechanical polishing (CMP) operations. However, the conventional process used to remove the silicon nitride layer from the backside of the wafer conflicts with the processing of shallow trench isolation regions, and can lead to semiconductors having poor electrical properties.
The use of low pressure chemical vapor deposition causes a layer of silicon nitride to be deposited on both the front and back surfaces of the wafer (wafer surface and wafer backside). The presence of a silicon nitride layer on the backside of the wafer can affect other subsequent manufacturing processes, for example, the stability of photolithographic and rapid thermal annealing (RTA) processes. Therefore, the silicon nitride layer on the backside of the wafer has to be removed prior to performing the subsequent processes. A conventional method used to remove the silicon nitride layer includes immersing the wafer in a hydrofluoric acid solution, which removes an oxide layer from the surface of the silicon nitride layer. This is followed by removing the silicon nitride layer using hot phosphoric acid. However, this process may result in the formation of grooves along an edge of a trench, which can lead to a "kink effect", which may increase the current leakage at a subthreshold voltage, thus affecting the electrical properties of the final transistor.
The presence of a silicon nitride layer on the backside of a wafer during the manufacturing of a shallow trench isolation region may adversely affect the characteristics of the transistor, due to the following reasons:
(1) the non-uniformity of the backside of the wafer may compromise the precision of the window opening formed using photolithographic processes;
(2) the possible stress created by the silicon nitriade layer on the silicon substrate while undergoing heat recycling (especially during the high temperature sealing process of the tetra-ethyl-orthosilicate (TEOS)) may increase the number of substrate defects; and
(3) as a result of an uneven thickness of the residual silicon nitride layer on the backside of the wafer, the sensitivity to surface temperature generated during rapid thermal annealing processes will be affected; consequently, temperature control precision in the rapid thermal annealing process is similarly affected.
FIGS. 1a through 1e are cross-sectional views of a shallow trench isolation region during the conventional manufacturing process. Referring to FIG. 1a, a pad oxide layer 101 is formed on the front surface of wafer (silicon substrate) 100. Simultaneously, a pad oxide layer 101' is formed on a backside of the wafer. Using LPCVP methods, a silicon nitride layer 102 is deposited over the front surface of the wafer. A silicon nitride layer 102' is simultaneously formed over the backside of the wafer. Referring to FIG. 1b, using photolithographic and etching processes, the silicon nitride layer 102, pad oxide layer 101, and wafer 100 are sequentially etched to form a shallow trench 103.
As shown in FIG. 1c, a side-wall oxide layer 104 is then grown on a surface of wafer 100 within the shallow trench 103. Concurrently, a silicon oxide layer 105 is formed over the backside of silicon nitride layer 102'.
Referring to FIG. 1d, TEOS, formed by atmospheric pressure chemical vapor deposition methods, fills the shallow trench 103 to obtain a dielectric layer 106 comprised of an oxide material.
Next, a sealing operation is performed. Due to the heat generated and the oxygen used during the sealing operation, the silicon oxide layer 105 at the backside of wafer 100 thickens.
Next, and using the silicon nitride layer 102 as a polishing end point layer, chemical mechanical polishing is used to remove extra portions of the dielectric layer 106. As a result, the cross-section shown in FIG. 1e is obtained.
In a subsequent step, the backside silicon nitride layer 102' has to be removed. The conventional method uses hot phosphoric acid to remove the backside silicon nitride layer 102'. However, the oxide layer 105 has to first be removed by immersing the layer in a solution of hydrofluoric acid. This process disadvantageously causes a portion of the oxide material of the dielectric layer 106 to be removed as well. Grooves are thus formed near the edges of the trench region, which may lead to the occurrence of the kink effect.
Referring to FIG. 2, an NMOS transistor having a gate oxide layer thickness of 60 .ANG., a drain voltage of 0.1 V, a channel width of 10 mm, a channel length of 0.25 mm, and a substrate voltage between about 0 and -4 V was provided and tested to determine the relationship between the drain current and the gate voltage when the kink effect was present. The relationship between the drain current and the gate voltage in the absence of such a kink effect is shown in FIG. 3. FIG. 2 shows that as a result of the subthreshold voltage distortion, a kink in the relationship graph is formed. This is the so-called kink effect.
USPTO Backgrounds
USPTO Backgrounds