The present invention relates to an integrated circuit such as an application specific integrated circuit (hereafter referred to as "ASIC"), for instance, and in particular, it relates to a circuit that facilitates the testing of such integrated circuits.
The full scan design method is one of the design methods for facilitating the preparation of test patterns in an LSI tester for integrated circuits. Through this method, a shift register operation is achieved by connecting all the sequential circuits such as flipflops that are present inside the circuit. Thus, it becomes possible to create a test pattern that achieves a high rate of error detection by improving the visibility and controllability of all the elements inside the circuit.
In the full scan design method, first a circuit that is not provided with a scan path circuit is designed, and then this circuit is automatically converted to a full scan circuit by employing a scan-enable tool. Through this conversion, the non scan-enabled flipflops are all converted to flipflops provided with a scanning function and by connecting scan paths, a shift register operation becomes possible.
A more detailed explanation is given on the concept of this circuit design in reference to FIGS. 1 and 2. It is to be noted that FIG. 1 is a schematic block diagram of an ASIC which is not provided with a test circuit, and FIG. 2 is a schematic block diagram of an ASIC provided with a test circuit.
During the initial stage of the design, first, an ASIC which is not provided with a test circuit, as shown in FIG. 1, is designed. The ASIC in FIG. 1 is provided with a user logic circuit 1 to which an input signal IN is input. The input side of a flipflop 2 is connected to the output side of the user logic circuit 1. The input side of a user logic circuit 3 is connected to the output side of the flipflop 2, and the input side of a flipflop 4 is connected to the output side of the user logic circuit 3.
Moreover, the input side of a user logic circuit 5 is connected to the output side of the flipflop 4, and an output signal OUT is output at the output side of the user logic circuit 5. A common clock signal CK is provided to the flipflops 2 and 4, and the timing for inputting and outputting data is in synchronization with the clock signal CK.
Next, by converting the flipflops 2 and 4 in the ASIC shown in FIG. 1 to flipflops provided with a scanning function (hereafter referred to as scan flipflops) 2A and 4A respectively using a scan-enable tool, a shift register operation via a scan path circuit becomes possible. It is to be noted that the scan flipflops 2A and 4A are structured identically to each other, each provided with a scan input terminal SD and a mode selection terminal SE in addition to a data input terminal D. Also, in these flipflops, input data IN provided to the data input terminal D are used as an input signal when a mode signal MOD provided to the mode selection terminal SE is set to "normal mode," whereas scan data SD provided to the scan input terminal SD are used as an input signal when the mode signal MOD is set to "scan mode."
The scan flipflop 2A may be provided with, for instance, a selector 2a, with the input side of the selector 2a connected to the input data terminal D and the scan input terminal SD. In addition, the mode signal MOD from the mode selection terminal SE is provided to a control terminal of the selector 2a. When the mode signal MOD is set to "normal mode," the input data terminal D is selected by the selector 2a, whereas when the mode signal MOD is set to "scan mode," the scan input terminal SD is selected by the selector 2a. The input side of a flipflop 2b is connected to the output side of the selector 2a, with the output side of the flipflop 2b constituting the output terminal of the scan flipflop 2A. Moreover, the clock signal CK is provided to the clock terminal of the flipflop 2b.
At the output side of the user logic circuit 5 at the last stage, the input side of a selector 6, which is controlled by the mode signal MOD, is connected, and the output signal OUT is output to the output side of the selector 6.
Moreover, in the ASIC in FIG. 2, the input side of the user logic circuit 1 and the scan input terminal SD of the scan flipflop 2A are connected with each other through a scan path 1S. In addition, the output side of the scan flipflop 2A and the scan input terminal SD of the scan flipflop 4A are connected with each other through a scan path 3S. The output side of the scan flipflop 4A and the input side of the selector 6 are connected with each other through a scan path 5S.
In the ASIC in FIG. 2 structured as described above, normal operation is performed by a logic circuit constituted of the user logic circuit 1, the scan flipflop 2A, the user logic circuit 3, the scan flipflop 4A, the user logic circuit 5 and the selector 6, by setting the mode signal MOD to "normal mode."
By setting the mode signal MOD to "scan modes" on the other hand, a scan path that sequentially connects the scan path 1S, the scan flipflop 2A, the scan path 3S, the scan flipflop 4A, the scan path 5S and the selector 6 is constituted. Then, when test data TD are input as an input signal IN, the test data TD are sequentially sent to the scan flipflops 2A and 4A and the selector 6 in conformance to the clock signal CK, to be output as an output signal OUT. By comparing the output signal OUT to the test data TD, the operations of the scan flipflops 2A and 4A within the ASIC can be checked.
USPTO Backgrounds
USPTO Backgrounds