This invention relates, in general, to semiconductor devices, and more particularly, to a monolithic polysilicon junction field effect transistor (JFET) and a method of integration with a power transistor to achieve a variable input impedance which is useful in protecting the power transistor.
In the past, several schemes have been used to protect semiconductor devices from potentially destructive voltages and currents. Such conditions are commonly encountered in the application of power semiconductor devices. For example, a power semiconductor device such as a power MOSFET, is frequently used to switch inductive loads. When the power MOSFET is switched off, the energy stored in the inductor will force the drain voltage of the power MOSFET to rise rapidly above the supply voltage. If no limiting means are employed, this rise will continue until the drain source avalanche voltage of the power MOSFET is reached, whereupon the energy stored in the inductor will be dissipated in the power MOSFET during device avalanche. Such dissipation leads to conduction in an internal parasitic bipolar transistor of the power MOSFET and can cause avalanche stress induced failure of the power MOSFET.
A more manageable form of stress commonly occurs in the operation of power semiconductor devices as the device switches current on and off within its normal mode of conduction. Such operation of a power MOSFET occurs when the current in the power MOSFET channel region is under the control of a gate of the power MOSFET. In this state, the internal parasitic bipolar transistor is non-conductive and device conduction stress can be regulated by appropriately modulating the signal on the power MOSFET gate. It is understood in the art of power MOSFET design and processing that the device conduction stress is less potentially destructive than device avalanche stress.
Various processing techniques are commonly employed to render the internal parasitic elements of the power MOSFET less susceptible to avalanche stress induced failure. A problem with these techniques is that normal variation in the processing parameters of a power MOSFET may inhibit operation or reduce the effectiveness of these techniques.
Other methods of protection involve the use of external devices to render the power MOSFET less susceptible to avalanche stress. One such method uses an external clamp diode whose avalanche voltage is less than that of the power MOSFET connected between the drain and source of the power MOSFET. When the rising drain-source voltage reaches the avalanche voltage of the drain-source clamp diode, the energy stored in the inductor is dissipated in the external drain-source clamp diode rather than the power MOSFET. This method requires the use of relatively large external drain-source clamp diodes which may, in fact, be more expensive than the power switching device which they are protecting. While the drain-source clamp diode is dissipating the inductive energy, the power MOSFET is idle.
A more advantageous method of protection involves diverting a small fraction of the inductive energy to the power MOSFET gate by means of a drain-gate clamp diode whose avalanche voltage is slightly less than the avalanche voltage of the power MOSFET. When a gate-drain diode clamp is used a resistor is coupled between the gate and source of the power MOSFET to dissipate any leakage current through the gate-drain clamp diode without activating the MOSFET gate. It is also desirable to place a blocking diode in series with the gate-drain clamp to block current flow from a gate signal source to the drain. This is often the case as typical gate-source voltages may be in the range of 10-40 volts while drain-source on-voltages may be only a few volts.
In operation, when a rising drain-source voltage exceeds the avalanche voltage of the drain-gate clamp diode, a current flows through the clamp diode. This current develops a voltage across the gate-source resistor which acts to turn the power MOSFET on. The gate-source voltage continues to rise until the power MOSFET is passing all of the stored inductive energy. Using this method, the power MOSFET dissipates the inductive energy in the less stressful conduction mode.
This protection scheme is usually implemented with discrete components connected externally to a power transistor. A monolithic integratable version of the draingate clamp protection method is described in co-pending U.S. application Ser. No. 278,988 which is owned by the same assignee as the present invention, and incorporated herein by reference. The integrated drain-gate clamp of the above identified application provides effective protection for the power device.
A convenient and effective way to drive the gate of the MOSFET when a gate-drain clamp is used calls for a series gate resistance to be connected between the power MOSFET gate and the gate signal source. This arrangement is useful in that the gate signal source is not loaded by the gate-source resistor when the power MOSFET is turned on, either in normal operation or avalanche mode operation. This series resistance also ensures the gate signal source does not draw current from the drain-gate clamp during an avalanche stress condition. If the signal source does draw current from the drain-gate clamp it becomes difficult or impossible to effectively turn the gate of the power transistor on when clamping is required. The series resistance, however, slows switching of the power MOSFET. Thus, this protection method offers outstanding protection against avalanche stress at the expense of degrading switching speed during normal operation.
Accordingly, it is an object of the present invention to provide a protection circuit for a power transistor comprising a variable input impedance.
Another object of the present invention is to provide a protection circuit for a power transistor which does not degrade switching speed of the power transistor.
Another object of the present invention is to provide a polycrystalline junction field effect transistor which can be used to provide variable input impedance.
Another object of the present invention is to provide an integratable monolithic variable resistance which is compatible with power MOSFET processing.
USPTO Backgrounds
USPTO Backgrounds