1. Field of the Invention
The present invention relates to high density integrated circuit devices including buried silicide conductors, and to methods for manufacturing such devices.
2. Description of Related Art
One common technology for interconnecting components on integrated circuits is the use of buried diffusion lines, which consist of lines of implanted dopants in relatively high concentration, so that they act as electrical conductors in the substrate.
A problem that arises with the use of buried diffusion lines is the loading effect due to their relatively high resistance. In operation, the relatively large resistance of the implanted dopants compared to that of metal results in increased power consumption and a reduction in the operation speed of the device. As a result, various techniques have been used to reduce the loading effect of the buried diffusion lines.
One approach is to reduce the resistance of the lines by increasing the dopant concentration. However, increasing the dopant concentration also increases the diffusion of the dopants into the substrate, making the implantation process more difficult to control. This can result in a loss of the desired pattern for the line, and limits the spacing between the lines.
Another approach to reducing the loading effect is to implement lower resistivity metal lines in parallel with the buried diffusion lines. Typically, the metal lines are formed on a dielectric layer overlying the buried diffusion lines. A series of metal contacts at intervals along a buried diffusion line extend through the dielectric layer to establish contact with a corresponding metal line. While parallel metal lines assist in reducing the loading effect of the buried diffusion lines, the metal lines and contacts can limit the density of the device and increase complexity of designs and manufacturing processes.
Silicides are also commonly used in integrated circuit manufacturing to increase the conductivity of doped lines or elements. A common version of the material is referred to as a “salicide”, changing the first two letters of the word to “sa-”, in a reference to self-aligned techniques for forming the material on the chip. A self-aligned process for forming silicide involves depositing a silicide precursor over a substrate that includes exposed regions of silicon, and annealing the silicide precursor to form a silicide in the exposed regions. Then the remaining silicide precursor on the substrate is removed, leaving the self-aligned silicide elements. Typical silicide precursors include metals or combinations of metals such as cobalt, titanium, nickel, molybdenum, tungsten, tantalum, and platinum. Also, silicide precursors may include metal nitrides or other metal compounds. Representative uses of silicide in integrated circuit manufacturing are shown in U.S. Pat. Nos. 7,365,385; 7,129,538; 7,081,377; 6,891,235; 6,815,298; 6,737,675; 6,653,733; 6,649,976; and 6,011,272; in U.S. Patent Publication Nos. 2001/0055838; and 2006/0017088. See also U.S. patent application Ser. Nos. 12/349903, and 12/349874, both applications commonly owned by the assignee of the present application and incorporated by reference herein.
Additionally, it is desirable to reduce the cross-sectional area or footprint of individual memory cells in an array of memory cells in order to achieve higher density memory devices. However, traditional field effect transistor access devices are horizontal structures having a horizontally oriented gate overlying a horizontally oriented channel region, resulting in the field effect transistors having a relatively large cross-sectional area which limits the density of the array. Attempts at reducing the cross-sectional area of horizontally oriented field effect transistors can result in issues in obtaining the current needed to induce phase change because of the relatively low current drive of field effect transistors. Thus, memory devices having vertically oriented field effect access devices have been proposed. See, for example, U.S. Pat. No. 7,116,593.
Accordingly, it is desirable to provide high density devices and methods for manufacturing such devices addressing the loading effect issues of doped semiconductor lines. In addition, it is desirable to provide high density devices that can be readily manufactured using these methods.
USPTO Backgrounds
USPTO Backgrounds