Memory devices are coupled in a mirrored configuration when at least some nodes of a memory device (e.g., address node A3) on one surface of a substrate are coupled to different nodes of a memory device (e.g., address node A4) on the opposite surface of the substrate. For example, in one embodiment, address nodes A3, A4, A5, A6, A7, A8, BA0 and BA1 of a memory device on one surface of a substrate might be respectively coupled to address nodes A4, A3, A6, A5, A8, A7, BA1 and BA0 of a memory device on the opposite surface of the substrate. Some dual- or higher-rank memory modules may couple memory devices in a mirrored configuration, such as to reduce address routing length, thereby improving signal integrity while reducing board space used for address routing. However, some single-rank memory modules may not be able to take advantage of mirrored configurations.
USPTO Backgrounds
USPTO Backgrounds