The present invention relates to an input circuit for semiconductor devices and more specifically to an input circuit suited for high-speed operation of semiconductor devices such as memories.
A circuitry of a conventional address buffer commonly employed for dynamic random access memories (DRAMs) is shown in FIG. 14(a). The address buffer in general is inserted between an address input signal and a decoder or pre-decoder so as to level and latch input signals.
Referring to FIG. 14(a), reference numerals 91, 94, 95 represent NAND gates, numerals 92, 96, 97 inverters, and 93 a D-latch. The conventional address buffer of such configuration takes in an address input signal Ai through the NAND gate 91 and inverter 92, latches it in the D-latch 93 and outputs internal address signals BiT, BiB through the NAND gates 94, 95 and inverters 96, 97. Designated .phi.1, .phi.2, .phi.3 are signals that specify capture, latch and output timings, respectively. The D-latch 93 outputs the state at the input D as is when the enable input E is high and, when E is low, retains the previous state. This latch may, for example, be formed by a circuit shown in FIG. 14(b).
The operation of this conventional address buffer is described by referring to operation waveforms shown in FIG. 15. During a standby state, i.e., when a row-address-strobe signal RAS is high, the signals .phi.1 and .phi.3 are low and the signal .phi.2 is high. Hence, because one of two N-channel MOS transistors forming the NAND gate 91 is cut off, a DC current does not flow, whether the address input signal Ai is high or low. Further, because the signal .phi.3 is low, both the output signals BiT, BiB are low.
When during operation the row-address-strobe signal RAS goes low, the signal .phi.1 goes high first to capture the address input signal Ai. At this point, the signal .phi.2 is still high, so that the input to the D-latch 93 appears as is at the output. Because the signal .phi.3 is low, the output signals BiT, BiB remain low. Then, the signal .phi.2 becomes low to latch the captured signal and at the same time the signal .phi.3 goes high causing one of the output signals BiT, BiB to go high. After this, if the input signal Ai changes, the output signals BiT, BiB do not change because the previously captured input signal is latched in the D-latch 93. When RAS returns to a high level, the signals .phi.1, .phi.2, .phi.3 return to their original levels, causing the output signals BiT, BiB to go low.
This conventional address buffer is suited as an address buffer for DRAMs in the following two points. First, because a DC current does not flow while in standby, as mentioned above, the address buffer consumes little power. Second, during the standby state, the output signals BiT, BiB are both low. During operation, the output signals BiT, BiB are complementary, that is, one is high and the other is low, causing a decoder to select one word line or bit line. During the standby, however, both of the output signals BiT, BiB are low to deselect all word lines or bit lines. DRAMs in particular require that the word lines be deselected or in a non-selected state during standby to retain stored information. This operation of the conventional address buffer is suited for DRAMs.
A circuit of a conventional pre-decoder used in DRAMs is shown in FIG. 16. Pre-decoding is to decode a part of an input signal for the decoder beforehand. Because pre-decoding reduces the number of fan-ins in the logic gate of the decoder, the use of a pre-decoder is effective in reducing the number of elements in the input logic gate of the decoder. In the case of a 10-bit address decoder, for instance, it requires a 10-input logic gate if pre-decoding is not performed whereas pre-decoding two bits at a time reduces the number of inputs of the logic gate to five.
A pre-decoder 98 in FIG. 16 comprises four NAND gates and four inverters and produces four pre-decoded signals Cij0-Cij3 by combining two pairs of internal address signals (output signals of address buffer) BiT, BiB, BjT, BjB. During standby, the internal address signals are all low as mentioned above and all the pre-decoded signals are also low. During operation, one of paired internal address signals BiT and BiB and one of paired internal address signals BjT and BjB go high. According to the combination of the high internal address signals, only one of the pre-decoding signals Cij0-Cij3 is high with the remaining three at low level.
Literatures related to this art include the IEEE Journal of Solid-State Circuits, vol.SC-18, pp457-463, October 1983.
The above-mentioned address buffer and pre-decoder that form the input circuit of a DRAM are not suited to high-speed operation, as explained below.
First, explanation goes to the conventional address buffer shown in FIG. 14. This circuit requires a timing margin, as indicated by T in FIG. 15, between the signal .phi.1 and the signals .phi.2, .phi.3 (signals .phi.2 and .phi.3 substantially coincide). This timing margin must be longer than a delay time which elapses from the moment the input is taken in by the signal .phi.1 to the moment the captured input signal appears at the output of the D-latch 93. Further, because the delay time varies due to manufacturing process and temperature variations, a sufficient margin should be taken so as to prevent erroneous operation even in the worst case. When this margin is not sufficient, e.g., when the margin between the signals .phi.1 and .phi.2 is not enough, there is a possibility of an erroneous signal being latched. When the margin between the signals .phi.1 and .phi.3 is insufficient, there is a possibility of a false signal being output temporarily. When the address buffer is used to input an address for selecting a word line for DRAM, the latter case, in particular, results in a wrong word line being selected temporarily, destroying stored information. The necessity of this timing margin limits the operation speed of the conventional address buffer, giving rise to the problem that it is not suited to high-speed operation.
Next, the conventional pre-decoder shown in FIG. 16 is explained. While pre-decoding, as mentioned earlier, is effective in reducing the number of fan-ins of the decoder, it has a problem of generating a delay. In the pre-decoder of FIG. 16, for example, there is generated a delay corresponding to two stages of logic gate.
It is an object of the present invention to provide an input circuit for semiconductor devices which solves the above problem and is suited to high-speed operation.
To achieve the above objective, the input circuit for semiconductor devices according to this invention comprises a differential amplifier that outputs a pair of differential signals in response to an input signal; and a latch means that detects, latches and outputs one of the paired differential signals that has changed first.
It is possible to provide a plurality of such latch means and connect the paired differential signals commonly to the inputs of the plurality of latch means.
In the input circuit for semiconductor devices, if an address signal is used as an input signal and a pair of complementary internal address signals are used as an output of the latch means, this input circuit would form a preferred address buffer. It is further preferred to provide the differential amplifier with an activate/inactivate means that performs, in response to the set signal, an activation whereby a potential difference is generated between the paired differential signals and an inactivation whereby the paired differential signals are made equal in potential. The activate/inactivate means may be formed in such a way as to turn on and off the power of the differential amplifier.
Further, the input circuit for semiconductor devices is characterized in that it has a plurality of differential amplifiers, each of which outputs a pair of differential signals in response to an input signal, and that it has at least a latch means which receives the plurality of pairs of differential signals and which detects, latches and outputs one of decoded sets of differential signals that has changed first. In this input circuit for semiconductor devices, too, it is preferred that the differential amplifiers each be provided with an activate/inactivate means, which performs an activation operation to generate a potential difference between the paired differential signals and an inactivation operation to make the potentials of the paired differential signals equal.
Further, it is possible to provide a plurality of sets of the differential amplifier and the latch means, the differential amplifier being adapted to output a pair of differential signals in response to an input signal, the latch means being adapted to detect, latch and output one of the paired differential signals that has changed first. It is also possible to provide a means which activates and inactivates each of the differential amplifiers in response to an input signal for each set supplied in a multiplexed mode to a common input terminal of the differential amplifiers of all the sets. It is preferred that the signal supplied to the differential amplifiers be made an address-multiplexed signal and that the output of each latch means be made a pair of complementary internal address signals.
The input circuit for semiconductor devices according to the present invention may also comprise a differential amplifier which outputs a pair of differential signals in response to an address input signal; an address counter which has a means to convert an input into a pair of complementary signal outputs; a mode switch means that switches between a normal operation mode for enabling the paired outputs from the differential amplifier and a refresh mode for enabling the paired outputs from the counter; and a latch means which receives the paired outputs from the differential amplifier and the paired outputs from the counter, latches one of the paired outputs enabled by the mode switch means that has changed first, and then outputs a pair of complementary internal address signals.
With the input circuit for semiconductor devices of the present invention, when the differential amplifier that outputs a pair of differential signals in response to an input signal is activated by a set signal from the activate/inactivate means, a potential difference is generated between the paired differential signals according to the input signal. The latch means, which takes in the pair of differential signals, detects one of the paired differential signals that has changed first and latches it. That is, the latch means requires no special timing signal for latching because it automatically performs the latch operation according to a change in the input signal. Thus, there is no need to provide a timing margin between the input capture by the differential amplifier and the latching, as is required in the conventional art, resulting in higher operation speed.
The input circuit for semiconductor devices, in which the paired differential signals from the differential amplifier are commonly fed to the plurality of latch means, can perform as a preferable address buffer for address-multiplexed DRAMs if the differential amplifier is supplied an address-multiplexed signal as its input.
Further, the latch means that receives a plurality of pairs of differential signals from a plurality of the above-mentioned differential amplifiers can incorporate a pre-decode function by being so configured as to detect one of decoded sets of differential signals that has changed first. Thus, it is not necessary to provide a separate pre-decoder, virtually eliminating a delay that would otherwise be caused by its logic gates, permitting high-speed operation.
When the differential amplifier is inactivated by the activate/inactivate means, the differential signals assume the same potential and at the same time the latch circuit is reset. If the power of the differential amplifier is turned on or off by the activate/inactivate means, when the power is turned off the output level of the input circuit becomes low and no DC current flows, realizing a low power consumption.
It is also possible to add a refresh function to the address buffer without increasing the number of logic gate stages if the input circuit for semiconductor devices comprises a differential amplifier which outputs a pair of differential signals in response to an address input signal; an address counter which has a means to convert an input to a pair of complementary signal outputs; a mode switch means to switch, as by a SetR signal and a SetX signal, between a normal operation mode for enabling the paired outputs from the differential amplifier and a refresh mode for enabling the paired outputs from the counter; and a latch means which receives the paired outputs from the differential amplifier and the paired outputs from the counter, latches one of the paired outputs enabled by the mode switch means that has changed first, and then outputs a pair of complementary internal address signals.
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USPTO Backgrounds