1. Field of the Invention
The present invention relates to a liquid crystal display device with a color image display function, and in particular to an active type liquid crystal display device that has a switching-element in each pixel.
2. Description of Related Art
In recent years, the increase in scale of glass substrate, corresponding elements and manufacturing devices, TVs and other commercially-available display devices have been produced with diagonal dimensions ranging from 5 to 100 cm. In addition, color display has been obtained easily by forming an RGB colored layer on one of the two glass substrates that are part of a liquid crystal panel. The active-type liquid crystal panels that have switching elements in each pixel, especially, are able to provide less cross talk, and therefore quick response speed, and images with high contrast ratio are ensured.
These liquid crystal display devices (liquid crystal panels) usually have a matrix formation of approximately 200-1,200 scanning lines and 300-1,600 data lines, but larger screens and higher precision are being offered simultaneously nowadays in order to meet the requirements of display capacity.
FIG. 19 shows the packaging structures of the liquid crystal panel. For example, the packing methods to provide electric signals to the active area include the COG (Chip-On-Glass) method, which is achieved by coupling a semiconductor integrated circuit chip 3 that provides driving signals with the electrode terminals 5 of scanning lines formed on one of the transparent insulating substrates that compose the liquid crystal 1 (for example, a glass substrate 2) through a conductive adhesive, or the TCP (Tape-Carrier-Package) method, which is achieved by pressure-coupling and fixing the TCP film 4 that has terminals of gold or solder-plated copper foil on a thin polyimide resin film base with the electrode terminals 6 of data lines through an appropriate adhesive that includes a conductive medium. For convenience, both of the packaging structures are shown in FIG. 19, but the most appropriate packaging structure between the two is selected in actual cases.
The wiring paths 7 and 8, which connect the pixels within the active area located in the near center part of the liquid crystal panel 1 and the electrode terminals 5 and 6 of scanning lines and data lines do not need to be composed of the same conductive material as the electrode terminals 5 and 6. Numeral 9 refers to a color filter or an opposed glass substrate that is a transparent insulating substrate having transparent conductive opposed electrodes respectively on its opposing surfaces, wherein the transparent conductive opposing electrodes electrically cover all the liquid crystal cells.
FIG. 20 shows the equivalent circuit of an active liquid crystal display device having an insulating gate type transistor 10 functioning as a switching element disposed in each pixel, wherein 11 (7 in FIG. 20) refers to the scanning line, 12 (8 in FIG. 20) refers to the data line, and 13 refers to a liquid crystal cell. The liquid crystal cells 13 are treated as capacitors for electricity. Elements drawn in solid lines are formed on glass substrate 2, which is a substrate of the liquid crystal panel. The opposing electrode 14 electrically covers all the liquid crystal cells 13 and shown by dotted lines in the figures formed on the opposed main surface of another glass substrate 9. In the case that the off resistance of the insulating gate type transistor 10 is low, the resistance of the liquid crystal cells 13 is low, or the tone of the display images is emphasized, a circuit processing such as adding an auxiliary storage capacitance 15 in parallel with the liquid crystal cell 13 is available in order to increase the time constant of the liquid cell 13 as a load. In addition, 16 refers to a storage capacitance line or a common electrode functioning as the common bus bar of the storage capacitance 15.
FIG. 21 shows the cross section view of the essential part of the active area of a liquid crystal display device. The two glass substrates 2 and 9 composing the liquid crystal panel 1 are separated in a specified distance of several μm by spacer materials (not shown) such as pillar-shaped spacers formed on the color filter 9, resin-based fibers, or resin-based beads. The gap between the glass substrates 2 and 9 is sealed to form a closed space by disposing a sealing material and an encapsulating material of an organic resin (not shown) at the periphery of the glass substrate 9. The closed space is filled with liquid crystal 17.
To obtain color display, a colored layer, which is a thin organic film of 1 to 2 μm in thickness containing a dye and/or pigment, is disposed on the lateral side of the closed space side of the glass substrate 9 to give the color display function. In such a case, the glass substrate 9 is called color filter (CF). Depending on the characteristics of the liquid crystal material 17, a polarizer 19 is attached to the upper surface of the glass substrate 9 and/or lower surface of the glass substrate 2 Therefore, the liquid crystal panel 1 can function as an electro-optical device. So far, most of the commercially available liquid crystal display panels use TN (Twisted Nematic)-type liquid crystal material, and normally require two polarizers 19. Transmissive liquid crystal panels, though not shown here, use back lighting as a light source that radiates white light up from a lower position.
Alignment films, for example, the polyimide based thin resin film 20 of approximately 0.1 μm in thickness formed on the glass substrate 2 and 9 in contact with the liquid crystal are used to orientate the liquid crystal molecules into specific directions. Numeral 21 refers to a drain electrode (wire) that connects a drain of the insulating gate type transistor 10 and a transparent conductive pixel electrode 22, and is normally formed at the same time as the data (source) lines 12 is formed. A semiconductor layer 23 positioned between the data lines 12 and the drain electrode 21 is explained later in detail. The Cr thin film layer 24 of about 0.1 μm in thickness is formed at the periphery of the adjacent colored layer 18 on the color filter 9, and is a light shielding component that prevents outside light from coming into the semiconductor layer 23, the scanning lines 11, and the data lines 12. This established technology is commonly known as black matrix (BM). Usually, the black matrix is made of black-pigment-dispersed type photosensitive resin with a thickness of around 1 μm.
Manufacturing an active substrate having pixel electrodes and insulating bottom gate transistors that include the scan lines, the data lines, and the switch elements need plural photolithography processes (developing and etching) that use masks to treat a semiconductor integrated circuit. Briefly, by rationalizing the processes of islanding the semiconductor layer and decreasing the processes of forming the contact with the scan line, the manufacturing method, which conventionally requires seven to eight photomasks and the introduction of dry etching, currently has been simplified to use five photomasks to decrease process costs. To reduce the production cost of the liquid crystal display device effectively, decreasing the process cost of the manufacturing processes of the active substrate, or the material cost of the panel assembling process and the module assembling process are well-known targets of development. Therefore, the manufacturing processes of the active substrate including photolithography processes are reduced, the yield of the liquid crystal display device is enhanced, and the cost of the liquid crystal display device is reduced.
As described above, the method for manufacturing an active substrate generally needs five photolithography processes. Part of the conventional methods for reducing manufacturing cost is introduced in the following description. A patent document 1, Unexamined Patent Application Number 7-74368 2000-206571, is an example of the prior art, which introduces a four-mask process. The four-mask process comprises rationalizing or reducing processes of islanding the semiconductor layer including a channel using halftone exposure technology and forming source/drain wires by one photomask. FIG. 22 is a plan view of a unit pixel of an active substrate corresponding to four-mask processes. Cross-section views of lines A-A′ (insulating-gate-type-transistor region), B-B′ (electrode-terminal region of scan line) and C-C′ (electrode-terminal region of data line) in FIG. 22(f) are shown in FIG. 23. So far, two types of the insulating gate type transistors are often applied more than others. Among them, a channel etch type insulating gate transistor is applied in the following example.
As shown in FIG. 22(a) and FIG. 23(a), a first metal layer of approximately 0.1-0.3 μm in film thickness is deposited on a main surface of a glass substrate 2 of 0.5-1.1 mm in thickness, such as Corning's product number 1737 as an example of an insulating substrate with high heat-resistance, high chemical-resistance, and high transparency, using a vacuum film-depositing equipment such as an SPT (sputtering). Besides, scanning lines 11 functioning as gate electrodes 11A and storage capacity lines 16 are formed selectively using fine-processing technology. The scanning line material is selected after considering the all-around heat resistance, chemical resistance, fluorinated acid resist, and conductivity, but a metal with high-heat resistance such as Cr, and Ta or an alloy such as MoW is commonly used.
In response to requirements for large screens and high precision of liquid crystal panels, it is reasonable to use Al (aluminum) as a material for scanning lines for lowering the resistance value of the scan lines. However, the general technique used today is a lamination of the heat resistant metals such as Cr, Ta, Mo, or their silicides because Al alone has low heat resistance. In other words, a scan line 11 consists of one or more metal layers.
Next, three kinds of thin film layers, such a first silicon nitride (SiNx) layer 30 functioning as a gate insulating layer, a first amorphous silicon (a-Si) layer 31 containing almost no impurities and functioning as a channel of an insulating gate type transistor, and a second amorphous silicon (n+a-Si) layer 32 containing phosphorous impurities and functioning as a source/drain of the insulating gate type transistor, are deposited in sequence over the entire surface of the glass substrate 2 by using a PCVD (plasma chemical vapor deposition) equipment with thicknesses of 0.3, 0.05, and 0.1 μm respectively for example. Subsequently, as shown in FIG. 22(b) and FIG. 23(b), a heat-resistant metal layer such as a Ti thin film layer 34 of about 0.1 μm in thickness, a low-resistance metal layer such as an Al (aluminum) thin film layer 35 of about 0.3 μm in thickness, and an intermediate conductive layer such as another Ti thin film layer 36 of about 0.1 μm in thickness are deposited in sequence by using a vacuum film-depositing equipment such as the SPT.
Then, the data line 12 functioning as the source electrode of the insulating gate type transistor composed of a laminate of the heat-resistant metal layer 34A, the low-resistance metal layer 35A, and the intermediate conductive metal layer 36A partially overlapping the gate electrode 11A, and the drain electrode 21 of the insulating gate type transistor composed of a laminate of the heat-resistant metal layer 34B, the low-resistance metal layer 35B, and the intermediate conductive metal layer 36B partially overlapping the gate electrode 11A are selectively formed at the same time by fine-processing technology. The formation of selective pattern is done by halftone exposure technology. As shown in FIG. 22(c) and FIG. 23(c), a notable feature of four-mask process is that the photosensitive resin pattern in the channel-forming-region 80B (diagonal line) between the source/drain electrodes is about 1.5 μm in thickness, and the photosensitive resin in the source/drain wires-forming-region 80A (12) and 80A (21) is about 3 μm in thickness, for example.
Photosensitive resin patterns 80A and 80B normally use positive photosensitive resin in the formation of the active substrate. Therefore, the photomask used here is black in the source/drain wires-forming area 80A, i.e. forming Cr thin film, gray (middle tone) in the channel-forming-region 80B, i.e. forming line-and-space (L&S) Cr patterns of 0.5-1 μm in width for example, to reduce the quantity of light passing through the photomask, and white in other areas, i.e. the photomask with removed Cr thin film. Line and space problems are not resolved since resolution of the exposure equipment is low in the gray area, and about half of the light from the lamp may be transmitted through the photomask. Accordingly, it possible to obtain photosensitive resin patterns 80A and 80B having a concave cross section as shown in FIG. 23(c) through the property of positive photosensitive resin. In addition, the gray area can be formed with a slit pattern by forming a metal layer with different thickness or transmittance, such as MoSi2 layer.
Then, as shown in FIG. 22(c) and FIG. 23(c), Ti thin film layer 36, Al thin film layer 35, Ti thin film layer 34, second amorphous silicon layer 33, and first amorphous silicon layer 31 are etched by using the photosensitive resin patterns 80A and 80B as a mask, and the gate insulating layer 30 is exposed. After that, more than 1.5 μm of the thickness of the photosensitive resin patterns 80A and 80B is reduced by an ashing method such as oxygen plasma ashing method to eliminate the photosensitive resin patterns 80B. Therefore, the Ti thin film 36 (not shown) in the channel-forming-region is exposed, and photosensitive resin patterns 80C (12) and 80C (21) the thicknesses of which are reduced, are formed in the source/drain wires-forming region.
The Ti thin film layer between the source/drain wires (i.e. the channel-forming-region), Al thin film layer, Ti thin film layer, second amorphous silicon layer 33A, and first amorphous silicon layer 31A are etched by using the photosensitive resin patterns 80C(12) and 80C(21) as the mask, and the residual thickness of the first amorphous silicon layer 31A is approximately 0.05-0.1 μm. Accordingly, the source electrode 33S and drain electrode 33D, which are both composed of the second amorphous silicon layer, are separated. The insulating gate type transistor manufactured in this method is called channel-etched type, and this method is achieved by leaving the first amorphous silicon layer 31A of approximately 0.05-0.1 μm in thickness after etching the metal layers for forming the source/drain wires. Furthermore, for the resist pattern 80A that is converted to 80C after its film is thinned down in the oxygen plasma treatment, it is desirable to strengthen anisotropy in order to regulate the pattern dimension changes. In general, oxygen plasma treatment of the RIE (Reactive Ion Etching) method, ICP (Inductive Coupled Plasma) method using high density plasma source, or TCP (Transfer Coupled Plasma) method high density plasma source is desirable.
Next, after removing the photosensitive resin patterns 80C(12) and 80C(21), a second SiNx layer of approximately 0.3 μm in thickness functioning as a passivation insulating layer 37 is deposited on the entire surface of the glass substrate 2. As shown in FIG. 22(e) and FIG. 23(e), openings 62, 63, and 64 are respectively formed on the drain electrode 21, and the electrode-terminal-forming-region of the scan line 11 and the data line 12 outside the active area by removing the passivation insulating layer 37 and the gate insulating layer 30 within the openings 63 to expose part 5 of scan lines, and removing the passivation insulating layer 37 within the openings 62, 64 to expose part of the drain wire 21 and part 6 of the data line at the same time. Similarly opening 65 is formed on the storage capacitor lines 16 and expose part of the storage capacitor lines 16.
Finally, a transparent conductive layer of approximately 0.1-0.2 μm in thickness, such as ITO (Indium-Tin Oxide), IZO (Indium-Zinc Oxide), or the mixture thereof, is deposited by using a vacuum film-depositing equipment such as the SPT. As shown in FIG. 22(f) and FIG. 23(f), a complete active substrate 2 is obtained by selectively forming a transparent conductive pixel electrode 22 containing the openings 62 in the passivation insulating layer 37 by using micro-processing technology. As for the storage capacitance 15, the storage capacitance 15 is formed in the area 50 (a diagonal line going up to the right hand side), where the storage capacity line 16 and the drain electrode 21 are overlapped level with the gate insulating layer 30, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33D sandwiched therebetween. As for the electrode terminals, transparent conductive electrode terminals 5A and 6A are formed on the passivation insulating layer 37 and the openings 63 and 64.
As the material of the source/drain wires 12 and 13 comprises Al, each of the source/drain wires 12 and 13 is a laminate of three layers because the source/drain wires 12 and 13 need the heat-resistance metal layer 34 to ensure the electrical connection between the second amorphous silicon layer and the source/drain wires, and the intermediate conductive layer 36 to avoid an oxidation-reduction reaction occurring between the transparent conductive layer and the source/drain wires. Moreover, it is difficult to avoid using the low-resistance metal layer in the liquid crystal display device with large panel size or high picture quality due to the strict electrical resistance of the source/drain wires. In addition, as the materials of the heat-resistant metal layer 34 and the intermediate metal layer 36 are both Ti, they must be dry etched by using chlorinated gas for example, and spontaneously the layer of Al is dry etched by chlorinated gas. Thus, burdens of the material choice and the production equipment are increased. On the other hand, as the materials of the heat-resistant metal layer 34 and the intermediate metal layer 36 are Mo, it is possible to etch a laminate of Mo/Al/Mo (three layers) at a time by using a solution of phosphoric acid and nitric acid. Thus, the cost of production equipment can be reduced, and obviously the production cost of the source/drain wires can be reduced.
As the contact formation process for the drain electrode 21 and the scan lines 11 is done simultaneously in the four-mask process as described above, the insulating layers corresponding openings 62 and 63 are different in thickness and type. Compared to the gate insulating layer 30, the passivation insulating layer 37 has a lower temperature of film-depositing and inferior film quality. Thus, the etching speeds of the insulating layers corresponding openings 62 and 63 are several 1000 A/minute and several 100 A/minute, respectively, and a 1-digit difference in the etching speed is generated. Considering that an excessive etching occurs on the upper part of the cross section at the openings 62 on the drain electrodes 21 causes difficulty in regulating the aperture diameters of the openings, fluorinated gas-based dry etching process is preferred.
However, after the dry etching method, the opening 62 on drain electrodes 21 only has the passivation insulating layer 37 therein. Compared to the opening 63 on the scan line 11, it is impossible to avoid excessive etching occurring at the openings 62. As a result, film of the intermediate inductive layer 36A may be reduced due to the etching gas, depending on the material used for the layer. Furthermore, when removing the photosensitive resin patterns after etching, it is usually done by eliminating approximately 0.1-0.3 μm of the photosensitive resin pattern surface by oxygen plasma ashing in order to remove polymers from the fluorinated surface, and this is then followed by applying chemical treatment, e.g. using an organic stripping solution such as Tokyo Ohka Kogyo's stripping solution 106. However, when the film of the intermediate conductive layer 36A is reduced to expose the aluminum layer 35A thereunder, an insulator Al203 is formed on the surface of the aluminum layer 35A by oxygen plasma ashing treatment, and therefore, no ohmic contact occurring between the drain electrode 36B and the pixel electrode 22 is not unusual.
Thus, there is an attempt to avoid this problem by setting up the film 0.2 μm in thickness in order to allow the reduced film thickness of the intermediate inductive layer 36A. Another way to avoid this problem is to remove the aluminum layer 35B to expose the Ti thin layer 34B functioning as the heat-resistant metal layer, and form the pixel electrode 22 when forming openings 62-65. In this case, there is a merit in not having to have an intermediate conductive layer 36 from the beginning.
However, the ways described above do not always work as effectively as expected if the thin film's homogeneity, or the etching speed's homogeneity within the surface is not good. Besides, although the latter way described above does not require the intermediate inductive layer 36B, it needs the process of removing the aluminum layer 35B and difficulty exists in controlling the correction shape of the opening 62. Thus, a possibility of pixel electrode 22 being cut off may occur.
Furthermore, in the 4-mask process, the channel-forming process is achieved by removing the source/drain wire materials and the semiconductor layer containing impurities between the source wire 12 and the drain wire 21. Therefore, the channel-forming process determines the channel length (4-6 μm in contemporary mass produced goods), which largely affects the On-state properties of insulating gate type transistors. The channel length fluctuation has significant effects on the On-state current of insulating gate type transistors. Accordingly, the requirements of fabricating management of the channel length are strict. The pattern dimension of the halftone exposure area is affected by many parameters such as exposure value (light source intensity and photomask pattern precision, especially line and space dimensions), coat thickness of the photosensitive resin, treatment conditions of photosensitive resin development, and the film reduction volume of the photosensitive resin in the etching process. The channel length is not always stable nor high-yielding due to the homogeneity of the parameters within the surface. As a result, fabricating management even stricter than before is needed. In other words, such management has not reached the optimum high-level yet. Accompanying the reduced thickness of the photosensitive resin pattern 80A(12) and 80A(21), the tendency is clearer especially when the channel length is 6 μm or below.
Increasing the size of the photomask is the easy way to avoid lessening the pattern size that corresponds to the reduced thickness of the photosensitive resin. However, the gap between the photosensitive resin 80C(12) and 80C(21) in the channel-region cannot be smaller than the resolution (at least 3 μm) of the exposure equipment. Hence, the channel length increases to two times of the reduced amount of the film of the photosensitive resin pattern in the horizontal direction. Besides, the reduced amount of the film of the photosensitive resin pattern in the glass substrate has great variation. Accordingly, the four-mask process cannot be introduced to the production line, in which the glass substrate has a dimension of more than 1 m, at present
Taking these situations into consideration, the present invention is provided to simplify the structure of the data line 12 without strict pattern accuracy management, to rationalize the process of forming the pixel electrode, and to reduce the manufacturing processes.
[Patent document 1] Japanese Unexamined Patent Application Publication H7-74368.
[Patent document 2] Japanese Unexamined Patent Application Publication 2004-317685.
[Patent document 3] Japanese Unexamined Patent Application Publication 2005-17669.
[Patent document 4] Japanese Unexamined Patent Application Publication 2005-19664.
[Non-patent document 1] November 2002 issue of the monthly publication of “Polymer Processing”.
USPTO Backgrounds
USPTO Backgrounds