1. Field of the Invention
The present invention relates to the field of electronic digital computer systems and in particular to a generator of a multiple phase clocking signal that is comprised of high frequency, uniformally spaced, uniformally shaped, pulses that are utilized for timing and synchronizing the operation of a computer system.
2. Description of the Prior Art
In a computer system that is comprised of synchronous electronic digital data processing equipment, it is known to use an oscillator circuit as the source of control and clock signals that time and synchronize the computer system's operation. It is also known to use shaping or pulse generating circuitry to shape the clock signal for the desired rise and fall time and amplitude. In addition to shaping the clock signal, it is also known to utilize phase generating circuitry to develop, from the clock signal, signals that represent a multiphase clock phase signal. For example, a clock signal of a frequency F may be utilized to generate, by phase generating circuitry, a multiphase clock signal of frequency F/N where the pulses of the clock phase signal have a predetermined interrelationship of time of occurrence.
In addition to the time relationship between the occurrence of the pulses of the clock phase signal, it is common for the pulses of the clock phase signal to be of similar signal shape with regard to rise time, fall time and amplitude. The clock phase signals are utilized through their known shape and time relationships to time sequences of computer system operation. If the clock phase signal generating circuitry fails to maintain the predetermined time relationship, a so-called clock skew results, and if this skew is too great, the computer system will generate error signals that stop computer system operation.
For clock signal timing of digital data processing equipment, clocking rate requirements are a function of the switching speed of the circuitry incorporated in the equipment. While early vacuum tube circuitry required clocking rate capability in the range of hundreds of kilohertz (KHz), discrete semiconductor circuits have required clocking rates that are orders of magnitude faster, while very large scale integrated (VLSI) circuitry have required clocking rates that are orders of magnitude greater than discrete semiconductor circuits. As clock rates increase, tolerances within the clock phase signal are necessarily diminished, and clock skew becomes an ever increasing problem.
Multiphase clock signal generating circuitry requires a driving clock signal that has symmetrical pulse shape and spacing, which clock signal is characteristically desired to have a 50 percent duty cycle. The precision of the duty cycle of the clock signal is especially critical in computer systems that utilize level sensitive circuitry. It is even more critical when both the positive and negative levels are utilized to control the logic circuitry. At relatively low frequencies of the clock source signal, a straightforward approach for providing the desired symmetrical clock signal is to drive a flip-flop circuit with the clock source signal in a manner such that there is an equivalent division by two for deriving the output clock signal frequency. It is of course apparent that the frequency of the clock source signal must be double that of the desired clock signal for such an approach to be feasible.
As clock signal frequencies increase, for example at 25 megahertz (MHz) and above, several design limitations arise in applying the flip-flop divider circuit. A major problem is that a flip-flop circuit will not exhibit the precisely same switching rates for driving an output terminal to achieve a rising edge as it will to drive the output terminal in the opposite direction to achieve a falling edge. At high clocking rates these differences in circuit switching rates result in an output clock signal waveform that does not exhibit the characteristic of a 50 percent duty cycle with an acceptable tolerance, and, accordingly, provides an unsatisfactory operation of the controlled circuitry. It has been found that by a careful selection of components, flip-flop dividers may work adequately, but would not be self-adjusting, would be relatively expensive, and would not yield an operation of a fixed pulse width, plus or minus 1 nanosecond (ns) which is nominally 50% duty cycle at normal operating frequency. A further drawback is that to obtain symmetrical clocking signals using this flip-flop technique it requires clock source signal frequencies double the desired output frequency. If the clock source signal circuitry is to be fabricated utilizing the same circuit technology as does the logic circuitry that is to be gated, the flip-flop divider approach is unworkable at higher frequencies.
Further, in many computer systems it is essential that upon power-on, or start-up, of the computer system or of its various components, or as by a Master Clear signal being coupled thereto, a multiphase clock signal always starts or begins with the first phase .0.1 pulse without the generation of runt or distorted signals. The clock generating circuitry of the present invention ensures that the multiphase clock signal always starts with the first phase .0.1 pulse while using the same semiconductor technology and requiring no adjustments of timing or of pulse shape. It is particularly adapted for high volume production of high speed, low to medium scale, computer systems, such as personal computers, while operating at a frequency that is near the speed limit of the logic family that is incorporated in the associated computer system.
USPTO Backgrounds
USPTO Backgrounds