A dynamic random access memory (DRAM), which is a typical semiconductor memory device, stores information by charges accumulated in cell capacitors, and, therefore, the information is lost unless refresh operations are periodically carried out. Therefore, refresh commands indicating refresh operations are periodically issued from a control device, which controls a DRAM. The refresh commands are issued from the control device at a frequency that all the word lines are certainly refreshed one time in the period of 1 refresh cycle (for example, 64 msec). Refresh starvation may occur when a controller violates a specification or standard in supplying refresh commands, making data stored at the DRAM vulnerable to unauthorized access.
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