1. Field of the Invention
The present invention relates generally to the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods of evaluating equipment defects for qualifying process tools used in the manufacture of integrated circuit dies on semiconductor wafers.
2. Description of Related Art
In previous methods used for qualifying process tools used in the manufacture of integrated circuit dies, equipment defects are evaluated by counting the number of defective dies on a wafer, transferring the wafer to a process tool, processing the wafer in the process tool, returning the wafer from the process tool, counting the number of defects on the wafer again, and subtracting the first defect count from the second to obtain the number of defects that were added to the wafer by the process tool. If more than a predetermined number of defects, or “adders”, were added to a wafer during the qualification check, then the process tool fails the qualification check. An investigation into the cause of the performance is then conducted to find a repair solution. When the process tool has been repaired, the qualification test is repeated, and so on, until the process tool passes the qualification test. At that point, production runs may be made with minimum loss in yield due to the process tool performance. Disadvantageously, identifying the cause of a problem in the process tool performance may require a large amount of time, which translates into higher production costs.
USPTO Backgrounds
USPTO Backgrounds