The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Advanced silicon manufacturing processes are allowing an ever increasing number of gates to be included in a given area of a SoC. Certain bus (or fabric) architectures have been introduced to allow for transfer of information (e.g., data, commands, parameters, addresses, etc.) between processor modules and interface control modules within a SoC. For example, an advanced microcontroller bus architecture (AMBA) is an on-chip interconnect specification for connection and management of modules in SoCs. One interface generation of AMBA is referred to as an advanced extensible interface (AXI).
A SoC having an AXI-based architecture may include multiple processor (or core) modules, a master AXI interconnection bus (or master fabric), a slave AXI interconnection bus (or slave fabric), and interface controllers. The processor modules control and/or access peripherals connected to the interface controllers via the interconnection buses. The AXI interconnection buses may be referred to as multi-level AXI fabrics and provide a mesh of interconnections between the processor modules and the interface controllers. The interface controllers may be connected respectively to peripheral devices and/or networks. The peripheral devices may include memory devices, such as a random access memory (RAM) or a read only memory (ROM). The peripheral devices may include a display, a flash drive, a hard disk drive, a hybrid drive, a camera, an embedded multi-media card (eMMC), an Ethernet device, a serial small computer system interface (SCSI) protocol (SSP) device, a device communicating via a universal asynchronous receiver transmitter (UART) interface, etc. The networks may include wireless or wired networks. An example of a wireless network is a wireless local area network (WLAN) such as a WiFi network.
The processor modules may be referred to as bus masters. The processor modules control and initiate operations of peripherals connected to the SoC. This may include the processor modules (or masters) transmitting commands to the interface controllers via the master AXI interconnection bus. Each of the interface controllers includes a master port (or interface) and a slave port (or interface). The master ports are connected to the master AXI interconnection bus. The slave ports are connected to the slave AXI interconnection bus. Commands may be transmitted to the master ports and then forwarded to the peripheral devices. Data may then be received from the peripheral devices at the slave ports. The slave AXI interconnection bus forwards the data from the slave ports to the processor modules.
In a SoC having an AXI architecture, each connection between the processor modules and the interface controllers includes multiple channels. The channels include a read address channel, a read data channel, a write address channel, a write data channel, a buffer write response channel, and a clock channel. These connections are provided via AXI bus interfaces of the processor modules and interface controllers. AXI bus interfaces may exist (i) between the processor modules and the AXI interconnection buses, and (ii) between the AXI connection buses and the interface control modules. The AXI bus interfaces and the AXI interconnection buses include a large number of wires. For example, write channels of an AXI bus interface may include as many as 224 wires for a parallel transfer of 128 bits. Read channels of an AXI bus interface may include as many as 208 wires for a parallel transfer of 128 bits. The slave AXI interconnection bus may include 200 wires for a parallel transfer of 32 bits. A 10-port AXI interconnection bus may include 5000 wires for a parallel transfer of 128 bits per port. S another example, a 10-port AXI interconnection bus may include 3000 wires for a parallel transfer of 32 bits per port. Additional wires are also required for transfer of interrupts. The AXI interconnection buses are large mesh networks of interconnections with limited data transfer speeds (e.g., 312 mega-hertz (MHz) or slower). Point-to-point transfer speeds between adjacent nodes in the mesh networks is also limited (e.g., 416 MHz) or slower.
The modules in a SoC with an AXI architecture operate based on a commonly shared clock. A clock signal is provided via a large clock tree of branches (or interconnections) in the AXI interconnection buses. As a result, communication between the modules is synchronous. If two of the modules are to operate based on different protocols (e.g., different AMBA protocols such as AXI and AMBA high-performance bus (AHB)) and/or different clocks (or clock signals having different frequencies), then a bridge is typically incorporated between the modules. The bridge allows for communication between two different domains having, for example, different bus widths (e.g., number of parallel transferred bits) and clock frequencies. Although integrators can be incorporated in the SoC to assure proper bandwidth and latency for the connections between the modules, allocation of bandwidth and control of access latency for each of the modules is difficult. This is because of the larger number of wires and interconnections between the modules and the distribution of the shared clock signal over the large mesh network.
It can be difficult to set the frequency of the clock signal to provide proper clock tree derating. Proper clock tree derating refers to setting the frequency of the clock signal to a highest frequency possible without negatively affecting operation and/or lifetime of a corresponding SoC. Increasing the frequency of the clock signal can increase process, voltage, and temperature (PVT) variations of the SoC. As a result, ability to increase the frequency of the clock can be limited due to the potential of increased PVT variations. The larger the clock tree, the slower the frequency of the clock signal.
USPTO Backgrounds
USPTO Backgrounds