Optimization of memory bandwidth, power efficiency and form factor are becoming increasingly important as memory causes significant bottlenecks to future microprocessor systems. It is common for most CPU systems to utilize a dynamic random access memory (DRAM) based bulk memory solution to provide capacity and bandwidth. However, DRAM process technology is primarily optimized for capacity and cost to the sacrifice of both bandwidth and power efficiency. On the other hand, logic process technology conventionally used for CPUs are optimized for logic density, power efficiency and bandwidth with the drawback being higher cost and lower memory density.
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