1. Field
This disclosure relates generally to integrated circuits, and more specifically, to an integrated circuit having an embedded memory and method for testing the memory.
2. Related Art
One of the most common ways to reduce power consumption in integrated circuits is to lower the power supply voltage. However, lowering the power supply voltage can cause increased failures and unreliable operation in some circuits. For example, the lowest power supply voltage (VMIN) on which a SoC (system-on-a-chip) can operate is often limited by the memory arrays embedded on the SoC. The embedded memories typically require a large built-in speed/reliability guard band margin to cover device mismatches. Device mismatches may be caused by, for example, random dopant fluctuations, negative bias temperature instability, and hot carrier injection. The problem is made worse as transistor sizes are decreased.
Therefore, what is needed is an integrated circuit and method for solving the above problems.
USPTO Backgrounds
USPTO Backgrounds