With development of semiconductor technology, various types of problems are being generated. With microminiaturization of semiconductor devices, the requirements for the electrical properties of semiconductor devices are increasingly exacting, and new processes or design changes are required.
As semiconductor devices are downsized, one of the problems most notably appearing may be RC delay when an external electrical signal is transmitted to a transistor. The RC delay characteristics may be naturally generated during a process of manufacturing the semiconductor devices and as an example thereof, parasitic resistance or parasitic capacitance may be used. Parasitic resistance and parasitic capacitance are often inevitably generated in a semiconductor device using oxide and metal. Therefore, research for reducing parasitic resistance and parasitic capacitance is ongoing.
For example, as methods for solving the problem, a wiring process using copper (Cu) and processes using an ultra low-k material are being proposed. However, since the materials also have parasitic resistance and parasitic capacitance, they do not constitute a permanent solution.
FIG. 1 is a diagram for describing RC delay in a semiconductor device. Referring to FIG. 1, a plurality of metal wires 11, 12, and 13 are formed on a predetermined layer and an IMD as an interlayer dielectric layer is formed between the metal wires.
In this case, during transmission of an electrical signal in the semiconductor device, the metal wires 11, 12, and 13 each show resistance characteristics, and the IMD shows capacitance characteristics. Accordingly, since resistance and capacitance are connected, the problem of a delayed transmission of the electrical signal persists.
USPTO Backgrounds
USPTO Backgrounds