1. FIELD OF THE INVENTION
This invention relates to a method for producing semiconductor devices and, more specifically, to a method for reducing the extrinsic base-collector capacitance of such semiconductor devices.
2. BRIEF DESCRIPTION OF THE PRIOR ART
Bipolar transistors as known in the art have an extrinsic base region which contacts an intrinsic base region. The extrinsic base region in NPN transistors is a P+ doped contact which enables contact to the intrinsically doped base of the transistor. When the P+ region is implanted and diffused into the substrate of the transistor structure, the substrate normally being an N-type epitaxial layer, a capacitance associated with the junction formed which is known as a parasitic capacitance is present, this parasitic capacitance being an undesirable but necessary evil in such prior art devices. It is desired to construct a bipolar transistor which will minimize this parasitic capacitance and yet form the required P+ contact to the P-type base region.
USPTO Backgrounds
USPTO Backgrounds