The present invention relates to output circuits in semiconductor integrated circuits.
JP H4-145717A discloses an output circuit including a driver circuit of CMOS configuration. In order to obtain a large current driving capability, this driver circuit includes a plurality of N-channel output transistors that are connected in parallel to one another and a plurality of P-channel output transistors that are connected also in parallel to one another. The times when a peak current flows through the output transistors are offset by controlling the gate voltages of the output transistors with a delay circuit such that the N-channel output transistors do not change the off-state simultaneously to the on-state, and such that the P-channel output transistors do not change the off-state simultaneously to the on-state, thereby suppressing noise at the time of data output. However, since analog means are used for the conduction timing adjustment of the output transistors, it is not possible to accommodate design changes smoothly, and furthermore the effect of noise suppression depends on the manufacturing process.
In order to address these problems, the output circuit in JP H9-232930A uses a digital circuit (made of a shift register and a multiplexer) receiving a single clock signal of variable period to adjust the conduction timing of the output transistors in a CMOS driver circuit similar to the one mentioned above.
Now, if a small-amplitude high-speed interface of, for example, SSTL (stub series terminated logic) or HSTL (high speed transceiver logic) is included in an LSI circuit, then the drain terminals of all output transistors in a CMOS driver circuit like the one described above are internally connected to a common output pad, the source terminals of the N-channel output transistors are internally connected to a common ground voltage VSSQ and the source terminals of the P-channel output transistors are internally connected to a common power source voltage VDDQ, and the output pad is connected via a terminating resistance outside the LSI circuit to a terminating voltage VTT. Ordinarily, VTT is set such that
VTT=(VDDQ+VSSQ)/2 
is fulfilled. Therefore, in addition to a charge/discharge current at the time of data transition that is specific to the CMOS driver circuit, a stationary output current flows between VTT and VSSQ when the N-channel output transistors become conducting and the output pad indicates a LOW voltage, and a stationary output current flows between VDDQ and VTT when the P-channel output transistors become conducting and the output pad indicates a HIGH voltage. The current driving capability of the output transistors fluctuates due to variations in the manufacturing process, or in response to changes in the power source voltage or in the temperature, so that also the output current of the driver circuit fluctuates.
Usually, the size of the output transistors is designed so as to satisfy certain specifications, such as the output current, under worst-case conditions with regard to the manufacturing process and power source voltage and temperature, that is, the conditions at which the output transistors have the lowest current driving capability. Consequently, conventionally, under the best-case conditions, under which the output transistors have the highest current driving capability, the output current of the driver circuit may become excessive, and may even reach twice the output current for the worst-case conditions. This, however, leads to an increase in power consumption of the LSI circuit.
It is thus an object of the present invention to make it possible to obtain from a driver circuit a substantially constant output current, even when there are variations in the manufacturing process or fluctuations in the power source voltage or the temperature.
In order to achieve this object, an output circuit in accordance with the present invention includes a driver circuit having a plurality of output transistors that are connected to one another in parallel, and a control circuit controlling this driver circuit such that when a given data signal indicates a predetermined logic level, at least one of the plurality of output transistors becomes conducting, wherein the control circuit comprises a delay circuit with a variable delay time that reflects a change of a current driving capability of the plurality of output transistors, wherein, when it is detected from a change of the delay time that the current driving capability of the individual output transistors has decreased, then the number of the output transistors that become conducting is increased, and wherein, when it is detected from a change of the delay time that the current driving capability of the individual output transistors has increased, then the number of the output transistors that become conducting is decreased.
In accordance with the present invention, it is possible to generate a delay fluctuation signal having a variable phase difference reflecting the delay time to, for example, a reference clock signal, by using a delay circuit having a variable delay time that reflects changes in the current driving capability of the output transistors. Then, by determining the phase relation between multi-phase signals each having a different phase difference with respect to the reference clock signal and the generated delay fluctuation signal, it is possible to detect changes in the current driving capability of the output transistors from that relation.
USPTO Backgrounds
USPTO Backgrounds