The present invention relates generally to lithography in very large scale integrated (VLSI) chip manufacturing, and more particularly to an improved phase shifted mask (PSM) lithography.
In recent years, demands to increase the number of transistors on a wafer have required decreasing the size of the features, but this has introduced diffraction effects, which have posed limitations on the desired feature size. Lithography in the context of VLSI manufacturing is the process of patterning openings in photosensitive polymers, commonly referred to as photoresists, which define small areas in which the silicon base material is modified by a specific operation in a sequence of processing steps. Conventionally, photoresist chemistry is optimized to discriminate between the brighter and darker intensities.
Phase-shift lithography was developed to enhance the range of conventional optical photolithography. Phase-shift lithography is based on opposite phase destructive interference of the waves of incident light. By shifting the phase of one region of incident light wave approximately 180° relative to an adjacent region of incident light waves, a sharply defined dark zone is created beneath the phase-shift mask due to destructive interferences of the waves. This zone defines the interface between light and dark regions, and hence defines the boundary between exposed and unexposed portions of the resist layer underlying the phase-shift mask. Having a portion of incident light traverse through a longer distance, or conversely, traverse through a shorter distance, typically generates interference phase shifting. The distance differences that the incident light traverses establishes a comparative phase shift. The longer distance may be established by introducing an extra deposited layer through which the light must travel. The shorter distance may be achieved by virtue of an etched groove. Phase-shifting masks are now well known in the art, and there are many varieties that have been employed.
The resolution, R, of a lithography tool is defined by the equation:R=κ1λ//NA
where,
λ is a wavelength of the electromagnetic radiation used in the exposure;
NA is a numerical aperture of the optical system; and
κ1 is an Aries factor, which relates to the limit of diffraction.
Phase shifted mask lithography improves the lithographic process latitude, allowing the operation of a lower Aries factor or κ1 value. Specifically, the electric field vector of the incident light, having magnitude and direction, can be made to constructively interfere with a 0° phase change or with an 180° phase change. For example, light traveling through a thicker portion of material of a predetermined thickness and index of refraction can be made 180° out of phase with incident light not traversing through the thicker material. The electric field vectors of this out-of-phase light will be of equal magnitude but in opposite directions, so that any interaction between these vectors will result in cancellation (destructive interference).
Conversely, light that is in phase will constructively interfere. The thickness of the masking layer is chosen to achieve the desired opacity. Thus, a binary nature of the image is projected, represent by areas of high intensity and areas of low or zero intensity. However, a perfectly square step function is only a theoretical limit.
Diffraction effects will cause images to occur at the edge. These images, in turn, will cause artifacts upon exposure. Trim masks are generally used to remove the artifacts created by the phase shifting mask. A trim mask is a second mask that transmits light, in part, in regions left unexposed by the residual phase edge.
The limits of phase shifted mask lithography are tested by the manufacture of high performance integrated circuits, such as dynamic random access memory (DRAM) technologies. Phase edge PSM lithography makes use of contrast enhancement caused by a phase transition under an opaque feature on a mask.
Phase shift mask solutions are used in lithography to enable printing of very small feature sizes in semiconductors that cannot be realized with conventional techniques. They represent a key technology enabling further shrinking of feature sizes. However, alternating phase shift masks have implications regarding layout rules, such as those relating to line end shortening, which can result in a significant layout area impact and further increase layout rule complexity. Due to the required phase shift technologic rules, some of the prior art design rules must change to accommodate the additional layers introduced in the design by alternate phase shifting methods.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a methodology to incorporate phase mask shapes having a minimum impact on the current design rules.
It is another object of the present invention to provide phase mask shapes that can eliminate line-end shortening without influencing conventional design styles.
A further object of the invention is to provide a methodology to reduce the space for critical shapes beyond a reference or feature layer.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
USPTO Backgrounds
USPTO Backgrounds