Some processes include the formation of polysilicon filled dielectric lined trenches. For example, polysilicon filled dielectric lined trenches can be used for dielectric isolation (e.g., shallow trench isolation (STI)), for making capacitors, or for making both. Some of these trenches are deep trenches, typically formed by reactive ion etching (RIE), which can be 10 μm to 50 μm deep, or more. Several of these processes add a polysilicon gate for metal-oxide-semiconductor field-effect transistor (MOSFET) devices and/or other polysilicon filled trenches, so that there are two levels of polysilicon trench filling.
For example, certain MOSFETs have a gate structure including polysilicon gate electrodes and a vertical drain drift region between RESURF trenches which are polysilicon filled regions. For the purposes of this application, the term “RESURF” is understood to refer to a material which reduces an electric field in an adjacent semiconductor region. A RESURF region may be for example a semiconductor region with an opposite conductivity type from the adjacent semiconductor region. RESURF structures are described in Appels, et. al., “Thin Layer High Voltage Devices” Philips J, Res. 35 1-13, 1980.
There can be active area RESURF trenches (hereafter “active area trenches”) which contain field plates which are electrically coupled to a source of the MOSFET. In the case of a n-channel MOSFET, there is a p-body region within an n-drift region on a substrate, where n-type dopants are in the source regions formed in the p-body region. The drain for the MOSFET can be a vertical drain drift region that uses the entire n-drift region below the p-body region, that has a drain contact on the bottom of the substrate which can be an n+ substrate.
A contact metal stack makes electrical contact with the source regions at lateral sides of the contact structure, makes electrical contact with a body contact region at a bottom surface of the contact structure, and makes electrical contact to the field plates in the active area trenches at the bottom surface of the contact structure. A perimeter RESURF trench (hereafter a “termination trench”) surrounds the MOSFET, including the active area trenches. The termination trench is formed at a first polysilicon level and the active area trenches include formation steps including a second polysilicon level, creating the need to remove the second polysilicon layer from over the termination trench.
USPTO Backgrounds
USPTO Backgrounds