1. Field of the Invention
The present invention relates to semiconductor structures, and, more particularly, to a conductive bump structure and a method of fabricating a stack-typed semiconductor structure.
2. Description of Related Art
Referring to FIG. 1A, in a conventional flip-chip packaging process, a semiconductor chip 1 having a plurality of bonding pads 110 and a packaging substrate 12 having a plurality of conductive pads 120 are provided. A solder material (not shown) is formed on each of the bonding pads 110 and a pre-solder material (not shown) is formed on each of the conductive pads 120. The solder material is aligned with the pre-solder material and reflowed to form solder bumps 10. Thereafter, an underfill 13 is formed between the semiconductor chip 11 and the packaging substrate 12 to encapsulate the solder bumps 10, thereby forming a flip-chip semiconductor package 1. The use of the solder bumps 10 leads to short electrical conductive paths, improves electrical performance, facilitates heat dissipation and results in a small package size, and is becoming more and more popular.
However, when the solder material is reflowed, it is difficult to control the average value and deviation of the volume and height of the solder bumps 10. Further, the collapse range of the solder bumps 10 needs to be accurately controlled. If the collapse range of the solder bumps 10 is wide, a solder bridge can easily occur between two adjacent solder bumps 10 so as to result in a short circuit. In addition, if the average value and deviation of the volume and height of the solder bumps 10 are large, the solder bumps 10 arranged in a grid array can have poor coplanarity, thus resulting in product failure and low reliability. As such, the semiconductor chip 11 cannot meet the fine-pitch requirement.
Accordingly, a flip-chip bump technology is provided. Referring to FIG. 1B, an under bump metallurgy (UBM) layer 101 and a copper post 100 are sequentially formed on each of the bonding pads 110 of a semiconductor chip 11′, and a solder material 102 is further formed on the copper post 100. Since the shape of the copper post dose not change in a reflow process, the height and volume of the bumps can be easily controlled so as for the semiconductor chip 1 to meet the fine-pitch requirement.
Further, along with miniaturization of electronic products, I/O pitches are continuously decreased and more and more chips and functions are integrated in a given area. Consequently, 3D stack technologies are developed.
Generally, in flip-chip process, the bumps which have the copper posts 100, a thermal compression bonding (TCB) process is performed such that the solder material 102 on the copper posts 100 and pre-solder material (not shown) are reflowed to form bumps 10′. Therefore, an ultra high compression force and an ultra high temperature are required in the TCB process.
Further, smaller size of electronic elements (such as the semiconductor chip 11′) are more significantly affected by RC delays. When RC delays increase, cross talks and capacitive couplings occurring between circuits will seriously adversely affect the speed and quality of signal transmissions. Therefore, low-k materials are used to avoid RC delays.
However, since a low-k material is hard and crisp, when used as the semiconductor chip 11′, the low-k material is easy to crack during the conventional TCB process due to the ultra high compression force and high temperature.
Therefore, how to overcome the above-described drawbacks has become critical.
USPTO Backgrounds
USPTO Backgrounds