1. Field of the Invention
The present invention relates to a method for forming a through-silicon via (TSV) in a through hole of a silicon substrate in a 3D integration technique, and more specifically relates to a technique of filling an internal space of a through hole of a small diameter provided in a silicon substrate with molten solder. The present invention also relates to an interlayer connection technique whereby a plurality of silicon substrates are stacked and joined to each other.
2. Description of Related Art
A through-silicon via (TSV) technique is one of the 3D integration techniques. An optimal fabrication method and material need to be selected for the TSV, according to specifications, architecture, silicon (substrate) thickness, and overall fabrication process of a product that requires this integration technique. A “through hole” filled with a conductive material becomes wiring that functions as a conductive path after the filling, and is also referred to as a “via”.
In a commonly known TSV fabrication method, a TSV is fabricated in a sequence of (1) etching silicon (substrate) to form a through hole in the silicon substrate, (2) forming an insulation film on an internal surface of the through hole, and (3) filling a remaining internal space of the through hole with a conductive material.
As a conventional technique for (3) in this sequence of the fabrication method, a process of filling with the conductive material (e.g. Cu) by plating is known. However, not only this process requires dedicated plating equipment, but also depositing the metal on the surface by plating takes time. Hence, this process has low yields.
FIG. 6 shows an example of a plating process in the conventional technique
FIG. 6(a) shows an example of plating equipment in the conventional technique. An object to be plated is placed at a position of a sample between a cathode and an anode. A plating solution contains ions of metal for plating.
FIG. 6(b) shows a situation where a void occurs in the through hole of the silicon substrate in the conventional technique. When there is such a portion that is not filled with the conductive material, the function as the conductive path cannot be sufficiently achieved. Even though the TSV conducts immediately after fabrication, there is a possibility that a conduction failure occurs as a result of deterioration with age. Thus, the conventional technique lacks reliability.
FIG. 6(c) shows a situation where the plating is not deposited (not distributed) throughout the internal space of the through hole. This is probably because, in the plating process, the metal ions contained in the solution are grown and deposited with time, and so there is a tendency that the metal deposits near an entrance between the internal space and an external space of the through hole before it reaches the internal space. In the experimental example shown in FIG. 6(c), a diameter of the through hole is φ=50 μm, and a depth of the through hole (a thickness of the silicon substrate) is t=400 μm. Under conditions of smaller scales than this, a further technique is needed to prevent such a situation.
Patent Document 1 discloses a technique of small metal particles having a nanocomposite structure. Such a technique can be applied to distribute metal particles of a small diameter throughout a through hole of a small diameter to thereby form a TSV. However, even if the metal particles can be supplied in a closest packing manner, still it does not mean that the metal particles are supplied as a gap-free continuous body. Therefore, perfect filling cannot be ensured. FIG. 7 is a diagram for describing such a conventional technique that uses small metal particles.
Patent Document 2 discloses a technique whereby, for an insulation substrate made of a thermoplastic resin, a semi-molten metal mixture is formed by mixing a binder resin in metal particles, to improve interlayer connection reliability of a multilayer substrate. However, required specifications and architecture are different between the insulation substrate and the silicon substrate, and the diameter of the through hole relating to the present invention is of a much smaller order than the diameter of the via hole (through hole) in Patent Document 2.
Although the binder resin is mixed in expectation of its gap reduction effect, the use of the binder resin causes generation of gas during melting and so rather raises a possibility of a void occurrence.
USPTO Backgrounds
USPTO Backgrounds