The fabrication of a semiconductor device involves a plurality of discrete and complex processes. One such process is a lithography process, where a substance, such as a photoresist, is applied to a surface of the workpiece. Subsequently, the photoresist is exposed to a pattern of light or other electromagnetic energy. In some embodiments, a mask is disposed between a light source and the workpiece. The exposure to light causes a chemical change that allows some of the photoresist to be removed by a special solution, referred to as a developer. Positive photoresist, the most common type, becomes soluble in the developer when exposed; with negative photoresist, unexposed regions are soluble in the developer. In either case, the remaining photoresist serves as a pattern for subsequent processes, such as etch processes.
The dimension of a feature in a photoresist pattern may be referred to as a critical dimension, also referred to as CD. For example, assume a pattern of lines, where each line of photoresist is surrounded by abutting regions, or spaces, where the photoresist has been removed. The width of a line is referred to as the critical dimension of the photoresist. Further, the distance between a given edge of two adjacent lines of photoresist, which is the width of the line plus the width of the space, may be referred to as the pitch.
Transistor performance is sensitive to the critical dimension of various device components, such as gate length, fin width (in the case of finFETs), shallows trench isolation size, contact dimension, metal line width and others. A critical dimension may be defined as the dimension of a feature whose size affects device performance. Variation of this critical dimension across a workpiece is problematic because the device will not operate as designed if the critical dimension of these features is not within design specifications. CD variation may be caused by many factors, such as etch non-uniformity, material non-uniformity, and workpiece topology. As semiconductor manufacturing technology advances, lithography and other processes are pushed close to the capability limits, it becomes increasingly difficult to reduce the variation in the critical dimension. For example, for lithography patterns having a CD of less than 30 nm, variability of 1-2 nm may be significant.
Therefore, it would be beneficial if there were a method of controlling the variability of the critical dimension in a lithography process. Further, it would be beneficial if this method improved the variability of the critical dimension of etched features on the workpiece.
USPTO Backgrounds
USPTO Backgrounds