The present invention relates to jitter measuring devices and more specifically to an improved device and method of measuring jitter of a clock signal.
When a reference signal is modulated by a second signal, such as noise, zero crossing of the reference signal is changed backward and forward. This change of phase is defined as jitter. In many applications which involve clock recovery, it is desirable to measure the amount of jitter. The prior art jitter measuring device Hewlett-Packard HP-3785B, for example, uses analog circuits and has an accuracy of 0.035UI.+-.4% for a jitter clock having a frequency of 1.544 mhz. Being an analog device, it is sensitive to temperature variations and aging. Also the range of jitter measurement is limited. The device also does not allow the adjustment of the phase between the jitter clock and the reference clock.
Thus, it is an object of the present invention to provide a jitter measurement device and method which is more accurate than the prior art devices.
It is another object of the present invention to provide a jitter measurement device and technique which is insensitive to temperature or aging.
A still further object of the present invention is to provide a jitter measurement device and method using a simplified circuit.
An even further object of the present invention is to provide a jitter measurement device and method having a variable range of jitter measurement.
A still even further object of the present invention is to provide a jitter measurement device and method which is capable of adjusting the phase between the jitter clock and the reference clock even to the point of centering.
These and other objects are achieved by applying a first clock signal to a device-under-test, measuring the phase difference between the jittered clock signal received from the device-under-test and a reference clock signal, and converting the phase difference to a jitter measurement. The phase difference is measured by counting the number of high frequency clock pulses between a transition of the jittered clock signal and a transition of the reference clock signal. The phase difference is converted to a jitter measurement by determining the highest and lowest phase difference count and taking the difference between the highest and lowest count. The phase of the reference clock signal can be adjusted as a function of the highest and lowest count by determining the mean value of the highest and lowest count and adjusting the reference clock to be of this mean value.
The range of the jitter measurement can be adjusted by adjusting the frequency of the high frequency reference clock signal to the counter, the jittered signal received from the device-under-test and the reference clock signal. The frequency of the reference clock is selected to be a harmonic of the first clock signal. This is produced by generating the jitter-free first clock signal and the reference clock signal from the high frequency clock signal, which clocks the counter, with appropriate dividers. This also provides for appropriate adjustment of the range.
The jitter measuring device would include a first clock for producing a jitter-free clock signal to be provided to the device-under-test, a second clock for producing a reference clock signal, a measuring circuit for measuring the phase difference between a jittered clock signal received from the device-under-test and the reference clock signal, and a conversion circuit for converting the phase difference to a jitter measurement. A counter is provided to count high frequency clock signals from a high frequency clock and the measurement circuit controls the start and stop of counting based on a transition of the jittered clock signal and the reference clock signal. The conversion circuit determines the highest and lowest count and uses the difference therebetween as the jitter measurement. A latch is provided at the output of the counter to latch the value of the counter. The conversion circuit includes a high latch and a low latch and comparator circuits for comparing the count latch value with the high and low latches and entering the lowest value between the low latch value and the counter latch value in the low latch and the highest value between the highest latch count and the latch counter count in the high latch. The difference between these two latches is the peak to peak jitter. The highest and lowest count value in the high and low latches are also used to determine the mean count value, which is used to adjust the phase of the reference clock. The phase is adjusted by converting the mean value into an adjustment value and delaying the transmission of signals from the high frequency count to the divider for the reference clock by a given count value. This produces the phase adjust.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds