1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and more particularly, to a method of fabricating a semiconductor device equipped with a polycide gate structure using titanium silicide (TiSi2).
2. Description of the Related Art
With semiconductor devices with Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), a polycide structure formed by the combination of a polysilicon film and a TiSi2 film has been usually used for gate electrodes and gate wiring lines because they need to be as low as possible in resistivity.
FIGS. 1A and 1B show a prior-art method of forming the polycide gate structure using TiSi2.
First, as shown in FIG. 1A, an isolation dielectric 112 is selectively formed on the surface of a silicon (Si) substrate 111, thereby defining active regions 113 thereon. Then, a thin gate oxide 114 is formed on the exposed areas of the substrate 111 in the active regions 113. A polysilicon film 115 is formed on the gate oxide 114 and the isolation dielectric 112.
Subsequently, using a sputtering apparatus, a titanium silicide (TiSi2) film 131 is formed on the polysilicon film 115 without heating the substrate 111 from its back side. Alternately, the TiSi2 film 131 is formed by a sputtering apparatus while the substrate 111 is held at a temperature of approximately 400xc2x0 C. to 600xc2x0 C. by a substrate holder with a heating function. The state at this stage is shown in FIG. 1A.
The TiSi2 film 131 formed by sputtering under the above-described condition is high in resistivity. Specifically, the film 131 formed without heating the substrate 111 from its back side is in the amorphous phase. On the other hand, the film 131 formed while the temperature of the substrate 111 is kept within the range of approximately 400xc2x0 C. to 600 xc2x0 C. is in the C-49 phase. It has been known that amorphous TiSi2 and C49-phase TiSi2 are high in resistivity.
To lower the resistivity of the TiSi2 film 131, the film 131 is typically subjected to a lamp annealing process, i.e., a Rapid Thermal Annealing (RTA) process, at approximately 800xc2x0 C., thereby transforming the amorphous or C-49 phase into the low-resistivity C-54 phase due to phase transition. Thus, as shown in FIG. 1B, a C-54 phase TiSi2 film 131a is formed on the polysilicon film 115. (This point has been disclosed in, for example, the Japanese Non-Examined Patent Publication No. 10-223561 published in 1998.)
As shown in FIG. 1B, the TiSi2 film 131a has depressions 131aa, which are formed to reflect the depressions of the isolation dielectric 112 located on its top face.
Furthermore, the polysilicon film 115 and the C-54 phase TiSi2 film 131a are patterned to have a specific shape, thereby forming gate electrodes (not shown) with the TiSi2 polycide structure.
With the prior-art method shown in FIGS. 1A and 1B, the volume of the amorphous or C-49 phase TiSi2 film 131 decreases during the phase transition to the C-54 phase from the amorphous or C-49 phase, resulting in tensile stress in the C-54 phase TiSi2 film 131a. As a result, as shown in FIG. 2, there arises a problem that cracks 132 tend to be formed in the film 131a at the bottom of the depressions 131aa. Due to existence of the cracks 132, the underlying polysilicon film 115 will be affected badly in subsequent process steps.
Moreover, the RTA process needs to be additionally performed to form the C-54 phase TiSi2 film 131a through phase transition after the process of forming the amorphous or C-49 phase TiSi2 film 131. Thus, there is another problem that the necessary time period to the fabrication sequence of the semiconductor device increases and its fabrication cost rises.
Accordingly, an object of the present invention is to provide a method of fabricating a semiconductor device equipped with a polycide gate structure that solves the above-identified problems in the prior-art method.
Another object of the present invention is to provide a method of fabricating a semiconductor device that makes it possible to form a polycide gate structure having a crack-free TiSi2 film.
Still another object of the present invention is to provide a method of fabricating a semiconductor device that eliminates the process to lower the resistivity of a TiSi2 film.
A further object of the present invention is to provide a method of fabricating a semiconductor device that lowers its fabrication cost.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A method of fabricating a semiconductor device according to a first aspect of the present invention comprises the steps of:
(a) providing a semiconductor substrate having an active region defined by an isolation dielectric;
(b) selectively forming a gate dielectric in the active region;
(c) forming a polysilicon film on the gate dielectric;
(d) forming a C-54 phase TiSi2 film on the polysilicon film while the substrate is kept at a temperature of approximately 750xc2x0 C. or higher; and
(e) patterning the polysilicon film and the C-54 phase TiSi2 film to form a gate electrode with a polycide structure.
With the method of fabricating a semiconductor device according to the first aspect of the present invention, the TiSi2 film with the low-resistivity C-54 phase is formed on the polysilicon film while the substrate is kept at a temperature of approximately 750xc2x0 C. or higher in the step (d). In other words, the C-54 phase TiSi2 film is directly formed without phase transition from the high-resistivity amorphous or C-49 phase. Thus, no volume shrinkage, which tends to occur during the phase transition, occurs in the TiSi2 film. As a result, the C-54 phase TiSi2 film contains no cracks, resulting in a polycide gate structure having a crack-free, low-resistivity TiSi2 film.
Also, since the TiSi2 film formed in the step (d) has the low-resistivity C-54 phase, the heat treatment process to cause the phase transition in the TiSi2 film (i.e., to lower the resistivity of the TiSi2 film) is unnecessary. In other words, the necessary time period to the fabrication sequence of the semiconductor device is shortened. Accordingly, the fabrication cost of the semiconductor device is lowered.
A method of fabricating a semiconductor device according to a second aspect of the present invention comprises the steps of:
(a) providing a semiconductor substrate having an active region defined by an isolation dielectric;
(b) selectively forming a gate dielectric in the active region;
(c) forming a polysilicon film on the gate dielectric;
(d) forming a barrier film on the polysilicon film;
(e) forming a C-54 phase TiSi2 film on the barrier film while the substrate is kept at a temperature of approximately 750xc2x0 C. or higher; and
(f) patterning the polysilicon film, the barrier film, and the C-54 phase TiSi2 film to form a gate electrode with a polycide structure.
With the method of fabricating a semiconductor device according to the second aspect of the present invention, because of the same reason as the method of the first aspect, the same advantages as those in the method of the first aspect are given.
In a preferred embodiment of the method according to the first or second aspect of the invention, in the step (d), the temperature of the substrate has a highest value of approximately 850xc2x0 C. In other words, the step (d) is performed while the substrate is kept at a temperature from approximately 750xc2x0 C. to approximately 850xc2x0 C. In this embodiment, there is an additional advantage that the possibility that TiSi2 grows to be like islands due to agglomeration in the step (d) can be eliminated.
In another preferred embodiment of the method according to the first or second aspect of the invention, the step (d) is carried out by sputtering, Chemical Vapor Deposition (CVD), or evaporation. In this embodiment, there is an additional advantage that the process for performing the step (d) can be selected according to the necessity.
USPTO Backgrounds
USPTO Backgrounds