1. Field of the Invention
Aspects of the present invention relate to a Flat panel display device and a method of manufacturing the same, and more particularly, an OLED display device having uniform electrical characteristics and a method of manufacturing the same.
2. Description of the Related Art
Flat panel display devices such as Liquid Crystal Display (LCD) devices, OLED display devices or Plasma Display Panels (PDPs) have recently attracted attention as such displays overcome disadvantages of conventional display devices, such as Cathode Ray Tubes (CRTs). Here, among the flat panel display devices, OLED display devices and LCD devices include a thin film transistor as a switching or driving device and a capacitor to store an external signal in connection with the thin film transistor and to provide the stored external signal until the next signal period.
FIG. 1A to 1E are cross-sectional views of a conventional OLED display device. First, referring to FIG. 1A, a buffer layer 110 is formed on a substrate 100, which is formed of plastic or glass, and an amorphous silicon layer is formed on the buffer layer 110, and the amorphous silicon layer is patterned to form a semiconductor layer 120 and a first capacitor electrode 125. Subsequently, an insulating layer 130 is formed on the substrate 100, i.e., the insulating layer 130 is formed to cover the patterned semiconductor layer 120, the first capacitor electrode 125, and the buffer layer 110.
Referring to FIG. 1B, a photoresist pattern 140 is formed in a region corresponding to the semiconductor layer 120. An impurity implantation process is performed using the photoresist pattern 140 as a mask, thereby defining source, drain, and channel regions, and implanting impurities into the first capacitor electrode 125.
Referring to FIG. 1C, the insulating layer 130 is etched to form an insulating layer pattern corresponding to the channel region of the semiconductor layer 120, and a metal catalyst layer 150 is formed on the substrate and then removed from regions other than the regions corresponding to the source and drain regions of the semiconductor layer 120 and the first electrode 125.
Referring to FIG. 1D, a gate insulating layer 160 is formed on the substrate 100, and the substrate is annealed to crystallize the source and drain regions and the first capacitor electrode 125 using a metal induced crystallization (MIC) technique and to crystallize the channel region using a metal induced lateral crystallization (MILC) technique.
Referring to FIG. 1E, a gate electrode 170 is formed to correspond to a region of the semiconductor layer 120 (the gate electrode 170 corresponds to the channel region of the semiconductor layer 120), and a second capacitor electrode 175 is formed to correspond to the first capacitor electrode 125. Then, an interlayer insulating layer 180 is formed on the substrate 100, and source and drain electrodes 191 and 192 are formed on the interlayer insulating layer 180 and extend through the interlayer insulating layer 180 and the gate insulating layer 160 to connect to the metal catalyst layer 150 on the source and drain regions of the semiconductor layer 120, thereby completing a thin film transistor and a capacitor. Moreover, not illustrated in FIG. 1E, a first electrode, an organic layer and a second electrode are formed, thereby completing a conventional OLED display device.
However, as described above, when the semiconductor layer is crystallized by the MIC/MILC techniques, MILC crystals are faced in the channel region, thereby generating a MILC front or grain boundary, that is, an uncrystallized region, which results in deterioration of charge mobility and device's characteristics.
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