1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a plurality of memory cell arrays and in which writing of data is carried in parallel by the plurality of memory cells.
2. Description of the Related Art
NAND flash memory is known as one type of non-volatile memory. In the NAND flash memory, non-volatile transistors are serially connected to form a NAND cell. Memory data of a plurality of non-volatile transistors can be simultaneously erased electrically. Writing of the NAND flash memory data can be carried out on the selected memory cell by applying predetermined voltages, thus shifting the threshold voltage. At the time of the writing, the threshold voltage is not shifted all at once to the desired threshold value. The voltage to be applied to the memory is gradually changed and one writing operation is carried out in a number of stages, and thus the threshold voltage can be changed by little by little. During the writing operation, data is read from the memory cell on which the writing is carried out, and a verifying reading operation is carried out to determine whether or not the data which was read matches the write data. For the memory cells whose verification result was “pass”, that is for the memory cell in which the writing was carried out such that the threshold voltage was within a predetermined range, the writing operation is finished. For the memory cells whose verification result was “fail”, that is, for those memory cells whose threshold voltage were not shifted sufficiently so as to be within the predetermined range, the voltage condition are changed and writing is carried out again.
It is to be noted that hereinafter, memory data for the memory cell in which the data is in the erased state or in which the threshold voltage is the original low value is considered “1”, while the memory data for the memory cell for which writing has been carried out and the threshold voltage had been converted to a high value is “0”.
The NAND flash memory is provided with a verification detecting circuit for determining whether or not the data has been correctly written in the memory cell.
FIG. 1 shows the main portions of a circuit structure of the NAND flash memory of the prior art in which a verification detecting circuit is provided.
A plurality of memory cells MC which includes the non-volatile transistors are provided in the NAND cell. Each of the non-volatile transistors has a control gate and a floating gate. Source-drain paths of the plurality of memory cells MC are serially connected. Also, a first select transistor SGT1 for selecting a NAND cell is connected to one end side of each NAND cell, and connected to the other end side is a second select transistor SGT2 for selecting the NAND cell. The control gates of the memory cells MC which form each of the NAND cells are provided so as to be common to those word lines which are provided so as to extend along a plurality of NAND cells. In addition, a select gate of the first select transistor SGT1 and a select gate of the second select transistor SGT2 are connected so as to be shared by the first select transistor SGT1 and the second select transistor SGT2 which are provided to extend along the plurality of NAND cells.
Also, each of the first select transistors SGT1 is connected to each of the latch circuits 31 via each of the bit lines BL. Each of the latch circuits 31 latches write data at a time of data writing, and at a time of the verifying reading, the latch circuit latches read data to be read to each of the bit lines BL from the memory cell. Each of the latch circuits 31 is connected to the verification detecting circuit 61.
A row decoder circuit 62 is connected to a plurality of word lines WL, a first select gate line SG1 and a second select gate line SG2. When data is read, written or erased, the word lines WL, the first select gate line SG1, and the second select gate line SG2 respectively are supplied with a predetermined voltage.
The writing operation of the memory shown in FIG. 1 is illustrated in the flowchart of FIG. 2. Firstly, write data is input to each of the latch circuits 31 and latched (S1). Subsequently, writing is carried out (S2). The writing is carried out as described in the following. Firstly, a bit line BL connected to the latch circuit latching the “1” level writing data charges voltage corresponding to “1” data. The bit line BL connected to the latch circuit 31 latching the “0” level writing data is caused to be 0 V. Subsequently, voltages which cause the first and second select transistors SGT1 and SGT2 to be in a on state are output from the row decoder circuit 62 to the first and second select gate lines SG1 and SG2. Further, a high voltage Vpgm is output from the row decoder circuit 62 to the selected word line connected to the memory cell in which the writing is carried out, and a high voltage Vpass which is lower than the high voltage Vpgm (Vpgm>Vpass) is output for all the remaining unselected word lines connected to memory cells in which writing is not carried out.
As a result, the voltage of the bit line BL which corresponds “1” data is transmitted to the drain of the memory cell in which writing is carried out and data writing is carried out on this memory cell.
After the data is written, the memory cell on which data writing was carried out is selected and data is read. The verifying reading is carried out by latching the data at the corresponding latch circuit 31 (S3). The data latched at each latch circuit 31 is sent to the verification detecting circuit 61. Here a comparison with the written data is carried out to thereby determine whether or not the writing was correctly carried out (S4). In the case where the data was not correctly written, the writing operation and the verifying operation are carried out once again. By repeatedly carrying out these operations, the data is eventually written correctly.
It is to be noted that in NAND flash memory, in order to increase the writing speed substantially, a system is used in which a large amount of data is written all at once. That is to say, the data writing is carried out in parallel at a plurality of memory cells connected to one word line. Accordingly, the unit for executing writing is a word line unit, and the writing unit is referred to as “page”.
When the unit of memory which must be written at one time increases because of increases in the amount and speed of memory, one page uses a plurality of memory cell arrays in a flash memory. When one page spreads across a plurality of memory cell arrays in this manner, at the time data writing is executed, high voltage Vpgm and Vpass are simultaneously supplied to the selected word lines and the unselected word lines of all of the memory cell arrays in one page. Accordingly, if there is even one memory cell in a page for which writing is not complete, high voltage continues to be applied to the control gates of memory cells in the memory cell arrays for which writing has already been complete. When writing continues to be carried out despite the fact that the writing has been completed, the threshold voltage is not within the predetermined voltage distribution and writing is erroneous. The time for writing to be completed differs for different memory cell arrays because writing conditions vary due to variations in the structure of the memory cells.
In order to prevent this erroneous writing, in the prior art, a measure is used in which the bit line connected to the memory cell for which writing is complete, is caused to float electrically.
However, even when the measure is used, the erased memory cell which has the data “1” in its memory has a small amount of writing, and as shown by broken lines in FIG. 3, a threshold voltage is not within the predetermined distribution range.
Accordingly, voltage unnecessary for the control gate of the memory cell must not be applied to memory cell arrays in which writing has been completed.
Further, the data to written may be less than one page, or there may at least one memory cell array in the plurality of memory cell arrays for which it is unnecessary to write data. In such cases, in the prior art, high voltage continues to be supplied to the control gate of the memory cell arrays which do not need to be written as well, until data writing is complete at all of the memory cell arrays. In these cases also, as described above, the erased memory cell which has the “1” data in its memory has a small amount of writing, and the threshold voltage is not within the predetermined distribution range.
In this manner, in the non-volatile memory of the prior art in which a unit of writing to be executed at once is executed by a plurality of memory cell arrays, voltage is supplied for word lines which are commonly provided to a plurality of memory cell arrays and writing of data is carried out. Thus due to variations in the structure of the memory cell, the conditions for writing differ, and after the writing, the threshold voltage is not with the desirable distribution range.
USPTO Backgrounds
USPTO Backgrounds