1. Field of the Invention
The invention relates in general to a memory control circuit, and more particularly to a memory control circuit performing erase verification operation on a memory array of a memory.
2. Description of the Related Art
Referring to FIG. 1, a schematic illustration of a conventional memory is shown. In an example, a memory array MA includes memory banks BNK0 to BNKN, each of which includes M memory blocks, wherein N is a natural number greater than 1 and M is a natural number greater than 1. For example, the memory bank BNK0 includes memory blocks BLO1 to BLOM. Since an erase process and an erase verification process performed on each of the memory blocks BLO1 to BLOM are similar, only the process performed on the memory block BLO1 is cited as an example described in the following paragraphs.
The memory block BLO1 includes memory cells Ce1 to Ce7, and boundary memory cell CB, each of which is for storing 2 bit data. For example, the boundary memory cell CB stores bit data BT1 and BT2. Generally, in an erase verification process performed on the memory block BLO1, data stored in the memory cells Ce1 to Ce7 and the boundary memory cell CB are sensed for determining whether the memory block BLO1 is verified to be erased. If not, the erase process will be executed for erasing the memory block BLO1.
Bit data stored in the memory cells Ce1 to Ce7 and the bit data BT1 stored in the boundary memory cell CB are sensed and erased by a sense amplifier SE1 and a bias circuit BS1, which are both corresponding to the memory block BLO1. However, due to the circuitry structure of the memory block BLO1, bit data BT2 stored in the boundary memory cell CB is sensed by the sense amplifier SE1 corresponding to the memory block BLO1, but is erased by a bias voltage VB provided by a bias circuit BS2 corresponding to the memory block BLO2.
For example, when the bit data BT2 is erased, the bias voltage VB provided by the bias circuit BS2 is provided to the end of the boundary memory cell CB storing the bit data BT2 via the Y-multiplexer YM2, the bit line BL1′, the bank selection switch Sel1 corresponding to the memory block BLO2. Thus, the sensed result corresponding to the bit data BT2 should be considered in the control of the bias circuit BS2 via which the erase voltage erasing the bit data BT2 stored in the boundary memory cell CB is provided.
Referring to FIG. 2, a schematic illustration of the Y-multiplexers in FIG. 1 is shown. In FIG. 2, only the Y-multiplexers YM1 to YM3 are shown as example. The Y-multiplexer YM1, YM2, and YM3 respectively includes data channels Ysa0 to Ysa3, Ysb0 to Ysb7, and Ysc0 to Ysc4. As shown in FIG. 2, each data channels Ysa0 to Ysa3, Ysb0 to Ysb7, and Ysc0 to Ysc4 are arranged in accordance with the sequence of the mark numbers and the data channels with the greatest mark numbers (i.e. 3, 7, and 4) correspond with the boundary memory cells of the corresponding memory blocks.
In an example, the mark numbers indicate the corresponding address value of an address Adr. For example, the data channels with mark number of 1, (i.e. Ysa1, Ysb1, and Ysc1) are enabled in response to the first value of the address Adr. The value of the address Adr is sequentially altered from its initial value to its terminal value.
When the address Adr indicates the value of 3, the bit data BT2 of the boundary memory cell CB of the memory block MLO1 is sensed by the sense amplifier SE1. According to the previous paragraphs, it can be obtained that the sensed bit data BT2 should be considered in the control of the bias circuit BS2. However, a bit data of a memory cell of the memory block MLO2, which is provided by the Y-multiplexer YM2 in response to the third value of the address Adr, is also sensed and outputted by the sense amplifier SE2. Thus, additional logic circuits and control signals are needed to control the operation of the bias circuit BS2 based on the two sensed result is a challenging task.
Furthermore, similar boundary situation will occur whenever two adjacent memory blocks corresponding to different numbers of data channels. Thus, it is challenging and time-consuming to design corresponding logic for all those logic control. Besides, once the order of the memory blocks is changed, all the logic circuits must be redesigned since the time of referencing the sensing result of the sense amplifier corresponding to the adjacent memory block is totally different. Therefore, it is desirable to design a circuit to simplify and unify the erase operation on the boundary of different memory blocks.
USPTO Backgrounds
USPTO Backgrounds