1. Field of the Invention
The present invention relates to a chemical vapor deposition (CVD) process chamber and, specifically, to a single wafer, multi-chamber CVD system.
2. Description of Related Art
A continuing challenge in the fabrication of integrated circuits is to maintain a wafer at a constant and uniform temperature so that various layers (i.e., epitaxial layers, polysilicon layers, etc.) of a uniform thickness and resistivity may be deposited thereon. In a typical radiantly heated "warm" wall CVD reactor, a wafer is placed in a quartz containment vessel. As the vessel and the wafer therein are heated by lamps positioned external to the vessel, process or reactant gases are pumped into the vessel so as to deposit on the wafer.
Warm wall CVD reactors, such as the one described above, have a number of limitations which adversely affect efficiency, reliability, and performance. For single wafer CVD systems, including those tailored to deposit epitaxial and polysilicon layers, throughput is an important consideration. Perhaps the biggest obstacle to improving throughput in such CVD systems is the time required to clean the chamber walls after each wafer is processed. Cleaning the chamber walls in radiantly heated quartz CVD chambers is vital since process gases deposit not only on the wafer but also on the chamber walls. The resultant film formed on the chamber walls absorbs some of the radiant energy emitted from the heating lamps and thereby locally increases the temperature of the chamber walls. As a result, process gases deposit on the chamber walls at an increasing rate, thereby creating a "snowball" effect. It is therefore critical, in a radiantly heated CVD chamber, that the walls be kept meticulously clean. This requires that the walls be etched frequently, sometimes even after every run. Cleaning the walls typically takes between 2 to 3.5 minutes after depositing an epitaxial layer, and up to one hour after depositing polysilicon used in sealing the backside of silicon wafers. Such long cleaning times result from the relatively slow etchant rates associated with the warm walls of the chamber (which are designed to transmit heat). Since the entire cycle time in warm wall CVD systems may be between 5-10 minutes, cleaning the walls accounts for a significant portion of the cycle time.
Another factor affecting the throughput of such CVD chambers is the deposition rate of the process gases. Chambers that are optimized for deposition rates can decrease the deposition time required for a single wafer by as much as 25%.
Additionally, lamp failure (and the maintenance related thereto) and a required wet etching of the quartz chamber walls of such CVD systems adversely affect reliability and uptime. Note that wet etching requires disassembling the CVD system so that the quartz walls may be submerged in a wet etch bath.
Temperature control of the wafer is imperative for the deposition of uniform layers. The above described deposition of process gases on the chamber walls of lamp heated systems can occur within a single run and may affect the temperature uniformity within a run. Thus, cleaning the chamber walls after each wafer run may be ineffective in preventing non-uniformities resulting from deposition of process gases on the chamber walls.
Achieving a constant and uniform temperature across a wafer is further complicated by variations in the emissivity of the wafer. Since a wafer's emissivity depends in part upon the surface material of the wafer and upon temperature, accurately calibrating a reactor so as to bring the wafer to a constant and uniform temperature may be difficult.
An optimum CVD system should be able to operate at both atmospheric and reduced pressures. Reduced pressure operation requires a chamber design able to withstand the physical stresses of a lower pressure processing environment, i.e., a vacuum chamber. On the other hand, optimum designs for wafer processing may require a process gas flow channel having a narrow profile. This narrow profile optimizes process gas flow to the wafer by facilitating a maximum velocity flow of process gas across the wafer while minimizing the mass transfer boundary layer. In addition to having a narrow profile, chambers designed for optimum processing typically have simple non-convoluted surfaces so as to minimize vortices and backflow, to minimize dead spots that may promote deposition on the chamber walls, and to allow etching gases employed to clean the chamber walls to quickly reach the chamber walls. Unfortunately, such flat-topped quartz or graphite process chambers cannot easily sustain a pressure gradient across their walls. Chambers capable of withstanding such pressure differences typically are either of a fuller shape, such as a bell or globe structure, and therefore not only compromise optimum gas flow across the surface of the wafer but also do not facilitate an efficient cleaning of the chamber walls. Another approach is to incorporate structural reinforcement elements on the chamber walls. Unfortunately, such elements hamper the uniform transmission of radiant energy to the wafer. As a result, single chamber CVD designs suitable for reduced pressure operation typically compromise processing considerations such as process gas flow or thermal uniformity in order to increase structural integrity.
USPTO Backgrounds
USPTO Backgrounds