1. Field of the Invention
The present invention relates to the field of fabrication of semiconductor devices. More specifically, the invention relates to the fabrication of bipolar transistors.
2. Background Art
In one type of bipolar transistor, and more particularly a heterojunction bipolar transistor (xe2x80x9cHBTxe2x80x9d),used as an example in the present application, a thin silicon-germanium (xe2x80x9cSiGexe2x80x9d) layer is grown as the base of the bipolar transistor on a silicon wafer. The SiGe HBT has significant advantages in speed, frequency response, and gain when compared to a conventional silicon bipolar transistor. Speed and frequency response can be compared by the cutoff frequency which, simply stated, is the frequency where the gain of a transistor is considerably reduced. Cutoff frequencies in excess of 100 GHz have been achieved for the SiGe HBT, which are comparable to the more expensive GaAs. Previously, silicon-only devices have not been competitive for use where very high speed and frequency response are required.
The higher gain, speed and frequency response of the SiGe HBT are possible due to certain advantages of silicon-germanium, such as a narrower band gap and reduced resistivity. These advantages make silicon-germanium devices more competitive than silicon-only devices in areas of technology where high speed and high frequency response are required. The advantages of high speed and high frequency response discussed above require, among other things, proper alignment of the SiGe HBT emitter window opening and minimal SiGe base resistance.
In a conventional approach for forming an emitter window opening in a SiGe HBT, two silicon dioxide (xe2x80x9coxidexe2x80x9d) spacers are formed on a base oxide layer on the top surface of a single-crystal SiGe base. A sacrificial post is formed between the two oxide spacers, followed by base ion implantation into the regions of the SiGe base not shielded by the sacrificial post and the oxide spacers. The sacrificial post and oxide spacers are then covered, for example, by a conformal layer of amorphous silicon. Next, a layer of masking material, such as photoresist, is deposited over the conformal layer of amorphous silicon. An emitter window clear-out opening is then formed by patterning and etching an opening in the layer of masking material to expose the conformal layer of amorphous silicon. An emitter window opening is next formed by etching the conformal amorphous silicon layer and the sacrificial post. A base oxide layer in the emitter window opening is then etched to expose the top surface of the base. The emitter of the SiGe HBT is then formed by depositing, for example, polycrystalline silicon between the two oxide spacers on the top surface of the base. The resulting emitter has a width approximately equal to the width of the sacrificial post.
Ideally, the width of the emitter window clear-out opening is equal to the width the sacrificial post. However, alignment tolerance must be taken into account since each photolithography tool utilized to pattern the emitter window clear-out opening is subject to some degree of misalignment. For example, if the emitter window clear-out opening is to be aligned with a 200.0 nanometer (xe2x80x9cnmxe2x80x9d)-wide sacrificial post, a photolithography alignment tolerance of plus or minus 85.0 nm requires that the emitter window clear-out opening etched in the masking material have a width of at least 370.0 nm. However, as the width of the emitter window clear-out opening is increased, the risk of exposing the regions beyond the outer edge of the spacers and etching into the SiGe base is also increased. The resulting damage that can be caused by etching into the SiGe base detrimentally affects the performance of the SiGe HBT.
Conventional methods utilized in the fabrication of SiGe HBTs have not provided adequate photolithographic alignment margin without compromising the performance of the SiGe HBT. For example, to protect against the above risk of etching into the SiGe base, conventional methods typically increase the width of the spacers to fully contain the alignment tolerance range of the photolithography tool when patterning the emitter window clear-out opening. By increasing the width of the spacers, however, a greater portion of the underlying SiGe base is shielded from the subsequent base ion implantation step and, therefore, remains undoped. This increases the resistance of the SiGe base and adversely affects the performance of the SiGe HBT. Thus, conventional methods for controlling the photolithographic alignment margin in the fabrication of a SiGe HBT typically sacrifice SiGe base resistance in order to avoid the risk of damaging the SiGe base.
Thus, there is a need in the art for a bipolar transistor, such as a SiGe HBT, that provides improved alignment tolerance without undesirably decreasing performance.
The present invention is directed to method for improved alignment tolerance in a bipolar transistor and related structure. The present invention addresses and resolves the need in the art for improved alignment tolerance in a bipolar transistor, such as a SiGe HBT, without undesirably decreasing performance.
According to one exemplary embodiment, a bipolar transistor comprises a base having a top surface. The bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. The heterojunction bipolar transistor further comprises a first inner spacer and a second inner spacer situated on the top surface of the base. The first and second inner spacers, for example, may be silicon oxide. The heterojunction bipolar transistor further comprises a first outer spacer situated adjacent to the first inner spacer and a second outer spacer situated adjacent to the second inner spacer on the top surface of the base. The first and second outer spacers may be, for example, situated over an implanted dopant region of the base and may comprise silicon oxide. The implanted dopant may be, for example, boron.
According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between the first and second inner spacers. The emitter may comprise, for example, polycrystalline silicon. The heterojunction bipolar transistor may further comprise an intermediate oxide layer situated on the first and second outer spacers. The intermediate oxide layer may comprise, for example, silicon oxide. The heterojunction bipolar transistor may further comprise an amorphous layer situated on said intermediate oxide layer. The amorphous layer may, for example, comprise amorphous silicon. The heterojunction bipolar transistor may further comprise an antireflective coating layer on the amorphous layer. The antireflective coating layer may, for example, comprise silicon oxynitride. In another embodiment, the present invention is a method that achieves the above-described bipolar transistor. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds