The majority of present day integrated circuits (ICs) are implemented utilizing a plurality of interconnected field effect transistors (FETs), also referred to as metal oxide semiconductor field effect transistors (MOSFETs) or more simply MOS transistors. MOS transistors have traditionally been fabricated on bulk silicon wafers. Although many MOS transistors are still fabricated on bulk silicon wafers, MOS transistors are increasingly produced on semiconductor-on-insulator (SOI) substrates. A representative SOI substrate includes a thin layer of silicon overlaying an intermediate insulating layer, which is supported by a bulk wafer. The intermediate insulating layer typically comprises silicon oxide and is commonly referred to as a “buried oxide” or “BOX” layer. In certain instances, the silicon layer overlaying the BOX layer may be scaled down in proportion to the dimensions of other device parameters (e.g., gate length). When the overlaying silicon layer has a thickness less than approximately 25 nm, the SOI substrate is commonly referred to as an “extremely thin” SOI or “ETSOI” substrate.
Relative to MOS transistors produced on bulk wafers, MOS transistors produced on ETSOI substrates generally achieve lower junction capacitances and higher operational speeds. However, the thin overlaying silicon layer of the ETSOI substrate provides relatively limited space in which to form source and drain regions. For this reason, elevated or raised source/drain regions may be formed in and over the ETSOI substrate. To create raised source/drain regions on an ETSOI substrate, one or more disposable sidewall spacers are typically formed adjacent the gate stack. The disposable spacers can be formed by, for example, low pressure chemical vapor deposition of silicon nitride (SiN). After one or more pre-cleaning steps, a selective epitaxial growth process is performed to grow raised source/drain regions offset from the gate stack by the disposable spacers. A previously-deposited silicon nitride (SiN) cap prevents epitaxial growth over the gate stack. After ions are implanted into the raised source/drain regions, a hot phosphoric acid wet etch is performed to remove the disposable spacers. The hot phosphoric acid etch removes the disposable spacers in their entirety and, in so doing, creates a void in the overlaying silicon layer between each sidewall of the gate stack and the neighboring raised source/drain. The hot phosphoric acid etch also removes the silicon nitride cap overlaying the gate stack. Finally, an activation spike anneal is performed to activate and diffuse the ions implanted in the raised source/drain, as well as ions implanted during previous gate doping steps. Various additional steps are then performed (e.g., halo and extension implants, final spacer formation, laser activation anneal, etc.) to further complete the device.
Although generally satisfactory for producing an ETSOI semiconductor device, the above-described fabrication process is limited in certain respects. For example, during the activation spike anneal, the ingress of oxygen from the source/drain region may result in under-oxide regrowth near the interface between the metal gate stack and the overlaying silicon layer of the ETSOI substrate. In particular, the ingress of oxygen into the ETSOI substrate may result in the oxidation of the well region underlying the gate stack, as well as oxidation of the gate insulator included within the gate stack, especially if the gate insulator is formed from a high-k material. Oxidation of the gate insulator increases the gate insulator's thickness undesirably and negatively impacts the overall performance and scalability of the resulting ETSOI semiconductor device.
Accordingly, it would be desirable to provide methods for manufacturing a semiconductor device, such as an ETSOI semiconductor device, that minimizes or eliminates the occurrence of under-oxide regrowth during the activation spike anneal and other high temperature processing steps (e.g., selective epitaxial growth of the raised source drain regions). Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds