1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices are known, which comprise a plurality of input pins in a row, a plurality of output pins in a row, and a memory cell array. The memory cell array includes a plurality of cell plates in a single row between the input and output pin rows and decoders. A plurality of sense amplifiers are in a row between the cell row and the output pin row. An address circuitry and an address transition detector (ATD) circuitry are disposed between the input pin row and the cell row. The ATD circuitry provides an ATD pulse upon detecting a transition in the address circuitry. An ATD pulse synthesizer is disposed between the ATD circuitry and the cell row and provides a synthesized pulse in response to the ATD pulse. An output circuitry is disposed between the cell row and the output pin row. A delay circuitry provides a sense amplifier data latch signal and an output data latch signal in response to the synthesized pulse. In the known semiconductor memory devices, one of the cell plates is selected after a first delay, called “a cell select” time, based on an address data from the input pins. In response to a delayed synthesized pulse from the ATD pulse synthesizer, the delay circuitry provides latch signals to excite the sense amplifier and the output circuitries after a second delay, called “a pulse delay” time. In order to save consumption of current and maintain high speed operation, the following relationship must be maintained.(Pulse delay time)>(Cell select time)In the known semiconductor memory devices, it was possible to keep a memory cell transistor conductive (ION) to allow for the use of digit line long enough to provide the “pulse delay” time required.
High-density demands are growing in semiconductor memory devices, This tendency makes it difficult for a cell transistor to maintain performance as high as required. In order to minimize deterioration of read speed, it has been proposed to shorten the digit line and increase the number of cell plates. High expectation remains toward implementation of this proposal in semiconductor memory devices.
One approach toward realization of such semiconductor memory devices involves use of two or more word lines and two or more digit lines per each of a plurality of unit cell plates.
According to this proposed semiconductor memory device, there is no space or area for all X-predecoders to be distant substantially equally from an address circuitry, which is located near input pins. Moreover, sense amplifiers and an output circuitry cannot find any space or area near output pins so as to be substantially equally distant from an address transition detector (ATD) circuitry and an ATD pulse synthesizer. Thus, selecting a cell plate remotest from the ATD pulse synthesizer makes increasingly difficult to maintain the required relationship that (Pulse delay time)>(Cell select time).
As the amount of parasitic CR increases, the “cell select” time upon selecting the remotest cell plate may exceed the “pulse delay” time. There are proposals to cope with this problem. One proposal Is to insert a delay element into a delay circuitry. Another proposal is to use a sufficiently long signal transmission line to the delay circuitry from the ATD pulse synthesizer.
As is well known to those skilled in the art, voltage dependency, temperature dependency and VT dependency differ considerably from a capacitor element made of a transistor to a capacitor element that occurs parasitically due to signal transmission through a line. Thus, implementing the first-mentioned proposal inevitably apply a considerably great capacitor element, as a delay element, to the delay circuitry. Use of such capacitor element causes a drop in high-speed characteristic of the semiconductor memory device. Thus, there is an upper limit to increasing capacitance of a capacitor element, as the delay element, for the delay circuitry.
The second proposal mentioned before causes an increase in wiring region, resulting in an increase in chip size.
A need remains for development of a semiconductor memory device to accomplish a high read/write speed characteristic and to reduce consumption of current by preventing output of error data.
USPTO Backgrounds
USPTO Backgrounds