The present invention relates to a method of manufacturing a semiconductor device and to a technology effectively applicable to the manufacture of a semiconductor device formed by mounting a chip laminate including a small-diameter semiconductor chip and a large-diameter semiconductor chip over the top surface of a substrate for example.
Patent Literature 1 discloses a SIP (System In Package) type semiconductor device formed by mounting a controller chip over the top surface of a wiring substrate and laminating a memory chip over the top surface of the controller chip. The controller chip to control the memory chip is mounted over the top surface of the wiring substrate by flip-chip (face-down) bonding through bump (protrusion) electrodes and the gap between the wiring substrate and the controller chip is filled with an adhesive agent. Meanwhile, the memory chip is mounted over the top surface of the controller chip by face-up bonding through an adhesive agent and electrode pads (bonding pads) of the memory chip are electrically connected with electrode pads (bonding leads) of the wiring substrate through wires.
Patent Literatures 2 and 3 disclose a COC (Chip On Chip) type semiconductor device formed by mounting a plurality of semiconductor chips (a chip laminate) between a metal substrate and a wiring substrate which are arranged oppositely. The semiconductor chips configuring the chip laminate: include a plurality of memory chips and an interface chip to control the memory chips; and are electrically connected with each other through through-vias formed by penetrating the semiconductor chips and bump electrodes formed at both the ends of the through-vias. In the chip laminate, the interface chip having a smaller area than the memory chips is arranged at a position nearest to the wiring substrate and bump electrodes of the interface chip are electrically connected with electrode pads of the wiring substrate through wire bumps.
USPTO Backgrounds
USPTO Backgrounds