This invention relates generally to testing integrated circuits and particularly relates to testing intellectual property cores formed on integrated circuits.
Cost effective integrated circuit or IC testing is very important to IC manufacturers from a profit and loss standpoint. Increases in complexity of ICs are being accompanied by an increasing difficulty to test ICs. New test techniques must be developed to offset increasing IC test cost, otherwise advancements in IC technology may be slowed. One emerging technology that is going to accelerate the complexity of ICs even more is intellectual property cores. These cores will provide highly complex pre-designed circuit functions such as; DSPs, CPUs, I/O peripherals, memories, and mixed signal A/D and D/A functions. These cores will exist in a library and can be selected and placed in an IC to quickly provide a complex circuit function. The low cost testing of ICs contain highly complex core functions will be challenging.
The way to improve test access to cores embedded within ICs is by providing an addressable test port for each core. The addressable test ports provide the capability of directly addressing a core to be tested and, once addressed, cost effectively testing the core. The addressable test port is scalable, allowing it to increase or decrease its test capabilities, depending upon the type of circuitry contained in the core to be tested.
In particular, this invention provides an integrated circuit comprising functional input and output signal leads, input and output circuits connected to the functional input and output signal leads, core circuitry, and interconnect wires and circuits connecting the input and output circuits and the core circuitry. The integrated circuit further includes an addressable test port for each core circuitry. Each test port is connected to its respective core circuitry and to the interconnect wires and circuits. External test signal leads connected to each test port.
The test ports connect to their respective core circuitry by mode, input, output, and control signals. The test ports connect to the interconnect wires and circuits by an input bus and an input/output bus, and the external test signal leads include a serial input, a serial output and a control bus.
Each test port includes an address register, a test controller, an input port, and an input/output port. The address register connects in series to a serial input lead and a serial output lead. The test controller connects to control bus leads and a mode signal lead connected to the core circuitry. The input port connects to input bus leads, which are connected to the interconnect wires and circuits, and connects to input leads that connect to the core circuitry. The input/output port connects to input/output bus leads, which are connected to the interconnect wires and circuits, and connects to output leads connected to the core circuitry and a status lead connected to the core circuitry.
The control bus leads include leads for analog inputs/outputs, a test status output, a test protocol input, a test clock input, and a reset input.
The test controller includes a test port state machine and plural test operation state machines connected to leads for a test protocol input and a test clock input and the test port state machine connects to a reset input.
The input port includes a comparator circuit, an input register circuit, a mode and address register circuit, an update register circuit and a decode logic circuit interconnected with one another.
The input/output port includes read enable sequencer circuitry, input buffer circuitry, multiplexer circuitry and input/output buffer circuitry.
USPTO Backgrounds
USPTO Backgrounds