The on-going demand for high performance electronic systems has driven the need for high-speed digital Very Large Scale Integration (VLSI) chips. VLSI implementations have proceeded in two inter-related directions: higher performance and higher density (more devices per unit area). While modern VLSI chips have achieved astonishingly high levels of performance and chip density, there is a very strong demand for even higher levels.
One serious impediment to achieving what is demanded from VLSI devices is power consumption. As a rule of thumb higher performance requires more power. But, more power produces more heat, which increases failure rates. Consequently, power consumption is the predominant challenge in improving modern high performance systems.
Almost all modern VLSI chips are clocked. That is, the operations of the gates within a VLSI chip are synchronized to act together by clock signals. As long as the gates can keep up, the higher the clock rate the faster the performance. Unfortunately, as clock rates and VLSI chip densities increase it becomes very difficult to ensure that all of the chips can keep up with the clocks. One reason for this is that each sequential element in a VLSI chip needs its own clock signal, but not all devices are the same distance from the clock signal source, which means that all clock lines are not the same length and that associated parameters such as distributed capacitances and resistances, differ. Different lengths coupled with unavoidable signal delays caused by distributed resistances and capacitances mean that clock signals arrive at different devices at different times (clock skew). Such can effectively limit the performance of a VLSI chip.
Compounding the clocking problems is the fact that clocking requires power. In fact, the on-chip clock distribution network (CDN) of modern VLSI chips often consumes more than 35% of the total chip power and can occasionally require as much as 70%.
Various approaches have been attempted in the prior art to address VLSI clocking problems. One approach to decreasing CDN power consumption is to use resonant clocks in the VLSI clock distribution network. For example see the following applications: U.S. App No. 61/502,619 Title: DISTRIBUTED LC RESONANT TANKS CLOCK TREE SYNTHESIS, and U.S. App No. 61/502,626 Title: DISTRIBUTED RESONANT CLOCK GRID SYNTHESIS, and U.S. App No. 61/502,635 Title: METHODS FOR INTEGRATED CIRCUIT C4 BALL PLACEMENT, inventor in all cases is Dr. Matthew Guthaus. Also see U.S. application Ser. No. 12/903,166 (US 2011/0090018 A1) that describes an inductor architecture for resonant clock distribution networks that allows for the adjustment of the natural frequency of a resonant clock distribution network, so that it achieves energy-efficient operation at multiple clock frequencies. Also see U.S. Ser. No. 12/903,168 (WO2011/046981A2) that describes an architecture allows for the energy-efficient operation of a resonant clock distribution network at multiple clock frequencies through the deployment of flip-flops that can be selectively enabled. Also see US20110090019A1, US20110090018A1, US20110084772A1, US20090027085A1, and WO2011046974A3. These applications and any publication thereof, and any and all publications referred to in this disclosure, are hereby incorporated by reference to the fullest extent allowed by law.
While resonant clock circuits have proven to be a viable way to reduce power consumption they have not been fully developed. For example, modern VLSI devices are capable of operating at multiple frequencies. One major reason for this is the desire to reduce power consumption, not only on the clock lines but on data lines. Consequently there is a need to achieve the benefits of resonance clock distribution networks and operation at multiple frequencies in the same device.
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USPTO Backgrounds