1. Field
Example embodiments relate to a non-volatile memory device and a method of fabricating the same. Other example embodiments relate to a variable resistance random access memory device that is operated at a lower operating voltage by including an n+ interfacial layer between a lower electrode formed of a common metal and a buffer layer and a method of fabricating the same.
2. Description of the Related Art
Semiconductor memory devices may have higher integration density, faster operation speeds and lower operating voltage. A conventional memory device may include a plurality of circuitry connected to memory cells. In the case of dynamic random access memory (DRAM), which is representative of a semiconductor memory device, a unit memory cell may include one switch and one capacitor. DRAMs may have higher integration density and faster operating speeds. However, stored data may be erased after power is turned off.
A non-volatile memory device may maintain stored data after power is turned off, and such an example of a non-volatile memory device may be a flash memory. The flash memory may be a non-volatile memory device that differs from the volatile memory device in that the non-volatile memory device may have a lower integration density and slower operating speeds than DRAM.
Research is being conducted on non-volatile memory devices including magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase-change random access memory (PRAM) and resistance random access memory (RRAM). Of the above mentioned non-volatile memory devices, RRAM may use variable resistance characteristics according to the voltage of a transition oxide.
FIG. 1A is a diagram illustrating a structure of a RRAM device that uses a variable resistance material having a conventional structure. The RRAM device that uses a transition metal oxide as a variable resistance material may have switching characteristics in order to be used as a memory device.
Referring to FIG. 1A, the RRAM may have a structure in which a lower electrode 12, an oxide layer 14, and an upper electrode 16 may be sequentially formed on a substrate 10. The lower electrode 12 and the upper electrode 16 may be formed of a common conductive metal and the oxide layer 14 may be formed of a transition metal having variable resistance characteristics. The transition metals may include ZnO, TiO2, Nb2O5, ZrO2 and/or NiO.
FIG. 1B is a graph illustrating operation characteristics of the non-volatile variable resistance memory device illustrated in FIG. 1A. Current was measured by applying a voltage with respect to a specimen in which the lower electrode 12 may be formed of Ru, the oxide layer 14 may be formed of NiO and the upper electrode 16 may be formed of Ru. Referring to FIG. 1B, when about 0.7 V are applied to the specimen at the first switching cycle, the reset current may be about 3 mA. However, after about 50 switching cycles, the reset current may be increased to about 50 mA. As the switching cycles are repeated, the resistance state of the oxide layer 14 may continuously change and an operating voltage and a reset voltage may increase, thereby reducing the reliability of the non-volatile variable resistance memory device. There may be a need to have a structure of a memory device that may have relatively stable operating characteristics.
Because higher integration is structurally difficult in the case of a flash memory device, research on cross-point type memory devices has been conducted. There may be a need to develop a cross-point type memory device having a structure using a variable resistance material. There may be a need of a memory device having a lower electrode using a common metal instead of an expensive noble metal.
USPTO Backgrounds
USPTO Backgrounds