Dual-bit flash memory cells, which allow the storage of two bits of information in a single memory cell, are becoming quite common. A dual-bit memory cell is generally symmetrical. One bit of information is stored as a level of electrical charge on one side (e.g., the “left side”) of a charge storage element (e.g., the gate structure), and another bit of information is similarly stored on the other side (e.g., the “right side”) of the charge storage element. Each side of the charge storage element can be programmed and erased independently of the other side, and the drain and source are interchangeable. That is, the left-side junction can serve as the source terminal for the left-side bit of information and as the drain terminal for the right-side bit of information, and the right-side junction can serve as the source terminal for the right-side bit of information and as the drain terminal for the left-side bit of information.
The memory cells are typically arrayed in rows and columns. All the cells in a row have their gate structures connected to the same word line. All the cells in a column have their left-side junctions connected to one bit line, and their right-side junctions connected to another bit line. During programming of a memory cell, a source bias voltage VS is applied to the bit line connected to the side of the memory cell that is serving as the source terminal, and a drain bias voltage VD is applied to the bit line connected to the other side of the memory cell.
Programming a dual-bit flash memory cell is facilitated if the drain and source sides of the cell are set to known voltages. The goal is to attain a relatively constant voltage difference VDS (VDS=VD−VS), resulting in relatively constant programming speed for all sectors in the memory array. However, some sort of voltage compensation is generally necessary because various voltage drops are present along the path from the voltage generator (e.g., a high voltage source) to the drain and source sides of a cell. “VDS compensation” refers to the adjustments of the drain and source voltages to account for any such voltage drops, so that the voltage across the cell remains relatively constant during programming.
A drain-side voltage regulator and a source-side voltage regulator can be used to adjust VD and VS, respectively. Conventionally, the voltage regulators are designed with specific capacitor ratios implemented in hardware. The capacitor ratios dictate the voltage compensation parameters applied to the various cells in the memory array.
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