1. Field of the Invention
This invention relates to computer systems and, more specifically, to a system and method which will allow any agent in a peripheral component interconnect (PCI) bus system to inform the CPU to PCI bus bridge that an input/output (I/O) instruction executed by the central processing unit (CPU) and targeted for the agent in question is to be trapped.
2. Description of the Prior Art
In the past, in order to trap I/O instructions issued by the CPU and destined for a device that is unable to respond, a centralized power and system management circuit detects the trappable I/O instructions by checking the I/O address of where the I/O instruction is to be sent to verify if the device in question was powered up or down. If the device was powered down, the power and system management circuit informed the system controller of this situation and asserted a system management interrupt (SMI) signal to the CPU before completion of the I/O instruction on the CPU bus. This centralized mechanism did not lend itself well to distributed power management systems because of the requirement to know in advance the devices to be used so the central power and system management circuit could be designed to monitor the power status of each device. This resulted in a large and complex centralized power and system management circuit. Therefore, there existed a need to provide an improved system for trapping I/O instructions and a method therefor.
USPTO Backgrounds
USPTO Backgrounds