Exemplary embodiments of the present invention relate to a technology of fabricating a semiconductor device, and more particularly, to a Schottky diode and a method for fabricating the same.
A Schottky diode mainly used as a switching element or a rectification element in a semiconductor device uses a metal-semiconductor junction and has superior high speed switching characteristics as compared with a general PN junction diode. This is because minority carrier injection (MCI) does not occur when a forward voltage is applied to the Schottky diode, differently from the PN junction diode. In the case of the Schottky diode, a current flows by majority carriers instead of minority carriers. Therefore, the Schottky diode has an advantage that a reverse recovery time is very short because there is no accumulation effect. However, the Schottky diode has a disadvantage that it is difficult to control a high current (or a high voltage) because a current flows by majority carriers. In this regard, recently, a Schottky diode is extensively used, which includes a guard ring in order to achieve high speed switching characteristics and simultaneously control a large current.
FIG. 1 is a cross-sectional view illustrating a Schottky diode in accordance with a first prior art, and FIGS. 2A and 2B are diagrams illustrating the problem of the Schottky diode in accordance with the first prior art.
Hereinafter, the Schottky diode in accordance with the first prior art will be described with reference to FIG. 1. The Schottky diode includes an N type deep well 12 formed in a substrate 11, an isolation layer 22 formed in the substrate 11, an N type well 16, a cathode electrode 17 coupled to the well 16, a P type guard ring 20, and an anode electrode 21 coupled to the deep well 12 and the guard ring 20. The N type well 16 is formed in the deep well 12 and is located at the right side of the isolation layer 22. The guard ring 20 is formed in the deep well 12 and is located at the left side of the isolation layer 22 while being spaced apart from the isolation layer 22 by a predetermined interval. The guard ring 20 includes a P-type first impurity region 19 formed on the surface of the substrate 11, and a P-type second impurity region 18 formed under the P-type first impurity region 19 having an impurity doping concentration lower than that of the first impurity region 19.
As indicated by reference numeral A of FIG. 1, which illustrates the Schottky diode in accordance with the first prior art, and reference numeral A of FIG. 2A which is a simulation image illustrating stress concentration, since the guard ring 20 is spaced apart from the isolation layer 22 by the predetermined interval, it is problematic in that stress is concentrated between the isolation layer 22 and the guard ring 20. When the stress is concentrated between the isolation layer 22 and the guard ring 20, a leakage current may easily flow through a stress concentration point. In the case of fabricating the Schottky diode in accordance with the first prior art, it may be difficult to control the interval between the isolation layer 22 and the guard ring 20, large variation in a leakage current value may occur according to dies/wafers or dies/lots.
Furthermore, as indicated by reference numeral B of FIG. 1, which illustrates the Schottky diode in accordance with the first prior art, and the graph of FIG. 2B which illustrates a reverse bias current (that is, a leakage current) according to dies on a wafer, the guard ring 20 includes the first impurity region 19 having an impurity doping concentration very higher than that of the deep well 12, the leakage current due to the big difference between the impurity doping concentrations of the deep well 12 and the first impurity region 19 may occur. In relation to the leakage current, large variation in the leakage current value may occur according to dies/wafers. In addition, due to the big difference between the impurity doping concentrations of the deep well 12 and the first impurity region 19, a breakdown voltage of the Schottky diode, that is, the ability of withstanding a high voltage (or a high current) may be reduced. For reference, (A) of FIG. 2B is a diagram illustrating the position of dies on a wafer and (B) of FIG. 2B is a current-voltage graph illustrating a leakage current generated in each die when a reverse bias is applied to the Schottky diode in accordance with the first prior art.
In order to solve the above problems in accordance with the first prior art, a Schottky diode in accordance with a second prior art has been proposed.
FIG. 3 is a cross-sectional view illustrating the Schottky diode in accordance with the second prior art.
Hereinafter, the Schottky diode in accordance with the second prior art will be described with reference to FIG. 3. The Schottky diode includes an N type deep well 32 formed in a substrate 31, an isolation layer 42 formed in the substrate 31, an N well 36, a cathode electrode 37 coupled to the well 36, a P well 40, and an anode electrode 41 coupled to the deep well 32 and the P well 40. The N well 36 is formed in the deep well 32 and is located at the right side of the isolation layer 42. The P well 40 is formed in the deep well 32 and is located at the left side of the isolation layer 42 while being in contact with the N well 36 and the isolation layer 42. The P well 40 serves as a guard ring, and has an impurity doping concentration lower than that of the first impurity region 19 in accordance with the first prior art.
In accordance with the second prior art, as compared with the first prior art, stress is not concentrated between the isolation layer 42 and the P well 40 serving as the guard ring because the isolation layer 42 is in contact with the P well 40 (see reference numeral A of FIG. 3 and FIG. 4A), and the generation of a leakage current due to the big difference between the impurity doping concentrations of the deep well 32 and the P well 40 may be reduced because the P well 40 has an impurity doping concentration lower than that of the guard ring 20 in accordance with the first prior art. For reference, FIG. 4A is a simulation image illustrating stress concentration between the isolation layer and the guard ring, and is a comparison image of the first prior art and the second prior art.
However, in the Schottky diode in accordance with the second prior art, as shown in reference numeral C of FIG. 3 and FIG. 4A, stress is concentrated at the boundary surface of the N well 36 and the P well 40, resulting in the reduction of the breakdown voltage of the Schottky diode. For reference, FIG. 4B is a current-voltage graph illustrating a comparison of the breakdown voltage of the Schottky diode in accordance with the first prior art and the breakdown voltage of the Schottky diode in accordance with the second prior art. Referring to FIG. 4B, it may be understood that the breakdown voltage of the Schottky diode in accordance with the first prior art is approximately 25.3 V, but the breakdown voltage of the Schottky diode in accordance with the second prior art is reduced to approximately 21.6 V.
Furthermore, in accordance with the second prior art, as shown in reference numeral B of FIG. 3 and FIGS. 4C and 4D, since the P well 40 serving as the guard ring is coupled to the N well 36 coupled to the cathode electrode 37, the current path from the anode electrode 41 to the cathode electrode 37 is increased (or lengthened) as compared with the first prior art, resulting in the deterioration of the forward characteristics of the Schottky diode. For reference, FIG. 4C is an image illustrating a comparison of the current path of the Schottky diode in accordance with the first prior art and the current path of the Schottky diode in accordance with the second prior art. FIG. 4D is a current-voltage graph illustrating the forward characteristics of the Schottky diode in accordance with the first prior art and the Schottky diode in accordance with the second prior art.
In brief, it is necessary to provide a Schottky diode capable of ensuring forward characteristics, leakage current characteristics, and breakdown voltage characteristics and simultaneously achieving uniform characteristics according to dies/wafers, and a method for fabricating the same.
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