The present invention relates generally to methods for heat-treating semiconductor wafers, and more particularly to methods for heat-treating wafers to improve wafer flatness.
Many applications require heating or annealing of an object or workpiece. For example, in the manufacture of semiconductor chips such as microprocessors and other computer chips for example, a semiconductor wafer such as a silicon wafer is subjected to an ion implantation process, which introduces impurity atoms or dopants into a surface region of a device side of the wafer. The ion implantation process damages the crystal lattice structure of the surface region of the wafer, and leaves the implanted dopant atoms in interstitial sites where they are electrically inactive. In order to move the dopant atoms into substitutional sites in the lattice to render them electrically active, and to repair the damage to the crystal lattice structure that occurs during ion implantation, it is necessary to anneal the surface region of the device side of the wafer by heating it to a high temperature.
However, the high temperatures required to anneal the device side also tend to produce undesirable effects. Because the wafer is subject to high thermal and physical stresses, it can be easily distorted instead of remaining flat as desired. Flatness is one of the most critical wafer parameters, primarily because the process of photolithography is highly sensitive to local-site flatness, especially for deep submicron photolithography. The annealing process creates a wafer that is not entirely flat and this creates difficulties for subsequent lithography alignment and poor overlay accuracy results. Lithography alignment is critical because the mask pattern must be precisely transferred to the wafer from layer to layer. Since multiple masks are often used during patterning, any overlay misalignment contributes to the total placement tolerances between the different features of the wafer surface (overlay budget). A large overlay budget essentially reduces the circuit density, which limits device feature sizes, and therefore, IC performance.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method of heat-treating a semiconductor wafer to improve wafer flatness that avoids the wafer manufacturing problems associated with conventional wafer heat-treating methods.
USPTO Backgrounds
USPTO Backgrounds