1. Field of the Invention
The invention relates to a method for fabricating nanowire transistor, and more particularly to a method of forming two spacers between gate structure and source/drain structure of a nanowire transistor.
2. Description of the Prior Art
In the past four decades, semiconductor industries keep downscaling the size of MOSFETs in order to achieve the goals of high operation speed and high device density. However, the reduction of device size won't last forever. When transistor shrink into or below 30 nm regime, leakage current due to severe short channel effects and thin gate dielectric causes the increase of off-state power consumption, and consequently causes functionality failure. One-dimensional devices based on nanowires or nanotubes are considered the immediate successors to replace the traditional silicon technology with relatively low technological risk. Nanowire transistor, which has higher carrier mobility and can be further enhanced by quantum confinement effect, is one of the most promising devices. In addition, the control of gate to channel can also be improved by using high-k dielectric layers.
USPTO Backgrounds
USPTO Backgrounds