1. Field of the Invention
The invention relates to a delay fault test technique to be used for a semiconductor integrated circuit. More specifically, the present invention relates to a calculation apparatus for calculating delay fault test quality, a method for calculating the quality thereof, and a delay fault test pattern generation apparatus.
2. Description of the Related Art
In recent years, a delay fault has become worse in accordance with high performance and high frequency of a semiconductor integrated circuit (hereinafter referred to as a large scale integrated circuit [LSI]). Conventionally, in the case in which the LSI cannot operate normally at a prescribed test frequency, the cause is called a delay defect.
As to the most basic fault model corresponding to the delay fault (defect), there are a transition fault model and a path delay fault model. The former is the simplest delay fault model and is effective to detect a large delay fault (delay defect) inside the LSI. The transition fault is assumed as slow-to-rise or slow-to-fall fault at an input and output terminal of a connection net or a basic cell inside a target LSI. The former has practical advantages that it simply comes out by a simple expansion of a stuck-at fault model and it may treat the delay faults in a comprehensive manner. On the contrary, the latter assumes the delay fault in each logical path in the target LSI, although it has an advantage capable of detecting distributed delays on the logical paths, the number of the logical paths becomes huge, and also a large number of redundant paths exist therein. Therefore, there are problems such that, in many case, applying a test pattern poses an extremely low value of a fault coverage, namely the number of tested logical paths/the number of all logical paths, and it is very hard to estimate the degree of the delay fault test quality. Because of such a reason, in general, the transition fault model has been widely used.
However, with respect to an LSI to be manufactured in recent fine process, physical defects which cause fine ((very) small) delays increase in number, so that a generation of a test pattern corresponding to a conventional generic transition fault model cannot sufficiently detect a physical defect causing a fine delay fault. Accordingly, the situation in which the delay fault is exposed after the shipment of the LSI has become worse.
Therefore, to detect the physical defect causing a fine delay fault, many proposals have been presented. A representative proposal generates a test pattern so as to detect the physical defect causing a fine delay fault by a logical path almost the longest path as much as possible on the basis of the transition fault model capable of detecting the defect in a comprehensive manner. However, this proposal is an effort to detect further many physical defects causing a fine delay fault, does not answer a question that the delay fault test quality of the test pattern, which has been actually obtained as a result, is to which degree, so that a suitable quality index is desired.
With respect to the estimation of the delay fault test quality, a variety of proposals have been presented. Especially, in a patent document 1 (e.g., Jpn. Pat. Appln. KOKAI No. 2005-257654), the proposal put together into one quality index from a comprehensive point of view. That is, in patent document 1, the proposal calculates the delay fault test quality with high precision, based on the delay fault coverage, and delay (timing) design information (e.g., static timing analysis information) of the target LSI, test timing precision (test frequency) information of a test pattern applied to the target LSI, and common delay defect distribution information. In the case of patent document 1, there is a large advantage in that an experimental question that an occurrence rate of delay faults is low in some products, and high in other products even with the same delay fault coverage may be explained reasonably, and it has found a course capable of estimating an actual market delay fault (defect) rate level with high precision.
A patent document 2 (e.g., Jpn. Pat. Appln. KOKAI Publication No. 2004-251895) proposes to estimate the delay fault test quality with high precision by adding layout information to the delay fault.
In another point of view, as to enhancing precision of a fault model, in a non-patent document (e.g., Zhuo Li, et al., “A Circuit Level Fault Model for Resistive Opens and Bridges”, Session 11 B-1, VTS 2003, 2003.), the quality improvement of generation of the delay fault test is confirmed by modeling a resistive defect that is a main cause of the delay fault in a circuit level.
However, patent document 1 only proposes an indirect method, such as a method for directly obtaining through a test element group (TEG) measurement (hard in reality) and a method for estimating by evaluating a large number of samples of target products (obtaining optimum solutions of the target products is delayed, and hard to develop the estimation result for other products), in a manner how to obtain a delay fault distribution that is the start point of a measure (metric) of the delay fault test quality. While patent document 1 assumes one kind of the delay defect distribution, (as disclosed in this patent specification), in an actual product the delay defect distribution of each delay fault differ much from that of the other, patent document 1 does not clearly describe a method for reasonably obtaining the way that which distributions should be employed, and then, it has not sufficiently disclosed the point to estimate the delay fault test quality of may products with high precision. In other words, although patent document 1 specifies that a direct distribution of delay defects (faults) is extracted from the common TEG, and the delay fault test quality is calculated on the basis of the extracted distribution, there is some doubt whether or not the delay defect distribution extracted from the common TEG can be applied as delay defect distributions of individual products as it is. The delay defect itself is expressed by abnormalities of further direct and common physical parameters (resistance [R] and capacitance [C]), and the parameters deeply depend on the unique layout of the product.
In patent document 2, since the weight to be added to the delay fault has not accurately responded to layout element information, there is every possibility that an appropriate delay defect distribution cannot be obtained. Although non-patent document 1 takes resistive faults into account, it does not reach the idea of combining the resistive faults with the physical defect distributions of the individual layout elements.
USPTO Backgrounds
USPTO Backgrounds