Often integrated circuit devices include circuits that operate in different voltage domains. For example, the core logic of a data processing integrated circuit may operate in a voltage domain that is suitable for the given overall circuit design scheme or fabrication process being implemented, while the associated input and output circuits may operate in another voltage domain, as required to maintain compatibility with corresponding external devices and systems. In such integrated circuits, voltage level shifters are required to translate signals from the voltage swing utilized in one voltage domain to the voltage swing utilized in another voltage domain as those signals cross voltage domain boundaries.
Disadvantageously, voltage level shifters introduce signal path delay, which can directly impact overall system performance, especially when those voltage level shifters are required in critical timing paths. For example, in a typical serial data port, commonly used in analog to digital converters (ADCs), the bits of a serial data (SDATA) stream are output on the falling edges of an associated serial clock (SCLK) signal, which, in the slave (asynchronous) mode, is provided by the destination device receiving the SDATA stream. Each bit of serial data output from the source device on the falling edge of the SCLK signal is latched on the next rising edge of the SCLK signal by the destination device. Hence, minimizing the delay between the receipt of the falling edge of the SCLK signal at the source device and the resulting output of the corresponding SDATA bit is critical, since sufficient time must be provided between the output of the SDATA bit by the source device and the following rising edge of the SCLK signal to allow for set-up at the destination device. When voltage level shifters are included in the SCLK signal path and/or the SDATA data path, the timing margins are reduced, which in turn limits the maximum frequency of the SCLK signal.
Given the utility of integrated circuits that include circuits operating in different voltage domains, techniques are required for minimizing the impact on system performance caused voltage level shifters delays. In particular, these techniques should provide for improved performance in multiple voltage domain integrated circuits operating in response to high frequency clock signals, such as those utilized in serial data ports.
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