The present invention relates to a circuit for detecting a valid range of a video signal, which may be used in a display apparatus of a personal computer (PC) and the like.
Video signals utilized in PCs have signal formats of various numbers of scan lines, picture elements and frame frequencies. Further, a video signal has a valid range (a range of time during which the video signal is displayed on a display screen), which is located at various positions within the video signal. Accordingly, for purpose of providing an image display, it is required that a location that an input signal should occupy on a display screen be adjusted in accordance with the signal format of the input signal. Measures are taken to allow the valid range of the video signal to be detected automatically so that a portion of the video signal that is contained within the valid range may be displayed on a display screen at an appropriate position.
FIG. 11 is a block diagram showing a display apparatus using a conventional circuit for detecting a valid range of a video signal. In FIG. 11, a reference numeral 1 denotes an A/D converter which converts a video signal into a digital signal, and 2 denotes a PLL circuit which generates from a horizontal sync signal H1 a dot clock and a horizontal reference signal, both of which are used in an internal processing. Further, a reference numeral 4 denotes an address generator which generates a horizontal address signal H2 and a vertical address signal V2 on the basis of the horizontal reference signal and a vertical sync signal V1, and 5 denotes a valid range detector which detects a valid range of a video signal. The address generator 4 and the valid range detector 5 form together a circuit 6 for detecting a valid range of a video signal. In FIG. 11, a reference numeral 7 denotes a display unit, which has a display screen and displays the video signal on the display screen in accordance with a horizontal address signal H2, a vertical address signal V2 and an output signal from the valid range detector 5. For ease of description, it is assumed in the description to follow that the display screen of the display unit 7 is a matrix display device having eight horizontal rows and four vertical columns or a total of 32 (=8xc3x974) picture elements. The display screen may be any one of a liquid crystal panel, a PDP (plasma display panel) a DMD (digital micro-mirror device) and the like.
The operation of the conventional circuit shown in FIG. 11 will be described below with reference to a series of timing charts shown in FIGS. 12A to 12J. FIGS. 12A and 12F show a video signal S1 which is input, FIG. 12B shows a vertical sync signal V1 which is input, FIGS. 12C and 12G show a horizontal sync signal H1 which is input, FIGS. 12D and 12H show a vertical address signal V2 which is output from the address generator 4, FIGS. 12E and 12J show a valid range detection flag signal F1 which is used in the internal processing performed by the valid range detector 5, and FIG. 12I shows a horizontal address signal H2. FIGS. 12F to 12J show part of FIGS. 12A to 12E in enlarged scale in time. In the description to follow, it is assumed that the horizontal sync signal H1 and the vertical sync signal V1 which are input are negative-polarity pulses, as shown in FIGS. 12B and 12C, respectively, having a falling edge as a Leading edge and a rising edge as a trailing edge.
The video signal S1 shown in FIGS. 12A and 12F is input to the A/D converter 1. The A/D converter 1 then converts it into a digital signal, which is sent to the valid range detector 5 and the display unit 7.
The PLL circuit 2 produces a dot clock. The PLL circuit 2 produces a horizontal reference signal by frequency-dividing the dot clock, and controls the dot clock frequency so that the falling edge of the horizontal reference signal coincides with the falling edge of the horizontal sync signal H1 shown in FIGS. 12C and 12G. The horizontal sync signal H1 and the horizontal reference signal are generally substantially aligned in their falling edges, but the horizontal reference signal that is in complete synchronization with the dot clock is used in the internal processing.
The address generator 4 generates the vertical address signal V2 by means of a counter which is reset by the falling edge of the vertical sync signal V1 and which is incremented by one by the falling edge of the horizontal reference signal (which coincides with the falling edge of the horizontal sync signal H1), in a manner shown in FIG. 12D. Simultaneously, the address generator 4 generates the horizontal address signal H2 by means of a counter which is reset by the falling edge of the horizontal reference signal and which is incremented by one by the dot clock, in a manner shown in FIG. 12I. The horizontal address signal H2 and the vertical address signal V2 are used by the valid range detector 5 and the display unit 7 as address information which indicates horizontal and vertical positions on the display screen.
The valid range detector 5 produces a valid range detection flag signal F1 (see FIGS. 12E and 12J), which has a high level when the video signal S1 is equal to or greater than a threshold TH and has a low level otherwise, on the basis of the comparison of the video signal S1 shown in a solid line and a predetermined threshold TH shown in a broken line in FIGS. 12A and 12F. The threshold TH is chosen to be equal to about one-eighth of a maximum amplitude of the video signal S1. The valid range detector 5 outputs a minimum value (or xe2x80x9c5xe2x80x9d shown in FIG. 12I) and a maximum value (or xe2x80x9c12xe2x80x9d shown in FIG. 12I) of the horizontal address signal H2 during the range of time the flag signal F1 has the high level to the display unit 7 as a left-end coordinate and a right-end coordinate, respectively. It also outputs a minimum value (or xe2x80x9c4xe2x80x9d in FIG. 12D) and a maximum value (or xe2x80x9c7xe2x80x9d in FIG. 12D) of the vertical address signal V2 during the range of time the flag signal F1 has the high level to the display unit 7 as an upper-end coordinate and a lower-end coordinate, respectively.
The display unit 7 displays the video signal S1 on the display screen at an appropriate position in accordance with left-end, right-end, upper-end and lower-end coordinates as input from the valid range detector 5, and the horizontal address signal H2 and the vertical address signal V2 which are input from the address generator 4. In the following description, values H and V of the horizontal address signal H2 and the vertical address signal V2 are denoted by (H,V) for purpose of convenience, wherein both H and V are positive integers.
By way of example, if the left-end coordinate is xe2x80x9c5xe2x80x9d, the right-end coordinate is xe2x80x9c12xe2x80x9d, the upper-end coordinate is xe2x80x9c4xe2x80x9d and the lower-end coordinate is xe2x80x9c7xe2x80x9d, the video signal which is input at a timing of (5,4) for the horizontal address signal H2 and the vertical address signal V2 is displayed on an upper-left picture element. The video signal which is input at a timing of (6,4) for the horizontal address signal H2 and the vertical address signal V2 will be displayed on a picture element which is located immediately to the right of the picture element, on which the video signal input at the timing of (5,4) has been displayed. A relationship between the position on the display screen and the values of the horizontal address signal H2 and the vertical address signal V2 is diagrammatically shown in FIG. 13.
In the above-described operation of the valid range detector 5, it is assumed that there is a video signal equal to or greater than the threshold at the left-end, right-end, upper-end and lower-end which collectively define the valid range, but this presents no problem for practical purposes inasmuch as a video signal is existing to the ends of the valid range of the video signal where an operating system having graphics user interface, which represents the main stream of recent versions of PCs, is used.
What has been described above is the arrangement of the conventional circuit for detecting a valid range of a video signal, and such arrangement suffers from the difficulty of properly detecting the valid range under the influence of a crosstalk noise which becomes mixed with the video signal on a cable which conveys the video signal.
An exemplary operation of the conventional circuit when a crosstalk noise CN from the horizontal sync signal H1 is mixed with the video signal will be described with reference to FIGS. 14A-14E.
FIG. 14A shows a behavior of the video signal S1 when a crosstalk noise CN from the horizontal sync signal H1 is mixed therewith. It is seen that a ringing noise occurs in response to a change in the horizontal sync signal H1. When such video signal S1 is input to the valid range detector 5, a portion of the crosstalk noise CN which exceeds the threshold TH will be detected as representing the valid range, and accordingly, the flag signal F1 which indicates the detection of the valid range behaves in a manner shown in FIG. 14E. Hence, the minimum value of the horizontal address signal H2 during the time the flag signal F1 has the high level occurs as xe2x80x9c1xe2x80x9d, as indicated in FIG. 14D, which is as much as four picture elements displaced to the left of the correct value of xe2x80x9c5xe2x80x9d for the left-end coordinate. Accordingly, because the display unit 7 displays the picture element at the wrong left-end coordinate at the leftmost position, thereby resulting a display as illustrated in FIG. 15. In FIG. 15, picture elements, which are located in the leftmost four columns that are delineated by broken lines, represent a picture during the non-valid range of time.
It will be seen from the foregoing that the conventional circuit as described above fails to detect a valid range correctly to cause an offset in the display position on the display screen where a crosstalk noise CN exists as on a cable, through which the video signal S1 is transmitted, by superimposing a change in the sync signal upon the video signal.
It is an object of the present invention to provide a circuit for detecting a valid range of a video signal capable of correctly detecting a valid range of a video signal in the presence of a crosstalk noise which may result from the superimposition of a change in the sync signal upon a video signal on a cable.
According to the present invention, a circuit detects a valid range of a video signal on the basis of a vertical sync signal which has a first period and has a first level only during a first range of time and a second level otherwise, a horizontal sync signal which has a second period and has a third level only during a second range of time and a fourth level otherwise, and the video signal, the valid range being a range of time of the video signal which is to be displayed on a display screen. The circuit comprises a detection window signal generator for generating a detection region window signal which has a fifth level during at least one of a first detection disable range of time of a predetermined length and a second detection disable range of time of a predetermined length, and has a sixth level otherwise, the first detection disable range of time containing a point of time when the vertical sync signal changes its level, the second detection disable range of time containing a point of time when the horizontal sync signal changes its level; and a valid range detector for detecting the valid range, during which the video signal has a level equal to or greater than a predetermined threshold and the detection region window signal has the sixth level.
According to another aspect of the present invention, a circuit detects a valid range of a video signal on the basis of a vertical sync signal which has a first period and has a first level only during a first range of time and a second level otherwise, a horizontal sync signal which has a second period and has a third level only during a second range of time and a fourth level otherwise, and the video signal, the valid range being a range of time of the video signal which is to be displayed on a display screen. The circuit comprises: a detection window signal generator for generating a detection region window signal which has a fifth level during at least one of a first detection disable range of time of a predetermined length and a second detection disable range of time of a predetermined length, and has a sixth level otherwise, the first detection disable range containing a point of time when the vertical sync signal changes its level, the second detection disable range of time containing a point of time when the horizontal sync signal changes its level; a gate for allowing the video signal to pass therethrough when the detection region window signal has the sixth level and for outputting a zero-level signal as the video signal when the detection region window signal has the fifth level; and a valid range detector for detecting the valid range, during which an output of the gate has a level equal to or greater than a predetermined threshold.
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