As DC-DC converters are scaled to the next generation of power converter products, there is a need to increase the switching frequency to reduce the size of the external passive components such as inductors while maintaining low power dissipation in its integrated power field effect transistors (FETs), such as LDMOS devices. In an LDMOS device, the drain is laterally arranged to allow current to laterally flow, and a drift region is interposed between the channel and the drain to provide a high drain to source breakdown voltage. Increasing the switching frequency involves reducing the diode reverse recovery (Drr) time of the power FET.
Drr is a function of reverse recovery charge (Qrr) which is the amount of minority carrier charge stored in the body region of a power FET during commutation. Commutation is when an inductive converter load is forcing current into the body diode of the power FET, for an n-channel power FET resulting in the p-type body region being flooded with minority carriers (electrons). The diode recovery current's time integral is Qrr. High Qrr can cause a variety of problems, including (1) activating parasitic body NPN bipolar paths during drain voltage ramps, which can cause power dissipation or in an extreme case thermal failure of the power FET and (2) body diode induced current dissipation which can result in reduced efficiency of the switching circuit.
Conventional power LDMOS devices are n-channel devices that employ p-type body regions having a fairly uniform doping profile in the vertical direction. Some of the body doping generally comes from the p-type epitaxial silicon, which has essentially uniform boron doping. Additional p-type body doping can come from a high energy (near-MeV or MeV) p-type (e.g., boron) buried layer (PBL) implant that is subject to subsequent high temperature furnace processing, and as a result diffuses the as-implanted largely Gaussian boron dopant profile in the vertical direction so that the variation in p-type doping across the LDMOS body region in the vertical direction is substantially gradual. For example, for known LDMOS devices the p-body region may be 4 μm deep and have at most a 12 times (×) doping variation from the top (silicon surface) to bottom of the body region that is distributed in an essentially constant vertical dopant concentration gradient. The essentially constant vertical dopant concentration gradient is typically about 2× to 3×/μm at most where being above the doping level of the p-epi region through any 0.5 μm or more wide region of the body.
USPTO Backgrounds
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