1. Field of the General Inventive Concept
The present general inventive concept relates to a flip-flop, a frequency divider, and a radio frequency (RF) circuit, and more particularly, to a flip-flop, a frequency divider, and a radio frequency (RF) circuit that support a multi-band signal.
2. Description of the Related Art
In general, a wireless communication system includes a digital or analog baseband circuit that processes information such as actual voice sound, audio data, video data, etc., and radio frequency (RF) circuit processing signals that are transmitted and received with high frequency. As is well known in the art, the baseband circuit and the RF circuit may be separately realized using chips, respectively, wherein the RF circuit converts baseband signals provided by the baseband circuit into high frequency RF signals. A conventional RF circuit to support a multi-band signal will be described with respect to FIGS. 1 and 2.
FIG. 1 is a block diagram illustrating an example of a conventional RF circuit 10. As illustrated in FIG. 1, the conventional RF circuit 10 requires various RF dividers to support a multi-band signal.
The conventional RF circuit 10 of FIG. 1 receives a baseband signal B/B Sig generated in a baseband circuit (not illustrated) and converts the baseband signal B/B Sig to a high frequency RF signal. The conventional RF signal 10 includes a phase locked loop (PLL) 11 that receives a reference clock signal CLK and outputs an oscillation signal fo, which may be a high frequency oscillation signal, and at least one frequency divider. The at least one frequency divider may be a first frequency divider 12 and a second frequency divider 13 which are serially connected to each other. For example, the first frequency divider 12 and the second frequency divider 13 may respectively be divide-by-two frequency dividers that divide a frequency of an input signal by two and output the signal with the divided frequency. Also, the conventional RF circuit 10 may include a first drive circuit 14 generating a low band signal LB to support the frequency band of about 800-900 MHz and a second drive circuit 15 generating a high band signal HB to support the frequency band of about 1700-1900 MHz.
In the conventional RF circuit 10 of FIG. 1, the oscillation signal fo passes through the first frequency divider 12 and the second frequency divider 13 which are serially connected to each other, and thus the frequency of the oscillation signal fo is converted to fo/2 or fo/4. The oscillation signal having its frequency converted to fo/4 is provided to the first drive circuit 14 to generate a low band signal LB, and the oscillation signal having its frequency converted to fo/2 is provided to the second drive circuit 15 to generate a high band signal HB. The first drive circuit 14 generates the low band signal LB by mixing the oscillation signal having its frequency converted to fo/4 with a baseband signal B/B Sig. Also, the second drive circuit 15 generates the high band signal HB by mixing the oscillation signal having its frequency converted to fo/2 with a baseband signal B/B Sig.
The conventional RF circuit 10 generates a fo/2 frequency signal and a fo/4 frequency signal using two divide-by-two frequency dividers that may be generally realized using two flip-flops. That is, only two divide-by-two frequency dividers that are serially connected to each other are included in the conventional RF circuit 10, and thus the number of flip-flops is reduced accordingly, and the surface area of chips can be reduced and the load capacitance at the output of the PLL 11 can be reduced. However, when generating a frequency signal fo/4, to generate a low band signal, division processes are performed twice by the divide-by-two frequency dividers, and thus out-band phase noise is decreased compared to a case where only one division process is performed using a divide-by-four frequency divider.
In general, a close-in phase noise of an operational frequency of a frequency divider is very small compared to an oscillation signal fo, and thus noise caused by the frequency divider may be neglected. However, it is difficult to maintain out-band phase noise, which is far away from the operational frequency, to be smaller than the phase noise of the oscillation signal fo. Accordingly, the out-band phase noise needs to be maintained small in order to support a multi-band signal.
FIG. 2 is a block diagram illustrating another conventional RF circuit 20. As illustrated in FIG. 2, the conventional RF circuit 20 includes a PLL 21 outputting an oscillation signal fo, which may be a high frequency oscillation signal, and at least one frequency divider. The at least one frequency divider may be a first frequency divider 22 and a second frequency divider 23 that are connected parallel to each other. For example, the first frequency divider 22 may be a divide-by-four frequency divider that divides a frequency of an input signal by four and outputs the signal with the divided frequency, and the second frequency divider 23 may be a divide-by-two frequency divider that divides a frequency of an input signal by two and outputs the signal with the divided frequency. Also, the conventional RF circuit 20 may include a first drive circuit 24 generating a low band signal LB and a second drive circuit 25 generating a high band signal HB.
As illustrated in FIG. 2, the first frequency divider 22 receives an oscillation signal fo and converts its frequency to fo/4, and provides the oscillation signal having its frequency converted to fo/4 to the first drive circuit 24. Also, the second frequency divider 23 receives an oscillation signal fo and converts its frequency to fo/2, and provides the oscillation signal having its frequency converted to fo/2 to the second drive circuit 25. The first drive circuit 24 mixes the oscillation signal having its frequency converted to fo/4 with a baseband signal B/B Sig to generate a low band signal LB. Also, the second drive circuit 25 mixes the oscillation signal having its frequency converted to fo/2 with a baseband signal B/B Sig to generate a high band signal HB.
The conventional RF circuit 20 of FIG. 2 generates a fo/2 frequency signal and a fo/4 frequency signal using a divide-by-two frequency divider and a divide-by-four frequency divider that may be generally realized using two flip-flops, respectively. Unlike in FIG. 1, the conventional RF circuit 20 uses individual frequency dividers for each band, and thus the out-band phase noise can be reduced. Also, in the conventional RF circuit 20, the divide-by-four frequency divider is activated to generate the low band signal LB and operates at a frequency fo/4, and thus the power consumption can be reduced compared to when the first frequency divider 12 of FIG. 1 operates at a frequency fo/2.
However, the divide-by-four frequency divider is generally realized using four flip-flops, and thus the number of flip-flops is increased compared to the case of FIG. 1, which is disadvantageous in terms of reducing the surface area of the chips. Also, in terms of the output of the PLL 11, two frequency dividers are arranged parallel and thus the load capacitance is increased.
USPTO Backgrounds
USPTO Backgrounds