1. Field of the Invention
The present invention relates to the field of computer systems, and more particularly, to a cache structure and a cache management method of a processor.
2. Description of the Related Art
In general, a computer system includes a processor and memory. In many cases, the operation speed of the processor exceeds the operation speed of the memory. This is due to the fact that high-speed memory is expensive and thus not abundant in most computer systems.
Referring to FIG. 1, most computer systems have a hierarchical memory structure including high-speed memory such as cache memories 12 and 14, middle-speed memory such as a main memory 16, and low-speed memory such as a hard disk 18. Since the cost of memory decreases as its operation speed decreases, most computer systems are equipped with a large amount of low- and medium-speed memory in order to increase the total memory capacity of the system without greatly increasing the system's cost.
The cache memories 12 and 14 themselves represent a hierarchical structure. Cache memory 12 is an on-chip cache included inside a processor chip 10, and cache memory 14 is an off-chip cache located outside the processor chip 10. The on-chip cache 12 is generally called a first cache or L1 cache and the off-chip cache 14 is called a second cache or L2 cache.
The cache memories 12 and 14 store instructions and/or data from the main memory 16. A cache lookup operation, in which instructions and/or data that the processor 10 desires are searched for, is firstly performed in the first cache memory 12. If the desired instructions and/or data are not found in the first cache memory 12, that is, if a cache miss occurs, a lower level of memory such as the second cache memory 14 or the main memory 16 is searched for the instructions and/or data. Once the instructions and/or data are found, they are stored in the first cache memory 12.
The processor 10 is often required to process exception programs such as an interrupt process routine, an exception process routine, a reset process routine or the like while running a normal program. When this occurs, the processor 10 temporarily stops the normal program to run the exception program and then goes back to running the normal program. In doing so, the instructions and/or data required by the processor 10 change back and forth, and instructions and/or data not needed at a particular time are often deleted from the first cache memory 12. Subsequently, when deleted instructions and/or data are needed again but found absent in the first cache memory 12, the second cache memory 14, and sometimes the lower level memories, must be searched, creating a delay. This delay decreases the response speed of the processor 10 to the exception programs and generally inhibits high-speed operation of the processor 10.
USPTO Backgrounds
USPTO Backgrounds