1. Field of the Invention
The embodiments of the invention generally relate to dynamic random access memory (DRAM) circuits and, more particularly, to a DRAM circuit with a reference cell having two trench capacitors connected in series as well as a design structure for such a circuit and an associated method of forming such a circuit.
2. Description of the Related Art
Ground sensing or VDD sensing schemes of DRAM circuits (e.g., embedded DRAM (eDRAM) circuits) provide many advantages in improving memory performance. However, such sensing schemes require a unique reference cell for providing a reference voltage for sensing. A conventional reference cell in a DRAM circuit comprises two access transistors and a single capacitor. The capacitor in the reference cell is exactly the same as the capacitor in the memory cell. Therefore, in order to differentiate reference cell data from the memory cell data and provide a reference voltage, the reference cell requires a particular power supply voltage, VREF. VREF should provide a large amount of current and be very stable during high frequency operation. However, as the operation frequency of DRAM circuits and of eDRAM circuits in particular increases, it is becoming more and more difficult to provide a stable, high current, VREF to the reference cell capacitor. Consequently, using VREF as a sensing reference creates lot of noise and degrades sensing operation and memory performance. Therefore, there is a need in the art for a DRAM circuit reference cell that uses an alternative means for providing a sensing reference.
USPTO Backgrounds
USPTO Backgrounds