In a conventional network system, an interconnection of data communications devices transmits message traffic between users. Such conventional data communications devices perform switching of message traffic to transport the message traffic from a source node to a destination node. Conventional message traffic typically includes a series of packets, each containing a source and destination address, corresponding to the source and destination nodes, respectively. Switching engines in conventional data communications devices read the address information in the packets, and switch the packets to an outgoing line corresponding to the destination node.
In such a conventional network, multiple data communications devices transmit a message packet between the source node and the destination node, in a series of “hops” along the interconnections. In such conventional data communications devices, the switching engines typically transport many packets corresponding to many different source and destination nodes. Accordingly, fast switching of the message packets is desirable to maintain message packet throughput, while minimizing the number of switching engines which the network employs for transporting the message traffic through the network.
Accordingly, conventional switching engines typically employ high-speed memory and processing circuits between a plurality of ingress and egress ports. The physical network interconnections connect to the ingress and egress ports, each of which in turn, connect to other data communications devices having conventional switching engines, or to the end-user nodes themselves. Therefore, the high-speed memory and processing control circuits in conventional switching engines switch the packets from the ingress ports onto the egress ports at a rate such that the switching engines avoid a bottleneck of message traffic.
Accordingly, such conventional switching engines employ a scheduler to facilitate message throughput through the data communications device. Such a scheduler manipulates the pending (queued) entries corresponding to message packets via a predetermined algorithm that quickly reads and interprets the address and other information in the packets. The scheduler then makes determinations, using the predetermined algorithm, concerning which message packets to transmit next on the egress ports. In this manner, a conventional scheduler prioritizes message traffic according to a variety of factors, such as packet address information, readable by such a conventional predetermined algorithm, in order to determine which packets to transmit and on which egress ports.
Conventional schedulers employ a variety of memory resources, data structures, and switching logic components to manipulate and manage the message packet throughput. Typically, the data structures include queues which store and order the message traffic according to scheduling logic. The scheduling logic orders and prioritizes the message traffic to determine the outgoing transmission order of the message traffic. Typically, service levels encompassing throughput rates, QOS (quality of service) minimums, rate limit maximums, and usage window guidelines are selectable by users, usually according to a fee based contractual obligation. Therefore, a service provider requires optimal queuing and servicing of message traffic according to the contractual obligations, as failure to maintain an agreed upon service level may have substantial repercussions for the service provider.
USPTO Backgrounds
USPTO Backgrounds