The present invention relates generally to semiconductor integrated circuit (IC) devices configured using metal oxide semiconductor (MOS) transistors, and more particularly to a semiconductor IC device which employs specific MOS transistors with a gate insulation film thin enough to permit flow of tunnel current therein and which is adaptable for use with low-power circuitry operable with low voltages of 2 volts or less.
One prior known semiconductor integrated circuit device employing highly miniaturized MOS transistors fabricated by microelectronics fabrication technology is disclosed, for example, in a paper entitled xe2x80x9cLimitation of CMOS Supply-Voltage Scaling by MOSFET Threshold-Voltage Variation,xe2x80x9d 1994 Custom Integrated Circuit Conference (CICC), pp. 267-270. This paper also teaches the correlation of the transistor threshold value versus flow of leakage current during standby periods.
Currently available standard MOS transistors are typically designed to operate with a gate voltage of from 1.8 to 2.5 volts (so-called the xe2x80x9cgate-to-sourcexe2x80x9d voltage which is normally equivalent to the power supply voltage) while making use of a gate insulation film ranging from 5 to 6 nanometers (nm) in thickness. Generally, as the integration density of MOS transistors increases, the transistor size decreases, and the thickness of the gate insulation film decreases accordingly. The present inventors Presently predict that MOS-IC devices of the next generation will require use of further miniaturized MOS transistors operable with a gate voltage of 2 volts or less while reducing the thickness of gate insulation film down at 4 nm or less.
Principally, it may be considered that the operation speed of MOS transistors remains inversely proportional to the gate insulation film thickness decreasesxe2x80x94that is, as this thickness decreases, the MOS transistor speed increases. However, this does not come without accompanying a xe2x80x9ctrade-offxe2x80x9d penalty: When the MOS gate insulation film becomes too thinner, a tunnel current begins flowing therethrough. This can result in an increase in leakage current (tunnel leakage current), such as a source-to-gate current or drain-to-gate current, which inherently does never take place in standard MOS transistors. Such increase in tunnel leakage current in turn leads to an increase in power dissipation of MOS transistors during standby periods thereof. In the description such dielectric films permitting tunnel current leakage will be referred to as the xe2x80x9cthinxe2x80x9d gate insulation film; likewise, certain MOS transistors employing such dielectric film will be called the xe2x80x9cthin-filmxe2x80x9d MOS transistors hereinafter. On the contrary, standard MOS transistors in which such tunnel leakage current does not flow will be referred to as the xe2x80x9cthick-filmxe2x80x9d MOS transistors. The xe2x80x9ctunnel current leakagexe2x80x9d problem has been also discussed in the monthly journal titled xe2x80x9cSemiconductor World,xe2x80x9d July 1995 at pp. 80-94; unfortunately, this is completely silent about any ideas for solving this problem.
A mechanism of an increase in power dissipation during standby due to tunnel current will be discussed more precisely in conjunction with the graphs shown in FIG. 10.
See FIG. 10(a). This is a graphical representation showing experimental results concerning the drain voltage versus drain current characteristics of one thick-film MOS transistor. Plotting experimental data in this graph assumes that its gate oxide film measures approximately 6 nm in thickness. Since the oxide film employed herein is thick enough to render negligible the tunnel leakage current which can flow between the gate and source or between the gate and drain.
See FIG. 10(b), which presents the drain-voltage/drain-current characteristics of a thin-film MOS transistor. This assumes that a gate oxide film used is 3.5 nm in thickness. Since the oxide film is thin, leakage current can flow between the gate and source and also between the gate and drain thereof. Accordingly, even where the drain voltage is at zero volts, a non-negligible amount of current flows between the gate and drain when its gate voltage is not zero volts. In the graph of FIG. 10(b), a drain current of 0.5 milliamperes (mA) or more or less was derived when the gate voltage is 2.0 volts.
In complementary MOS (CMOS) circuitry configured using thick-film MOS transistors, since gate leakage current remains negligible in amount, any constant current (DC current) will by no means flow insofar as leakage current is absent between the source and drain. On the contrary, with CMOS circuitry employing thin-film MOS transistors, gate leakage current does flow so that constant current (DC current) flows accordingly. This means that some power dissipation arises even where the circuitry is inoperative.
See FIG. 11, which shows the relation of the thickness of gate insulation film versus gate leakage current. Even when the gate voltage is at 2 to 3 volts or around it, if the gate insulation film is 6 nm or greater in thickness, then any resultant tunnel current remains harmless in practical applications. On the other hand, it may be seen by those skilled in the art that even if the gate voltage is potentially decreased to range from 2 to 1.5 volts which may be lower than ever, the leakage current will no longer remain negligible in magnitude once after the thickness of gate insulation film is reduced at approximately 3 nm. Presumably, if the gate voltage is 2 volts or more or less, then the boundary exists at a 4-nm range of gate insulation film thickness or around it. According to the teachings of the Semiconductor World document, it has been pointed out that the tunnel effect in quantum theory takes place with a 5-nm gate insulation film point being as the criticality. This document also teaches that a remarkable tunnel current can occur not only when the gate insulation film is as thin as 1.5 nm but also when it falls within a range of from 3 to 3.5 nm. As can be seen from the graph of FIG. 11, while the gate voltage tends to be lowered for reduction in power dissipation; even in this situation, when the gate insulation film becomes thinner to decrease from 2.9 to 2.0 nm in thickness, large leakage current begins flowing even upon application of a gate voltage of 1 volt or below. Additionally, it is currently presumed that a minimal thickness of gate insulation films capable of retaining the nature of silicon oxide is about 10 angstroms.
Another approach is known which suppresses a sub-threshold source-to-drain leakage current by potentially raising the threshold value of MOS transistors. However, even with use of such approach, it stays impossible in principle to reduce standby power dissipation due to the flow of source-to-gate tunnel current.
While the gate leakage current (tunnel current) might be under control by increasing the thickness of gate insulation films to reduce standby power dissipation involved, this does not come without accompanying a penalty: As discussed supra, if such MOS transistors are employed for circuitry then operation speed decreases making it impossible or at least greatly difficult to attain any desired performance.
It is therefore an object of the present invention to provide a semiconductor integrated circuit device capable of reducing standby power dissipation without having to degrading circuit operation speed.
In order to attain the foregoing object, the invention provides a low-power/high-performance semiconductor integrated circuit device by selective use of different kinds of MOS transistors including thick-film MOS transistors and thin-film MOS transistors, wherein the former is negligible in flow of tunnel leakage current whereas the latter is capable of operating at high speeds while accompanying the tunnel current leakage problem.
In accordance with the principles of the invention, there is provided a semiconductor integrated circuit device including on the same substrate a plurality of kinds of MOS transistors different in magnitude of a leakage current flowing either between the source and gate or between the drain and gate. The semiconductor integrated circuit device is configured to have main circuitry constituted from at least one MOS transistor of the plurality of kinds of MOS transistors being greater in leakage current, and control circuitry inserted between the main circuitry and at least one of two power supplies and comprised of at least one MOS transistor less in leakage current.
It should be noted that intended high-speed characteristics may be successfully accomplished by designing the MOS transistors such that the gate insulation film measures 3.5 nm or less in thickness: Also, rendering it thinner at 3.0 nm and further thinner at 2.0 nm or less may enable the operation speed to further increase. However, as the operation speed increases, tunnel leakage current will likewise increase in magnitude. In view of this, it may be desirable that the MOS transistors of reduced leakage current be specifically employed for interruption or interception of a standby voltage(s) as applied to the thin-film MOS transistors. Intended advantages may be sufficiently attained whenever the power-supply intercept MOS transistors measure 5.0 nm or greater in thickness; if extra high speed requirements are not required when reduction to practice, it may be permissible for them to measure 10.0 nm or greater.
These MOS transistors may be structured to offer any desired characteristics by suitably designing the thickness of gate insulation film or changing either carrier density or distribution at the gate electrode, drain and/or source electrode. Generally, increasing the gate insulation film thickness requires that the gate length increase in value accordingly.
In regard to the microelectronics fabrication process, the characteristic control or adjustment may become accurate when the two kinds ofxe2x80x94namely, thin-film and thick-filmxe2x80x94MOS transistors are manufactured such that the gate insulation films and gate electrodes thereof are formed at separate process steps. Especially, it will be recommendable that thick gate insulation films be formed prior to formation of thin gate insulation films because of the fact that the latter is difficult than the former in control of process parameters during fabrication. In addition, in cases where such two kinds of MOS transistors are formed separately, forming a protective dielectric film on resultant gate electrode layer may enable suppression or elimination of occurrence of gate-electrode degradation otherwise occurring due to execution of succeeding processes.
It should be noted here that in the semiconductor integrated circuit device in accordance with the instant invention, the thin-film MOS transistors are preferably selected for use with specific circuitry parts under strict requirements of high-speed characteristics, including, but not limited to, information signal processor circuits, such as logic function units (logic circuits such as NAND gates, NOR gates and the like) as built in central-processing units (CPUs), latch circuits, high-speed memory cell arrays, and others.
In contrast, switch elements for interruption of power supply during standby periods of these thin-film MOS transistors may be configured using thick-film MOS transistors, which function as the power-supply intersect transistors. Also, any circuitry parts without high-speed requirements as well as circuits under strict requirements of high voltage withstand characteristics may be configured by such thick-film MOS transistors. Memory cells with no high-speed requirements such as static random access memory (SRAM), dynamic RAM (DRAM), mask read-only memory (mask ROM) are one example. Protective circuitry as inserted for prevention of gate-insulation film dielectric breakdown is another example. Preferably, those of the thick-film MOS transistors which are to be applied with high voltages come with a specifically designed source/drain structurexe2x80x94that is, electric field relaxation structure including, but not limited to, a lightly-doped drain (LDD) structure.
It should be also noted that in cases where the semiconductor integrated circuit device of the invention is arranged as an IC chip, it will be recommendable that a level converter circuit for potential level conversion of electrical signals be built therein in order to xe2x80x9cabsorbxe2x80x9d any possible differences in potential level between incoming signals to the chip and outgoing ones from it. When this is done, it is desirable in view of reliability that thick-film MOS transistors be employed in certain circuit part for receiving high potential external signals whereas thin-film MOS transistors be in remaining circuit part for handling relatively low potential internal or xe2x80x9cin-chipxe2x80x9d signals.
The memory cells configured using thick-film MOS transistors may functionally include at least one of register files, cash memories, translation look-aside buffers (TLBs), and DRAM cells; if this is the case, it is preferable that the memory cells are arranged to store therein data during standby periods. The invention however should not be limited exclusively thereto and may alternatively be modified such that these include first kinds of memory cells of high access rate and second kind of ones lower in access rate than the former, wherein the MOS transistors constituting the first memory cells are greater in leakage current than those forming the second memory cells.
It should further be noted that upon interruption of the power supply of the thin-film MOS transistors by the power supply intercept transistor(s), it is possible by providing a level hold circuitxe2x80x94this may be configured using thin-film MOS transistors for retaining or holding the last potential level of an output of logic circuit operatively associated therewithxe2x80x94to eliminate any adverse influence or affection by power supply intercept of the thin-film MOS transistors. Preferably, such level hold circuit may be formed of one or more thick-film MOS transistors less in leakage current magnitude.
The thin-film MOS transistors as employed in accordance with the principles of the invention may advantageously serve to reduce power dissipation significantly by interrupting or xe2x80x9cinterceptingxe2x80x9d power feed during standby periods in light of the fact that leakage current can increase in magnitude even where these thin-film MOS transistors are designed to operate with extra low gate voltage below 2 volts, such as 0.8 volts or 1.2 volts or therearound, by way of example.
Preferably, that the leakage current-increased MOS transistors and leakage current-decreased ones are potentially driven by use of different gate voltages therefor. Practically, the leakage current-increased MOS transistors are to be driven upon application of certain voltage between the gate and source of each one, which voltage is lower than that being applied to the leakage current decreased MOS transistors.
In accordance with one aspect of the invention, a semiconductor integrated circuit device is provided which includes first and second MOS transistors as formed on the same silicon chip substrate. A respective one of the first MOS transistors has an insulative film of 4-nm thick or less as laid between the source and drain thereof or between its drain and gate; a corresponding insulative film of each second MOS transistor measures more than 4 nm in thickness.
In accordance with another aspect of the invention, a semiconductor integrated circuit device includes first and second MOS transistors as formed on the same silicon chip substrate. A respective one of the first MOS transistors has an insulative film of 4-nm thick or less as laid between the source and drain thereof or between its drain and gate; each second MOS transistor has an insulative film between the source and gate or between the drain and gate thereof, which film is greater in thickness than the first MOS transistors. The second MOS transistors are specifically adaptable for use in controlling flow of source-to-gate current or drain-to-gate current of the first MOS transistors.
In accordance with still another aspect of the invention, a semiconductor integrated circuit device includes first and second MOS transistors as formed on the same silicon chip substrate. A respective one of the first MOS transistors has an insulative film of 4-nm thick or less as laid between the source and drain or between the drain and gate thereof. The second MOS transistors are adaptable for use in interrupting transfer of associated power supply voltages toward the first MOS transistors. The semiconductor integrated circuit device further includes a level hold circuit for holding the last potential level of an output signal of each first MOS transistor during interruption of power supply.
In accordance with yet another aspect of the invention, a semiconductor integrated circuit device includes first and second MOS transistors as formed on the same silicon chip substrate. The first MOS transistors are inherently greater in magnitude of leakage current flowing between the source and gate or between the drain and gate thereof whereas the second MOS transistors remain less in leakage current than the first ones. The integrated circuit device is specifically arranged so that the second MOS transistors are driven by a predefined high voltage which is higher than that being applied to the first MOS transistors.
In accordance with a further aspect of the invention, a semiconductor integrated circuit device responsive to receipt o: an input signal having a specified amplitude voltage Vcc2 is arranged to include a level converter circuit for generating and issuing an in-chip signal by potentially reducing the amplitude voltage of an input signal, wherein leakage current occurrable between the gate and source or between the gate and drain of a MOS transistor accepting the in-chip signal is greater than that in another MOS transistor receiving the input signal.
When practicing the invention by applying it to integrated circuit devices such as those for use with microcomputers, the semiconductor integrated circuit device comes with an arithmetic processor unit and a data storage unit as configured using MOS transistors, which circuit may include at least one of the mask ROM, SRAM, and DRAM. The MOS transistors constituting one or more logic circuits in the arithmetic Processor has a gate insulation film which is less in thickness than those forming memory cells of the storage unit.
In accordance with a still further aspect of the invention, a semiconductor integrated circuit device includes on the same silicon substrate a plurality of kinds of MOS transistors including first MOS transistors and second MOS transistors different from each other in magnitude of tunnel current flowing between the source and gate or between the drain and gate. The semiconductor integrated circuit device also includes a main circuit configured using at least one tunnel current increased MOS transistor. The device further includes a controller circuit as operatively is coupled to the main circuit and also to at least one of two power supply units. This controller employs at least one of tunnel current decreased (or absent) MOS transistor. The controller is responsive to a control signal fed thereto for providing control so as to selectively permit and inhibit the flow of a current between the source and gate or between the drain and gate of the tunnel current increased MOS transistor for use in constituting the main circuit.
One characterizing feature of the semiconductor integrated circuit device lies in that the plurality of kinds of MOS transistors include MOS transistors different in gate insulation film thickness, or alternatively MOS transistors of the same conductivity type having gate electrodes doped with the same kind of impurity to different degrees of dopant concentration.
Another feature is that where MOS transistors different in gate insulation film thickness are employed, those MOS transistors each having a thick gate insulation film is provided with a side wall spacer which is adhered coating the side wall of its gate electrode. The spacer may be made of a chosen insulative material chemically insensitive to hydrofluoric acid. This side wall spacer may be for use as a mask for fabrication of the LDD structure, supra.
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USPTO Backgrounds