1. Field of the Invention
This invention relates to semiconductor devices and more particularly to MOSFET memory devices and methods of manufacture thereof.
2. Description of Related Art
U.S. Pat. No. 5,103,274 of Tang et al. for xe2x80x9cSelf-Aligned Source Process and Apparatusxe2x80x9d and shows a method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device.
U.S. Pat. No. 5,120,671 of Tang et al. for xe2x80x9cProcess for Self Aligning a Source Region with a Field Oxide Region and a Polysilicon Gatexe2x80x9d teaches a method and apparatus for self-aligning a source region with a field oxide region and a polysilicon gate and word line in a semiconductor device. The method and apparatus allows reduced memory cell size and improved device density by substantially eliminating the bird""s beak encroachment and corner rounding effects usually found between neighboring cells due to inadequacies in the prior art photolithography process.
U.S. Pat. No. 5,534,455 of Liu for xe2x80x9cMethod for Protecting a Stacked Gate Edge in a Semiconductor Device from Self Aligned Source (SAS) Etchxe2x80x9d shows a process for protecting the stacked gate edge of a semiconductor device. The process provides the step of spacer formation before the Self-Aligned Source (SAS) etching is accomplished.
This invention provides a method for shrinking array dimensions by one mask defining of cell and source line in a split gate flash memory device.
1. The active region is defined with a silicon nitride mask.
2. Field oxidation is performed and the silicon nitride mask is removed.
3. The cell is defined (process is different from the traditional method since one block replaces two separate cells)
4. The polysilicon 2 (second polysilicon) layer is defined by forming a photoresist mask for the split gate mask pairs without the source lines, which are formed later.
5. Source lines are defined by one mask, the cell blocks are separated simultaneously by etching polysilicon 2 layer, polysilicon oxide, polysilicon 1 (first polysilicon) layer and field oxide regions away where unprotected by the photo resist mask.
6. Remove the photoresist and the basic cell has been completed.
A method in accordance with this invention comprises forming split gate electrode MOSFET devices by the following steps which also produces a structure in accordance with this invention.
Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a floating gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Etch a source line slot bisecting the control gate layer and the floating gate stack. Form a source region through the source line slot with the gate electrode stack. Form a drain region self-aligned with the split gate electrodes and the gate electrode stack.
Preferably, form the floating gate electrode of a doped polysilicon layer. Form a silicon nitride floating gate mask over the polysilicon layer. Form the masking cap on the surface of the doped polysilicon by forming polysilicon oxide cap on the surface of the polysilicon layer. Pattern the tunnel oxide layer and the floating gate electrode layer in a subtractive process using the cap as a mask such as etching the tunnel oxide layer and the floating gate electrode layer using the cap as a mask to form the floating gate electrode.
Preferably, form FOX regions and then form active regions in the substrate prior to forming the tunnel oxide layer.
In accordance with another aspcect of this invention, form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern a gate electrode stack formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Form intermetal dielectric and control gate layers over the substrate covering the stack and the source regions and the drain regions. Pattern the intermetal dielectric and control gate layers into a combined split gate electrode. Pattern a source line slot in the center of the gate electrode stack down to the substrate. Form a source region self-aligned with the source line slot. Form a drain region self-aligned with the split gate electrodes and the gate electrode stack.
Preferably, form the floating gate electrode of a doped polysilicon layer. Pattern the tunnel oxide layer and the floating gate electrode layer in a subtractive process using the cap as a mask. Form the floating gate electrode of a doped polysilicon layer. Form a silicon nitride floating gate mask over the polysilicon layer. Form the masking cap on the surface of the doped polysilicon by forming polysilicon oxide cap on the surface of the polysilicon layer. Pattern the tunnel oxide layer and the floating gate electrode layer in a subtractive process using the cap as a mask.
Alternatively, start by forming the floating gate electrode of a doped polysilicon layer. Form a silicon nitride floating gate mask over the polysilicon layer. Form the masking cap on the surface of the doped polysilicon by forming polysilicon oxide cap on the surface of the polysilicon layer. Etch the tunnel oxide layer and the floating gate electrode layer using the cap as a mask to form the floating gate electrode. Form long FOX regions and then form active regions in the substrate prior to forming the tunnel oxide layer. Form a floating gate electrode from a doped polysilicon layer. Form a silicon nitride floating gate mask over the polysilicon layer. Form a masking cap on the surface of the doped polysilicon by forming polysilicon oxide cap on the surface of the polysilicon layer. The slot has a width from about 3500 xc3x85 to about 6500 xc3x85.
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