Given certain conditions, digital pictures taken with a digital camera using complimentary metal-oxide semiconductor (CMOS) image sensors may display an image defect in the output image. The image defect occurs most prevalently in output images with large contrasts. The image defect makes certain areas within the output image appear brighter in comparison with the original image. For example, if the original image has a very bright spot surrounded by a dark area, the output image will display the dark area as being brighter than the dark area in the original image.
This image defect is caused by a phenomenon commonly referred to as “blooming.” Blooming occurs when neighboring pixels collect electrons that have been injected into the substrate by another pixel. A pixel will inject electrons into the substrate when the photodiode of the pixel becomes forward biased due to a very large photocurrent across the photodiode (i.e., original image had a bright line condition).
FIG. 1 is a schematic 100 of a conventional pixel cell architecture for an individual pixel. The pixel cell architecture includes three transistors and will be hereinafter referred to as a 3-T pixel cell. The 3-T pixel cell includes a photodiode 108, an NMOS transistor 102, an NMOS transistor 104 and an NMOS transistor 106. The transistor 102 is employed to reset the pixel cell, transistor 104 operates as a source follower voltage buffer and transistor 106 is employed to select the pixel cell. The drains of transistor 102 and transistor 104 are coupled to the positive rail of the power supply (Vcc). The drain of transistor 106 is coupled to the source of transistor 104. The source of transistor 102 is coupled to the gate of transistor 104 and the cathode of the photodiode 108 at Node A. A parasitic capacitance (CP) at the gate of transistor 104 and a depletion layer capacitance (CD) of photodiode 108 appear at node A. The gate of transistor 102 is coupled to a reset line and the gate of transistor 106 is coupled to a select line. The bodies of transistors 102, 104 and 106 are coupled to the substrate at PWRN. Also, the anode of the photodiode 108 is coupled to the substrate at PWRN.
In operation, a positive pulse is applied to the gate of reset transistor 102 so that a positive bias voltage is applied at the cathode of the photodiode 108 and the depletion layer capacitance (CD) of the photodiode will charge up. After the reset transistor 102 turns off, photodiode 108 remains biased at the positive bias voltage because of the charge stored in its depletion layer capacitance (CD). However, when photons (light) are incident on photodiode 108, a photocurrent (not shown) will flow from the cathode to the anode of the photodiode. The photocurrent discharges the photodiode's depletion layer capacitance (CD) and causes the voltage across the photodiode 108 to drop. After a certain time interval (i.e., the integration time), a positive pulse (i.e., row select) is applied to the gate of row select transistor 106. This connects the output of source follower transistor 104 to the column readout line so that the output signal voltage (VDIODE) can be read out through the source follower transistor 104 on the column line at the source of the select transistor 106.
As mentioned above, blooming occurs when the photocurrent is very large. When the photocurrent is very large, node A can be discharged and may become at a lower potential than PWRN. If this occurs, photodiode 108 becomes forward biased, which causes the injection of charge carriers into the substrate. The charge carriers (i.e., electrons) in the substrate are then collected by neighboring pixels. Thus, these additional charge carriers that are collected impact the read out of the output signal voltage for the neighboring pixel and will result in the image defect described above.
Traditionally, the low level (i.e., “off”) of the reset signal is at ground (i.e., PWRN). In conventional image sensors that prevent photodiode 108 from becoming forward biased, the logic low level (i.e., “off”) of the reset signal is raised so that the photodiode 108 is well in reverse bias region. By raising the low level of reset to 1V, the cathode of photodiode 108 will be at 1V minus the threshold voltage of transistor 102, which is around 0.3V. Briefly, turning to FIG. 2, in a conventional image sensor, the RESET signal generated by mux 14 is supplied directly to pixel 12 (i.e., transistor 102 in FIG. 1). Then, to implement the blooming control, an external source of 1V is applied to mux 14. As a result, the output of mux 14, the RESET signal, that goes directly to pixel 12 will have the desirable logic low level of 1V. However, as shown in FIG. 2, in an image sensor implementing a high voltage reset circuit 204, inputting the 1V source at mux 14 will not produce the desired effect. Firstly, the high voltage level shifter will dissipate significant power. Secondly, the output signal (i.e., RESETH) will have a low logic level of 0V, rather than the desired 1V. Therefore, blooming will occur in image sensors implementing a high voltage reset circuit.
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