(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a substrate potential detection circuit.
(2) Description of the Related Art
FIG. 1 shows a conventional substrate potential detection circuit used in a semiconductor integrated circuit device, which has a circuit configuration wherein a P-channel MOS transistor (hereinafter referred to as a "PMOS") Q10 and an N-channel MOS transistor (hereinafter referred to as an "NMOS") Q20 are connected in series between a power supply source V.sub.CC and a substrate potential source V.sub.BB. The PMOS Q10 has a source connected to the power supply source V.sub.CC, a gate connected to the ground, and a drain connected to a detection output (true output) node N1 from which a detection output is derived. The NMOS Q20 has a source connected to the substrate potential source V.sub.BB, a gate connected to the ground, and a drain connected to the detection output node N1. The detection output from the output node N1 is amplified by serially connected inverters I.sub.1 through I.sub.n.
Next, how the above circuit operates is explained. The gate-source voltage V.sub.GS of the NMOS Q20 is the absolute value of the substrate potential V.sub.BB (hereinafter also referred to as "V.sub.BB ") at the source thereof because the potential at the gate electrode thereof is a constant value of the ground potential. On the other hand, the gate-source voltage V.sub.GS of the PMOS Q10 becomes V.sub.GS =-V.sub.CC since the gate is at the ground potential and the source is at a power source voltage V.sub.CC (hereinafter also referred to as "V.sub.CC "). Since this gate-source voltage V.sub.GS is sufficiently larger than a threshold voltage of the PMOS Q10, the PMOS Q10 is normally in its conductive state.
Thus, when the substrate potential V.sub.BB is shallow (that is, small in its absolute value), the detection output node N1 becomes a high level state (wherein an output of the inverter I.sub.1 is rendered substantially to the ground potential) because of a high current driving capability of the PMOS Q10. On the other hand, when the substrate potential V.sub.BB becomes deep, and the current driving capability of the NMOS Q20 becomes larger than that of the PMOS Q10, the detection output node N1 becomes a low level state (wherein the output of the inverter I.sub.1 is rendered substantially to the power source voltage level).
As readily understood from the above explained operation, a detection level for the substrate potential is a transition point where the detection output node N1 changes from its high level to its low level. In other words, since the detection level is determined by a difference or a ratio between the current driving capability of the NMOS transistor Q20 and that of the PMOS transistor Q10, it is possible to change such detection level by having the sizes of the respective MOS transistors Q10 and Q20 changed.
In the conventional substrate potential detection circuit explained above, the difference between the current driving capability of the PMOS transistor and that of the NMOS transistor is utilized for detecting a change in the substrate potential.
However, since the threshold voltage values of PMOS transistors and NMOS transistors vary due to variations in the parameters involved in the fabricating process whereby the current driving capabilities are caused to deviate from the designed values and, accordingly, the detection level of the substrate potential is also caused to change unavoidably. This is a problem to be solved.
USPTO Backgrounds
USPTO Backgrounds