The majority of present day integrated circuits are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A MOS transistor includes a gate electrode as a control electrode and spaced apart source and drain regions between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel between the source and drain regions.
The production process leading to the provision of integrated circuits on a large scale typically includes a plurality of processing steps that take place on a thin wafer of semiconductor material, for example a monocrystalline silicon wafer. The wafer is subjected to a plurality of chemical and physical treatments and to photolithographic processes that lead to the definition of a complex three-dimensional topography constituting the integrated circuit architecture. A single wafer may contain hundreds of integrated circuits commonly called “chips” and arranged side by side, for example, and separated by scribing lines.
The term “metrology” broadly refers to the measurement and testing of objects. Metrology schemes are commonly used in the fabrication of integrated circuits. Metrology schemes are often used to measure features formed on the wafers to ensure that the features meet desired specifications, including the layout and spacing of the various integrated chips to be fabricated on the wafer. Various metrology methods may be used following any number of steps in a fabrication sequence to ensure that the semiconductor devices are formed within desired specifications.
In some fabrication processes, the first step in fabricating an integrated circuit (subsequent to the design of the integrated circuit) includes the design “tape-out” process, which begins with sending tape-out forms to the integrated circuit manufacturer. Tape-out forms are data files describing manufacturing related data and other details, such as mask tooling information for manufacturers or technology information. After tape-out forms are generated, descriptions of a circuit will be sent for manufacture. In current practice, metrology schemes for the semiconductor wafer are prepared based on the tape-out form. Thus, for each new tape-form that is received by the manufacturer, a new metrology scheme needs to be implemented specific to the respective wafer design. Currently, the preparation of a new metrology scheme for each tape-out form takes about a week's worth of time to complete, thus undesirably delaying the semiconductor fabrication process, and increasing fabrication expenses.
Accordingly, it is desirable to provide improved metrology schemes and improved methods for fabricating integrated circuits that reduce the time and expense involved in the design and implementation of metrology schemes. Additionally, it is desirable to provide a fixed-coordinate metrology scheme and methods for fabricating integrated circuits using a fixed-coordinate metrology scheme that does not need to be re-designed for each tape-out form. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.
USPTO Backgrounds
USPTO Backgrounds