1. Field of Invention
The invention relates to three-dimensional (3D) integrated assemblies, and more particularly to three-dimensional (3D) integrated circuit assemblies including metallization interconnections.
2. Discussion of Related Art
Today's integrated circuits often include many (up to millions, or greater) integrated components and devices. However, for a given product, it sometimes is not possible, even with access to millions of components, to achieve on one integrated substrate (or integrated circuits, also know as chips) all of the circuitry or performance required. Thus, two or more substrates may be required. Also, fabrication process limitations sometimes dictate the use of two or more substrates for manufacturing different components. A major challenge then becomes the interconnection of the circuitry on multiple substrates. There may be hundreds of connections required between chips and it is necessary to keep connection resistance low and path lengths short to minimize inductive and capacitive effects, permitting high speed operation. While numerous interconnection arrangements and processes are known, many require special, complicated processes or expensive structures.
Additionally, as the number of components and devices on integrated circuits continues to increase, there exists an increasing number and complexity of on-chip wires used to connect the various components and devices, and to connect internal components and devices to external circuitry. These interconnections may be space-consuming, forcing the length of the interconnections to be longer and thus introducing more delay in signal propagation along these on-chip wires. Introducing additional wiring layers can result in a reduction of wiring lengths, but the formation or fabrication of such additional wiring layers may require additional or complicated processing steps. In addition, the cost of making interconnections is often a critical factor in determining the number of interconnections that may be used if a product is to sell.
Another way to reduce the length of interconnections (and the corresponding wiring delay, coupling capacitance between wires, loss mechanisms, and other unwanted wire parasitics) is to position the devices to be interconnected in a three-dimensional (3D) spatial arrangement. Part of the wire congestion in two-dimensional (2D) spatial arrangements comes from the inability to optimally place the components to be connected, and a 3D arrangement allows more possibilities for attaining optimal placement of components and devices. However, to attain the maximum advantage of wire shortening, the wires would have to be able to be directed vertically through vias between the 3D stacked circuits anywhere within the volume of the circuitry, and not just around the periphery of the stack. FIG. 1 illustrates an example of a 3D chip stack with vertical vias in the interior of the stack. The chip stack 100 includes substrates 110, 120, 130, and 140. Examples of vertical vias are shown as 112, 114, and 116.
A further advantage of 3D placement of components can be a reduction in the overall size of the package required to house these integrated circuits. Packages are often more expensive than the integrated circuits that they enclose, so housing more than one integrated circuit in a single package that would normally enclose only one integrated circuit produces a cost advantage, provided heat removal from the package does not exceed reasonable limits. One kind of multi-chip package would stack dies one upon another. For example, one existing method of packaging 3D integrated circuits consists of centering consecutively larger dies one upon another using wirebond or perimeter tape connections along the edges of the dies. Stacking by wire bonding is in current use today in multifunction cell phones and digital cameras. But this technique does not permit vertical vias within the body of the 3D circuit that can achieve optimal wire shortening between components within the stack, as the only vertical connections are around the periphery of the dies.
Another 3D configuration utilizes two substrates stacked in a face-to-face configuration, as illustrated in FIGS. 2A and 2B. The term face-to-face implies that the surfaces of the substrates that contain the devices and their contacts, called the faces, will be bonded facing each other. As shown, the two substrates 210 and 220 are aligned and bonded with their respective face surfaces facing each other. In such a configuration, a bridge via may be used to form an interconnection. Bridge vias are relatively expensive in chip area since they require the space of two vertical tunnels as well as the space (gap) between the tunnels to be dedicated to one vertical via signal connection. Since each tunnel and gap takes up surface area and creates some wire exclusion area, it is desirable to minimize this exclusion area for layout compactness.
Thus, a structure and method of forming compact integrated circuit assemblies and interconnections is needed. Preferably, this structure and method will be economical, will facilitate vertical connections within the body of the 3D assembly and not just around the periphery, and will not require processing equipment beyond that employed for semiconductor monolithic wafer fabrication including those developed for existing Microelectromecanical Systems (MEMS). It is also desired that such structures and methods should support device interconnections that maintain low inductive, capacitive and resistive coupling between devices on different layers of the 3D die assembly.
USPTO Backgrounds
USPTO Backgrounds