Radio frequency (RF) transmitters in wireless networks are generally required to operate in a linear region of a power-vs.-gain curve. If the transmitter is used in a system over a range of transmission power, linearity is generally measured by how the output gain (e.g., the P1 dB, or 1 dB compression point with reference to the output power) scales as a function of output power. For example, as the transmitter power is lowered, the P1 dB requirement is also reduced, and the power amplifier power dissipation should also be reduced for efficient operation.
To achieve optimal efficiency, circuit designers typically design a power amplifier to be as efficient as possible while meeting the linearity requirements. For a bipolar power amplifier (such as those typically used in RF transmitters), an optimal bias point is the bias at which the class B effect of low power signal gain expansion cancels or offsets the class A effect of high-power signal gain compression. This optimal class A/B bias point can also be represented as an optimal voltage at the base of the bipolar amplifier transistor or an optimal emitter current density in the bipolar power amplifier. The designer therefore scales amplifier device sizes such that sufficient power is provided to the load at the amplifier output (which may be scaled with an impedance network to maximize amplifier efficiency). For a fixed transistor size and a given optimal quiescent current density, efficient operation is possible only over a relatively small transmission power range, and maximum efficiency is possible only at a single transmission power.
If one could change the size of the bipolar device(s) in the amplifier, one could maintain the optimal emitter current density over a relatively large output power range. For example, one may wish to implement a low power mode (e.g., where the output is in the range of from 0 to 10 dBm), in addition to a “normal operation” mode (e.g., where the output is in the range of from 10 to 20 dBm). However, once the bipolar amplifier is manufactured, the size of the devices generally cannot be changed, thereby effectively preventing the same power amp from providing highly efficient low power and “normal operation” modes.
One approach to providing power amplification over a range exceeding the linear range of a single amplifier has employed multiple amplifiers, each having a different linear range of operation. In this approach, one simply selects the appropriate amplifier for the power range in which one is operating. However, such an approach consumes a relatively large chip area, in comparison to single amplifier designs. Furthermore, this approach typically introduces a digital or CMOS switch in the RF signal path, thereby introducing (i) non-linearities into the signal amplification function and/or (ii) attenuation and/or insertion loss into the signal itself.
Another approach has varied the bias applied to the power amp. While this approach extends the efficient range of operation, it does so at the cost of reduced linearity and potentially unacceptable linearity at the lower end of the output power range. Thus, a need is felt for a power amplifier that operates efficiently over a large output power range and that does not consume an inordinate amount of chip area.
USPTO Backgrounds
USPTO Backgrounds