1. Field of the Invention
The invention generally relates to shared bus systems, and particularly relates to a shared bus system in which a bus is released by avoiding extended bus occupancy.
2. Description of the Related Art
When a plurality of masters share a bus, a master in need of using the bus issues a request to an arbiter to request the right to use the bus. The arbiter arbitrates in response to requests from a plurality of masters, and grants the right to use the bus to a master that is selected according to priority.
One or more cycles are needed in order to perform the arbitration process as described above. It follows, therefore, that the arbitration process needs to be carried out each time a request is made if masters issue requests in a piecemeal manner, for example, resulting in the excessive use of cycles. Moreover, if a certain master holds on to the right to use the bus, and refuses to release it, other masters have no chance to use the bus. This results in a drop in system-wide performance.
A related-art document (Japanese Patent Application Publication No. 2000-010914) shows an arbitration controlling apparatus which controls the number of requests that can be processed consecutively with respect to a request signal, thereby shortening an excess processing time that would be needed at the time of switching request signals. According to this related-art document, a selected request signal is dropped to the lowest priority. However, a request holding signal corresponding to this request signal is asserted so as to process the same request signal consecutively despite its priority.
As an example of a method of preventing extended bus occupancy by a single master, an arbiter may monitor the state of the bus continuously, and take away the right to use the bus from the master if the bus occupancy continues more than a predetermined time period, or if a request from another master is detected. In order to achieve this, however, the arbiter circuit and circuitry on the master side need to exchange control signals, resulting in a complex circuit structure and complex control procedures. As a result, the number of cycles required for bus control may increase, and, under some circumstances, the system may be locked, resulting in a long period of suspended state.
Accordingly, there is a need for a shared bus system in which simple control operations by an arbiter and masters can prevent an extended state of bus occupancy.
USPTO Backgrounds
USPTO Backgrounds