1. Field of the Invention
This invention relates to a plasma display panel, and more particularly to a plasma display panel that is adapted to be driven by a low voltage signal.
2. Background of the Related Art
Recently, it has been possible to manufacture a plasma display panel (PDP) of a large-dimension panel. Such a PDP has a number of discharge cells arranged in a matrix. The discharge cells are provided at each of intersections between sustain electrode lines for sustaining a discharge and address electrode lines for selecting a cell to be discharged.
The PDP is largely classified into a direct current (DC) type panel and an alternating current (AC) type panel depending on whether or not a dielectric layer for accumulating a wall charge exists in the discharge cell. The PDP requires a high voltage of hundreds of volts to cause a glow discharge. To this end, a driving circuit of the PDP includes high voltage devices for generating a high voltage signal of hundreds of volts. For instance, the triple-electrode AC PDP is driven with a high voltage of about 200 to 300V.
Referring to FIG. 1, each cell of the triple-electrode AC PDP includes a front substrate 10 provided with row sustain electrodes pair 12A and 12B, and a rear substrate 18 provided with column address electrodes 20. The front substrate 10 and the rear substrate 18 are spaced in parallel to each other with having barrier ribs 24 therebetween. A mixture of gases, such as Ne-Xe or He-Xe, etc., is injected into a discharge space defined by the front substrate 10, the rear substrate 18 and the barrier ribs 24.
Any one electrode of the sustain electrode pair 12A and 12B is used as a scan/sustain electrode that responds to a scanning pulse applied in an address interval to cause an matrix discharge along with the address electrode 4 while responding to a sustaining pulse applied in a sustaining interval to cause a surface discharge along with the other adjacent sustain electrode. Also, one of the sustain electrode pair 12A or 12B is used as the scan/sustain electrode and the other is used as a common sustain electrode to which a sustaining pulse is applied commonly.
On the front substrate 10 provided with the sustain electrodes 12A and 12B, a dielectric layer 14 and a protective layer 16 are disposed. The dielectric layer 14 is responsible for limiting a plasma discharge current as well as accumulating a wall charge during the discharge. The protective layer 16 prevents damage of the dielectric layer 14 caused by the sputtering generated during the plasma discharge and improves the emission efficiency of secondary electrons. This protective layer 16 is usually made of magnesium oxide (MgO).
The rear substrate 18 is provided with a dielectric layer 26 covering the address electrodes 24. The barrier ribs 24 for dividing the discharge space extend perpendicularly at the rear substrate 18. A fluorescent material 22, excited by a vacuum ultraviolet lay to generate a visible light, is coated between the barrier ribs on the rear substrate.
As shown in FIG. 2, the cells 1 of the PDP are arranged on a panel 30 in a matrix. In each cell 1, scan/sustain electrode lines S1 to Sm, common sustain electrode lines C1 to Cm and address electrode lines D1 to Dn cross each other. The scan/sustain electrode lines S1 to Sm and the common sustain electrodes C1 to Cm comprise the sustain electrodes pair 12A and 12B in FIG. 1, respectively. The address electrode lines D1 to Dn comprise the address electrodes 20.
Such a triple-electrode AC PDP selects a cell to be displayed by a matrix discharge between the address electrode 20 and any one of the sustain electrodes 12A and 12B and thereafter sustains a discharge by a surface discharge between the sustain electrodes 12A and 12B. An ultraviolet generated by a sustaining discharge excites the fluorescent material 22.
At this time, a voltage required for a discharge is different depending on a distance between the electrodes and a wall charge amount accumulated in the dielectric layers 14 and 26, but it must be a high voltage of about 200 to 300V. To this end, the PDP driving apparatus requires a high voltage driving integrated circuit (IC). The high voltage signal generated from the high voltage driving IC is applied to a panel electrode comprising the sustain electrode pair 12A and 12B and the address electrode 20. The high voltage driving IC is mounted on a printed circuit board (PCB) connected to the panel 30.
As shown in FIG. 3, the high voltage driving IC includes a plurality of sets of a high voltage switch 42 supplied with a high-level voltage VDD and a low-level voltage VSS (or the ground GND), and a logic unit 40 for controlling the high voltage switch 42. The high voltage switch 42 includes a p-channel MOS FET T1 and an n-channel MOS FET T2 connected in a push-pull configuration. The high voltage switch selects any one of the high-level voltages under control of the logic unit 40 and applies it to a panel electrode 50. The panel electrode 50 corresponds to the sustain electrode pair 12A and 12B or the address electrode 20 and is provided on the panel 30.
The logic unit 40 responds to a logic input signal Lin to generate a low logic control signal. Then, since the p-channel MOS FET T1 is turned on, the high-level voltage VDD is applied, via a first voltage input line 31 and an output line 33, to the panel electrode 50. On the other hand, if a high logic control signal is generated from the logic unit 40, then the n-channel MOS FET T2 is turned on to apply the low-level voltage VSS, via a second voltage input line 32 and the output line 33, to the panel electrode 50.
Since the logic unit 40 and the high voltage switch 42 are connected, in series, to the panel electrode 50, their number is determined by the number of the panel electrode 50. In the case of a panel having a resolution of VGA class, the total number of address lines D1 to Dn supplied with red, green and blue data is 1920 (3xc3x97640). In this case, if the number of the output pin of each set of high voltage driving IC is 64, then 30 high voltage driving IC""s are required to drive the address electrode lines D1 to Dn. Accordingly, as a resolution of the panel 30 increases to an SXGA class or more, a larger number of high voltage driving IC""s are required. Since the high voltage driving IC is more expensive than the general low voltage driving IC, however, the cost of the PDP increases.
Moreover, since a larger number of high voltage driving IC""s are required as a resolution of the panel 30 is improved into an SXGA class or more, the manufacturing cost of the PDP increases greatly. Further, the complexity of manufacturing process increases. Such problems are generated in the case of the triple-electrode AC PDP as well as in the case of a DC-type PDP causing a discharge by a DC voltage signal of more than hundreds of volts (V).
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Accordingly, it is an object of the present invention to drive a plasma display panel with low voltage signals.
Another object of the invention is to reduce at least one of PDP cost, manufacturing cost, and manufacturing complexity.
A further object of the present invention is to provide a low voltage driving apparatus and method for a plasma display panel wherein a driving circuit are implemented with low voltage devices to drive the plasma display panel with low voltage signals.
In order to achieve these and other objects of the invention, a plasma display panel according to one aspect of the present invention includes a source electrode supplied with a voltage; and a trigger electrode opposite to the source electrode, whereby a discharge being generated between source electrode and trigger electrode to apply a voltage at each source electrode to each panel electrode.
A plasma display panel according to another aspect of the present invention includes a plurality of trigger electrodes responding to a low-level to cause an initial discharge; and a plurality of source electrodes receiving a high-level voltage from an external high-level voltage supply to cause the initial discharge and generating a secondary discharge along with the panel electrodes, whereby a voltage at each of the source electrode is transferred to each of panel electrodes by virtue of the secondary discharge.
A low-level voltage driving apparatus for a plasma display panel according to still another aspect of the present invention includes a driving circuit for generating a low-level voltage control signal; and a trigger driver, being provided at the plasma display panel, to apply a high-level voltage of each panel electrode in response to the low-level voltage control signal.
A method of driving a plasma display panel at a low-level voltage according to still another aspect of the present invention includes the steps of generating a low-level voltage control signal; and responding to the low-level voltage control signal to cause an initial discharge; and generating a secondary discharge between the panel electrode and the source electrode supplied with a high-level voltage by virtue of a transition of the initial discharge to apply the high-level voltage from the source electrode to the panel electrode.
Additional advantages, objects and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
USPTO Backgrounds
USPTO Backgrounds