1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of manufacture thereof and, more particularly, to a semiconductor integrated circuit in which npn and pnp bipolar transistors and p- and n-channel MOSFETs are formed together on the same chip and a method of manufacture thereof.
2. Description of the Related Art
Hereinafter, a description is given of a conventional inverter gate circuit of a Bi-CMOS structure which is formed of complementary metal oxide semiconductor field effect transistors (CMOSFETs) and npn bipolar transistors with reference to FIG. 4.
Referring to FIG. 4, there is shown a typical prior art inverter gate circuit formed of CMOS transistors and npn bipolar transistors.
As shown in FIG. 4, the inverter gate circuit is of a totem pole type in which emitter 105 of a load driving npn bipolar transistor Q101 and collector 106 of npn bipolar transistor Q102 are connected together at node d. Npn bipolar transistor Q101 has its base 101 connected to drain 103 of a p-channel MOSFET T101 so as to be driven by MOSFET 101.
Heretofore, each of four transistors T101, T102, Q101 and Q102 constituting the inverter gate circuit is formed within a separate region on a semiconductor substrate. For this reason, the number of regions for isolating transistors from each other increases, thus increasing the occupied area of the inverter gate circuit on the semiconductor chip.
N-channel MOSFET T102 is of a source current supply type and thus susceptible to base potential V.sub.B of npn bipolar transistor Q102 during operation. That is, the effective gate potential of n-channel MOSFET T102 will be given by the difference between input potential Vin of MOSFET T102 and base potential V.sub.B of npn bipolar transistor Q102. This leads to insufficient driving of n-channel MOSFET T102. Where MOSFET T102 is not driven sufficiently, the collector current of npn bipolar transistor Q102 will decrease, making the inverter gate circuit slow in operation. This disadvantage becomes remarkable particularly when a low supply voltage is used. Moreover, because collector 106 of npn bipolar transistor Q102 is connected to node d, the collector potential varies with output levels. For this reason, collector 106 of transistor Q102 must be electrically isolated from other transistors Q101, T101 and T102.
That is, it is desired that npn bipolar transistor Q102 be formed within a n-type well and n-channel MOSFET T102 be formed within a p-type well. For this reason, it is impossible to form bipolar transistor Q102 and MOSFET T102 within the same well. Thus, with the inverter gate circuit of the Bi-CMOS structure it is required to provide a device isolation region between bipolar transistor Q102 and MOSFET T102. This leads to an increase of the occupied area of the inverter gate circuit on a semiconductor chip.
USPTO Backgrounds
USPTO Backgrounds