1. Field
Exemplary embodiments of the present invention relate to a test circuit, a memory system, and the test method of the memory system.
2. Description of the Related Art
As the size of a semiconductor chip is reduced, demands for a technique for reducing the size of the semiconductor chip or a semiconductor package have increased. The technique for reducing the size of the semiconductor chip or the semiconductor package commonly includes a system on chip (hereinafter referred to as an SOC) technique for making several individual semiconductor devices into one semiconductor chip and a system in package (hereinafter referred to as an SIP) technique for packaging several semiconductor chips into one semiconductor package. Above techniques are also used when fabricating memory chips or memory packages.
For an efficient test on a plurality of memory circuits included in a memory chip or a memory package, there is a recent proposal for a method of including a built-in self test (BIST) circuit (hereinafter referred to as a test circuit) for testing a plurality of memory circuits, together with the plurality of memory circuits, in the memory chip or the memory package when fabricating the memory chip or the memory package by using the SOC or SIP technique.
In case of a memory chip or a memory package that includes a test circuit, test equipment externally connected to the memory chip or the memory package and a large number of ports for coupling memory circuits within the memory chip or the memory package are not necessary and the memory chip or the memory package may be rapidly tested because a test algorithm for testing the memory circuits may be embodied in the memory chip or the memory package.
FIG. 1 shows a known memory system that includes a test circuit (shows a memory chip or a memory package that includes heterogeneous or homogeneous memory circuits).
As shown in FIG. 1, the memory system includes first to third memory circuits 110, 120, and 130 having different capacities, a test circuit 140 for testing the first to third memory circuits 110, 120, and 130, and a bus BUS for transferring signals between different elements included in the memory system. It is hereinafter assumed that the first to third memory circuits 110, 120, and 130 are heterogeneous or homogeneous. However, they have different densities and different memory capacities. The first memory circuit 110 has the lowest memory capacity, and the third memory circuit 130 has the highest memory capacity.
The known memory system is described below with reference to FIG. 1.
When a test is started, the test circuit 140 tests the first to third memory circuits 110, 120, and 130. For example, when the first memory circuit 110 is tested, the test circuit 140 supplies commands (including a read command and a write command), an address, and data that has a test pattern (hereinafter referred to as test execution information) for the test to the first memory circuit 110 through the bus BUS. The test circuit 140 receives and analyzes the output of the first memory circuit 110 through the bus BUS, and generates information indicating whether a failure has occurred in the first memory circuit 140 and indicating a fail address (hereinafter referred to as test result information) based on a result of the analysis. Here, the test circuit 140 may perform the test by using test execution information stored in a storage unit (not shown in FIG. 1) (hereinafter referred to as an embedded storage unit) embedded in the test circuit 140 and store test result information in the embedded storage unit.
In general, when a memory circuit that has a higher memory capacity is tested, the size of test execution information or test result information is increased. For this reason, the embedded storage unit of the test circuit 140 is designed to have a memory capacity so that a memory circuit that has the highest memory capacity among memory circuits to be tested by the test circuit 140 (hereinafter referred to as target test memory circuits) may be smoothly tested. For example, in case of the memory system of FIG. 1, the embedded storage unit of the test circuit 140 is designed to have a memory capacity enough to smoothly test the third memory circuit 130 not the first memory circuit 110 or the second memory circuit 120.
However, if the memory capacity of the embedded storage unit of the test circuit 140 is designed based on a memory circuit that has the highest memory capacity among target test memory circuits, the memory capacity and the area of the test circuit 140 are increased. As a result, the size of the memory system is increased.
USPTO Backgrounds
USPTO Backgrounds