The present invention relates to a semiconductor package, and more particularly to a semiconductor package and a method for manufacturing the same which, can easily supply power without an increase in the number of pads required for the power supply.
The latest semiconductor device, e.g., Dynamic Random Access Memory (DRAM) has been manufactured to have high density and velocity. Chips of higher velocity and performance require operational characteristics of low voltage to reduce the amount of power used and heat generated due to the amount of power used.
However, in order to satisfy such characteristics, a larger number of the pads are required for power supply. The ability to increase the number of pads within the chip is limited and it makes total size of the chip greater, which results in increasing a product cost.
The latest semiconductor chip of higher velocity and performance requires a larger number of the pads for power supply, and such pads must be formed only on specific locations that enable wire bonding in an assembly process. However, the size of the chip must be necessarily increased in order accommodate a larger number of pads in the specific locations. This causes an increase in the product cost.
Moreover, in the typical DRAM device the pads are arranged in a center portion to be manufactured as package of a Board On Chip (BOC) type using a substrate with a window. It is difficult to supply sufficient power because the power is supplied to edge portions of the chip via a metal wire connected to the pads in the center portion.
In addition, since the semiconductor chip is manufactured using fine processes, proposals for the size, the number and the pitch of the pad are very limited. A pitch for a lead frame or substrate used for packaging the semiconductor chip is very great due to limitation of the process. Therefore, although a sufficient number of pads is formed on the semiconductor chip to supply the power, it is possible to connect all of the pads via the wire due to a difference between the pitch of the pad and the pitch of the lead frame.
Moreover, a lot of the time and cost is involved because the whole semiconductor chip must be redesigned or additional metal wiring must be formed via a Fab process in order to prepare additional power or signal wiring.
USPTO Backgrounds
USPTO Backgrounds