The present invention relates generally to static read-write randomly accessible memory cells (RAMs), more particularly to static RAMs which are based on the silicon-controlled rectifier (SCR) device, and especially to improvements in the speed with which new data can be written into such cells.
As is by now well known, the SCR-based memory cell uses an alternating-conductivity-type (PNPN) SCR structure to form each half or side of the memory cell. The alternating conductivity regions are typically formed by diffusion into an epitaxial layer, such that the resulting device is arrayed laterally along or across the layer.
The circuit has two stable operational states, corresponding to either the left or right side conducting while the other side is cut off. By arbitrary assignment of the logic bits 1 and 0 to these bistable states, the cell is used as a memory device for the storage of one data bit. Memory devices of a size large enough to be useful are formed of an addressable matrix-array which may include many thousands of such cells.
An important performance criterion of such devices is their speed of operation, which in turn affects the speed of operation of the computer using such memory cells. An important component of the overall speed of these memory devices has proven to be the speed with which they can be written to a new data state. Considered on the level of the memory cell itself, the writing speed amounts to the speed with which one side of the cell can be turned on while the other is turned off.
For reasons which will become apparent in the more detailed technical descriptions later in this application, the writing speed of such memory cells is principally limited by the substantial intrinsic capacitance associated with each cell. This intrinsic capacitance has considerable stored charge which causes delays whenever it is necessary to change the operational state of the cell to reflect the new data being written to it.
The magnitude of this capacitance could be significantly reduced by changes in the geometry and other parameters of the memory cell, but such changes would have other negative consequences. In particular, the large stored charge of the capacitance serves the positive purpose of increasing the immunity of the memory cell to alpha-particle-induced alterations of the memory state of the cell. Consequently, some method of increasing writing speed without significantly reducing capacitance is needed.
USPTO Backgrounds
USPTO Backgrounds