This invention relates to frequency compensated electronic circuits, and more particularly relates to amplifier circuits having Miller-compensating capacitors.
The stability performance of circuits having feedback is improved by providing compensation so as to increase phase margin. A well known technique for improving phase margin takes advantage of the Miller Effect, by adding a Miller-compensating capacitance in parallel with a gain stage, e.g., the output stage of a two stage amplifier circuit. Such a configuration results in the well-known and desirable phenomenon called pole splitting, which advantageously multiplies the effective capacitance of the physical capacitor employed in the circuit. See, e.g., for background on compensation of amplifier circuits using Miller-compensating capacitance, Paul R. Gray and Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., John Wiley and Sons, Inc., New York, 1993, Ch. 9, pp. 607-623.
However, integrated capacitors occupy a relatively large area on an integrated circuit chip, relative to other components such as complementary-metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) transistors. The problem becomes worse when the load capacitance seen by a circuit having Miller-compensating capacitance becomes large. This requires the compensating capacitance to increase in value in order to maintain stability. However, the larger compensating capacitance occupies even more physical space. But, this is not a luxury that can be afforded in an environment where more circuits are integrated onto the same die, which, of course, is the trend
A current-mode capacitor multiplier technique has been proposed, in an article entitled, xe2x80x9cActive Capacitor Multiplier in Miller-Compensated Circuits,xe2x80x9d by Gabriel A. Rincon-Mora, IEEE JSSC, Vol. 35, No. 1, January 2000, at pages 26-32, by which the size of the Miller capacitor can be reduced by a factor equal to the current gain of a new loop added to the circuit.
FIG. 1 is a circuit diagram of a simple amplifier circuit. This circuit has one dominant pole, in the left hand plane, located at:                                           F            P1                    =                                    -                              (                                                      g                    1                                    +                                      g                    2                                                  )                                                    C              c1                                      ,                            Eq        .                  xe2x80x83                ⁢                  (          1          )                    
where fP1 is the pole frequency, f01 is the zero frequency, gi is the conductance (i.e., inverse of output resistance 1/R0) of transistor Mi, and Cc1 is the value of the compensating capacitor.
FIG. 2 is a circuit diagram of a simple amplifier circuit like that of FIG. 1, but modified using the technique described in the Rincon-Mora article. The added current gain loop consisting of current source I and transistor M5 can be seen in the figure. The circuit has one dominant pole and one dominant zero. The pole and the zero are both in the left half plane (xe2x80x9cLHPxe2x80x9d), and they are located at:                               f          P2                =                                            -                                                gm                  5                                ⁡                                  (                                                            g                      3                                        +                                          g                      2                                                        )                                                                                    C                c2                            ⁡                              (                                                      gm                    4                                    +                                      gm                    5                                                  )                                              ⁢                      xe2x80x83                    ⁢          and                                    Eq        .                  xe2x80x83                ⁢                  (          2          )                                                                            f              02                        =                                          -                                  gm                  5                                                            C                c2                                              ,                ⁢                  xe2x80x83                                    Eq        .                  xe2x80x83                ⁢                  (          3          )                    
where fP2 is the pole frequency, f02 is the zero frequency, gmi is the transconductance of transistor Mi, Cc2 is the value of the compensating capacitor, and other values are as defined above. In this circuit, there is an effective capacitor multiplication of:                               C          eq                =                                            C              c2                        ⁡                          (                              1                +                                                      gm                    4                                                        gm                    5                                                              )                                .                                    Eq        .                  xe2x80x83                ⁢                  (          4          )                    
This is the basic principle of the technique discussed in the Rincon-Mora article.
However, an aspect of the technique discussed in the Rincon-Mora article is that a second capacitor is used to stabilize the amplifier that is discussed in that article, which is more complex than the amplifier discussed above and more typical of amplifiers used in applications such as amplifiers, LDOs and regulators. Another aspect is that the LHP zero reduces the gain margin, and can be a source of long settling time constants. It would therefore be desirable to provide Miller compensation of circuits with capacitor multiplication, but with only a single capacitor. It would also be desirable to provide Miller compensation of circuits with capacitor multiplication, with improved gain margin.
In accordance with the invention there is provided a Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion staae includes a first current mirror adapted to mirror a first current corresponding to a current throuuh the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication. The invention is applicable to single stage amplifiers, as well as multi-stage amplifiers, low drop-outs (xe2x80x9cLDOsxe2x80x9d) and regular circuits, having Miller compensation.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds