A Cathode Ray Tube (CRT) display generally provides the best brightness, highest contrast, best color quality and largest viewing angle of prior art computer displays. CRT displays typically use a layer of phosphor which is deposited on a thin glass faceplate. These CRTs generate a picture by using one to three electron beams which generate high energy electrons that are scanned across the phosphor in a raster pattern. The phosphor converts the electron energy into visible light so as to form the desired picture. However, prior art CRT displays are large and bulky due to the large vacuum envelopes that enclose the cathode and extend from the cathode to the faceplate of the display. Therefore, typically, other types of display technologies such as active matrix liquid crystal display, plasma display and electroluminescent display technologies have been used in the past to form thin displays.
Recently, a thin flat panel display (FPD) has been developed which uses the same process for generating pictures as is used in CRT devices. These flat panel displays use a backplate including a matrix structure of rows and columns of electrodes. One such flat panel display is described in U.S. Pat. No. 5,541,473 which which is incorporated herein by reference. Typically, the backplate is formed by depositing a cathode structure (electron emitting) on a glass plate. The cathode structure includes emitters that generate electrons. The backplate typically has an active area surface within which the cathode structure is deposited. Typically, the active area surface does not cover the entire surface of the glass plate, a thin strip is left around the edges of the glass plate. The thin strip is referred to as a border or a border region. Conductive traces extend through the border to allow for electrical connectivity to the active area surface. These traces are typically covered by a dielectric film as they extend across the border so as to prevent shorting.
Prior art flat panel displays include a thin glass faceplate (anode) having a layer of phosphor deposited over the surface of the faceplate. A conductive layer is deposited on the glass or on the phosphor. The faceplate is typically separated from the backplate by about 1 millimeter. The faceplate includes an active area surface within which the layer of phosphor is deposited. The faceplate also includes a border region. The border is a thin strip that extends from the active area surface to the edges of the glass plate. The faceplate is attached to the backplate using a glass sealing structure which does not contain phosphor. This sealing structure is typically formed by melting a glass frit in a high temperature heating step. This forms an enclosure which is pumped out so as to produce a vacuum between the active area surface of the backplate and the active area surface of the faceplate. Individual regions of the cathode are selectively activated to generate electrons which strike the phosphor so as to generate a display within the active area surface of the faceplate. These flat panel displays have all of the advantages of conventional CRTs but are much thinner.
In order to maximize the display area for any given size of flat panel display, it is important to minimize the amount of area of the faceplate and the backplate which is required as a border. Typically, traces extend through the border such that the traces extend outside of the area enclosed by the seal to allow for connection to input, output, and power utilities.
Ceramic walls or "spacers" are currently used in assembly to separate the faceplate and the backplate in thin cathode ray tube (TCRT) displays. One of the most critical aspects of making supports invisible in the display is the mechanical placement of the supports in the correct location. Once the display is sealed and becomes a vacuum envelope, atmospheric pressure creates a significant load on the walls. This load permanently captures the walls in the location where they were the moment before the display was introduced to atmospheric pressure in the sealing process. Since this capture is permanent, it is critical that the walls remain in the correct location and orientation from the time the supports are placed in the display until the seal process is finished.
Prior art methods for supporting walls use wall supports or "feet" attached to both ends of each wall so as to make each wall self standing and help maintain perpendicularity of the walls with respect to the anode and the cathode. Conventional wall feet must reside in the border and do not extend into the active area surface. Thus, prior art methods require that the border be of sufficient size to accommodate wall feet. It is further required that the walls be perpendicular to the cathode and the faceplate such that they do not interfere with electron emission and reception. In the event that a wall becomes misaligned or tilted, the wall deflects emitted electrons, interfering with the operation of the display so as to cause visible defects on the display. Other types of wall feet include ceramic frames that capture the walls between slots, ceramic feet attached to the ends of the walls, and metal or glass clips that are clamped to the ends of the walls. Each of theses types of feet are attached to each end of each wall.
The process of making long ceramic walls is expensive and time consuming. Much of this time and expense is due to the extensive processes required to attach wall feet to the ends of each wall. Ceramic wall feet are typically formed by making ceramic bars which are attached to opposite sides of ceramic wafer by a process referred to as caning. The wafers are then sliced so as to form individual walls. The numerous process steps for forming and attaching feet are expensive, they are difficult, they take up a significant amount of time, they lower throughput rates and they lower yield. The process of making walls for displays having widths of six inches or more is particularly expensive and time consuming since large wafers having a diameter of 6 inches or more must be handled. The handling of the large wafers requires an extensive amount of expensive capital equipment for each size of wafer to be used. Moreover, specialized equipment is required for each size of display to assure that the walls are properly placed. This specialized equipment is expensive and the requisite set-up time for forming different sized displays adds expense and time to the manufacturing process.
It is further beneficial to reduce the required width of the border. In so doing, more display area is obtained for a given size of glass. Since the feet reside in the border region, and since the feet must be maintained at a distance from the active area surface of the display due to the fact that the cane material used to attach the feet to the wall has properties that can cause arcing near high electric field regions, the feet require a significant amount of border region. What is needed is a method which will decrease or eliminate the amount of border allotted for wall feet. This would allow for a larger display area to be formed over a particular size of glass plate.
Another prior art method for alignment of walls includes the mechanical restraint of the walls by a fixture which maintains each wall in proper alignment and position until the wall is bonded to the faceplate in a high temperature process step. This has been done in the past by tacking of each wall on one side thereof using glass frit. Typically, temperatures in the range of 450 degrees centigrade are used to melt the frit. These thermal process steps are lengthy, they decrease throughput, and they stress the surfaces of the faceplate and the backplate. Moreover, the high heat causes the surfaces of the display assembly to outgass (primarily the polyimide surfaces on the faceplate and the backplate). Furthermore, this outgassing contaminates the emitter surface, resulting in reduced display performance.
As yet another drawback, flat panel display fabrication processes are expensive and the manufacturing process is time consuming due in large part to the number of complex steps required in the bonding process. Moreover, prior art bonding processes are performed at high temperatures, resulting in outgassing and heat generated defects. This decreases yield and increases overall manufacturing cost. In addition, the numerous process steps take up a significant amount of time so as to cause low throughput rates. Hence, the high temperature processes associated with conventional bonding methods damages the active area surface of the display.
Thus, a need exists for a wall which does not require that feet be manufactured and attached to both ends thereof. A further need exists for a wall alignment and placement method which does not require a large border and which does not reduce the available active area surface. A further need exists for a flat panel display and a method for forming a flat panel display which allows for standardization of the tooling such that different tooling is not required for each size of display. The present invention meets the above needs.
USPTO Backgrounds
USPTO Backgrounds