Non-volatile memory devices (shortly, non-volatile memories) are commonly used in several applications that need the data stored in the memory device to be preserved even in absence of the power supply.
Within the class of non-volatile memories, electrically alterable memories, particularly electrically programmable and erasable memories, such as flash memories, have become very popular in applications in which the data to be stored are not immutable (as it might be case of, e.g., a consolidated microcode for a microprocessor), being instead necessary from time to time to store new data, or to update the data already stored.
Typically, a memory device includes a plurality of memory cells, arranged for example in rows and columns so as to form a matrix of memory cells (“memory matrix”).
Depending on the way the memory cells in the memory matrix are interconnected, two classes of flash memories can be identified: those having a so-called NOR architecture, or NOR Flash memories, and those having a so-called NAND architecture, shortly referred to as NAND Flash memories. Roughly speaking, in a NOR architecture the memory cells of a same matrix column are connected in parallel to a same bit line, whereas in a NAND architecture groups of memory cells of a same matrix column are serially interconnected so as to form respective strings (sometimes also referred to as “stacks”); several strings are connected, in parallel to each other, to a same bit line.
Compared to NOR Flash memories, NAND Flash memories are more compact (a lower number of electrical contacts in the memory matrix is required), and they are also better suited for applications such as file storage.
In the NAND architecture, the memory space is ideally partitioned into a plurality of memory pages, each page corresponding to a group of memory cells that, in operation, are accessed, i.e., read or written simultaneously, i.e., in parallel to each other. The number of memory cells in each group determines the size (i.e., the number of bits) of the memory page. Memory pages of 8192 (8K) cells are rather typical, but larger memory pages are also encountered, for example of 16384 (16K) cells.
A circuit arrangement referred to as “page buffer” is typically provided in a NAND flash memory for managing the operations of reading the information stored in the memory cells of a selected memory page, or altering the content of the memory page (i.e., writing new information thereinto, or erasing the memory page). In very general terms, the page buffer includes a buffer register of size equal to that of the memory page, wherein data read (in parallel) from the memory cells of a selected page are temporarily stored, before being serially outputted in chunks of, e.g., eight or sixteen bits, depending on the number of I/O terminals of the memory; similarly, when data are to be written into the memory, the page buffer is replenished with data received serially in said eight- or sixteen-bits chunks, and, after the page buffer has eventually been filled, the data are written in parallel into the memory cells of a selected memory page.
The basic operations that a page buffer usually allows performing on the memory cells are a “page read” (an operation involving reading data from a selected memory page), a “page program” (writing data into a selected memory page), and an “erase” operation, wherein the information content of the memory cells is erased.
Memory devices capable of storing one bit of information per memory cell are referred to as “two-level” memories, whereas memory devices capable of storing more than just one information bit per memory cell are referred to as “multi-level” memories. In particular, four-level memories are known, whose memory cells can be programmed in any one of four different programming states, each one associated with a corresponding logic value of the pair of bits they are adapted to store. Usually, the programming state of a memory cell is defined by the threshold voltage value of a MOS transistor included in the memory cell; in a memory cell adapted to store two bits, the threshold voltage values of the MOS transistor included in the generic memory cell may take one of four different values (or values within four different ranges of values).
A typical choice is to associate the values “11”, “10”, “01” and “00” to increasing threshold voltage values, the logic value “11” being associated with the programming state having the lowest threshold voltage value (erased state), and the other logic values being associated, in succession, with programming states having increasing threshold voltage values. In this case, reading data stored in a two-bit memory cell may require up to three read accesses thereto, using different references.
A solution known in the art for reducing the number of read accesses necessary to retrieve the data stored in a two-bit memory cell consists of partitioning the memory space in such a way that the data stored into each single memory cell belongs to two memory pages (each page corresponding to one bit among the two stored in the memory cell) and using a different correspondence between stored logic values and programming states, exploiting the Gray coding. In this way, the stored logic values are associated with the programming states (ordered in increasing threshold voltage values) according to the binary sequence “11”, “10”, “00”, “01”, the logic value “11” being associated to the erased state, and the other logic values being associated in succession with programming states having increasing threshold voltage values. A distinctive advantage of using the Gray coding is that “adjacent” programming states (in terms of threshold voltage values) correspond to logic values that differ from each other by only one bit. This feature implies a series of advantages.
An example of page buffers for NAND memories adopting the Gray coding is for example provided in the published U.S. Patent Application 2002/0126531, which is incorporated by reference.
A page buffer for a two-bit memory typically includes a plurality of read/program units, each one adapted to be operatively associated with a selected memory cell to be read or programmed. Each read/program unit includes at least a pair of volatile storage elements, each volatile storage element of the pair corresponding to one bit of the pair each memory cell is adapted to store. The page program operation performed by such a page buffer involves the transfer of data between the two volatile storage elements, for example during a data load procedure of the datum to be programmed. For this purpose, the outputs of each of said two volatile storage elements are coupled with a corresponding common node, that requires to be brought to the supply voltage and to be kept into a floating condition before the execution of the abovementioned data transfer.
It has been observed that the presence of such common node may cause problems during the data transfer between the volatile storage elements.
In fact, precharging the common node to the supply voltage and maintaining said voltage while the common node is kept in a floating condition may be unsafe for different reasons. For example, the voltage of the common node may fall, because of unavoidable leakage effects. Moreover, when the common node is in the floating condition, its voltage may vary in an unpredictable way, since it is strongly affected by the voltage of other signal lines in the page buffer, capacitively coupled therewith. These drawbacks may affect the correct working of the page buffer, because they may invalidate the page program operations.
Furthermore, every time the common node has to be charged/discharged, it may be necessary to move a substantial amount of electrical charge, wasting electrical power. In fact, assuming that each common node has associated therewith a capacitive load of the order of 50-100 fF, and assuming that the page buffer includes 16K-32K read/program units, a similar number of common nodes have to be charged in parallel, and the average current consumption (with a charging time of 100-200 nsec and with the supply voltage equal to 3 Volts) may vary from 12 mA to 100 mA.
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