1. Field of the Invention
The present disclosure relates to semiconductor memory devices and, more particularly, to memory devices employing cell diodes.
2. Description of Related Art
Non-volatile memory devices have an advantage in that data stored in such memory cells does not vanish when electrical power is not supplied to the memory cells. The non-volatile memory devices mainly employ flash memory  cells having a stacked gate structure. The stacked gate structure includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked on a channel region. Therefore, in order to enhance reliability and program efficiency of the flash memory cells, film quality of the tunnel oxide layer should be improved and a coupling ratio of the flash memory cell should be increased.
Recently, novel non-volatile memory cells such as phase change memory cells have been proposed instead of the flash memory cells. Methods of fabricating the phase change memory cells are disclosed in U.S. Pat. No. 6,605,527 B2 to Dennison et al., entitled “Reduced Area Insertion Between Electrode and Programming Element”. According to Dennison et al., the phase change memory cells are disposed at cross points between a plurality of bit lines and a plurality of word lines. In addition, each of the phase change memory cells includes a phase change material pattern and a cell diode, which are electrically connected in series. An N-type semiconductor of the cell diode is electrically connected to the word line, and the phase change material pattern is electrically connected to the bit line. The process for forming the word lines and the cell diodes includes a first process for sequentially forming a first N-type semiconductor layer, a second N-type semiconductor layer having a lower impurity concentration than the first N-type semiconductor layer and a P-type semiconductor layer on a P-type semiconductor substrate using an epitaxial technique and a second process for forming a metal silicide layer on the P-type semiconductor layer. 
The metal silicide layer, the P-type semiconductor-layer, the second N-type semiconductor layer and the first N-type semiconductor layer are patterned to form a plurality of parallel N-type word lines disposed on the P-type semiconductor substrate as well as second N-type semiconductor patterns, P-type semiconductor patterns and metal silicide patterns which are sequentially stacked on the respective N-type word lines. In this case, the P-type semiconductor substrate may be over-etched while the first N-type semiconductor layer is etched to form the word lines. This is because the P-type semiconductor substrate may not have an etch selectivity with respect to the first N-type semiconductor layer. As a result, deep trench regions having a high aspect ratio may be formed between the word lines. Such deep trench regions may not be completely filled with an isolation layer to be formed in a subsequent process. That is, the high aspect ratio of the deep trench regions may cause voids or seams in the isolation layer.
In addition, the second N-type semiconductor patterns, the P-type semiconductor patterns and the metal silicide patterns on the word lines are etched using mask patterns crossing over the word lines as etching masks, thereby forming a plurality of cell diodes and a plurality of metal silicide electrodes which are two-dimensionally arrayed and separated from each other. In this case, the word lines may also have a low etch selectivity with respect to the second N-type semiconductor patterns. As a result, the word lines may be over-etched while the second N-type semiconductor patterns are etched in order to form the cell diodes. Therefore, the word lines between the cell diodes may  be recessed, as shown in FIG. 2 of the U.S. Pat. No. 6,605,527 B2 to Dennison et al. Over-etching of the word lines may cause an increase in the electrical resistance of the word lines. According to Dennison et al., pockets (200 of FIG. 2) heavily doped with impurities are formed on the recessed regions of the word lines to prevent the electrical resistance of the word lines from being increased.
Each word line may act as a base region of a lateral bipolar transistor, which is parasitically formed between the adjacent phase change cells. In this case, if the electrical resistance of the word lines (that is, the base region) increases, current gain of the parasitic lateral bipolar transistor may increase. When the current gain of the parasitic lateral bipolar transistor increases, a voltage induced to a bit line electrically connected to a selected phase change cell may be temporarily unstable during a read mode for reading data of the selected phase change cell. This is because a large charging current corresponding to a collector current of the parasitic bipolar transistor may flow through a bit line of a non-selected phase change cell adjacent to the selected phase change cell. As a result, access time for reading out data stored in the selected phase change cell may increase to degrade characteristics of the phase change memory device.
Further, in the event that the current gain of the parasitic lateral bipolar transistor increases, the parasitic lateral bipolar transistor may operate during a program mode for storing data into the selected phase change cell to increase collector current flowing through the bit line of the non-selected phase change  cell adjacent to the selected phase change cell. As a result, the non-selected phase change cell may also be programmed to alter the data of the non-selected phase change cell.
In order to decrease the electrical resistance of the word lines in a limited area, a thickness of the first N-type semiconductor layer can be increased. However, in the event that the thickness of the first N-type semiconductor layer is increased, the aspect ratio of the trench region may increase to degrade the reliability of the isolation layer in the trench region.
USPTO Backgrounds
USPTO Backgrounds