The present invention relates to an arrangement for adapting a serial interface of a data processing system to the data transmission speed of a communication partner.
Individual data processing systems of a computer network system frequently have different clock frequencies and resulting data transmission speeds. One of the main reasons is that the components of the computer network system partly operate using completely different microprocessors of varied manufacturers. The communication of these individual data processing systems with one another via serial interfaces, however, requires all communication partners to be adapted to use the same data transmission speed.
In German Patent No. 23 55 533 and German Published Unexamined Patent Application No. 31 24 163, receivers for data signals were suggested that have a change detector for the data transmission speed. A disadvantage of these systems is that the different data transmission speeds of the communication partners must be known and for each occurring data transmission speed a separate recognition circuit is required.
In order to avoid these disadvantages, the circuit for the retrieval of clock pulses according to German Published Unexamined Patent Application No. 26 28 581 uses a circuit arrangement that can adjust itself individually to data transmission speeds in a frequency range of 1:8. This frequency range is, however, relatively narrow and is suitable only for the adaptation to fluctuations around a fixed frequency. In addition, the circuit arrangement has an enormous number of assemblies and components and requires many expensive analog components, such as collators, filters, etc., so that during manufacturing/servicing extensive compensating measures are required. Therefore, a good long-term stability can hardly be expected.
Based on the above state of the art, it is an objective of the present invention to provide an arrangement for the individual adaptation of a serial interface of a data processing system to the data transmission speed of a communication partner that has the advantage of a simple construction of largely digital components and permits a simple, fast, secure, and exact adjustment over a wide frequency range, of the data processing system to the data transmission speed.
This and other objects are achieved in the present invention by providing, in an arrangement for adapting a serial interface of a data processing system to the data transmission speed of a communication partner, a recognition circuit for recognizing the data speed. A microprocessor controls the recognition circuit and a clock frequency generator outputs a clock frequency signal to the microprocessor. An adjustment circuit adjusts the clock frequency generator to produce an adjusted clock frequency signal which corresponds to a matching data transmission speed which matches the data transmission speed from the communicating partner. A derivation circuit in the microprocessor derives the matching data transmission speed from the adjusted clock frequency signal.
Advantages of the invention are that an arrangement for the individual adaptation of a serial interface of a data processing system to a data transmission speed of a communication partner is provided that has a simple construction from largely digital components. It also ensures a wide frequency range of 1:200 or more, and an exact, fast and secure adjustment of the interface to the data transmission speed of the communication partner without an extensive control procedure
Further objects, features, and advantages of the present invention will become more apparent from the following description when taken with the accompanying drawings which show, for purposes of illustration only, an embodiment in accordance with the present invention.
USPTO Backgrounds
USPTO Backgrounds