Exemplary embodiments of the present invention relate to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit (IC) having a chip-on-chip structure.
A wire bonding technology has been used to integrate a control semiconductor IC and a main semiconductor IC into a single package. However, the wire bonding technology imposes a limitation on increasing the operating speed of the semiconductor ICs.
To address such a concern, a chip-on-chip package technology may be used instead, which stacks a control semiconductor IC and a main semiconductor IC in a vertical direction. The chip-on-chip package technology is a package technology which identifies positions of both bump pads between a control semiconductor IC and a main semiconductor IC, and directly connects both bump pads without the use of wires. This chip-on-chip package technology may increase an operating frequency due to high-speed signal transmission, reduce total power consumption, and minimize/reduce the overall area of the chip.
However, if the chip-on-chip package technology is applied, the bump pad size of the semiconductor IC may become too small (e.g., 30-μm×30-μm) to properly perform a probe test on the bump pads in a test mode. Therefore, in order to achieve a normal probe test, a probe test pad having a size of about 60-μm×60-μm may need to be separately provided.
USPTO Backgrounds
USPTO Backgrounds