1. Field of the Invention
The present invention relates to semiconductor device trench isolation structures, processes for their manufacture and methods for their operation. In particular, the present invention pertains to polysilicon filled trench isolation structures that include a polysilicon contact for supplying a bias voltage. The trench isolation structure, as well as process of manufacture and method of operation thereof, can be used in association with complementary metal-oxide semiconductor (CMOS), bipolar, and combination bipolar and CMOS (BiCMOS) semiconductor devices.
2. Description of the Related Art
It is often desirable to electrically isolate semiconductor devices from one another in an integrated circuit. One way to accomplish such isolation is by utilizing insulator filled vertical trenches in the semiconductor substrate to circumscribe the semiconductor devices, thereby obstructing lateral electrical leakage. See, for example, S. M. Sze, VLSI Technology, 489-490 (2nd edition 1988). In some instances, particularly with high voltage semiconductor devices, a "buried" horizontal insulator layer in the semiconductor substrate is employed. The "buried" horizontal insulator layer is intersected with the vertical trenches to completely surround and electrically isolate the high voltage semiconductor devices.
FIG. 1 shows a cross-section of a conventional semiconductor device trench isolation structure 2 that includes a semiconductor substrate 4 and an isolation trench 6. Isolation trench 6 contains therein a multi-layered trench fill that includes a layer of trench lining oxide 8, a layer of trench lining silicon nitride 10 and trench fill polysilicon layer 12. Insulating layer 14 covers the surface of semiconductor substrate 4 and isolation trench 6 and serves to isolate trench fill polysilicon layer 12 from conductive layers deposited in subsequent processing.
FIG. 2 shows a conventional silicon-on-insulator (SOI) semiconductor device trench isolation structure that includes a base silicon substrate 16 with a buried horizontal insulator layer 18 (typically oxide) formed on its upper surface. An active silicon layer 20 is formed on the buried horizontal insulator layer 18. Isolation trench 22 extends from the surface of the active silicon layer 20 to the buried horizontal insulator layer 18, thereby completely electrically insulating a portion 24 of the active silicon layer 20 from the remainder of the structure.
Typically the isolation trench 22 includes a layer of trench lining oxide 26 (i.e. the outer layer of the isolation trench) formed on the active silicon layer sidewalls that surround the isolation trench. Isolation trench 22 may also include a layer of trench lining silicon nitride 28 (i.e. the middle layer of the isolation trench) formed over the layer of trench lining oxide 26. Trench fill polysilicon layer 30 (i.e. the innermost layer of the isolation trench) occupies the remainder of the isolation trench 22. Insulating layer 32 isolates the trench fill polysilicon layer from conductive layers deposited in later processing.
The electrical isolation provided by conventional trench isolation structures can be less than ideal. For example, it has been found, upon initial biasing of certain high voltage semiconductor devices, that the devices may pass current at a voltage less than the designed breakdown voltage. Upon continued stress and passage of current, the breakdown voltage will then "walk out" to its design breakdown voltage. This unstable electrical isolation behavior may be associated with high electric fields across conventional isolation trenches and/or avalanche breakdown at the corners of conventional trench isolation structures.
Thus, there is a need in the art for a semiconductor device trench isolation structure, a process for its manufacture and a method for its operation that provides for stable electrical isolation even under high operating voltage conditions. The semiconductor device trench isolation structure should also be relatively compact in order to avoid increasing die size.
USPTO Backgrounds
USPTO Backgrounds