1. Field of the Invention
The present invention relates to a semiconductor device which includes a circuit including a semiconductor element such as a transistor, and a method for manufacturing the semiconductor device. In particular, the present invention relates to a circuit structure and an element structure of a static random access memory (SRAM) and a method for manufacturing the SRAM.
In this specification, a “semiconductor device” generally refers to a device which can function by utilizing semiconductor characteristics; a memory device, an electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all included in the category of the semiconductor device.
2. Description of the Related Art
A signal processing circuit such as a central processing unit (CPU) has a variety of configurations depending on its application and is generally provided with some kinds of memory devices such as a register and a cache memory as well as a main memory for storing data or a program. A register has a function of temporarily holding data for carrying out arithmetic processing, holding a program execution state, or the like. In addition, a cache memory is located between an arithmetic circuit and a main memory in order to reduce access to the main memory and speed up the arithmetic processing.
In a memory device such as a register or a cache memory, writing of data needs to be performed at higher speed than in a main memory. Thus, a flip-flop or the like is used as a register, and a static random access memory (SRAM) or the like is used as a cache memory, for example. That is, a volatile memory device in which data is erased when supply of power supply potential is stopped is used for such a register, a cache memory, or the like.
A typical example of a volatile memory device is a dynamic random access memory (DRAM). A DRAM stores data in such a manner that a transistor included in a storage element is selected and charge is stored in a capacitor. Thus, when data is read from a DRAM, charge in a capacitor is lost, so that another writing operation is necessary whenever data is read. Moreover, since leakage current (off-state current) flows between a source and a drain of a transistor included in a memory element when the transistor is in an off state, charge flows out of the transistor even if the transistor is not selected, which makes a data holding period short. For that reason, another writing operation (refresh operation) is necessary at predetermined intervals, and it is difficult to sufficiently reduce power consumption. Furthermore, since stored data is lost when power supply stops, an additional memory device using a magnetic material or an optical material is needed in order to hold the data for a long time.
Another example of a volatile memory device is an SRAM. An SRAM retains stored data by using a circuit such as a flip-flop and thus does not need refresh operation. This means that an SRAM has an advantage over a DRAM. However, cost per storage capacity is increased because a circuit such as a flip-flop is used. Moreover, as in a DRAM, stored data in an SRAM is lost when power supply stops.
An SRAM circuit includes an inverter such as an NMOS inverter or a CMOS inverter.
An SRAM circuit including an NMOS inverter includes four transistors and two resistors. In this case, the SRAM circuit can be formed using n-channel transistors and resistors. Since a p-channel transistor is not needed, the area of a memory cell can be reduced. However, current flows through the resistor when the inverter is turned on; therefore, power consumption is increased.
In contrast, an SRAM circuit including a CMOS inverter includes six transistors; therefore, the area of a memory cell is large. However, only off-state current of a transistor flows when the inverter is turned on, so that power consumption is very low.
Power consumption of a semiconductor device is substantially equal to the sum of power consumed in an operation state and power consumed in a stop state (hereinafter referred to as standby power) of the semiconductor device.
The standby power can be classified into static standby power and dynamic standby power. The static standby power is power consumed by generation of leakage current between a source and a drain, between a gate and the source, and between the gate and the drain in a state where voltage is not applied between the electrodes of a transistor in the semiconductor device, that is, in a state where voltage between the gate and the source is approximately 0 V. On the other hand, the dynamic standby power is power which is consumed when voltages of various signals such as a clock signal or a power supply voltage continues to be supplied to a circuit in a standby state.
Further, in order to increase the operation speed of a semiconductor device, a microfabrication technique has been developed. As microfabrication of a semiconductor device such as a transistor advances, the channel length of the transistor is shortened and the thicknesses of various insulating layers typified by a gate insulating layer are decreased. Therefore, leakage current of the transistor tends to be increased and accordingly the static standby power is increased.
As described above, a memory device including an SRAM can operate at high speed and, like a DRAM, does not require data refresh operation. Further, an SRAM including a CMOS inverter consumes very low power. However, the area occupied by a memory cell is large because the SRAM including a CMOS inverter includes many transistors.
The area of a memory cell can be reduced by devising a circuit layout (see Patent Document 1, for example).
Further, circuit patterns have been miniaturized in accordance with the scaling law, but it seems that a design rule of 100 nm or less is difficult to achieve. One of the reasons is that in a transistor having a channel length of 100 nm or less, leakage current caused by a punch-through phenomenon is likely to flow due to a short-channel effect and the transistor becomes incapable of functioning as a switching element. In order to prevent the punch-through current, a silicon wafer may be doped with an impurity with a high concentration; however, the doping causes a problem in that the junction leakage current easily flows between a source and the substrate or between a drain and the substrate.
Against such a problem, a method is suggested for reducing an area occupied by a memory cell and also maintaining the effective channel length of a transistor by forming a three-dimensional transistor in a semiconductor device so as not to cause a short-channel effect. One example is a structure in which a U-shaped vertically long groove portion is formed in a region where a channel portion of a transistor is formed, a gate insulating film is formed on a wall surface of the groove portion, and a gate electrode is formed so as to fill the groove portion (see Non-Patent Document 1).
A transistor having a channel portion of such a structure has a long effective channel length because current flows between a source region and a drain region via an indirect route across the groove portion. Thus, an effect of reducing the area occupied by a transistor and suppressing a short-channel effect can be obtained.
USPTO Backgrounds
USPTO Backgrounds