1. Field of the Invention
The present invention relates to an analog signal extracting circuit used for sampling an analog signal.
2. Description of the Related Art
FIG. 2 is a circuit diagram showing an arrangement of an analog signal extracting circuit known by the present inventor.
12 denotes a transmission gate for sampling an analog input voltage applied to an input terminal 11. The sampling of the analog voltage is carried out each time the transmission gate 12 becomes conductive.
At the next stage of the transmission gate 12, a differential amplifier 14 and a buffer 15 constitute a voltage follower circuit 13. The voltage follower circuit 13 serves to supply at an output terminal 16 a voltage equal to the input voltage sampled by the transmission gate 12.
The differential amplifier 14 includes p-channel MOS transistors Q11 and Q12 constituting a current mirror circuit 17, an n-channel MOS transistor Q13 serving as an input transistor, an n-channel MOS transistor Q14 serving as an output transistor, and an n-channel MOS transistor Q15 serving as a constant current source. The sources of the MOS transistors Q11 and Q12 are connected to a constant voltage source VDD. The gate of the MOS transistor Q15 is connected to a bias power supply Vb11 and the source of the MOS transistor Q15 is grounded.
The buffer 15 includes n-channel MOS transistors Q16 and Q17 connected in series between the constant voltage source Vdd and the ground. A contact point between the MOS transistors Q16 and Q17 is connected to the output terminal 16 and the gate of the MOS transistor Q14 of the differential amplifier 14. The gate of the MOS transistor Q16 which serves as an input transistor for receiving an output of the differential amplifier 14, is connected to the drain of the MOS transistor Q14 which serves as an output transistor of the differential amplifier 14. The source and the back gate of the MOS transistor Q16 are connected to the output terminal 16 to constitute a source follower circuit. The gate of the MOS transistor Q17 is connected to a bias power supply Vb12.
The analog signal extracting circuit basically functions as follows.
The input voltage which has passed the transmission gate 12 is applied to the gate of the MOS transistor Q13 which serves as an input transistor of the differential amplifier 14. Depending on variation of the input voltage, the drain voltage of the MOS transistor Q14 varies. The drain voltage of the MOS transistor Q14 is applied to the gate of the MOS transistor Q16 of the buffer 15. Depending on variation of the drain voltage of the MOS transistor Q14, that is, depending on variation of the voltage inputted to the differential amplifier 14, the MOS transistor Q16 varies its resistance when it is on, that is, when it is conductive. As a result, the MOS transistor Q16 outputs a voltage equal to the input voltage sampled at the transmission gate 12 from the output terminal 16.
In the foregoing analog signal extracting circuit, in a case where a positive voltage input to the differential amplifier 14 is lower than the threshold voltage of the enhancement type n-channel MOS transistor Q13, the MOS transistor Q13 is in an off state so that the differential amplifier does not function. In such a condition, the differential amplifier 14 cannot function normally and the output voltage is restricted when the input voltage is lower than the threshold voltage of the MOS transistor Q13. Hence, the minimum value of the output voltage obtained at the output terminal 16 depends on the threshold voltage of the MOS transistor Q13.
On the other hand, the maximum value of the voltage output at the output terminal 16 depends on the threshold voltage of the MOS transistor Q16 constituting the buffer 15. That is, the output voltage at the output terminal 16 is limited to be lower than the resultant voltage of subtracting the threshold voltage of the MOS transistor Q16 from the constant voltage source Vdd.
This limitation brings about a shortcoming for the normal functioning of the circuit in that an effective range of the input and output voltages with respect to the given constant voltage source VDD is made narrower accordingly.
USPTO Backgrounds
USPTO Backgrounds