1. Field of the Invention
The present invention relates generally to a method for making an improved trench for a semiconductor memory device and the device formed thereby and, more particularly, to a method for fabricating a low leakage trench for a Dynamic Random Access Memory (DRAM) cell wherein trench parasitic sidewall leakage currents from a bitline contact to the storage node and from the storage node to the substrate are eliminated by an insulating or diffusion ring surrounding an upper portion of the trench.
2. Description of the Prior Art
There are many DRAM applications where it is important to maximize the retention time of the cell. In particular, applications depending on battery power for the system would benefit from a DRAM cell which did not need to be refreshed very often. Very Large Scale Integrated (VLSI) DRAM cells in the time frame of 4Mbit and beyond require trench storage capacitors in order to meet high density requirements. DRAM cells having a storage capacitor disposed in a trench formed in a semiconductor substrate are known in the art. For example, U.S. Pat. No. 4,688,063 assigned to the same assignee as the present invention, which patent is hereby incorporated by reference, discloses a substrate plate trench (SPT) DRAM cell which utilizes a trench storage capacitor formed in a semiconductor substrate. A portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench forms the other electrode of the storage capacitor. The SPT DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The trench capacitor extends from the surface of the well, through the well and lightly doped substrate portion, into the heavily doped portion of the substrate. The capacitor electrode disposed in the trench is directly connected to the source/drain of the access transistor.
Trench DRAM cells suffer from two main disadvantages resulting from a parasitic sidewall leakage current. The two disadvantages are the trench parasitic sidewall leakage through the trench sidewalls (1) from the bitline contact to the storage node and (2) from the storage node to the substrate. The latter leakage mechanism is described in Lu et al., "A Substrate Plate Trench Capacitor (SPT) Memory Cell for Dynamic RAM's", IEEE J. of Solid State Circuits, Vol. SC-21, No. 5, pp. 627-633 (1986) and Noble et al., "Parasitic Leakage in DRAM Trench Storage Capacitor Vertical Gated Diodes", IEDM Tech. Digest, pp. 340=343 (1987).
To reduce these leakage currents, the DRAM cell of U.S. Pat. No. 4,688,063 includes an n-well interposed between the substrate plate and the access transistor electrodes. As described in Cottrell et al., "N-Well Design for Trench DRAM Arrays" IEDM Tech Digest, pp. 584-587, 1988, to further increase the immunity of an SPT DRAM cell to leakage current an n-well with a doping profile that monotonically decreases with depth can be utilized. However, these improvements do not significantly reduce the trench parasitic sidewall leakage currents.
Another way to reduce the parasitic sidewall leakage currents is by increasing the thickness of an oxide collar formed within an upper portion of the trench. However, increasing the collar thickness reduces the contact area available for contact, increases the RC time constant of the storage node polysilicon and introduces process constraints.
A further way to reduce the sidewall leakage currents is disclosed in a co-pending application, assigned to the same assignee as the present application, Ser. No. 696,691, filed May 7, 1991. The application discloses an SPT DRAM cell which includes a buried oxide collar surrounding an upper portion of the trench of the storage capacitor and extends from the n-well through the n-well and into a lightly doped portion of the substrate. The oxide collar is contiguous with an insulating layer formed within the trench on all sides. However, since the oxide collar does not extend to the surface of the substrate, this DRAM cell does not reduce the leakage current from the storage node to the bitline contact. Moreover, by extending the oxide collar through the n-well and into the lightly doped substrate portion, this DRAM cell results in additional leakage problems. The method for fabricating this DRAM cell includes forming a thick oxide layer on an upper portion of the substrate. The oxide layer is then buried within an upper portion of the substrate by conventional epitaxial overgrowth technology. A trench is then dug down to and through the buried oxide layer and the substrate such that the oxide layer completely surrounds an upper portion of the trench.
U.S. Pat. No. 4,987,470 discloses a DRAM device which includes a field shield conducting layer placed inside a trench to prevent parasitic sidewall leakage through the trench sidewalls. The conductive shield layer is disposed between the trench sidewall and the storage node with insulating material between them. The conductive layer shields the field from the storage polysilicon. However, the use of the shield layer within the trench does not substantially prevent parasitic leakage currents. Thus, there is a need to develop a DRAM cell that significantly reduces trench parasitic sidewall leakage currents from the bitline contact to the storage node and from the storage node to the substrate.
USPTO Backgrounds
USPTO Backgrounds