This application claims priority to Italian Application Serial Number 2002A000794, filed Sep. 12, 2002.
1. Field of the Invention
The invention relates to voltage converters. More particularly, the invention relates to the management and control of an on-chip voltage down-converter that steps down an external power supply to a lower, internal power supply for memory devices.
2. The State of the Art
Semiconductor systems involve circuitry requiring a broad range of power. Microprocessors typically operate at higher voltage levels than memories, for example. In order to make an external power source compatible with both a microprocessor and its memory, for example, the voltage from the external power supply must be down-converted.
FIG. 1 illustrates one example of a prior art voltage down-converter. Amplifier 2 drives the gate of p-channel metal-oxide semiconductor (MOS) transistor 4. The source of transistor 4 connects to external power source 6 and the drain of transistor 4 connects to load circuit 8. The voltage across load circuit 8 drops as current consumption in circuit 8 increases, and when the voltage drops below that of reference generator circuit 10 then amplifier 2 lowers the voltage across the gate of transistor 4. Transistor 4 increases in conductivity as its gate voltage decreases and consequently supplies load circuit 8 with current.
FIG. 2 illustrates another example of a prior art voltage down-converter. N-channel MOS transistor 20 has a low threshold voltage and is configured as a source follower. In one example driver transistor 20 is a natural MOS built on a substrate without a special implant and with a very large aspect ratio (W/L). Replica transistor 22 is coupled to driver transistor 20 and has a smaller aspect ratio than transistor 20. Amplifier 24 and resistors 26 complete a control loop with transistor 22. Amplifier 24 controls the gate of transistor 22 and keeps the voltage at node 28 in a desired range. Consequently transistor 20 provides current through node 30 when voltage at node 28 drops below a predetermined level.
FIG. 3 illustrates a more detailed version of the voltage converter in FIG. 2. Replica circuit 40 has a similar function to that of transistor 22 in FIG. 2. Stand-by circuit 42 and active circuit 44 perform the function of driver transistor 20 in FIG. 2. The prior art voltage converter in FIG. 3 has two operation modes: stand-by and active. In stand-by mode, current leakage to the load is very low. In active mode the transistors are on and provide up to the maximum level of current.
One problem with the aforementioned designs is the need for perfect matching among the driver and reference parts. Another problem is that temperature and process variations must be compensated by the replica circuit. Also, a reference circuit is always on since the follower needs a bias to operate. Finally, problems arise in the prior voltage down-converters while switching between active and stand-by mode. The prior voltage down-converters may fail to achieve a good response to the current step. The prior voltage down-converters may also have dangerous voltage spikes while switching modes.
The invention provides a system to manage the switching between active to stand-by transition and stand-by to active transition. The system to manage switching between active and stand-by and stand-by to active modes has two transitions. The first transition is the stand-by to active transition. In one embodiment, the load current for the internal, stepped-down power is initially furnished by a load capacitor, acting as a charge tank, on the internal power node. Prior to entering active mode, a replica transistor for the active mode is biased to charge a capacitor. When the voltage at the internal power supply node drops to a determined level, a switch biases the driver transistor to the node with the capacitor that was charged by the replica transistor, thus activating the driver transistor and increasing the current to the load circuit.
The second transition of the system is the active to stand-by transition. The transition is indicated by the fall of an enable signal. In one embodiment, a delay signal is interjected between the fall of the enable signal and the time at which stand-by mode is entered. The delay signal provides time for a driver transistor gate to be discharged and a node to be charged towards stand-by values. Comparators charge and discharge the gate and node as long as the delay signal is high. A switch disconnects the driver transistor from the power supply node when the enable signal falls so that current stops flowing from the driver transistor while the comparator discharges the gate of the driver transistor. The system enters stand-by mode at the end of the delay signal.
USPTO Backgrounds
USPTO Backgrounds