Phase-locked loop (PLL) circuits and delay-locked loop (DLL) circuits are used in clock and data recovery (CDR) circuits. PLL circuits are used in systems where clock and data signals are recovered from a single serial stream of data. Ethernet, Fibre Channel and synchronous optical networking and synchronous digital hierarchy (SONET/SDH) communication systems are examples of systems that typically use PLL circuits in CDR circuits.
Traditional CDR circuits use a PLL (which includes a frequency detector, phase detector, charge pump, and a voltage-controlled oscillator (VCO)) to generate a clock signal from a received data signal and a reference frequency, such as the output from a crystal oscillator. PLL circuits can adjust for both changes in frequency and phase between the VCO output frequency and the data signal to lock the VCO to the received data signal. The frequency detector and the VCO often require a significant portion of the integrated circuit area when used to implement the CDR circuit. In addition, the VCO consumes a significant portion of the power required by a traditional CDR circuit that uses a PLL.
Traditional DLL circuits use a controllable delay line to adjust the phase of a clock source with respect to the data signal that the DLL circuit is trying to recover. Traditional DLL circuits cannot accommodate a frequency difference between disparate clock sources. Accordingly, a traditional DLL circuit is inappropriate for communication systems with multiple data channels that originate from different sources. Thus, present solutions for communication systems with co-located asynchronous data lines often employ a PLL based CDR circuit for each data line or channel.
For example, U.S. Pat. No. 7,197,102, hereinafter the '102 patent, describes a CDR circuit with a DLL adapted to recover data from a data stream and a PLL in communication with the DLL adapted to recover a clock signal from the data stream. The CDR circuit employs a DLL to separate the data retiming process from a clock signal recovery function, in which the clock signal is extracted from the data channel by a PLL. The PLL extracts the clock information from a noisy serial data stream, while the DLL performs data synchronization in the phase domain. While, the '102 patent shows a single PLL circuit that supports clock recovery for four different data channels, the '102 patent teaches away from methods using multiphase because multiphase operation is believed to result in poor jitter performance.
Therefore, it would be desirable to implement an effective CDR circuit with improved jitter performance, as well as reduced circuit area and power requirements for communication systems with co-located and asynchronous data channels.
USPTO Backgrounds
USPTO Backgrounds