The development of the application of integrated circuits shows that more complex functions are to be realized but there are limitations of the number of functions realizable on a single chip. Therefore, technologies for stacking of two or more dies with several functions and methods for the mechanical and electrical interconnection with one another or with a base substrate which is the basis for stacking and for mounting on a PCB (Printed Circuit Board) have been developed.
Several technologies for contacting different chips are known. Conventional technologies are using chip and wire bonding for contacting the dies electrically. These are known processes with well-known parameters. Using these technologies for stacked dies (FBGA: fine ball grid array) the chips are placed one over another and the contacts of the dies are connected with corresponding contact pads on the substrate by wire loops performed by bonding.
For this wire bonding it is necessary to reroute the bond pads, which are typically arranged in a row at the die center, to the edge of the die, to avoid long wire bond loops (electrical performance). The rerouting (redistribution layer, RDL) is typically a metal line made of copper (basis metal), nickel (covering layer) and gold (suitable for contacts). It can be built by electro- or electroless plating.
According to FIG. 1 (prior art), a first die 1 is bonded to the substrate or interposer board 2 by chip bonding. This can be performed by positioning an adhesive 3 between the first die 1 and the substrate 2. Such adhesive 3 can be a tape with an adhesive coating on both sides. Then the bond pads 4 of the first die 1 are connected with contact pads 5 on the substrate with wire loops 6 by wire bonding.
Now a distance element or spacer 7 must be mounted on the top side of the first die 1. This is possible with known technologies like die bonding with adhesive 8 or a tape. The spacer 7 is necessary for protecting the wire loop 6 between the bond pad 4 on the first die 1 and the contact pad 5 on the substrate 2. The spacer 7 can be a silicon die, an adhesive tape with a sufficient thickness or any other suitable material, but the dimensions of the spacer 7 must be smaller than the dimensions of the die 1.
After this step, a next die 9 can be mounted on the spacer 7 with adhesive 10 or tape and then the same connecting procedure must be performed like for the first die 1 including connecting the bond pads 11 on the second die 9 with contact pads 5 on the substrate 2 by wire loops 12. The stacked structure is now protected (backside- and edge protect) by a mold encapsulant 13. The substrate 2, opposite the stacked dies 1, 9 is provided with solder balls 14 which are electrically connected (normally soldered) to the contact pads 5 on the substrate 2.
It seems to be clear that this is a very expensive technology (serial processes with high accuracy), even in case that more than two dies are stacked.
The high number of interfaces (due to the spacer) results in a lower processing yield. Additionally, the top die has to be bonded on overhang, which is a critical process for very thin dies. These are needed because the absolute height of the package is increased by the spacer, but the height restrictions of stacked packages nevertheless have to be fulfilled. Furthermore, the reliability (e.g., moisture resistance) is a critical aspect due to the high number of interfaces if a spacer is used in a wire-bonded stacked package.
An example for a package of semiconductor chips is known from U.S. Patent Application Publication 2003/0015803 A1. The semiconductor chips have identical dimensions and are spaced apart by spacers of smaller lateral dimensions, preventing the chip from directly contacting to the neighbor and allowing wire-bonding of each of the stacked chips to the bonding pads on a carrier.
Another stacked multi-chip module and a method for manufacturing a stacked multi-chip module is described in EP 0 575051 B1. According to this document, a first element (die) is mounted on a substrate by using an adhesive material. A second element (die) is mounted to the first again by using an adhesive material. The third die should be at least partially supported by the second die and the second die should be at least partially supported by the first die. Furthermore, the second die is positioned such that the electrical contacts are exposed and accessible for making fine wire connections thereto. Likewise, the third die may be positioned such that electrical contacts of the second die are exposed and accessible for making fine wire connections thereto. Although the upper dies are progressively smaller in size.
The problem of this prior art is that the dies must be equal in size but it is possible to stack very thin dies.
USPTO Backgrounds
USPTO Backgrounds