In order to address the high demands of electronic packaging from the rapidly growing telecommunication, electrical, automotive, aerospace and defense industries, a variety of integrated circuit packages have been developed to meet a diverse range of application requirements from these industries. The integrated circuit package serves to encapsulate the integrated circuit die and connects onto a printed circuit board through a substrate which is a part of the integrated circuit package that is interposed between the integrated circuit die and the printed circuit board.
U.S. Pat. No. 7,795,071 describes a semiconductor package for fine pitch miniaturization and its manufacturing method. The method involves the formation of a plurality of electronically isolated package trace layout units that is formed by a first patterned conductive layer and a second patterned conductive layer on a carrier. The second bottom surface of the second patterned conductive layer is disposed on the first top surface of the first patterned conductive layer. A mold forms an insulating layer for encapsulating the first and second patterned conductive layers.
However, U.S. Pat. No. 7,795,071 utilizes a molding technology to encapsulate the conductive layers that requires insulating materials to be infused or injected to form the mold.
USPTO Backgrounds
USPTO Backgrounds