This invention relates in general to a synchronizer circuit for controlling the counting operation of an associated timer/counter circuit which is well suited for use in a microcomputer system as an interval timer or event counter. In particular, the synchronizer circuit of the present invention is operable to resolve any conflicts that may result from the simultaneous occurrence of a load pulse that is attempting to update the count value stored within the timer/counter circuit and a read command that is attempting to obtain the count value stored within the timer/counter circuit. By resolving such conflicts, the synchronizer circuit is operable to synchronize the timer/counter circuit's update and read functions such that the timer/counter circuit may be randomly interrogated during its counting operation without adversely affecting or disturbing the count in progress.
In order to minimize overhead in a software routine, many of the timing and counting functions that are essential to the proper operation of today's more sophisticated microcomputer systems are performed by peripheral components such as interval timers and event counters. An interval timer is typically comprised of a counting circuit that is arranged to generate an accurate time period under software control. The interval timer is constructed to have a preselected maximum count state that corresponds to the desired time interval. Upon command, a clock signal is provided to the interval timer causing it to begin counting to its maximum count state. Once this count state is reached, the interval timer generates a logic signal that indicates that the preselected time period has ended. An event counter operates in basically the same manner as an interval timer with the exception that the timer/counter circuit is not clocked by a periodic clock signal but rather by a logic signal that is generated in response to the occurrence of a particular event.
When using interval timers and event counters, it is often necessary to obtain the contents of the timer/counter circuit while the circuit's counting operation is still in progress. If the timer/counter circuit and its associated microcomputer are operating at two different frequencies, it is possible for the timer/counter circuit to be updating its count state at the same time as it is being interrogated by the microcomputer. This condition can produce instabilities that may have an adverse effect upon the outputted data.
A presently known synchronization technique for overcoming the above-mentioned problem involves a two-step procedure. In the first step of this technique the microcomputer sets an anticipation flag within the timer/counter circuit a preselected period of time before the timer/counter circuit is to be interrogated by the microcomputer. The timer/counter circuit responds to this flag by causing its count state to be latched into an associated holding register. This latching function is performed by the timer/counter circuit within the next time slot during which the count state of the timer/counter circuit is not being updated. Since the count state of the timer/counter circuit must be stored within the holding register prior to interrogation of this circuit by the microcomputer, it is imperative that the timer/counter circuit be operating at a frequency that is equal to or less than the operating frequency of the microcomputer. The second step of the technique involves the issuance of a normal read command by the microcomputer. The timer/counter circuit responds to this read command by providing to the microcomputer the count value stored within the holding register.
The above-described synchronization technique, however, is unsatisfactory in several respects. In particular, this technique is fairly complicated to implement, and as a result, adds considerable overhead to software routines that utilize the services of an interval timer or event counter. A further problem associated with the above-mentioned technique is that the timer/counter circuit must be operated at a frequency that is equal to or less than the operating frequency of the microcomputer. This requirement limits the flexibility of the microcomputer system. Accordingly, the above-described synchronization technique has a number of inherent disadvantages that make it undesirable for use in today's more sophisticated microcomputer systems.
USPTO Backgrounds
USPTO Backgrounds