1. Field of the Invention
The present invention relates to the field of liquid crystal display, and in particular to a drive circuit of liquid crystal panel of liquid crystal display device.
2. The Related Arts
The progress of science and technology and the improvement of living quality of human beings makes liquid crystal display devices widely used everywhere in daily living. People are now asking for more for the liquid crystal display devices and start demanding large display screen and fast response. However, increasing the size of the liquid crystal display brings more complicated wire lay-out. Also, accurately controlling pixel electrodes is getting more difficult due to wiring delay caused by the increase of number of pixel electrodes driven by a TFT (Thin-Film Transistor) substrate and feedback caused by the existence of TFT parasitic capacitor.
FIG. 1 is a schematic view showing the structure of a VA (Vertical Alignment) liquid crystal display device. In the drawing, liquid crystal molecules 100 maintain perpendicular to and are aligned between two substrates 300, 400 when no drive voltage is applied. When a drive voltage is applied, the liquid crystal molecules 100 located around pixel electrodes 200 are rotated by 0-90°.
FIG. 2 is a schematic view showing a basic drive circuit of a TFT array substrate. In the drawing, pixel electrodes 200 are shown distributed in the entire TFT array substrate and each pixel electrode 200 is at least connected to a drain terminal d of one TFT. The source terminal s of each TFT is at least connected to one data line and a plurality data lines collectively constitutes a data bus structure. The gate terminal g of each TFT is at least connected to one gate line and a plurality of gate lines collectively constitutes a gate bus structure. The data bus and the gate bus collectively control data writing of the pixel electrodes via the thin-film transistors. As shown in FIG. 2, the pixel electrode P(I,j) of the ith column and the jth row of the TFT array substrate is commonly controlled by the gate line G(j) and data line S(i). When a writing operation is performed on the pixel electrode P(i,j), the gate line G(j) is set at a high level to set the thin-film transistor T(i,j) in a conducting state. Under this condition, the magnitude of the drive voltage applied through the data line S(i) causes the liquid crystal molecules neighboring the pixel electrode P(I,j) to rotate according to a predetermined rotation direction so as to achieve displaying of image. Such a writing operation is performed in row-wise manner, so that when the gate line G(j) is in the high level, all the pixel electrodes of the jth row can perform a writing operation.
Referring to FIG. 3, which is a schematic view showing connection of an equivalent drive circuit of each pixel electrode, the ith data line S(i) is connected to the source terminal s of the thin-film transistor T(i,j) at the ith column and the jth row. The jth gate line G(j) is connected to the gate terminal g of the thin-film transistor T(i,j) at the ith column and the jth row. The drain terminal d of the thin-film transistor T(i,j) at the ith column and the jth row is connected to the pixel electrode P(i,j) at the ith column and the jth row. Capacitor Cgd is a parasitic capacitor between the gate terminal g and the drain terminal d. The parasitic capacitor Cgd is inherent to the TFT triode. The symbol Clc indicates an equivalent capacitor of a liquid crystal layer between the TFT substrate and a CF (Color Filter) substrate. The symbol Cs is a compensation capacitor between the TFT substrate and Vcom and the capacitor is provided for compensation for voltage drop of Clc through electrical discharging in order to properly extend the retention time for direction change of liquid crystal molecules in the area of Clc. However, with the increase of the numbers of rows and columns of the pixel electrodes that are arranged in a matrix form, the lengthened gate lines and data lines cause time delay in the drive circuit. As shown in FIG. 4, on the other hand, the parasitic capacitor Cgd existing between the gate terminal g and the drain terminal d of the thin-film transistor directly affects the gate voltage Vg controlling conduction and cutoff of the thin-film transistor, especially for the neighboring site of the pixel electrode P(n,j) that is located at a distal end away from the data bus circuit, where due to the influence of discharging voltage caused by the parasitic capacitors Cgd of the previous (n−1) thin-film transistors that the gate signal passed first and the influence caused by circuit delay, this site may have an extended response time and also suffers attenuation of gate voltage caused by the electrical discharging when the gate voltage goes from high to low, making the conduction time of the thin-film transistor T(n,j) extended from Tj by ΔTj. In other words, the thin-film transistor that is supposed to be cut off is abnormally conducted on. This makes the driving time of the pixel electrode P(n,j) connected to the drain terminal d of the thin-film transistor extended by ΔTdx, leading to abnormal rotation of the liquid crystal molecules neighboring the pixel electrode, which causes variation of transmittance and abnormality of contrast.
U.S. Pat. No. 7,304,626 suggests the following in respect of the abnormality of displaying resulting from TFT gate voltage delay caused by parasitic capacitance:
(1) Using variation of resistance of a resistance-variable component or a voltage-controlling resistance-variable component to compensate the influence of discharging voltage caused by parasitic capacitor when the voltage of gate line is getting lower.
As shown in FIG. 5, in a gate signal generation circuit, SC is resistance-variable component or voltage-controlling resistance-variable component. A drive voltage is such that a high level VD1 generated by a high level generation circuit VD1X and a low level VD2 generated by a low level generation circuit VD2X form a drive voltage for a gate line through the conduction and closing of a controlled switch 3b. When 3b is in conduction with the high level VD1, charging is made to the parasitic capacitor Cgd and Clc to drive the pixel electrode; and when 3b is in conduction with the low level VD2, the variation of resistance of the SC component is applied to vary voltage drop of the resistor to compensate the discharging voltage of the parasitic capacitor, thereby reducing the delay of the gate line voltage and improving image displaying quality.
(2) Using a VD1a signal generation circuit structure of FIG. 6A to form a VD1 high level generation circuit on the basis of FIG. 5 and also omitting the resistance-variable component or voltage-controlling resistance-variable component SC that compensates the influence of discharging voltage of the parasitic capacitor when voltage of the gate line gets lowering.
The signal VD1a generated by the circuit structure shown in FIG. 6A is shown in FIG. 6B in a high level. At the end of each period of the high level, a waveform of the falling edge is formed in a predetermined dropping rate. At the end of a period of the signal VD1a, the switch 3b is surely set in connection with the low level VD2 generation circuit. A period of the high level VD1a and a low level period of VD2 collectively form a period of the gate signal VG of the gate line.
Symbol Stc is voltage having a waveform similar to GCK and can be a basic voltage obtained through GCK/GSP conversion and generally uses an inverting amplifier to control conduction and cutoff of SW2 switch.
When Stc is high level, SW1 is conducting and SW2 is low level, where SW2 is cut off and the voltage passes is Vdd and at the same time Vdd charges Ccnt capacitor so that after becoming steady, the voltage of VD1a is Vdd. When Stc is low level, SW1 is cut off and SW2 is high level, where SW2 is conducting and the voltage of VDa is obtained as a division voltage through Rcnt on the basis of Stc. The already-charged Ccnt is now discharging, providing VD1a a constant dropping rate, of which the waveform is specifically shown in FIG. 6B, thereby obtaining a drive voltage that is applied from the gate line to the gate terminal of the thin-film transistor to be of a waveform illustrated as VG(j).
(3) Using a VD1b signal generation circuit structure of FIG. 7A to form a VD1 high level generation circuit on the basis of FIG. 5 and also omitting the resistance-variable component or voltage-controlling resistance-variable component SC that compensates the influence of discharging voltage of the parasitic capacitor when voltage of the gate line gets lowering.
The signal VD1b generated by the circuit structure shown in FIG. 7A is shown in FIG. 7B in a high level. At the end of each period of the high level, a waveform of the falling edge is formed in a predetermined dropping rate. At the end of a period of the signal VD1a, the switch 3b is surely set in connection with the low level VD2 generation circuit. Similarly, a period of the high level VD1a and a low level period of VD2 collectively form a period of the gate signal VG of the gate line.
The block indicated by phantom lines in FIG. 7A is a DC charging/discharging oscillation circuit, while that outside the phantom line block is an operational amplifier, wherein Stc is still a voltage having a waveform similar to GCK and can be a basic voltage obtained through GCK/GSP conversion. Vct is a voltage at the negative terminal of the amplifier and Rct and Cct are charging/discharging unit. When Cct is saturated, the voltage thereof is exactly the voltage Vct of a direct current let flowing through Rct.
When Stc is high level, SW3 is open, where the output voltage VD1b is a voltage that is of the same polarity as Vdd and is proportional to Vdd. The voltage is high level and is sufficient to conduct TFT on.
When Stc is low level, SW3 is closed, where the negative input of the amplifier receives positive voltage rise from electrical discharging of Cct. The positive voltage rise that is connected to the negative terminal of the amplifier passes through the amplifier to form an amplified negative voltage drop. The negative voltage drop and the high level of the opening condition of SW3 collectively form VD1b that is high level similar to VD1 of FIG. 5.
Although these solutions may reduce the influence of the delay of the gate voltage caused by discharging voltage of the parasitic capacitor, yet the equivalent parasitic capacitor Cn at the site of the pixel electrode T(n,j) that is distant from the gate bus G is in parallel with the previous (n−1) parasitic capacitors. This may result in different discharging voltages of the parasitic capacitors at the pixel electrodes T(I,j). In other words, for all the thin-film transistors connected to an entire gate line, when the gate voltage is changed from a high level to a low level, the negative voltages resulting from electric discharging of the gate parasitic capacitors of the thin-film transistors is variable. The above solutions of drive circuit cannot well dissolve the issue of extension of conduction time of thin-film transistors.
USPTO Backgrounds
USPTO Backgrounds