1. Technical Field
The present invention relates to a semiconductor device.
2. Related Art
The recent progress in micronization of semiconductor chips has elicited the drawback of signal delay that takes place in an interconnect, and the improvement therefor has been required. One of the solutions is employing a low relative dielectric constant (hereinafter, low-k) film as an interlayer dielectric. Such technique can be found, for example, in JP-A No. H08-264627, JP-A No. 2007-115980, and in the non-patented document cited below.
For example, a semiconductor device 100 shown in FIG. 4 has been proposed.
The semiconductor device 100 includes a plurality of low-k layers 101 to 103 formed on a substrate (not shown), which respectively includes a lower interconnect 104, a via 105, and an upper interconnect 106.
[Patented document 1] JP-A No. H08-264627
[Patented document 2] JP-A No. 2007-115980
[Non-patented document 1] IEICE TRANS. FUNDAMENTALS, VOL. E88-A, No. 12 December 2005, Kurokawa et al, P3471-3478
In the highly micronized interconnect structure of latest semiconductor devices, the via diameter and the interconnect width have to be minute, and hence the connection area between the via and the interconnect is quite small. The semiconductor device is, therefore, prone to incur the following drawback which has not been observed in a conventional structure.
A tensile stress is originated in the low-k film based on a difference between the thermal expansion coefficient of the substrate and that of the low-k film. Specifically the low-k film itself is biased to shrink, and the biasing force of the low-k film in the shrinking direction applies the tensile stress to an end portion of the interconnect in contact with the low-k film. Such tensile stress often forms a void in a region including the interface between the lower interconnect 104 and the via 105.
In the case where an electron runs, for example from the upper interconnect 106 to the lower interconnect 104, under the state that the tensile stress is exerted, an atom constituting the conductor migrates by electromigration in response to the flow of the electron, to thereby further promote the formation of the void at the interface between the lower interconnect 104 and the via 105, where a harrier metal blocks the migration of the atom. The void formed at the interface, though small in volume, leads to such drawback as provoking a conduction failure, thereby degrading the reliability of the semiconductor device because of the poor performance of the interconnect.
USPTO Backgrounds
USPTO Backgrounds