1. Field of the Invention
The present invention relates to a one time programmable (OTP) memory cell, an OTP memory, and a method of manufacturing an OTP memory cell. In particular, the present invention relates to an OTP memory cell having a nonvolatile state memory cell that is writable only once, an OTP memory, and a method of manufacturing an OTP memory cell.
2. Description of Related Art
As an example of a nonvolatile state memory cell formed in a semiconductor device, there is known a one time programmable cell (hereinafter, referred to as “OTP cell”) that is writable only once. Japanese Patent Translation Publication No. 2005-504434 (hereinafter, referred to as “Related Art 1”) discloses an example of a memory cell having the OTP cell. FIG. 47 shows a cross-sectional diagram of a memory cell 100 having the OTP cell as disclosed in Related Art 1.
The memory cell 100 includes an OTP cell and a selection transistor. FIG. 47 shows two memory cells. In a case of writing data in the memory cell, a voltage of about 2.5 V is first applied to a gate electrode (for example, row terminal Vr1) of the selection transistor, and then, a voltage of about 7.0 V is applied to a column terminal Vc1 of the OTP cell. As a result, the selection transistor is brought into a conducting state, and the voltage of 7.0 V is applied between a drain diffusion layer 107 and an electrode 102 of the OTP cell, whereby a breakdown occurs between the drain diffusion layer 107 and the electrode 102. Due to the breakdown, the drain diffusion layer 107 and the electrode 102 are short-circuited, with the result that data is written.
In such a writing operation, a voltage difference of about 7.0 V is generated between a gate r1 of the selection transistor and the drain diffusion layer 107. In Related Art 1, in order to prevent a breakdown of the selection transistor due to the voltage difference between the gate r1 and the drain diffusion layer 107, a gate insulating film 108 of the selection transistor is formed with a thickness greater than that of the gate insulating film 108 of the OTP cell.
However, in Related Art 1, the voltage high enough to cause the breakdown in the OTP cell is applied. Accordingly, it is necessary to additionally provide a booster circuit incorporating a high withstand voltage element. Alternatively, it is necessary to additionally provide a power supply capable of generating a voltage higher than a power supply voltage which is applied to a control circuit or the like for the writing operation. Also for peripheral circuits of the memory cell, it is necessary to use a transistor capable of withstanding a voltage higher than the power supply voltage. In general, a high withstand voltage element has an element area larger than that of an element constituting a logic circuit such as a control circuit. Accordingly, when a circuit incorporating such a high withstand voltage element is additionally provided, there arises a problem of an increase in chip area.
USPTO Backgrounds
USPTO Backgrounds