1. Field of the Invention
The present invention relates to a buffer flush controller, and more particularly to a buffer flush controller of a peripheral component interconnect-peripheral component interconnect bridge.
2. Description of the Prior Art
In order to improve the efficiency of a computer, a computer system often uses various data buffers such as a posted write buffer, a read buffer, and a line buffer. Because data consistency sometimes cannot be maintained when these buffers are used, a buffer system can fall into deadlock and cause a fatal defect in the computer system. For this and other reasons, contemporary practice is concerned with handling data and memory access with peripherals, in situations with flush of data, and in situations that are related to these situations. One exemplar, Craft et al. (U.S. Pat. No. 5,438,666, Shared Memory Bus System for Arbitrary Access Control Among Contending Memory Refresh Circuits, Peripheral Controllers, And Bus Masters, Aug. 1, 1995) proposes use of computers having a shared address, data and control bus for providing access to a memory storage unit to store instructions and data therein and to retrieve instructions and data therefrom. Bus arbitration units determine which of many devices is granted access to a shared bus, such as an AT-type shared bus as used in an IBM.RTM.PC-AT or a compatible computer system. Chan et al. (U.S. Pat. No. 5,345,577, DRAM Refresh Controller With Improved Bus Arbitration Scheme, Sep. 6, 1994) shows a cache controller with both burst and hidden refresh modes. In the burst mode, refresh requests are counted, but not acted on, until a predetermined number of refresh requests have been received. In the hidden refresh mode, a request is acted upon, but no hold signal is sent back to stop the central processing unit while the refresh request is being acted on. Circuitry is provided which allows local memory access, but holds other memory access until the refresh is completed. In addition to the data buses, data buffers are provided. Dishon et al. (U.S. Pat. No. 4,862,411, Multiple Copy Data Mechanism On Synchronous Disk Drives, Aug. 29, 1989) advocated use of multiple copy data mechanisms on synchronous disk drives. At least two direct access storage devices that are predetermined to record the same data from a central processing unit, are normally kept synchronized with each other except during the transient power up phase. The synchronization of direct access storage devices is controlled and maintained by synchronization control independent of any commands from the central processing unit. Shriver (U.S. Pat. No. 4,625,296, Memory Refresh Circuit With Varying System Transparency, Nov. 25, 1986) shows a memory refresh circuit with varying system transparency. A memory refresh circuit controls the refreshing of dynamic RAM included in a system wherein a control store outputs micro-code instructions to control the system operation in response to sequences specified by a sequence and interrupt logic circuit. A counter transmits certain counts of system machine cycles to an array logic device.
USPTO Backgrounds
USPTO Backgrounds