Some types of semiconductor logic gates show a strong temperature dependence. This effect has proved to be particularly a problem in logic gates which use a gallium aresenide depletion mode FET's but also may arise in other instances. The result of this temperature dependence is to limit the temperature range over which such logic gates may be used. This limited temperature range is much less than the full military temperature range of -55.degree. C. to +125.degree. C. for some logic families. In order to obtain logic gates of such families which can operate over this entire range, a temperature compensation scheme is required. The present invention provides such a temperature compensation system.
USPTO Backgrounds
USPTO Backgrounds