1. Field of the Invention
This invention relates to the design of integrated circuits (ICs) in general, and in particular to an automated system and process for creating highly optimized transistor-level building blocks that incorporate design-specific optimization goals and yields significant benefits for most design environments, such as, COT/COL, ASICS, ASP, etc.
2. Description of the Related Art
Over the last four decades, design and manufacturing of ICs has evolved into a multi-billion dollar industry. IC designs can be broadly classified into two major categories: (i) storage designs, which store digital data; and (ii) logic designs, which manipulate digital data.
The present invention described herein is applicable to the category of logic ICs or parts thereof, that deal broadly with data manipulation and several sub-categories thereof, viz., ASICs, ASSPs, COT/COL, etc.
The proliferation of digital ICs and the diversity of applications using ICs have led to the development and use of various types of metrics for evaluating the cost and quality of developed ICs. Die size, performance (i.e., speed), and power consumption have evolved as three of the most commonly used metrics for measuring the quality of IC designs. Other metrics, such as, for example, noise, signal integrity, reliability, etc. are gaining in importance. Time-to-market or design cycle time, and expected sales volume have evolved as two other commonly used business metrics. It is generally observed that the time-to-market period is steadily decreasing for nearly all digital ICs.
The importance of quality metrics, such as those mentioned above, is generally application-dependent, and thus varies from one design to another. Two of the most commonly used combinations of metrics are: (i) performance and power, and (ii) die size and power.
Due to ever-increasing time-to-market pressures, highly automated IC design processes have been developed that can be broadly categorized as: (i) fully pre-fabricated, highly programmable component-based design process (e.g., FPGA, etc.); (ii) partially pre-fabricated platform (e.g., gate array) based design processes, which, upon completion, require only that the metal layers be fabricated, and (iii) design processes that do not rely on any pre-fabricated components or platforms, but instead, use fixed building blocks (standard cells) with pre-defined schematic structure and layout, and fully customizable interconnections between the blocks wherein at the completion of the design process, all components (layers) in the design need to be fabricated from scratch. Among these, the last category of IC designs typically offers the highest performance, the smallest die size, and the lowest power among designs created using automated tools. In order to limit the complexity of the design process to manageable levels, traditionally, standard cell libraries are used in such automated design flows. Numerous automated IC design tools, e.g., simulation, synthesis, place-and-route, extraction, verification, etc., suitable for utilizing and/or use with standard cell libraries, have been developed. The synthesis tools accept as input a given design description in some suitable format (e.g., register-transfer level (RTL), behavioral, etc.), and generate a netlist. The netlist is simply an interconnection of the pre-defined cells in the standard-cell library. Place-and-route tools create a layout utilizing the layouts of the pre-defined standard cells such that the interconnections between the cells, as specified in the netlist, are preserved. Place-and-route tools also take into account the detailed timing issues that arise from the actual location of the various cells in the layout. A typical flow diagram of a process for creating IC designs using such standard-cell libraries is shown in FIG. 1.
A key problem with the existing approach of automated IC design processes is that designers, using synthesis tools, are forced to use components from a static, pre-defined standard-cell library of cells developed to be applicable to a wide variety of digital ICs. As a result, the cells tend to be relatively small and general-purpose. Standard-cells, such as basic Boolean gates: AND, OR, NAND, NOR, XOR, XNOR, AND-OR-INVERT, OR-AND-INVERT, MUX, etc. However, for a given design, the forced use of such pre-defined standard cells leads to poor quality in the final design as compared to full-custom (hand-crafted) IC design processes and judged by the aforementioned quality metrics. Particular attention has been drawn to this fact by recent comparisons of designs created by automated flows versus designs created using a full-custom, heavily manual design process.
Therefore, although automated tools and flows speed up the design creation process, the relatively poor quality of resultant designs as judged against the quality that can be achieved with a manual re-design of the same part, has major cost and business implications. Increased die-size and increased power consumption by as much a factor of 10 or more are two major and obvious such implications. Reduced performance of the automated design, by as much as a factor of 2, also has significant implications in the marketplace. Even a cursory comparison of handcrafted designs to automatically generated design shows a noticeable difference in the usage patterns of various layers in the physical design. Handcrafted designs tend to use all the layers, including diffusion and polysilicon layers, very effectively and efficiently, while automatically generated designs tend to use diffusion and polysilicon layers relatively sparsely while using the metal layers profusely. Recently, it has been noted by many designers and researchers that this profusion of metal interconnects in automatically generated designs constitutes an increasing problem (and bottleneck) in terms of performance and power consumption, as IC designs into deep-sub-micron geometries approaching 0.10 micron or less.
Prior attempts at improving the quality of automatically generated designs, over the past two decades, have focused primarily on automatic layout synthesis. A key constraint faced by automatic layout synthesis methods is that they are primarily appropriate for layouts of relatively small transistor-level designs. Attempts to apply the same automatic layout synthesis methods to the creation of VLSI designs—popularly known as silicon compilation in the early 1980's was pursued without such success for many years, and was eventually dropped.
More recently, a body of work has been reported in the area of automated creation of transistor-level designs. These efforts are primarily academic in nature, with a heavy focus on the use of pass-transistor logic (PTL). The vast majority of industrial standard-cell based designs continue to use static CMOS style of design, due to various problems inherent in PTL. Key among such problems is the loss of one V_t (threshold voltage of a transistor, modified by appropriate body effects) while passing a signal (high or low voltage) through pass transistors, which can easily lead to slow/improper functioning of subsequent stages of transistors driven by a pass transistor. A relatively smaller portion of the efforts that apply to static CMOS module generation are focused on simply minimizing transistor count in the transistor-level modules created. The prior automated IC design processes do not take into account performance of the resultant modules as well as a host of real-life constraints that must be taken into account while creating transistor-level modules used in actual designs. Such real-life constraints include (i) tolerable delays from individual inputs to output(s) of modules created at the transistor level, (ii) maximum depth of n- and p-transistor stacks in the modules created, (iii) tolerances on transition times of the signals at the outputs of modules created, (iv) desired drive-strength of resultant module, (v) limits on capacitive loads at inputs of the module created, etc.
USPTO Backgrounds
USPTO Backgrounds