1. Field of the Invention
The present invention relates to a memory device and a method for accessing memories of the memory device.
2. Description of the Related Art
Conventionally, a type of LSIs (large scale integrated circuits) referred to as DSPs (digital signal processors) are mounted in various types of apparatuses as digital signals are processed in more and more fields. A DSP executes arithmetic operations of digital signals at high efficiency, and thus generally includes a mechanism for reading data corresponding to a plurality of words (two words in most cases) within one machine cycle. A CPU (central processing unit) is mounted in an apparatus together with the DSP for the purpose of controlling various peripheral circuits including the DSP. A CPU mainly performs determinations on various conditions and logic operations, and thus generally reads data corresponding to one word within one machine cycle.
Now, with reference to FIG. 7, an exemplary operation of the DSP for reading data from a memory will be described.
An instruction (not shown) is input to a control section 301. When the instruction input to the control section 301 instructs reading of data from two memories 310 and 320, the control section 301 instructs an address generation section 315 to output two addresses 317 and 327 to the memories 310 and 320, respectively. The address 317 defines the location of the data to be read in the memory 310. The address 327 defines the location of the data to be read in the memory 320.
The address generation section 315 outputs the address 317 to the memory 310 and outputs the address 327 to the memory 320. The address 317 has, for example, value 0002h. The address 327 has, for example, value 0003h. Herein, letter "h" indicates that the value of the address is represented hexadecimally.
The values of the addresses 317 and 327 output by the address generation section 315 are in the range from 0000h to the maximum possible values which are respectively defined by the memory capacities of the memories 310 and 320. When the memory capacity of the memory 310 is 1K words, the address generation section 315 outputs the address 317 having a value in the range from 0000h to 03FFh to the memory 310.
The control section 301 activates a read signal 311 for the memory 310 and also activates a read signal 321 for the memory 320.
When the read signal 311 is active, the memory 310 outputs data 318 stored at the location designated by the address 317 (for example, 0002h) to an arithmetic operation section 330. Similarly, when the read signal 321 is active, the memory 320 outputs data 328 stored at the location designated by the address 327 (for example, 0003h) to the arithmetic operation section 330.
The arithmetic operation section 330 executes an arithmetic operation based on the data 318 and 328.
As described above, the CPU accesses the memory on the one-word-within-one-machine-cycle basis. The method for designating the location of the data in the memory by the CPU is different from the method for designating the location of the data in the memory by the DSP in that the CPU designates the location of the data in the memory to be accessed using one address.
The technologies for microscopic processing of the LSIs have been developed rapidly, and today it is possible to integrate a CPU and a DSP, which designate the location of the data in the memory in different manners, on one chip.
However, the above-described system is disadvantageous as to the following point. In the case where the CPU and the DSP, which respectively designate the location of data in the memory in different manners, are integrated on one chip and the DSP and the CPU both access the memories 310 and 320, either one of the memories 310 and 320 which are accessible by the DSP is not accessible by the CPU. The reason is that, since the address is designated for the locations in each of the memories 310 and 320 from 0000h, the CPU can designate the location of the data only in one memory 310 or 320.
Furthermore, in the case where the CPU writes the data corresponding to two words to the memory (for example, the memory 310) and then the DSP performs an arithmetic operation of the data corresponding to the two words, the DSP needs to transfer the data corresponding to one of the two words to the other memory (for example, the memory 320). The above-described system is also disadvantageous in that execution of such processing which is not related to the arithmetic operation may spoil the performance of the DSP.
USPTO Backgrounds
USPTO Backgrounds