1. Field of the Invention
The present invention relates to a method of fabricating semiconductor devices. More particularly, the present invention relates to a method of fabricating conductive lines.
2. Description of the Related Art
With the increase in the level of integration for semiconductor devices, the pattern and line width of devices is reduced correspondingly. As a result, the contact resistance between the gates of the devices and the conductive lines is significantly increased and the longer resistance-capacitance (RC) delay is produced leading to a slower operating speed. Because metal silicide has an electrical resistance lower than polysilicon and a higher thermal stability than most interconnect material (such as aluminum), a metal silicide layer is often formed on the connecting interface between the various electrodes of transistors and the metallic interconnect to reduce contact resistance. At present, the most commonly adopted process for forming a silicide layer in the manufacturing of semiconductor device is the self-aligned metal silicide layer.
The process of forming a self-aligned silicide layer includes several steps. First, a metallic layer is formed over a semiconductor chip. Then, the chip is transferred to a high temperature environment. If the metallic layer is in contact with silicon, then the two will react to form a silicide layer. On the other hand, if the metallic layer is not in contact with silicon, no silicide layer is formed. Thereafter, the metallic layer that has not participated in the reaction is removed. Since the aforementioned silicide process does not involve a photolithographic process, the metal silicide material can be formed on specified locations. Hence, this type of silicide fabricating process is called a self-aligned silicide process.
However, with the rapid progress in integrated circuit fabricating techniques, a higher level of integration in semiconductor devices is also demanded so that the pitch between neighboring conductive lines has to be set closer together. Consequently, the silicide material formed in a self-aligned silicide process frequently forms unwanted bridges between neighboring conductive lines. FIG. 1 is a schematic cross-sectional view of a conventional conductive line structure. In FIG. 1, a pair of polysilicon layers 101 (conductive lines) is formed over a substrate 100 and an insulating layer 102 is formed between the polysilicon layers 101. After forming a metallic layer 103 over the substrate 100, a high temperature annealing process is carried out to form a self-aligned silicide layer 104 on the upper surface of the polysilicon layers 101. However, during the high temperatures annealing process, some of the polysilicon material will diffuse to cause lateral diffusion. Such lateral diffusion of polysilicon material frequently leads to the formation of some silicide compound 106 on the insulating layer 102. When the pitch between two neighboring polysilicon layers 101 is small and the growth of silicide compound 106 over the insulating layer 102 is strong, an electrical bridge will form leading to the problem of having a short-circuit between neighboring conductive lines.
USPTO Backgrounds
USPTO Backgrounds