Planar transistors have been the core of integrated circuits for several decades, during which the size of the individual transistors has steadily decreased. At the current pace of scaling, the industry predicts that planar transistors will reach feasible limits of miniaturization in the near future, concurrent with the widespread adoption of 32 nm technologies. At such sizes, planar transistors are expected to suffer from, undesirable short channel effects, especially “off-state” leakage current, which increases the idle power required by the device.
As microelectronic devices become smaller and smaller, three-dimensional structures are coming into the mainstream in forming semiconductor junctions. Multigate transistors are one of several strategies being developed by CMOS semiconductor manufacturers to create ever-smaller microprocessors and memory cells and extend Moore's Law. Development efforts into multigate transistors have been reported by AMD, Hitachi, IBM, Infineon, Intel, TSMC, Freescale, UC Berkeley and others and the ITRS predicts that such devices will be the cornerstone of sub-32 nm technologies.
In a multigate device, the channel is surrounded by several gates on multiple surfaces, allowing more effective suppression of “off-state” leakage current. Multiple gates also allow enhanced current in the “on” state, also known as drive current. These advantages translate to lower power consumption and enhanced device performance. Nonplanar devices are also more compact than conventional planar transistors, enabling higher transistor density which translates to smaller overall microelectronics. The primary challenges to integrating nonplanar multigate devices into conventional semiconductor manufacturing processes include fabrication of a thin silicon “fin” tens of nanometers wide and fabrication of matched gates on multiple sides of the fin.
The term fin-field effect transistor (FinFET) was coined by University of California, Berkeley researchers to describe such a structure. Referring now to FIG. 1, the distinguishing characteristic of the FinFET is that the conducting channel is wrapped around a thin silicon “fin,” which forms the body of the device. The dimensions of the fin determine the effective channel length of the device.
The term FinFET is also employed by various microprocessor manufacturers to describe their double-gate development efforts. In the technical literature, FinFET is used somewhat generically to describe any fin-based, multigate transistor architecture regardless of number of gates. Dozens of multi-gate transistor variants may be found in the literature. In general, these variants may be differentiated and classified in terms of architecture (planar vs. non-planar design) and number of channels/gates (two, three, or four). Planar double-gate transistors generally employ conventional planar (layer-by-layer) manufacturing processes to create double-gate devices, avoiding more stringent lithography requirements associated with non-planar, vertical transistor structures. In planar double-gate transistors the channel is sandwiched between two independently fabricated gate/gate oxide stacks; a significant challenge in fabricating such structures is achieving satisfactory self-alignment between the upper and lower gates. In the technical literature, the term tri-gate is sometimes used generically to denote any multi gate FET with three effective gates or channels. Gate-all-around FETs are similar in concept to FinFETs except that the gate material surrounds the channel region on all sides. Depending on design, gate-all-around FETs can have two or four effective gates.
It has become very difficult to create such three-dimensional structures with standard etching techniques, and almost impossible to figure out how to make them even smaller. The formation of 3-D device architectures such as the FinFET is thus fraught with challenges. To form a thinner channel body structure with a wide body in the channel extension region in a FinFET MOSFET device, complex processing methods are generally employed, such as hard mask trimming after e-beam or optical lithography, spacer patterning, which is using a sacrificial and spacer layers that are formed by chemical vapor deposition (CVD), and a phase-shift mask method using a deep ultra-violet lithography at 193 nm.
If one could directly etch such structures along a given direction while not affecting the other surfaces, smaller and more advanced features could be made. This, in turn, could enable the production of smaller, faster, and cheaper computer chips and all of the consumer electronics products in which they are found.
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