1. Field of the Invention
The present invention generally relates to semiconductor integrated circuit devices, and more particularly, to driving of a signal line provided therein.
2. Description of the Related Art
It has been required that a semiconductor memory device, which is one of semiconductor integrated circuit devices, operates at a higher frequency as a CPU (Central Processing Device) operates at a higher frequency. In order to raise the operating frequency, a static operation is preferable to a dynamic operation. Generally, the dynamic operation includes two steps. The first step is to precharge a signal line to a high level (H) (or a low level (L)). The second step subsequent to the first step is to precharge the signal line again in such a manner that the signal line is set at L (H) when a signal to be transferred is at H (L). The static operation consists of a single step of driving the signal line to H or L based on the signal to be transferred.
FIG. 1A shows the dynamic operation, and FIG. 1B shows the static operation.
The dynamic operation shown in FIG. 1A shows a case where the signal line is precharged to H. In the state in which the signal line has been precharged, the signal line is driven based on the level of the signal to be transferred. Two steps, namely, the driving step and the precharging step are needed during a period T. As indicated by NG in FIG. 1A, the dynamic operation has a disadvantage in that the precharge operation is not completed during a cycle T when the frequency of the transferred signal is high (the cycle T is reduced to T′). Hereinafter, a mode for the dynamic operation is referred to as a dynamic mode.
The static operation shown in FIG. 1B only drives the signal line on the basis of the transferred signal during the cycle T′. Since the precharge operation is not needed, the static operation is suitable for transmission of high-frequency signals. A mode for the static operation is referred to as a static mode.
A semiconductor memory device having both the dynamic and static modes is known. Data is read out in the high-speed static mode, while the semiconductor memory device is tested in the dynamic mode. An example of the above semiconductor memory device is illustrated in FIG. 2.
FIG. 2 is a circuit diagram of a data bus via which data is read from a memory cell, and its peripheral circuits. Referring to FIG. 2, data bus lines DB0–DB3 (which may be referred to as signal lines) of the data bus are used in a normal operation mode, and test-dedicated data bus lines TDB0 and TDB1 (paired) are used in a test operation mode. The normal operation mode is the static mode for transferring the signal at high speed (bit rate). The test operation mode is the dynamic mode because there is no need to drive the test-dedicated data bus lines TDB0 and TDB1 at high frequencies.
A drive circuit 10 is provided to the data bus lines DB0–DB3 and the test-dedicated data bus lines TDB0 and TDB1. A precharge circuit 12 is provided to the test-dedicated data bus lines TDB0 and TDB1. The precharge circuit 12 is needed because the test-dedicated data bus lines TDB0 and TDB1 are driven in the dynamic mode.
The drive circuit 10 drives the data bus lines DB0–DB3 and the test-dedicated data bus line TDB0 and TDB1 on the basis of complementary read data RDc and RDt read from sense amplifiers 24 and a test mode signal TST. The sense amplifiers 24 are connected to pairs of bit lines extending from a memory cell array (internal circuit) 22. The drive circuit 10 includes NMOS transistors 14, 16 and 20, a PMOS transistor 18, a NAND gate 26, NOR gates 30 34 and 48, and inverters 28, 32, 36 and 40. The above NMOS is an abbreviation of Negative-channel Metal Oxide Semiconductor, and PMOS is an abbreviation of Positive-channel Metal Oxide Semiconductor. The precharge circuit 12 includes a NAND gate 42 and PMOS transistors 44 and 46. Although omitted for the sake of simplicity, for each of the sense amplifiers 24 (for each memory cell), provided are the NAND gate 26, NOR gates 20, 34 and 38, and the inverters 28, 32, 26 and 40.
The memory cell array 22 includes a plurality of memory cells arranged in a matrix formation. The pairs of bit lines extending from the respective memory cells are connected to the corresponding sense amplifiers 24. FIG. 2 shows only four sense amplifiers 24. Inverters, each composed of a corresponding one of the PMOS transistors 18 and a corresponding one of the NMOS transistors 20 of the drive circuit 10, are connected to the data bus lines DB0–DB3, as shown in FIG. 2. A part indicated by “*” in FIG. 2 corresponds to four sense amplifiers 24. Read data RDc and RDt on the pair of bit lines extending from the sense amplifier 24 and the test mode signal TST are applied to the drive circuit 10 as shown.
In the normal operation, the test mode signal TST is at L. Depending on the levels of the read data RDc and RDt, one of the PMOS transistors 18 and the NMOS transistor 20 is turned ON, and the transistor switched to ON drives the corresponding data bus line to H or L.
A description will now be given of a data compression test using the test-dedicated data bus lines TDB0 and TDB1. The data compression test puts a plurality of data bits (memory cells) together and tests these data bits. Then, resultant complementary data is referred to and it is determined whether there is an error in any of the plurality of memory cells. If no error is found, one of the test-dedicated data buses TDB0 and TDB1 is switched to H and the other to L. In contrast, if there is an error in even any one of the data bits, both the test-dedicated data bus lines TDB0 and TDB1 become L.
The data compression test is performed in the state in which the test mode signal TST is at H and a precharge signal PCG applied to the NAND gate 42 of the precharge circuit 12 is at H. In this state, the NAND gate 42 outputs L, which turns ON the PMOS transistors 44 and 46. Thus, the test-dedicated data bus lines TDB0 and TDB1 are precharged to H (a level of a power supply voltage VDD). When the test mode signal TST switches to H from L, the NAND gate 26 and the NOR gate 30 of the drive circuit 10 are disabled, while the NOR gates 34 and 38 are enabled. Since the NAND gate 26 and the NOR gate 30 are disabled, the data bus lines DB0–DB3 are not driven.
When the normal complementary read data RDc and RDt are obtained from an activated memory cell, one of the RDc and RDt is switched to L and the other to H. The read data RDc and RDt associated with a memory cell that is not enabled are both at L. Thus, the NMOS transistors 14 and 16 of the drive circuit associated with the memory cell that is not enabled are both OFF. Depending on the read data RDc and RDt from an enabled memory cell, one of the NMOS transistors 14 and 16 is ON, and the corresponding one of the test-dedicated data bus lines TDB0 and TDB1 is driven to L from H.
Now, the following is assumed. Data H is written into the memory cells connected to the four sense amplifiers 24 and is read (a wired-OR operation on the data is made) to the test-dedicated data bus lines TDB0 and TDB1 via the corresponding circuit * of the drive circuit 10. Thus, it is determined whether there is an error on the enabled-cell basis (on the circuit * basis). The four sense amplifiers 24 are associated with a group of memory cells that can be segmented by an specific address. In the above assumption, a circuit part ** related to another address and similar NMOS transistors 14 and 16 that are not shown are all OFF.
If there is no error with data H being written into the memory cells, read data RDt are at H, and the related NMOS transistors are all turned ON, so that the test-dedicated data bus line TDB0 is driven to L. In contrast, the NMOS transistors 16 are all OFF, and the test-dedicated data bus line TDB1 is maintained at the precharge level H. That is, if there is no error, one of the test-dedicated data bus lines TDB0 and TDB1 are at H and the other at L. If there is an error in even one of the four memory cells, the H/L relation between the read data RDc and RDt is reversed. In this case, the corresponding NMOS transistors 16 are turned ON and drive the test-dedicated data bus line TDB1 to L. Thus, both the test-dedicated data bus lines TDB0 and TDB1 are at L. In the above-mentioned manner, the presence of error can be identified.
If there is no error when L is written into the memory cells, all the NMOS transistors 14 are turned OFF, and all the NMOS transistors 16 are turned ON. Thus, the test-dedicated data bus lines TDB0 and TDB1 are set at H and L, respectively. If there is an error in even one of the memory cells, the test-dedicated data bus line TDB0 is switched to L. Thus, error can be identified.
However, the conventional circuitry shown in FIG. 2 has the following disadvantages. In a case where the data bus lines DB0–DB3 that are used in the normal operation mode are operated in the static mode, there is a need to additionally and separately provide the pair of test-dedicated data bus lines TDB0 and TDB1 that are operated in the dynamic mode. Further, the drive circuit 10 needs a modification with a larger number of circuit elements. This modification needs a larger chip area and prevents increase in the integration density.
USPTO Backgrounds
USPTO Backgrounds