The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a semiconductor device including a sidewall and a method for fabricating the same.
The structure of a known semiconductor device will be described hereinafter with reference to FIGS. 6A and 6B. FIG. 6 shows the structure of the known semiconductor device, in which FIG. 6A is a plan view, and FIG. 6B is a cross sectional view taken along the line A—A in FIG. 6A.
As shown in FIG. 6A, the known semiconductor device has a substrate 1 comprising a semiconductor layer 2 as an element formation region and a shallow trench isolation (hereinafter referred to as an STI) 3 surrounding the sides of the semiconductor layer 2. A gate electrode 4 is provided so as to extend across the top of the semiconductor layer 2 to the top of the STI 3. An insulative sidewall 9 is formed on all sides of the gate electrode 4 so as to surround them.
As shown in FIG. 6B, the known semiconductor device is formed of: the substrate 1 consisting of the semiconductor layer 2 and the STI 3; source/drain regions 8 provided apart from each other in the semiconductor layer 2 and each consisting of a high-concentration impurity diffusion layer 6 and a low-concentration impurity diffusion layer 7; a gate dielectric 5 which is provided on a region of the semiconductor layer 2 located between the source/drain regions 8 and made of a silicon oxide film (SiO2); the gate electrode 4 provided on the gate dielectric 5 and made of polysilicon; and the sidewall 9 provided from the sides of the gate electrode 4 to the top of the semiconductor layer 2 and made of a silicon nitride film (SiN).
The high-concentration impurity diffusion layer 6 of each of the source/drain regions 8 is provided in a portion of the semiconductor layer 2 which is located outwardly of the insulative sidewall 9. The low-concentration impurity diffusion layer 7 borders on the inner surface of the high-concentration impurity diffusion layer 6 in the semiconductor layer 2 and is provided so as to have a smaller depth than the high-concentration impurity diffusion layer 6.
Next, a known method for fabricating a semiconductor device will be described with reference to FIGS. 7A through 7D. FIGS. 7A through 7D are cross sectional views showing process steps for fabricating the semiconductor device shown in FIG. 6.
First, in the process step shown in FIG. 7A, an STI (not shown) is formed on a substrate to surround a semiconductor layer 2, and thereafter a gate dielectric 5 made of a silicon oxide film and a gate electrode 4 made of polysilicon are formed on the semiconductor layer 2. Subsequently, ions are implanted into the semiconductor layer 2 using the gate electrode 4 as a mask, thereby forming low-concentration impurity diffusion layers 7 in portions of the upper part of the semiconductor layer 2 which are located at both sides of the gate electrode 4.
Next, in the process step shown in FIG. 7B, a silicon nitride film 9a covering the gate electrode 4 and the gate dielectric 5 is deposited on the semiconductor layer 2.
Then, in the process step shown in FIG. 7C, the silicon nitride film 9a is subjected to etchback, thereby forming a sidewall 9 on the sides of the gate electrode 4.
Next, in the process step shown in FIG. 7D, ions are implanted into the semiconductor layer 2 using the gate electrode 4 and the sidewall 9 as masks, thereby forming high-concentration impurity diffusion layers 6 in portions of the upper part of the semiconductor layer 2 which are located outwardly of the sidewall 9. Each of the high-concentration impurity diffusion layers 6 is formed so as to have a larger implantation depth than each of the low-concentration impurity diffusion layers 7. Each pair of the high-concentration impurity diffusion layer 6 and the low-concentration impurity diffusion layer 7 constitutes a source/drain region 8. Through the above-described process steps, the known semiconductor device is formed.
Typically, silicon nitride is employed as a material of the sidewall 9. Silicon nitride has a large stress. Therefore, a stress caused by the sidewall 9 is applied to the gate electrode 4, the gate dielectric 5 and the semiconductor layer 2. As a means for relaxing the stress as described above, a method for interposing an L-shaped stress-relaxation layer between the gate electrode and the sidewall has been suggested. This known art is disclosed in Japanese Unexamined Patent Publication No. 5-102074 (page 4, FIG. 4), for example.
However, with the progress of miniaturization of MISFETs (metal insulator semiconductor field effect transistors), the relative thickness of the sidewall to the gate length has been increased and the influence given to the gate electrode by the stress of the sidewall has also increased.
If the stress of the sidewall reached the gate electrode and the gate dielectric, the threshold voltage would be easily displaced. If this stress reached the semiconductor layer, crystal defects leading to the occurrence of leakage currents might take place. Therefore, it is difficult to effectively reduce the stress simply by interposing the stress-relaxation layer between the gate electrode and the sidewall, and thus further relaxation or reduction of the stress is required.
USPTO Backgrounds
USPTO Backgrounds