1. Field of the Invention
The present invention relates to a three-dimensionally mounted semiconductor module, and in particular, to a three-dimensionally mounted semiconductor module in which stacked semiconductor chips are mounted on an interconnect substrate, with an improved cooling structure. The present invention also relates to a three-dimensionally mounted semiconductor system in which the three-dimensionally mounted semiconductor module is mounted.
2. Description of the Related Art
Conventional stacked-type three-dimensionally mounted semiconductor modules are configured so that when a cooling operation is performed in the system, the module is indirectly cooled by being joined to a radiator, a heat pipe, or the like or is directly cooled by being immersed into a liquid, as shown in FIGS. 9A to 9C.
FIG. 9A is a sectional view of a large and small chip stacked type. FIG. 9B is a sectional view of a TCP (Tape Carrier Package) stacked type. FIG. 9C is a sectional view of a chip-stacked type. In the figures, reference numeral 601 denotes a mounting substrate, and reference numeral 602 denotes an interposer. Reference numerals 603 and 604 denote semiconductor chips. Reference numerals 605, 606, and 607 denote a bonding wire, a sealing resin, and a radiator, respectively. Reference numerals 611, 613, and 614 denote a TCP, an outer lead, and a heat pipe, respectively. Reference numerals 621, 622, and 623 denote a semiconductor chip, a sealing resin, and a channel wall, respectively.
However, such cooling structures create the problems described below. With an indirect cooling structure utilizing thermal conduction as shown in FIGS. 9A and 9B, a chip located in an inner layer of stacked semiconductor chips must be cooled via the chips located on a top and bottom surfaces, respectively, of this chip. In this case, disadvantageously, an increase in power consumption makes cooling difficult to lead the chip in the inner layer to cause an abnormally large temperature rise. Further, even if the semiconductor module is immersed into a liquid as shown in FIG. 9C, only the sides of the semiconductor module contact with the liquid, that is, the area of the semiconductor module which contacts with the liquid is limited. As a result, the cooling of the inner layer chips is also difficult.
In particular, owing to its thermal design, the chip stacked type module has a disadvantageous structure in which the “cooled surface area of the module does not increase even with an increase in the overall heat flux of the module accompanying an increase in the number of chips stacked”. Accordingly, with an increase in the power consumption of the device, the cooling is becoming more difficult.
As another conventional example, a method using a heat sink which has channel structure of micron-order (called microchannel) has been reported (refer to, for example, IEEE ELECTRON DEVICE LETTERS, VOL. EDL-2, No. 5, p. 126 to 129, MAY 1981) in order to achieve more efficient cooling. This method is shown in FIGS. 10A and 10B. In the figures, reference numerals 701, 702, 704, and 705 denote a semiconductor chip, a connection bump, a cover plate, and a microchannel machined portion, respectively. However, to implement this structure, it is essential to have a complicate processing on a back surface of the semiconductor chip or the like. This complicates the manufacturing process and increases the costs of the whole semiconductor module.
Thus, in the prior art, with a three-dimensionally mounted semiconductor module in which semiconductor chips are stacked on an interconnect substrate in a vertical direction, cooling efficiency decreases with an increase in the number of chips stacked. In particular, it is disadvantageously difficult to adequately cool semiconductor chips in inner layers. Further, complicated micromachining is required in order to utilize the microchannel cooling. This disadvantageously complicates the manufacturing process and increases manufacturing costs.
USPTO Backgrounds
USPTO Backgrounds