The present disclosure relates to a semiconductor device including a plurality of semiconductor chips within the same package.
In recent years, as electronic apparatuses that have more functions and are smaller in size have been developed, semiconductor devices used therein have also been caused to be more multifunctional and thinner. The development of a semiconductor device including a plurality of semiconductor chips within the same package has been required. To achieve such a purpose, there is a conventional known semiconductor device having a structure in which a plurality of semiconductor chips are provided on the same die pad, or a structure in which a plurality of die pads are provided within the same package, and further, a plurality of semiconductor chips are provided on the respective die pads.
Hereinafter, a structure of a conventional semiconductor device, specifically, a Quad Flat Package (QFP package) having a plurality of die pads within the same package, will be described with reference to FIGS. 10A and 10B and 11A to 11E.
FIGS. 10A and 10B are cross-sectional views of a structure of a QFP package as a conventional semiconductor device.
In the conventional QFP package of FIGS. 10A and 10B, die pads 101 and 102 are formed within the same package. The die pads 101 and 102 have a Point Support Die pad (PSD) structure. A semiconductor chip 104 is electrically connected via an electrically conductive resin 103 to the die pad 101. A semiconductor chip 105 is electrically connected via the electrically conductive resin 103 to the die pad 102. Electrodes 106 on the semiconductor chips 104 and 105 are electrically connected via gold wires 109 to inner leads 108 of a lead frame 107 that is a part of the package. The semiconductor chips 104 and 105 are also electrically connected to each other via gold wires 109 so that they can exchange information. The resultant structure is sealed with a sealing resin, which forms an outer shape of the semiconductor device.
As can be seen from FIGS. 10A and 10B, in the conventional QFP package having the structure described above, the die pads 101 and 102 are positioned at different heights, but not at the same height. Thus, in a PSD structure in which semiconductor chips provided on die pads have larger sizes than those of the respective die pads, the arrangement of the die pads at different heights allows portions of semiconductor chips extending off the respective upper and lower die pads to three-dimensionally overlap each other, as shown in FIG. 10B. Therefore, an area occupied by all of the semiconductor chips within the package is reduced, so that the package can be reduced in size.
Next, a method for fabricating a conventional semiconductor device (QFP package) will be described.
FIGS. 11A to 11E are cross-sectional views schematically showing the conventional semiconductor device (QFP package) fabricating method.
Initially, as shown in FIG. 11A, an electrically conductive resin 103 is applied onto die pads 101 and 102.
Next, as shown in FIG. 11B, semiconductor chips 105 and 106 are mounted onto the die pads 101 and 102, respectively, with the electrically conductive resin 103 being interposed therebetween. When the semiconductor chips 105 and 106 have regions overlapping each other, the semiconductor chips 105 and 106 will be damaged if the semiconductor chips 105 and 106 contact each other. Therefore, in order to prevent from the semiconductor chips 105 and 106 from contacting each other, the semiconductor chips 105 and 106 need to be carefully isolated from each other in a region where the semiconductor chips 105 and 106 three-dimensionally overlap each other. After the semiconductor chips 105 and 106 are mounted, the electrically conductive resin 103 is cured in a curing furnace (not shown).
Next, as shown in FIG. 11C, gold wires 109 connecting a lead frame 107 and the semiconductor chips 104 and 105 and gold wire 109 connecting the semiconductor chips 104 and 105 are provided by performing a wire bonding step. During wire bonding between the semiconductor chips 104 and 105, it is necessary to hold the semiconductor chips 104 and 105 in a manner that prevents the semiconductor chips 104 and 105 from contacting each other.
Next, as shown in FIG. 11D, a sealing step is performed by a known technique using a sealing mold and a sealing resin 114.
Next, as shown in FIG. 11E, a step of working the lead frame 107 is performed. Packages are isolated from each other along the lead frame 107. A shape of an external connection lead 111 of the lead frame 107 is changed. Thus, a semiconductor device is completed.
As described above, a semiconductor chip is mounted in a resin package, so that the semiconductor chip is allowed to function while electrical connection thereof is protected from external environments (the above description is based on Japanese Unexamined Patent Application Publication No. 2005-347428).
Also, Japanese Unexamined Patent Application Publication No. 2008-28006 discloses a semiconductor device that includes separate die pads and has excellent heat dissipating capability. In this semiconductor device, a common metal plate for heat dissipation is provided for a plurality of die pads, and the heat dissipating metal plate is exposed from a sealing resin. Note that the die pads are provided on the same plane while sharing the heat dissipating metal plate, so that a chip having a larger size than that of a die pad cannot be connected to the die pad, for example.
USPTO Backgrounds
USPTO Backgrounds