1. Field of the Invention
This invention relates generally to semiconductor fabrication, and, more particularly, to bypassing silicon bugs formed during semiconductor fabrication.
2. Description of the Related Art
Conventional devices formed on semiconductor chips, such as processors and memory elements, can include thousands or millions of interconnected transistors and other electronic elements. The operation of these individual components must be precisely coordinated so that the device can perform its desired function. However, despite the best efforts of the design engineers, initial circuit designs almost invariably include numerous “bugs,” e.g., defects or errors in the design that cause the device to operate incorrectly, generate errors, lock up, or fail to operate at all. Almost by definition, the presence of bugs is impossible to detect in a device design and so an actual device must be fabricated and tested to find bugs. For example, engineers may use computer-aided design to generate a representation of a design for a cache memory and use this design to control fabrication of prototype devices. The design may (and in fact should) appear bug-free to design engineers prior to testing an actual device. Nevertheless, when the signals are applied to a cache memory formed on a chip using the design, the cache memory may malfunction. For example, the cache logic may become locked in a repetitive loop and perform the same operation over and over in response to particular combinations of events, such as a particular combination of cache hits and/or misses.
Engineers typically use an iterative process to identify and correct bugs in a design. The process begins by creating an initial design and using this design to form a device in silicon. The device is then subjected to a battery of tests that are intended to reveal any bugs in the design. If the test results reveal the presence of one or more bugs in the design, engineers attempt to identify the root causes of the bug(s) and modify the design to correct the bug. The modified design can then be used to form another device in silicon so that the new design and device can be tested to make sure that the previously identified bugs have been removed and no new bugs have been added. Each iteration of the testing process increases the design costs for the device and delays production of the device. The testing process would therefore ideally reveal all of the bugs in the device design during one iteration. However, this virtually never occurs in practice at least in part because the presence of one bug may obscure the presence of another bug until the first bug is corrected. For example, if events early in the testing process lead to a fatal error caused by a first bug, then the testing process will not be able to detect any bugs that may be triggered by subsequent events in the testing process. These bugs can only be detected after the first bug has been corrected so that the testing process can proceed to the subsequent events.
One approach to correcting bugs during design testing is to use focused ion beam processes to correct the bug or at least to prevent the bug from occurring during testing. For example, the focused ion beam can be used to modify the circuit on the chip to correct the bug or at least to re-wire the circuit so that the bug does not occur. This approach has the advantage of allowing testing to proceed past a particular bug so that additional bugs can be detected on the same physical device and therefore within the same iteration of the testing process. However, focused ion beam modifications are difficult, expensive, and require significant manual input from engineers. For example, an engineer may need to examine the actual chip with a scanning electron microscope to identify a particular wire that needs to be cut or to identify a location where a new wire should be fabricated. The engineer then needs to configure the focused ion beam device to perform the desired operation at the identified location. These techniques are too time intensive and labor intensive to be used during production runs and so they do not save silicon revisions.
Additional metal spins can be used to modify the metal layers in the device while leaving the base layers substantially intact. The metal spins can fix many bugs and allow validation of the design to continue. They can also be used to fix bugs in volume and so they can be used on production runs to produce chips that are shipped to customers, thereby reducing the time required to get the chips to production. However, a metal spin takes weeks to perform and costs hundreds of thousands of dollars. Metal spins are therefore not used between each iteration of the testing process.
USPTO Backgrounds
USPTO Backgrounds