The present invention relates to interconnect systems for use on a reconfigurable chip.
Reconfigurable chips typically have a number of reconfigurable elements, which transfer data through interconnect units to other reconfigurable elements. FIG. 1 shows a prior-art reconfigurable chip arrangement. The reconfigurable chip 20 includes a number of reconfigurable elements 22, 24, 26, 28, 30, 32 and 34 which can be interconnected through interconnect elements 36, 38, 40, 42, 44 and 46. Typically, interconnect elements 36-46 are pass gates that allow signals to be transferred in either direction between the reconfigurable elements. The reconfigurable elements can be, for example, reconfigurable logic blocks, data path units or the like.
The problem with the arrangement shown in FIG. 1 is that if data is to be sent between element 22 and element 34, the data will pass through each of the pass gates 36-46. This can induce an unacceptable resistive/capacitive (RC) signal delay, resulting in an unacceptable signal rise and fall time. The RC delay can impact the total timing and affect the speed of the reconfigurable chip itself.
It is desired to reduce the problem of the RC delay between elements on a reconfigurable chip.
The present invention comprises a reconfigurable chip with a reduced signal rise and fall time between reconfigurable elements.
One embodiment of the present invention comprises a reconfigurable chip with a plurality of reconfigurable elements arranged in a line. The interconnection units are arranged in a first path to allow the plurality of elements to be interconnected to one another. A bypass path includes at least one additional interconnection unit. The bypass path allows the interconnection of at least some of the elements while bypassing a number of interconnection units in the first path so as to reduce the signal delay between some of the elements. The use of the bypass path reduces the maximum signal delay and thus can improve the interconnection speeds for the reconfigurable chip.
A number of other embodiments of the present invention use buffer elements. The buffer elements reduce rise and fall times by driving the parasitic capacitance in the path. One disadvantage of using the buffers is that some manner of arranging a connection between all the reconfigurable elements must be provided.
One embodiment of the present invention is a reconfigurable chip comprising a plurality of elements arranged in a line, and an interconnection path arranged in a loop to allow the plurality of elements to be interconnected to one another. The interconnection path includes buffer elements to reduce the signal delay and isolating elements to electrically isolate different sections of the loop.
Another embodiment of the present invention comprises a reconfigurable chip comprising a plurality of elements arranged in a line, and interconnection paths to allow the plurality of elements to be interconnected to one another. The interconnection paths can include buffer elements to reduce signal rise and fall times and isolating elements to electrically isolate sections of the path. The buffer and isolating elements are arranged such that signals can go in either directions along path sections.
USPTO Backgrounds
USPTO Backgrounds