Recently, as semiconductor integrated circuits have become more highly integrated and their operation speed has increased, metal lines in semiconductor devices have become narrower and multi-layered. In addition, copper wiring and low dielectric constant (low-k) materials have been proposed for minimizing the RC signal delay associated with such lines. Furthermore, patterning of wiring has become more difficult as the design rule has decreased, and, thus, a damascene process has been developed to skip a metal etching step and an insulator gap-filling step in a metallization process. Such a damascene processes may be categorized as single damascene and dual damascene processes. A conventional method of metallization by a dual damascene process will hereinafter be described as an example of a general damascene process.
An etch stop layer, an intermetal insulating layer, and an anti-reflection layer are sequentially formed on a lower metal layer. Then, a via mask is formed on the anti-reflection layer. A via hole is formed by selectively etching the anti-reflection layer and the intermetal insulating layer by the via mask and then ashing the mask.
After filling the via hole with a sacrificial layer (for example, formed of novolac), the sacrificial layer is recessed to a predetermined depth. Then, after coating an anti-reflection layer, a trench mask is formed. A trench is then formed by a dry etching process using the trench mask.
Subsequently, the trench mask and the sacrificial layer remaining in the via hole are removed by an ashing process. In addition, the etch stop layer exposed in the bottom of the via hole is removed to complete a dual damascene pattern including a via hole and a trench. A metallization process is then completed by subsequently forming a barrier metal layer in the damascene pattern, filling the damascene pattern with a conductive material such as copper, and polishing the conductive material.
In such a conventional method of fabricating metal wiring, mask patterns for a via hole and a trench are separately required, since the via hole is formed first and then the trench is formed. Therefore, a process for fabricating metal wiring is complicated since the dry etching process using the mask and the ashing process for removing the mask pattern are respectively performed twice, and a sacrificial layer is involved.
In addition, in the conventional method of fabricating metal wiring described above, when the sacrificial layer is not completely removed during the ashing process for removing the trench mask, the etch stop layer is also not completely removed. Accordingly, the contact resistance increases, thereby causing a degradation of device characteristics.
To clarify multiple layers and regions, the thickness of the layers are enlarged in the drawings. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way positioned on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.
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