(a) Technical Field
The present disclosure is directed to a thin film transistor array panel and a manufacturing method thereof.
(b) Description of the Related Art
In general, a thin film transistor array panel includes a gate electrode disposed on a substrate, a gate insulating layer disposed on the gate electrode, a semiconductor layer disposed on the gate insulating layer, a source electrode and a drain electrode disposed on the semiconductor layer and facing each other with respect to the gate electrode, and an ohmic contact disposed between the source electrode and drain electrode and the semiconductor layer.
In addition, a thin film transistor array panel typically includes a channel formed in the semiconductor layer between the source electrode and the drain electrode that is referred to as a horizontal channel.
An interval between the source electrode and the drain electrode has a minimum size that is determined by the resolution of the light exposer used to form the source electrode and the drain electrode in a photolithography process. Accordingly, reducing the length of the interval between the source electrode and the drain electrode to be less than the light exposer resolution is a challenge.
In addition, parasitic capacitance between the gate electrode and the source electrode and between the gate electrode and the drain electrode generated by an overlap between the source electrode and drain electrode and the gate electrode decreases an on-current of the thin film transistor.
Furthermore, the ohmic contact is made from an impurity-doped portion of the semiconductor layer that is formed under the source and drain electrodes, and forming the ohmic contact may damage the channel portion of the semiconductor layer.
USPTO Backgrounds
USPTO Backgrounds