(1) Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and more particularly to the fabrication of dynamic random access memory (DRAM) device having capacitors with increased capacitance.
(2) Description of the Prior Art
Advances in semiconductor processing technologies has dramatically decreased the size of discrete devices on semiconductor substrates and have increased the integrated circuit density on the substrate. The dynamic random access memory (DRAM) device is one type of semiconductor devices experiencing this down scaling is size and increase in density. This DRAM device is used extensively in the electronic industry and particularly in the computer industry for data storage. The DRAM device is composed of an array of memory cells which are addressable by peripheral circuits on the chip for reading and writing information on the individual cells. These individual memory cells are formed from a single pass transistor and storage capacitor, and the information is represented on the cell as binary data by the presents of charge on the storage capacitor. The number of memory cells on a DRAM chip are expected to reach 256 Megabits by the year 1998 and about 1 Gigabits by the year 2001. If these goals are to be achieved on a DRAM chip of reasonable size, then the memory cells on the chip must be substantially reduced in size. For the latest technology Roadmap on the future trends in DRAMs by the Semiconductor Industry Association (SIA) see, the article entitled "Extending Optical Lithography to the Gigabit Era" by M. Levenson, in Solid State Technology, page 57, Feb. 1995, with specific reference to table I.
Unfortunately, as the individual memory cells decrease in size, the storage capacitor must also decrease in size. However, the reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain the required signal-to-noise level, and to maintain a reasonable refresh cycle time to retain the necessary charge level. Therefore, alternative methods are required to maintain the capacitance while restricting the capacitor area to the size of the smaller cell area.
Two basic approaches for increasing capacitance without increasing the physical area of the capacitor is to use a trench capacitor formed within a trench in the cell area, and a stacked capacitor formed on the cell area over the transistor. However, as the cell area decreases in size it becomes increasingly more difficult to form the deeper trench required for trench capacitance and to also provide the area for the transistor. The stacked capacitor, however, has received considerable interest in recent years because of the variety of ways that its shape can be changed in the third dimension (vertical direction) to increase the capacitance without increasing the area it occupies on the substrate.
Numerous three dimensional capacitor structures have been reported in the literature. For example, K. Seo, U.S. Pat. No. 5,071,781, and H. M. Chou, U.S. Pat. No. 5,286,668 teach methods for making a stacked capacitor having fin-shaped electrodes that extend upward and outward over the cell area. Another approach is to build vertical extending sidewalls and columns, as described by P. Fazan, U.S. Pat. No. 5,234,858, and by Y. Jun, U.S. Pat. No. 5,219,780. Still another method for making a capacitor having a H-shaped electrode structure is described by H. Chan, U.S. Pat No. 5,137,842.
In general, the methods involve more processing step and are more costly to manufacture and have lower process and final test yields. Therefore, there is still a need to further improve the capacitor structures and provide a simple manufacturing process.
USPTO Backgrounds
USPTO Backgrounds