1. Field of the Invention
This invention relates to Hall effect semiconductor devices. More particularly, it relates to methods of manufacturing Hall effect devices which minimize introduction of offset voltages resulting from piezoresistance effects induced by device packaging.
2. Description of the Prior Art
Various semiconductor devices have been designed, fabricated and mass-produced utilizing the well known Hall effect. For example, Hall effect switches and the like commonly employ a silicon body through which a bias current is passed between two spaced apart contacts or terminals. Sensing terminals are positioned on opposite sides of the bias current path and spaced equidistant from the two spaced apart bias current input terminals to detect a voltage potential in a direction perpendicular to the bias current path. Ideally, zero potential is developed between the sensing terminals in the absence of a magnetic field. Unfortunately, the ideal condition is seldom achievable in the real world because of various factors other than Hall effect.
One of the most significant factors contributing to non-ideal performance of Hall effect devices is the piezoresistance sensitivity of semiconductor materials such as silicon. For example, most semiconductor devices must be encapsulated in a suitable housing or package for protection of the semiconductor element. The semiconductor device is typically mounted on a substrate and encapsulated in a protective body such as epoxy, plastic or the like. Since the mounting substrate and the encapsulation material generally have different coefficients of thermal expansion and elastic moduli which are also different from the coefficient of thermal expansion and elastic modulus of silicon, mounting and encapsulation of the silicon chip place mechanical stresses on the chip. Since silicon is piezoresistive, physical stresses placed on the chip alter its electrical resistance characteristics resulting in voltage offsets produced by mechanical stress rather than Hall effect.
Prior attempts to minimize voltage offsets resulting from mechanical stress generally concentrated on reduction of mechanical stress. Thus encapsulation materials and mounting techniques have been developed which reduce (but not eliminate) mechanical stress. Unfortunately, such encapsulation materials and mounting techniques are generally expensive and thus add considerably to the production cost of the devices. Attempts have also been made to predetermine predictable stress effects and orient the Hall element with respect to the crystallographic orientation of the chip to minimize stress effects and/or provide trimming resistors to compensate for piezoresistance effects. While these approaches are somewhat satisfactory for gross adjustments to predeterminable voltage offsets, they suffer from lack of reproducibility and sensitivity to packaging process parameters and, of course, trimming resistors formed in the integrated circuit chip cannot be used to further adjust voltage offsets after the device has been encapsulated.
USPTO Backgrounds
USPTO Backgrounds