A serial data system consists of a transmit circuit for transmitting data bits on a serial link to a receive circuit. In a serial data system, the timing information to sample the incoming data signal is embedded in the data stream. To recover a time to sample or clock the incoming data signal, most receive circuits include a Clock-Data Recovery (“CDR”) circuit to synchronize a sample clock with the incoming data. A CDR circuit actively looks for transitions in the incoming data and phase aligns a sample clock signal with respect to the incoming data transitions to provide maximum setup-hold timing margins.
A CDR circuit is typically responsible for tracking incoming data over a range of bit-rates. However, the bit-rate of the incoming data may be different than the frequency of the sample clock. Further, the bit-rate of the incoming data may vary over time with respect to the sample clock frequency. For example, the bit-rate of an incoming data signal may range between 1.50045 GHz and 1.49955 GHz at any particular time. In other words, a CDR circuit needs to track a data signal having a bit-rate of approximately 1.5 GHz±300 parts per million (“ppm”).
Therefore, it is desirable to provide a circuit, such as a CDR circuit, apparatus and method that is capable of synchronizing a sample clock signal to incoming data even when such incoming data has a high variable data bit-rate.
USPTO Backgrounds
USPTO Backgrounds