The present invention relates to semiconductor integrated circuits, and more particularly relates to a power-supply wiring structure for optimizing the amount of IR drop and the flow of current in the power-supply wiring.
As semiconductor devices for semiconductor integrated circuits have been miniscaled, the number of semiconductor devices integrated on a chip has been increasing year after year, forcing the power-supply wiring in the chip to be increased in length and decreased in wire width. In addition, the problem of how to ensure signal integrity has manifested itself. In particular, how to deal with IR drop and electro migration (which will be hereinafter referred to as “EM”) that occur in power-supply wiring has become a critical issue.
Conventional techniques for addressing these problems of IR drop and EM that occur in power-supply wiring will be described below.
If a miniscaled semiconductor device has a scaling coefficient of k, the wire length, wire width, wire-to-wire distance, and wire thickness of the power-supply wiring is reduced by the scaling coefficient k in order to keep effects on the semiconductor device at the same level as those in the conventional fabrication process. As a result, a wire resistance per unit length of the power-supply wiring increases to the square of the scaling coefficient k, and the IR drop resulting from the increased resistance of the power-supply wiring decreases the operational reliability of the semiconductor device. A conventional technique for overcoming this IR-drop-related problem is described, for example, in Japanese Laid-Open Publication No. 11-45979 (Document 1).
FIG. 12 illustrates the conventional technique disclosed in Document 1, which provides a method for power-supply wiring arrangement. In FIG. 12, power-supply wiring 110 and ground wiring 120 for supplying power supply voltages to internal circuits are disposed in a semiconductor chip 100. The power-supply wiring 110 and the ground wiring 120 extend vertically and horizontally to form lattices. The lattice-shaped power-supply wiring 110 is connected with power supply pads 130 for supplying the power supply voltage provided from an external device. Likewise, the lattice-shaped ground wiring 120 is connected with ground pads 140.
In FIG. 12, supporting power-supply wiring 150 and supporting ground wiring 160 are disposed to support the lattice-shaped power-supply wiring 110 and the lattice-shaped ground wiring 120, respectively. The supporting power-supply wiring 150 is connected to a power supply pad 170, which is provided independently of the power supply pads 130, while the supporting power-supply wiring 150 is divided into branches, which are connected to the lattice-shaped power-supply wiring 110. Similarly, the supporting ground wiring 160 is connected to a ground pad 180, which is provided independently of the ground pads 140, while the supporting ground wiring 160 is divided into branches, which are connected to the lattice-shaped ground wiring 120.
In the power-supply wiring structure shown in Document 1, the supporting power-supply wiring 150 connected to the ground pad 170 that operates independently of the power supply pads 130 is connected to the lattice-shaped power-supply wiring 110, while the supporting ground wiring 160 connected to the ground pad 180 that operates independently of the ground pads 140 is connected to the lattice-shaped ground wiring 120, whereby IR drop can be restricted within certain limits so that the circuit operation is not affected by the IR drop.
On the other hand, when the scaling of a semiconductor device is reduced by a factor k, and so are the wire length, wire width, wire-to-wire distance, and wire thickness of the power-supply wiring, the current density in the power-supply wiring is increased by the factor k. This increase in the current density in the power-supply wiring raises the rate of occurrence of EM-related wire breaks. EM is a phenomenon in which metal atoms in wiring are diffused by interaction between the metal atoms and the electrons traveling through the wiring to cause failures in the wiring. Specifically, EM causes the creation of voids at the cathode of the wiring, leading to an open failure, or causes the growth of hillocks or whiskers at the anode of the wiring, resulting in a short failure. As a measure to solve these EM-caused problems, there has been a conventional technique, which is disclosed in Japanese Laid-Open Publication No. 10-56162 (Document 2), for example.
FIG. 13 illustrates a power-supply wiring structure disclosed in Document 2. In FIG. 13, a plurality of vertically extending wire tracks Y0 to Y3 are spaced uniformly, while a plurality of horizontally extending wire track X0 to X6 are spaced at two different intervals. More specifically, the set of horizontal lines is defined by the wire tracks X1 to X3 and X4 to X6 that have a first pitch and the wire tracks X0 to X1 and X3 to X4 that have a second pitch, which is narrower than the first pitch. In this structure, a power supply wire 200 formed along the wire track X2 of the wire channel lattice, and a power supply wire 210 formed along the wire track X5 can be formed to have a large wire width, for example. As in this technique, if the pitch distance between adjacent wire tracks in some areas is set larger than in the other area, some wires in the power-supply wiring can have a larger width. As a result, the cross sectional area of those power-supply wires with a larger width is increased, thereby effectively suppressing EM-caused reduction in wire yield.
Another conventional technique for overcoming the EM-caused problems is described in Japanese Laid-Open Publication No. 8-46049 (Document 3), for example. FIG. 14 illustrates a power-supply wiring structure disclosed in Document 3. In FIG. 14, a first-layer wire 320, which is a thin signal wire, is connected to a semiconductor substrate 300 by a contact 310, and also connected to a third-layer wire 340 by a via 330. On the other hand, a first-layer power supply wire 350 and a second-layer power supply wire 360 are in direct contact with each other with no via interposed therebetween. The first-layer wire 350 is connected to the semiconductor substrate 300 by a contact 310, while the second-layer wire 360 is connected to the third-layer wire 340 by a via 370. In this power-supply wiring structure, it can be considered that the cross sectional area of the power supply wire 350 is increased by the second-layer power supply wire 360, such that resistance to EM can be increased.
However, in cases in which the technique disclosed in Document 1 is employed as a measure to cope with the above-mentioned IR drop, the lattice-shaped power-supply wiring 110 is directly connected to cell power-supply wiring formed on lower cells located below the lattice-shaped power-supply wiring 110, by vias formed in an insulating layer provided between the lattice-shaped power-supply wiring 110 and the cell power-supply wiring, in order to supply power from the upper lattice-shaped power-supply wiring 110 to the lower cells. In this technique, since the supporting power-supply wiring 150 also supplies power so as to overcome the IR-drop problem, the current density is increased at the connection points of the cell power-supply wiring to the vias. Therefore, the wire width of the cell power-supply wiring must be increased so that the current density in the cell power-supply wiring does not exceed a maximum allowable current density level. It is thus difficult to reduce the wire width of the cell power-supply wiring for reduction in the cell area, which results in the increased cell area.
On the other hand, when the technique disclosed in Document 2 is used as a measure to address the problem of maximum allowable current density in the cell power-supply wiring, that is, as a measure to improve resistance to EM, there arises the disadvantage of causing the resultant semiconductor chip area to be increased. Specifically, when the technique in Document 2, which is designed to be applied to gate array cells, is applied to a standard cell system, the distance between the cell power-supply wiring and the cell ground wiring, and hence the area of each cell, are increased. This results in increases in the semiconductor chip area.
Moreover, when the technique disclosed in Document 3 is used as a measure to improve EM resistance, the following disadvantage arises. Since the first-layer power supply wire 350 and the second-layer power supply wire 360 are in direct contact with each other, the wiring thickness is increased. Consequently, the fringing capacitance between the side faces of the power supply wires 350 and 360 and the signal wire 320 located close to those side faces is increased and cannot be regarded as negligible anymore, and the resultant crosstalk with the neighboring signal wire 320 increases signal propagation delay or causes noises in the signal wire 320.
USPTO Backgrounds
USPTO Backgrounds