The present invention relates generally to semiconductors, and more specifically, to semiconductor chip authentication.
Authentic semiconductor components are verified by semiconductor manufacturers to meet graded specifications. As a part of the testing and verification process, labels that identify the semiconductor component may be placed on a viewable surface, such as a semiconductor package. However, information contained on the label, for example, can be easily altered. Also, identifiable information may be programmed within memory such as electrically erasable programmable read-only memory (EEPROM). Memory such as EEPROM can be duplicated and has a limited lifetime.
Given the relatively small size of semiconductor components, surface identification of authentic chips may also be difficult. The use of readily available on-chip identification can lead to tamper which may include, but is not limited to, a duplication or a counterfeit substitute in place of the original integrated circuit within the package.
USPTO Backgrounds
USPTO Backgrounds