1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and particularly relates to a semiconductor integrated circuit having a logic and a memory integrated on the same semiconductor substrate. Specifically, the present invention relates to a construction for testing the memory. More specifically, the present invention relates to a construction for testing a tri-state output circuit of the memory externally.
2. Description of the Background Art
In recent years, as the development of a technique for semiconductor integrated circuit devices progresses, various technical innovations including the miniaturization, high integration and speed up of the circuit devices have been achieved. In order to reduce the manufacturing cost of a semiconductor integrated circuit device and to speed up the operation thereof, a semiconductor device having a semiconductor storage unit (memory) and a semiconductor logic circuit unit (logic) assembled on a single semiconductor chip is under development.
FIG. 16 is a schematic diagram showing an example of the construction of a conventional semiconductor integrated circuit device. In FIG. 16, a semiconductor integrated circuit device 1 includes memories ME0 and ME1 each of which is, for example, a DRAM (dynamic random access memory) and a logic 2 integrated on the same semiconductor chip with memories ME0 and ME1. Memories ME0 and ME1 are coupled to logic 2 in parallel through a common data bus 3. This common data bus 3 includes a memory data bus section 3a coupled to memory ME0, a memory data bus section 3b coupled to memory ME1 and a data bus section 3c coupled to a bus terminating circuit BT.
Bus terminating circuit BT sets the respective bus lines of data bus sections 3, 3a, 3b and 3c at a predetermined voltage level (pulls up or down the respective bus lines of data bus sections 3, 3a, 3b and 3c) since the output circuits of memories ME0 and ME1 enter a high impedance state when being unselected.
Semiconductor integrated circuit device 1 further includes DMA circuits (direct memory access circuits: test interface circuits) TF0 and TF1 provided corresponding to memories ME0 and ME1, respectively. DMA circuits TF0 and TF1 are coupled to memories ME0 and ME1 through data buses 3a and 3b, respectively.
Testers TA0 and TA1 provided externally directly access memories ME0 and ME1 through DMA circuits TF0 and TF1, to execute tests for memories ME0 and ME1, respectively.
Logic 2 and memories ME0 and ME1 are interconnected through an address/command bus 4 transferring addresses and commands. Address/command bus 4 is also connectable to external testers (test units) TA0 and TA1.
By integrating memories ME0 and ME1 on the same semiconductor chip, the interconnection internal common buses 3 and 4 interconnecting logic 2 and memories ME0 and ME1 are made using on-chip interconnection lines. Due to this, compared with on-board wiring, interconnection line load is small, signals/data can be transferred at high speed and high-speed access can be achieved. In addition, since memories ME0 and ME1 are not provided with pin terminals, there are no restrictions such as pitch conditions of the pin terminals and the bus width of common data bus 3 can be set sufficiently large. For example, common data bus 3 has a bus width of 32 to 256 bits, to make it possible to transfer a large quantity of data at high speed.
For the semiconductor integrated circuit device in which logic 2 and memories ME0 and ME1 are integrated on the same semiconductor substrate, an external processor can only transmit and receive data/signals to and from logic 2. Logic 2 accesses memories ME0 and ME1 in accordance with a request of the external processor, executes a necessary processing and stores the execution result in memories ME0 and ME1. Only logic 2 can, therefore, access memories ME0 and ME1.
Accordingly, when memories ME0 and ME1 are tested before the shipment of products and memories ME0 and ME1 are tested through logic 2, then the influence of logic 2 reflects on the test contents, thereby preventing the memories from being accurately tested. Considering such situation, external test units (testers) TA0 and TA1 are allowed to directly access memories ME0 and ME1 using a test interface circuit and to determine whether or not memories ME0 and ME1 satisfy predetermined specification conditions and accurately operate.
Bus terminating circuit BT is provided to prevent common data bus 3 from entering an electrically floating state and to match the output impedance of the output circuits of the memories with the input impedance of logic 2 since memories ME0 and ME1 are coupled in common to data bus 3 and enter a high output impedance state while being unselected.
As for common data bus 3, a write data bus transferring data written to memories ME0 and ME1 and a read data bus transferring data read from memories ME0 and ME1 are provided in common, or the write data bus and the read data bus are provided separately. Since common data bus 3 is shared between memories ME0 and ME1, bus terminating circuit BT fixes the potentials of the respective bus lines of common data bus 3 when memories ME0 and ME1 are unselected.
FIG. 17 is a schematic diagram showing the construction of the data output section of memories ME0 and ME1. Since memories ME0 and ME1 have output sections having the same construction, FIG. 17 representatively shows one memory ME.
In FIG. 17, memory ME includes an output circuit OPK transmitting data read from a memory circuit MKT to the bus lines IO<0> to IO<N−1> of external common data bus 3 in accordance with an output enable signal OE. Memory circuit MKT includes a memory cell array, a memory cell selection circuit, an internal data read circuit and others.
Output circuit OPK includes output buffers OBF's provided corresponding to common data bus lines IO<0> to IO<N−1>, respectively. Each output buffer OBF enters an output high impedance state when output enable signal OE is inactive, which allows data to be transferred between a select memory out of memories ME0 and ME1 and logic 2.
FIG. 18 is a schematic diagram showing the construction of the DMA circuit shown in FIG. 16. Since DMA circuits TF0 and TF1 have the same construction, FIG. 18 representatively shows one DMA circuit TF.
In FIG. 18, DMA circuit TF includes a buffer circuit 500 inputting and outputting data to and from the external test unit (tester), and a data selector 502 for transferring data between buffer circuit 500 and internal data bus lines IO<N−1:0>. Buffer circuit 500 inputs and outputs, as test data TDQ, data of 16 bits or 8 bits in accordance with the number of the data input and output lines of the external test unit (tester). By way of example, FIG. 18 shows a construction in which 8 bits TDB<0> to TDB<7> of test data are inputted and outputted through buffer circuit 500.
Common data bus 3 provided in the semiconductor integrated circuit device, is constituted of data bus lines IO<N−1:0>, and has a width of N bits. Upon outputting data, data selector 502 adjusts the data transfer width between buffer circuit 500 and internal data bus lines IO<N−1:0>. Upon writing test data, data selector 502 is supplied with test data bits TDB<0> to TDB<7> from buffer circuit 500, expands the bit width of the test data bits by a copy operation or the like for transmission onto internal data bus lines IO<N−1:0>. Upon reading test data, data selector 502 converts N-bit test data read onto internal data bus lines IO<N−1:0> into test data TDB<0> to TDB<7> of 8-bit width for outputting. Data selector 502 may sequentially transmit data on internal data bus lines IO<N−1:0> to the test unit (tester) through buffer circuit 500 in a unit of 8 bits, or may selectively transmit data on specific bus lines among internal data bus lines IO<N−1:0> as test data bits TDB<0> to TDB<7> to the test unit (tester) through buffer circuit 500.
In the semiconductor integrated circuit in which logic 2 and memories ME0 and ME1 are integrated on the same semiconductor chip, by utilizing DMA circuits TF0 and TF1, external testers TA0 and TA1 can directly access memories ME0 and ME1 or transmit and receive data to and from memories ME0 and ME1 without using logic 2, respectively. It is, therefore, possible to accurately determine whether or not memories ME0 and ME1 are normally operated.
It is noted that testers TA0 and TA1 may test respective memories ME0 and ME1 simultaneously or individually. Also, testers TA0 and TA1 may be test units having different test contents.
FIG. 19 is a schematic diagram showing the construction of a portion of buffer circuit 500 shown in FIG. 18, which portion is related to 1-bit data. In FIG. 19, buffer circuit 500 includes an inverter 10 inverting a test output enable signal TOE, a tri-state buffer circuit 12 activated when a complementary test output enable signal ZTOE from inverter 10 is inactive (at an H level), for buffering test input data TIO<i> to generate internal test data TOB<i>, a flip-flop (FF) 14 transferring test data bit TDB<i> in accordance with a test data output control clock signal DOCKL when the test data is outputted, and a tri-state buffer circuit 16 activated when test output enable signal TOE is active (at H level), for buffering the test data from flip-flop 14 to generate test output data TIO<i>.
Test output enable signal TOE is a signal applied from the external tester. In accordance with test output enable signal TOE, buffer circuit 500 is set into either a data output mode or a data input mode in a test mode. Memories ME0 and ME1 are clock synchronous type semiconductor memories operating synchronously with a clock signal. A test data output control clock signal DOCLK is generated in accordance with a test clock signal applied in place of the clock signal when buffer circuit 500 is in this test mode. Now, the operation of buffer circuit 500 shown in FIG. 19 will be described.
Now, as shown in FIG. 20, description will be given to a case where bus terminating circuit BT has a pull-up function for pulling up each of internal data bus lines IO<N−1:0> to a power supply voltage Vdd level. Namely, a terminating voltage Vt is at the power supply voltage Vdd level.
When test data is read, data output control clock signal DOCLK is generated in accordance with a master clock signal (test clock signal) CLK. Data D (D0, D1) read to internal data bus line IO<k> are sequentially selected by data selector 502 shown in FIG. 18 and are applied to buffer circuit 500 in accordance with master clock signal CLK. Data selector 502 performs a selection operation in accordance with a test select signal TDS. In accordance with the data read onto internal data bus line IO<k>, output bit TDB<i> of data selector 502 changes.
Flip-flop 14 transfers this test data bit TDB<i> in accordance with data output control clock signal DOCLK. In FIG. 20, in response to the rise of test data output control clock signal DOCLK, test data bit DO is outputted from flip-flop 14 and then test data TIO<i> is outputted through tri-state buffer 1 in an active state.
Accordingly, if internal data bus line IO<k> is pulled up to a bus terminating voltage Vt level, test data bits TDB<i> and TIO<i> are transferred as binary data changing between the H level and the L level in accordance with test data DO (D0, D1).
As shown in FIG. 17, each output buffer OBF in memory ME is in an output high impedance state when memory ME is inactivated. In a default state such as a standby state, test data bit TIO<i> outputted from DMA circuit TF through buffer circuit 500 and tri-state buffer 16 is at the power supply voltage Vdd level. Only when L-level data is outputted, test data output bit TIO<i> is driven to a ground voltage level.
With this construction, therefore, even if each output buffer OBF is set in an output high impedance state in memory ME, test output data bit TIO<i> is at the H level. Therefore, the external tester is unable to identify whether each output buffer in memory ME is outputting H-level data or set in an output high impedance state. That is, it is disadvantageously impossible to identify whether each output buffer OBF in this memory is normally controlled in three states, i.e., an H-level data output state, an L-level data output state and an output high impedance state.
Further, as shown in FIG. 21, if bus terminating voltage Vt is an intermediate voltage Vdd/2 between power supply voltage Vdd and the ground voltage and data at this intermediate voltage level is applied, DMA circuit TF cannot accurately determine whether data is at the H level or the L level. As a result, the output data of DMA circuit TF becomes uncertain. If memory ME outputs binary data, test data TDB<i> and TIO<i> are sequentially generated in accordance with test data IO<k> from the memory. As a result, if this bus terminating voltage is intermediate voltage Vdd/2, it is impossible to identify whether or not the operation of each output buffer OBF is accurately controlled to be in either of the three states in the memory.
Moreover, if bus terminating voltage Vt is an intermediate voltage and data selector 502 in DMA circuit TF has a selector constituted of a CMOS inverter circuit or the like, then a large through-current flows in the CMOS inverter in a selected state in accordance with internal data bit IO<k> at the intermediate voltage level. Likewise, if data selector 502 is an analog switch such as a CMOS transmission gate, a through-current flows in flip-flop 14 in accordance with this signal at the intermediate voltage level in buffer circuit 500. If the output signal of flip-flop 14 is not completely driven into a binary state, a through-current also flows by this signal at the intermediate voltage level in output tri-state buffer 16, making output data uncertain.
Therefore, if such a through-current is generated in DMA circuit TF, the number of internal test data bits is large and a large through-current flows. Accordingly, such a large through-current causes the power supply voltage Vdd level to be lowered or the ground voltage Gnd level to be raised, with the result that memory ME cannot be operated and tested under accurate operation conditions.
USPTO Backgrounds
USPTO Backgrounds