1. Field of the Invention
The present invention relates to a manufacturing method for semiconductor structures, and more particularly, to a manufacturing method for semiconductor structures capable of simultaneously forming semiconductor structures having different sizes.
2. Description of the Prior Art
Conventional planar metal-oxide-semiconductor (MOS) transistor has difficulty when scaling down to 65 nm and below. Therefore the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor.
Please refer to FIG. 1, which is a schematic drawing of a conventional FinFET device. As shown in FIG. 1, the conventional FinFET device 100 is formed by: first a single crystalline silicon layer of a silicon-on-insulator (SOI) substrate 102 is patterned to form a fin film (not shown) in the SOI substrate 102 by proper etching process. Then, an insulating layer 104 covering the fin film is formed and followed by forming a gate 106 covering the insulating layer 104 and the fin film. Next, ion implantation and anneal treatment are performed to form a source/drain 108 in the fin film not covered by the gate 106. Since the manufacturing processes of the FinFET device 100 are easily integrated into the traditional logic device processes, it provides superior process compatibility. Furthermore, when the FinFET device 100 is formed on the SOI substrate 102 as shown in FIG. 1, traditional shallow trench isolation (STI) is no longer in need. More important, since the FinFET device 100 increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. In addition, the channel region is longer under the same gate length, and thus the current between the source and the drain is increased.
However, the FinFET device 100 still faces many problems. For example, semiconductor structures having different sizes are formed on the substrate 102, thus to construct fine patterns (such as the fin of the FinFET device) and large patterns. However, those semiconductor structures having different sizes are formed by different processes in the prior art. Therefore, it is still in need to develop a manufacturing method for semiconductor structures having different sizes, that means a manufacturing method integrating fine patterns and large patterns is still in need.
USPTO Backgrounds
USPTO Backgrounds