1. Field of the Invention
This disclosure relates to a computer and, more particularly, to a point-to-point serial communication link between bus interface units in a computer system.
2. Description of the Related Art
A computer may have multiple buses connected between the CPUs and numerous input/output devices. The buses may have dissimilar protocols depending on which devices they link. For example, a CPU local bus connected directly to the CPU preferably transfers data at a faster rate than a peripheral bus connected to slower input/output devices. A mezzanine bus may be used to connect devices arranged between the CPU local bus and the peripheral bus. The peripheral bus can be classified as, for example, an industry standard architecture (xe2x80x9cISAxe2x80x9d) bus, an enhanced ISA (xe2x80x9cEISAxe2x80x9d) bus or a microchannel bus. The mezzanine bus can be classified as, for example, a peripheral component interconnect (xe2x80x9cPCIxe2x80x9d) bus to which higher speed input/output devices may be connected.
Coupled between the various buses are bus interface units. According to somewhat known terminology, the bus interface unit coupled between the CPU bus and the mezzanine bus (e.g. PCI bus) is often termed the xe2x80x9cnorth bridgexe2x80x9d. Similarly, the bus interface unit between the PCI bus and the peripheral bus is often termed the xe2x80x9csouth bridgexe2x80x9d.
The north bridge, henceforth termed a system interface unit, serves to link specific buses within the hierarchical bus architecture. Preferably, the system interface unit couples data, address and control signals forwarded between the CPU local bus, the PCI bus and the memory bus. Accordingly, the system interface unit may include various buffers and/or controllers situated at the interface of each bus linked by the interface unit. In addition, the system interface unit may transfer data to/from a dedicated graphics bus, and therefore may include an advanced graphics port (xe2x80x9cAGPxe2x80x9d). As a host device, the system interface unit may support both the PCI graphics transfers on the AGP (e.g., graphics-dedicated transfers associated with PCI, henceforth is referred to as a graphics component interface, or xe2x80x9cGCIxe2x80x9d), as well as AGP extensions to the PCI protocol.
Thus, two or more bus interface units may be used in a computer system to interface between the hierarchy of buses. A computer system may also implement various power management states. Such power management states may be specified by, for example, the advanced configuration and power interface (ACPI) specification. Circuitry to implement the system and power management functions may be included in one or more of the bus interface units. In order to maintain synchronization within the computer system between various system and power management states, the bus interface units may need to communicate system and power management information between each other. For example, the power state of the CPU may be known to a system interface unit that interfaces to the CPU bus, but may not be directly observable by a bus interface unit that interfaces between peripheral buses. Thus, the system interface unit may need to communicate CPU power state information to the bus interface unit. Similarly, the bus interface unit may control the power management states of various system resources, such as memory. The bus interface unit may need to apprise the system interface unit of the power management states for the system resources.
A point-to-point serial communication link between a system interface unit and a peripheral bus interface unit is provided. The system bus interface unit may interface between a CPU bus and a peripheral bus, such as the PCI bus, and may be referred to as a north bridge. The system interface unit may also interface to main memory and to an advanced graphics port. The peripheral bus interface unit may interface between a first peripheral bus, such as the PCI bus, and a second peripheral bus, such as an ISA bus, and may be referred to as a south bridge. The serial communication link between the system interface unit and the bus interface unit may be a one wire serial bus that uses a bus clock from the first peripheral bus as a timing reference. This clock may be the PCI clock. The serial communication link may use a single pin on the system interface unit and a single pin on the bus interface unit to transfer commands between the interface units. A pull-up device may be provided on the serial communication link to maintain a high voltage level on the link when it is not being driven by one of the bus interface units.
After initializing the serial communication link, the system interface unit and the bus interface unit send commands back and forth over the serial communication link. The interface units alternate between which one is sending and which one is receiving commands. For example, the system interface unit may send a command to the bus interface unit followed by the bus interface unit sending a command to the system interface unit followed by the system interface unit sending a command to the bus interface unit and so forth. Thus, commands are sent back and forth in a ping pong type fashion. A one clock turnaround period may be used between commands where neither interface unit drives the serial communication link to avoid bus contention on the serial communication link. The devices may continue alternating commands until the first peripheral bus is reset. After a reset, the serial communication link may be initialized by a command sent from the system interface unit to the bus interface unit. After initialization, the interface units trade commands in the ping pong fashion described above. If an interface unit has no command pending, a NOP (no operation) command may be sent. The commands typically may communicate system or power management information.
Broadly speaking, a computer system is provided having a first system interface unit configured to interface a processor bus to a first peripheral bus. A bus interface unit is also provided and configured to interface the first peripheral bus to a second peripheral bus. A serial communication link is present between the first system interface unit and the bus interface unit. The first system interface unit and the bus interface unit are further configured to communicate with each other across the serial communication link. A graphics device may be coupled to the first system interface unit, and a display monitor for displaying images to a user of the computer system may be coupled to the graphics device. The first system interface unit and the bus interface unit may communicate with each other across the serial communication link by sending commands across the serial communication link. The first system interface unit and the bus interface unit may alternate after each command between which device is sending and which device is receiving a command.
The first system interface unit and the bus interface unit may synchronize sending and receiving commands across the serial communication link to a common clock reference. The common clock reference may be the bus clock for the first peripheral bus, e.g., the PCI clock. A turnaround period may exist following the sending of the command during which neither interface unit drives the serial communication link. Also, a pull-up device may be included on the serial communication link to pull the serial communication link to a high voltage when the serial communication link is not actively driven. The serial communication link may be a single, point-to-point connection between one conductor on the first system interface unit and one conductor on the bus interface unit. Thus, except for the one conductor, no other conductors besides the ones present for normal bus, e.g. PCI or ISA, operation may be required.
The serial communication link may be used to communicate system information between the interface units. The interface units may alternate sending and receiving commands across the serial communication link. The commands may include a command for the first system interface unit to communicate to the bus interface unit that a processor coupled to the processor bus is in a system management mode. Another command may communicate that the processor is not in the system management mode. Power management information may also be communicated. A command may be sent from the first system interface unit to communicate to the bus interface unit that a processor coupled to the processor bus is in a reduced or low-power state. The commands may also include a command for the bus interface unit to instruct the first system interface unit to place system memory coupled to the first system interface unit in a low-power mode. Another command may be used to instruct the system interface unit to bring the system memory out of the low-power mode.
The first system interface unit may arbitrate between a graphics bus and a first peripheral bus for access to the system memory. The first system interface unit may use a command on the serial communication link to communicate to the bus interface unit that this arbitration is masked. The first system interface unit may use another command to indicate to the bus interface unit that a device coupled to the first system interface unit is requesting service or access to the system memory. This command may be a device wake-up command and may also be used by the system interface unit to initialize the serial communication link after a reset.
An arbiter for the first peripheral bus may be included in the bus interface unit. A command may be used by the bus interface unit to communicate to the system interface unit that this arbiter has been parked, or granted, to the CPU bus. Similarly, a command may be used to indicate that the first peripheral bus is unparked.
A second system interface unit may also be included and connected to the serial communication link. The commands may include a command for the second system interface unit to communicate to the first system interface unit that bus arbitration performed by the second system interface unit is masked. The first system interface unit may use a command to indicate to the bus interface unit that bus arbitration by all system interface units is masked.
A method for communicating information between interface units in a computer system may include sending a first command from a system interface unit to a bus interface unit on a serial communication link between the bus interface units. The method may also include sending a second command from the bus interface unit to the system interface unit on the serial communication link after sending the first command. The method may include continuing to send commands between the system and bus interface units with the bus interface units alternating after each command between which interface unit is receiving and which is sending a command. The method may further include initializing the serial communication link after a reset by the system interface unit sending an initialization command to the bus interface unit.
The system interface unit may interface a processor bus to a first peripheral bus, and the bus interface the first peripheral bus to a second peripheral bus. The serial communication link may be synchronized to a common clock received by the system and bus interface units. In one embodiment, neither the system nor the bus interface units drive the serial communication link for one common clock period after each command is sent. The commands may be four bits in length.
A method for communicating information between bus interface units and a computer system may include placing a CPU in a low-power state and sending, on a serial communication link between the system and bus interface units, a CPU low-power command from the system interface unit to the bus interface unit. The system interface unit may be coupled to the CPU and the CPU low-power command may be used to inform the bus interface unit that the CPU is in the low-power state. The method may also include sending on the serial communication link, a memory-off command from the bus interface unit to the system interface unit to instruct the first interface unit to place system memory coupled to the first interface unit and a power down state.
The method may further include sending on the serial communication link a system management start command from the system interface unit to the bus interface unit. The system management start command may be used to inform the bus interface unit that the CPU is in a system management mode. Similarly, a system management stop command may be sent to inform the bus interface unit that the CPU is not in the system management mode.
A device wake-up command may be sent from the system interface unit to the bus interface unit to inform the bus interface unit that a device coupled to the system interface unit is requesting service. A memory-on command may be sent from the bus interface unit to the system interface unit to instruct the system interface unit to place system memory coupled to the system interface unit in a full power state. An arbiter-parked command may be sent from the bus interface unit to the system interface unit to inform the first interface unit a bus arbiter in the second interface unit is parked.
USPTO Backgrounds
USPTO Backgrounds