The present invention pertains to field programmable devices, and in particular to a computational field programmable architecture.
Since their introduction in the 1980's, Field Programmable Devices (FPDs) have become an integral tool for digital circuit implementation. FPDs offer many advantages over conventional VLSI designs in areas such as manufacturing cost, time--to--market and in-system modification. However, the benefits of using FPDs come at a price. Re-programmable hardware is inferior in both speed and area compared to full custom VLSI circuit implementations.
FPDs implement circuits by connecting a number of generic logic elements with a flexible interconnection network. The network consists of a series of wires joined through programmable switches, whose capacitance and resistance contribute to the relative slowness of FPD-implemented circuits. The interconnect of an FPD, which can account for close to 70 percent of its total area, is also largely responsible for the fact that FPDs are larger than custom VLSI circuits.
Traditional FPDs can be divided into two classes: Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs). Both types of devices contain logic blocks, connected by a programmable interconnect. FPGA logic blocks typically rely on Look-Up Tables (LUTs) or multiplexers to provide functionality, while CPLDs use AND-OR planes.
FPDs are used for many applications such as communications, data processing, industrial/instrumentation applications, etc. One application class of interest is compute-intensive applications such as signal and media processing. FPDs are becoming a popular means of implementing signal and media processing algorithms because they can effectively extract parallelism. Compute-intensive circuits can often be divided into two main parts; data path, and control circuitry. The latter can be implemented efficiently in traditional FPGAs that are LUT-based. However, the data path of computational applications, which is often significantly larger than the control part of the circuit, cannot be efficiently realized in a LUT-based structure as general purpose FPDs do not offer area-efficient realizations for compute-intensive applications.
It is therefore desirable to provide computational field programmable architecture ("CFPA") that is designed for compute-intensive applications, and a core logic circuit for use in such an architecture. It is also desirable to provide an architecture that is specifically intended to efficiently realize data path operations.
USPTO Backgrounds
USPTO Backgrounds