Generally, semiconductor devices include a plurality of circuits, which form an IC fabricated on a single silicon crystal substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires the formation of multi-level or multi-layered interconnection schemes, such as, dual damascene wiring structures based on copper or other conductive metals. Copper based interconnects are desirable due to their efficacy in providing high speed signal transmission between large numbers of transistors on a complex semiconductor chip.
Within the interconnect structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate. Presently, interconnect structures formed on an integrated circuit chip include at least about 2 to 10 wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thin wires”) and above these levels are about 2 to 6 wiring levels fabricated at a larger size (referred to as “fat wires”). Further enhancement of the signal speed and reduction of interaction of signals in adjacent metal lines (known as “cross-talk) is achieved in the 90 nm node product IC chips by surrounding the metal lines and vias in a low k dielectric having a dielectric constant (k) of about 3 to about 3.5. Future product nodes will use an ultra low k dielectric that has a dielectric constant between 1.8 and 3.
In various prior art structures, the thin wires (and optionally the fat wires) are formed in a low dielectric constant (k) material having a dielectric constant between about 3 and about 3.5. In other prior art structures, thin wires (and optionally the fat wires) are formed in an ultra low dielectric constant (ULK) material having a dielectric constant less than 3 and potentially as low as 1.8. Typically, the ULK materials have dielectric constants within a range from 1.8 to 3.
However, fabrication and reliability problems are associated with these prior art structures. For example, in order to perform chemical mechanical polish (CMP) planarization of the conductive metal, such as copper and a metal liner, a hard mask (HM) layer is used atop the ULK dielectric. The HM provides a layer with a low CMP rate, and prevents contamination of the ULK dielectric with components of the CMP slurry, including water (which reacts to form Si—OH groups in the ULK dielectric) and chemicals that interact with the ULK dielectric.
Two specific problems with porous ultra low k (ULK) dielectric films and integration using a HM layer are capacitance and HM retention; porous ULK dielectrics may be made using a sacrificial porogen phase in which the as deposited film contains 100% of the sacrificial phase, while the cured ULK has essentially all of this phase removed, and contains only a few percent or less of the sacrificial phase. The effective dielectric constant (keff) of the BEOL structure is higher than desired due to the use of the HM layer in the structure. HM retention means ensuring uniform retention of the HM in all structures, despite CMP rates that depend on metal pattern density and despite center-to-edge variability of the polishing rates across the wafer. This could lead to potential HM erosion and polishing into the ULK dielectric, thus directly exposing the ULK dielectric to the CMP slurry. The aforesaid erosion and polishing could adversely impact the overall chip performance by increasing the interline leakage (conductivity) and the capacitance (due to a higher film dielectric constant). Further, the topography (roughness) generated at a lower level could result in other CMP or lithography issues at the subsequent upper level(s) in an integrated multilevel build.
A third problem using porous ULK dielectrics is CMP damage to the HM layer, which may exist in three different forms. The first is added Si—OH groups which raise the k and increase the conductivity of the ULK dielectric. The second is broken bonds which increase conductivity. The third is contamination of the HM with metal ions or other chemicals that also increase conductivity.
A solution to the HM retention problem has been to integrate without a HM layer, which is common with low k dielectrics. Within this approach, the ULK dielectric is exposed to CMP, which can cause the dielectric to have severe electrical problems such as high conductivity and increased k. FIG. 1 shows J vs. E plots (i.e., current density vs. electric field) measured on a blanket ULK dielectric layer exposed to CMP Process A for 60 seconds. CMP Process A is chemical-mechanical in nature, but uses a very low down force (0.8 psi) suitable for integration with porous ultra low k dielectric films. The blanket ULK films of FIG. 1 were exposed to Process A, the details of which are: H2O2 based commercial liner slurry (Cabot6618), for 60 sec at 0.8 psi down force. Process A causes the dielectric constant to increase from 2.2 to 3.4 (measured at 150° C.). The J vs. E plot shown in FIG. 1 illustrates how Process A increases the conductivity of the porous ULK dielectric films that were deposited by plasma enhanced chemical vapor deposition. In FIG. 1, curves 1A and 1B (same SiCOH dielectric measured at 150° C.) and 2A and 2B (same SiCOH dielectric measured at 23° C.) are measured on a wafer exposed to process A and show high leakage current density (J). Curves 5 (SiCOH dielectric measured at 150° C.) and 6 (SiCOH dielectric measured at 23° C.) also present in FIG. 1 are measured from a control wafer with no CMP exposure and show low J.
As is known in the art, some of this electrical damage may be repaired using a thermal anneal process step. FIG. 2 illustrates a known prior art method to repair the CMP damage using a thermal (e.g., furnace) anneal. While the physisorbed water can be easily removed by low temperature annealing, the chemisorbed water (which forms Si—OH groups) would require extended high temperature annealing.
Specifically, FIG. 2 shows J vs. E plots (current density vs. electric field) measured on the same ULK dielectric (blanket) films used in FIG. 1. The blanket film was exposed to CMP Process B, the details of which are: a commercial liner slurry, with 6 psi down force, and 15 sec contact time. The CMP Process B exposure results in an increased leakage, line 21, and a dielectric constant of 2.6. Pieces of the wafer were annealed at temperatures of 350° C., 375° C. and 400° C. for 6 minutes. The J vs. E plot after CMP Process B is line 21, with highest leakage current. The J vs. E plot after CMP Process B and then annealing at 350° C. is line 22, after annealing at 375° C. is line 23, and after a 400° C. anneal is line 24. The film leakage is reduced in lines 22-24, but never reaches the original value for a control (no CMP exposure) film, which is illustrated by line 25.
A different fabrication and reliability problem associated with these prior art structures occurs during deposition of the copper barrier/etch stop layer deposited on the copper lines (referred herein as ‘the Cu cap’). A plasma pre-clean for the Cu cap (PPFCC) step is used in-situ immediately prior to depositing the Cu cap, in order to provide strong adhesion of the Cu cap to the Cu lines and hence to provide resistance to a common failure mode: electromigration. This plasma pre-clean enhances cap adhesion to copper, but induces damage to the HM or the ULK dielectric. This plasma damage may be in at least 3 forms. The first is nitrogen implantation (when NH3 or N2/NH3 plasmas are used) which raises the dielectric constant (capacitance) between the metal lines. The second is broken bonds which increase the conductivity between the metal lines. The third is removal of carbon from the HM or the ULK, which raises k and increases conductivity.
FIG. 3 shows an increase in leakage current for a HM film having a SiCOH composition after the HM film was exposed to the NH3 PPFCC. Specifically, FIG. 3 shows J vs. E plots (current density vs. electric field) measured on the same ULK dielectric (blanket) films used in FIGS. 1 and 2. Line 31 is the J vs. E plot from the control wafer (no plasma exposure) and lines 32 are measured after exposure to the plasma pre-clean (PPFCC).
Use of ultraviolet (UV) light to modify the bulk of a SiCOH dielectric film is well known. As is known in the art, UV radiation may be used to penetrate into a dielectric of the SiCOH composition to strengthen the bulk of the dielectric to raise the elastic modulus. For example, U.S. Pat. No. 6,566,278 to Harvey teaches the use of UV light to make the bulk of a SiCOH film denser. Specifically, the '278 patent teaches the conversion of Si—OH groups in the bulk of the film into Si—O—Si linkages. The resulting film disclosed in the '278 patent has “bonds characteristic of an ordered silicon oxide lattice” after UV irradiation. To accomplish this, the UV radiation breaks Si—O and O—H bonds and causes formation of more Si(O)3 and Si(O)4 structures (with 3 or 4 bonds to Si, respectively) and these render the material stronger and with a higher elastic modulus.
FIG. 4 shows the absorbance vs. wavelength spectrum of two prior art ULK SiCOH dielectrics. Curve 42 is measured from the ULK dielectric film used in FIGS. 1, 2, 3. Curve 41 is measured from a different ULK dielectric film prepared by a similar process. It is seen that absorbance is higher the shorter the wavelength.
In view of the above, there is a need for providing methods that ensure the successful integration of BEOL structures without a HM/CMP stop layer being present in the structure.
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