1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device which can be used in a data line driver of a plane type display apparatus such as a liquid crystal display (LCD) apparatus.
2. Description of the Related Art
Generally, in a plane type display apparatus including a panel having data lines (or signal lines), scan lines (or gate lines) and cells each located at one intersection between the data lines and the scan lines, a plurality of data line drivers are provided along a horizontal direction to drive the data lines and a plurality of scan line drivers are provided along a vertical direction to drive the scan lines. Each of the data line drivers is constructed by a horizontal shift register and a data register in order to latch 18-bit pixel signals each formed by red data (R) (6 bits), green data (G) (6 bits), and blue data (B) (6 bits). For example, the horizontal shift register is constructed by 128-cascaded flip-flops for shifting a horizontal start signal in synchronization with a horizontal clock signal to sequentially generate 128 shift pulse signals for latching 128 pixel signals in synchronization with the 128 shift pulse signals. This will be explained later in detail.
In the above-described data line driver, as the quality of the panel has become highly-defined and the size of the panel has been increased, a clock signal line for carrying the horizontal clock signal and pixel lines for carrying the pixel signal have been lengthened. Therefore, buffers for generating the horizontal clock signal and the pixel signal need to have large driving ability. In this case, since the speed of the horizontal clock signal and the pixel signal have also been increased, the average values and peak values of the circuit currents of the buffers have been increased, so that the power consumption has been increased and the electromagnetic interference (EMI) noise has been increased.
In a first prior art semiconductor integrated circuit device including a plurality of shift registers and a plurality of data registers (see: JP-2001-42813A), clock signal lines for the shift registers are divided into two internal clock signal line groups which are time-divisionally controlled by a clock control circuit including counters, and pixel lines for the data registers are divided into two internal pixel line groups which are time-divisionally controlled by a data control circuit including AND circuits. Thus, the capacitance of the clock signal lines and the capacitance of the pixel lines are substantially decreased to decrease the power consumption.
In a second prior art semiconductor integrated circuit device including a shift register and a data register (sampling register) (see: JP-2002-014657A), clock signal lines for the shift register and pixel lines for the data register are divided into two internal clock signal line groups and two internal pixel line groups, respectively, which are time-divisionally controlled by a switch control circuit. Thus, the capacitance of the clock signal lines and the capacitance of the pixel lines are substantially decreased to decrease the power consumption.
In a third prior art semiconductor integrated circuit device including a shift register and a data register (see; JP-2000-250495A), a pixel line for the data register is divided into two internal pixel lines which are time-divisionally controlled by a control signal generating circuit in synchronization with the operation of the shift register which are also divided into two portions. Thus, the capacitance of the pixel lines is substantially decreased to decrease the power consumption.
USPTO Backgrounds
USPTO Backgrounds