1. Field
The present innovations relate generally to data bus inversion, and, more specifically, to systems and method involving data bus inversion associated with memory configuration and/or operation.
2. Description of Related Information
Data bus inversion (DBI) is an interface scheme capable of reducing simultaneous switching noise, IO AC current and IO DC current drain and associated problems. According to DBI schemes, for example, when half or more I/O pins are low (i.e. 0) in the binary bus, a DBI pin named DBI# for signaling the data bus inversion is set to low (i.e. 0) and the data bus is inverted in the DBI bus. DBI# set to zero indicates an inverted data bus, where half or more bits in the DBI bus are high. Inversion may be performed on the data bits by DBI logic circuitry based on the DBI pin. Since no more than half of the bits can switch under the DBI scheme, then no more than half of the I/O lines consume AC power. The output in the DBI scheme is normally set to be terminated to high level through resistive connection to VDD supply. I/O DC current due to output termination is also reduced because no more than half of the outputs can be at low level.
FIG. 1 illustrates current switching of an internal M bit data bus. The maximum current switching is performed when all M bits switch from low to high in one cycle and from high to low the next cycle. When all M bits switch in the same direction, IDD and ground current are at a maximum level and therefore cause a current spike, which in turn causes VDD to drop and causes ground bounce through the power bus resistors R1 and R2. This, in turn, reduces the switching speed. So, although an external data bus adopts a DBI scheme to reduce DC and AC current and SSO (Simultaneously Switching Output) noise, the conventional design converts the external data bus to the normal data bus that is still noisy, e.g., with all bits switching.
An example of a conventional memory system incorporating DBI logic is provided in FIG. 2. Here, both DBI formatter circuitry 245 and DBI converter circuitry 241 are provided at each of the inputs and outputs of the memory core 244 of the memory chip 210. Likewise, the corresponding outputs and inputs of the memory controller 220 includes both the DBI formatter circuitry 245 and DBI converter circuitry 241. In this manner, DBI processing is performed between logic 221 and memory 244. The data stored in memory 244 does not include any DBI information. Conventionally, DBI converter circuitry 241 or DBI formatter circuitry 245 is provided in the memory controller 220 and paired with a corresponding DBI formatter circuitry 245 or DBI converter circuitry 241 within the memory chip 210.
Other existing DBI logic circuitry is provided in FIGS. 3A and 3B which illustrate DBI formatter logic and DBI converter logic, respectively. The DBI formatter logic of FIG. 3A receives inputs of nine data bits provided from a memory core and a DBI mode enabling signal DBIe#, and outputs the data bits with a one bit DBI pin DBI# indicating data inversion or non-inversion based on a quantity of the low data bits. DBIe# signal can be supplied from the external pin or from an internal mode register. The DBI converter logic of FIG. 3B receives inputs of nine data bits with the DBI pin DBI# and DBIe#, and outputs the data bits being inverted, or not, as a function of DBI# and DBIe#.
FIG. 4A illustrates one such conventional circuit design 440 implementing DBI logic. During a write cycle, for example, nine bit data DQ and one bit DBI pin DBI# is received and is processed through DBI converter logic 441 and outputted as a signal Din that is inverted if the DBI# is set to low. The data bits are then processed through Section Data 442 and outputted as section data sd, input to column pass gate 443, and then written into the memory core 444. During a read cycle, the stored M bit core data is processed through the column pass gate 443 and outputted as ssl, sensed in the Section circuitry 442 and outputted on the sense line SL. The DBI formatter logic 445 then outputs a DBI pin DBI# and the M bit data DQ. Further, FIG. 4B is a diagram illustrating exemplary circuit components of the memory core 444, column pass gate 443 and section circuitry 442.
Such conventional systems and methods, however, possess certain drawbacks and/or inefficiencies in processing the DBI bit and associated data into and out of the memory cell. These deficiencies lead to various issues, such as unnecessary power consumption, and/or as undesired current fluctuations and noise, among other drawbacks. As such, there is a need for systems and methods that may provide advantageous reduction of simultaneous switching noise, reduction of IDD current and/or IDD current spike issues, and/or removal of delay(s) due to DBI conversion, among other innovations.
USPTO Backgrounds
USPTO Backgrounds