Metal interconnect structures are common structures in the semiconductor devices. A typical metal interconnect structure includes metal line patterns and conductive vias under the metal line patterns. The metal line patterns are usually formed by forming trenches via etching processes; and followed by filling the trenches with a metal material. Recently, with the increasing of the device density, the line width of the metal interconnect structures has become smaller and smaller. During a photolithography process, because of the existence of certain phenomena, such as diffraction, etc., the resolution of an exposure apparatus has an optical limitation. Such a limitation may cause an Optical Proximity Effect (OPE) during a pattern transformation process of the reticle which has patterns corresponding to the metal line patterns. Such an OPE causes an error between the patterns on the reticle and the patterns transferred to a photoresist. Further, this error causes the metal line patterns not to cover the contact vias completely. Thus, the electrical contact between the metal line patterns and the contact vias may be unreliable. Further, the patterned photoresist are significantly long and thin, and a peeling effect may occur due to the error. Thus, adjacent metal line patterns may be connected; and the performance of the metal interconnect structures may not be reliable.
The above-mentioned error is often overcome by an optical proximity correction (OPC) method. One typical OPC method is to change the boundary of the circuit patterns to cause the circuit patterns to have certain pre-deformations. The pre-deformation may cause the circuit patterns to be more similar to the target patterns obtained after developing and exposing processes. Another typical OPC method is to dispose Scattering Bars (SBs) between adjacent metal line patterns. The SBs may be used to prevent the incomplete cover issue of the conductive vias; and prevent the photoresist from peeling.
However, with the further decreasing of the CD of the integrated circuits (ICs), the device density of ICs has been further increased. Thus, the effect of changing boundary for OPC is limited. Further, the distance between adjacent metal line patterns has become smaller and smaller. Thus, it may be inappropriate to form SBs between adjacent metal line patterns. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.
USPTO Backgrounds
USPTO Backgrounds