1. Field of Invention
Embodiments of the present invention relate generally to connecting elements and semiconductor devices having the same. More particularly, embodiments of the present invention relate to a rotation joint that can prevent mismatch due to thermal expansion and a semiconductor device (e.g., a package on package (POP), a flip-chip package, a wafer-level package (WLP), and a memory module) having the same.
2. Description of the Related Art
In general, it is desirable that semiconductor devices operate at room temperature. In many cases, however, semiconductor devices incorporated within, for example, spacecraft and military equipment, are used under severe temperature conditions and need to operate properly in the presence of sudden temperature variations.
Meanwhile, semiconductor devices (e.g., semiconductor packages, memory modules or the like) may suffer from problems due to a difference in the coefficient of thermal expansion (CTE) among internal elements, such as a semiconductor chip, a solder ball (or a bump), and a printed circuit board (PCB). A typical problem is that frequent sudden temperature variations can lead to deterioration of solder joint reliability (SJR) in semiconductor devices. Reliability problems such as SJR may be easily confirmed via a temperature cycling test. The temperature cycling test includes inspecting the state and functions of a semiconductor device while maintaining the semiconductor device at temperatures between −55° C. and 125° C. for 5 or 10 minutes for each process several tens or hundred of times.
FIG. 1 is a cross sectional view of a semiconductor device having a conventional solder ball or a bump.
Referring to FIG. 1, in a semiconductor device 20, such as a flip-chip or a memory module, a semiconductor chip 40 is electrically connected to a PCB 30 using bumps or solder balls 10. However, the semiconductor chip 40, the bumps 10, and the PCB 30 of the semiconductor device 20 have different coefficients of thermal expansion. Thus, when frequent and sudden variations in the temperature of the environment within which the semiconductor device 20 occurs, stress can be concentrated on the semiconductor chip 40 as indicated by the arrows. Moreover, the stress usually becomes worse as the magnitude of temperature variation increases.
FIG. 2 is a cross sectional view illustrating defects generated within semiconductor device shown in FIG. 1 due to CTE mismatch.
Referring to FIG. 2, a solder ball 10′ connects the semiconductor chip 40 and the PCB 30. When stress is repetitively applied to the solder ball 10′ due to a CTE mismatch between the semiconductor chip 40 and the PCB 30, the mechanical endurance of the solder ball 10′ deteriorates and cracks 12 and 14 are generated along a generally horizontal direction. In FIG. 2, a bond pad 46 is formed on the surface of the semiconductor chip 40, while a solder ball pad 33 is formed on the surface of the PCB 30.
As described above, defects such as the cracks 12 and 14 are generated in the solder ball 10′ (or the bump 10), thus lowering the reliability of the semiconductor device 20. Therefore, it would be desirable to prevent the occurrence of such defects that lead to generation of leakage current.
USPTO Backgrounds
USPTO Backgrounds