This application claims the priority benefit of Taiwan application serial no. 89100398, filed Jan. 12, 2000.
1. Field of the Invention
The invention relates to a structure of a printed circuit board or a ball grid array (BGA) board for greatly reducing the mutual inductance between two adjacent transmission lines on a substrate.
2. Description of the Related Art
Currently, devices on the main board of a personal computer at least includes a central processing unit (CPU). If the main board has a multi-processing function, it can include more than one CPU. In addition to CPU, the main board has an accelerated graphics port (AGP) connected to a display card, memory slots for the insertion of modular memories and peripheral component interconnects (PCI) for installation of various interface cards. Furthermore, anther control circuit is mostly designed in a chip set which must be connected to the CPU, memories, AGP slots and PCI slots. The arrangement of the pins of the chip set with respect to the positions of other devices must be taken into account. Especially, data processed by the CPU all are 32-bit or more than 32-bit data. Therefore, there are several hundreds of transmission lines among the chip set, CPU, memories, AGP slots and PCI slots. On the other hand, since the clock frequency of the CPU is as high as several hundred MHz, it should be careful during the circuit layout of the main board to ensure the main board stability.
A part of the prior art for a ball grid array (BGA) board or a printed circuit board layout is shown in FIG. 1A. A chip set, such as Intel-made chip set 440BX, is mounted on the above conventional ball array board or the printed circuit board. Generally, the chip set has a square flat package with a thickness of several millimeters. Moreover, there are two square planes on both sides of the chip set, wherein one has electrical balls and the other is printed with a text label. In FIG. 1A, transmission lines 11, 12, 13 are parallel to one another on a conventional printed circuit board. The mutual inductance of any two adjacent transmission lines has a logarithmic relation with pitch. Therefore, even though the distance between two adjacent transmission lines is increased, the corresponding mutual inductance can not be effectively reduced. Furthermore, since the clock frequency of a currently used CPU is over several hundred MHz, the mutual inductance of the transmission lines 2 and 3 and transmission lines 2 and 1 becomes more serious. In turn, the mutual inductance then causes a cross-talk effect, resulting in a data error.
AS shown in FIG. 1A, reference symbols L1, Ls, L2 represent the self-inductance of transmission line 11, 12, 13, respectively, and reference symbol Lm represents the mutual inductance between the transmission line 12 and 13 and between transmission lines 12 and 11. Each transmission line has a width of 80 xcexcm. The pitchs between the transmission lines 11 and 12 and between the transmission lines 12 and 13 is 200 xcexcm and 70 xcexcm, respectively. The lengths of the transmission lines 11, 13 and the transmission lines 12 are 10000 xcexcm, 10000 xcexcm and 3000 xcexcm, respectively. The transmission line 12 is used for a high-frequency signal line, such as a clock signal. The reason that the length of line 12 equal to 3000 xcexcm is based on the requirement of PC design. On end of line 12 is bond finger; the other end is via which connects with ball. The same to line 11 and line 13. The self-inductance Ls of the transmission lines 11, 12, 13 and the mutual inductance Lm between the transmission lines 12 and 11 and between the transmission lines 12 and 13 obtained by using Ansoft-Spicelink simulation software at f=100 MHZ are shown in Table 1.
As can be seen from Table 1, since the pitch between the transmission lines 12 and 13 is only 70 xcexcm, the mutual inductance Lm2, 0.788 nH, between the transmission lines 12 and 13 is larger than the mutual inductance Lm1, 0.539 nH, between transmission lines 11 and 13. Generally, cross talk is related to the ratio of self-inductance and mutual inductance. From Table 1, the ratio of mutual inductance and self-inductance Lm1/Ls and Lm2/Ls is 0.357 and 0.522, respectively.
Referring now to FIG. 1B, the pitches between the transmission lines 11 and 12 and between the transmission lines 12 and 13 is adjusted to 145 xcexcm. The width and length of each line are not changed. The self-inductance Ls of the transmission lines 11, 12, 13 and the mutual inductance Lm between the transmission lines 12 and 11 and between the transmission line 12 and 13 obtained by Ansoft-Spicelink simulation software are shown in Table 2.
As can be seen from Table 2, since the pitches between the transmission line 12 and 11 and between the transmission line 12 and 13 all are 145 xcexcm, the mutual induction Lm1 of the transmission line 11 is the same to the mutual inductance Lm2, that is, Lm1=Lm2=0.655 nH, wherein Lm1/Ls=Lm2/Ls=0.414.
Next, referring to FIG. 1C, the pitch between the transmission lines 11 and 12 is 70 xcexcm and the pitch between the transmission lines 12 and 13 is 220 xcexcm. The width and the length of each line are kept. The self-inductance Ls of the transmission lines 11, 12, 13 and the mutual inductance Lm between the transmission lines 12 and 11 and between the transmission line 12 and 13 obtained by Ansoft-Spicelink simulation software are shown in Table 3.
From Table 3, as the pitch between the transmission lines 12 and 13 is increased to 220 xcexcm, the mutual inductance Lm2 between transmission lines 12 and 13 is reduced to 0.539 nH. Furthermore, Lm1/Ls=0.522 and Lm2/Ls=0.357. As described above, after the pitch between the transmission lines 12 and 13 is increased from 70 xcexcm to 220 xcexcm, Lm2/Ls is just slightly reduced from 0.522 to 0.357. Even though the pitch between two adjacent transmission lines is 3 times larger, the mutual inductance Lm2 can not be efficiently reduced to eliminate cross-talk effect.
In summary, the layout of a conventional ball grid array board or printed circuit board has the following disadvantages: the mutual inductance between two adjacent transmission lines can not be effectively reduced. In particular, when the clock frequency of a CPU is as high as several hundred MHz, the mutual inductance between two adjacent transmission lines will become much more serious.
In view of the above, the invention is to provide a method and a structure for reducing the mutual inductance between two adjacent transmission lines. Even though the pitch between any two adjacent transmission lines is the same, the mutual inductance between them can be almost eliminated.
A structure for reducing the mutual inductance between two adjacent transmission lines on a substrate according to the invention includes an inverse U-shaped transmission line. One terminal is bond finger for signal input; the other is via for signal output. The length of these two sides of the inverse U-shaped line is different. The side adjacent to sensitive trace is shorter. Furthermore, corners of the inverse U-shaped transmission line are mitered to prevent antenna effect. With such structure stated above, mutual inductance and cross-talk can be effectively reduced.
A method for reducing the mutual inductance between two adjacent transmission lines on a substrate is as follows: (1) designing an inverse U-shaped transmission line which has a first side, a second side and a base; (2) keeping the positions of bond finger and via; and (3) optimizing the lengths of the first side and the second side, the base length, and the pitch between this line and adjacent sensitive line to get minimum mutual inductance by simulation.
USPTO Backgrounds
USPTO Backgrounds