1. Field of the Invention
The present invention relates to a method for testing standby current of a semiconductor package, and more particularly, to a method of automatically setting a standby current limit for a package testing process based on values measured during an electrical die sort (EDS) of a wafer.
2. Description of the Related Art
To realize a particular function, a circuit is designed and a plurality of parameters are set to measure the characteristics of the circuit. The circuit is manifested as a semiconductor chip fabricated on a wafer. To check whether the semiconductor chip was fabricated as it was originally designed, the predetermined parameters are measured while the chips are on the wafer. Thereafter, the semiconductor chip is packaged. To determine whether the characteristics of the semiconductor chip have been changed during the packaging, the parameters are measured again in a package testing process.
Among those parameters, standby current is a parameter for checking the amount of leakage current dissipated in a standby mode not an operation mode. Standby current is usually leakage current of a transistor, e.g., a memory cell transistor of a semiconductor memory device. The main cause of an increase in the leakage current of a memory cell transistor is a decrease in a gate poly critical dimension or an active critical dimension. In addition, when a threshold voltage decreases according to the thickness of a gate insulating layer and cleaning conditions for a memory cell transistor, the leakage current of the memory cell transistor increases.
In this situation, when high-voltage stress is applied to a semiconductor package in a package testing process, in order to skip a burn-in process, the median (central) and statistical spread or dispersion (distribution) of the standby current may shift because of a vulnerable process management standard. Besides, the standby current may change due to various factors in wafer fabrication processes. Particularly, in a low-power semiconductor apparatus, the range of fluctuation in medians and statistical dispersions of the standby currents increase during wafer fabrication and package testing.
The change in the median value and distribution of standby current does not necessarily cause faults during fabrication or problems in product quality. However, since the test limit set for the standby current at an initial characteristic evaluation is fixed, yield loss occurs during the package testing process.
To prevent yield loss from occurring during package testing attributable to the change in the characteristics of standby current, a conventional method includes measuring the standby current of each semiconductor chip formed on a wafer when yield loss occurs or inspecting the result of wafer fabrication processes and the result of an EDS, statistically estimating the level of standby current, manually adjusting the test limit for the standby current in a package testing process, and repeating the above operations.
As described above, when standby-current yield loss occurs during package testing, a standby current limit must be adjusted manually. The manual adjustment takes a large amount of time and requires a lot of labor.
USPTO Backgrounds
USPTO Backgrounds