1. Field of the Invention
The present invention relates to a semiconductor memory device, which is capable of storing binary or more data in one memory cell.
2. Description of the Related Art
There has been proposed a NAND flash memory using an EEPROM, that is, a non-volatile semiconductor memory device capable of storing multi-valued data in one memory cell (e.g., see JPN. PAT. APPLN. KOKAI Publication No. 2000-195280).
The NAND flash memory is configured in a manner that all or half of several memory cells arrayed in a row direction are each connected to the corresponding latch circuit via a bit line. The latch circuit holds data in data write and read. The foregoing all or half of cells arrayed in the row direction collectively write and read data (e.g., see JPN. PAT. APPLN. KOKAI Publication No. 2003-196988).
Quick Pass Write (QPW) has been proposed as a method of preventing a data write time with respect to memory cell from increasing and narrowing a threshold voltage distribution width after data write. According to the QPW, a bit line is charged while a potential (voltage) of word line is set to a level lower than a normal verify level. Thereafter, a select gate is set to a high level, and then, the pre-charged bit line is discharged. In non-write cell and write continuing cell, which are far from a write threshold voltage, the bit line potential becomes a low level because current is carried. On the other hand, in a write continuing cell, which is close to the write threshold voltage and a write completed cell, the bit line is intactly kept high. At that time, the bit line potential is detected (first time verify).
Then, the word line potential is set to a normal word line level. By doing so, in the write continuing cell, the bit line becomes low. Therefore, in the write completed cell only, the bit line potential becomes high. At that time, the bit line potential is detected (second time verify).
According to the result of the second time verify, a cell becoming high is a write completed cell. The write completed cell is regarded as a non-write cell in the next program loop, and therefore, it sets the bit line to a power supply voltage Vdd, and does not carry out a write operation. On the other hand, according to the result of the second time verify, a cell becoming low is a write incomplete cell. The write incomplete cell carries out a write operation in the next program loop. However, according to the result of the first time verify, a cell becoming high is a cell, which is close to the threshold voltage (normal verify level). For this reason, the cell sets the bit line to an intermediate potential (e.g., 0.75V), and carries out a write operation in a state of reducing a write speed. On the other hand, according to the result of the first time verify, a cell becoming low sets the bit line to a ground voltage Vss, and carries out a write operation.
In this manner, program and verify are repeated until all write cells pass the second time verify. Therefore, the write speed of the cells closing to a normal verify potential becomes late; as a result, threshold voltage distribution is narrowed.
However, the first time verify operation is made in a state that the word line potential is set to a level lower than a normal verify level. Thereafter, the second time verify operation must be made in a state that the word line potential is set as the normal write verify level. The word line has a large capacity; for this reason, time is taken to step up the word line potential. As a result, there is a problem that the verify time increases. Therefore, it is desired to provide a semiconductor memory device capable of preventing the verify time from increasing.
USPTO Backgrounds
USPTO Backgrounds