For the purpose of utilizing the big data, attention to the high-speed analysis technology of big data is increasing. An IT platform capable of accessing large amounts of data at high speeds is needed to realize this high-speed analysis technology.
To meet this requirement, for example, Patent Literature 1 discloses a parallel processor having multiple processors, a distributed shared memory (cache memory) provided for each processor, and an information transfer line therebetween. Specifically, each processor is able to store data, which is being held in a distributed shared memory of another processor, in its own distributed shared memory as needed. That is, each processor disclosed in Patent Literature 1 is able to share data with another processor using the distributed shared memory. Thus, the entire parallel processor is able to access large amounts of data at high speeds without increasing the capacity of the distributed shared memory.
However, in a case where the capacity of the distributed shared memory is large enough to be able to store all the data targeted by an application pursuant to processing large amounts of data, the distributed shared memory, although fast, becomes very expensive. For this reason, it is conceivable that an I/O (Input/Output) node, which comprises a nonvolatile storage device and a cache memory for temporarily storing data to be input/output to/from this storage device, be coupled to a processor (computation node) comprising a cache memory, frequently used data be stored in the cache area of the processor, and infrequently used data be stored in the I/O node storage device.
For example, Patent Literature 2 discloses a technology for hierarchizing a storage area, which includes the computation node cache memory, the I/O node cache memory, and the I/O node storage device, linking this hierarchized storage area to the processing of an application, and arranging data required by the application in a storage area belonging to a prescribed tier.
USPTO Backgrounds
USPTO Backgrounds