1. Field of the Invention
The present invention generally relates to transistors and more particularly to an improved N-type lateral double diffusion metal oxide semiconductor that has a shallow trench isolation region between the gate and the drain.
2. Description of the Related Art
Power semiconductor devices are currently being used in many applications. Such power devices include high-voltage integrated circuits, which typically include one or more high-voltage transistors, often on the same chip as low-voltage circuitry. A commonly used high-voltage component for these circuits is the lateral double diffused MOS transistor (LDMOS). LDMOS structures used in high-voltage integrated circuits may generally be fabricated using some of the same techniques used to fabricate the low voltage circuitry or logic circuitry. In general, these existing LDMOS structures are fabricated in a thick epitaxial layer of opposite conductivity type to the substrate or they use a thin epitaxial layer and apply the RESURF (reduced surface field) principle (e.g., see U.S. Pat. No. 6,242,787, that is incorporated herein by reference, for a complete description of RESURF) to equally distribute the applied drain voltage laterally across the silicon surface in the drift region of the device.
High-power applications call for the use of such lateral double diffused MOS transistors primarily because they possess lower “on” resistance (“Rdson”), faster switching speed, and lower gate drive power dissipation than their bi-polar counterparts. These devices have heretofore also been strongly associated with bi-polar based process flows when integrated into a Bi-CMOS (bipolar complementary metal oxide semiconductor) environment.
USPTO Backgrounds
USPTO Backgrounds