1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having electrically rewritable nonvolatile memory cells, and particularly relates to a multi-valued nonvolatile semiconductor memory device which is capable of storing information corresponding to a plurality of bits per a memory cells.
2. Background Art
EPROMs (Erasable Programmable Read Only Memory) or EEPROMs (Electrically Erasable PROM) have been used as nonvolatile semiconductor memory devices capable of being electrically written into memory cells in the past. However, the recent mainstream tends toward flash memories because of the capability of collective erasure of a erasure block defined as block units in a memory cell array. In a flash memory device, a memory cell comprises a source, a drain, and a floating gate, and a control gate laminated on each other through insulating films. Writing and erasing operations are executed by injection and extraction of electrons for the floating gate using the hot electron effect or the tunneling effect and the writing operation can also be executed utilizing a phenomenon that the threshold value of the memory cell changes with or without electron injection.
Now, there are a few types of memory cells in a flash memory device because of the thickness variation or the inclusion of minute defects in oxide films due to dispersion of manufacturing process. One type of the memory cell is that necessary to write repeatedly because writing is difficult, and another one is, in contrast to the above type, that necessary to complete writing in a short time so as to prevent overwriting. In other words, when writing is executed to all memory cells by an identical condition, the threshold values for those memory cells become diverse so that margins for the operating voltage or the access time become not adjustable.
In order to cope with the above circumstance, the writing operation to the memory cells in the flash memory devices are executed not by one time but by a plurality of times while adjusting writing pulse widths or writing voltages, and always determining a degree of writing until the desired level of the threshold value is attained. This is because, if too many electrons are injected in the floating gate, then, except by executing an erasing operation, it is difficult to restore the gate and that it is possible to erase the flash memory cell only when a collective erasure of a total memory cells or a block unit of the memory cells is carried out, in contrast to the EEPROM, in which the memory cells can be erased individually. The above-mentioned repetitive writing operations allows overcoming the diverse threshold values of the memory cells and it is necessary to recognize the diverse distribution of the threshold values. In fact, the threshold values of all memory cells in a memory cell array are distributed as shown in FIG. 14, described later.
In order to reduce the chip size while increasing the memory volume of the memory cells, the memory cells are now changing to store multi-valued data are more than the binary data. For that purpose, the memory cells that can store the multi-valued data is realized by setting the multilevel threshold values or threshold voltages (multilevel cells) in accordance with the data by controlling the amount of electron injected into the floating gate. When each memory cell is made into a multilevel cell, for example, a four valued cell, each memory can store the data corresponding to two bits. When four valued cells are used, the number of memory cells for a flash memory, which originally includes 512 million binary cells can be reduced to 256 million binary cells, which results in reducing the chip area for the memory cells.
Japanese Unexamined Patent Application, First Publication No. Hei 8-315586 discloses a flash memory, the schematic structure of which is shown in FIG. 12. In the flash memory 100 shown in FIG. 12, a plurality of memory cells 101 are arranged in a matrix form. A plurality of word lines extending in the row direction of the cell matrix are connected with a plurality of control gates corresponding to respective word lines. A plurality of bit lines extending in the column direction of the cell matrix are connected to drains of a plurality of memory cells corresponding to respective word lines. The sources of respective memory cells are connected with a common source line (not shown). The row decoder 102 selects one of word lines according to an address signal externally input from the flash memory through an I/O buffer 103. The I/O buffer 103 is a circuit which forms an interface between the flash memory 100 and the outside.
A combination sense circuit and writing data latch 104 comprises sense amplifiers (not shown) and writing amplifiers (not shown) so as to correspond to each bit line, and one end of the writing data latch 104 is connected to the bit line of the memory cell array 101, and the other end is connected to the I/O buffer 103 through a column gate 105. A column decoder 106 controls a column switch constituting the column gate 105 according to the above-mentioned address signal for selecting a bit line designated by the address signal and corresponding to the combination sense circuit and writing data latch 104. A boosting circuit 107 generates various voltages (for example, high voltages necessary for writing and erasing the memory cell array 101) for supplying these voltages to the flash memory 100. A control circuit 108 sends various control signals to various portions of the flash memory 100 for controlling respective portions and making them execute writing and erasing operations.
FIG. 13 shows a detailed structure of a combination sense circuit and writing data latch 104 provided corresponding to one bit line among the sense circuits and writing data latches 104 shown in FIG. 12. In this conventional example, the flash memory is assumed to be constituted by memory cells which store two bits data (four level data). In this conventional example, when 2-bit data is written in the memory cell, the threshold value corresponding to the data xe2x80x9c11xe2x80x9d is the lowest, and the threshold values increases in the order of xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d, and xe2x80x9c00xe2x80x9d. It is assumed that 2-bit data from xe2x80x9c11xe2x80x9d to xe2x80x9c00xe2x80x9d (in FIG. 14, MSB is the higher rank bit, and LSB is the lower rank bit) are in the states from the xe2x80x9cstate 1xe2x80x9d to the xe2x80x9cstate 4xe2x80x9d, and that differences of the threshold values separating adjacent threshold values are VREF1 to VREF3. Here, xe2x80x9cthe state 1xe2x80x9d is the state after erasure.
In FIG. 13, both reference symbols MSEN and LSEN denote sense amplifiers and both amplifiers are provided with respective latches 110 and 111 constituted by two inverters connected like a loop. The latch 110 stores the higher rank bit and the latch 111 stores the lower rank bit among two bits data. FIG. 15 is a diagram for explaining the writing operation executed by the circuit shown in FIG. 13. FIG. 15 shows a time serial change of data stored in respective latches 110 and 111 for each of the 2-bit data for writing in the memory cells.
Here, the conventional writing operation into the memory cell will be described with reference to FIGS. 13 to 18. The details of the circuit shown in FIG. 13 will not be described, but the operation as a whole will be explained. At first, the threshold value of the memory cell is changed to the value corresponding to the xe2x80x9cstate 1xe2x80x9d. Since the writing data are divided into respective two bits (each xe2x80x9cwrite dataxe2x80x9d in FIG. 15) in the course of delivering the writing data into the column gate 105 externally from the flash memory 100 (FIG. 12) through the I/O buffer 103, the latches 110 and 111 (FIG. 13) uptake writing data respectively through the data lines IO and IOB.
As shown below, the writing operation is performed by three stages, and the final writing state is attained by the writing operations executing respective stages shown in FIG. 16xe2x86x92FIG. 17xe2x86x92FIG. 18. In the first stage, based on the upper rank bit uptaken in the latch 110, writing into the memory cell is executed until reaching the VREF 2 corresponding to the xe2x80x9cstate 3xe2x80x9d wherein the upper rank bit of the writing data is xe2x80x9c0xe2x80x9d (xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d) (xe2x80x9cwrite 1xe2x80x9d in FIG. 15). As described above, since the threshold values for memory cells disperse even if an identical writing condition is applied to each memory cell, the memory cells subjected to writing do not necessarily reached the threshold value of VREF2. Thus, it becomes necessary to verify (hereinafter, called verification) whether or not the threshold values of respective cells reach VREF2.
Since it is possible to verify whether or not the threshold value of each cell reaches VREF2 by applying the potential of VREF2 to the control gate of each memory cell, the writing operation to the memory cells is considered to be completed by rewriting the higher rank bit into xe2x80x9c1xe2x80x9d for the memory cells having threshold values exceeding VREF2. In contrast, the higher rank bits for the memory cells having threshold values less than VREF2 are left unchanged at xe2x80x9c0xe2x80x9d, and even if there is a memory cell in which the threshold value is less than VREF2, and even if there is a memory cell in which the higher rank bit is still xe2x80x9c0xe2x80x9d, further writing and verification are executed. By repeating the above series of operations, practical writing goes forward for memory cells to be written. Finally, threshold values of every memory cell with writing data of xe2x80x9c01xe2x80x9d or xe2x80x9c00xe2x80x9d increases up to VREF 2, and the higher rank bits for every memory cells are turned into xe2x80x9c1xe2x80x9d (Verify 1 in FIG. 15 and FIG. 16).
Next, the following processing is executed prior to the second stage writing operation. First, the lower rank bits are transferred to the higher rank bits, so that the higher rank bits that change when the writing data is xe2x80x9c10xe2x80x9d or xe2x80x9c11xe2x80x9d. Then, reading is executed by applying VREF2 to the control gates of the memory cells, and if the threshold value of a memory cell is higher than VREF2, xe2x80x9c1xe2x80x9d is added to the lower rank bit. As a result, the lower rank bits change when the writing data is xe2x80x9c00xe2x80x9d. Similar to the writing operation in the first stage, writing is executed until the threshold value reaches VREF1 for the memory cell with the writing data of xe2x80x9c10xe2x80x9d (Write 2 in FIG. 15) and also a verification operation is executed for memory cells having threshold values of more than VREF1 for setting to xe2x80x9c1xe2x80x9d. When threshold values of every memory cells exceed the value of VREF1, the second stage writing is completed (Verify 2 in FIG. 15 and FIG. 17).
Next, the following processing is executed prior to the third stage writing operation. First, similar to the second stage, the memory cell is read in order to set the low rank bits to xe2x80x9c0xe2x80x9d when the threshold value of the memory cell is less than VREF2. As a result, when the written data are xe2x80x9c0xe2x80x9d and xe2x80x9c01xe2x80x9d, the lower rank bit changes. By successively setting the lower rank bit to xe2x80x9c1xe2x80x9d when the higher rank bit is xe2x80x9c1xe2x80x9d, the lower rank bit changes when the written data in the lower rank bit is set to xe2x80x9c1xe2x80x9d. Then, similar to the writing operation at the first and second stages, the writing operation is executed according to the stored data for memory cells having the writing data of xe2x80x9c00xe2x80x9d up to the threshold value of VREF3 (Write 3 in FIG. 15), which follows the verification operation for setting xe2x80x9c1xe2x80x9d for every bit having higher threshold values than VREF3. The writing and verification operations are repeated until threshold values of every memory cell exceed VREF3 (Verify 3 in FIG. 15).
As shown above, the conventional device is constructed such that the first stage writing operation is first executed using the higher rank bits, and the second and third stage writing operations determine the latched data used for the writing operation, after the state of the memory cells is read out each time writing occurs. Thus, in the conventional technique except for the verification purpose, an excess reading time is consumed, which makes the total time necessary for writing in the memory cells longer.
The reasons for requiring the above-described reading from the memory cell at the time of writing is as follows: when the flash memory uses the four valued memory cell, it is necessary to write three times to the three threshold levels corresponding to the three states of the memory cells excluding the state after the erasing operation. In order to carry out three time writing operations, the memory cells must be maintained at three respective states while confirming that the writing to a threshold state is completed. In the conventional device, therefore, the writing is executed in advance for memory cells having the upper rank bit of xe2x80x9c0xe2x80x9d up to the threshold value of VREF2, and the latch (latch 110 and 111) are provided only for two remaining states. In the end, one state among three states is stored by the memory cell and the latches (110 and 11) are provided only for other two states. However, at the stage when respective verification operations executed at respective writing operations are completed, the data stored in the latches used for judging whether the writing can be executed are destroyed. In order to proceed with the processing, it becomes necessary to refer to the data remaining in the latches 110 and 111 without being destroyed and the data remaining in the memory cells, which requires reading the memory cells.
From the point of view of the time for the writing operations, there is other useless time in the conventional device. As shown in FIG. 19, it is assumed that the xe2x80x9cstate 1xe2x80x9d to the xe2x80x9cstate 4xe2x80x9d shown in FIG. 14 are defined as xe2x80x9cerasure levelxe2x80x9d, xe2x80x9cwriting level 1xe2x80x9d, xe2x80x9cwriting level 2xe2x80x9d, and xe2x80x9cwriting level 3xe2x80x9d. In addition, as shown in FIG. 19, it is also assumed that the time required for changing the xe2x80x9cerasure levelxe2x80x9d to the xe2x80x9cwriting level 1xe2x80x9d is T1, the time for changing the xe2x80x9cwriting level 1xe2x80x9d to the xe2x80x9cwriting level 2xe2x80x9d is T2, and the time for changing the xe2x80x9cwriting level 2 to the xe2x80x9cwriting level 3xe2x80x9d is T3.
As shown above, in the conventional technique, the overall writing operation is carried out first writing from the xe2x80x9cerasure level (the state 1)xe2x80x9d to the xe2x80x9cwriting level 1 (the state 2)xe2x80x9d, then from xe2x80x9cthe erasure levelxe2x80x9d to the xe2x80x9cwriting level 2 (the state 3)xe2x80x9d, and finally from the xe2x80x9cerasure levelxe2x80x9d to the xe2x80x9cwriting level 3 (the state 4)xe2x80x9d. Thus, the total time for the overall writing operation becomes (T1+T2)+T1+T3=2*T1+T2+T3. If it is possible to raise the writing level from the xe2x80x9cerasure levelxe2x80x9d to the xe2x80x9cwriting level 2xe2x80x9d in sequence, then the total writing time can be reduced to T1+T2+T3. The conventional device, therefore, has a problem that it spends an excess time of T2 compared with the minimum time of T1+T2+T3.
Another problem arises in the above-described conventional writing processing. That is, since no further writing is executed for the memory cells of which the verification is completed, subsequent cases are caused in which, among memory cells connected with an identical word line, some memory cells are written and the other memory cells are not yet written. In such a case, a high voltage is also applied to every memory cell, which means that a high voltage also applied to the not written memory cells. Thereby, those memory cells are turned into a weakly written state. This weakly written state is called a xe2x80x9cdisturbedxe2x80x9d state.
FIG. 20 shows the state in which two memory cells are disturbed. In the figure, two memory cells 150 and 151 are connected to a word line WL1, and the other two memory cells 152 and 153 are connected to another word line WL2. It is now assumed that writing is executed in the memory cell 150. In this case, the voltage applied to the word line WL1 to which the memory cell is connected is assumed to be xe2x80x9c15 Vxe2x80x9d, and the voltage applied to another word line WL2 is assumed to be xe2x80x9c0 Vxe2x80x9d. In addition, the voltage applied to the bit line BL1 connected with the memory cell 150 and 152 is assumed to be xe2x80x9c0 Vxe2x80x9d, and the voltage applied to the bit line BL2 connected with the not written memory cells 151 and 153 is assumed, for example, to be xe2x80x9c5 Vxe2x80x9d. Thus, xe2x80x9c15 Vxe2x80x9d plus xe2x80x9c5 Vxe2x80x9d are applied to the memory cell 151, and xe2x80x9c5 Vxe2x80x9d is applied to the memory cell 153, both memory cells are turned into the disturbed state. Since the repeated occurrence of the disturbed state will degrade the reliability of each memory cell, so that it is preferable to prevent each memory cell from causing the disturbed state. However, in the conventional writing operation, the writing from the xe2x80x9cerasure levelxe2x80x9d to the xe2x80x9cwriting level 1xe2x80x9d is executed twice, which implies that the disturbed state occurs more frequently than the sequential writing operation from the xe2x80x9cerasure levelxe2x80x9d to the xe2x80x9cwriting level 3xe2x80x9d. As a result, it is preferable not to execute the writing operation so frequently as the conventional operation.
Furthermore, in the conventional device, the threshold values for holding the memory cells at the time of the writing operation increases in the order from the lowest xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d to the highest xe2x80x9c00xe2x80x9d. If the threshold values are reduced for some reasons such as the stress, the essential data xe2x80x9c10xe2x80x9d contained in the conventional rank appears as if it were xe2x80x9c10xe2x80x9d, which causes two error bits, when viewed from the outside of the flash memory.
In general, one error bit can be corrected by a data correction circuit using an ECC (Error Correction Code), but it is difficult to correct two error bits by this data correction system. However, it becomes possible to correct two error bits by the addition of an extra redundancy bit to the normal redundancy bit for the ECC, which results in reducing the utilization efficiency of the ECC, and enlarging the circuit scale compared to the circuit for correcting one bit.
It is therefore an objective of the present invention to provide a nonvolatile semiconductor memory device, which nonly requires reading the essentially necessary writing and verification operations when writing the multi-valued data is carried out. It is also a further objective of the present invention to provide a nonvolatile semiconductor memory device, which, in writing multi-valued data, is capable of writing by the least number of times, and which does not cause degradation of reliability due to unnecessary occurrence of the disturbed state. It is also a still further objective of the present invention to provide a nonvolatile semiconductor memory device, which prevents generation of two error bits, even when the threshold of the memory cells storing multi-valued data is reduces.
In order to solve the above problems, according to the first aspect of the present invention, a nonvolatile semiconductor device is provided with a plurality of memory cells for storing more multi-valued data than binary data, comprising: a plurality of latches provided in the same number of the threshold values set for identifying each data of said multiple data stored in said memory cell; and a writing device for writing into said memory cells until reaching the threshold value corresponding to writing data, while setting and referring to the data stored in said plurality of latches corresponding to the given multi-valued writing data.
According to the second aspect of the present invention, in the nonvolatile semiconductor device according to the first aspect, each data of said multi-valued data which is identified by each of said threshold values is constructed by a gray code.
According to the third aspect, in the nonvolatile semiconductor device according to the first aspect, said latches comprise the three first to the third latches provided with the same numbers as three first to the third threshold values for identifying the four valued data represented by two bits, and said writing device executes the writing operation comprising the steps of: (1) setting initially said first and second latches with each bit of said writing data and initializing the said third latch to the writing permission data or the writing prohibition data in accordance with said writing data; (2) resetting said second latch to the writing permission data in advance, if the data stored in said third latch is the writing permission data, before respective writing stages for executing writing operations up to said first to said third threshold values; (3) setting the writing prohibition data in the second latch after writing data from the erasure level of the memory cell to said first threshold value when the data of the second latch is the writing permission data; (2) resetting said second latch to the writing permission data in advance, if the data stored in said third latch is the writing permission data, before respective writing stages for executing writing operations up to said first to said third threshold values; (3) setting the writing prohibition data in the second latch after writing data from the erasure level of the memory cell to said first threshold value when the data of the second latch is the writing permission data; (4) setting the writing prohibition data in said first latch after writing from the first threshold to the second threshold value when the writing permission data is latched in the first latch; and (5) setting the writing prohibition data in the second latch by writing from the second threshold value to the third threshold value when the writing permission data is written in said second latch.
According to the fourth aspect, in the nonvolatile semiconductor device according to the first aspect, said writing device executes the writing operation from the threshold value closest to the erasure level of the memory cells at the time of erasing said memory cells towards the remotest threshold values in sequence.
According to the fifth aspect, in the nonvolatile semiconductor device according to the first aspect, said plurality of latches and said writing device are provided in the circuit comprising a sense amplifier and a writing amplifier.
According to the sixth aspect, in the nonvolatile semiconductor device according to the first aspect, wherein, among said plurality of latches, the data read from said memory cells is absorbed in the latch in which said writing data is initially set at the time of writing in said memory cells.
According to the seventh aspect, in the nonvolatile semiconductor device according to the first aspect, wherein the writing device executes a verification operation for verifying whether or not the threshold value to be written is reached each time of the writing operation, and after repeating the writing operation and the verification operation until the threshold value is reached, setting the writing prohibition data in either one of latches used for the writing operation or the verification operation.
USPTO Backgrounds
USPTO Backgrounds