A microprocessor generally is accepted to include various elements of a computer on a single chip of semiconductor material with the possible exception of memory (Program and Data Store).
The various processing functions of a microprocessor are carried out in an area of the chip which includes registers and an arithmetic logic unit and is referred to as the data path portion of the chip. The cooperation between the various elements of the data path portion as well as the sequences in which those elements cooperate is determined by sequences of outputs generated by a programmable logic array (PLA) and applied in a manner to control the data path portion of the chip. See "Introduction to VLSI Systems" by Carver Mead and Lynn Conway, Addison-Wesley, 1980 for a full explanation of PLA's.
A PLA includes a decoder section and a read only memory (ROM) section with associated input and output registers respectively. The decoder section is known as an "AND" plane and includes a drive line for each input term and one for each complement term. Each of the drive and complement lines intersect electrically conducting output lines which extend into the ROM section where they become "word" lines. The lines which intersect the drive and complement lines are called decoder output lines. At selected intersections in the decoder section, pulldown transistors are formed. The transistors respond to various input codes to ground selected decoder output lines. The outputs of the AND plane thus are determined by the locations and gate connections of pulldown transistors connected to the decoder output lines.
The ROM section of a PLA also includes output lines which intersect the word lines. Again, pulldown transistors are formed at selected ones of those intersections with transistor gates connected to the word lines. In the case of CMOS logic, if the gate of any transistor connected to a decoder output line is at a high (low) voltage, that entire output line is at a low (high) voltage as is the associated word line in the ROM section. By a selective placement of transistors in both the decoder section and the ROM section of a PLA, a particular output code appears on the ROM output lines for each input code applied to the inputs of the decoder section. In this manner, instructions of an input program are decoded into a sequence of cycle-by-cycle actions. A representation of the repertoire of actions is termed a state diagram.
The action to be performed during a give two phase cycle (.phi..sub.1 and .phi..sub.2) is defined at the output of a ROM section of a PLA at an output register clocked during phase .phi..sub.2 or a two phase clock cycle. An input register to the PLA is operative to store, in a .phi..sub.1 phase, input data that were applied to it during the immediately preceding .phi..sub.2 phase.
As the number of operations performed by the elements of the data path portion of a microprocessor chip increases, so does the requisite number of cycle-by-cycle actions. The number of distinct actions that a PLA can invoke is a function of the number of word lies. Consequently, the PLA has to increase in size in order to invoke an increased number of actions. Since the available area on a semiconductor chip is limited, the space available for the PLA is also limited. Further, as the PLA increases in size it operates more slowly and thus limits the clock rate of the entire device. The problem thus is to implement a requisite logic function with a PLA of relatively reduced area.
USPTO Backgrounds
USPTO Backgrounds