1. Field of the Invention
This invention relates generally to field programmable gate arrays (FPGAs). In particular, it relates to the implementation of improved architectures and functions to interface with an FPGA.
2. Background of Related Art
A Field Programmable Gate Array (FPGA) is a programmable integrated circuit which provides a customized logic array and functionality to a particular customer.
FIG. 8 depicts a conventional Field Programmable Gate Array (FPGA).
In particular, as shown in FIG. 8, an FPGA 400 typically includes four distinct features: configuration memory 406, input/output (I/O) blocks 408-414, configurable logic blocks 404, and a routing network 402 between the internal components.
Configuration memory 406 provides access between the elements of the FPGA 400 and one external controlling device (e.g., a programmer). Based on the contents of the configuration memory 406, various logical functions of the configurable logic blocks 404 are enabled and wired together via a configuration of the routing network 402. Similarly, certain logic blocks are provided I/O access through various types of I/O devices 408-414, as determined by both the configuration memory 406 and the routing provided by the routing network 402.
The configuration memory 406 may be, e.g., static RAM (SRAM). The configuration memory bits turn elements or switches on or off in embedded elements of the configurable logic blocks 404, and establish routing between elements of the FPGA 400, to define the functionality of the FPGA 400.
Typically, individual memory bits of the configuration memory 406 define the desired functionality of the FPGA device 400. These configuration memory bits are conventionally loaded one at a time using data lines and address lines directly to the configuration memory 406 (e.g., SRAM) over an external bus 420 from an external source. All embedded elements are programmed similarly using the same format to the configuration memory 406.
Other types of configuration memory 406 typically include, e.g., EPROM or EEPROM, anti-fused, fused, or other storage devices, providing either one-time programmability, or multiple reprogrammability. The configuration memory 406 may be formed of one or more types of memory (e.g., SRAM and EEPROM).
The I/O blocks 408-414 conventionally provide direct connection between an internal, embedded component of the FPGA 400, and external devices. The I/O blocks 408-414 may be hard-wired and/or configured and routed based on the user-instructed configuration stored in the configuration memory 406.
Typically, multiple I/O blocks are provided each conforming to a separate transmission standard. For instance, a first I/O block may be provided to allow for 5 volt powered, single ended transmission, another for 5 volt powered, differential transmission, another for low voltage such as 3.3 volt powered single ended transmission, etc. To provide flexibility for an end user, multiple I/O circuits are required to accommodate the broadest range of possible uses by the user.
The routing network 402 is programmably defined by the configuration memory 406 to route signaling between the internal logic blocks of the FPGA. The routing network 402 carries signal traffic between the various internal, embedded components of the FPGA 400. Some portions of the routing network 402 may be directly connected or hard wired and/or may not be fully programmable by the user.
FPGA devices often include embedded run-time memory 450 in addition to the configuration memory 406. The embedded run-time memory 450 is accessible until configuration of the FPGA 400 is complete. Moreover, the configuration memory 406 is generally not reprogrammed while the FPGA device 400 is in operation.
FPGA devices 400 are typically programmed using an appropriate configuration and routing software application which inputs a users particular requirements, and determines a best configuration of the routing of the FPGA 400 by steps generally referred to as xe2x80x9cpartitioningxe2x80x9d, xe2x80x9cplacingxe2x80x9d, and xe2x80x9croutingxe2x80x9d, to ultimately configure the elements of the FPGA 400 to meet the particular user""s needs.
In general, FPGAs are targeted toward higher-speed applications, which require high-speed I/O interfaces. The I/O interfaces of conventional FPGA devices (e.g., those conforming to differential transmission techniques such as LVDS or LVPECL standards) require the inclusion of an external resistor by the user (e.g., circuit board designer) to meet given I/O standards. Unfortunately, use of an external resistor increased costs to the user. Moreover, signal integrity is dependent on the proximity of the termination resistor to the receiver, and thus external resistance reduces signal integrity at the receiver.
In other conventional devices, particular conformance to certain standards (e.g., LVDS or LVPECL) is provided, by selection of one of a plurality of differently dedicated I/O buffers. However, each of these dedicated I/O buffers offer little flexibility to perform in other capacities, or required complimentary logic to do so. Unfortunately, a large number of dedicated I/O buffers and/or such complimentary logic requires additional silicon space, making the FPGA device larger and possibly consume additional power.
There is thus a need for a more flexible FPGA device, allowing a wide range of flexibility in I/O interfacing without requiring significantly more silicon space in an integrated circuit.
In accordance with the principles of the present invention, a multi-function I/O buffer in a programmable device comprises an enablable differential receiver, and an embedded differential resistance on a same integrated circuit as the enablable differential receiver.
A method of providing multi-functionality in an I/O buffer of a programmable device in accordance with another aspect of the present invention comprises programmably enabling either a differential receiver or a single ended receiver. A differential transmitter or a single ended transmitter is programmably enabled. If the differential receiver is enabled, an embedded resistance between input terminals of the differential receiver is also programmably enabled. If the single ended receiver is enabled, the embedded resistance is programmably disabled.
In yet another aspect of the present invention, an I/O bank in a programmable device comprises a plurality of groups of I/O buffers, each of the I/O buffers being bonded to an external pin for power input. Each of the I/O buffers is capable of being powered at a different voltage level.
In accordance with still another aspect, an I/O element of a programmable logic device relating to a single external pin of the programmable logic device comprises at least two input flipflop devices. A first one of the two input flip-flop devices is clocked on a first edge of a clock signal, and the other input flip-flop device is clocked on a second edge of the clock signal, the second edge being opposite the first edge.
Still another aspect includes an I/O element of a programmable logic device relating to a single external pin of the programmable logic device comprising at least two output flip-flop devices. A first one of the two output flip-flop devices is clocked on a first edge of a clock signal. A second one of the two output flip-flop devices is clocked on a second edge of the clock signal, the second edge being opposite the first edge.
A method of providing a double data rate mode in a programmable logic device in accordance with an aspect of the invention comprises configuring a first flip-flop to input a data signal clocked on a first edge of a clock signal. A second flip-flop is configured to input the data signal clocked on a second edge of the clock signal opposite the first edge of the clock signal.
USPTO Backgrounds
USPTO Backgrounds