1. Field of the Invention
The present invention relates to a semiconductor device including a metal-insulator-metal (MIM) capacitor. More particularly, the present invention relates to a method for manufacturing such a device in which a via for connecting upper and lower conductive layers is formed through an insulating interlayer after a silicon nitride layer is deposited as a thick layer on the insulating interlayer. An edge region of a MIM capacitor during an etching process to form the via is thereby protected. Also, the use of a fluorine gas to remove a polymer residue during a via pattern photoresist stripping process is thereby enabled.
2. Discussion of the Related Art
A related art MIM capacitor includes upper and lower electrodes, each formed of a patterned layer of metal, such as copper. A semiconductor device including such a capacitor typically comprises a number of metal wiring layers separated by an insulating interlayer, and upper and lower wiring layers electrically connected to each other by a contact plug formed in the insulating interlayer. The insulating interlayer may be made of oxide. In a process for forming the contact plug, photoresist is deposited on the insulating interlayer and is patterned to leave an opening over a pad of the lower wiring layer. The photoresist pattern is used as a mask during an etching process for the insulating interlayer, to thereby form a contact hole or via exposing the underlying pad of the lower wiring layer. The via is then filled with a low-resistance metal, such as tungsten, to improve the contact resistance of the plug. The upper metal layer is then formed over the plug. The plug is formed adjacent the MIM capacitor. The metal wiring layers of the plug may be deposited and patterned at the same time as the electrodes of the capacitor are formed.
An insulator layer of the MIM capacitor is typically formed of a layer of silicon nitride deposited on the insulating interlayer. The insulating interlayer should have a thickness for sufficiently separating the upper and lower wiring layers. Since the upper and lower electrodes of the capacitor should be separated by a minimum distance in order to maximize capacitance, a large step at the edges of the MIM capacitor is typically present. The insulator layer is thus formed over the step, and a photoresist pattern for forming the via is formed on the insulator layer. Thus, the photoresist tends to be thinner at the corners of these stepped edges, permitting an etchant to attack the MIM structure during the etching process for forming the via.
FIGS. 1A-1E are cross-sectional views of a related art MIM capacitor of a semiconductor device and illustrate the above-mentioned etching process being performed with respect to the MIM capacitor. A lower metal layer is formed on a surface of a semiconductor substrate (not shown) and includes a lower electrode 101 and a lower wiring layer 102. The lower electrode 101 and the lower wiring layer 102 may occupy different planes. An insulating interlayer 103 may be formed of an oxide to a thickness such that the lower wiring layer 102 will be separated from an upper wiring layer by a distance A. This distance is typically about 9,000 Å. A silicon nitride layer 104, for isolating the lower electrode 101 from an upper electrode, is formed on the insulating interlayer 103 and has a thickness of approximately 650 to 750 Å. A photoresist layer 105 for forming a via is deposited on the silicon nitride layer 104.
Referring to FIG. 1A, a thin portion 10 of the photoresist layer 105 occurs at the edges of the step of the MIM structure. This thinning phenomenon occurs despite the thickness of the photoresist layer 105. The thinning phenomenon degrades the coating performance and the masking characteristics of the photoresist.
Referring to FIG. 1B, the photoresist layer 105 is subject to exposure and development to form a photoresist pattern. Then, using the photoresist pattern as a mask during an etching process, a via 106 for exposing a pad surface area of the lower wiring layer 102 is formed in the insulating interlayer 103. The etching may result in a damaged region 20, i.e., spiking, at the thinner portion of the photoresist pattern.
Referring to FIG. 1C, a gas stripping process is performed to remove the photoresist pattern. The gas may include oxygen (O2). During and after the stripping process, an undesirable polymer residue 40 may remain. The polymer residue is a severe problem, particularly in a semiconductor device having greater topology variations. The step size increases at the edges of the MIM structure in a semiconductor device having greater topology variations.
Referring to FIG. 1D, after the photoresist pattern is removed, the via 106 may be filled with a material, such as tungsten. The material may be formed as a thick layer on the entire substrate. The thick layer is then planarized by, for example, chemical-mechanical polishing, to leave a plug 106a, such as a tungsten plug, in the via. Simultaneously, the damaged region 20 is also filled with the material, such as tungsten, to form a conductive notch 106b that may reach the lower electrode 101 by piercing the silicon nitride layer 104.
Referring to FIG. 1E, an upper electrode 107 is formed on the silicon nitride layer 104 to correspond to the lower electrode 101, and an upper wiring layer 108 is formed on the plug 106a to connect to the lower wiring layer 102. Thus, the conductive notch 106b causes an electrical short between the lower electrode 101 and the upper electrode 107.
FIG. 2 shows the polymer residue remaining near the edges of the related art MIM structure after via etching and photoresist stripping and before tungsten deposition. The polymer residue remains even after photoresist stripping, which is typically performed by an oxygen (O2) gas stripping process. The polymer residue unfavorably changes the characteristics of the MIM capacitor and causes uncontrollable variations in a desired capacitance value. Though photoresist stripping and polymer removal can be improved by stripping using other gases, such alternative techniques are too aggressive for the insulator layer of a MIM capacitor and thus lead to lower yields.
USPTO Backgrounds
USPTO Backgrounds