1. Field of the Invention
The invention pertains to fuse refresh circuits for semiconductor memories, wherein a fuse latch circuit is set by a set circuit in at least one refresh cycle after a voltage supply has been switched on.
Fuse refresh circuits are conventionally employed in order to ensure redundancy especially in semiconductor memory configurations. Specifically, according to the redundancy principle, in a semiconductor memory configuration it is necessary to replace any defective memory cells by memory cells which are operating without any defects. The fuse refresh circuit in this case constitutes a device which, depending on the logic signals fed to it, supplies at its output a defined logic state which may be a "0" or "1", which in turn depends on whether or not the fuse is severed. The fuse is thus a safety device in its true sense insofar as an electrical line is switched on, i.e., set, or severed. "Refresh" should be understood to mean that when the semiconductor memory configuration is switched on, the individual fuses are checked by means of fuse latch circuits, in other words the memory is "refreshed".
2. Description of the Related Art
A conventional prior art fuse refresh circuit is illustrated in FIG. 2. After a DRAM (e.g. 16 Mbit) has been switched on, a set circuit (not shown in FIG. 2) supplies a voltage for a signal CLRN which has a value of 0 V at an operating voltage of about 1 V. If the operating voltage then subsequently reaches a value of about 2.7 V, then the signal CLRN likewise assumes a value of 2.7 V which then follows the operating voltage in the further course of events. The signal CLRN is fed to a p-MOS transistor or FET 14 of the fuse refresh circuit. This p-MOS transistor 14, which has a negative threshold voltage, is connected in series with an n-MOS transistor 16, which has a positive threshold voltage, and with a fuse 20. A fuse latch circuit comprising transistors 17, 19 of mutually opposite conductivity type and an inverter 50 is connected downstream of this series circuit.
The signal CLRN, before it has reached the operating voltage V.sub.B (compare FIG. 3), sets the fuse latch circuit via the p-MOS transistor 14 in such a way that a "1" is present at the input D1 of the fuse latch circuit, i.e., D1="1".
After the signal CLRN has reached the operating voltage, the set circuit supplies a voltage pulse with a duration of about 20 ns for a signal SETP which is fed to the gate of the MOS transistor 16. If the fuse 20 is actually severed, then the input D1 remains set at "1". If, however, the fuse 20 is not severed, then the fuse latch circuit is set in such a way that D1="0". Depending on the state of D1, an address signal AO and a brain signal BRAIN a "0" or a "1" is then present at the output 30 of the fuse refresh circuit.
A two-stage inverter circuit comprising inverters 51, 52 and a parallel circuit comprising MOS transistors 25, 26, 27 and 28 are provided between the inverter 50 and the output 30, the MOS transistors 25 and 26 having the same conductivity type as the MOS transistors 14 and 17, respectively, and the MOS transistors 27, 28 having the same conductivity type as the MOS transistors 16 and 19, respectively. The gate of the MOS transistor 25 is in this case connected to the source and/or drain of the MOS transistor 26, the gate of which is connected to the gate of the MOS transistor 27. The source and/or drain of the transistor 27 is in turn connected to the gate of the MOS transistor 28. The source and/or drain of the MOS transistor 28 is connected to the sources and/or drains of MOS transistors 10, 11, which are of the same conductivity type as the MOS transistor 14. The address signal AO is fed to the gate of the MOS transistor 10 and to the gate of a MOS transistor 9 connected in series with the latter. The signal BRAIN is applied to the gate of the transistor 11 and to the gate of a MOS transistor 8.
For reasons which are difficult to explain in individual cases, problems arise in the existing fuse refresh circuit of FIG. 2 with regard to incorrectly set fuse latch circuits. In other words, in the event of an incorrectly set fuse latch circuit, the signal D1 has, for example, the value "1" even though it should have the value "0". As a consequence, the opposite state to the "correct state" is then likewise present at the output 30.
A partial voltage dip to about 1 V during switching-on with very steep voltage slopes or an incompletely severed fuse having a residual resistance of 100 k.OMEGA. for example, may be assumed to be possible causes of such incorrectly set fuse latch circuits.
Since the 16 Mbit DRAM has about 2,000 fuses, the occurrence of an incorrectly set fuse latch circuit entails extensive investigations, which, nevertheless, do not always yield absolute clarity concerning the defect mechanism that has occurred. These investigations may be so extensive that it is often more expedient to reject the semiconductor memory configuration and not to search for a remedy for the incorrectly set fuse refresh circuit. It is quite understood, however, that such a course of action is undesirable in every way.
USPTO Backgrounds
USPTO Backgrounds