With the development of the semiconductor technology, integrated circuits with better performance and more powerful functions require greater device integration density. Thus, the sizes of the components need to be scaled further. Particularly, with continual scaling of the feature sizes, it becomes more difficult to manufacture contact holes which are used to connect gates and source/drain between devices, and defects existing in the process for manufacturing contact holes will seriously affect yield of products. Although there is another type of trench contact of relatively large size which makes it easier for performing such contact manufacturing processes as patterning and filling and also provides a relatively large contact area, the trench contact with a large contact area will significantly increase capacitance between the trench contact and the gate electrode as scaling down of the feature size of device, thereby impairing performance of devices.
Accordingly, there is a need to propose a method for manufacturing a trench contact structure, which has a large contact area but is capable of reducing capacitance between a trench contact and a gate electrode, and a semiconductor device having such a trench contact structure.
USPTO Backgrounds
USPTO Backgrounds