1. Field of the Invention
The present invention relates to a buffer managing method and a buffer controller thereof, and more particularly, to a buffer managing method of synchronizing units of a buffer controller and the buffer controller thereof.
2. Description of the Prior Art
Buffer controlling related to mass data processing is always an important issue, where the mass data includes multimedia data streams. For buffering the mass data, different high-speed interfaces and drivers of different operating systems are also utilized in a buffer controller.
However, using the different interfaces and drivers may introduce compatibility-related issues in the buffer controller as well, for example, asynchronous clocks of different elements in a single buffer controller. Please refer to FIG. 1, which schematically illustrates a conventional buffer controller 100 and how it cooperates with a host 110 and a flash memory 120, for explaining the compatibility-related issues mentioned above.
As shown in FIG. 1, the buffer controller 100 serves as a bridge between the host 110 and the flash memory 120 in data transmission, where the buffer controller 100 and the flash memory 120 may be disposed in a same hardware device. The buffer controller 100 includes an interface 130, a data processing unit 140, a rear processing engine 150, a micro processor 160, and a buffer 170.
The interface 130 is utilized for receiving data from the host 110 in correspondence with an operating system utilized by the host 110. The data processing unit 140 is utilized for processing data received by the interface 130. The rear processing engine 150 is utilized for checking the data processed by the data processing unit 140, such as error correction so that correctness of the data transmitted to the flash memory 120 can be ensured. The micro processor 160 is utilized for coordinating operations of the interface 130, the data processing unit 140, the rear processing engine 150, and the buffer 170, where the buffer 170 is utilized for buffering process variables or information for the micro processor 160.
As can be observed from FIG. 1, if the interface 130, the data processing unit 140, the rear processing engine 150, the micro processor 160, and the buffer 170 are operated under a plurality of asynchronous clocks respectively, correctness of data processed by the elements of the buffer 100 may be significantly decreased.
USPTO Backgrounds
USPTO Backgrounds