Charge pump circuits are frequently used in semiconductor integrated circuits to provide a voltage that is higher than the voltage of a power supply, often a battery, or a voltage of reverse polarity. These circuits are particularly useful in flash and EEPROM non-volatile memories, but are gaining more and more acceptance in analog circuits in order to increase dynamic range and simplify circuit design. One of the most popular charge pump circuits is the Dickson charge pump 10, shown in FIG. 1 wherein switched capacitor multi-stage circuitry is featured. Each stage is made of a capacitor 12 and an NMOS type transistor 14 acting as a diode. These transistors have their bulk or substrate connected to ground, their drain and gate connected together to the stage capacitor, and their source connected to the capacitor of the next stage. Two inverted phase clocks, not shown, are used for pumping charge from stage to stage. The maximum gain per stage of the Dickson charge pump 10 is (VDD−VT), where VT is the threshold voltage of an NMOS device.
For some applications, the Dickson charge pump 10 has a number of drawbacks. For instance, the number of stages that can be cascaded is limited by the amount of the voltage drop increase between the source and the bulk of an NMOS device resulting in a dramatic VT increase on the last stages. Another significant drawback is that thick oxide, high voltage dedicated transistors are necessary to sustain a large voltage drop between gate and bulk in a reliable way. This makes it impossible to design Dickson charge pumps using thin oxide, low voltage standard devices which can sustain a maximum drop of VDD.
Many improvements to the basic Dickson structure have been made to overcome the gain degradation due to threshold voltage described above. Among the large number of proposed solutions, the four phase charge pump structure disclosed by Hongshin Lin and Nai-Hsein Chen in the paper “New Four-Phase Generation Circuits for Low-Voltage Charge Pumps,” published in the Proc. ISCAS' 2001, stands out as a very efficient approach to prevent gain degradation due to the threshold voltage. For example, a 9V output voltage was obtained by using a ten stage pump, starting from 1V power supply. However, this approach is not feasible for a standard CMOS process. Another solution involves overcoming the gain degradation due to threshold voltage by using low voltage transistors, is disclosed in the U.S. Pat. No. 5,874,850, issued to Pulvirenti. The '850 patent uses a two phase clocking scheme and NMOS devices with triple well technology. Triple well processes require additional masking and etching steps compared to the standard CMOS process. An object of the invention is to achieve a high efficiency charge pump overcoming drawbacks of the prior art.
USPTO Backgrounds
USPTO Backgrounds