The fabrication of many present day devices often entails etching of multiple layers to define device features. For example, some memory devices such as magnetic random access memory (MRAM) or other advanced memory devices are fabricated from a layer stack that includes multiple different materials in the different layers, including metals or metal alloys. Etching of such a layer stack suffers from many challenges due to the presence of non-volatile material within the layer stack such as Co, Pt or Fe. Because of the non-volatile nature of such material, the etching process for patterning an MRAM layer stack mainly relies on physical etching mechanisms.
After a patterned mask material that is used to define MRAM cells is formed on a substrate, the mask etch rate may be similar to that of the exposed layer stack materials, resulting in significant erosion of the mask. This limits the thickness of a layer stack that can be etched for a given mask thickness. For example 90 nm TiN or W may be used as a hard mask for etching of a 30 nm MRAM layer. In addition, material that is etched from the layer stack including metallic material may be redeposited on sidewalls of patterned features being formed, such as memory cells, leading to an increase in critical dimension of a cell, for example, from 25 nm to 40 nm. Metal residue may form at the edge of a recess oxide due to ion knock-on/mixing during etching, leading to shorting between metal layers. Moreover, lack of abruptness and sidewall damage in such cells may degrade performance in MRAM devices to be formed.
Current attempts to address these problems include the use of multiple angle ion etching to improve profile abruptness of patterned features and reduce redeposition. However, this may involve time based etching, which is not a robust process that can account for variation in layer stack thickness or etch rate drift with time. It is with respect to these and other considerations that the present embodiments may be needed.
USPTO Backgrounds
USPTO Backgrounds