This invention relates to a PNPN semiconductor switch, more particularly, to a planer-type semiconductor switch with an MOS structure for the use in speech paths of an electronic telephone exchange or the like.
Generally, a PNPN semiconductor switch is triggered by injecting a gate current into a P gate region or by projecting light upon a PN junction between a P gate region and an N gate region (N type silicon substrate) for producing a photocurrent.
The performance of such a PNPN semiconductor switch is represented by its drive sensitivity, dv/dt capability and voltage resistance characteristics.
The drive sensitivity characteristic means a minimum gate current or a photocurrent that triggers the PNPN semiconductor switch and can be controlled by the value of a shunt resistance connected in parallel with the P gate electrode and the cathode electrode. Generally, a high shunt resistance value allows the PNPN semiconductor switch to be triggered with a small gate current or light.
However, when the drive sensitivity of the PNPN semiconductor switch is too high, and where an input voltage having a high rise time is impressed across the anode and cathode electrodes, without injecting a gate current into the P gate region or without projecting light, the PNPN semiconductor switch is often erroneously triggered due to a transient current generated at the PN junction inside of the PNPN semiconductor switch.
The dv/dt durability characteristic depends upon the value of the shunt resistance. Thus, if the value of the shunt resistance is small, the probability of misoperation is small, whereas as the value of the shunt resistance increases, erroneous operations are liable to occur. In this manner, in the PNPN semiconductor switch, the drive sensitivity characteristic and the dv/dt capability characteristic (difficult to misoperate due to dv/dt) conflict with each other.
Furthermore, the PNPN semiconductor switch is required to have high voltage resistance characteristics for both forward and reverse anode-cathode voltages. More particularly, where the breakdown voltages of PN junctions in the PNPN semiconductor switch are low, thus causing avalanche currents or a PNP portion and an NPN portion constituting the PNPN semiconductor switch accompany punch-through phenomena causing currents to flow, and such currents would cause the PNPN semiconductor switch to misoperate.
Unless all of the high voltage resistance characteristics, the high dv/dt capability characteristic and the high drive sensitivity characteristic are satisfied, a satisfactory PNPN semiconductor switch cannot be realized.
Among the devices which simultaneously satisfy the high dv/dt capability and the high drive sensitivity is a PNPN semiconductor switch provided with a MAC (MOS associated circuit) in which a planar type PNPN element and a MOS FET all integrally combined for preventing dv/dt misoperation.
The prior art PNPN semiconductor switch shown in FIG. 1A comprises a P type diffused region 1 acting as an anode region, a P type diffused region 2 acting as a P gate region, an N type diffused region 3 acting as the cathode region and a source region of a MOS FET, an N type diffused region 4 acting as the drain region of the MOS FET, an anode electrode 5, an anode terminal 5', an aluminum gate electrode 6, an aluminum conductor 7 interconnecting the anode electrode 5 and the aluminum gate electrode 6, a polycrystalline silicon gate electrode 8 of the MOS FET, a resistor 9 formed by changing the configuration of a portion of the polycrystalline silicon gate electrode, a P gate electrode 10 interconnecting the diffused regions 2 and 4, and an N type silicon substrate 11 acting as an N gate region. The semiconductor switch further comprises a semiinsulator film 12 formed on the surface of the N type silicon substrate 11 between the P type diffused regions 1 and 2, an insulating film 13, for example a silicon oxide film interposed between the semiinsulator film 12 and the aluminum conductor 7, a semiinsulator film 14 which, except for the area covered by semiinsulator film 12, is formed on the surface of the N type silicon substrate 11, an insulating film 15, a cathode electrode 16 led out from the N type diffused region 3 through an electrode not shown in FIG. 1A, and a shunt resistor 17 electrically interconnecting the cathode terminal 16 and the P gate electrode 10.
In the PNPN semiconductor switch described above, a capacitor C.sub.1 is formed between the aluminum gate electrode 6 and the polycrystalline silicon gate electrode 8. Further, a capacitance C.sub.2 is formed between the polycrystalline gate electrode 8 and the diffused regions 2, 3 and 4.
The P type diffused region 1, the N type silicon substrate 11, the P type diffused region 2 and the N type diffused region 3 constitute a PNPN element.
A two layer gate MOS FET is formed by using the N type diffused region 3 as the source region, the N type diffused region 4 as the drain region, the P type diffused region 2 as a substrate, and the gate electrodes 6 and 8 as a two layer gate electrode. In this MOS FET, the resistor 9 and the P gate electrode 10 constitute a MAC. The resistor 9 and the capacitors C.sub.1 and C.sub.2 form a discharge circuit of the polycrystalline silicon gate electrode 8 of the MOS FET with the MAC.
To improve the sensitivity characteristic of the PNPN semiconductor switch described above, the value of the shunt resistor 17 is usually selected to be large.
This PNPN semiconductor switch operates as follows.
Where an input voltage having a shorter rise time than the time constant of a RC circuit comprising the resistor 9 and the capacitors C.sub.1 and C.sub.2 is impressed across the anode and cathode electrodes, the diffused regions 2, 3 and 4 would have substantially the same potential as the cathode terminal 16 due to the provision of the P gate electrode 10 and the shunt resistor 17.
At this time, the potential of the polycrystalline silicon gate electrode 8 rises to a value determined by the voltage dividing action of the capacitors C.sub.1 and C.sub.2 and forms an N type channel on the surface of the P type diffused region 2 (P gate region) between two N type diffused regions 3 and 4, thus decreasing the impedance between the N type diffused regions 3 and 4, and hence that between the diffused regions 2 and 4. Thus, the impedance between the P gate electrode and the cathode electrode of the PNPN element becomes low so that the switch does not misoperate due to dv/dt.
The potential at the polycrystalline silicon gate electrode 8 discharges through a RC circuit including the resistor 9 and the capacitors C.sub.1 and C.sub.2. It is easy to set the time constant of the RC circuit to a length sufficient to prevent dv/dt misoperation of the switch by suitably selecting the shape of the polycrystalline silicon resistor 9 and the concentration of the impurity.
As described above the PNPN semiconductor switch shown in FIG. 1A has a high dv/dt capability characteristic.
The drive characteristic will now be considered. The PNPN semiconductor switch can be driven by either one of a light drive in which light is projected upon a PN junction between the N type silicon substrate 11 and the P type diffused region 2, a method in which drive current is applied to the P gate electrode 10, and a method in which the drive current is taken out from the N type silicon substrate 11. In each case, the drive sensitivity is determined by the impedance between the P gate electrode and the cathode electrode at the time of driving the PNPN element.
When driving the semiconductor switch, it is usual to impress direct current or low frequency alternating current between the anode and cathode electrodes. At this time, the potential of the polycrystalline silicon gate electrode 8 becomes equal to that of the P type diffused region 2 through the resistor 9 and the P gate electrode 10 which is different from the prior art dv/dt input application so that no channel would be formed between the N type diffused regions 3 and 4. Consequently, the impedance between the P gate electrode and the cathode electrode of the PNPN semiconductor element at the time of drive is determined only by the shunt resistor 17 so that the sensitivity of the semiconductor switch can be improved by increasing the value of the shunt resistor 17. As above described, a large value of the shunt resistor 17 does not affect the dv/dt durability.
In the PNPN semiconductor switch shown in FIG. 1A, a high voltage resistance characteristic under an off state is obtained by the provision of the semiinsulator film 12. It is now supposed that a reverse bias potential lower than that of the cathode terminal 16 is applied to the anode terminal 5'. Then, the PN junction between the P type diffused region 1 and the N type silicon substrate 11 will be biased reversely, thus forming a large depletion layer. In the absence of the semiinsulator film 12, the potential difference between the aluminum conductor 7 interconnecting the anode electrode 5 and the aluminum gate electrode 6 and the N type silicon substrate 11 beneath the conductor 7 would be substantially the same as the impressed voltage so that a depletion layer is formed on the surface of the N type silicon substrate 11 through the insulating film 13 and since this depletion layer is connected with the first mentioned depletion layer formed by the P type diffused layer 1 and the N type silicon substrate 11, the P type diffused regions 1 and 2 are connected through the depletion layers, whereby current flows due to a punch-through phenomenon to decrease the voltage resistance characteristic between the anode and cathode electrodes of the PNPN semiconductor element to an extremely small value. However, where the semiinsulator layer 12 is provided as shown in FIG. 1A, the aluminum conductor 7 prevents a depletion layer from being formed on the surface of the N type silicon substrate 11 with the result that the punch-through phenomenon would not occur between the P type diffused regions 1 and 2 and the PNPN semiconductor element manifests an excellent voltage resistance characteristic.
A term semiinsulating film usually means an insulating film having a resistivity of about 10.sup.6 -10.sup.10 ohm cm. On the other hand, the silicon substrate has a resistivity of 1-10.sup.2 ohm cm, and an insulating film has a which is higher than at least 10.sup.14 ohm cm.
The semiinsulator film usually comprises a polycrystalline silicon film containing 10-50% of oxygen. However, the characteristics, such as the electrical conductivity, of a polycrystalline silicon film containing oxygen vary depending upon such factors as the content of oxygen, the conditions which occurred during the forming of the film, such as temperature, and the grain size of the grown film. For this reason, the manufacturing process of a semiinsulator film having desired characteristics is difficult which respect to reproduceability and controllability.
The semiinsulator film of this type is not used for other portions of the semiconductor element so that it cannot be formed simultaneously with the other component elements, thus increasing the manufacturing cost which contradicts to the advantage of manufacturing an integrated circuit.
Furthermore, the semiinsulator film has a defect in that its electrical characteristics vary with time due to its crystal structure when it is subjected to a strong electric field of about 1 MV/cm at a temperature of about 100.degree. C. for about 100-1,000 hours. When the resistivity of the semiinsulator film increases, the voltage resistance characteristic across the PNPN semiconductor switch shown in FIG. 1A perfectly disappears, whereas when the resistivity decreases, leakage currents through the switch increase. For this reason, the use of the semiinsulator film decreases the reliability of the semiconductor switch. Especially, the aging of the characteristics of the semiinsulator film has an adverse effect on the PNPN semiconductor switch for use in a telephone exchange.
When a semiinsulator film is used, a response time that prevents formation of a depletion layer immediately beneath the semiinsulator film is slow so that the semiinsulator film has substantially the same effect as an insulating film for a high frequency signal having a frequency of higher than several tens of KHz or a transient signal so that its voltage resistant ability is low whereby a transient current momentarily flows.
Accordingly, where a semiinsulator film is used, it has been extremely difficult to readily manufacture at a high yield a reliable planar type PNPN semiconductor switch having a high voltage resistance characteristic between the anode and cathode electrodes of more than 500 V.
USPTO Backgrounds
USPTO Backgrounds