1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the invention relates to a dual chip package comprising two memory chips configured in a single package.
This application claims priority under 35 U.S.C § 119 to Korean Patent Application 2006-35480 filed on Apr. 19, 2006, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
Semiconductor memory devices may be categorized as random access memory (RAM) and read only memory (ROM). RAM is volatile in its storage nature and loses data when power is interrupted. In contrast, ROM is non-volatile and retains stored data even when power is interrupted. RAM includes dynamic RAM (DRAM) and static RAMs (SRAM). ROM includes programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), and flash memory.
Contemporary semiconductor memory devices are characterized by higher performance, lower cost, smaller size and greater integration density. Most semiconductor memory devices are now manufactured using technology allowing unit components having sizes in the range of 0.18 micrometer or less. Still higher integration densities and smaller component and circuit pattern sizes are highly desirable objectives in emerging semiconductor device designs. A variety of technical approaches have been advocated to reduce device size as well as the overall manufacturing costs.
One approach suggests manufacturing at least two individual semiconductor “chips” within a single package. For example, multi-chip packages may include a processor and associated memory chips, or one or more logic chips together with memory chips, or multiple memory chips. By reducing the number of separately packaged chips and eliminating the corresponding external (i.e., outside a chip package) means of connecting multiple chips, significant size and cost reductions may be realized.
One conventional approach to the manufacture of dual memory chips within a single package is disclosed, for example, in U.S. Pat. No. 6,366,487, the subject matter of which is hereby incorporated by reference. In the above-mentioned patent, a dual chip package technology is described. Consistent with this approach, identical memory chips are provided within a single package in order to increase memory capacity. The dual memory chips in the single package are configured to share external pins (e.g., address, control, and data pins). For this reason, the memory chips in the single package are classified, using option pads, into a designated “top” memory chip and a “bottom” memory chip.
For example, an option pad associated with a bottom memory chip may be connected to a ground voltage, while an option pad associated with the top memory chip may be connected to a power supply voltage. When an externally applied input address signal indicates the bottom memory chip (e.g., a most significant address bit in the input address matches a logic value apparent at an option pad associated with the bottom memory chip), the bottom memory chip is accessed using the input address. However, when an externally applied input address indicates the top memory chip (e.g., a most significant address bit in the input address matches a logic value apparent at an option pad associated with the top memory chip), the top memory chip is accessed using the input address.
In a typical conventional dual chip package, access to the bottom memory chip is disabled (i.e., cut off) during access period to the top memory chip, and vice verse. Thus, in conventional dual chip packages, the top and bottom memory chips cannot be simultaneously accessed. Thus, in the context of a dual chip package containing dual memory chips, the operating performance of the package (e.g., data bandwidth capabilities) is limited to the capabilities of one of the constituent chips.
USPTO Backgrounds
USPTO Backgrounds