1. Field of the Invention
The present invention relates to data communication, and more specifically, to a system and method for sequentially testing a high-speed serialization and deserialization (SerDes) core.
2. Description of the Related Art
Data communication, such as over cables and backplane traces and between computer chips, cards, systems etc., is commonly provided by serialization and deserialization (SerDes) cores providing high speed and high bandwidth data communication. SerDes cores are often used instead of parallel data buses that provide moderate data transfer rates.
FIG. 1 shows a pair of exemplary SerDes cores 10a and 10b for providing data communication between a first card 12a and a second card 12b across a backplane 16. SerDes core 10a includes transmitter blocks TXa1 and TXa2 and receiver blocks RXa1 and RXa2. SerDes core 10b includes transmitter blocks TXb1 and TXb2 and receiver blocks RXb1 and RXb2. Each receiver and transmitter block includes four links 18RX and 18TX, respectively.
Data is transmitted from card 12a to card 12b by transmitting the data from the links of transmitters TXa1, TXa2 of SerDes core 10a to respective left connectors 20L of backplane 16. The data is transmitted across respective cables 24 to corresponding respective right connectors 20R. The data is received by the links of respective receivers RXb1 and RXb2 of SerDes core 10b. Data is transmitted from card 10b to card 10a in a similar fashion but in the reverse direction. Typically each SerDes core 10a, 10b has an equal number of transmitter and receiver links for enabling communication in both directions between cards 12a and 12b. 
Testing of a SerDes core such as SerDes cores 10a and 10b is time consuming and requires many Built-In-Self-Test (BIST) circuits that consume valuable space and power. Furthermore, if any link fails to function properly during a test, the whole chip on which the link is housed is discarded.
In order to clearly describe testing of the SerDes core 10a or 10b, the design and function of links 18RX and 18TX will be described with reference to FIG. 2 and FIG. 3, respectively. FIG. 2 shows a conventional receiver link 18RX. In an operational mode receiver link 18RX receives actual differential signals RXIP, RXIN in a serial stream. The received actual signals are sensed and amplified by receiver block 202, and then provided to multiplexer (MUX) 206. In a test mode a pseudo-random code (PRC) generator 210 of BIST block 212 generates a serial stream of test differential signals RXTSTP, RXTSTN which are provided to the MUX 206. Depending on whether the receiver link 18RX is operating in the operational mode or in the test mode, the MUX 206 transfers the amplified actual signals or the test signals to a receiver complex 216 where the signals are sampled and latched.
In one embodiment, the receiver block 202 may be a differential amplifier. The receiver complex 216 include sample latches 218 and a selector 220, and a timing complex 224, having a phase rotator 226 and a clock recovery/data detection (CR/DD) block 228, which operate together in a loop including feedback signals fb for coordinating timing of sampling and latching of the data. A multi-phase ½ rate phase lock loop (PLL) 230 receiving a reference clock signal REFCLK provides clock signals to the timing complex 224. The CR/DD block 228 uses a clock recovery algorithm to generate “early” and “late” signals when detected data edge positions are not at expected positions. The “early” and “late” signals are used to continually adjust the phase rotator 226 via the feedback signals fb for obtaining proper data detection. Two bits of data at a time pass through MUX 206 and receiver complex 216, and are then stored in a shift register 234, and then transferred to an 8/10 bit register 238. A counter 240 counts the number of bits transferred into the 8/10 bit register 238, and upon reaching the target number of 8 or 10 bits (depending on whether or not a 10 bit scheme is used) the counter 240 sends a signal DCLK to the 8/10 bit register 238 to release the 8 or 10 bits as output signals RXO<0:9> in parallel. During the test mode, the output signals RXO<0:9> are routed to a pattern recognition logic block 244 of the BIST block 212 which checks the received output signals RXO<0:9> for errors and outputs an error flag indicating when an error has been detected.
FIG. 3 shows a conventional transmitter link 18TX. In an operational mode, transmitter link 18TX receives actual signals TXIN<0:9> in parallel. The received actual signals are provided to multiplexer (MUX) 306. In a test mode a pseudo-random code (PRC) generator 310 of a Built-In-Self-Test (BIST) block 312 generates a series of test signals TXTSTIN<0:9> in parallel which are provided to the MUX 306. Depending on whether the transmitter link 18TX is operating in the operational mode or in the test mode, the MUX 306 transfers the received actual signals or the test signals to an 8/10 bit register 316 where the incoming data is stored. The data (which may comprise single polarity signals or differential signal pairs) is transferred synchronously through a MUX 320 two bits at a time beginning with the least significant bit (LSB) and sequencing to the next significant bit, and is transferred therefrom into a pair of holding latches 322.
Counter 326 tracks the number of two bit pairs processed. Upon determining that all of the bits have been transferred from the 8/10 bit register 316 in a serial fashion a new 8/10 bit word is received and processed by the 8/10 bit register 316. The latches 322, controlled by ½ rate PLL 324, are operated at a ½ bit rate for forwarding the data to a driver/equalizer block (also known as a driver pre-emphasis block) 330. The driver/equalizer block 330 receives the two-bit stream and uses an alternating multiplexing scheme to create a full-rate differential data pair as output signals TXOP, TXON, as is known in the art. During the test mode, the output signals TXOP, TXON are routed to a pattern recognition logic block 344 of the BIST block 312, which outputs an error flag indicating when an error has been detected.
There are several disadvantages associated with the conventional system and method described for testing receiver links 18RX and transmitter links 18TX. First, each receiver and transmitter link, 18RX, 18TX must have a BIST block, which consumes space on the chip and consumes power. Second, the test time for each link is time consuming. Before testing each receiver and transmitter link 18RX, 18TX the respective receiver and transmitter link 18RX, 18TX must be operating with its respective PLL in a locked state. Alternatively the respective PLL may either be locked to a preset multiplied frequency of the REFCLK, or the receiver or transmitter link 18RX, 18TX may be used with any unspecified (garbage) data until the respective PLL reaches a locked state. Thus preparation of the respective PLL consumes time. Further time is consumed while ensuring proper seeding of the PRC generator of the respective BIST of each receiver and transmitter link, 18RX, 18TX prior to testing each link.
Third, MUX 206 is located along the critical path of the actual data signals RXIP, RXIN and the test data signals RXTSTP, RXTSTN, causing signal degradation due to extra signal impedance associated with the MUX 206. Fourth, the test data signals RXTSTP, RXTSTN transmitted by the BIST travel along a short path having a small noise impact relative to a path (not shown) traveled by the actual data signals RXIP, RXIN, so that in the test mode the low noise impact is not realistic. Fifth, the receiver block 202 is bypassed by the test data signals RXTSTP, RXTSTN, and therefore the receiver block 202 is excluded from the testing process.
A conventional test known as link verification partially alleviates the time consumption problems associated with individual testing of each link described above by configuring the receiver and transmit links 18RX and 18TX so that each transmitter link 18TX is paired and connected by a transmission line with one receiver link 18RX. During testing, each link of the 18TX, 18RX link pair being tested is operated in an operational mode until the respective PLL's reach a locked state. The PRC generator 310 of the BIST 312 in the 18TX link is seeded, after which it generates PRC testing data and transmits the testing data to the MUX 306 of the transmit link 18TX. The BIST 212 of the receiver link 18RX is disabled, or alternatively a BIST is not included with the receiver link 18RX. The test data is processed by the transmit link 18TX and transmitted via the transmission line to the paired receiver link 18RX which processes the test data and provides it to the pattern recognition logic block 344 of BIST 312 of the transmit link 18TX. Thus, only one PRC generator and one pattern recognition logic block is needed for each transmitter/receiver link pair, and only one delay is associated with locking the PPL's of the links of the receiver/transmitter link pair, and only one delay is associated with seeding the PRC generator. However, each transmitter/receiver link pair is isolated from other link pairs and must be tested individually. Furthermore, testing of the link pairs is not performed under a controlled noise environment.
Accordingly, a need exists for a system and a method for testing receiver and transmitter links of a high speed SerDes core which eliminates the problems associated with the prior art time, and minimizing the size of associated BIST units. A need further exists for a system and method for providing realistic noise conditions while testing the transmitter and receiver links. Finally, a need exists for a system and method for testing transmitter and receiver links of a high speed SerDes core without causing signal degradation during normal operation or during testing.
USPTO Backgrounds
USPTO Backgrounds