The present invention relates to a semiconductor integrated circuit device and, more particularly, to improvements in a bias supply for digital-to-analog converters and operational amplifiers integrated into a semiconductor chip.
In the field of demodulation as applied to various types of electronic equipment, such as television equipment, stereophonic equipment, etc., multichannel digital-to-analog (D/A) conversion has been required recently in order to increase signal processing efficiency. To meet this requirement, a semiconductor integrated circuit device has been manufactured in which a plurality of D/A converters are integrated into a single semiconductor chip.
To minimize differences in conversion output among the D/A converters, they are each supplied with a bias voltage from a bias circuit. A small change in power supply voltage thus causes different currents in the D/A converters because they are distributed over a single semiconductor chip. As a result, variations may occur in D/A converter output currents, causing errors among channels Therefore, a device is desired which can minimize errors among D/A converter output channels even if the power supply voltage changes slightly.
FIGS. 1, 2 and 3 illustrate a prior art semiconductor integrated circuit device
FIG. 1 is a block diagram of a prior-art current-output-type D/A converter. As shown, the D/A converter is constructed from a decoder circuit 1, a latch circuit 2, a current selecting and outputting circuit 3 and a load resistor RL. The current selecting and outputting circuit 3 comprises a bias voltage generating circuit 3A, a current source group 3B and a switching circuit 3C.
A description will be made of the operation of the device of FIG. 1 on the assumption that it is a 4-bit current-output-type D/A converter. Upon receipt of digital data DIN, the decoder circuit 1 decodes its value. By this decoding process, of the 15 outputs of the decoder, outputs corresponding in number to the value of the digital data DIN are caused to go to a 1 level.
The digital data (selecting signals S) output from the decoder 1 is applied to the latch circuit 2 which is comprised of 15 flip-flop circuits. The outputs of the latch circuit 2 are coupled to the switching circuit 3C of the current selecting and outputting circuit 3.
The bias voltage generating circuit 3A applies a bias voltage v corresponding to an external control signal to the current source group 3B. The current source group 3B has 15 current sources, each for providing a current corresponding to the bias voltage v. The current outputs are applied to the switching circuit 3C.
The switching circuit 3C has 15 switches, whose respective control terminals are connected to the 15 outputs of the latch circuit 2. Each of these switches is turned on or off by the corresponding one of the 15 outputs (i.e., the decoder output) of the latch circuit to control the flow of a current output from the corresponding one of the 15 current sources.
The switch outputs are coupled in common to an end of the resistor RL. The other end of the resistor RL is connected to ground. All the currents flowing through the switches flow through the resistor. Since the output currents of the 15 current sources are of equal magnitude, the amount of current flowing through the resistor RL is proportional to the number of switches which are simultaneously turned on. This number corresponds to the value of the digital data DIN so that the output current of the current selecting and outputting circuit 3 is proportional to the digital data DIN. Conversion of the output current of the D/A converter to a voltage value is accomplished by passing it through the resistor RL, as shown in FIG. 1.
FIG. 2 illustrates an arrangement of the current selecting and outputting circuit 3 for one channel.
As shown, the bias voltage generating circuit 3A is comprised of an operational amplifier OPJ, a bias generating transistor TJ1 and a bias resistor RBJ.
The transistor TJ1 and the biasing resistor RBJ are connected in series between the power supply and ground. When the gate voltage of the transistor TJ1 increases, the potential at the junction between the bias resistor connected to the noninverting input of the operational amplifier OPJ and the drain of the transistor TJ1 decreases and vice versa. That is, the transistor TJ1 and the resistor form an inverting amplifier. The drain of the transistor TJ1 is connected to the noninverting input of the operational amplifier OPJ and the output of the operational amplifier OPJ is connected to the gate of the transistor TJ1. Thus, the operational amplifier OPJ and the transistor TJ1 form a buffer circuit.
Current flowing through the transistor TJ1 all flows through the resistor RBJ and the output ( bias voltage v) of the buffer circuit is applied to the resistor RBJ. Thus, the current flowing through the transistor TJ1 will equal the voltage applied to the inverting input of the operational amplifier OPJ divided by the resistance of the resistor RBJ. The output (bias voltage V) of the operational amplifier serves as a gate voltage which permits the current to flow through the transistor TJ1.
The current source group 3B is constructed from operation setting transistors TJ2 to TJ5, a current mirror circuit comprised of transistors TJ3 and TJ4 and 15 current source transistors TJ61 to TJ615. When the bias voltage v produced by operational amplifier OPJ, bias generating transistor TJ1 and bias resistor RBJ of the bias voltage generating circuit 3A is applied to the operation setting transistor TJ2 of current source group 3B, a bias current ib flows through the transistor TJ2 so that the gate voltage of the transistor TJ5 becomes va. The voltage va is applied to the current source transistors TJ61 to TJ615 as their bias voltages.
The current source transistors TJ61 to TJ615 are selected by the select transistors TK61 to TK615 of the switching circuit 3C so that an output current im is produced. An analog voltage vo is thereby taken at an end of the load resistor RL on the basis of select signals from the latch circuit 2.
With the prior art multichannel D/A converter arrangement described above, the bias voltage v produced by the bias voltage generating circuit 3A is applied in common to the operation setting transistors TJ2 of the current mirror circuits, as illustrated in FIG. 3. Thus, when voltages at power supply points p0, p1, p2, . . . pn of the bias voltage generating circuit 3A and the D/A converters shift subtly under the influence of wiring resistance Rl between the D/A converters, bias currents ib1, ib2, ibn of the current source group 3B may correspondingly shift so that they become different from one another. The differences among the bias currents of the current source group will cause variations in the output currents i1, i2, . . . , in of the D/A converters, thus producing interchannel errors. This will decrease the reliability of a multichannel type of D/A converter in which a plurality of D/A converters are operated by a common bias circuit.
USPTO Backgrounds
USPTO Backgrounds