A rectifier converts a signal from AC to DC, usually using a bridge full-wave rectifier circuit, as is shown in FIG. 1, which gets input from a power transformer and consists of four rectifying diode D1-D4 and loading resistor RL. The four diodes are in bridge configuration, so it's called bridge rectifier, whose operating principle is shown in FIG. 2a and FIG. 2b. D1, D3 are on and D2, D4 are off at positive cycle of AC signal u, current flows from the top terminal of the secondary coil, through D1→RL→D3, back to the bottom terminal of the secondary coil, one half-wave rectified voltage is achieved on RL, as shown in FIG. 2a. D1, D3 are off and D2, D4 are on at negative cycle of AC signal u, current flows from the bottom terminal of the secondary coil, through D2→RL→D4, then back to the top terminal of the secondary coil, the other half-wave rectified voltage is achieved on RL, as shown in FIG. 2b, hence, a full-wave form is achieved on RL, as is shown in FIG. 3. The two diodes that are connected adversely in series withstand the maximum input voltage.
As is shown in FIG. 4, which is a bridge full-wave rectifier circuit that is usually implemented in integrated circuit. It uses 4 MOS transistors T1-T4 to replace the 4 diodes. The gate and drain of T3 and T4 are shorted to form a MOS diode. The operating principle of the rectifier is shown in the following, diode T3, transistor T2 are on and diode T4, transistor T1 are off at positive half cycle of AC signal u, current flows from one terminal of AC signal, S1, through T3→RL→ground→the source and the drain of T2, back to the other terminal of AC signal, S2, one half-wave rectified voltage is achieved on RL, as is shown in FIG. 5a. Diode T3, transistor T2 are off and diode T2, transistor T1 are on at negative half cycle of AC signal u, current flows from S2, through T4→RL→ground→the source and drain of T1, back to S1, the other half-wave rectified voltage is achieved on RL, as is shown in FIG. 5b. Hence, a full-wave form is achieved on RL. The maximum input voltage is imposed on a reverse MOS diode and on the gate of an off-state MOS transistor in the rectifier.
It usually takes low-voltage logic transistors in standard logic CMOS process, the gate oxide of these transistors has two types, one is ultra-thin oxide for core cell, for instance, about 50 angstroms thickness in 0.25 um process, about 30 angstroms thickness in 0.18 um process and about 20 angstroms thickness in 0.13 um process; the other is thick oxide for input/output (I/O) cell, for instance, about 70 angstroms thickness in 3.3v I/O process and about 50 angstroms thickness in 2.5V I/O process.
For example, the thin gate oxide thickness is about 30 angstroms for core cell which use 1.8v process and the thick gate oxide thickness is about 70 angstroms for I/O cell which use 3.3v process in 0.18 um standard logic CMOS process. The voltage resistant capability depends on the oxide thickness, the lifetime of 70 angstroms oxide is 2000-3000 hours at 5V, but few seconds at 10V.
The non-volatile memory integrated in an existing RFID electronic tag or smart card is implemented with EEPROM technology, but considering the minimum feature line width of CMOS logic process is more advanced than that of EEPORM process, CMOS logic process costs less than EEPROM process with the same storage density if the RFID electronic tag or smart card chip was manufactured in standard low voltage logic CMOS process. However, a RFID electronic tag or smart card chip gets inputs for its rectifier by coil coupling, the peak-peak voltage of carrier is more than 10V, so it would affect the rectifier lifetime if so high voltage imposed on a transistor implemented in standard logic CMOS process.
At present, four transistors usually use high-voltage-resistant transistors in RFID electronic tag or smart card chip, whose source and drain is doped with same type low-density impurity one more time to improve the gate-source and the gate-drain breakdown voltage of the MOS transistor when a MOS transistor is formed; or use thicker oxide to improve gate breakdown voltage. It needs additional process complexity, and couldn't make use of advanced standard logic CMOS process in which the transistor oxide thickness and minimum feature line width is constantly decreasing (e.g. 0.18 um, 0.13 um, 90 nm, 65 nm, and so on).
USPTO Backgrounds
USPTO Backgrounds