1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having an impurity region formed by ion implantation with a gate electrode as a mask, and a method of manufacturing thereof.
2. Description of the Background Art
A semiconductor device having a gate electrode is well known. FIG. 6 is a sectional view of a conventional P channel MOS transistor having a gate electrode. Referring to FIG. 6, a conventional P channel MOS transistor comprises an N type silicon substrate 11, an element isolation oxide film 12 formed on N type silicon substrate 11 with a predetermined distance therebetween for element isolation, one pair of p.sup.+ impurity regions 16 formed between element isolation oxide films 12 with a predetermined distance therebetween, and a polycrystal silicon layer 14 formed between the pair of p.sup.+ impurity regions 16 with a gate oxide film 13 thereunder. FIG. 7 is an enlarged sectional view for explaining the crystal structure of the gate electrode of FIG. 6. Referring to FIG. 7, polycrystal silicon layer 14 forming a gate electrode does not have the crystallographic axis of the crystal grains arranged in the same direction. More specifically, polycrystal silicon layer 14 is formed of crystal grains having two different plane orientations (111), (110), for example, as shown in FIG. 7.
FIGS. 8A-8D are sectional views for explaining the method of manufacturing a conventional P channel MOS transistor. Referring to FIG. 8A, an isolation oxide film 12 is formed on an N type silicon substrate 11 using the LOCOS method. Then, a gate oxide film 13 is formed all over the surface. Referring to FIG. 8B, a polycrystal silicon layer 14 having phosphorus doped is formed on gate oxide film 13 by the CVD method. Referring to 8C, gate oxide film 13 and polycrystal silicon layer 14 are selectively etched using a resist pattern (not shown) as a mask to form a gate wiring pattern. Referring to FIG. 8D, ion implantation of B.sup.+ 17 is carried out using polycrystal silicon layer 14 which becomes a gate electrode as a mask. As a result, a p.sup.+ impurity region 16 is formed in self-alignment. Thus, a conventional P channel MOS transistor is formed.
A conventional P channel MOS transistor has p.sup.+ impurity region 16 formed in self-alignment using polycrystal silicon layer 14 which becomes a gate electrode as a mask, as mentioned above.
The crystallographic axis direction of the crystal grains of polycrystal silicon layer 14 comprises a plurality of different crystal orientations. Therefore, there was a problem that B.sup.+ ions pass through polycrystal silicon layer 14 in the B.sup.+ ion implantation process using polycrystal silicon layer 14 of FIG. 8D as a mask. This is called channelling phenomenon, occurring particularly when polycrystal silicon layer 14 forming the gate electrode has a columnar crystal structure whose plane orientation matches the ion implantation angle. Two types of channelling phenomenon are seen; one is where B.sup.+ ions pass through the interior of the crystal grains, and another is where B.sup.+ ions pass through the crystal grain boundary.
In a conventional polycrystal silicon layer 14 which becomes a gate electrode, there are local locations where B.sup.+ ions easily pass through. B.sup.+ ions passing through polycrystal silicon 14 also easily pass through the underlying gate oxide film 13 since gate oxide film 13 is very thin. This means that B.sup.+ ions are implanted into the N.sup.- region beneath gate oxide film 13. The N.sup.- region right beneath gate oxide film 13 is the channel region of the P channel MOS transistor. This local P.sup.+ ion implantation into the channel region will yield the following disadvantages.
A channel is likely to be formed, whereby V.sub.TH rises (the channel cut off voltage rises). The breakdown voltage between the source/drain decreases to induce a problem that the leakage current is increased at the time of channel off. There is also a problem of increase in leakage current and malfunction generation in the entire semiconductor device such as ICs and LSIs. These problems become more significant when elements are reduced in size to comply with increase in integration density of semiconductor devices. This means that reduction in film thickness of polycrystal silicon layer 14 which becomes the gate electrode and reduction in wiring width are required in accordance with miniaturization of elements. This is responsible for the crystal grains of polycrystal silicon layer 14 to become single layered, whereby the number of crystal grains is.-drastically reduced in the direction of the gate width. It is for this reason that B.sup.+ ions easily pass through polycrystal silicon layer 14.
In a conventional P channel MOS transistor where an impurity region is formed by ion implantation using the gate electrode as a mask, it was difficult to effectively prevent ions from passing through locally to the channel region right beneath the gate electrode (channelling phenomenon). This resulted in the problem that the transistor characteristic of the eventually formed MOS transistor is aggravated.
USPTO Backgrounds
USPTO Backgrounds