The micro cooling and power supply structure refers to a structure in which an electron tunneling effect is produced to shift energy to a collector end chip in a chip module comprising an emitter end chip and the collector end chip which is separated from the emitter end chip by an insulation layer. The electron tunneling effect occurs when the emitter electron absorbs energy to break free from its lattice chain, thereby transmitting energy. The electron tunneling effect produces both cooling and power. supplying effects which are applicable to semiconductor devices, mechanical equipment, home appliances, cars, or the aviation industry, so as to achieve highly efficient heat dissipation in a small area or to generate additional electrical power from the exhaust heat in a system.
FIG. 5A illustrates the operating principle of the micro cooling structure, where a power supply is connected to an emitter/collector chip module. With an electromotive force applied by the power supply, electrons are driven to break free from the lattice chain of the emitter end and tunnel through the insulation layer to the collector end where the heat energy is dissipated. This is known as a heat generated micro cooling chip module. In addition, as shown in FIG. 5B, with an external heat source (such as exhaust heat) applied to the emitter end chip, the emitter end electrons having a higher heat energy can break free from the lattice chain and tunnel to the cooler collector end. And by such transmission, a heat generated micro power supply chip is formed to produce an electric current for generating electrical power, so as to supply power to an external electrical system (such as cooling fan).
The above-mentioned insulation layer is generally designed as a vacuum insulation layer based on the low heat conduction characteristics of a vacuum, and the lattice chain refers to the work function of the emitter end chip surface material, that is the energy required to excite electrons above the Femi energy level. Improving the electron tunneling energy, reducing the gap between the two chips, and minimizing the work function of the emitter end chip surface material are the best way to cause the electrons to break free from the lattice chain more easily to produce the electron tunneling effect, thereby improving efficiency in cooling and power generation. FIG. 6 graphs the relationship curves for the chip distance, material work function, operating temperature, drive electric field strength, and the heat dissipation efficiency calculated based on Quantum theory. As can be seen from the graph, when the work function of the emitter end chip surface material decreases with higher operating temperature and narrower chip gap, higher heat energy can be dissipated. That is, better cooling and power generation effects are achieved. But from observing the curves, it can be seen that the heat dissipation efficiency gradually drops if the gap (vacuum insulation layer thickness) between two chips becomes too small. So, a critical bottleneck for such technology is controlling surface planarity and the position of the two chips, such that their vacuum gap is accurately positioned in the nanometer range and an optimal electron tunneling distance is maintained
The most well-developed cooling and power supply structures so far are the cool chips and power chips developed by Borealis Technical Limited in UK. U.S. Pat. No. 6,417,060, as illustrated in FIG. 7A through to FIG. 7E, discloses a monocrystal substrate 50 to serve as an emitter end 55 of the electron tunneling chip module. Then, a metal film 51 (such as PB, Mo, or Ti) is deposited on the substrate 50. Next, a thin copper layer 52 with a 5 μm thickness is deposited as illustrated in FIG. 7C before growing a thick copper layer 53 with 650 μm thickness by an electrochemical method as shown in FIG. 7D which serves as a collector end chip 56 for electron tunneling. The deposited layer is then separated by a heat peeling or mechanical peeling method, while the metal film 51 on the substrate 50 is removed by liquid nitrogen, so that the emitter end and the collector end chips 55, 56 having complementary surfaces are obtained as illustrated in FIG. 7E, in order to minimize the surface planarity problem via the complementary surfaces. However, such a design allows only a fixed gap to be maintained between two chips, but not always the optimal electron tunneling vacuum gap. As the chip is influenced by environmental factors, such as heat expansion and lattice heat-induced vibration at high operating temperatures, the vacuum distance between the two chips may change during operation. And even if the distance changes. by only several nanometers, the cooling and power supply effects can be significantly and often adversely affected (as illustrated in FIG. 6).
Furthermore, this prior art employs a positioning platform to enhance positioning of the vacuum gap between the two chips as illustrated in FIGS. 8A and 8B. FIG. 8B illustrates an elevation view of FIG. 8A, where the collector end chip 56 is moved by four Piczo-electric positioners 60 to carry out nanometer range position adjustments monitored by three inductive position sensors 61, which provide control signals based on current variations. Although distance control for the vacuum gap can be enhanced by such a design, the position of the entire chip is shifted instead of shifting sub-regions of the chip independently as appropriate to achieve maximum efficiency. It appears unlikely that this method can achieve optimal control of vacuum gap distance over the various regions of the chip since environmental factors (such as heat expansion) are difficult to control, or adjust for in actual application. This, then, limits electron tunneling efficiency during the operation. And fabrication cost is increased by this prior art method, making it difficult to be carried out on a mass production scale in the commercial market.
Therefore, it is understood. that the vacuum gap that serves as the electron tunneling path in all the prior arts is minimally adjustable, and the gap value is often difficult to maintain via nanometer positioning at an optimal electron tunneling distance, leading to a decrease in the cooling and power supply efficiency. And if there is a slight error in the chip surface planarity or a change in environmental factors, the electron tunneling effect is reduced significantly. Meanwhile, the higher work function material cannot be adopted to fabricate the emitter end chip. Thus, this poses a big limitation in commercial application.
Summarizing the above, it is an urgent issue in this technology field to design an electron tunneling type. micro cooling and power supply device which minimize the requirement for chip surface planarity while maintaining the nanometer gap of the vacuum insulation layer by optimally spacing the electron tunneling distance to minimize the tunneling potential and the need for low work function material, so as to achieve an excellent cooling and power supply efficiency.
USPTO Backgrounds
USPTO Backgrounds