A memory controller circuit may be used for controlling data transmission between a memory device and an integrated circuit. Types of data transmission include writing data into the memory device or reading data from the memory device. However, the data that is read from the memory device may oftentimes include errors due to multiple factors including: the age of the memory device, transient signal failure within the memory device, or impinging alpha particles causing soft errors in the memory device.
Therefore, the memory controller circuit may include additional circuitry that performs error detection and error correction on the read data. A commonly used error detection/correction method is based on the error-correcting code (ECC) technique.
However, the ECC technique generates multiple parity bits for every data that is written into the memory device. As such, a relatively large amount of memory or storage may be needed to store the generated parity bits. Furthermore, implementing the ECC technique on a memory controller circuit generally requires a large printed circuit board (PCB), which is often not desired in most cost constrained applications. In addition to that, having these additional memory devices may increase power consumption.
USPTO Backgrounds
USPTO Backgrounds