1. Field of the Invention
This invention relates to peripheral processors for digital computers. More particularly, the invention pertains to a peripheral processor interfaced to the address and data bus of a microcomputer and occupying a portion of the memory space of the microcomputer. Specifically, the invention relates to a peripheral processor wherein a host microcomputer periodically loads an array of data into processor memory and the host microcomputer reads back the results from the processor.
2. Description of the Prior Art
The decreasing price/performance ratio for microprocessors and microcomputers is inducing electronic designers to substitute micros for minicomputers and special purpose dedicated hardware. But designers recognize that the computation or execution time for certain serial operations is a limiting factor. It is known, for example, that microprocessors require rather bulky and slow software for performing floating-point arithmetic. Thus, special hardware arithmetic circuits have been designed which are addressed in the same way as an input/output port. The arithmetic unit Am 9511 from AMD Corp., for instance, along with the four fundamental arithmetic operations, has routines for computation of transcendental functions.
Microprocessors and computers are widely used in the field of machine control to perform calculations and Boolean logic, but it is known that the typical byte-oriented machine data words are inefficient for performing Boolean operations on individual bits. Conners, U.S. Pat. No. 4,212,076 issued July 8, 1980, for example, discloses that a Boolean processor for processing any selected bit of any selected word held in memory should be combined with a computer's registers and arithmetic logic unit. The instruction/address register of the computer functions as a bit selection and logic instruction register for the Boolean processor.
In a particular programmable controller, the PC400 manufactured by Giddings & Lewis, Inc. (now Giddings & Lewis, Division of AMCA International, Fond du Lac, Wis.), single bit, on-off type input and output signals were viewed in groups as eight-bit wide words of memory and were addressable by an 6800 microprocessor acting under the address portions of instruction words. Any bit of any byte word could be brought back to the microprocessor on the highest order data line D.sub.7. Moreover, instruction words which contained the operand address included a bit location within the address field to designate whether the selected bit of a selected byte was to be brought back in its true or complement form. Finally, the PC400 permitted output signals to be written to a selected bit of a byte word treated as writable memory, and the address coding designated the particular bit which was to be written to agree with the end result of a Boolean chain sequence. This resulted in "phantom" memory addresses in the PC400.
By "phantom" memory addresses it is meant that data is a single physical location of memory (e.g., the eight storage cells for one byte word) may be read onto the data bus in one form or another by applying one set or another of address signals to the memory address bus. The data which comes back to the central computer will appear as if they are different data held at two separate address locations, but in fact the retrieved data derives in each instance from common data at a single physical location. Phantom memory addressing should be distinguished from the case of the same data and the same physical memory location being read from at least two different memory locations due to "partial decoding." According to the method of partial decoding, address decoding is simplified by testing only those address bits which are needed to differentiate between memory locations actually existing in hardware. This presumes, of course, that the memory capacity of the system is under utilized.
By following the teachings of the Conners patent, chained Boolean processing is efficiently performed, and the many steps in the overall performance of the numerical control system may be made dependent on the results of Boolean sequences. The inputs, for example, are limit switches and other binary condition sensors on a machine, and the outputs are solenoid valves or indicator lamps. Each input or output corresponds to a particular bit or binary variable sensed or manipulated by the Boolean processor. To efficiently design the software or instruction sequence executed by the Boolean processor, each single-bit input and each single-bit output is assigned a distinct memory address. Thus, programmed control of a machine involves the three major steps of (1) receiving single-bit machine inputs which may change from time to time in real time, (2) performing chained Boolean calculations on input single bit data to generate single-bit output data, and (3) transmitting the single-bit machine outputs to the machine's solenoid valves or indicator lamps via appropriate drivers or relays.
Soulsby et al. U.S. Pat. No. 4,078,259 discloses that it may be desirable to have dedicated hardware for sequentially and repetitively performing steps (1) and (3). The input and output image tables are stored in separate memories which are sequentially scanned as data is transferred between the machine inputs and outputs and the respective memories. A microprocessor for performing chained Boolean operations has priority access to the input and output memories, at which time the "scanning in" or the "scanning out" procedure is interrupted. The lowest order bit D.sub.0 of the microprocessor's 8-bit arithmetic logic unit is used as the single-bit Boolean accumulator.
Soulsby et al. uses single-bit input and output memories so that individual input and output bits are assigned different addresses, the addressed single bit being transferred to or from the lowest order data bit D.sub.0. Address line A.sub.13 provides a true/complement function on the addressed bit, thereby providing phantom addressing of a complement image table.
It has also been recognized that it is desirable to sense transitions in single-bit inputs and outputs in order to monitor for malfunctions in a programmable controller. As disclosed in Chance et al. U.S. Pat. No. 3,701,113 issued Oct. 24, 1972, a programmable controller continuously scans single-bit input and output signals and controls the output signals in normal fashion. During each "present scan," however, before each net bit is written into a scanning memory (58), the previous state from the "past scan" is read from the memory (58) for comparison to generate a transition signal when any transition occurs. The transition signal is transmitted to a data processing system separate from the programmable controller and the transition monitor, where the transition signal is recorded and sequentially stored as a transition word identifying the changing element and describing the change. The data processing system compares the sequence of transition words to a reference list in order to identify malfunctions.
It is a general objective of the present invention to reduce the cost of hardware, increase the speed of execution, and enhance the ease of programming for a computer system organized to control machine tools or the like wherein (i) arithmetic operations on quantified variables and (ii) logic manipulations on single-bit, on-off signals, are both to be performed.
More specifically, it is an object of the invention to facilitate the handling and use of single bit, on-off input signals in such a computer system by making it possible for transitions in any particular single bit input signal to be read back to a CPU as a result of the CPU executing what seems to it to be an ordinary memory read cycle.
Stated in different terms, it is an object to provide a scanned data memory to and from which a central processor can rapidly and efficiently transfer single-bit input and output data, and also from which transition information can be read by the central processor.
Another object of the present invention is to provide a scanned data memory in a microcomputer system wherein either selected bits, selected bytes, or the presence of positive or negative transitions in selected bits are addressable and retrieved by read cycles.
Yet another object of the invention is to provide a "memory processor" having a scanned data memory with both present scan memory and past scan memory, and means for performing predefined logical operations upon corresponding present and past scan memory elements during a memory read operation.
Still another object of the present invention is to provide a memory processor of the foregoing type having automatic means for transferring present scan memory data to past scan memory when new present scan data are written to the memory processor.
USPTO Backgrounds
USPTO Backgrounds