1. Field of the Invention
The present invention relates to a semiconductor device structure and memory implementation; and more particularly, relates to a technique for integrating ferroelectric device and metal-oxide-semiconductor (MOS) transistor.
2. Prior Art of the Invention
In general, a MOS transistor uses SiO2 oxide film as gate thin film and the operations of the MOS transistor is controlled by a threshold voltage responding to a gate voltage. On the other hand, a single ferroelectric transistor is under the control of polarization characteristic of a ferroelectric device, using Pb(zr,Ti)O3(PZT), or SrBi2Ta2O9 (SBT), etc. for gate thin film. A non-volatile ferroelectric memory device stores data using hysteresis characteristic between voltage and accumulated electric charge. There are some non-volatile ferroelectric memory devices of which unit memory device is composed of single transistor and single ferroelectric capacitor, or single ferroelectric transistor. FIG. 1 is a graph illustrating the hysteresis characteristic between voltage and electric charge of a normal ferroelectric device. When applied voltage V is xe2x80x9c0Vxe2x80x9d, electric charges Q have two different states C, E. Thus, a ferroelectric device lies in different polarization states, xe2x80x9cthe first statexe2x80x9d or xe2x80x9cthe second statexe2x80x9d. Namely, a polarization state of a ferroelectric device is arranged for a regular direction, then, it lies in xe2x80x9cthe first statexe2x80x9d or xe2x80x9cthe second statexe2x80x9d. FIGS. 2A and 2B are two schematic cross-sectional views illustrating the operation principle of an N-channel single ferroelectric transistor. When a voltage of gate to P-Si is positive(+), electric charges are induced on silicon surface. On the contrary, when a voltage of gate to P-Si is negative(xe2x88x92), any electric charge is not induced. FIG. 3 is a graph illustrating the hysteresis characteristic between drain current and gate voltage of a single ferroelectric transistor. The drain current Id depends on when the gate voltage Vg increases or decreases. Also, FIG. 4a and 4b are schematic circuit diagrams illustrating memory cell arrangement of a ferroelectric memory device having a single ferroelectric transistor, using usual techniques. A plurality of unit memory cells are organized in a matrix type, by crossing a plurality of word line WL1-WLn, a plurality of bit line BL1-BLm and source line SL1-SLn. A unit memory cell is connected between source lines SL1-SLn and bit lines BL1-BLm. Single ferroelectric transistors FM1, FMm, FMn, FMn+m are arranged with connecting gates to word lines WL1-WLn. For programming an arbitrarily selected unit memory cell for xe2x80x9cthe first statexe2x80x9d in a memory cell of the ferroelectric memory device illustrated in FIGS. 4A and 4B, a supply voltage Vdd is applied to the corresponding word line of the unit memory cell and the corresponding bit line, source line and common well line WELL are grounded. In addition, for preventing the other unselected unit memory cells from being programmed for xe2x80x9cthe first statexe2x80x9d, a ground voltage is applied to the corresponding word line and source voltages is applied to source line, bit line and common well line. Here, the write disturb phenomenon is generated in the unselected unit memory cells, when the grounded voltage is applied to the gate of a single ferroelectric transistor and the source voltages are applied to the drain and the common well line. Namely, it is the case that xe2x80x9cthe first statexe2x80x9d is wrongly programmed for the unselected unit memory cell. When the write disturb phenomenon is generated, or when wrong data are programmed for the unselected unit memory, the data are damaged because normal data programmed for xe2x80x9cthe first statexe2x80x9d, for instant, are changed to xe2x80x9cthe second statexe2x80x9d. Also, for programming the selected unit memory cell for xe2x80x9cthe second statexe2x80x9d, the grounded voltage is applied to the corresponding word line and the source voltage is applied to the corresponding bit line, source line and common well line. In this case, since specific memory cell is not able to be selected from a plurality of unit memory cells, a voltage should be applied commonly to the arranged whole ferroelectric transistor.
An object of the present invention is to provide a ferroelectric memory device organized into unit ferroelectric transistors, which can select one unit memory cell and to program it, when the unit memory cell is programmed for xe2x80x9cthe first statexe2x80x9d or xe2x80x9cthe second statexe2x80x9d. An additional object of this invention is to provide a ferroelectric memory device organized into unit ferroelectric transistors, in which there is no Write Disturb phenomenon when a program for the unit memory cell operates.
A ferroelectric memory device in accordance with one aspect of the present invention comprises a plurality of unit memory cells arranged in a matrix type. A plurality of word lines are arranged in column direction and a plurality of bit lines and source lines are arranged in row direction and crossed the plurality of word lines and each memory cell is connected between the source line and the bit line. The unit memory cell comprises a single ferroelectric transistor whose gate is connected to the corresponding word line. The single ferroelectric transistor comprises a well which is coupled to one common well line in row direction and is electrically isolated from common well lines of adjacent different rows. Also, the single ferroelectric transistor comprises a source commonly connected to the bit line or the source line in row direction and comprises a drain commonly connected to the bit line or the source line in row direction.
USPTO Backgrounds
USPTO Backgrounds