The present invention is related to integrated circuit devices and, more particularly, to integrated circuit devices including delay circuits that delay an input signal by a predetermined time.
Signal delay circuits or pulse generating circuits have been used in integrated circuit devices for various purposes, such as signal control. Such signal delay or pulse generating circuits are typically formed using a delay circuit. Generally, the width of a pulse signal is dependant upon a delay time of a delay circuit. Accordingly, it may be important to control the delay time of the delay circuit in order to obtain an accurate pulse width. The delay time may be controlled using a time constant that is determined using the values of one or more resistors and capacitors in the delay circuit. A resistor may be formed of polysilicon, for example, a polysilicon resistor, and a capacitor may be formed using a gate capacitance of a transistor.
The gate capacitance of the transistor is typically dependent upon the thickness of its gate oxide film, thus, possibly making it difficult to freely adjust the capacitance per the unit area. The area occupied by the capacitor in a chip may be relatively large as compared with the area occupied by the resistor. For this reason, gate capacitance is determined so as to ignore parasitic capacitance and the time constant of a delay circuit is adjusted using a resistor whose sheet resistance can be controlled relatively easily and whose chip area is small relative to the chip area of the capacitor.
Unfortunately, since a polysilicon resistor is susceptible to temperature variation, it may be difficult to form a polysilicon resistor that has a constant resistance value as the temperature of the integrated circuit device increases and/or decreases. This variation in the resistance value of a polysilicon resistor caused by the temperature variation may, therefore, introduce inaccuracy into the control signals that are used in integrated circuit devices.
Embodiments of the present invention provide integrated circuit devices including delay circuits having first and second resistive elements electrically coupled in series having first and second resistance values. The first resistance value varies in proportion to temperature and the second resistance value varies in inverse proportion to temperature.
In some embodiments of the present invention, the sum of the first and second resistance values may remain substantially constant as a temperature of the integrated circuit device increases and/or decreases.
In further embodiments of the present invention, the ratio of the first resistance value to the second resistance value is 2:1. In certain embodiments of the present invention, a change ratio of a resistance rate of change of the first resistive element to a resistance rate of change of the second resistive element is 1:2. The first and second resistive elements may include first and second resistors.
In still further embodiments of the present invention, the integrated circuit device may be an integrated circuit memory device. In certain embodiments, the memory device may include a flash memory device, the first resistive element may comprise a floating gate of the flash memory device that includes lightly doped polysilicon and the second resistive element may comprises a control gate of the flash memory device that includes highly doped polysilicon. The lightly doped polysilicon may have an impurity concentration of from about 1xc3x971016 to about 1xc3x971018 and the highly doped polysilicon may have an impurity concentration of about 1xc3x971020.
USPTO Backgrounds
USPTO Backgrounds