1. Field of the Invention
The present invention relates to a semiconductor device and method of manufacturing the same.
2. Description of the Related Art
In recent years, with progress in digital technologies, development work has heretofore been made to provide non-volatile memories that can store large volumes of data at high speeds.
As such non-volatile memories, a flush memory and ferroelectric memory have heretofore been known in the art.
Of these, the flush memory includes a floating gate, embedded in a gate insulating film of an insulation gate type field effect transistor (IGFET), wherein information is stored by accumulating electric charges in the floating gate. However, with such a flush memory, a drawback is encountered in that during writing and erasing information, a tunnel current must be passed through the gate insulating film and a relatively high voltage needs to be supplied.
In contrast, the ferroelectric memory is also referred to as FeRAM (Ferroelectric Random Access Memory) that stores information upon utilizing a hysteres is characteristic of a ferroelectric film incorporated in a ferroelectric capacitor. In the ferroelectric film, polarization takes place depending on a voltage applied across upper and lower electrodes of the capacitor, and spontaneous polarization remains even if the voltage is removed. As a polarity of the applied voltage is inversed, the spontaneous polarization is also inverted. Information is written in the ferroelectric film by relating the direction of the spontaneous polarization to “0” and “1”. The FeRAM is advantageous in that the voltage necessary for writing is lower than that needed in the flush memory and writing can be accomplished at a faster speed than that in the flush memory.
To take such an advantage, a study has been made to apply a logic embedded chip (SOC: System on Chip), composed of a combination of logic circuits and FeRAM, to an IC card.
By the way, due to compatibility between an upper electrode and a ferroelectric film constituting a ferroelectric capacitor, a ferroelectric characteristic of the ferroelectric capacitor significantly depends on a structure of the upper electrode.
For instance, in Patent Literature 1, the upper electrode has an SRO (SrRuO3) film that is covered with a platinum film, which suppresses the occurrence of mutual reaction between the SRO film and oxide silicon.
Further, in Patent Literature 2, an upper electrode includes an iridium oxide film, an iridium film and a platinum film that are formed in this order. Forming the iridium oxide film as the lowermost layer of the upper electrode allows a capacitor to have an improved fatigue characteristic and, further, the presence of the platinum film on the uppermost layer results in reduction in contact resistance between the upper electrode and a wiring. Also, the presence of the intermediate iridium film results in improved adhesion property between the iridium oxide film and the platinum film.
In the meanwhile, Patent Literature 3 discloses an upper electrode including an iridium oxide film and an iridium film that are formed in this order.
Further, Patent Literature 4 discloses an upper electrode with a structure having a single layer film or a stacked film made of materials such as noble metals including platinum, iridium, etc., and an oxide conductive film such as oxide iridium (IrOx), SRO, oxide platinum (PtO), etc.
Furthermore, Patent Literature 5 discloses an oxide iridium film, a platinum film or an SRO film that are formed as an upper electrode.                [Patent Literature 1] Japanese Patent Laid-Open Publication No. H11-195768        [Patent Literature 2] Japanese Patent Laid-Open Publication No. 2000-91539        [Patent Literature 3] Japanese Patent Laid-Open Publication No. 2000-173999        [Patent Literature 4] Japanese Patent Laid-Open Publication No. 2003-258201        [Patent Literature 5] Japanese Patent Laid-Open Publication No. 2003-152165        
USPTO Backgrounds
USPTO Backgrounds