1. Field
Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a method for fabricating a semiconductor device with buried gates (BG).
2. Description of the Related Art
As the size of semiconductor devices becomes smaller, it becomes more difficult for the semiconductor devices to have diverse device properties and fabricate such the semiconductor devices. In particular, under the design rule of 40 nm or less, the semiconductor device reaches the technical limitations in forming a gate structure, a bit line structure, and/or a contact structure. Even if the structure is formed, desired device properties may not be obtained. Therefore, the technology of forming buried gates (BG) by burying gates in a substrate is being developed.
FIGS. 1A to 1C are cross-sectional views illustrating a method for fabricating a conventional semiconductor device including buried gates.
Referring to FIG. 1A, a hard mask pattern 12 including a pad oxide layer 12A and a hard mask polysilicon layer 12B stacked therein is formed over a substrate 11, and an isolation layer 13 for defining an active region 14 is formed using the hard mask pattern 12.
Referring to FIG. 1B, after the hard mask pattern 12 is removed, a cleaning process is performed. Subsequently, a conductive layer 15 for forming landing plugs is deposited over a groove from which the hard mask pattern 12 removed, and a planarization process is performed until the surface of the isolation layer 13 is exposed.
Referring to FIG. 1C, trenches 16 are formed by selectively etching the conductive layer 15, the active region 14, and the isolation layer 13, and at the same time, landing plugs 15A are formed. Buried gates are formed by sequentially forming a gate insulation layer (not shown) on the surface of the trenches 16, forming a gate electrode 17 that fills a portion of each trench 16, and a sealing layer 18 that fills the other portion of each trench 16.
Subsequently, an inter-layer dielectric layer 19 is formed over the substrate 11, and then storage node contact plugs 22, that is in contact with the landing plugs 15A by penetrating through the inter-layer dielectric layer 19, and bit lines 25, that are in contact with the landing plugs 15A and are buried in the inter-layer dielectric layer 19, are formed. In the drawing, the reference numeral 21 denotes storage node contact holes, and the reference numeral ‘23’ denotes a damascene pattern. The reference numeral ‘24’ denotes bit line spacers, and the reference numeral ‘26’ denotes a sealing layer.
However, since the landing plugs 15A are formed before the bit lines 25 and the storage node contact plugs 22 are formed in the conventional semiconductor device, the landing plugs 15A may be lost in the course of forming the damascene pattern 23 and the storage node contact holes 21, thus increasing contact resistance.
Also, when the storage node contact holes 21 are formed, the landing plugs 15A are lost and thus a short circuit may occur between the storage node contact plugs 22 of the active region 14 and other active regions adjacent to the active region 14 in the longitudinal direction. This occurs because the conductive layer 15 for forming landing plugs fills the groove from which the hard mask pattern 12 is removed. To be specific, the height of the landing plugs 15A is decided based on the height H1 or H2 of the isolation layer 13 protruding from the substrate 11, and the isolation layer 13 protruding from the substrate 11 is lost during the removal process of the hard mask pattern 12, the cleaning process, and the planarization process that are carried out before the landing plugs 15A are formed, and as a result, the height of the isolation layer 13 is decreased (H1→H2).
The decrease in the height of the landing plugs 15A is caused by the loss of the isolation layer 13 and may be prevented by increasing the thickness of the hard mask pattern 12 in consideration of the height of the isolation layer 13 that is lost in the course of forming the conductive layer 15 for forming landing plugs. However, when the thickness of the hard mask pattern 12 is increased, the level of the process difficulty in forming isolation trenches for the isolation layer 13 is increased and at the same time process margin is decreased as well. Moreover, since the height of the active region 14 including the hard mask pattern 12 is increased when the isolation trenches are formed, the active region 14 may lean/slant.
USPTO Backgrounds
USPTO Backgrounds