The invention relates generally to methods for monitoring and controlling processes used in forming features on patterned substrates, such as semiconductor substrates. More specifically, the invention relates to a method for detecting an endpoint in a recess etch process.
Recess etch processes are used in fabricating semiconductor devices such as dynamic random access memory (DRAM) and embedded DRAM (eDRAM). DRAMs and eDRAMs store information in integrated circuits that contain capacitors. FIG. 1A shows a typical storage node 100 of a DRAM cell. The storage node 100 includes a deep trench 102 formed in a patterned semiconductor substrate 104. A column of polysilicon 106 is formed in the deep trench 102, and a recess 108 is provided above the column of polysilicon 106. The recess 108 may be lined with an insulation material (not shown) so as to isolate the polysilicon 106 from structures, such as transfer devices, above. The trench 102 typically has a high aspect ratio. In the current technology, for example, the depth of the trench 102 is typically several microns deep, while the width of the trench 102 is typically on the order of 300 nm. As advances are made in integration technology, the width of the trench is expected to get even smaller, e.g., shrink down to 90-100 nm.
FIG. 1B shows the semiconductor substrate 104 prior to forming the deep trench (102 in FIG. 1A). In a typical configuration, the semiconductor substrate 104 includes a substrate layer 110, typically made of silicon, a dielectric layer 112, typically made of silicon dioxide, and a mask layer 114, typically made of silicon nitride. The semiconductor substrate 104 is coated with a thin-film of photoresist mask 116. Before forming the trench, an area 115 of the photoresist mask 116 where the trench will be formed is removed, causing the underlying layers to become exposed. The semiconductor substrate 104 is then placed in a process chamber (not shown), such as a plasma chamber, and the trench is etched through the exposed underlying layers and into the substrate. After etching the trench, the remaining photoresist mask 116 is removed.
FIG. 1C shows the semiconductor substrate 104 after etching the trench 102 and removing the photoresist mask (116 in FIG. 1B). In the figure, the trench 102 is filled with polysilicon 106. As the trench 102 is filled with polysilicon, a blanket of polysilicon 120 is also formed on the top surface of the semiconductor substrate 104, i.e., over the mask layer 114. Typically, a small dish (or depression) 122 also appears above the opening of the trench 102 as a consequence of the filling process. To facilitate etching of a recess in the column of polysilicon 106 in the trench 102, the blanket of polysilicon 120 is then removed (or planarized), as shown in FIG. 1D. The planarized surface 123 can be produced by a process such as planar layer etching or chemical-mechanical polishing. It should be noted that all or only a portion of the blanket of polysilicon (120 in FIG. 1C) may be removed during the planarization process. After planarizing the blanket of polysilicon, the column of polysilicon 106 in the trench 102 is etched down to a predetermined depth to form the recess (108 in FIG. 1A).
Various modifications can be made to the sequence of processes described above to form different recess structures. For example, as shown in FIG. 1E, the trench 102 can be initially lined with a dielectric material 124, such as an oxide. Polysilicon 106 can then be deposited into the lined trench 102 and on top of the mask layer 114, as previously described. The blanket of polysilicon 120 on the mask layer 114 can be planarized, and the column of polysilicon 106 can be etched down to form a lined recess (126 in FIG. 1F). This process may be used to create a buried polysilicon strap, for example. In another example, as shown in FIG. 1G, the column of polysilicon 106 in the trench 102 can be etched to form a recess 128. The recess 128 can then be filled with a dielectric material 130, such as an oxide. Another etching process can be used to remove a portion of the dielectric material 130 so as to form a dielectric liner (132 in FIG. 1H) that extends partly down the trench 102.
In most applications, the depth of the recess relative to a reference point in the semiconductor substrate, such as the bottom of the sacrificial mask layer, is a critical dimension. Thus, the ability to accurately determine how far down to etch the column of polysilicon in the trench to achieve the desired recess depth is very important. Various factors make it challenging to form a recess of a desired depth in the trench. For example, the opening of the trench through which the recess will be etched is very tiny, and the scale of the depression above the column of polysilicon in the trench can easily be on the same order as the accuracy or even the absolute depth of the recess to be etched. Perhaps even more challenging are the incoming material variations from one substrate to another, e.g., the variations in the thickness of the mask layer and the depth of the depression above the column of polysilicon in the trench. Without knowing these variations, it would be difficult to accurately determine how far down to etch the column of polysilicon to make the required recess depth.
What is desired therefore is a method for detecting an endpoint in a recess etch process by monitoring the absolute recess depth that takes into account such factors as incoming material variations.
USPTO Backgrounds
USPTO Backgrounds