1. Field of the Invention
The present invention relates to semiconductor capacitors and, more particularly, to a semiconductor capacitor with large area plates and a small footprint that is formed with shadow masks and only two lithography steps.
2. Description of the Related Art
A semiconductor capacitor is a well-known structure that typically includes two metal plates that are vertically separated by a dielectric layer. Semiconductor capacitors are commonly formed as part of the metal interconnect structure, which allows the capacitors to be formed without requiring any additional lithography steps.
For example, the lower capacitor plate can be formed at the same time that a first metal layer is etched to form a first layer of metal traces, while the upper capacitor plate can be formed at the same time that a second metal layer is etched to form a second layer of metal traces. In this case, the interlayer dielectric that electrically isolates the first layer of metal traces from the second layer of metal traces functions as the capacitor dielectric.
Although a capacitor which is formed as part of the metal interconnect structure does not require any additional lithography steps, and thus comes for free, the capacitance of the capacitor is limited by the available area and the requirements of the metal interconnect structure. In other words, the area that can be occupied by a capacitor, the vertical spacing between the first and second layers of metal traces, and the material used as the interlayer dielectric are defined by the requirements of the metal interconnect structure, not by the requirements of the capacitor.
When not defined by the requirements of the metal interconnect structure, the capacitance provided by a capacitor can be increased by utilizing different dielectric materials, such as high k materials. In addition, the capacitance can be increased by increasing the area of the plates. One common approach to forming a capacitor with large area plates and a small footprint is to form plates that conformally line an opening anisotropically dry etched in the substrate.
Another common approach to forming a capacitor with large area plates and a small footprint is to use a number of small area interleaved plates, where each odd numbered plate is connected together to form a first capacitor plate, and each even number plate is connected together to form a second capacitor plate. Thus, even though the area of each plate is small, the effective areas of the first and second capacitor plates are much larger. A further approach is to form a number of interleaved plates in an opening anisotropically dry etched in the substrate.
These approaches to increasing the capacitance provided by a capacitor, however, typically require a large number of lithography steps. Lithography, in turn, is one of the most expensive steps in a semiconductor fabrication process. In addition, when capacitor plates are formed to conformally line an opening anisotropically dry etched in the substrate, the materials deposited to form the capacitor tend to have a non-uniform thickness, and be very thin at the bottom corners of the opening where the bottom surface and the vertical side wall of the opening meet. As a result, these capacitors tend to have a higher defect rate.
Thus, there is a need for a capacitor with large area plates and a small footprint that is formed with a limited number of lithography steps.
USPTO Backgrounds
USPTO Backgrounds