This invention relates in general to the field of radio communications and more specifically to a method and apparatus employing a decimation filter for down conversion in a receiver.
In all digital receiver architectures, the final output has to be a baseband signal in the digital domain. To get this baseband signal there are a few receiver architectures to choose from. Each of these receiver architectures has some advantages and disadvantages. It is worth noting here that for ease of discussion that only one of the paths (I or Q) are shown in FIGS. 1, 2, 3 and 5.
One of the most commonly used receiver architectures is the heterodyne receiver as shown in FIG. 1. The heterodyne receiver uses two mixers 108, 114 to down convert the RF signal 102 to baseband followed by an analog-to-digital converter (ADC) 118 to convert the signal to the digital domain. A low pass filter (LPF) 116 provides filtering of the second mixer""s output signal prior to presentation to the ADC 118. The ADC 118 receives a sampling frequency signal 122 which is equal to or greater than two times the desired bandwidth (i.e., Fsamplexe2x89xa72*B.W.).
Also included as part of the heterodyne receiver shown in FIG. 1, is a conventional front-end filter 104 and a low noise amplifier (LNA) 106. Together the filter 104 and LNA 106 provide front-end filtering and amplification to the RF signal 102 prior to introducing the RF signal to the first mixer 108. A second filter 110 and automatic gain control (AGC) circuit 112 provide further filtering and gain control to the first IF signal prior to providing the IF signal to the second mixer 114 for down conversion. A digital decimation filter 120 decimates the digital signal in order to reduce the data rate. Heterodyne receivers, like that shown in FIG. 1 are very robust and have very good performance characteristics. However, the heterodyne receiver uses many components, and therefore requires a large amount of silicon die space to manufacture.
A second receiver architecture that is used frequently is the direct conversion receiver as shown in FIG. 2. The direct conversion receiver uses only one level mixer 508 to down convert the RF signal 202 to base-band followed by an AGC 212 and an ADC 214 to convert the signal into the digital domain. A decimating filter 216 decimates the digital signal as required. The ADC 214 and decimating filter 216 are provided a sampling frequency signal 218 having a frequency equal to or greater than two times the desired bandwidth (Fsamplexe2x89xa72*B.W.). Direct conversion receivers have very simple architectures so they tend to save space, cost and power consumption. However, they suffer from DC offset problems, large even order distortion, flicker noise, and LO leakage.
A third well known receiver architecture is a compromise between the heterodyne and the direct conversion receiver, where the RF signal 302 is down converted by an (local oscillator) LO using mixer 308 to a low IF frequency. This signal is then filtered and amplified through a filter 310 and automatic gain control circuit (AGC) 312 combination. The signal is then digitized through an ADC 314 operating at a sampling frequency that is a multiple (e.g., 4) of the IF frequency. At this point the signal is in the digital domain, but still centered in frequency around the IF frequency and has a data rate equal to the sampling frequency signal 320, Fsample=4*IF. A digital mixer 316 is used to down convert the digital signal to baseband. The choice of Fsample=4*IF, is very useful since the digital mixer 316 is simplified to a multiplication process with coefficients of 1, 0, xe2x88x921, 0, etc. This result of the multiplication operation is shown in FIG. 4.
Note that the 1, 0, xe2x88x921, 0 coefficients act as a second LO of frequency equal to the IF. The result is that the signal is down converted in the digital domain to baseband but still has a data rate equal to Fsample. To reduce the data rate, a decimation filter 318 is needed. The receiver architecture of FIG. 3 still requires a second mixer 316, but this mixer is in the digital domain, so its distortion and noise are not as critical as in the heterodyne receiver architecture. Given the above examples of prior art receiver architectures, it would be beneficial to have a receiver architecture that eliminates the need for a second mixer in the receiver in order to down convert the IF frequency to base band. By eliminating the second mixer, its associated noise, distortion and power consumption are also eliminated.
USPTO Backgrounds
USPTO Backgrounds