1. Technical Field
The present application relates generally to an improved data processing system and method. More specifically, the present application is directed to a system and method for asynchronous clock modeling in an integrated circuit simulation.
2. Description of Related Art
Electronic design automation (EDA) is now commonly used in the design of integrated circuits. EDA makes extensive use of computers to automate the design process. Once a circuit has been designed and physically laid out, extensive testing is performed to verify that the new design and layout will work as desired. Testing of the new design is typically performed by simulating the design using a computer, which permits relatively fast verification of the circuit without necessitating physically placing the design in silicon.
Static analysis and dynamic simulation are two primary conventional methods employed to analyze and verify circuit behaviors of a design. Dynamic simulation provides a relatively close approximation of actual operation of a circuit design but requires extensive time and resources to perform. Static analysis requires less time and resources to perform, but has limitations with regard to the information that may be obtained.
A major problem exists in current dynamic simulation of integrated circuits in that all clocks of the integrated circuit simulation, even those which are asynchronous with respect to one another, appear to be synchronous during simulation. Thus, the simulation does not adequately represent the actual operation of the integrated circuit device when it is fabricated in hardware.
In hardware, clocks of the integrated circuit device rarely operate in a completely synchronous manner. To the contrary, asynchronous clocking of the logic is much more frequent in integrated circuits. Thus, while in simulation different independently driven clock logic is modeled as being in phase with one another, the clock logic of the actual hardware that is generated based on the integrated circuit device will typically go out of phase during operation.
The synchronous behavior of clocks which are supposed to be asynchronous with one another occurs because clocks do not walk through the logic of the integrated circuit design in an asynchronous manner with respect to one another in simulation unless they are made to do so. This means that one or all of the clocks in the integrated circuit simulation must be generated externally from the integrated circuit model, e.g., via code driving the simulation or by externally manipulating the clock signals of the integrated circuit simulation.
While external control of the clocks may allow one to force an asynchronous operation within the simulation, there currently is no mechanism that allows one to limit the asynchronous clock phases to phase differences of interest. To explain this further, it should be kept in mind that clock skewing is typically used in conjunction with data skewing at asynchronous crossing. For example, assume that random propagation delays are inserted across an asynchronous boundary crossing. Assume, for example, that the clock period of the send side of the asynchronous boundary is 10 simulation cycles and the clock period of the receive side of the asynchronous boundary is 1000 simulation cycles. Further assume that the minimum latency of signals is 0 and the maximum latency of signals is 2 simulation cycles across the asynchronous boundary.
With the above assumptions, one will have a 2 (maximum latency-minimum latency) in 1000 (receive side's clock period) chance of capturing a data skewed value in the receive side's clock domain during simulation. In other words, if a test of the integrated circuit device requires 1000 simulation or clock cycles to complete, the chance of capturing a data skewed value within the test period is only 0.2 percent. Hence, if data capture is performed at particular points during the test, there is only a 0.2 percent chance that the data capture will capture a skewed data value. This problem is made even greater when the test of the integrated circuit device requires a larger number of clock or simulation cycles to complete.
Thus, with the known systems for testing the operation of integrated circuit designs, either the clocks of the integrated circuit design are synchronous, their phase difference is static, or if there is a non-static phase difference, the testing allows the phase difference to drift out of a range of interest thereby reducing the chance of capturing a data skewed value within the testing period.
USPTO Backgrounds
USPTO Backgrounds