1. Field of the Invention
The present invention relates to integrated circuits having arrays of digital logic gates, and more specifically to a structure and method for producing mask-interconnected integrated circuit substitutes for user-configured logic arrays.
2. Description of the Prior Art
U.S. Pat. No. 5,068,603 issued Nov. 26, 1991 to John E. Mahoney and assigned to Xilinx, Inc. (incorporated herein by reference) discloses (see Abstract) a particular structure and method for producing mask-configured integrated circuits which are pin compatible substitutes for user-configured logic arrays. Scan testing networks are formed in the mask-configured substitutes to test the operability of logical function blocks formed on such chips. What is variously called "hard-wired interconnection", "metal interconnection" or "mask-configured interconnection" for integrated circuit chips uses the fixed layout of various conductive paths in the integrated circuit that are either diffused in the substrate or patterned in metal layers on the substrate to interconnect input and output terminals of logic gates one to the next. The mask-configured interconnection is associated for instance with standard gate arrays.
This is in contrast to the alternate approach for interconnecting such logic gates described variously as "soft wiring", "soft configured interconnection" or "user-configured interconnection". This user-configured interconnection is associated with field programmable gate arrays (FPGA). The above-referenced patent discloses a method eliminating the need for simulation when transferring a particular logic design from a user-configured interconnection to a mask-configured interconnection, because functional compatibility is guaranteed by the absence of any logic transformation; a configurable logic block ("CLB") in the field programmable gate array is replicated by a group of logic gates in the gate array. (Various names are used by different FPGA vendors for the CLB. Altera calls it a Logic Array Block (LAB) in their FLEX family; AT&T calls it a Programmable Logic Cell (PLC) in their ORCA family.)
A logic block is a large number of predesigned logical gates of a particular configuration which is replicated in a number of such blocks on one chip. Xilinx logic blocks include one or two combinational function generators and one or two flip flops with programmable means for selecting the combinational function to be implemented and for routing signals into the logic block, to and from the function generators and flip flops and out of the logic block. The designation "configurable logic blocks" is used because the user may determine the configuration of the logic blocks in the FPGA. In the above-referenced patent, for synchronous paths, the timing compatibility of the gate array to the original FPGA is guaranteed by the timing of the logic blocks in the gate array being identical to that of the configurable logic blocks in the FPGA. All routing delays between logic gates are proportionally shorter in the gate array than in the FPGA. Thus, the gate array implements logic the same way the FPGA does. That is, the gate array essentially replaces the programmable elements (pass transistors) of the FPGA with metal contacts using a single masked-defined metallization layer. For some asynchronous paths, the gate array equivalent may be incompatible with the FPGA version, in which case the path and its logic elements must be redesigned before the gate array can be completed. For each and every CLB in the user-configured design (whether used or not) there exists a corresponding logic block in the mask-configured gate array circuit.
Additionally, the method of fabricating gate arrays described in the above-referenced patent provides 100% fault coverage by a test block associated with each (1) function generator in each logic block, and (2) with each flip-flop output in each logic block. This allows each function generator and flip-flop to be exhaustibly tested in isolation. The test blocks are also referred to as a "scan chain".
In contrast, other prior art methods for substituting a mask-configured chip for a user-configurable chip map the circuit of the user-configurable chip design into the mask-configured chip design, so that the arrangement of circuit elements (logic gates) is substantially altered in the process. This typically requires several mask-configured metallization (interconnect) layers in the mask-configured chip. (Mapping is the process of taking an FPGA logic function and synthesizing it as an interconnection of logic gates such as NAND, NOR, INV etc. for a gate array.) These other prior art methods are more economical in use of chip real estate than is the approach of the above-referenced patent, but require logic and timing simulation of the mask-configured chip design to ensure functionality.
As has been recognized by the present inventors, the 100% replication of each FPGA logic gate in the approach of the above-referenced patent requires the use of extra real estate on the gate array, and so wastes gates in the gate array. This one-to-one match of CLB's (and also input/output blocks) of the FPGA to logic in the gate array takes place even though typical designs use anywhere from 60% to 100% of the logic blocks in the FPGA.
Similarly, the provision of 100% test block coverage in the above-referenced patent has been recognized by the present inventors as consuming substantial extra area on the gate array.
Additionally, the above-referenced patent requires a custom base integrated circuit gate array that is specially designed (at substantial expense) to be configured by a single interconnect layer and which is usable only with one member of an FPGA device family, and for which a new gate array must be provided for each new FPGA architecture.
Thus disadvantageously the method of the above-referenced patent requires excessive chip area in the mask-configured chip to replicate the functions in the user-configured design. A substantial cost saving would result if chip real estate could be reduced, by replacing the user-configured design with a gate array (mask-configured) design with a smaller number of gates than that of the gate array of the above-referenced patent. Further, it would be desirable to do so without the need for logic and timing simulation as in other prior art methods using mapping. Also, it would be advantageous to eliminate the need for a unique base gate array (configured by a single interconnect mask) for each member of an FPGA device family.
USPTO Backgrounds
USPTO Backgrounds