a. Field of the Invention
The present invention is concerned with a junction field effect transistor of a vertical type, especially it relates to an improved method of forming the gate region of the junction field effect transistor of a vertical type.
B. Description of the Prior Art
Researches are being conducted animatedly of late in general on the so-called vertical-type junction field effect transistors exhibiting an unsaturated characteristic (drain voltage versus drain current characteristic) resembling the characteristic of a triode vacuum tube. Under such situation, there have recently been proposed such junction field effect transistors (the words "Field effect tansistor" will hereinafter be abbreviated as FET) of a vertical Type as shown in FIG. 1 and such junction FET of a vertical type as shown in FIG. 2.
The known junction FET of a vertical type having an embedded gate construction as shown in FIG. 1 is prepared by the steps of: selectively difussing, for example, a highly concentrated P-type impurity into the drain region 10 made of an N-type semiconductor of a low impurity concentration from one surface thereof, to form a gate region 11 composed of grids; then forming, on top of the drain region 10 by a chemical vapor-deposition (growth) technique, a source region 12 composed of an N-type semiconductor of an impurity concentration not lower than that of the drain region 10 in such manner that this gate region 11 is substantially embedded between the drain region 10 and the source regions 12; and thereafter forming, on top of a gate region 11' by an etching technique or thermal diffusion technique, a gate electrode lead-out layer 14 of a low resistance connected to that gate region 11'.
Such a known junction FET of a vertical type having an embedded gate formation, however, has several problems that have to be solved. The gate region 11 is formed by diffusing, through the apertures of a mask, a required impurity into the drain region 10. However, this impurity spreads in horizontal as well as vertical directions through said apertures. This spreading of the impurity could result in an increase in the width as well as the depth of the gate grid 11. As a result, there arises the inconveniences that the respective channels 13 between the respective gate grids 11 are undesirably closed, and that the area of P-N junction between the gate region 11 and the source region 12 is increased, causing the junction capacitance to increase and also causing the upper limit level of the operating frequency or cut off frequency to become lowered. On the other hand, in order to heighten this upper limit level of the operating frequency, it is necessary to sufficiently enhance the impurity concentration of the gate grid 11 and thereby to reduce the series resistance at the gate region. In view of the nature of the diffusion technique which is applied, however, the local maximum impurity concentration of the gate region 11 tends to become markedly high when it is intended to elevate the mean impurity concentration. Therefore, crystal defect is apt to develop at the intersurface between the drain region 10 and the source region 12 which is formed on top of this drain region 10, especially at the sites adjacent to the gate regions 11. This development of crystal defect, in turn, increases reverse leakage and brings about a degradation of the breakdown voltage property.
Still further, the construction of the conventional junction FET of FIG. 1 having such an embedded gate structure as described above requires mask-forming steps of ordinarily more than five (5) stages, and therefore a considerable length of time is needed for the manufacture of such FET.
On the other hand, the known junction FET of a vertical type shown in FIG. 2 is prepared by a selective local oxidization of the surface of, for example, an N-type semiconductor substrate 20; then forming grooves at the oxidized site by digging down this site through an etching technique; thereafter forming a gate region 21 by diffusing a P-type impurity into the inner circumferential surfaces of these dug-out grooves; then oxidizing the resulting surfaces of the grooves to provide an oxidized region 22 while causing those portions of the diffused impurity located close to the surface of the substrate 20 to be absorbed substantially into the second-occurring oxidized region 22 to define a source region 23 between the respective oxidized regions 22; finally forming a gate electrode lead-out layer 24 to be connected to a desired gate region 21' formed for the sake of the gate electrode.
However, the known junction FET of vertical type having the gate region formed by digging down as shown in FIG. 2 also has several drawbacks to be solved. More particularly, since the gate region 21 is formed by "digging", this gate region 21 is located relatively close to the source electrode 23a which is provided on top of both source region 23 and the oxidized region 22. Accordingly, the produced FET has a low breakdown voltage property. Also, in the event that the aforesaid absorption of those portions of the impurity diffused into the dug-out groove which are located close to the surface of the source region 23 is not perfectly carried out, there will arise the inconvenience that the gate region 21 may locally contact the source electrode 23a, resulting in a contribution to the degradation of the breakdown voltage. Furthermore, in order to form such a junction FET having the dug-out gate formation as described above, there are required at least two manufacturing steps, i.e., selective oxidization and etching steps, causing the manufacturing process as a whole to become considerably complicated.
USPTO Backgrounds
USPTO Backgrounds