1. Field of the Invention
The present invention relates to a digital demodulator such as a grand alliance (GA) type HDTV (High Definition Television) receiving unit, and in particular, to an improved digital demodulator which is capable of simplifying an application specific integrated circuit (ASIC) of a demodulator using a combined sampling technique.
2. Description of the Conventional Art
As shown in FIG. 1, the GA type HDTV receiving unit includes an IF output unit 10 for outputting an IF (Intermediate Frequency) signal based on a signal received from an antenna 1, a carrier wave demodulator 20 for performing a carrier wave demodulation with respect to an output signal from the IF output unit, and an output unit 30 for performing a segment/field synchronization, a timing recovery, and a channel equalization with respect to an output signal from the carrier wave demodulator.
The operation of the GA type HDTV receiving unit will now be explained with reference to the accompanying drawings.
First, the signal received through the antenna 1 is converted into an IF signal by a first local oscillator 12 of a tuner 11, and a frequency drifter or variation are compensated by a second local oscillator 28 which is a voltage controlled oscillator. The second local oscillator 28 is controlled by a frequency and phase compensation loop.
In addition, the output signal from the tuner 11 passes through a SAW (Surface ascoutic wave) filter 13, thus minimizing the noise effect of a surrounding channel, and the output signal from the SAW filter 13 is amplified by a low noise intermediate frequency amplifier 14 and is inputted into mixers 21 and 22, respectively.
A mixer 21 detects an I-signal component by multiplying the output signal from the low noise intermediate frequency amplifier 14 and a cosine value of the oscillating frequency of a third local oscillator 23 of the fixed frequency, and a mixer 22 detects a Q-signal component by multiplying the output signal from the low noise intermediate frequency amplifier 14 and a sine value of the oscillating frequency of the third local oscillator 23.
Since the GA type HDTV receiving unit adapts a VSB (Vestigial Sideband) modulation method, an I-signal component is sued for processing data. However, for obtaining a frequency, the I-signal component and Q-signal component are all needed.
The AFC low pass filter 24 operates by the frequency difference between a pilot signal and the second local oscillator 28 before the synchronization of the phase is implemented like the channel of the television receiving unit is changed.
Here, the high frequency components such as a noise or an interference excluding the pilot signal are eliminated.
The pilot signal is limited by the limiter 25 having a value of .+-.1 and is multiplied by the Q-signal by the mixer 26. Therefore, it is possible to obtain an AFC characteristic curve having a typical S-curve.
The polarity of the S-curve error signal is determined depending whether it is higher or lower than the frequency input IF signal from the second local oscillator 28.
The signal DCed by the limiter 25 is rectified by the APC low band pass filter 27 and controls the second local oscillator 28 for reducing the frequency error.
When the frequency error becomes closer to the value of 0, the input IF signal from the carrier wave demodulator 20 and the third local oscillator 23 are phase-synchronized.
When the phases are synchronized, the pilot signal having a value of .+-.1 is inputted into the mixer 26.
In addition, the I-signal in which the pilot signal is detected is converted into the digital data by the A/D (Analog/digital) converter 31.
A segment synchronous detector 32 obtains a synchronous value based on the repeated segment data existing in the receiving data, and obtains a symbol clock of 10.76 MHz which is properly synchronized by the PLL 33.
An automatic gain controller 34 outputs an AGC signal which is capable of controlling the size using the low noise intermediate frequency amplifier 14 and the tuner 11 and maintains a predetermined level of the input signal.
The output data from the A/D converter 31 is outputted to the segment synchronous detector 32 and a rear portion field synchronous signal detection terminal (not shown), thus detecting the field synchronous value, and determines whether an NTSC interference eliminating filter in accordance with the level of the interference with the NTSC co-existing channel.
In addition, FIG. 2 is a block diagram illustrating an analog type circuit when converting into a base band width signal of an IF signal in the conventional art. Namely, FIG. 2 illustrates an analog type conversion circuit converting into a base band width signal with respect to the IF signal.
In order to detect the I-signal component, the IF signal inputted from the mixer 41a is multiplied by a cos.omega.t, and the Q-signal is multiplied by sin.omega.t by the mixer 41b.
Namely, in order to obtain optimum I and Q signals, the input IF signal should be multiplied by cos.omega.t and sin.omega.t, respectively, at a corresponding sampling time.
The output signals from the mixers 41a and 41b are converted into the digital signals by the A/D converters 43a and 43b through the low pass filters 42a and 42b and then are outputted as I- and Q-signals.
Namely, the carrier wave demodulator 20 of the GA type HDTV receiving unit performs an analog signal processing step, and the rear portion of the carrier wave demodulator 20 performs an A/D conversion step for a digital processing. Therefore, when implementing the ASIC, since the ASIC in which the digital and analog circuits are mixed is implemented, the implementation of the ASIC is difficult.
USPTO Backgrounds
USPTO Backgrounds