As semiconductor devices such as static random access memories (SRAMs) are scaled down into the 32 nm generations and beyond, Fin Field Effect Transistors (FinFETs), which utilize a “fin” to form multiple channel regions, have become popular over the more standard planar transistors. These FinFETs provide for larger channel widths by using not only the top surface of the fin, as would be used in a planar transistor, but also the sidewalls of the fin. By using these FinFET designs deleterious short-channel effects, such as variability in the threshold voltage and excessive drain leakage currents, can be suppressed or reduced, thereby allowing for a more efficient device.
However, the use of FinFETs has encountered problems. Standard lithographic techniques, which have traditionally been used to both form the fins as well as the gate electrodes that lie over the fins, have become untenable as a primary manufacturing technology for FinFETs. Fundamental limitations involved with the lithographic process limit its usefulness in forming fins and gate electrodes as FinFETs are scaled to smaller and smaller dimensions. In other words, the standard lithographic process is itself limited and may be unable to scale downwards along with the scaling of the FinFETs that it is being used to manufacture.
As such, other manufacturing processes need to be developed in order to maintain the scaling that will be required for further reductions of FinFETs.
USPTO Backgrounds
USPTO Backgrounds