In many applications, comparators only function over a portion of a time period. Such circuits are driven by a clock and have a first (sampling) phase when the comparator output is not available and a second (amplifying) phase when the comparator output is available. Some of these comparators can include one or more preamplifier stages followed by a latch stage. When a low offset is required, the preamplifier stage(s) can build up an input voltage difference to a sufficiently large value and then apply the input voltage to the latch stage to decrease the effect of latch offset. When low power is required, a dynamic latch can be used.
The conventional comparator described above works well for some applications. However, when a very low operational current (e.g., 100 nA) and hysteresis are required, the linear preamplifier stage(s) cannot be used.
USPTO Backgrounds
USPTO Backgrounds