The present invention relates to an apparatus and method for measuring the thickness of a semiconductor such as the outer layer of a semiconductor-on-insulator wafer for thicknesses of more than five microns and up to many hundreds of microns.
There are no accurate full aperture imaging systems which can measure very thick layers of silicon in a bonded wafer and provide a thickness map of the outer layer. Commercial instruments operate one point at a time on the wafer in either the ultraviolet or visible region and cannot measure films hundreds of microns thick since the high absorption in the silicon outer layer effectively eliminates fringe formation.
Even though infrared radiation is not absorbed as much, it is difficult to achieve a plurality of narrowband infrared filters such as would be required to expose the wafer separately to many different infrared wavelengths (as was similarly done in the above mentioned copending application Ser. No. 07/804,872) with visible light for relatively thin layers of silicon on insulator, i.e., on the order of four or five microns or even tens of microns thick.
Semiconductor manufacturers presently purchase silicon wafers that have been micropolished down to the four-to-five micron thickness range. The above cited patent application permits smoothing down to less than 100 nanometers with uniformity better than 10 percent. Nevertheless, it has heretofore been required to purchase wafers already micromachined down to the four-to-five micron thickness level as a starting point. This is due to the inability of the visible light system disclosed in the above cited copending patent application to create a thickness map for wafers in the hundreds of micron thickness range for the reason of the absorption problems mentioned above.
It would be desirable to purchase thick wafers to begin with and be able to create a thickness map thereof so that high rate plasma assisted chemical etching (PACE) polishing might be used to remove the bulk of the layer now removed by conventional grinding and chemo-mechanical polishing technologies. If such thickness maps of thick silicon layers could be produced quickly (approximately one minute per map), then not only can less expensive starting wafers be used, but the map would allow partial smoothing of the outer film as the bulk of the layer is removed by a high rate plasma assisted chemical etching polishing process. The final thickness target would be in the four-to-five micron range and the additional smoothing afforded by the high rate PACE process would reduce local slopes and subsequently allow precise measurement with the visible metrology system disclosed in the above cited copending application.
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