1. Technical Field
The present invention relates generally to clocks in electronic circuits, and more particularly, to a system for self alignment of complement clocks.
2. Related Art
The use of clock signals to control the timing of operations in electronic circuits is well known. Stability of the clock signals is important to the proper operation of digital systems. In digital systems with complement clock signals, such as delay locked loop (DLL) circuits in double data rate-synchronous dynamic access random access memory (DDR SDRAM) stability is especially important to maintain alignment of the clock signals. Ideally, complement clock signals in such a digital system should have the same slew rate, the same duty cycle and remain phase shifted by exactly 180 degrees. In reality, since the clock signals are distributed over the area of a semiconductor chip, the alignment of complement clock signals is difficult to maintain over the whole chip. Difficulties are mainly the result of routing constraints and semiconductor process variations.
Accordingly, in digital circuits such as DLL circuits, complement clock signals have to be redriven. One simple way to redrive complement clock signals is by passing each of the clock signals through a separate series of inverters. The more inverters placed in respective inverter chains, the larger the amount of delay imposed on the complement clock signals passing therethrough. The drawback of using inverter chains is that mismatches of the complement clock signals that are present at the inputs to the inverter chains usually propagate to the outputs. In addition, the magnitude of the mismatch may be increased by the inverter chains.
USPTO Backgrounds
USPTO Backgrounds