Metal-oxide semiconductor field effect transistors (MOSFETs) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.
When a MOSFET device is in the on state, a voltage is applied to the gate structure to form a conduction channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low so that a conduction channel does not form, and thus current flow does not occur. During the off state, the device must support a high voltage between the source and drain regions.
In optimizing the performance of MOSFET devices, designers often are faced with trade-offs in device parameter performance. Specifically, available device structure or fabrication process choices may improve one device parameter, but at the same time such choices may degrade one or more other device parameters. For example, available structures and processes that improve the output or drive current (IDS) capability and on resistance of a MOSFET device also degrade its breakdown voltage (BVDSS) capability and increase gate to drain capacitance.
Accordingly, improved semiconductor device structures and methods of their manufacture are needed to address the above mentioned issues as well as others.
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