An end-to-end design flow of an integrated circuit includes schematic construction and pre-layout simulation, layout generation based upon the schematic, and post-layout simulation of the generated layout prior to manufacturing. Pre-layout simulation and post-layout simulation verify consistency of an integrated circuit between the schematic representation and the layout representation, respectively. Parameters which account for parasitic effects in the pre-layout simulation step are removed prior to layout generation to avoid double-counting of the parasitic effects in the post-layout simulation step. These parameters are derived directly from layout topologies within the layout representation.
USPTO Backgrounds
USPTO Backgrounds