It is well recognized that increasing the mobility of charge carriers in metal oxide semiconductor (MOS) transistors in integrated circuits (ICs) improves the operating speed of ICs. There are several techniques used in advanced ICs to increase the mobilities of electrons and holes in silicon n-channel MOS (NMOS) and p-channel (PMOS) transistors, including orienting the silicon substrate to take advantage of the fact that carrier mobility varies depending on the orientation of the crystal lattice in the MOS transistor channel. Electrons have maximum mobility in (100)-oriented silicon when the NMOS transistor is aligned on a [110] axis, that is, when the electron movement in the NMOS transistor channel is along a [110] axis. Note that the notation “(100)-oriented silicon” refers to a crystal orientation in which the vector 1·x+0·y+0·z, or its equivalent, is perpendicular to the surface of the crystal, while the notation [110] axis refers to a direction parallel to the vector 1·x+1·y+0·z, or its equivalent. Holes have maximum mobility in (110)-oriented silicon when the PMOS transistor is aligned on a [110] axis. To maximize the mobilities of electrons and holes in the same IC requires regions with (100)-oriented silicon and (110)-oriented silicon in the substrate, known as hybrid orientation technology (HOT). Known methods of HOT include amorphization and templated recrystallization (ATR) which introduces defects adjacent to shallow trench isolation (STI) structures. Reduction of the ATR defects requires annealing at temperatures higher than 1250 C, which introduces wafer distortions, making fabrication of deep submicron MOS transistors difficult and costly.
USPTO Backgrounds
USPTO Backgrounds