A large-scale chip such as an SoC (System on a Chip) on which various circuits coexist often uses more than one clock and therefore requires a CDC circuit design for exchanging data between different clock domains. In an asynchronous circuit design, which presupposes misalignment of clock edges, various clock combinations can be selected. However, if data passing is not sufficiently reviewed, a failure may occur in an unexpected case. In a synchronous circuit design, which presupposes alignment of clock edges at certain regular intervals, circuit operations can be assured through a logical simulation and STA (Static Timing Analysis). Therefore, compared with the asynchronous circuit design, the synchronous circuit design advantageously allows for easy design.
FIG. 1 shows an exemplary conventional circuit using two synchronous clocks. An enable signal is used to pass data between clock domains. The frequency ratio of the clocks is supposed to be 1:n. FIG. 1 illustrates an example of synchronous clocks with the frequency ratio 1:2, one being 166.666 . . . MHz (hereinafter simply referred to as “166 MHz”) of a period of 6 ns and another being 333.333 . . . MHz (hereinafter simply referred to as “333 MHz”) of a period of 3 ns. At every 6 ns, edges of the two clocks coincide, i.e., rising edges or falling edges of the two clocks align. At the rising edge of the 333 MHz clock, data in a left-side flip-flop circuit (hereinafter referred to as “FF”) is maintained when the enable signal is low (0) (this state is defined as “disabled”), and data received at the left flows to a right-side FF when the enable signal is high (1) (this state is defined as “enabled”). Thus, the left-side circuit including a multiplexer and the FF, although operating at 333 MHz (a period of 3 ns), can be operated at the same period (a period of 6 ns) as the FF operating at twice the period, i.e., 166 MHz (a period of 6 ns).
As shown in FIG. 2, the enable signal (see a waveform in a first row) is controlled to be high at rising edges of the 333-MHz clock when edges of the 333-MHz clock and the 166-MHz clock coincide (see points indicated by circles). In this manner, the timing of passing data from an FF operating at 333 MHz (see clocks and data in a second row) and receiving data directed to an FF operating at 333 MHz (see clocks and data in a fourth row) can be matched to an FF operating at 166 MHz (see clocks and data in a third row). Specifically, when the enable signal is high, the data occurring in the FF operating at 333 MHz (see the data in the second row) changes at the times (every 6 ns) of the rising edges of 166 MHz, so that the data can be passed even to the FF operating at 166 MHz at the times (every 6 ns) of the rising edges of 166 MHz (see the data in the third row indicated by solid arrows). Further, the data can be passed in a similar manner to the FF operating at 333 MHz (see the data in the fourth row indicated by dashed arrows). FIG. 3 shows a circuit further illustrating the data passed from the FF operating at 166 MHz to the FF operating at 333 MHz.
While an increase in the operation speed can be expected by increasing the clock frequency of a circuit, the maximum operation frequency of a circuit varies with circuit design. Therefore, as shown in FIG. 4, the frequency of a clock domain A may not be able to be increased above the upper limit of 333 MHz even when it is desired to increase the frequency of a clock domain B. If the clock frequencies of the both domains can be increased with the clock ratio 1:n maintained, the conventional technique shown in FIG. 1 can be applied. However, the technique in FIG. 1 cannot address the case of 333 MHz and 200 MHz as shown in the lower row in FIG. 4, in which the clock frequency ratio is 5:3.
In this case, data passing is possible by, for example, making the enable signal high at every 15 ns at which edges of the clocks coincide and passing data at every 15 ns, as shown in FIG. 5. However, this results in a data transfer rate of once in 15 ns (a speed of 66.666 . . . MHz), which is one third of the data transfer rate of even the slower FF operating at the 200-MHz clock.
FIG. 6 shows a case in which data is transferred three times in 15 ns with the 200-MHz timing according to a conventional method. In FIG. 6, the timing with which the enable signal (see a waveform in a first row) is high is adjusted so that data is transferred at a rate of three times in 15 ns in the circuit shown in FIG. 5. In this case, when the enable signal is high, data from the FF operating at 333 MHz (see clocks and data in a second row) to the FF operating at 200 MHz (see clocks and data in a third row) is correctly transferred (in the order of a, b, c, d, e) (see data transfer indicated by solid arrows). However, the data is not successfully transferred from the FF operating at 200 MHz to the FF operating at 333 MHz (see clocks and data in a fourth row) with the loss of the data b and e (see data transfer indicated by dashed arrows and dashed circles). Particularly, immediately after the data is passed to the FF operating at 200 MHz at 5 ns, the data is passed to the FF operating at 333 MHz at 6 ns. That is, the setup time is 1 or 2 ns, resulting in severe data passing timing.
In a synchronous circuit design, combinations of available clocks are limited. Trying to transfer data fast leads to inability to correctly transfer the data due to failures such as data loss. Conventionally, a dedicated circuit customized by considering data passing directions for a clock combination must be designed, and changing the clock combination requires another circuit. In an asynchronous circuit design such as based on double latch, as shown in FIG. 7, the both clock domains need to be taken into account to provide a latch connection circuit in each clock domain. The asynchronous processing such as based on double latch causes losses at the time of data passing. When the clock combination is changed, the circuit needs to be reviewed and possibly redesigned.
Patent Literature 1 describes providing a function for achieving signal synchronization between modules operating at clocks with a non-integer multiple ratio through a simple method in a semiconductor integrated circuit device.
Patent Literature 2 describes a method and an apparatus for generating a phase control clock signal capable of outputting a clock signal at a frequency in a non-integer multiple ratio relationship with an external system clock.
USPTO Backgrounds
USPTO Backgrounds