1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for manufacturing a three-dimensional capacitor electrode using an insulating layer.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the area of the capacitor decreases. The required capacitance of a capacitor, however, increases. Accordingly, methods have been proposed for enlarging the effective surface area of a dielectric layer for a storage node, which is adopted in a semiconductor device, such as a dynamic random access memory (DRAM).
A representative method of enlarging the effective surface area of a storage node is disclosed in U.S. Pat. No. 5,162,248, issued to Charles H. Dennison et al., entitled xe2x80x9cOptimized Contained Stacked Capacitor DRAM Cell Utilizing Sacrificial Oxide Deposition and Chemical Mechanical Polishing.xe2x80x9d In U.S. Pat. No. 5,162,248, a sacrificial oxide layer is used for making the shape of a storage node into a three-dimensional shape.
As semiconductor devices have become more highly integrated, another approach of using a high dielectric constant material, such as ditantalum pentaoxide (Ta2O5) or BST ((Ba, Sr)TiO3), for the dielectric layer of a capacitor has been proposed. Use of such high dielectric constant materials for a dielectric layer requires that a capacitor electrode is formed of a metal layer, such as a titanium nitride (TiN) layer, instead of conductive polysilicon. That is, use of a metal-insulator-metal (MIM) structure for a capacitor has been favorably proposed.
When a metal electrode is used, it is difficult to form a storage node of a three-dimensional shape, such as cylinder, container or stack, using a sacrificial oxide layer. For example, a sacrificial oxide layer, which is adopted for forming a three-dimensional storage node, is utilized as a mold for making the shape of a storage node three-dimensional. An additional sacrificial oxide layer may be adopted for isolation of a storage node. It is preferable to remove this sacrificial oxide layer in a later process to obtain the maximum effective surface area of the storage node.
A sacrificial oxide layer is typically removed by a wet etching process. It is essential to introduce an etch stop layer under the sacrificial oxide layer in order to control the wet etching process. For such an etch stop layer, a silicon nitride layer is utilized. When such silicon nitride layer is utilized as an etch stop layer, an insulating layer under the etch stop layer may be damaged during a wet etching process for removing the sacrificial oxide layer. Put another way, an etchant used in the wet etching process may permeate along the border between the silicon nitride layer and the storage node into the underlying insulating layer and liquefy the insulating layer. This phenomenon is substantially caused by the low adhesive property between a silicon nitride layer and a metal electrode.
Since the insulating layer under the etch stop layer serves to support the storage node, the storage electrode may fall down or slant due to dissolution of the underlying insulating layer, thereby causing a defect in an electrode. Accordingly, to utilize a metal electrode as a capacitor electrode, it is desirable to adopt a new etch stop layer, which can prevent an underlying insulating layer from being corroded by an etchant.
To solve the above problem, a feature of an embodiment of the present invention is to provide a method of manufacturing an electrode of a capacitor using a new etch stop layer. The new etch stop layer can prevent an underlying insulating layer from being dissolved or an electrode from falling down or sinking due to a wet etching process for removing a residual sacrificial insulating layer, during formation of a three-dimensional capacitor electrode using a sacrificial insulating layer.
Specifically, an additional feature of an embodiment of the present invention provides a method of manufacturing an electrode of a capacitor. Initially, a lower insulating layer surrounding a conductive plug, which is electrically connected to a semiconductor substrate, is formed on the semiconductor substrate. Next, a support insulating layer is formed on the lower insulating layer. Then, an etch stop layer including a tantalum oxide layer is formed on the support insulating layer. Additionally, a mold sacrificial insulating layer is formed on the etch stop layer.
A mold, exposing the conductive plug, is formed by sequentially patterning the mold sacrificial insulating layer, the etch stop layer and the support insulating layer. The patterning for forming the mold is performed by dry etch. To control the extent of etching, an auxiliary etch stop layer may be formed on or under the tantalum oxide layer. The auxiliary etch stop layer may be formed of an aluminum oxide layer or a tantalum nitride layer.
A storage node layer covering the inner surface of the mold is formed on the mold such that the storage node layer is electrically connected to the conductive plug. A storage node is formed by separating the storage node layer. The residual mold sacrificial insulating layer that is exposed by the separation of the storage node layer is selectively etched and removed using the etch stop layer as an etch stopper.
Accordingly, the storage node having a three-dimensional shape, such as a cylindrical shape or a stack shape, is completed.
These and other features of the embodiments of the present invention will be readily apparent to those skilled in the art upon review of the detailed description that follows.
USPTO Backgrounds
USPTO Backgrounds