Exact rational frequency translation using a phase locked loop (PLL) is well known. However, it generally has been implemented with integer dividers yielding an output/input frequency ratio given by: FOUT/FIN=B/A (A and B are both integers). The integer constraint significantly limits the useful range of ratios, because FOUT is bounded by the range of the PLL's internal frequency source (typically a VCO). The bound on FOUT limits the usefulness of the B/A integer divide ratios. A further constraint on the usefulness of this approach is that FIN/A must be sufficiently large to ensure that the input PLL phase margin is not compromised due to an excessively low PFD update rate. Generally, it is desirable to have the A and B dividers be programmable in order to support a range of FOUT/FIN ratios. A problem arises, however, when the A and/or B dividers lack sufficient depth to satisfy a particular FOUT/FIN ratio.
As discussed in provisional application 61/114,676, the inventors have developed a frequency translation system that provides frequency conversion according to non-integer frequency conversion—where A and B need not be integers. Moreover, the inventors have developed such a system that accepts input clock signals from a variety of independent sources and converts the various clock signals to a common frequency. A problem remains, however, if the frequency converter were to switch from one input clock to another as a dominant clock signal. In such a case, the clock signals generated from the input branches may not be in synchronism, which can cause data loss until the system recovers and a new output clock signal is established. This performance degradation is called a switchover “hit,” colloquially.
Accordingly, the inventors have identified a need in the art for a hitless switchover mechanism in frequency conversion systems, particularly in frequency conversions systems that perform frequency translation that is a ratio of very large integers.
USPTO Backgrounds
USPTO Backgrounds