For high performance Software Defined Radio (SDR) applications it is often desirable to have a transceiver that operates continuously from 100 MHz to 6 GHz and within Land Mobile Radio (LMR) equipment signal quality performance requirements. This level of signal quality in a transceiver is traditionally achieved using a phase-locked loop (PLL) synthesizer having a narrow bandwidth Fractional-N Phase-Locked Loop (PLL) Synthesizer as a signal source implemented with a Voltage Controlled Oscillator (VCO) using a discrete resonator. The narrow bandwidth Fractional-N PLL synthesizer can provide in excess of −80 dBc of spurious performance and the discrete resonator VCO can provide sideband noise performance of about −126 dBc/Hz at a 25 KHz offset from a 1 GHz carrier. However, the Fractional-N PLL synthesizer typically has a slow slew rate which results in a long transition time of indeterminate phase when changing from one frequency to another.
It would be desirable to have a SDR receiver which is flexible with respect to the frequencies it receives and which has the ability to almost instantaneously (e.g., less than about 1 ms) change from one frequency to the next.
One problem in making such a flexible SDR receiver is that the Fractional-N PLL synthesizer has a complex frequency transition when going from an output signal having a first frequency to an output signal having a second frequency. This includes a duration of time in which the Fractional-N PLL synthesizer generates an output signal having unlocked, nondeterministic signal quality with unknown frequency. A second problem is that the VCO used in the above-described PLL synthesizer often has a limited output frequency range of less than 20% or +/−10% about the frequency of the signal output from the VCO.
Therefore it is desirable to provide a PLL synthesizer which can provide continuous LMR signal quality output to an electronic device, such as a SDR receiver, along with the flexibility to almost instantaneously (e.g., again within about 1 ms) change frequencies across a broad band of frequencies, such as from 100 MHz to 6 GHz. It is also desirable to provide such a PLL synthesizer which uses only one VCO, to lower size and cost of the PLL synthesizer, designed with a discrete resonator which overcomes having any duration of time in which an output signal is generated having unlocked, nondeterministic signal quality and an unknown frequency when the output signal is transitioning from one frequency to a second frequency.
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