1. Technical Field
The present invention relates in general to clock distribution in digital systems, and in particular to an apparatus and method for accurately and unintrusively measuring clock skew.
2. Description of the Related Art
Computer systems and other digital electronic systems are made up of individual devices that must communicate with each other. These devices are interconnected via busses that serve as the inter-device communication medium. Such busses may operate either synchronously or asynchronously.
Whereas an asynchronous bus is not clocked, a synchronous bus employs a clock signal that is applied within the bus control lines. A fixed protocol is incorporated within a synchronous bus for facilitating communication relative to the timing of the clock signal. For example, when a processor-memory bus performs a read from memory, the protocol utilized therein may transmit the address and read command over bus control lines on the first clock cycle to indicate the desired read request. The target memory device may respond with the requested data word on the sixth clock cycle. This type of synchronous protocol can be implemented easily as a simple finite state machine.
One major disadvantage of synchronous busses is that as bus length increases, clock skew becomes a problem. Clock skew is the difference in absolute time between when two bus elements receive a clock edge. Clock skew arises when a clock signal travels over at least two different paths, having different delays, to reach different bus elements. Edge-triggered devices within a synchronously bussed system are particularly sensitive to clock skew since such devices require relatively precise clock edge timing.
Clock skew is typically minimized through a two-step process of first measuring or simulating it and then inserting appropriate tuning circuitry in the clock distribution paths. These steps may be performed at the board level, from a clock source point on the board to the clock input of each integrated circuit device on the board. These steps may also be performed on a system level, from a system clock source point to the clock source points of each board in the system. The ever-increasing speeds of current and future digital systems together with the trend toward System On Chip (SOC) devices may necessitate clock tuning between state devices such as latches fabricated on the same integrated circuit chip. The present invention relates to the measurement step in this process.
Measurement of clock skew on bussed devices such as microprocessors presents difficulties due to the loading of sensitive internal circuits and the dependence on extremely sensitive laboratory equipment. Conventional measurements of low skew ( less than 50 psec) require probes that operate over very narrow time bases. Such probes often impose load capacitances that distort the clock distribution. E-beam and photoemission microscopy are alternative clock skew techniques that avoid the problem of capacitive loading, but are expensive, difficult to calibrate and maintain, and require extended sample times that are prone to drift.
From the foregoing, it can be appreciated that a need exists for an inexpensive clock skew measurement system that is suitable for unintrusively measuring very low skew.
An apparatus and method for measuring clock skew in a digital system are disclosed herein. A phase detector generates an error signal proportional to a phase difference between signals applied to first and second phase detector inputs. A controlled oscillator produces an output signal having a frequency that is proportional to the filtered error signal. In accordance with the method of the present invention, a feedback path from the output of the controlled oscillator to the second input of the phase detector is opened. A sequence of pairs of mutually delayed signals are applied to the first and second phase detector inputs to obtain a range of delay reference values. A pair of signals from different nodes within the digital system are applied to the first and second phase detector inputs to obtain a skew response. The skew response is evaluated with respect to the range of delay reference values to obtain a skew result.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
USPTO Backgrounds
USPTO Backgrounds