1. Field of the Invention
The present invention pertains to a method and apparatus for down converting signals from an Intermediate Frequency (IF) input signal to Inphase (I) and Quadrature (Q) signals at baseband. In particular, the present invention pertains to a down conversion technique by which an IF signal is hard-limited and the hard-limited signal is digitally processed to form I and Q sampled signals at baseband.
2. Description of the Related Art
Down conversion is the process by which a radio frequency (RF) signal is stripped of its high frequency carrier wave to reveal the information carrying waveform embedded within. Needless to say, down conversion processes are implemented within virtually every radio, cell phone, two-way transceiver, pager, transponder and other devices that receive information propagated via RF signal. Received RF signals are downconverted to a form and frequency that can be manipulated using electronic components so that the information contained within can be extracted and used.
In the first downconversion stage, the RF signal is physically received by an antenna designed for the nature of the physical waveform chosen by the transmitting device to propagate the embedded information signal. The RF signal is typically fed from the antenna as input to an RF tuner that mixes the RF frequency signal with a local oscillator (LO) signal specifically chosen so that the mixed signal, produced as output from the RF tuner, has a frequency significantly lower than that of the original RF signal, known as an Intermediate Frequency (IF). This IF signal is typically passed through a bandpass filter to eliminate extraneous components, thereby producing a filtered IF signal.
In the second downconversion stage, the filtered IF signal is further processed to generate In-Phase and Quadrature signals at baseband. Inphase (I) and Quadrature (Q) signals at baseband are typically generated by multiplying the Intermediate Frequency (IF) signal by cos(2πfo*t) and sin(2πfo*t) signals, where the frequency (fo) is the center frequency of the desired signal in the IF passband.
It is well known among those schooled in the art that multiplication by sine and cosine signals can be greatly simplified, digitally, by choosing a sampling frequency that is four times the signal frequency in the IF passband. Hence, multiplication by cos(2πfo*t) and sin(2πfo*t) can be reduced to multiplication by the values 1, 0, −1, 0 or 0, 1, 0, −1 by making the sampling time correspond to t=n*1/(4*fo) where n is a positive integer (recall that the values of sine and cosine are 1, 0, or −1 at angles of 0, π/2, π, and 3π/2 radians).
In terms of hardware used to implement IF to baseband down conversion, prior approaches generally use analog-to-digital (A/D) converters to digitize the IF signal into a sequence of samples, with the amplitude of each sample being represented by a binary number, typically consisting of at least twelve bits. If the sampling rate is four times the IF signal frequency, then the I and Q signals are formed by using every second sample for I and the alternate samples for Q. In addition, every other I and Q sample has its sign inverted to achieve multiplication by cosine and sine functions, as described above.
One shortcoming with this approach is that the A/D converter must sample at four times the IF signal frequency which, for most intermediate frequencies, requires a fast A/D converter. Such fast A/D converters are typically costly and consume considerable power. In addition, an automatic gain control (AGC) must be used prior to the A/D conversion to keep the IF signal within the A/D converter's dynamic range. These twelve-bit samples are then low-pass filtered, digitally, in an Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Digital Signal Processor (DSP) or similar device to produce the desired bandlimited I and Q output signals. A second shortcoming associated with the above approach is that twelve-bit sample precision greatly increases the complexity inside the programmable gate-array type devices typically used to perform the low-pass filtering. Besides requiring twelve bits per sample, such low-pass filters typically require twelve-bit multiply and add operations. Such operations require a large number of gates in FPGA and ASIC devices.
While the known approaches for down converting signals from an Intermediate Frequency (IF) input signal to Inphase (I) and Quadrature (Q) signals at baseband are operationally effective, they include many cost/performance inefficiencies. The circuits required to implement current IF to baseband down conversion are unnecessarily complex due to the need for AGC's, A/D converter's, and FPGA's, ASIC's and DSP's with large numbers of gates. This increased complexity not only increases production costs, but can also lead to increased production defects. Furthermore, greater circuit complexity leads to greater power consumption.
As a result, IF to baseband converters based upon the prior art approaches are disadvantageous for use in devices in which cost of production and/or device operational power consumption must be optimized. Such devices include a large number of military and commercial devices such as radios, pagers, cell phones, transponders used to monitor the status/location of resources, and other devices in which cost of production and/or and power consumption are key design considerations.
Hence, there remains a need for an IF signal downconverter capable of generating I and Q signals at baseband using circuitry of reduced complexity, power consumption, and cost.
USPTO Backgrounds
USPTO Backgrounds