Heretofore, semiconductor devices with an Al/SiO2 multilayer interconnect structure, which uses Al, Al alloy or the like as an interconnect material, and uses an SiO2 film as an interlayer dielectric, have been mainly manufactured. In recent years, in order to reduce the interconnect delay caused by the miniaturization of semiconductor devices, semiconductor devices with a Cu/low-k multilayer interconnect structure, which uses Cu with low resistance as an interconnect material and a low-k film (a low dielectric constant film) with low interconnect capacitance as an interlayer dielectric, are being manufactured in large quantities.
Cu/low-k multilayer interconnect structures are produced by a process called damascene. In this process, an interconnect structure is obtained by forming trenches or holes (via holes) in an interlayer dielectric substrate, and then filling the trenches or holes with an interconnect material such as Cu.
In a process called dual damascene, trenches for an interconnect and via holes are formed continuously in an interlayer dielectric substrate made of a low-k film or the like, and then filled with an interconnect material such as Cu. A dual damascene structure can be formed by a via-first process, wherein via holes are formed prior to trenches for an interconnect; or conversely, by a trench-first process, wherein trenches for an interconnect are formed prior to via holes; or by other processes such as a middle-first process or a dual hard mask process.
In, for example, processes such as the via-first process, via holes are formed in an interlayer dielectric substrate by dry etching, and then filled with a filling material and planarized. Lithography is subsequently performed to form trenches, and dry etching follows. Ashing or a like process is performed to remove unwanted substances such as resist or filling material from the substrate having trenches and via holes.
Even after this process, however, unwanted substances (hereinafter referred to as “residues after a dry process”) that cannot be completely removed remain on the substrate.
Moreover, dry processes using plasma, such as dry etching and ashing, cause damage to some portions of Cu used as the interconnect material or the low-k film as the interlayer dielectric. Further, if the substrate is exposed to air while being transferred from one process to another, a Cu oxide film is formed on the surface of the Cu metal interconnect.
In a damascene structure, when trenches and via holes are filled with metals such as TaN as a barrier metal and Cu as an interconnect material, the presence of residues after a dry process or Cu oxide film leads to defective semiconductor devices. For this reason, these residues are typically removed using a polymer-removing solution. Because the damaged low-k film is structurally more fragile than the original, it is easily etched by a chemical solution or the like, and undergoes changes in pattern dimensions. Thus, during removal of these residues, it is necessary to prevent the corrosion of Cu caused by the chemical solution, and prevent the etching of the low-k film.
When commercially available known polymer-removing solutions or etchants are used to remove the residues after a dry process and Cu oxide films, problems with workability arise. For example, the residues can be removed using hydrochloric acid or fluoric acid diluted with water, but a large number of dissociated H+ tend to cause Cu corrosion. Moreover, if the interlayer dielectric (especially when it is a porous low-k film) has been damaged by dry etching, the surface condition of the interlayer dielectric may be degraded by etching, or the substrate cannot sometimes be processed to the dimensions as designed.
USPTO Backgrounds
USPTO Backgrounds