The present invention relates to a clock extraction device for generating from incoming data a clock in synchronization therewith.
With the rapid spread of multimedia, there have been increasing demands for transmission of large amounts of data at high speed. As means to meet such demands, high-speed serial data interfaces, such as IEEE 1394 and Gigabit Ethernet, and Fibre Channel, have lately attracted considerable attention. In these interface techniques, only data is transmitted from the sending side at a high transmission rate (for example, 1 Gbps) and the phase-locked loop (PLL) on the receiving side generates a clock in perfect sync with such high-speed data. Then, the high-speed data is latched and received on the receiving side by the generated clock. Such technology reduces the skew between clock and data as compared with conventional interfaces designed to transmit both a clock and data, for speeding up the transmission of data.
The IEEE 1394 Std. provides a configuration in which a single interface LSI (physical layer LSI) has a plurality of I/O ports. However, as described above, synchronization of incoming, data with a latch clock for the incoming data is established by a receiving-side PLL and the ports, in fact, receive their respective input data at slightly different frequencies (several hundreds of ppm), so that each port requires a PLL for synchronization. In other words, in accordance with the IEEE 1394 Std., one chip is required to carry a corresponding number of PLLs to the number of ports. This accordingly leads to increase in power consumption and in heat release amount. It therefore becomes impossible to seal the chip into a plastic package and, in addition, there is a considerable increase in chip area. This produces the problem that reductions in costs are difficult to achieve.
When performing serial transmission of burst data from a sending-side driver to a receiving-side receiver through a transmission line, the data is generally latched by an internal clock of the receiver. However, the burst data has a burst interval, so that even if the phase relationship of clock versus data is proper at one point in time the timing relationship of data versus clock will deviate during the burst interval. Because of this, there is a possibility of the occurrence of improper latching.
With a view to being able to avoid such a problem, in conventional burst data transmission techniques, when transmitting the next data upon completion of the burst interval, a preamble period is provided prior to the transmission. This allows the receiver to perform phase adjustment on a clock during the preamble period. During the preamble period, actual data is not transmitted. That is, the preamble-period serves as a period used mainly for clock-to-data phase adjustment on the receiver side. This degrades the efficiency of data transmission.
Accordingly, an object of the present invention is to make it possible to achieve extraction of different clocks corresponding to a plurality of input ports respectively with a single PLL, thereby to prevent the number of PLLs in an LSI from increasing even when the number of input ports increases.
Further, another object of the present invention is to eliminate a preamble period used for phase adjustment in transmitting burst data in conventional techniques, for improving the efficiency of data transmission.
In order to provide a solution to the above-described drawback, the present invention discloses a clock extraction device comprising a data sampler part for quantizing incoming serial data by N times oversampling where N is a predetermined number, a data divider part for dividing a datastream obtained by quantization in the data sampler part into a plurality of groups on the basis of transient points in the datastream and of the number N, and a clock generator part for generating a clock on the basis of boundaries of the plurality of groups obtained by the data divider part.
In the clock extraction device of the present invention, input data is quantized by N times oversampling to produce a datastream. Then, the datastream is divided into a plurality of groups on the basis of transient points in the datastream and of the predetermined number N. That is to say, when the data varies for every one cycle, transient points of the datastream exhibit a data cycle, and grouping of a datastream is carried out at the data cycle. Further, when the data does not vary for some cycles, datastream grouping is basically carried out for every N data bits. Then, a clock is generated on the basis of boundaries of the groups of the datastream. Extraction of a clock matched with the data cycle is thus achieved.
Such clock extraction provides the following advantages: (1) A transient point of the datastream is used as a basis, so that the cycle of data specified by oversampling (sample ratexc3x97N) does not necessarily match with that of actual input data in the order of ppm; (2) Adjustment in clock phase is automatically carried out using a transient point of the datastream as a basis, so that extraction of a clock matched with the data input timing is performed in order to ensure that, even when asynchronous, sudden burst data is input, the data is received in safe and reliable manner from the first bit thereof; and (3) A series of such processes can be implemented by application of digital processing for each port at which input data is received (although generation of a clock for oversampling is carried out by means of PLL), so that the provision of a single PLL suffices, regardless of the number of ports.
The present invention discloses another clock extraction device comprising a data sampler part for quantizing incoming serial data by N times oversampling where N is a predetermined number, a first converter part for producing from a first datastream obtained by quantization in the data sampler part a second datastream which specifies transient points in the first datastream, a second converter part for producing from the second datastream a third datastream which specifies boundaries based on transient points in the second datastream and on the number N, and a clock generator part for generating a clock on the basis of boundaries in the third datastream. Such arrangement therefore makes it possible to divide the processing necessary for the extraction of a clock into three process steps, namely, a process of producing a first datastream, a process of producing a second datastream, and a process of producing a third datastream. Accordingly, if the production of each datastream is performed by pipeline, this reduces the load of each process, making it possible to handle high-speed input data.
Further, the third datastream is produced by (a) making reference to an N-th bit from each of the transient points in the second datastream and to bits in front of and behind the N-th bit, (b) if there exists no transient point in any one of the bits, determining the N-th bit as a boundary, and (c) if there exists a transient point in either one of the bits, determining the transient point bit as a boundary. As a result of such arrangement, the bits on each side of the N-th bit are referred to. Accordingly, even when a transient point of the datastream fails to perfectly agree with the N-th bit because of the presence of jitter in the input data, it is possible to achieve adequate clock extraction.
Furthermore, an arrangement may be made in which the third datastream has boundary bits different in logical value from the other bits and the clock is generated by a time-series EXOR of bits in the third datastream. As a result of such arrangement, clock generation is achieved by a relatively simple logic circuit.
The present invention provides a serial-parallel conversion device comprising: (i) a clock extraction circuit including (a) a data sampler part for quantizing incoming serial data by N times oversampling where N is a predetermined number, (b) a first converter part for producing from a first datastream obtained by quantization in the data sampler part a second datastream which specifies transient points in the first datastream, (c) a second converter part for producing from the second datastream a third datastream which specifies boundaries based on transient points in the second datastream and on the number N, and (d) a clock generator part for generating a clock on the basis of boundaries in the third datastream, (ii) a data recovery circuit for recovering the input data from the first datastream, and (iii) a demultiplex circuit for expanding, based on the input data recovered by the data recovery circuit and on the clock extracted by the clock extraction circuit, the input data into a predetermined number of bits.
In the serial-parallel conversion device of the present invention, both the clock generated by the clock extraction circuit and the input data recovered by the data recovery circuit are generated based on the first datastream, so that they are in perfect synchronization with each other. Accordingly, data expanded in the demultiplex circuit by the use of these synchronized clock and data is highly reliable.
In another serial-parallel conversion device of the present invention, a pattern decision circuit sequentially receives expanded data. When the pattern decision circuit determines that there exists a specific pattern in the expanded data received or that there exists a specific pattern extending over not less than two items of expanded data, a data shift circuit shifts the expanded data so that the specific pattern is output at a time as a predetermined number of bits. As a result of such arrangement, for the case of parallel expansion of serial data, alignment is made by the specific pattern and the serial data is set apart for a predetermined number of bits. Accordingly, by appropriate insertion of the specific pattern during the transmission of serial data, it becomes possible to align the expanded data at the receiving side as intended by the sending side.
For example, when the sending side transmits data by 10:1 parallel-serial conversion (the predetermined number of bits is ten), if the data is serially transmitted by parallel-serial conversion from the sending side wherein a specific pattern of ten bits is formed of a bitstream of 1111111111 on the communication condition that 1 does not continue for ten bits, then the data received after the specific pattern (1111111111) and serial-parallel converted is aligned by the specific pattern to become the same 10-bit data at the sending side. This is extremely convenient because, when 10-bit data is sequentially subjected to digital processing at the receiving side, the data (for example, a packet) from the sending side is reproduced remaining intact.
Further, if encoding, such as 8B10B/10B8B, is applied to serial data that is sent, in other words, if a decode circuit is disposed for decoding data encoded at the sending side and expanded by the demultiplex circuit, this provides various types of unique patterns. Accordingly, an adequate pattern in objective communication can be set as the specific pattern.
Furthermore, when the input data is burst data, if a specific pattern is assigned during a preamble period provided at the beginning of a burst period and used for establishing synchronization between the data and an internal clock, then data alignment can be carried out during the preamble period in which no actual data is transmitted. This improves the efficiency of burst data transmission.
A suitable data receiver can be constructed of a plurality of serial-parallel conversion devices of the present invention wherein these conversion devices are operated by a clock from a common PLL.
USPTO Backgrounds
USPTO Backgrounds