Anti-fuse cell technology using a standard CMOS logic process is attractive due to its low manufacturing cost especially for embedded memory applications. The conventional anti-fuse cell using an NMOS device has low-cost, is easy-to-shrink, and provides high-density for advanced process nodes. Therefore, it is a good choice over other embedded memory devices, such as the flash memory. However, conventional anti-fuse cells do have several limitations. For example, because the anti-fuse cell can be programmed only one time, it is not suitable for systems that require re-programmability. To compensate for being only one-time programmable, conventional anti-fuse cells use multiple spare anti-fuse array blocks, which increase the overall die size and cost. Additionally, conventional anti-fuse cells may require isolation regions between cells due to the way the cells are programmed. This additional isolation may also increase the overall array size.
FIG. 1A shows a top view of a conventional N-channel anti-fuse cell structure 100 based on a standard CMOS logic process. The cell structure 100 includes a polysilicon select gate (SG) 101, a polysilicon control gate (CG) 102, N+ diffusions 103, a bit line contact 104, and a field isolation 105, such as a STI (Shallow-Trench-Isolation) oxide. A cross section indicator 111 is also shown.
FIG. 1B shows a cross section view of the cell structure 100. The cross section view is taken at cross section indicator 111 and further shows N+ diffusions 103a, 103b, and 103c, P− well 110, and gate oxides 106 and 107. In this cross section view, a metal bit line (BL) 109 connected to the bit line contact 104 has been added. The CG 102 and the N+ diffusions (103b and 103c) form transistor 113, which may be a low voltage device, such as a 3V device. The transistor 112 is similarly formed.
During programming of the transistor 113, a 5V signal is applied to the CG 102, a 0V signal is applied to the bit line 109, and VDD (e.g., 3V) is applied to the SG 101. The 5V signal applied to the CG may be applied from 5V I/O devices that are normally available in a standard CMOS logic process. With these bias conditions, 0V passes from the BL 109 to the N+ diffusion 103b. The 5V signal applied to the CG 102 will turn on the channel of transistor 113 and allow 0V to pass to the channel region 114. Because the voltage difference between the CG 102 and channel region 114 exceeds the breakdown voltage of the gate oxide 107, the gate oxide 107 will rupture (or breakdown) and cause the CG 102 to be shorted to the channel region 114 (this is referred to as ‘on-cell’). Thus, transistor 113 is programmed as an “on-cell.”
Meanwhile, the 3V signal is applied to cells associated with other (or unselected) bit lines (not shown). This 3V signal will be passed to the channel regions of these unselected cells. This prevents the voltage difference between the CGs and associated channels of these unselected cells from exceeding the gate oxide breakdown voltage, and thus the gate oxides of these unselected cells will not be ruptured (this is referred to as ‘off-cell’).
During a read operation, a positive voltage, such as 3V, is applied to the CG 102 and the BL 109 is biased at a lower voltage, such as 1V. If the cell (e.g., transistor 113) is an on-cell, current will flow from the CG 102 through the gate oxide breakdown region and to the BL 109. If the cell is an off-cell, there will be no current flowing.
When the channel 114 is turned on during programming of transistor 113, the oxide breakdown may occur at any location along the channel 114, such as breakdown path 108a near the drain of transistor 113, breakdown path 108b in the middle of the channel 114, or breakdown path 108c near the source of transistor 113. The location of the breakdown path is dependent on where the oxide 107 is defective.
During a read operation, the channel 114 must be turned on to allow the leakage current to flow from CG 102 though the channel 114 to the drain diffusion 103b. Since the breakdown may occur in the middle of the channel 114 (e.g., 108b) or near the source side diffusion 103c (e.g., 108c), the source diffusion 103c must be isolated from the adjacent cell by the field isolation 105. Otherwise, if the selected cell (e.g., transistor 113) is an off-cell but the adjacent cell is on-cell that has an oxide breakdown path near the source diffusion 103c, current may flow from the adjacent cell to the selected cell and cause a read error. This condition may occur even if the adjacent cells' channel is turned off.
Moreover, during a program operation, because the selected cell's CG channel is turned on, the adjacent cell's CG voltage may leak to the selected cell and cause a programming failure. As a result, the cell's source region 103c must be isolated to prevent these situations. However, the extra field isolation region (e.g., region 105) increases the cell size. It should also be noted that because the cell's channel is on during programming, the gate oxide breakdown may occur in different locations, and therefore different on-cell currents may result due to the different channel resistances that result. There may also be different cell characteristic resulting from different manufacturing processes and/or foundries.
It is therefore desirable to have an anti-fuse cell with uniform and less process dependent on-cell current and which avoids the use of additional isolation between cells to reduce size and cost.
USPTO Backgrounds
USPTO Backgrounds