1. Technical Field
The present invention relates to a semiconductor device and an offset voltage correcting method. More particularly, the present invention relates to a semiconductor device having an amplifier circuit and an offset voltage correcting method.
2. Background Art
An amplifier circuit has a first input terminal and a second input terminal, and operates as follows. A bias voltage is applied to one of the first input terminal and the second input terminal. An input signal is provided to at least one of the first input terminal and the second input terminal, and the amplifier circuit outputs an output signal employing the bias voltage as the operating point. The amplifier circuit ideally has a virtual short-circuit characteristic in which the voltage difference between the first input terminal and the second input terminal becomes zero in the non-signal state where no input signal is input. However, practical anally, the voltage difference between the first input terminal and the second input terminal is present even in the non-signal state. This voltage difference is referred to as the offset voltage. This offset voltage causes a shift of the operating point of the amplifier circuit, and therefore it poses a problem.
In order to cope with the problem, Patent Literature 1 (Japanese Unexamined Patent Application Publication No. 2000-174570) and 2 (Japanese Unexamined Patent Application Publication No. 09-148930) each disclose a technique of correcting the offset voltage. Patent Literature 1 discloses a technique of adjusting gain using a variable resistor. Further, Patent Literature 2 discloses a technique of directly adjusting the bias by an AD converter.
As described above, according to Patent Literature 1 and 2, the offset voltage is corrected by adjusting the bias voltage. However, when the offset voltage is corrected using the techniques of Patent Literature 1 and 2, since the correction component of the bias voltage is amplified and output by the amplifier circuit, there is a problem that a high-precision correction of the bias voltage must be carried out.
Other problems and novel features will become apparent from the description of the present specification and accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds