Integrated circuits that include MOS transistors are particularly susceptible to damage by electrostatic discharge (ESD) events, e.g. when the circuit is touched by a person handling the circuit causing static electricity to discharge from the handler through the circuit. This is particularly the case once the circuit has been packaged but prior to it being installed in a product.
Different protection circuits have been developed to deal with ESD events, including CMOS transistors and SCR devices that shunt ESD current to ground. The CMOS transistors may be implemented as normal operation devices or as snapback devices.
The advantage of using snapback NMOS devices for ESD protection of analog circuits is that they can be implemented using the same process steps for the supported analog circuit. The disadvantage is that the NMOS protection devices therefore also have similar characteristics as the supported or protected circuit devices. This creates a problem since the ESD protection device clearly should have a lower turn-on or triggering voltage than the circuit it is protecting.
The present invention seeks to provide an ESD protection device implemented in a BiCMOS process that has a lower turn-on voltage characteristic.
USPTO Backgrounds
USPTO Backgrounds