1. Field of the Invention.
This invention relates to eliminating errors in digital-to-analog converters. More particularly, this invention relates to a significant reduction or elimination of linearity superposition errors due to reference and ground line resistance in a D/A converter/system using a voltage-output resistor ladder network.
2. Description of the Prior Art.
Analog-to-digital (A/D) and digital-to-analog (D/A) converters are important because they allow digital systems, such as digital computers, to interact with the physical world. Generally, a digital-to-analog converter accepts, at its input, a number which is represented, in binary form, by digital signals. The D/A converter then produces an analog output which represents the digital input. The conversion is usually done by weighting currents, using a resistive ladder network, according to the significance they represent in the digital input. These weighted currents are then summed in an operational amplifier, the output of which is the analog representation of the digital input.
A portion of a typical D/A converter is shown in FIG. 1. In FIG. 1, digital information which is to be converted is represented by binary bits (not shown). Each bit is represented by a signal, as indicated above, which controls the operation of one of switches 10, 12, 14 or 16. If a bit is 0, the switch that it in effect controls will be in the position shown in FIG. 1. If the bit is 1, the switch will be in the position opposite those shown in FIG. 1. For example, if the binary bit which controls switch 10 were a 1, switch 10 would be in the position shown by dotted line 18.
However, no matter what position switches 10, 12, 14 and 16 are in, they are at ground reference potential either directly at node 15, as shown in FIG. 1, or through the virtual ground of op-amp 20 at node 48 when they are in the opposite switch position. Therefore, the magnitude of currents I0, I1, I2 and I3 are essentially independent of the positions of corresponding switches 16, 14, 12 and 10. Since the binary digital signals which represent the bits to be converted (not shown) control switches 16, 14, 12 and 10, it follows that the magnitude of currents I0, I1, I2 and I3 are also independent of the state of the bits which in effect control switches 10 through 16 (whether they are a 0 or a 1). Hence, the voltages at nodes NO, N1, N2 and N3 can easily be calculated.
Since it appears at node N0 that two parallel resistors 22 and 24, each with a resistance value of approximately 2R, are effectively connected in parallel between NO and ground, and one resistor 26 with a resistance value of about R is connected between node NO and node N1, the value of the voltage at node NO must be half of the value of the voltage at node N1 due to the voltage divider formed by resistor 26 and the parallel combination of resistors 22 and 24. Following this analysis from node to node, it can be shown that the value of the voltage at node NO equals VREF/8, at node N1 the voltage equals VREF/4, at node N2 the voltage equals VREF/2, and at node N3 the voltage equals VREF (the same analysis is true for any extension of the ladder network).
Thus, one can see that currents I0, I1, I2 and I3 are weighted so as to be monotonically increasing fractions of the reference current IREF with each twice the value of the preceding one. Also, Iop is comprised of the sum of just those of the weighted currents I0, I1, I2 and I3 which correspond to a bit in the digital signal which is a 1. Hence, the output voltage VOUT of op-amp 20 is a value which represents the number to be converted.
Often, switches 10, 12, 14 and 16 are comprised of coupled n-channel MOS transistors as shown in FIG. 1A. Transistors 34 and 36 each have the drain thereof jointly coupled to the bottom terminal of one of the 2R value resistors 24, 28, 30 or 32 in FIG. 1. The source of transistor 36 would be typically connected to ground node 15, and the source of transistor 34 would typically be connected to virtual ground node 48. The gate terminals of MOS transistors 34 and 36 are coupled such that they receive the binary signals representing that bit which is controlling the switching of MOS transistors 34 and 36.
Logic signal D0 in FIG. 1A is applied to the gate terminal of MOS transistor 34, and its complement signal D0 is applied to the gate terminal of MOS transistor 36. Therefore, if the binary state of bit signal D0 is 1 using positive logic, MOS transistor 34 is in the "on" condition and MOS transistor 36 is in the "off" condition. Likewise, if the binary state of bit signal D0 is 0, MOS transistor 36 is "on" and MOS transistor 34 is "off". If p-channel MOS transistors are used, the opposite transistor conditions will occur for these D0 digit signal logic values.
As indicated above, the value of the current I flowing through the resistor of value 2R in FIG. 1A is independent of the binary state of bit signal D0 controlling this switch. Similarly, the value of currents I0, I1, I2 and I3 in FIG. 1 are independent of the binary state of the bits which effectively control switches 16, 14, 12 and 10, respectively. Therefore, the value of IREF is constant and independent of interaction between the binary bits which control switches 10, 12, 14 and 16. Alternatively stated, a constant input impedance appears between node VREF and ground. The R and 2R valued resistors 22, 24, 26, 28, 30, 32, 40 and 42 in FIG. 1 can be trimmed to desired values by using laser trimming techniques. Also, the switching transistors, which make up switches 10, 12, 14 and 16, can be carefully scaled with respect to the resistance through them when they are in the "on" condition (R.sub.ON). Since currents I0, I1, I2 and I3 are constant, using these techniques enables good performance with respect to absolute accuracy (a measure of each output current or voltage level with respect to its intended value), and relative accuracy (the accuracy of each analog output level as a fraction of the full-scale value).
Although the D/A converter of FIG. 1 can be made to operate quite accurately, capacitances are associated with the MOS transistors in switches 10, 12, 14 and 16. These capacitances slow the operation of the D/A conversion by lengthening the time required for VOUT to achieve the proper level of voltage. Leakages in the actual transistor switches used also cause difficulties as such leakage currents become error portions or the current Iop which determines the output voltage. For these reasons, a voltage-output D/A converter such as that shown in FIG. 2 is often used.
The structure, with respect to resistors 22, 24, 28, 30 and 32, each of a resistance value of approximately 2R, and with respect to resistors 26, 40 and 42, each of a resistance value of R, of the D/A converter shown in FIG. 2 is identical to that structure in the D/A converter shown in FIG. 1. The switching transistors 34 and 36, shown in typical form in FIG. 2B, are a CMOS pair, and they have been repeatedly inserted in FIG. 2 in place of the simple switch models of switches 10, 12, 14 and 16 shown in FIG. 1.
The necessary switching effect can be obtained by applying a single bit signal D0 to the gate terminals of two complementary MOS transistors as shown in FIG. 2B without needing its complement. In FIG. 2B, n-channel MOS transistor 36 is coupled at its drain to the drain of p-channel MOS transistor 34. The drains of complementary MOS transistors 34 and 36 are also coupled to one of the 2R valued resistors 24, 28, 30 or 32, as discussed above. The sources of the complementary MOS transistors 34 and 36 are switch terminals A and respectively. As before, switch terminals A are typically connected to reference voltage node 48', and switch terminals B are typically connected to ground reference node 15. Due to MOS transistor 36 being n-channel and MOS transistor 34 being p-channel, applying D0 to the gates of both MOS transistors 34 and 36 achieves the switching effect of having one in the "on" condition and the other in the "off" condition because opposite gate voltage logic levels are required at the gate of each to achieve the same transistor conduction condition.
Also, the digital binary signal source which effectively controls switches 10, 12, 14 and 16, is explicitly shown in FIG. 2. The bit signals are shown taken from digital signal register 44 with its outputs labeled with the bit signals supplied thereat, these being logic signals D0 through D3.
In the D/A converter of FIG. 2, the magnitude of the voltage which appears at output node V0 varies With the state of digital logic signals D3 through D0. As any logic signal D.sub.N (or D.sub.N-0), D.sub.N-1, D.sub.N-2, . . . , D.sub.N-n, D.sub.0 (or D.sub.N-N), here covering the range D3 through D0, becomes a "1", the voltage which appears at V0 increases by a fraction of the reference voltage appearing at the corresponding A terminals of switches 10 through 16. Each switch, on having its controlling digit signal D.sub.N-n take a logical value of "1", can be shown to provide an increase of (1/2).sup.n+1 VREF. For instance, if the binary code representing D3, D2, D1 and D0 were 1000, V0=VREF/2 assuming a unity gain in the output amplifier. If it were 0100, V0=VREF/4. If it were 1100 V0=3VREF/4 and so forth. This manner of operation applies for any extension of the ladder network. Therefore, the voltage appearing at V0 is an analog reflection of the digit signals D0 through D3 as provided in complementary form at the outputs of digital signal register 44, the uncomplemented digit signals representing the digits or bits of the binary number to be converted.
Similar to the D/A converter shown in FIG. 1, ground terminal 15 in FIG. 2 is electrically connected to the B terminals (ground terminals) of switches 10, 12, 14 and 16 by a single track 52. Track 52 also has an inherent internal track resistance 52' associated with it, particularly if the circuit is implemented in a monolithic integrated circuit. The reference voltage VREF, rather than being applied to the junctions of resistors 32 and 42 as in FIG. 1, is now applied in FIG. 2 to node 48' by low output impedance reference voltage circuit 46, which is electrically connected by a single track 50 to the A terminals (voltage reference terminals) of switches 10, 12, 14 and 16. Track 50 also has an inherent internal track resistance 50' associated with it which will often be significant in a monolithic integrated circuit.
Correspondingly, the output voltage V.sub.0 in FIG. 2 appears at the junction of resistors 32 and 42, and is applied to a high impedance input of an output amplifier circuit 54. Arbitrary valued resistors are shown indicating gain is possible if desired, but a unity gain amplifier can also be used. Since the output voltage is taken at the junction of resistors 32 and 42 rather than from node 48', the capacitances associated with the MOS transistors in switches 10, 12, 14 and 16 do not appear between this output and ground. Therefore, those capacitances do not affect the rate at which V0 varies with respect to the number to be converted, and so the speed of the device is significantly enhanced.
However, there are also some disadvantages associated with the D/A converter of FIG. 2. Since a single track 50 electrically connects all the A terminals of switches 10, 12, 14 and 16 to voltage reference potential VREF at node 48, the amount of current flowing through track 50, and consequently through track resistance 50', is dependent on whether each of the MOS transistors in switches 10, 12, 14 and 16, associated with the A terminals, are in the "on" or "off" condition.
For instance, if all the MOS transistors in switches 10 through 16, associated with the A terminal, are "on", a different current will flow through track 50 than would flow if only the MOS transistors associated with the A terminals in, for example, switches 10 and 12 are "on". This is because the MOS transistor associated with the A terminals in switches 14 and 16 are then "off", and the MOS transistors associated with the B terminals in those switches will be "on". Consequently, the currents I0 and I1 in those switches will flow through track 52 rather than track 50. Since the state of the MOS transistors ("on" or "off") in switches 10, 12, 14 and 16 is determined by the logic states of the bits in the digit signals D0 to D3 (either 1 or 0) which represent the number to be converted, the magnitude of the current which flows through track 50 is varied with combinations of different logic states in the digit signals D0 through D3 provided at the outputs of digital register 44.
Since the current through track 50 varies with different ones of these combinations of digit signals used in forming various input binary numbers, the voltage drop across track resistance 50' in track 50 will vary with these combinations as well. This varying voltage drop will cause varying voltage values to appear at the A terminals of switches 10, 12, 14 and 16 (i.e., the magnitude of the voltage appearing at point 49 on track 50), dependent upon the combination of values of bits in the digit signals D0, D1, D2 and D3 selected. Since the voltage at terminals A of switches 10 through 16 varies with combinations of the binary digital data stored in digital signal register 44, and since, as stated above, V0 is comprised of fractions of the voltage appearing at the terminals of switches 10 through 16, a linearity error will appear in V0. A linearity error is the deviation in actual output from a straight line passing through the end points of the transfer characteristic of the D/A converter.
Similarly, the current flowing through track 52 to ground terminal 15 will vary with respect to the state of the MOS transistor ("on" or "off") associated with B terminals in switches 10, 12, 14 and 16. Since track 52 also has a track resistance 52' associated with it, the value of the voltage reference potential which appears at B terminals of switches 10, 12, 14 and 16 will vary with respect to the binary number digital data represented by logic signals D0, D1, D2 and D3 provided at the outputs of digital signal register 44. The varying reference potential appearing at B terminals of switches 10, 12, 14 and 16 will add to the linearity error as well. This is because when the transistors associated with the B terminals in switches 10, 12, 14 and 16 are "on", the voltage potential at the B terminals will vary and will add varying voltage components to V0 causing V0 to be inaccurate.
The error which appears in V0, which is caused by varying currents through track resistances 50' and 52' of tracks 50 and 52, which is in turn determined by combinations of the logic states of digit signals provided in digital signal register 44, is called linearity superposition error. Although the linearity errors associated with any one digit signal D0, D1, D2 and D3 can be trimmed arbitrarily close to zero by laser trimming of the corresponding one of 2R valued resistors 24, 28, 30 and 32, the linearity superposition errors remain.
For instance, the linearity error associated with bit D0, if D0 were treated as the only bit in the D/A converter, could be trimmed to as close to zero as desired by laser trimming the resistance of resistor 24, having nominally a resistance of 2R, since the track resistance could be taken into account when trimming 2R resistor 24. Similarly, the linearity error due to binary digital bit D1 could be trimmed very close to zero by laser trimming the resistance value of resistor 28, again of nominally resistance 2R, assuming bit D1 was the only bit in the D/A converter of FIG. 2. However, the linearity superposition error caused by the various combinations of logic states which could be provided as in digit signals D0 and D1 at the corresponding outputs of digital register 44 cannot be trimmed to zero because of the track resistance portions which are common to both of them.
The linearity superposition error in the D/A converter of FIG. 2 can be mathematically suggested using the circuit approximation of FIG. 2A. For simplicity, a D/A converter of only three bits capability is used in FIG. 2A with resistor 32 of FIG. 2 assumed open and resistor 42 shorted. A track resistance r is assumed for simplicity for both track resistance 50' in track 50 between true voltage reference node 48' and the A terminal of switch 12, and track resistance 52' in track 52 between true ground reference terminal 15 and the B terminal of switch 12. There is also assumed to be no track resistance between the A terminals of switches 12, 14 and 16 on track 50, or between the B terminals of switches 12, 14 and 16 on track 52. This assumption is made again for simplicity because the track resistance in this length of track is either negligable or can be adequately dealt with using the trimming techniques discussed above.
Additionally, switches 12, 14 and 16 are assumed to be ideal (R.sub.ON =0). This assumption is reasonable since the voltage drops across switches 12, 14 and 16 can be made to be equal with respect to each switch in the D/A converter by scaling the length-to-width ratios of the MOS transistors used as switches in accord with the scaling of the currents chosen to pass therethrough. This keeps the "on" resistances proportional to the resistance effectively in series therewith to thereby minimize the trimming of such resistances and the area of such resistances which must be available for trimming.
As discussed above with respect to FIG. 2, the analog voltage V0 varies by fractions of the voltage appearing at the A terminals of switches 10, 12, 14 and 16, depending on the logic states in the corresponding digit signals D3 through D0. On this basis, for the similar three bit D/A converter shown in FIG. 2A, the sum of (i) the value of voltage V0 if the state of the digit logic signal D0 equals a one and the logic states in both of the remaining digit signals D1 and D2 equal a zero, plus (ii) the voltage value of V0 if the logic states in D0 and D1 each equal zero and that in D2 equals one, should equal the level of voltage V0 if both D0 and D2 have logic states of one and D1 has a logic state of zero. That is, the sum of the two voltages V0 developed in the first two conditions, where only one digit signal of the three has a value of one although a different digit signal in each condition, should equal the voltage value V0 developed in the further condition having both of these digit signals concurrently equal to one. In other words, V0.sub.100 +V0.sub.001 should equal V0.sub.101.
Using loop equations on the circuit of FIG. 2A with the switches connected appropriately, it is possible to determine the analog output voltage V0 corresponding to the three digit signal logic state value combinations or bit combinations in digit signals D0, D1 and D2 described above. These combinations again are 100, 001 and 101 for the digit signals being ordered D2, D1, D0.
For digit signals logic state combination 101: ##EQU1## For digit signals logic state combination 100: ##EQU2## For digit signals logic state combination 001: ##EQU3## Therefore, linearity superposition error of code 101 is: ##EQU4## and it follows that: EQU VOUT.sub.100 +VOUT.sub.001 .noteq.VOUT.sub.101
The linearity superposition error can be calculated in a similar fashion for any combination of bits in a D/A converter with any extension in the ladder network.
Elimination of the linearity superposition errors suggested in the above analysis for the circuit in FIG. 2A has been previously attempted. One attempt was to use very low resistance tracks for voltage and ground tracks 50 and 52, respectively. The use of these low resistance tracks would minimize track resistances 50' and 52' in tracks 50 and 52, respectively. Consequently, the linearity superposition errors would be lowered because the voltage drop across these track resistances, caused by varying currents in tracks 50 and 52, would decrease as the value of the track resistance decreased. However, without changing the length of the tracks or the resistivity of the material, the lowering of the resistance of the tracks requires the area of the tracks in a monolithic integrated circuit chip be increased. Consequently, this solution tends to require tracks 50 and 52 to take up an undesirable amount of area in a monolithic integrated circuit chip, thus increasing its cost.
Another method which has been previously used in an attempt to eliminate or reduce linearity superposition errors is to keep the length of the reference voltage tracks and ground tracks 50 and 52, respectively, as short as possible in the chip. By shortening the length of tracks 50 and 52, the resistance of the tracks can be decreased without changing the resistivity of the material or the area of the tracks. However, decisions such as chip connecting pin placement often determine where voltage reference node 48 and analog ground node 15 must be located. Consequently, tracks 50 and 52 cannot always be kept as short as desired, and the linearity superposition errors will then be too great to ignore in precision applications.
Although each of the above methods may be used with some success to reduce linearity superposition errors somewhat, neither of them can consistently reduce them to a point where it is not significant in precision applications.
USPTO Backgrounds
USPTO Backgrounds