The present invention is generally related to electrical circuits for interconnecting an electronic device, such as a microprocessor, and a synchronous state machine and, in particular, to an interface circuit and method for properly interconnecting an electronic device which operates at a device clock speed and an synchronous state machine that operates at a state clock speed wherein the device clock speed may be faster than the state clock speed.
Microprocessor speeds continue to increase due to advances in technology. It is likely that microprocessors having a clock speed of over 120 MHz will be common place. These increasing speeds have caused reliability problems when interconnecting the microprocessors to slower devices, such as synchronous state machines including field programmable gate arrays (FPGAs) and programmable array logic devices (PALs).
For reliable operation, the asynchronous input signals into a synchronous state machine must have two conditions. First, the input signals must be latched by a flip-flop in order to synchronize the input signals to the clock speed of the synchronous state machine to avoid metastability. Second, the pulse width of the input signals must be a minimum of one clock period of the synchronous state machine plus the setup time of the flip-flop.
These requirements cannot always be satisfied when interconnecting a fast microprocessor with a slower synchronous state machine. In particular, the requirement that the input signals have pulse widths at least as long as one clock period of the synchronous state machine cannot always be met.
These problems could be substantially obviated by manufacturing faster synchronous state machines. However, faster synchronous state machines would be prohibitively expensive and commercially unfeasible. Consequently, the microprocessor is typically operated at a slower speed. As is readily apparent however, this results in less than optimal operation of the microprocessor. The advantages of having the faster speed microprocessor are thus somewhat negated.
Accordingly, there is a need in the art for an interface circuit and method for interconnecting an electronic device operating at a device clock speed and a synchronous state machine operating at a state clock speed wherein the device clock speed may be greater than the state clock speed.
USPTO Backgrounds
USPTO Backgrounds