As the area occupied by various semiconductor elements in semiconductor devices such as a dynamic random access memories (DRAMs) has been reduced by increased integration, a cell capacitance should be maintained constant or increased. Some methods used to ensure a sufficient cell capacitance within a limited area include using a high dielectric material as a dielectric film, reducing a thickness of a dielectric film, and/or increasing an effective area of a lower electrode. Using a high dielectric material may require large investments such as the introduction of new equipment, assurance of reliability, mass-production of dielectric films, use of subsequent low temperature processes, etc. Accordingly, methods of increasing the effective area of a lower electrode may be relatively easy to realize because conventional dielectric films may be used.
Methods of increasing the effective area of the lower electrode may include approaches such as making three-dimensional lower electrodes such as cylindrical or fin shape lower electrodes, growing hemispherical grains (HSGs) on lower electrodes, and/or increasing the height of lower electrodes. When growing HSGs on lower electrodes a critical dimension (CD) between the lower electrodes may be difficult to secure. Because HSGs may be detached from the lower electrodes and may cause bridges between the lower electrodes, growing the HSGs may be difficult to apply to a semiconductor device having a design rule of 0.14 μm (micrometer) or less. Accordingly, a method of making lower electrodes into a three-dimensional shapes and increasing a height thereof has been used to increase cell capacitance. Lower electrodes may also be formed into a cylindrical or a stack shape.
In the case of cylindrical or stack type electrodes, both external and internal surfaces of the electrodes can be used, thereby increasing effective electrode surface areas. For cylindrical or stack type electrodes having an integrated one cylinder stack (OCS) structure, however, a height of the lower electrodes may be increased to ensure a capacitance greater than a certain level required for the operation of a semiconductor device. Thus, such electrodes may collapse or break before the deposition of a dielectric material.
One of the main reasons that lower electrodes may collapse is a surface tension of a cleaning liquid used in a cleaning liquid-drying process after wet etching of a mold oxide film. Expansion of the area of an electrode by conventional methods may be limited due to collapsing of the lower electrodes, and a method of forming supporting pads has been devised to address this problem.
Conventional supporting pads may be formed in the shape of a lattice, and when the lattice supporting pads are formed, the lower electrodes may be twisted because the supporting pads apply stress to the lower electrodes. In addition, a material used in a subsequent process may not be symmetrically and uniformly deposited because the interval between the lower electrodes may be too narrow due to the lattice support pads. Furthermore, the non-uniformly deposited subsequent materials may increase the stress applied to the lower electrodes.
Therefore, when the lower electrodes collapse, break, or are twisted due to the stress applied by the pads, bridges or leakages may be caused between cells, thereby causing defects in semiconductor devices.
Meanwhile, in conventional semiconductor devices having an OSC structure, a plate electrode and a metal plug may be formed after a capacitor is formed. In order to form the metal plug, a planarization process may be used after an oxide film having a thickness greater than an OCS level difference is deposited. Thus, the oxide film may need to be deposited up to 30,000 Å (Angstroms) or more according to the height of the OSC structure, and then an excess chemical mechanical polishing (CMP) process may be performed to remove the level difference of the oxide film after the deposition process. That is, an excess CMP process may be used to thin the deposited oxide film by about 3,000 to 4,000 Å (Angstroms). Accordingly, a distribution of CMP slurry (quantity) on the water may deteriorate, and the thickness of the oxide film after the CMP process is performed may not be sufficiently uniform. The non-uniform thickness of the oxide film may cause open CD distribution deterioration during an etch used to form subsequent metal plugs, thereby decreasing product yield.
USPTO Backgrounds
USPTO Backgrounds