In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals produced by an IC tester at its appropriate pins at predetermined test timings and waveforms. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed at predetermined timings and results are compared with expected data to determine whether the IC device functions correctly.
The assignee of this invention has developed an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. In an event based test system, test data is described in terms of event and its timing where events are any changes of the logic state in the signals used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals (drive events) or occurrences of strobe signal (strobe events or sample events). Typically, a timing of each event is defined either as a time length from the most recent event (immediately prior to the current event) or the absolute time of an event.
The basic design of the event tester is disclosed in U.S. Pat. Nos. 6,532,561 and 6,360,343, which is briefly described here. An example of basic structure in the event based test system is shown in a block diagram of FIG. 1. In the example of FIG. 1, the event based test system includes a host computer 12 and a bus interface 13 both are connected to a system bus 14, an internal bus 15, an address control logic 18, a failure memory 17, an event memory 30 consisting of an event count memory (event count RAN) 20 and an event vernier memory (event vernier RAM) 21, an event summing and scaling logic 22, an event generator unit 24, and a pin electronics 26. The event based test system evaluates a semiconductor device under test (DUT) 28 connected to the pin electronics 26.
An example of the host computer 12 is a work station having a UNIX, Window, or other operating system therein. The host computer 12 also provides a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and other test conditions, or to perform test result analysis in the host computer. The host computer 12 interfaces with a hardware test system through the system bus 14 and the bus interface 13.
The internal bus 15 is a bus in the hardware test system for interfacing the functional blocks such as the address control logic (address controller) 18, failure memory 17, event summing and scaling logic 22, and event generator 24. An example of the address control logic 18 is a tester processor which is exclusive to the hardware test system. The tester processor (address control logic) 18 provides instructions to other functional blocks in the test system based on the test program and conditions from the host computer 12 as well as to generate address data for event memory 30 and failure memory 17. The failure memory 17 stores test results, such as failure information of the DUT 28. The information stored in the failure memory logic 17 is used in the failure analysis stage of the DUT.
In an actual test system, a plurality of sets of event count memory and event vernier memory will be provided, each set of which typically corresponds to a test pin of the test system. The event count and vernier memories 20 and 21 store the timing data for each event of the test signals and strobes. The event count memory (RAM) 20 stores the timing data which is an integer multiple of the reference clock (event count data), and the event vernier memory (RAM) 21 stores timing data which is a fraction of the reference clock (event vernier data).
The event summing and scaling logic 22 is to produce a signal showing overall timing of each event based on the timing data from the event count memory 20 and the event vernier memory 21. Basically, such overall timing signal (event enable) is produced by summing the event count data (integer multiple data) and the event vernier data (the fractional data). During the process of summing the timing data, a carry over operation of the fractional data (offset to the integer data) is also conducted in the timing count and offset logic 22. Further during the process of producing the overall timing signal, timing data may be modified by a scaling factor so that the overall timing can be modified accordingly.
The event generator 24 is to actually generate the events based on the overall timing signal and the vernier sum data from the event summing and scaling logic 22. Typically, an event is generated by delaying the overall timing signal by the value shown in the vernier sum data. The events (drive events and/or strobe events) thus generated are provided to the DUT 28 through the pin electronics 26. Basically, the pin electronics 26 is formed of a large number of components, each of which includes a driver and a comparator as well as switches to establish input and output relationships with respect to the DUT 28.
For producing high resolution timings, as noted above, the time length (delay value) between the events is defined by a combination of an integral part of the reference clock (event count data) and a fractional part of the reference clock (event vernier data). A timing relationship between the event count and the event vernier is shown in a timing chart of FIGS. 2A–2D. In this example, a reference clock (ex. master clock) of FIG. 2A has a time period T. The timings of Event 0, Event 1 and Event 2 of FIG. 2C are related in a manner shown in FIG. 2C. To describe the timing of Event 1 with reference to Event 0, the time difference NT+ΔT between the two events is shown in FIG. 2B where N denotes the event count data, T is a reference clock period, and AT denotes the event vernier data which is a fraction of the reference clock period T.
The type of event is either a drive event shown in FIG. 2C or a sampling (strobe) event shown in FIG. 2D. A drive event drives a tester pin or a DUT input pin to a specific voltage level. A strobe event samples the output of the DUT pin at its timing. Ordinarily, a strobe waveform has no or almost no pulse width because it defines a single timing for sampling the output of DUT. However, as shown in FIG. 20D, there is another type of strobe having a significantly large pulse width, i.e, a window strobe, which is one of the subjects of the present invention.
As noted above, in an event based test system, the event data in the event memory is expressed by a time difference between the current event and the previous event. Thus, to produce events according to the event data, an event based test system must be able to calculate the sum of the delays of each event up to the current event. This requires a logic in the test system to keep counting of the delay times expressed in the event count data and the event vernier data from the event memory 30.
In the U.S. Pat. Nos. 6,360,343 and 6,557,133 and U.S. application Ser. No. 10/318,959 (Publication No. US-2003-0229473), owned by the same assignee of this invention, it is disclosed an event summing and scaling logic for calculating a timing of the current event using the event data from the event memory. In the event summing and scaling logic disclosed in the prior inventions, however, high speed reproduction of events was not fully established with use of pipeline processing. Further, compression technology is used for storing the event data in the event memory for saving the memory space. In the event summing and scaling logic disclosed in the prior inventions, high speed processing of decompressed vernier events is not fully established with use of parallel pipelines.
Therefore, what is needed is an event processing apparatus and method for a high speed event based test system which is able to perform high speed event timing processing with use of pipeline structure.
USPTO Backgrounds
USPTO Backgrounds