The fabrication of semiconductor circuits involves many process steps for forming active and passive components in a semiconductor substrate. Many of the processing steps are carried out at high temperatures for depositing dopants or materials in or on the surface of the semiconductor wafer. Furnaces especially adapted for processing semiconductor wafers in a controlled environment are commercially available. Wafer processing furnaces generally include a quartz cylinder in which the wafers are disposed in an evacuated chamber. Temperatures generated by the furnace and conducted to the quartz chamber are typically in the range of 400.degree. C. to 700.degree. C., depending upon the particular process and materials involved. Further, the quartz tube has an inlet and outlet through which various gases can be passed to subject the semiconductor wafers to the desired temperature, as well as various chemical compositions according to a recipe. It is well known that optimum performance and yield of the wafers are dependent upon the uniformity of temperature and gas distribution within the quartz chamber.
While many different types of wafer processing furnaces are available, many such furnaces utilize a quartz chamber having a frontal flanged opening. A wafer paddle assembly, including the furnace door, is externally movable, generally under computer control, for moving the paddle assembly into the horizontally situated quartz chamber. The paddle assembly holds a number of wafers at the end thereof, and has affixed thereto the furnace door that seals to the opening when the paddle assembly is fully inserted into the quartz chamber. The chamber is pumped down to a desired vacuum, the furnace is heated to a desired temperature, and then the appropriate gases are passed through the quartz chamber for depositing various material layers on or in the wafers. Such a process is commonly known as chemical vapor deposition (CVD). Many other processes can be carried out with such furnaces. As noted above, optimum processing occurs in the quartz chamber at a certain location, termed a "sweet spot", where the temperature and chemical composition are maintained at desired parameters prescribed in the processing recipe. By trial and error techniques, or by conducting tests on test wafers, the exact sweet spot location and size of each furnace can be found. In order to precisely place the semiconductor wafers in the sweet spot, the paddle assembly often requires vertical or horizontal adjustments. The paddle assembly itself can generally accommodate small adjustments in a vertical or lateral direction without substantially affecting the seal of the door to the quartz chamber. However, situations often arises in which the paddle assembly cannot be adequately ad3usted in the sweet spot without affecting the seal between the furnace door and the quartz chamber. In this situation, wafer processing must be carried out at a location in the chamber that is suboptimal, thereby compromising the yield of the die on each wafer. As a result, the cost per circuit die increases, and sometimes entire batches of wafers are destroyed or unusable due to an inadequate vacuum seal between the furnace door and processing chamber.
From the foregoing, it can be seen that a need exists for an apparatus and technique for allowing adjustability between the paddle assembly and the furnace door so that a wider degree of adjustability is afforded, without affecting the seal between the furnace door and the temperature chamber. Another need exists for a technique providing the noted adjustability that is simplified and does not require precision equipment, apparatus or a high degree of operator expertise.
USPTO Backgrounds
USPTO Backgrounds