Integrated circuits are vulnerable to a phenomenon generically referred to as electrostatic discharge ("ESD"). During handling, integrated circuits can build up relatively large static charges on their inputs. These charges, if not properly compensated for, may flow or "discharge" to a lower potential region. Discharging in this way produces large electric fields within the transistors that are immediately connected to the various inputs and outputs of a particular circuit. High electric fields in turn, produce high temperature gradients and ultimately yield electrothermo migration ("ETM") within the transistor. ETM describes how a transistor fails when the contact metallization migrates across the transistor under the combined effects of electrical and thermal stress to produce a short. ETM causes irreversible circuit failures. ESD and ETM become more severe as circuits dimensions decrease. The smaller the dimension of, for instance, a doped drain region, the higher the electric field will be per charge. As a result, new semiconductor technologies require more effective designs to overcome these problems.
USPTO Backgrounds
USPTO Backgrounds