1. Technical Field
The disclosure relates to a clock generator and clock generating method, and more particularly, to a phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method.
2. Related Art
Phase interpolator has been widely when using two clock sources to generate a multiple of multi-phase clocks.
FIG. 1 is a schematic diagram showing a multi-phase interpolation device 10, while FIG. 2 is a timing diagram of the input clocks c1 and c2 of the multi-phase interpolation device 10 as well as the output clock signals p0˜pm thereof.
Please refer to FIGS. 1 and 2, in which multi-phase interpolation device 10 receives two input clocks c1 and c2 and generates m+1 output clock signals p0˜pm, wherein in is a positive integer greater than zero.
A time spacing between the two input clocks c1 and c2 is shown as Δ in the figure, in other words, the input clock c1 and the input clock c2 have the same waveform, but the input clock c1 has a leading phase difference Δ with respect to the input clock c2. The output clock signal p0 is equivalent to the input clock c1 having a delayed phase difference δ, and the output clock signal pm is equivalent to the input clock c2 having a delayed phase δ. Furthermore, the rest output clock signals p1˜p(m−1) are obtained by interpolating the input clocks c1 and c2. Additionally, the output clock signals p0˜pm have an equal time spacing between each other. In other words, there is a phase difference Δ/m between any two adjacent output clock signals. The phase difference Δ/m indicates a least significant bit (LSB).
How to interpolate uniform multi-phase output clock signals is one of the circuit design emphases for the present multi-phase interpolation device 10.
USPTO Backgrounds
USPTO Backgrounds