A non-volatile memory AND-array is known from international application WO 94/10686.
The AND-array comprises a plurality of memory cells which each consist of a stacked gate transistor comprising a floating gate which is capable of storing electric charge and a control gate which is capable to control operations on the floating gate, i.e., reading, writing, and erasing.
In the AND-array configuration, the memory cells are arranged in rows and columns. Memory cells in the same row share a word-line which is connected to each of their control gates. Memory cells in the same column share one bit line which is connected to each of their sources and another bit line which is connected to each of their drains.
The AND-array configuration may be an alternative for memory arrays with two-transistor (2T) memory cells. For instance, both array configurations allow programming by means of Fowler-Nordheim (FN) tunneling. In 2T memory cells, the stacked gate transistor is paired with an additional access transistor.
In earlier process generations the size of a memory cell in an AND-array was typically larger than in a 2T-array because the need for two bit lines per cell imposed a much larger column pitch, but for more advanced process generations (“break-even” is around the 90 nm node), the AND-array configuration may offer a smaller cell size than 2T mainly due to the fact that the length of the access transistor of a 2T memory cell can not be downscaled further, leading to a much larger row pitch in the 2T configuration.
Moreover, the AND-array configuration may provide a larger read current than the 2T configuration which can favorably be applied in a non-volatile memory AND-array based on SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) or other charge trapping cells. This higher read current can be realized thanks to the absence of the access gate (AG) transistor, which in series with the control gate transistor limits the current in a 2T cell. Additionally, in the AND-array configuration a higher program inhibit voltage can be applied than in the 2T configuration. In the 2T configuration, a higher program inhibit voltage would cause punch-through of the access transistor, but obviously in the AND-array configuration this is not an issue, since both bit lines can be biased at the inhibit voltage.
In non-volatile semiconductor devices based on SONOS, charge can be stored in the silicon nitride layer of the ONO stack by a mechanism of (direct) tunneling of electrons through the bottom silicon dioxide layer (tunnel-oxide layer) from the current carrying channel to the silicon nitride layer.
The charge trapping properties of the silicon nitride layer allow for downscaling the thickness of the tunnel-oxide layer, which may result in lower program/erase voltages.
Alternatively, the “SONOS” material stack can comprise other materials than SiO2 or Si3N4, such as Al2O3, HfO2, HfSiO, HfSiON, ZrO2, etc. For the sake of clarity, the entire class of charge trapping cells is referred to as “SONOS” in the remainder of this document.
Disadvantageously, SONOS memory devices suffer from a gate disturb effect, for example during the read action.
Gate disturb relates to a disturbance of a threshold voltage VT of a memory cell and is caused by exposure to a relatively large voltage difference between the channel region of the cell and the control gate, leading to a relatively large electric field in the ONO stack, which can gradually change the charge in the nitride by soft programming or soft erase. As a consequence the level of the threshold voltage VT which defines the memory state, or bit value, of the memory cell (being either ‘0’ or ‘1’, depending on the actual threshold voltage of the memory cell being above or below the voltage applied to the control gate during read, VCG,read), tends to change gradually over the lifetime of the memory cell.
For example, gate disturb due to the application of a voltage on the control gate of the memory cell during a read operation may cause a slow programming of the memory cell, i.e., some tunneling takes place during reading.
Also, in comparison to non-volatile memory devices based on a floating gate, SONOS memory devices suffer from a relatively low data retention capability. On the other hand, an advantage of SONOS-like memories is the absence of strong extrinsic behavior, i.e., the behavior of different cells is to a great extent identical.
USPTO Backgrounds
USPTO Backgrounds