1. Field of Use
This invention relates to memory systems containing semiconductor memory elements including those in which stored information must be periodically refreshed to preserve the integrity of such information.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in U.S. Pat. No. 4,236,203, assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide system bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a cycle of operation which consists of a series of response cycles.
It will be noted that in such double word fetch memory module systems, it is necessary to generate and decode even and odd addresses for accessing both memory modules. Such an arrangement for accomplishing the required address generation/decoding is described in U.S. Pat. No. 4,185,323 which is assigned to the same assignee as named herein.
In the above arrangement, the low order bits of the address provided with the memory request specify the storage location being accessed while the high order bits specify which pair of rows DRAM chips is being selected.
The address arrangement includes a primary address register which also served as a counter and two parallel secondary address registers. In carrying out a double fetch operation, the initial address was loaded into the primary address register and then stored in the appropriate secondary address register. Then the memory subsystem, after signalling it was busy, incremented the initial address contents of the primary address register by one and the resulting address was then stored in the other secondary address register. Because of the additional time required to generate the second address, the memory timing circuits included circuits for generating two sets of clocking signals and for steering the sets of clocking signals to the appropriate memory module units. This was necessary to enable the read out of the pair of words into the subsystem data output registers in time for transfer to the bus.
To reduce this additional time, another arrangement employed sequential chip select decode apparatus which would provide a pair of decodes according to the least significant address bits for simultaneously accessing a pair of words from even and odd memories. A system which utilizes this arrangement is disclosed in U.S. Pat. No. 4,323,965 which is also assigned to the same assignee as named herein. While the system provided a double fetch capability with less circuits than the prior art, it still required circuits for accessing at least a pair of memories. Moreover, as the capacities of these memories become more dense, it becomes desirable to provide the double fetch memory in smaller increments. However, this is not possible in those prior art systems which provide a double fetch capability.
Accordingly, it is a primary object of the present invention to provide a low cost memory subsystem which incorporates a double fetch capability.
It is a further object of the present invention to provide a double fetch memory subsystem which can be implemented with a minimum of circuits.
USPTO Backgrounds
USPTO Backgrounds