1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and more particularly to an input voltage sensing circuit for sensing whether a voltage of an input signal is higher or lower than a predetermined normal level.
2. Description of the Related Art
In a semiconductor integrated circuit, for example, a CMOS type semiconductor memory, an address signal or a control signal is inputted from an outer unit, and such input signals are changed between a power supply voltage VDD and a reference voltage VSS at the time when the memory is normally operated. There is a case in which the input voltage of a particular input signal is set to be higher than the voltage of the normal operation time so as to change the memory from the normal operation mode to a test mode by use of the input signal.
An input voltage sensing circuit, which is provided in the memory so as to detect whether the voltage of such an input signal is higher or lower than a predetermined normal level, is conventionally structured as shown in FIG. 1.
More specifically, an input signal terminal 10 and a source of a PMOS transistor TP are connected to each other. A drain of the PMOS transistor and one end of a resistor element R are connected to each other, and another end of the resistor element R is connected to a reference voltage VSS (ground voltage in this case). The drain of the PMOS transistor TP is also connected to an input side of an inverter IV, which is one of input portions of an internal circuit, and a gate of the PMOS transistor TP is connected to a predetermined normal voltage (e.g., power supply voltage VDD of the memory). It is noted that other ordinary input circuits (not shown) are also connected to the input signal terminal 10.
FIG. 2 shows power supply voltage VDD dependency of a circuit threshold value Vt of the above-structured input voltage sensing circuit. More specifically, the threshold voltage of the input voltage sensing circuit corresponds to the sum of an absolute value .vertline.Vtp.vertline. of a threshold value of the PMOS transistor TP and the power supply voltage VDD.
In this circuit, when the input signal is changed between the normal power supply voltage VDD and the reference voltage VSS, the PMOS transistor TP is turned off, an output signal of the inverter IV is set to be an "H" level, and the memory circuit to be connected thereafter is set to be in the normal operation mode.
On the other hand, when the input signal voltage VIN is higher than the normal voltage VDD by the absolute value .vertline.Vtp.vertline. of the threshold value of the PMOS transistor TP or more (VIN .gtoreq.VDD +.vertline.Vtp.vertline.), the PMOS transistor TP is turned on, the output signal of the inverter IV is set to be an "L" level, and the memory circuit to be connected thereafter is set to be in the test mode.
However, the following problem is found out in the conventional input voltage sensing circuit.
In the system using memory devices, there is a case in which the power supply voltage VDD is lowered to reduce power consumption of the memory devices in standby state. At this time, there occurs a case in which the supply voltage of the input signal (provided from the outer unit of the memory) is not lowered. In this way, in the case that the source voltage of the input signal is maintained to be the power supply voltage corresponding to the state in which the memory is in the normal operation, the following problem will occur. When the voltage of the input signal is in an "H" level and becomes higher than the current lowered power supply voltage VDD, which is supplied to the input voltage sensing circuit, by the absolute value .vertline.Vtp.vertline. or more, the input voltage sensing circuit erroneously senses that the test mode is designated.
In order to solve the above problem, it can be considered that .vertline.Vtp.vertline. of the PMOS transistor of the input voltage sensing circuit is increased. However, in this case, it is needed that the voltage VINTM (VINTM .gtoreq.VDD +.vertline.Vtp.vertline.) of the input signal, which is used to designate the test mode when the memory is normally operated (i.e., a state where the power supply voltage VDD is returned to the normal value), should be much higher than that in the case where the PMOS transistor having the normal threshold value is used, in accordance with the increase in .vertline.Vtp.vertline. of the PMOS transistor. As a result, voltage stress, which is much larger than that in the normal operation mode, is applied to an input line of the input voltage sensing circuit when the test mode is designated. As a result, there is possibility that a characteristic of a peripheral circuit will be deteriorated.
USPTO Backgrounds
USPTO Backgrounds