1. Field of the Invention
This invention relates to the deposition of coplanar thin films atop substrates. In particular, it relates to a method for forming a conductive pattern which is coplanar with its adjacent insulator. When applied to multiple levels the method thereby eliminates rough or uneven surfaces at the upper levels of multi-level structures.
2. Description of the Prior Art
The introduction of a process for depositing planar glass atop metallic stripes or thin films on substrates has made it possible to adequately insulate the stripes as well as avoiding steps, bumps, or depressions in the glass covering the stripes. Such a process is described in copending application of Auyang et al., Ser. No. 512,781 filed Dec. 31, 1970, now U.S. Pat. No. 3,983,022. The application is assigned to the assignee of the present invention. Such complete planarization of insulating layers is particularly desirable in structures having several layers of metallurgy separated by several levels of insulation material. The cumulative effects of several levels of raised metallization on succeding insulating layers is progressively more pronounced and undesirable.
Although the basic resputtering process of Auyang et al., has been successful, it has not led to satisfactory planarized, multi-level metallurgies. In the first place, the degree of planarity achievable in the basic planarization process depends on the width of the metallic stripes. The complete planarization of an insulating layer deposited over a metallic stripe of conventional width, from 300 to 1500 microinches, may take as much as 24 hours. This is an inordinate amount of time. In addition, there may be wide variations between the widths of the various lines and stripes on the substrate which introduce a time factor making complete planarization impractical.
Another, perhaps more significant, problem in attempting to form multi-levels of metallization with the basic planarization process is the necessity for forming via connections through the insulating layer covering each metallic level. At present, via holes are generally etched in the insulating layer; and a subsequent level of metallization is selectively deposited through the via holes to interconnect with the lower level.
However, etching of the insulator, no matter how controlled the process, tends to result in shorts and pinholes between levels. This requires a thicker insulation layer than would be expected.
In addition, the dielectric etching process materially restricts the density of the metallic stripes unless different types of dielectric materials are used for contiguous levels. It is ordinarily necessary to provide for the possiblity of locating two via holes in adjacent parallel lines in side-by-side relation on the substrate. Photolithographic and masking technology requires that the diameter of a via hole at the top of the dielectric or insulating surface be at least 0.25 mils. A conventional pad which interconnects levels of metallurgy must overlap the via hole by at least 0.15 mils or else a sharp-pointed, upperly-extended lip occurs about the via hole which is detrimental to mask life. It is also difficult to deposit a layer of metal or glass over the pad. This requires that the pads have a diameter of 0.55 mils. Because adjacent pads must be located at least 0.2 mils apart, the minimum center-to-center spacing between two parallel, adjacent conductive stripes is of the order of 0.75 mils. In an ideal structure, i.e., one which did not require pads over the via holes, the stripes could be spaced at 0.5 mils center-to-center distance.
Still another problem encountered in present-day manufacturing is the practical impossibility of making one feedthrough, or via stud, connection directly atop another. In fact, the fabrication of coincident feedthroughs is rarely, if ever, attempted even though some wiring designs would benefit thereby.
The difficulty lies with the extremely non-planar topography of the metal deposited in the coincident via holes. This results in very thin metal sidewalls, metal spike formations and photoresist coverage problems. The thin sidewalls pose severe electric problems because of the extremely high current densities in these regions.
USPTO Backgrounds
USPTO Backgrounds