The present application relates to methods of manufacture of photolithographic reticles, i.e. masks, and reticles produced thereby. More particularly the present application relates to methods for fabrication of reticles for exposure of microelectronic integrated circuits and other micro-scale devices and to the reticles produced thereby.
During the process of manufacturing of microelectronic integrated circuits on a substrate comprising a workpiece such as a semiconductor wafer or the like, layers of material on the workpiece are patterned photolithographically. A layer of a radiation sensitive resist (hereinafter resist) is deposited on the workpiece. The resist (e.g. photoresist) comprises a radiation sensitive material which can be exposed to a master image projected as patterns of radiation, e.g. light, ultraviolet light, x-ray, electron beam, or other forms of radiation. The resist is later exposed using an exposure tool and a reticle. The reticle comprises a photomask or the like which is patterned with opaque regions, transparent regions and possibly partially transparent regions. During the exposure process, radiation is directed onto the reticle to expose the resist selectively with patterns of radiation projected through the reticle.
The resist is developed, and then the remaining resist forms a mask on the workpiece which protects areas of the workpiece during subsequent fabrication processes, such as deposition, etching, or ion implantation. A mask or photomask is generally used for photoimaging with a positive or negative image when exposing a photosensitive material known as photoresist or analogous materials sensitive to electromagnetic or other forms of radiation.
Binary Reticle
A binary reticle includes a pattern corresponding to features to be formed on work pieces such as FET devices or other Integrated Circuit (IC) features. A binary reticle may be formed on a reticle mask plate comprising a transparent glass plate coated with a patterned, opaque (light blocking) material. This type of reticle is typically referred to as a binary mask since some of the light is completely blocked by the opaque material and the remainder of the light is fully transmitted through the transparent, glass portions.
Chrome on Glass (COG) Binary Reticle
A Chrome-On-Glass (COG) reticle (i.e. a mask, photomask, or photoreticle) typically comprises a quartz-chrome patterned mask. In more detail, a COG reticle comprises a single crystal quartz reticle mask plate that is substantially planar, which carries a mask pattern defined using a patterned chrome (Cr/CrO2) layer, formed by sputtering. The chrome layer is laminated to the top surface of the reticle mask plate. A virgin or blank COG reticle mask plate or mask blank comprises a virgin reticle which has not been patterned. In other words, a virgin COG reticle comprises an unpatterned or blank planar layer of chrome deposited on a quartz reticle mask plate.
In the production of a COG patterned reticle, e.g. an Integrated Circuit Device (ICD), an image of one or more microelectronic devices is printed onto a virgin COG reticle via a lithographic process by exposure to radiation. A layer of resist is applied to the blank COG reticle mask plate covering the top surface of the chrome layer. After patterning by exposure of the resist to a master image, the resist is developed to reproduce the exposed pattern thereby producing openings down to the surface of the chrome of the COG mask. Exposed surfaces of the COG mask are removed by etching leaving the remaining portions of the chrome layer intact. Then the resist is removed with appropriate chemicals and washed away.
In the context of photolithography, the term reticle refers to a semiconductor photomask, which contains an image which is adapted to expose only a small part of a semiconductor wafer which is to be employed in a step-and-repeat exposure system, i.e. a wafer stepper or scanner. A semiconductor reticle typically contains the pattern of a several semiconductor devices. The reticle is employed in the wafer stepper to project an image to be exposed over and over onto a workpiece comprising a semiconductor wafer covered with unexposed photoresist by moving the workpiece relative to the reticle with the wafer stepper or scanner, which is employed to expose several areas of the unexposed photoresist repeatedly and sequentially.
In addition to visible light, the absorber may be capable of absorbing radiation such as infra-red, x-ray, E-beam, or light in ranges such as the UltraViolet (UV) range, Deep UltraViolet (DUV) range, Vacuum UltraViolet (VUV) range, and Extreme UltraViolet range (EUV).
The present application relates to processing of integrated circuit devices and particularly to the manufacturing of optical projection masks for deep submicron (<0.25.μm) integrated circuit processes.
A common method of manufacturing of projection reticles for exposure of integrated circuit devices has relied on etching a pattern into an actinic radiation absorber comprising a layer of absorbent material which is deposited on a reticle mask plate (i.e. a transparent substrate or mask blank.) Currently in semiconductor fabrication the patterning of structures on a substrate is often performed with reticles defined by lithography performed on a blank COG reticle.
There is a serious problem with the process of etching through the chrome of a COG reticle mask plate down to the quartz therebelow which is that the etching process for the chrome also consumes the photoresist mask very quickly which forces certain restrictions in the mask making process (e.g. resist thickness.)
There are other serious problems with etched COG reticles. One such problem with etched COG reticles is that Electro-Static Discharge (ESD) can cause damage to the metal (chrome) pattern on a substrate composed of quartz as the insulating material. The problem is that unwanted Electro-Static Discharge (ESD), involving rapid dissipation of electric charge in a short amount of time, often causes delamination of the chrome pattern from the quartz substrate. In other words, at least a portion of the chrome pattern on the quartz substrate is lifted away from the top surface thereof, as the ESD energy is being dissipated in the laminated material. That renders the mask defective so that it is not useful for the fabrication of devices on semiconductor substrates.
Another serious problem with COG reticles is that they grow defects over the lifetime of the mask which limits the useful lifetime of such reticles and forces regular cleaning.
Phase Shift Mask (PSM)
Another type of reticle is the Phase Shift Mask (PSM), which can be produced by allowing some light to pass through a partially-transmissive chrome feature thereby changing the phase of the light that passes therethrough, i.e. creating phase shifted light. The phase shifted light from the partially-transmissive feature affects the interference pattern of the light transmitted from neighboring fully transparent areas, resulting in a higher contrast at the imaging plane. This allows imaging features with significantly smaller feature sizes than would be possible using the same mask pattern implemented as a standard COG reticle. These reticles are referred to as attenuated PSM (AttPSM) reticles.
Alternating PSM (AltPSM) Mask
A third type of reticle is known as an Alternating PSM (AltPSM) reticle (mask) wherein feature recesses are etched into the virgin reticle mask plate. The feature recesses result in a path length difference for the light passing therethrough, and the depth of the feature recess is tuned to result in a 180° phase shift of the incident electromagnetic radiation to be used in exposure of the image on the reticle. The AltPSM mask has limitations in that the termination of features can be difficult and a second mask called a block out has to be used in conjunction therewith to terminate the features that are desired on the substrate. The higher cost of these AltPSM reticle processes is negligible in view of expenses saved as compared to more advanced lithography tooling that would be required when only COG reticles would be used. However the cost of fabrication of a mask set has increased dramatically by introducing those extra processing steps required for AltPSM reticle processing.
Commonly assigned U.S. Pat. No. 5,932,377 of Ferguson et al. entitled “Exact Transmission Balanced Alternating Phase-Shifting Mask for Photolithography” describes forming an AltPSM mask with etched-quartz trenches. It states that a phase difference between two clear shapes for an AltPSM is achieved in standard industry practice by selectively etching into a quartz reticle mask plate so an optical path difference equivalent to the desired phase offset is obtained between two adjacent openings. After standard mask patterning, a second write step is used to selectively open a protective resist coating for a phase-shifted opening leaving a non-phase shifted opening covered. Typically, the quartz is then etched with an anisotropic Reactive-Ion Etching (RIE) process.
Commonly assigned U.S. Pat. No. 5,565,286 of Lin entitled “Combined Attenuated-Alternating Phase Shifting Mask Structure and Fabrication Methods Therefor” describes a structure and fabrication method for a phase-shifting lithographic mask. AltPSM and AltPSM are combined to provide a mask combination consisting of phase-shifted and unshifted attenuated backgrounds in which the phase-shifted attenuated background surrounds the unshifted components and the unshifted attenuated background surrounds the phase-shifted components.
U.S. Pat. No. 6,660,653 of Tzu et al. entitled “Dual Trench Alternating Phase Shift Mask Fabrication” describes fabricating a dual-trench AltPSM mask. A chromium layer formed over a quartz layer of the PSM is patterned with deep trenches by dry etching through a photoresist layer. The quartz layer is dry etched through another photoresist layer applied over the chromium layer and patterned according to the deep trenches and the shallow trenches of the AltPSM design using backside exposure to ultraviolet light.
Damascene Patterning
Traditionally, the term damask refers to rich tapestry patterns of damask silk, such as a figured fabric of silk, wool, linen, cotton, or synthetic fibers, with a pattern formed by weaving. An artistic damascene process of metal work involves inlaying metal into trenches in another metal is a process of inlaying different metals into one another, e.g. gold or silver into a darkly oxidized steel background, to produce intricate patterns.
In semiconductor technology, damascene or dual-damascene metal patterning processes have been employed in forming copper interconnects in a dielectric layer, e.g. silicon oxide, for external electrical connections and interconnections of semiconductor devices. The semiconductor damascene process starts by a subtractive process of etching open trenches reaching down into a dielectric layer wherein copper conductor patterns are to be formed. An additive patterning process is employed involving deposition of a conformal barrier layer followed by deposition of a blanket (thick) coating of copper that significantly overfills the trenches. Then, the excess copper is removed by planarization to the level of the top of the insulating layer by Chemical-Mechanical Polishing (CMP). The copper, which remains within the trenches of the insulating layer, comprises a patterned interconnect conductor.
U.S. Pat. No. 6,821,192 of Donohue entitled “Retaining Ring for Use in Chemical Mechanical Polishing” describes a retaining ring for use on a carrier head in a Semiconductor Wafer CMP (SWCMP) apparatus with a bottom surface, an inner surface and an outer surface, and a plurality of recesses on the bottom surface. Each recess includes an inner trailing surface and a slurry capture area. A channel connects the slurry capture area to the inner surface. The inner trailing surface can be configured for fastening thereon an insert tool having a contact edge for abrasively contacting a polishing pad. The Donohue patent states “Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes successively less planar. This non-planar outer surface presents a problem for the integrated circuit manufacturer as a non-planar surface can prevent proper focusing of the photolithography apparatus. Therefore, there is a need to periodically planarize the substrate surface to provide a planar surface. Planarization, in effect, polishes away a non-planar, outer surface, whether a conductive, semiconductive, or insulative layer, to form a relatively flat, smooth surface.”
Transmissivity, τ and Opacity
Transmissivity in the context of this invention is defined as the fraction of incident radiation (at actinic wavelength) that passes through a mask, more specifically, a mask plate or combination of materials in or on the mask plate. In the context of this invention a material is considered to be transparent if it has a maximum value of transmissivity equal to that of the mask plate or substrate without any other materials than quartz. Opacity is defined as the fraction of incident radiation (at actinic wavelength) that is absorbed while passing through a mask, more specifically, a mask plate or combination of materials in or on the mask plate. In the context of this invention a material is considered to be opaque (having a value of opacity nearing a value of 1) if practically all the light is absorbed in the material, e.g. darkly pigmented glass.
USPTO Backgrounds
USPTO Backgrounds