1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to a method of fabricating an integrated circuit transistor using a disposable dielectric layer.
2. Description of the Related Art
Insulated gate field effect transistors ("IGFET"), such as metal oxide semiconductor field effect transistors ("MOSFET"), are some of the most commonly used electronic components in modem integrated circuits. Embedded controllers, microprocessors, analog-to-digital converters, and many other types of devices now routinely include millions of MOSFETs. The dramatic proliferation of MOSFETs in integrated circuit design can be traced to their high switching speeds, potentially low power dissipation, and adaptability to semiconductor process scaling.
A typical MOSFET implemented in silicon consists of a source and a drain formed in a silicon substrate, and separated laterally to define a channel region in the substrate. A gate electrode composed of a conducting material, such as aluminum or polysilicon, is disposed over the channel region and designed to emit an electric field into the channel region. Changes in the electric field emitted by the gate electrode enable, or alternatively, disable the flow of current between the source and the drain.
In a conventional process flow for forming a typical MOSFET, a gate oxide layer is grown on a lightly doped silicon substrate and a layer of polysilicon is deposited on the gate oxide layer. The polysilicon and the gate oxide are then anisotropically etched back to the upper surface of the substrate leaving a polysilicon gate electrode stacked on top of a gate oxide layer. Following formation of the polysilicon gate electrode, a source and a drain are formed by implanting a dopant species into the substrate. The gate electrode acts as a hard mask against the implant so that the source and drain are formed in the substrate self-aligned to the gate electrode. Many conventional semiconductor fabrication processes employ a double implant process to form the source and drain. First implant is performed self-aligned to the gate electrode to establish lightly doped drain ("LDD") structures. After the LDD implant, dielectric sidewall spacers are formed adjacent to the gate electrode by depositing and anisotropically etching a dielectric material, such as silicon dioxide. The second of the two source/drain implants is then performed self-aligned to the sidewall spacers. The substrate is then annealed to activate the dopant in the source and the drain. Salicidation steps frequently follow the formation of the source and drain.
The conventional self-aligned gate and source/drain formation process has been widely practiced in the industry for a number of years. One of the principle benefits of using such a self-aligned process is the ability to form channel regions with predictable dimensions, and to form gate electrodes without the requirement for additional masking steps that may be subject to photolithographic misalignment errors. However, there are certain disadvantages associated with the conventional self-aligned gate and source/drain formation process. First, the gate electrode is formed prior to the high temperature thermal processing steps associated with the formation of the sidewall spacers and the anneal of the source and drain. These high temperature thermal processes, if performed after the formation of the gate electrode, may cause contaminants to diffuse from the gate electrode into the channel region or vice versa. In either case, the electrical performance of the transistor may be diminished. Second, the dielectric material used to form the sidewall spacers is commonly composed of silicon dioxide formed by an oxidation reaction with an oxygen bearing ambient and the silicon substrate. The silicon dioxide growth rate for undoped or very lightly doped silicon substrates is such that the step of forming the silicon dioxide layer consumes processing time that might otherwise be eliminated or devoted to other steps in the process.
The present invention is directed to overcoming or reducing one or more of the foregoing disadvantages.
USPTO Backgrounds
USPTO Backgrounds