Computers are becoming a necessity in day-to-day business and user activities. This not only includes the typical desktops and portable computers, but devices that also use processors for application execution such as smart phones, for example. There are only a few processor architectures that have survived in the cut-throat computer business, and which account for the bulk of the millions of computers in use today.
Because of this mix of processor architectures, software vendors design and sell software for use on one or more of these processor architectures. This can be an expensive proposition so vendors typically will focus on the architecture that offers the most return on the investment. It is not uncommon for a user to prefer to run an application designed for one architecture on a different computer architecture. Such an example includes running an application designed for a PowerPC™ processor architecture on an x86-based processor architecture.
In order to accomplish this, the host machine (e.g., the x86 machine) will need an emulator to convert the guest instructions (of the PowerPC) to x86-based host instructions, and to provide a PowerPC execution environment for the converted guest instructions. The guest instruction set (e.g., the PowerPC instruction set) has a group of instructions that need to be translated down to be executed by the host. In other words, instructions can work differently on different architectures. If the translation process from guest to host is slow, this will translate into sluggish performance of the guest application and system overall making the user experience less than desirable.
One of the many challenging aspects of the translation process is to translate compare instructions. The PowerPC has dedicated instructions for signed and unsigned integer compares, each of which represents the result of the comparison by setting and clearing three status bits: “greater than”, “less than”, and “equal”. Conditional branch instructions then branch by testing these bits. The x86 host, in contrast, provides only one compare instruction that computes the results for both signed and unsigned integer compares and represents the result of the comparison by setting and clearing four status bits: “carry” (for unsigned integer values), “zero”, and “sign” and “overflow” (for signed integer values). These four bits are spread out over two 8-bit bytes of a flags register.
Given that instruction compares and conditional branches occur very frequently, poor performance at this level means reduced performance at the guest application level if these operations cannot be handled quickly.
USPTO Backgrounds
USPTO Backgrounds