1. Field of the Invention
This invention relates to a semiconductor integrated circuit device comprising a plurality of semiconductor packaging substrates.
2. Description of the Related Art
In order to constitute a multifunctional electronic device by using integrated circuits, it has been required to incorporate a greater number of semiconductor elements in a semiconductor integrated circuit. As the integrated circuit technique has been greatly improved, the integration density and the operation speed of a semiconductor circuit has become higher and higher. By the improvement of the integrated circuit technique, the number of input and output terminals of an integrated circuit has been increased to 500 or more, and it will be 1000 in near future.
However, when an integrated circuit having a great number of pins is mounted on an ordinary substrate such as a PGA (Pin Grid Array) or a QFP (Quad Flat Package), an outer side of the package of the integrated circuit is longer than 5 cm. In fact, a conventional semiconductor integrated circuit mounted on a printed board has the drawbacks that the integration density cannot be improved and the full use of all circuit functions cannot be realized.
In order to overcome the drawbacks, a method of mounting semiconductor integrated circuits on the above-mentioned substrate by a TAB (Tape Automated Bonding) method or a flip chip bonding method has been developed in recent years, whereby an insulating layer made of polyimide and a predetermined fine wire made of conductive material such as copper are formed in sequence on the substrate.
However, a high density semiconductor integrated circuit device wherein many semiconductor integrated circuits are incorporated, i.e., a semiconductor integrated circuit device constituted by a plurality of semiconductor packaging substrates electrically connected to one another, cannot operate at its maximum performance on account of a signal delay time. For example, in a parallel arithmetic processing device constituted by a plurality of processors, since the processors are connected by a large number of signal wires, it is necessary to increase the signal transmission speed in every wire to improve processing performance of the entire device. However, since the semiconductor integrated circuit device of a high integration density inevitably includes a portion in which impedance matching is not obtained, for example, a connecting portion between processors, it is difficult to maintain a constant characteristic impedance throughout the overall wiring path. As a result, signal reflection and distortion of a signal waveform will occur. Moreover, since crosstalk easily occurs with a narrow interval between signal wires, noise is superposed on a signal. Consequently, it is difficult to electrically transmit a signal with high speed between processors. In the semiconductor integrated circuit device constituted by electrically connecting semiconductor packaging substrates each having a number of integrated circuits, the signal waveform is degraded by connectors and the delay time due to a back plane is increased, since a signal is transmitted between packaging substrates through an electric path. As a result, the device cannot perform its function satisfactorily.
In summary, the above-described conventional integrated circuit device, which is constituted by high-density semiconductor packaging substrates electrically connected by TAB or flip chip bonding method, has the following drawbacks: (1) distortion occurs in a signal waveform; (2) the delay time in signal transmission increases; and (3) the semiconductor integrated circuit device does not operate efficiently.
The conventional art related to the present invention is reported by L. A. Hornak, "Fresnel phase lenses for through-wafer optical interconnections"; APPLIED OPTICS, Vol. 26, No. 17, pp. 3469-3654, 1 Sep. (1987) and L. A. Hornek, "Through-wafer Optical Interconnection Coupling Characteristics"; ELECTRONICS LETTERS Vol. 21, No. 11, pp. 714-715, 26 May (1988) and disclosed in U.S. Pat. No. 4,720,634, 19 Jan. (1988).
USPTO Backgrounds
USPTO Backgrounds