1. Technical Field
This invention relates to system on chip architectures. More specifically, this invention relates to combining the CoreConnect architecture with the AMBA architecture.
2. Description of the Prior Art
Core Connect bus architecture owned by IBM is a standard System-On-a-Chip (SoC) design that allows peripherals formerly attached to the processor at the card level to be integrated onto the same die as the processor. The Core Connect architecture provides the following three buses for interconnecting core, library macros, and custom logic: processor local bus (PLB), on-chip peripheral bus (OPB), and device control register (DCR). The PLB and OPB buses provide the primary means for data flow among macro elements. The PLB generally interconnects high-bandwidth devices, such as processor cores, external memory interfaces, and DMA controllers. The PLB addresses the high performance, low latency and design flexibility issues with peripherals. The PLB supports interconnection with various master and slave macros. Each PLB master is attached to the PLB macro via separate addresses, read data and write data buses, and a plurality of transfer qualifier signals. PLB slaves are attached to the PLB macro via shared, but decoupled address, read data and write data buses along with transfer control and status signals for each data bus. The PLB architecture supports up to 16 master devices. The PLB architecture also supports any number of slave devices. The number of masters and slaves attached to a PLB macro directly affects the maximum attainable PLB bus clock rate.
PLB transactions consist of multiphase address and data tenures. Depending on the level of bus activity and capabilities of the PLB slaves, these tenures may be one or more PLB bus cycles in duration. In addition, address pipelining and separate read and write data buses yield increased bus throughput by way of concurrent tenures. Address tenures have three phases: request, transfer, and address acknowledge. A PLB transaction begins when a master drives its address and transfer qualifier signals and requests ownership of the bus during the request phase of the address tenure. Once the PLB arbiter grants bus ownership, the master's address and transfer qualifier are presented to the slave devices during the transfer phase. The address cycle terminates when a slave latches the master's address and transfer qualifiers during the address acknowledge phase.
AMBA, the Advanced Microprocessor Bus Architecture is an open standard on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a SoC. AMBA defines a multilevel busing system, with a system bus and a lower-level peripheral bus. These include two system buses: an AMBA High-Speed Bus (AHB) or an Advanced System Bus (ASB), and an Advanced Peripheral Bus (APB). The two buses are linked via a bridge that serves as the master to the peripheral bus slave devices and helps reduce system power consumption.
The CoreConnect architecture shares many similarities with the AMBA. For example, both architectures support data bus widths of 32 bits and higher, utilize separate read and write data paths, and allow multiple masters. CoreConnect and AMBA both provide high performance features including pipelining, split transactions, and burst transfers.
It is known in the art to implement the CoreConnect bus architecture and the AMBA bus architecture into a single mixed architecture. Due to the dissimilarity of these two bus architectures, a bridge has been used to carry out protocol conversion between the two bus architectures. FIG. 1 is an overview of a prior art bus architecture (10) used by existing technology to arbitrate data communications when the CoreConnect and AMBA are mixed. As shown, a bridge (50) is used to carry out protocol conversion between the two bus architectures. The processor local bus (PLB) (22) of the CoreConnect architecture (20) and AHB (32) of the AMBA architecture (30) are connected with the bridge (50). This bridge (50) includes two elements for data conversion. One element is a PLB2AHB bridge component (52) that converts a PLB master transfer into an AHB master transfer. Another element is an AHB2PLB bridge component (54) to convert an AHB master transfer into a PLB master transfer. However, since these two bus architectures are dissimilar, it is known that data transfer error problems occur. In one embodiment, the error takes the form of an increased number of read times for an AHB Slave than the number of reads of a corresponding DMAC. This results in a bus error.
Therefore, there is a need to connect the PLB of the CoreConnect architecture and AHB of the AMBA architecture with a solution that eliminates the bus error.
USPTO Backgrounds
USPTO Backgrounds