1. Field of the Invention
The present invention relates to a thin-film transistor which may be used as a load transistor in an SRAM (static random access memory) cell.
2. Description of the Related Art
High-density SRAM cells using thin-film transistors (TFTs) composed of thin films subsequently formed on a silicon substrate have been studied. With an SRAM cell which employs TFTs and which has been studied so far, a high-resistivity polysilicon layer which has conventionally been used as a load is replaced with a TFT.
FIG. 7 illustrates an equivalent circuit of a conventional SRAM cell which employs P-channel TFTs as loads.
In FIG. 7 , N-channel MOS transistors Q1 and Q2, which serve as transfer gates, have their current paths connected, at their corresponding ends, to bit lines BL and BL, respectively, and at the other ends, to storage nodes A and B, respectively. The gate of each of the transistors Q1 and Q2 is connected to a word line WL. To the storage node A are connected the drains of an N-channel MOS transistor Q3 and a P-channel TFT Q4. The gates of the transistor Q3 and TFT Q4 are connected to the storage node B. The source of the transistor Q3 is connected to ground potential Vss, while the source of the TFT Q4 is connected to a supply potential Vcc. In a similar manner, an N-channel MOS transistor Q5 and a P-channel TFT Q6 have their drains connected to the storage node B and their gates connected to the storage node A. The source of the transistor Q5 is connected to ground potential Vss, while the source of the TFT Q6 is connected to the supply potential Vcc.
In the above SRAM cell, the transistor Q3 and TFT Q4 constitute one complementary MOS (CMOS) inverter, while the transistor Q5 and TFT Q6 constitute one CMOS inverter. Each of the TFTs Q4 and Q6 serves as a load transistor of the CMOS inverter.
FIG. 8 illustrates a pattern layout of the SRAM shown in FIG. 7, and FIG. 9 is a sectional view taken along the line 9--9 of FIG. 8. In FIGS. 8 and 9, 11 denotes a P-type semiconductor substrate, 12 denotes field insulating layers formed within the semiconductor substrate 11, and 13 denotes N+ diffused regions which are formed within the semiconductor substrate 11 which serve as source regions or drain regions of the N-channel MOS transistors. Note that, in FIG. 8, the N+ diffused regions 13 described above, and the gate oxide films and insulating layers to be described later are omitted. Reference numeral 14 denotes a first layer of polysilicon serving as gate electrodes of the N-channel MOS transistors, which is isolated from the semiconductor substrate 11 by an oxide film 31. Reference numeral 15 denotes a second layer of polysilicon serving as the gate electrode of a P-channel TFT, which is isolated from the first polysilicon layer 14 by an insulating layer 32. Reference numeral 16 denotes a third layer of polysilicon which serves as the channel region, source region and drain region of a P-channel TFT. The polysilicon layer 16 is isolated from the gate electrode layer 15 by an insulating layer 33. Reference numeral 17 denotes the channel region of a TFT which is formed in the third polysilicon layer 16 and is substantially undoped with impurities so that it remain highly resistive. The word line WL and ground line are formed of the first polysilicon layer 14, and the power supply line for supplying the potential Vcc is formed of the third polysilicon layer 16. An interlayer insulating film 34 is formed over the resultant structure. A metal line 18, which serves as the bit line BL, is formed on the interlayer insulating film 34 and connected to the N+ diffusion region 13.
In FIG. 8, the N+ diffusion region is omitted.
As shown in FIG. 9, the TFT is composed of the gate electrode layer 15 and the polysilicon layer 16 disposed above the layer 15. The channel region 17 is provided in that portion of the polysilicon layer 16 which corresponds to the gate electrode 15. In contrast to a usual field effect transistor using silicon, the TFT has its gate electrode, source and drain regions reversed in position. Thus, the TFT is not of a self-alignment type.
The TFT uses a thin polysilicon layer whose thickness is on the order of some hundreds of angstroms. Thus, if a contact hole were opened in this thin polysilicon layer, the underlying polysilicon layer would also be etched away.
The metal line 18, which normally serves as the bit line BL, is formed above the thin polysilicon layers constituting the TFT. Separation is made between the metal line 18 and the polysilicon layer 16 by the relatively thick interlayer insulating layer 34 of the order of some thousands of angstroms. However, the metal line 18 may serve as a gate electrode for the polysilicon layer 16, thereby constituting a parasitic TFT. The potential on the metal line 18 serving as the bit line varies between read and write operations. Thus, a variation in the potential on the bit line will allow a parasitic operation which causes the on or off state of the P-channel TFT to be changed. At the time of writing of data in particular, one of the paired bit lines goes to a low level to cause the P-channel TFT to turn on. This results in an increase in the current of a memory cell when it is in the quiescent state. The on current of the parasitic TFT resulting from the metal line 18 is very small because of the relatively thick gate layer. However, the on current has a great influence upon the extremely-low leakage current characteristic of the SRAM when it is in the quiescent state.
Where, in the future, a semiconductor device of a three-dimensional structure is developed by forming TFTs upon each other, a TFT parasitic gate electrode will be developed in its upper or lower layer. Therefore, it is expected that the influence of the parasitic gate electrode will become an even more serious problem.
USPTO Backgrounds
USPTO Backgrounds