Certain circuits use different clocks where the frequency of one clock is an integer multiple of a frequency of another clock. In these cases, it is common to provide a clock and a frequency divider circuit that divides the clock by some multiple. An output of the frequency divider may then be used as the second clock in the circuit. In some contexts, it is desirable for the clocks to be synchronized to each other. Specifically, it is desirable that an edge of the lower frequency clock be placed in time relative to a specific edge of the higher frequency clock. Which one of the specific edges destined for synchronization is determined in a circuit that provides a “1” or “0” logic value depending upon whether the two clocks are properly synchronized or not. At power-up, however, the phase difference between the two clocks is not known or predictable. There is a need, therefore, for an apparatus and method to synchronize two clocks relative to each other.
USPTO Backgrounds
USPTO Backgrounds