Multiplexers are commonly used to select one of several input signals for provision at an output line. The logic function corresponding to 2:1 multiplexing may be expressed as OUT=A*S+B*SBAR, where A and B are data inputs, S and SBAR are a select input and its complement, OUT is the output of the multiplexer, and “*” and “+” represent logical “AND” and logical “OR,” respectively. A known implementation of a 2:1 multiplexer includes a pair of tri-state inverters. Each tri-state inverter is coupled to one of the data inputs and includes four metal oxide semiconductor (MOS) transistors, including two NMOS transistors and two PMOS transistors. For each tri-state inverter, if one of the PMOS transistors and one of the NMOS transistors are controlled to be in an open (“off”) state, an output of that tri-state inverter is set to be electrically floating (high impedance), and if those transistors are controlled to be in a closed (“on”) state, the output of that tri-state inverter is the logical complement of the corresponding data input. The two tri-state inverters share a common output node, which is possible due to tri-state logic (one of the tri-state inverters disconnects its output). An inverter having that common output node as an input provides the overall multiplexer output. Another inverter inverts a data select input for provision to the tri-state inverters.
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