1. Field of the Invention
This invention relates to an emitter coupled logic (ECL) circuit, and more particularly to reduction in the power consumption thereof.
2. Description of the Related Art
An ECL circuit (disclosed in "Nikkei Electronics" Feb. 6, 1989, No. 466. pp 211 to 218) shown in FIG. 1 is known as an example of the conventional ECL circuit. The ECL circuit includes a pull-up transistor Q7 constituting an emitter follower and a pull-down transistor Q5 having a capacitor Cc as a coupling capacitor.
Transistors Q1 and Q2 constitute a differential type switching circuit 12, and the base of the transistor Q2 is applied with a reference bias potential V.sub.T and the base of the transistor Q1 is applied with a potential of (VT.+-.250) mV.
Assuming that the base of the transistor Q1 is raised to a high level potential of (VT+250) mV, then the transistor Q1 is turned on and the transistor Q2 is turned off. When the transistor Q2 is turned off, the collector potential of the transistor Q2 is raised, causing a transistor Q7 to be turned on. As a result, the potential of an output 14 is set to a high level.
When the switching mode of the switching circuit 12 is inverted, that is, when the transistors Q1 and Q2 are respectively turned off and on, the collector potential of the transistor Q1 is raised. The raised collector potential is applied to the base of the transistor Q5 via the coupling capacitor Cc, thus turning on the transistor Q5. As a result, a discharging operation (indicated by an arrow 13) of stored charge on an output capacitor C.sub.L is caused via the transistor Q5, thereby setting the potential of the output 14 to a low level.
Addition of the pull-down transistor Q5 and pull-up transistor Q7 permits the pull-down operation and pull-up operation to be actively effected.
In the conventional circuit shown in FIG. 1, a transistor Q4 and a constant voltage source (not shown) for supplying a clamp voltage V.sub.CLAMP to clamp the base potential of the transistor Q4 are used as a bias potential supplying circuit for the transistor Q5.
In order to keep the static state of the transistor Q5 stable, it is necessary to prevent the static current flowing in the transistor Q5 from being influenced by temperature variation. To meet the requirement, compensation for variation in the clamp voltage V.sub.CLAMP with respect to temperature variation must be made and a corresponding device must be provided.
Further, since the transistor Q4 and a resistor R4 connected in series with the transistor Q4 are additionally provided, additional power consumption is caused by these elements and this is not preferable from the viewpoint of reduction in the power consumption.
Further, it is difficult to stably effect the temperature compensation for the V.sub.CLAMP voltage at a level (approx. .+-.0.5 V) near the ground (GND) potential level. For example, in a case where a power source V.sub.E is set at approx. -2 V which is normally required to reduce the power consumption, sufficient compensation for variation in V.sub.CLAMP with respect to temperature variation cannot be attained and thus it becomes difficult to stably maintain the current flowing in the transistor Q5.
USPTO Backgrounds
USPTO Backgrounds