In the semiconductor industry, conductive interconnects have traditionally been formed using Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) processes. Currently, PVD processes are preferred due to cost, ease of deposition, and availability of equipment. However, as the critical dimensions of semiconductor devices shrink, the aspect ratio of contact and via openings increase, and it is difficult to form a conformal film within these openings using PVD processes. Thus, current PVD processes provide poor step coverage within high aspect ratio openings, and interconnect structures formed often contain voids. These voids reduce the overall conductivity of the interconnect structure, and they adversely effect the reliability of semiconductor device. CVD processes, on the other hand, typically provide a more conformal film than PVD processes. CVD processes, however, require expensive processing equipment, frequent downtime for cleaning, and use a high cost low efficiency chemical precursor. In addition, interconnect structures formed in high aspect ratio openings, using CVD techniques, also suffer from void formation and adhesion of these films to underlying dielectric materials is often problematic. Therefore, a need exists for a metallization process that deposits highly conformal films within high aspect ratio openings, and that can be used to reduce void formation in interconnect structures.
USPTO Backgrounds
USPTO Backgrounds