Semiconductors have traditionally scaled in accordance with the Moore's Law wherein packing more and more transistors (at a reduced pitch) over the same area leads to an overall improvement in the device performance at a reduced cost. However, as the technology nodes are shrinking to tens of nanometers, the development costs associated with increasing semiconductor density has been steadily increasing. Therefore, in order to offset the development costs associated with traditional semiconductor scaling, 3D packages (stacked dies, dies on interposers, etc.) have been considered.
However, developing 3D semiconductor packaging technologies present unique challenges with regards to optimizing the thermo-mechanical performance and ensure device reliability. For example, there is a growing need to reduce the chip package interaction (CPI) shear stresses between the die/interposer and associated underfill to offset the added stress caused by the increasing package complexity. Additionally, the cost to produce such packages should be minimum to stay competitive in the market.
Quadrilateral (especially square and rectangle) shaped die/interposers have high CPI shear stress concentrations at the corners between the underfill and the die/interposer. Reduction of this underfill to die/interposer shear stresses is limited by the properties of the existing package component materials and by geometric constraints. Additionally, because the die shape is restricted to square/rectangular forms, system optimization can only be obtained through substrate modifications, which is limited by the properties of existing substrate materials.
USPTO Backgrounds
USPTO Backgrounds