The present invention relates to an input/output buffer system having a novel buffer area allocation system.
A conventional computer system includes a buffer memory between an input/output device and a main memory of a processor to temporarily store a required number of data signals. Conventional buffer systems include a fixed length buffer system and a variable length buffer system. The latter system is developed to eliminate the disadvantages of the former system.
A conventional variable length buffer system is disclosed in U.S.P. No. 4,258,418 (Mar. 24, 1981). This system aims at dynamically adjusting the size or capacity of a buffer memory so as to minimize buffer filling delay and I/O device start/stop delay. In this buffer system, the buffer memory has a maximum data storage capacity value and is controlled by software to selectively establish a threshold storage capacity value which is less than the maximum storage capacity value of the buffer memory. According to this buffer system, when data is transferred between a processor and a low-speed I/O device, the threshold storage capacity value can be small, and most of the capacity of the buffer memory need not be used. In addition, since a single I/O device occupies a buffer memory for a predetermined period of time (e.g., time required for transferring one-block data), it is impossible to transfer multiplexed data between the processor and a plurality of I/O devices.
In order to set the threshold value by software, attributes of the I/O device must be recognized before initialization thereof, thus overloading the processor.
In the prior art as described above, even if the threshold value is small, all buffer areas are sequentially used. Even if a failure occurs in some of the buffer areas, the failed areas cannot be disconnected.
USPTO Backgrounds
USPTO Backgrounds