1. Field of the Invention
The invention relates to a semiconductor integrated circuit which can perform parallel signal processes.
2. Related Background Art
In association with a rapid development of the signal processing technique, at present, attention is paid to neuro information processes such as pattern recognition, voice recognition, image understanding, and the like which are weak points for the von Neumann computer. Perfect parallel signal processes which are executed by the human brain cells are the central processes among them. If parallel comparing processes for detecting a storing position of data having the maximum or minimum value from a number of data are executed by a binary digital circuit as a main circuit of a signal processing circuit of the present LSI, an extremely large number of circuit elements and a large electric power consumption are needed and a real-time response is difficult. On the other hand, a circuit for dealing with a number of data as analog signals, executing analog signal processes as they are, and performing the parallel signal processes at a high speed has been proposed in J. Lazzaro, S. Ryckebusch, M. A. Mahowald, and C. A. Mead, "Winner-Take-All Networks of 0(n) Complexity", in Advances in Neural Information Processing Systems 1 (San Mateo, Calif.: Morgan Kaufman, 1989), pp. 703-711, and G. Gauwenberghs and V. Pedroni, "A charge-based CMOS parallel analog vector quantizer", in Advances in Neural Information Processing Systems 7 (Cambridge, Mass.: The MIT Press, 1995), pp. 779-786.
FIG. 1 shows an example of a maximum position detection parallel signal processing circuit. This circuit has N input signal data trains comprising a first input signal current 100, a second input signal current 101, and an N-th input signal current 102. One of terminals of each of the input signal currents 100, 101, and 102 is connected to a power source voltage at an input terminal 1 and another terminal to which the signal current is outputted is connected to a drain terminal of each of NMOS transistors 103, 104, and 105 whose sources are connected to the ground. Gate terminals of the NMOS transistors 103, 104, and 105 are commonly connected. Gate terminals of NMOS transistors 106, 107, and 108 are connected to the drain terminals of the NMOS transistors 103, 104, and 105. Source terminals of the NMOS transistors 106, 107, and 108 are connected to the commonly connected gate terminals of the NMOS transistors 103, 104, and 105. A current source Ic 109 is connected between a ground potential at an input terminal 2 and common connecting point of the gate terminals of the NMOS transistors 103, 104, and 105 and the sources of the NMOS transistors 106, 107, and 108. It is now assumed that a current value of the input signal current source 100 is labelled as I1, a current value of the input signal current source 101 is set to I2, and a current value of the input signal current source 102 is shown by In, there are relations of (I2=In) and (I1&gt;I2=In), and I1 is the largest among the input data trains. All of the NMOS transistors 103, 104, 105, 106, 107, and 108 operate in a sub threshold region which is fairly lower than a threshold value Vth of the NMOS. When the input currents I1, I2, and In are inputted to the NMOS transistors 103, 104, and 105, respectively, a voltage between the gate and source of each transistor rises. However, since each gate terminal is commonly connected, the gate-source voltage of the NMOS transistor 103 to which the maximum current I1 is supplied becomes dominant. A gate common electric potential of each of the NMOS transistors 103, 104, and 105 is set to Vc=Vo.multidot.In(I2/Io) (Vo=KT/q: Io is a constant). When the gates of the NMOS transistors 104 and 105 are biased by Vc, it is intended to drive the drain terminals so as to pull in drain currents to a current equivalent to I1. However, since the currents I2 and In which are supplied to the drain terminals of the NMOS transistors 104 and 105 are smaller than I1, by reducing each drain-source voltage, the drain currents of the NMOS transistors 104 and 105 are set to I2 and In. Therefore, voltages of the drain terminals of the NMOS transistors connected to the input current sources other than the maximum input current are reduced. Consequently, gate electric potentials of the NMOS transistors 107 and 108 decrease and only a gate electric potential of the NMOS transistor 106 to which the maximum current is inputted rises. A voltage at the common connecting point of the gate terminal of the NMOS transistor 106 at this time and the drain terminal of the NMOS transistor 103 is equal to the sum EQU Vi1=Vo.multidot.In(I1/Io)+Vo.multidot.In(Ic/Io)
of the gate-source voltages of the transistors. Therefore, the current Ic of the current source 109 is concentrated to the NMOS transistor 106 to which the maximum current is inputted. As mentioned above, by monitoring the gate voltages of the NMOS transistors 106, 107, and 108, the voltage is developed in only the cell to which the maximum input current is supplied and the voltages of the other cells are suppressed to 0. Thus, the maximum position of the signal can be detected by the parallel processes.
In the case where it is intended to retrieve the analog signals at high precision by using the maximum position detection parallel signal processing circuit shown in FIG. 1, however, there are several problems. If the input current such that a difference from the maximum input signal current value is very small exists, the drain terminal voltage of the NMOS transistor to which such an input current is supplied is not equal to 0 but slightly decreases to a value for the drain terminal voltage of the NMOS transistor to which the maximum current is inputted. Therefore, a high precision voltage comparator is needed to a circuit of the maximum position detecting system of post processes, thereby making the circuit complicated. Due to a variation in threshold values Vth of the NMOS transistors, even in case of the same current input, gate-source voltages Vgs which are generated differ. There is a problem that the magnitudes of the analog signals cannot be accurately compared. Since the operating mode of the MOS of the circuit in the conventional example is operative in the sub threshold region in which the gate-source voltage Vgs is equal to or less than Vth, the current for the voltage is exponentially determined. Therefore, a value of the set current value for the voltage variation also exponentially varies and causes a deterioration in detecting precision.
USPTO Backgrounds
USPTO Backgrounds