1. Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor capable of reducing equivalent series inductance (ESL), maintaining a suitable equivalent series resistance (ESR), and allowing electrostatic capacitance thereof to be easily tested.
2. Description of the Related Art
A multilayer chip capacitor is useful for a decoupling capacitor in a power supply circuit of a LSI or a capacitive component for removing a high-frequency noise from signal lines. In order to stabilize the power supply circuit, the multilayer chip capacitor is required to have a low equivalent series inductance (ESL). This requirement is further increased as electronic apparatuses tend to be operated in a high frequency and a high current. The stability of the power supply circuit greatly depends on an equivalent series resistance (ESR) as well as the ESL of the multilayer chip capacitor. If the ESR has a too small value, the stability of the power supply circuit deteriorates, so that the supplied voltage is severely fluctuated. Therefore, it is preferable that the ESR is chosen to have a suitable value.
In U.S. Pat. No. 5,880,925, there is disclosed a technology of reducing the ESL by using an interdigitated arrangement where leads of first and second internal electrodes having opposite polarities are interdigitated. FIG. 1A is a perspective exploded view illustrating a structure of internal electrodes of a conventional multilayer chip capacitor 50, and FIG. 1B is a perspective view illustrating an outer appearance of the multilayer chip capacitor 50 of FIG. 1A.
Referring to FIG. 1A, a first and second internal electrodes 12 and 13 having opposite polarities are disposed on dielectric layers 11a and 11b. A capacitor body 20 is formed by alternately laminating the dielectric layers 11a and 11b. Internal electrodes 12 and 13 are connected to external electrodes 31 and 32 through leads 16 and 17, respectively (see FIG. 1B). The lead 16 of the first internal electrode 12 and the lead 17 of the second internal electrode 13 are disposed to be adjacent to each other in an interdigitated arrangement. Since polarities of voltages supplied to the adjacent leads are different, magnetic fluxes generated from high frequency currents flowing through the external electrodes are cancelled between the adjacent leads, so that the ESL can be reduced.
Each of the internal electrodes 12 and 13 has four leads. Since resistances formed by the four leads are connected to each other in parallel, a total resistance of the multilayer chip capacitor becomes very low. As a result, the ESR of the multilayer chip capacitor also has a too small value. The excessive decrease in ESR causes instability of the power supply circuit.
In U.S. Pat. No. 6,441,459, there is proposed a technology for preventing the excessive decrease in ESR by using only one lead in each internal electrode. However, according to the US patent, since only one lead is provided to each internal electrode, the ESL is relatively increased. In addition, all the internal electrodes having the same polarities are not electrically connected to each other in the multilayer chip capacitor, so that electrostatic capacitance of the multilayer chip capacitor cannot be easily tested or measured.
USPTO Backgrounds
USPTO Backgrounds