This invention relates, in general, to logic circuits using field effect transistors, and more particularly, to logic circuits using vertically stacked complementary field effect transistors.
Complementary field effect logic, such as silicon CMOS, is very power efficient as a result of data being stored as potential energy rather than current flow. Compound semiconductors, such as heterojunction field effect transistors (HFETs), promise even more efficient devices as a result of higher mobility of charge carriers in compound semiconductor materials. One problem with conventional HFET structures, however, is a mismatch in P-channel and N-channel threshold voltage and operating characteristics. Mismatch between N-channel and P-channel devices complicated processing and made circuits using the devices more complex.
Compound semiconductors are expensive to process. Unless a device can be manufactured in a smaller chip using compound semiconductors, it cannot be cost competitive with silicon designs. This cost problem has limited compound semiconductor applications to high performance integrated circuits where performance commands a premium price, justifying the additional cost. To successfully compete in commodity markets such as computer memory, a design is needed which dramatically reduces chip size of compound semiconductor circuits while maintaining performance advantages as compared to silicon devices.
USPTO Backgrounds
USPTO Backgrounds