The present invention relates to level shifters, and more particularly to an improved level shifter that rejects voltage variations that would cause the level shifter to shift in error.
A level shifter shifts digital signal input voltages to digital signal output voltages. That is, it takes a digital signal that has one set of input voltages, typically input supply and reference voltages (e.g., 10 and zero volts) and shifts the input voltages to some other level appropriate for a specific application, typically output supply and reference voltages (e.g., 110 and 100 volts.) The level shifter also includes a trigger connected to the input supply and reference voltages for triggering a pulse at each transition of the digital signal between the input supply voltage and the input reference voltage, and a latch connected to the output supply and reference voltages for switching and holding the digital signal to one of the output supply voltage and the output reference voltage in response to receipt of a pulse from the trigger.
A level shifter typical of the prior art is illustrated in FIG. 1. The level shifter 10 has six connections: IN, OUT, VDD, VSS, HB, HS. VSS is the ground reference for the circuit. VDD is the supply voltage relative to VSS. HS is called the "floating" ground and HB is the supply voltage relative to HS. IN is a digital input whose logic zero voltage is the VSS voltage and whose logic one voltage is the VDD voltage. OUT is a digital output whose logic zero voltage is the HS voltage and whose logic one voltage is the HB voltage. The logical value of OUT is the same as that of IN. That is, when IN is high then OUT is high and when IN is low then OUT is low. As an example of typical operation, if VSS is 0 V then VDD is 10 V, HS is 100 V, and HB is 110 V. When IN is 0 V then OUT is 100 V and when IN is 10 V then OUT is 110 V.
In FIG. 1 there are four voltage sources. The sources labelled VHB and VDD are DC sources. The source labelled VIN is a digital signal generator, that is, its voltage is either VSS or VDD except when it is rapidly transitioning from one to the other. The last source, labelled VHS, may have any value, although typically it is limited to some range, such as between -1 V and 100 V. The HS voltage changes to any voltage from -1 V to 100 V without upsetting the relationship between IN and OUT. The HS voltage variation is desirably less than some value, such as less than 10 V per 1 ns. The invention disclosed herein improves the rejection of HS variations.
With further reference to FIG. 1, a prior art level shifter 10 may include trigger 12 and receiver 14, current source IIN, resistor Rload, and capacitor Cerror. Trigger 12 turns on current source IIN in response to input signal IN. The current from current source IIN flows into resistor Rload and creates a voltage drop across the resistor. This voltage drop is sensed by receiver 14 which drives the OUT signal to the correct value. This normal mode of operation can get disturbed when the HS voltage changes because the unavoidable parasitic capacitor Cerror also causes current to flow in resistor Rload. For example, if Cerror is 1 pF and HS increases at 10 V/ns then 10 mA flows in Rload. If receiver 14 cannot distinguish this 10 mA of error current from the intentional current produced by IIN then receiver 14 will drive the OUT pin to the incorrect value.
HS variations can cause improper operation in several ways, and the typical prior art level shifter may include components for reducing HS variations. With reference now to FIG. 2, the prior art level shifter may include paired circuits to attempt to reject the variations in HS voltage. Trigger 12, receiver 14, current source IIN, and resistor Rload may be copied (copies provided with a suffix "2" in FIG. 2) and driven with the inversion of the IN signal. When IN is high current source IIN is activated and when IN is low current source IIN2 is activated. Another circuit block, subtractor 16, is inserted between resistors Rload and receiver 14. Subtractor 16a subtracts the signal on Rload2 from the signal on Rload and passes the result to receiver 14a. If IN is high then there is a signal on Rload and no signal on Rload2. Since there is no signal on the subtracting input to subtractor 16a the signal on Rload is sent to receiver 14a which, in turn, forces OUT high. Likewise, if IN is low then resistor Rload2 has a signal and resistor Rload has none.
The HS variations can create current in the two capacitors, Cerror and Cerror2. These currents cause voltage drops on Rload and Rload2 that are added to the desired voltages on the resistors. If the two capacitors are equal sized and the two resistors are also equal then the HS variations add the same voltage to each resistor. Subtractor 16 subtracts these voltages from each other so no variation-induced signal is passed on to receiver 14 and the OUT signal is unchanged.
The circuit may include triggers 12 for decreasing power dissipation in the current sources by only turning on during the pulses that are generated by the edge-triggered one-shots. That is, IIN is pulsed on just after a rising edge on the IN node and IIN2 is pulsed on following a falling edge on IN. The current sources only dissipate power during the pulses and so the average power dissipation is decreased.
The level shifter may also include a second subtractor 16b and receiver 14b, a latch 18 for converting the pulses into a stable level on the OUT node, and diodes 20 for only transmitting positive pulses. The pulse of current from IIN (generated on the rising edge of IN) creates a positive pulse on the output of subtractor 16a and a negative pulse on the output of subtractor2 16b. The positive pulse passes through diode 20a while the negative pulse is blocked by diode 20b. Receiver 14a will then have a pulse on its output while receiver2 14b output will remain in the low state. The pulse from receiver 14a drives the SET input of latch 18. This causes OUT to go high and to stay high until a falling edge on IN creates a similar sequence of events as described above that conclude with a pulse on the RESET input to latch 18.
While the circuit of FIG. 2 may reduce power dissipation, the output is stored in a latch. If a disturbance, such as excessive HS variation, a glitch from the VHB supply, or radiation, causes the latch to flip states at the wrong time, the output of the level shifter will not be the same as the input. In many level shifter applications, such as power systems, an incorrect output can lead to the destruction of the electronics and maybe even the load (motor, transformer, solenoid, etc.).
Accordingly, it is an object of the present invention to provide a novel level shifter that obviates the problems of the prior art in rejecting voltage variations that cause the level shifter to shift in error.
It is another object of the present invention to provide a novel level shifter that includes plural current mirrors connected to reduce capacitances that would cause a latch in the level shifter to switch in error.
It is yet another object of the present invention to provide a novel level shifter that includes plural current mirrors connected to discharge stored charges in current mirror transistor junctions that would cause a latch in the level shifter to switch in error.
It is still another object of the present invention to provide a novel level shifter with a current source for providing a current to current mirrors responsive to receipt of a pulse, wherein the current source has a transistor with a source terminal that is an open circuit when the voltage on the source is less than an input supply voltage for reducing a capacitance that induces voltage variations.
It is a further object of the present invention to provide a novel level shifter with series connected current mirrors for providing two copies of a capacitance-induced error current that have a timing relationship that ensures that the latch can not be switched.
It is yet a further object of the present invention to provide a novel level shifter with a current mirror having a load transistor for sensing a voltage related to a pulse, and with a second diode for diverting current from a drain of the load transistor to thereby reduce a charge stored in a junction of the load transistor and reduce a time for discharging the stored charge when an output reference voltage changes from a falling voltage to a rising voltage.
It is still a further object of the present invention to provide a novel level shifter with current mirrors having load transistors for sensing a voltage related to a pulse, each with a parasitic transistor for selectively diverting current from a drain of its load transistor to thereby selectively reduce a charge stored in a junction of the load transistor so that a voltage variation caused by a difference between times for discharging the stored charge in the load transistors does not cause the latch to switch when the output reference voltage changes from a falling voltage to a rising voltage.
It is an additional object of the present invention to provide a novel level shifter with a logic circuit for comparing a state of the latch to a state of the digital signal input voltages, and for providing a corrective signal when the two states are different.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the following detailed description of the preferred embodiments.
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