Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade the performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled down into the deep-submicron range, parasitic series resistances of the source/drain diffusion layers and polysilicon gate electrodes increase. A conventional approach to counteract the increase in parasitic series resistances of the source/drain diffusion layers and the polysilicon gate electrodes involves salicide technology which comprises forming a layer of metal silicide on the source/drain regions and the gate electrode.
Conventional salicide technology for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range, i.e., about 0.18 microns and smaller. For example, agglomeration causes silicide to have high sheet resistance. Due to the scaling, the silicide integrity becomes worse when the line width is narrowed. Silicide is prone to agglomeration. With a wide line width, if a portion of the silicide agglomerates, more alternative paths still exist for currents. However, with a narrow line width, an agglomerated portion may occupy a greater portion of a cross sectional area on the current path, thus the sheet resistance will increase significantly with an agglomeration. Therefore sheet resistance tailing occurs, which means that there is a higher probability that a silicide has high sheet resistance.
It can be appreciated from the geometry of a MOS device that smaller device sizes, in particular a shorter distance between the source and drain, will allow the conducting channel between the source and drain to form more rapidly and allow the device to operate at higher switching speeds. As the device dimensions are reduced to achieve higher packing densities and improved performance, the junction depth needs to be scaled in proportion to the junction length. However, the formation of silicide consumes crystalline silicon from the underlying semiconductor substrate. When the junction depth is significantly smaller than the thickness of the silicide, the thickness variation of the silicide caused by process variations may be greater than the junction depth, making the junction depth very hard to control.
Another significant problem is leakage current. FIG. 1 illustrates a conventional transistor. The source/drain region includes a lightly doped source/drain region (LDD) 104 and a deep source/drain region 106. Silicide 102 typically consumes a portion of the deep source/drain region 106, thus lowering the top surface of the deep source/drain region 106. As a result, the silicide 102 is closer to a corner point 108, which is located at an interface of the LDD region 104 and the deep source/drain region 106. When the transistor is scaled down, the distance D decreases, and a leakage current between the silicide 102 and the substrate 2, as is symbolized by arrow 110, increases. With continued scaling of the MOS devices, the distance D will continue to decrease, causing an increase in the leakage current. If processes are not well controlled, silicide 102 may become very close to, or even reach, point 108, causing a significant leakage current.
Accordingly, there exists a need for a simplified methodology for forming low resistance contacts in semiconductor devices with increased reliability and reduced junction leakage.
USPTO Backgrounds
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