(a) Field of the Invention
The invention relates to a data processing circuit, particularly to a data processing circuit for a memory.
(b) Description of the Related Art
FIG. 1 shows a schematic diagram of a common data processing circuit 10. The data sorting unit 101 of the data processing circuit 10 receives the data transmitted by a memory, 32-bit data, as shown in the figure. The decoder 102 is used to decode the data and output 24-bit data. A 24-bit data comprises six 4-bit data and each 4-bit data is processed by the data sorting unit 101 and then transmitted through the data transmission path.
It should be noted that the data sorting unit 101 comprises a plurality of data transmission paths and each path can output data with 1˜10 bits. As the data sorting unit 101 outputs a 4-bit data through one data output path, the decoder 102 receives and decides which of the 1˜10 bits are the effective bits and which are ineffective bits so as to transmit the effective bit length L back to the data sorting unit 101. At the same time, the decoder 102 decodes a 4-bit data. By following this method, six 4-bit data should be processed because the data processing circuit 10 has to decode a 24-bit data and thus the whole process should be repeated six times.
However, when the system is requested to process six 4-bit data within one clock, the data processing circuit according to the prior art can only achieve such request by increasing the processing frequency or memory capacity. But, it causes the problems of increasing the power consumption of the system, raising the temperature of the system, and increasing the cost of the system.
USPTO Backgrounds
USPTO Backgrounds