1. Field of the Invention
Implementations described herein relate generally to semiconductor devices, and, more particularly, to a planarization method using a hybrid oxide and polysilicon chemical mechanical polishing and/or planarization (CMP).
2. Description of Related Art
The escalating demands for high density and performance associated with non-volatile memory devices require small design features, high reliability, and increased manufacturing throughput. The reduction of design features below a critical dimension (CD) challenges the limitations of conventional methodologies.
For example, after CMP, uneven topography may occur. A memory core of a semiconductor device, for example, may contain several memory cells having uneven topography. A peripheral component of the semiconductor device (e.g., a select transistor for a word line driver, a word line, etc.) may have uneven topography with the core memory cells as well. Topography height differences will cause problems in subsequent processing steps of the semiconductor device. However, elimination of uneven topography from semiconductor device components requires expensive lithography, masking, and etching steps. Thus, there is a need to eliminate extra topography and/or provide global planarization (e.g., a totally flat surface) across a semiconductor device without incurring the added expense of these extra manufacturing steps.
USPTO Backgrounds
USPTO Backgrounds