The present invention generally relates to the field of semiconductors, and more particularly relates to vertical field-effect-transistors (FETs) having bottom source/drain epitaxy.
Vertical transistors are a promising option for technology scaling for 5 nm and beyond. However, during fabrication of these transistors it is difficult to form an aligned bottom junction since there is not guarantee that etching of the fins stops at the edge of the highly doped source/drain layer. Conventional fin etching processes usually result in the fins having a wider bottom portion where it is not suitable for forming FET channels.
USPTO Backgrounds
USPTO Backgrounds