1. Field of the Invention
This invention relates to wiring connection structures for semiconductor integrated circuit devices, and more particularly to a wiring connection structure included in a semiconductor integrated circuit device for interconnecting a plurality of wiring layers isolated by an insulating layer, via a through hole formed in the insulating layer.
2. Description of the Background Art
In the manufacture of semiconductor integrated circuit devices having a plurality of wiring layers, it is an essential technical requirement to electrically interconnect an upper wiring layer and a lower wiring layer via a through hole formed in an insulating layer. FIG. 16A is a fragmentary plan view showing a two-layer-wiring connection structure in a conventional semiconductor integrated circuit device. FIG. 16B is a vertical section taken on line XVIB--XVIB of FIG. 16A. FIG. 16C is a cross section taken on line XVIC--XVIC of FIG. 16B and showing a second wiring layer. The conventional two-layer-wiring connection structure will be described hereunder with reference to these drawings.
As illustrated, a first wiring layer 1, e.g. an aluminum wiring layer, is formed on an insulating base layer 5 acting as a substrate. A second wiring layer 2, e.g. an aluminum wiring layer, is formed as insulated and separated from the first wiring layer 1 by an interlayer insulating film 4, e.g. a film of silicon oxide. The interlayer insulating film 4 defines a through hole 33 in a region of the second wiring layer 2 overlapping with the first wiring layer 1. Via this through hole 33 the first wiring layer 1 are electrically interconnected with the second wiring layer 2 in the region where the two layers intersect. The through hole 33 has a rectangular cross section.
In order to secure a large current capacity of the wiring layers having fixed thicknesses, it has been a common practice to form the wiring layers with an extended width. Thus, it is also necessary for the through hole formed for electrical connection between the first and second wiring layers to have the largest possible opening area, in order to minimize the components of resistance of the through hole. For this purpose, the conventional wiring connection structure, as shown in FIG. 16A, includes a through hole having a maximum opening area in the region of intersection between the first and second wiring layers for allowing a connection therebetween.
As, as shown in FIG. 16C, however, the second wiring layer 2 has a reduced thickness where it extends along side walls of the through hole 33. Assuming that the first wiring layer 1 and second wiring layer 2 include flat portions having a thickness t1, the portions of the second wiring layer 2 on the side walls of the through hole 33 have a thickness t2 which is on the order of 10 to 30% of the thickness t1. The portion of the second wiring layer 2 formed in a bottom region of the through hole 33 has a thickness t3 on the order of 50 to 70% of the thickness t1. The interlayer insulating film 4 interposed between the first wiring layer 1 and second wiring layer 2 has a thickness t4 which is about twice the thickness t1. To quote one example of the layer thicknesses, t1 is on the order of 5000 to 10000.ANG..
As noted above, the thickness t2 of the second wiring layer 2 formed on the side walls of the through hole 33 is smaller than the thickness t3 of the flat portions of the first wiring layer 1 and second wiring layer 2 and the thickness t3 of the second wiring layer 2 in the bottom region of the through hole 33. This means the presence of a reduced sectional area in the passage of a current flowing from the second wiring layer 2 to the first wiring layer 1. That is, when a current flows between the first wiring layer 1 and second wiring layer 2 via through hole 33, the current will concentrate in the positions formed along the side walls of the through hole 33. A high density current, e.g. a current having a density of 1.times.10.sup.5 A/cm.sup.2 or more, flowing through a wiring layer tends to cause electromigration. Electromigration is a phenomenon of movement of metallic atoms occurring when a dense flow of electrons collides with the metallic atoms of a wiring layer whereby the electrons become scattered. As a result of electromigration, defects called voids are produced in the wiring layer along grain boundaries. These voids will grow gradually, and the current density will increase with the decrease in the sectional area of the wiring layer, thereby heating and breaking the wiring layer.
Generally, the following measures are considered feasible for improving resistance to the electromigration occurring in the through hole:
(1) Change the material of the wiring layer for one highly resistive to electromigration.
(2) Form a through hole with side walls including tapered portions to increase the thickness of the wiring layer on the side walls.
(3) Disperse the current flowing along the side walls of the through hole by increasing the perimeter around the opening of the through hole. That is, mitigate the concentration of the current density on the side wall of the through hole.
(4) Fill up the through hole to be level with the wiring layer.
Japanese Patent Publications Nos. 58-39380 and 62-23460 disclose wiring connection structures having through holes improved with the measure (3) above. FIG. 17 is a fragmentary plan view showing a wiring connection structure having the through holes disclosed in these publications. According to the wiring connection structure having the improved through holes, the second wiring layer 2 is electrically connected to the first wiring layer 1 via through holes which are standardized into a plurality of small units. That is, in this drawing, the first wiring layer 1 and second wiring layer 2 are electrically interconnected via two through holes 34.
In the improved wiring connection structure, the wiring layers are interconnected via a plurality of through holes having a small opening area. The plurality of through holes have a total perimeter around their openings longer than the perimeter around the opening of a single through hole in the same through-hole forming region. The concentration of the current density on the side walls of the through holes is mitigated where the wiring layers are interconnected via a plurality of through holes, compared with the case where the wiring layers are interconnected via a single through hole. Consequently, a reduced resistance of the wiring layer occurs around the through holes.
Forming a plurality of through holes, however, is not necessarily of advantage in increasing the perimeter around the opening of the through hole. FIG. 18A shows a mask used in forming a plurality of through holes, e.g. four through holes. FIG. 18B is a fragmentary plan view showing an example of finished patterns of the four through holes formed by using the mask shown in FIG. 18A. A resist 9 used as the mask defines a plurality of through hole patterns 302 formed as perforations for providing predetermined perimeters. This mask is used to form a plurality of through holes in an interlayer insulating film 4. If the interlayer insulating film 4 is etched under non-uniform conditions or etched in an insufficient amount, the resulting through holes 32a, as shown in FIG. 18B, have markedly reduced opening areas with respect to the through hole patterns 302. Thus, even if through hole patterns 302 are formed in the mask stage to have long perimeters, the finished patterns of through holes actually formed in the interlayer insulating film 4 have far shorter perimeters than the through hole patterns 302.
Where the through holes are standardized into a plurality of small units, not only is the resistance of the through holes reduced for the increase in the perimeter, but portions are formed that contribute toward an increase in the resistance of the through holes. FIG. 19A is a fragmentary plan view showing a wiring connection structure having, for example, four standardized through holes. FIG. 19B is a fragmentary sectional view taken on line XIXB--XIXB of FIG. 19A. FIG. 19C is a graph showing variations in the resistance occurring along the section of the wiring layer shown in FIG. 19B. It is assumed here that a current flows from the second wiring layer 2 to the first wiring layer 1 via through holes 32 in the direction of arrow i. Components of resistance of the through holes are conceptually grasped as follows, which occur in the course of current flow from the second wiring layer 2 to the first wiring layer 1.
R1: A component of resistance occurring from the second wiring layer 2 to an end of each through hole (i.e. a component of resistance due to the shape of the through holes).
R2: A component of resistance occurring along a side wall of each through hole (i.e. a component of resistance due to the perimeters around the openings of the through holes).
R3: A component of resistance occurring when the current flows through the first wiring layer 1 in the through hole forming region.
R4: A component of resistance occurring when the current flows through the first wiring layer 1 outside the through hole forming region.
It is assumed that, as shown in FIG. 19B, the current flows from the second wiring layer 2 to the first wiring layer 1 via the through holes 32 along the course indicated by the arrows marked with the respective components of resistance. The component of resistance R2 occurring when the current flows along the side walls of the through holes 32 is high as shown in FIG. 19C. This resistance component R2 of all the four through holes 32 taken as a whole is reduced for the increase in the total perimeter of the through holes 32. However, the current having passed through the side wall portion of each through hole 32 flows to the first wiring layer 1 in the bottom portion thereof. At this time, the current flows also to portions of the first wiring layer 1 out of electrical contact with the second wiring layer 2 since there are a plurality of through holes 32. In regions where the first wiring layer 1 and second wiring layer 2 are in electrical contact, the sectional area of the passage of the current is a sum of sectional areas of the first wiring layer 1 and second wiring layer 2. Therefore, as shown in FIG. 19C, the regions of electrical contact between the first wiring layer 1 and second wiring layer 2 have a low resistance component R32. On the other hand, the regions where the current flows only through the first wiring layer 1 in bottom portions of the through hole forming region have a high resistance component R31. In some cases, the resistance component R3 increases despite the reduced resistance component R2 of the all through holes taken as a whole. Thus, even if a plurality of through holes are formed in order to increase the perimeter around the opening of the through hole, there is the problem that this does not necessarily contribute toward a reduction in the resistance occurring in or adjacent the through hole.
USPTO Backgrounds
USPTO Backgrounds