A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode for accumulating photo-generated charge in the specified portion of the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state before the transfer of charge to it; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. No. 6,140,630, U.S. Pat. No. 6,376,868, U.S. Pat. No. 6,310,366, U.S. Pat. No. 6,326,652, U.S. Pat. No. 6,204,524 and U.S. Pat. No. 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12, implemented as a pinned photodiode, transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and a pixel supply voltage Vpix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the pixel supply voltage Vpix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between an array supply voltage Vaa and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal PIX OUT. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal PIX OUT to a column line 22 of a pixel array.
FIG. 1b illustrates a typical timing diagram for the readout and photo-charge acquisition operations for the pixel 10 illustrated in FIG. 1a. FIG. 1b illustrates a first readout period 30 in which previously stored photo-charges are readout of the pixel 10. During this first readout period 30, the reset control signal RST is pulsed to activate the reset transistor 16, which resets the floating diffusion region FD to the pixel supply voltage Vpix level. While the SEL signal is high, a sample and hold reset signal SHR is pulsed to store a reset signal Vrst (corresponding to the reset floating diffusion region FD) on a sample and hold capacitor. The transfer control signal TX is then activated to allow photo-charges from the photosensor 12 to be transferred to the floating diffusion region FD. While the SEL signal remains high, a sample and hold pixel signal SHS is pulsed to store a pixel signal Vsig from the pixel 10 on another sample and hold capacitor.
During the acquisition period 32, the reset control signal RST, transfer control signal TX and sample and hold signals SHR, SHS are set to a ground potential GRND. It is during the acquisition period 32 that the photosensor 12 accumulates photo-charge based on the light incident on the photosensor 12. After the acquisition period 32, a second readout period 34 begins. During the second readout period 34, the photo-charges accumulated in the acquisition period 32 are readout of the pixel 10 (as described above for period 30).
One common problem associated with conventional imager pixel cells, such as pixel cell 10, is dark current (that is, current generated as a photodiode signal in the absence of light). As shown in the potential diagram of FIG. 1c, a major component of dark current occurs underneath the gate of the transfer transistor 14. These “dark carriers” 25 are accumulated on the pinned photodiode photosensor 12 during integration (i.e., during the acquisition period 32), which creates parasitic dark charge that is added to the light signals when they are readout. This is undesirable.
Accordingly, there is a desire and need to reduce dark current and the factors that cause dark current in imagers.
USPTO Backgrounds
USPTO Backgrounds