The invention relates generally to integrated circuit packages and, more particularly, to an apparatus and method of fabricating a package having a reduced stacking height thereof.
Integrated circuit (IC) packages are typically fabricated having a number of embedded silicon devices such as memory chips, microprocessors, translation circuitry, buffering, switching, and the like. In order to combine and increase functionality of an IC, it is often desirable to stack and interconnect various die types into a single device or package. Thus, embedded chip packages can be manufactured having a plurality of chips or electronic components in a stacked 3D arrangement. The plurality of chips or electronic components are electrically connected to an input/output system by way of metal interconnects routed through a plurality of laminate re-distribution layers.
Advancements in IC packaging requirements pose challenges to the existing embedded chip build-up process. That is, it is desired in many current embedded chip packages to have an increased number of re-distribution layers, with eight or more re-distribution layers being common. The advancements are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. New packaging technology also has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale. Thus, as ICs become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packaging, to laminate-based ball grid array (BGA) packaging, to chip-scale packaging (CSP), to flipchip packages, and to embedded chip build-up packaging.
There are a variety of known methods for stacking die to form a stacked package. One method includes stacking on the wafer level. In this approach, the dies are kept in wafer format and are stacked on top of each other and bonded together at high temperatures. Typically the layer-layer connections are formed by thru silicon vias. However, this method limits the mixing of die types that can be intermixed in the IC package. Another method is by stacking on the individual die level. Typically this method includes mounting a single die to a lead frame chip carrier interconnect platform and additional dies are then glued and stacked on top of each other. The interconnect is then formed by wirebonding to the exposed pads of the stacked die and to an I/O of the lead frame. However, this arrangement also limits the use of die types to those having perimeter connections and pyramid die stacking.
Additionally, these stacking methods typically result in an unacceptably thick package height. In order to handle and process the die (in either wafer format or as individual die), each must be typically 250 microns or greater in thickness. Thus, when in final package form, an 8-layer structure, for example, may be 2 mm or more in thickness. Such a package may be cumbersome to work with, expensive to fabricate and process, and may be fragile to handle for subsequent processing and usage. Also, such limitations may limit the overall number of layers in the final package if there is a restrictive total package thickness for the final application, thus limiting the functionality and performance.
Accordingly there is a need for a method for embedded chip fabrication that allows for the application of multiple dies and die types in a stacked arrangement with a reduced overall stack height. There is a further need for embedded chip fabrication that allows for the application of multiple re-distribution layers and also provides a simple flexible stacking method.
It would therefore be desirable to have a system and method capable of processing and fabricating a stacked IC package having a reduced package thickness.
USPTO Backgrounds
USPTO Backgrounds