1. Technical Field
The present invention relates to a data transmission control device, and particularly, to a technique that improves the efficiency of data transmission.
2. Related Art
Conventionally, a CPU (Central Processing Unit) included in a printer controller that controls a printer utilizes a DRAM (Dynamic Random Access Memory), etc. as a main memory. The CPU and the DRAM perform data transmission mutually via a memory control ASIC (Application Specific Integrated Circuit).
The memory control ASIC controls data transmission between a printing engine and the DRAM, or data transmission between various devices, such as a personal computer (hereinafter referred to as “PC”), and the DRAM.
Generally, the control in the data transmission with the DRAM of the memory control ASIC is performed according to a sequence including (bank) active processing, read/write processing, and precharge processing. Here, the (bank) active processing is the processing that the memory control ASIC designates a row address on the DRAM. The read/write processing is the processing that the memory control ASIC makes a storage element having the address designated by active processing execute predetermined processing including read processing and write processing. The precharge processing is the processing that the memory control ASIC holds the data of the storage element that has undergone the read/writing processing.
Further, the precharge processing is performed after lapse of several clock periods from the read/write processing in consideration of execution time of read/write processing.
In the method of controlling data transmission according to the sequence as described above, if the memory control ASIC gets continuous access to the DRAM, the same sequence is repeated. Accordingly, even if the memory control ASIC gets continuous access to the same page of the DRAM, the processing that has no problem even if not executed, such as precharge processing or active processing after read/write processing.
Thus, a technique of suppressing execution of the processing that has no problem even if not executed when the memory control ASIC gets continuous access to the same page of the DRAM has been developed. For example, in the related art, the memory control ASIC determines whether the access to the same page is continuous when it accesses to the DRAM, and does not executes the processing that has no problem even if not executed. In the following, the event that the memory control ASIC gets continuous access to the same page of the DRAM is called “page hit.”
However, there is a problem with the relates art in that the probability of page hit is low because the above determination period is fixed to one clock period of a system clock.
USPTO Backgrounds
USPTO Backgrounds