1. Technical Field
The present invention relates in general to integrated circuits. More particularly, the present invention relates to providing power to integrated circuits. Still more particularly, the present invention relates to a system and method of compensating for effects of on-chip processing variation on an integrated circuit.
2. Description of the Related Art
As integrated circuits increase in size and complexity, improvements in lithography have led to smaller device dimensions and interconnect pitches. The reduction of device dimensions and interconnect pitches contribute to increased relative variation in processing across each integrated circuit. Several properties such as effective channel length, gate oxide thickness, threshold voltages, and other device parameters vary over a single integrated circuit. These device parameter variations affect device characteristics, which contribute to variations in operating frequency and power dissipation across the integrated circuit.
FIG. 2 is a pictorial representation of on-chip processing variation across a critical path on an integrated circuit 200 according to the prior art. Included in integrated circuit 200 are exemplary circuits 208a-208e. Circuits 208a-208e, coupled by interconnect 210, form a path across integrated circuit 200. Also, as illustrated in FIG. 2, regions 202, 204, and 206 define regions on integrated circuit 200 where the processing in those regions are characterized as “slow”, “nominal”, and “fast”, respectively. Those with skill in this art will appreciate that regions with processing characterized as “slow” typically limit the frequency in which a signal may propagate through the region. An integrated circuit designer can remedy this problem by increasing the supply voltage. Consequently, regions with processing characterized as “fast” typically operate at a higher frequency at the same voltage setting as a “slow” region. The “fast” regions of an integrated circuit contribute to DC leakage currents. As well-known to those with skill in this art, integrated circuit 200 is typically coupled to a single power supply (not illustrated in FIG. 2). The region with processing characterized as “slow” limits the cycle time and the maximum operating frequency of integrated circuit 200. Likewise, the region with processing characterized as “fast” contribute to power consumption or dissipation through DC. leakage currents. If a designer utilizes integrated circuit 200 in a power-sensitive application, raising the supply voltage often requires the designer to lower the operating frequency to reduce the power dissipation effects of “fast” regions. Therefore, there is a need for a system and method of minimizing differences in frequency and power dissipation across various regions of an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds