In recent years, the use of solid-state memory devices as a form of data storage media in computer and other electronic equipment has become widespread. For example, programmable ROMs (PROMs), which are non-volatile, are often used for storing data or programs which do not change frequently and which must survive when power is removed from the memory.
All PROM's can be programmed at least once. However, there are also types of PROMs that can be erased. For example, flash non-volatile read only memory (NVROM) devices, such as electrically erasable PROMs (EEPROMs) or the like, are widely used to provide high density non-volatile memory that is capable of in-system reprogrammability.
In the case of a conventional EEPROM, which is a polysilicon floating gate flash device, a “0” state is defined by the voltage on the floating gate being above a Vt(0) level while a “1” state is defined by the voltage on the gate being below a Vt(1) level. In other words, a “0” state occurs when the floating gate is charged with electrons to a voltage above a threshold level. The cell is erased to the “1” state by applying a voltage of opposite polarity to erase the negative charge. It will be appreciated, therefore, that sufficient electron mobility within a cell can cause the cell to transition to Vt(1), thereby resulting in a loss of the “0” state. However, because electrons migrate so slowly over time, state changes due to electron migration are generally not a problem. Therefore, once each cell has been programmed to a “0” state by creating a negative charge on the cell, it will generally remain in the “0” state until the cell is intentionally erased to the “1” state by erasing the charge on the cell.
On the other hand, exposure of the gate region of the cell to ultraviolet light will vastly accelerate movement of electrons in the gate region and can cause a state transition. This can be a particular problem during device fabrication, since the gates are often exposed to UV light during deposition, etching, and other steps in the normal fabrication process. Exposure to UV light during fabrication can cause such high electron mobility that it renders the cell unprogrammable or unerasable. Sensitivity to UV during processing is further exacerbated due to the fact that the reduced operating voltages of newer devices have brought Vt(0) closer to Vt(1).
Therefore, a need exists for a method of reducing in-line UV charging during processing of flash NVROM devices to enhance the yield and reliability of these devices. The present invention satisfies those needs, as well as others, and overcomes the deficiencies found in previously developed solutions.
USPTO Backgrounds
USPTO Backgrounds