This application is related to the U.S. application titled SEMICONDUCTOR DEVICE WITH A SINGLE BASE REGION AND METHOD THEREFOR, Ser. No. 09/425,623, by Prasad Venkatraman, filed of even date herewith, and is subject to a common obligation of assignment with this application.
The present invention relates to semiconductor devices in general and, more particularly, to a semiconductor device having an undulating base region and a method of manufacturing such a device.
Vertical insulated gate field effect transistors (IGFETs) are commonly used for power transistor applications, such as anti-lock brake systems, electronic power steering, solid-state relays, and switching power supplies. Such transistors generally have a large number of cells and are preferred because they offer a low on-resistance per unit area, which, for example, benefits battery powered applications. The low on-resistance is largely the result of the relatively high channel density of a cellular design. Channel density is the amount of horizontal channel width within a given area.
FIG. 1 illustrates an example of a typical cellular IGFET layout for a vertical transistor found in the prior art. Device 10 includes a plurality of cells 12 surrounded by a gate layer 14, made of for example polysilicon. Gate layer 14 has straight-sided gate edges 15. Within each cell 12, a base contact region 16 is surrounded by a source region 18. A conventional base region (not shown), which is a doped region for providing a channel region induced and controlled by gate layer 14, is disposed underneath source region 18 and gate edges 15. Each cell 12 has a substantially square or polygonal shape and typical layout dimension of less than a few microns on each side. During the manufacture of such a cellular IGFET, base contact regions 16 are defined by photoresist pillars, which are used to block dopant from entering the area of the semiconductor substrate that provides base contact regions 16, during the implant step used to form source region 18.
One manufacturing problem with a cellular design is that as the dimensions of the cell become smaller, the dimensions of the photoresist pillars also must become smaller such that they approach the limits of the resolution possible with the photolithography methods used to manufacture the device. This makes it difficult to define and form the photoresist pillars. One specific problem resulting from approaching these resolution limits is the tendency of one or more of the pillars to be improperly formed or missing. This leads to base contact regions 16 missing from one or more cells so that the final manufactured device is rejected.
Another manufacturing problem with a cellular design is related to the electrical isolation of the base regions of each cell. All base regions should be at the same electric potential in order to improve the breakdown voltage and unclamped inductive switching (UIS) characteristics of the final device. Each base region is conventionally electrically isolated in an epitaxial layer, and it is necessary that the overlying source electrode interconnect layer (not shown) make good contact to each base region through each corresponding base contact region 16 so that all base regions are at the same potential. However, because of the large number of such base contacts, there is a significant chance that one or more base regions will not be properly contacted. This is especially true when, as discussed above, photoresist pillars are used to form base contact regions 16. Thus, there is often a significant reliability yield loss resulting in the rejection of many final devices from each semiconductor wafer used during manufacture due to the improper formation of one or more base contacts in each device.
An alternative structure that is more manufacturable than a cellular design is a so-called straight or linear-stripe design, in which source stripes are placed within base stripe regions. Such a straight-stripe design reduces the manufacturing difficulty of a cellular design since the longitudinal layout dimension of the stripe is relatively large. However, straight-stripe designs exhibit reduced channel density relative to cellular designs.
Accordingly, a need exists for a power transistor that provides good channel density and good electrical contacts to the base region resulting in a more uniform electric potential and that reduces the manufacturing difficulties associated with forming photoresist pillars or other features of minimum size in a narrow device cell.
USPTO Backgrounds
USPTO Backgrounds