Prefetchers are used to fetch program instructions and program data so that a processor can readily avail itself of the retrieved information as it is needed. The prefetcher predicts which instructions and data the processor might use in the future so that the processor need not wait for the instructions or data to be accessed from system memory, which typically operates at a slower rate than the processor. With a prefetcher implemented between a processor and system memory, the processor is less likely to remain idle as it waits for requested data from memory. As such, prefetchers generally improve processor performance.
Generally, the more predictions generated by a prefetcher, the more likely that the prefetcher can arrange to have the necessary instructions and data available for a processor, thereby decreasing the latency of a processor. But conventional prefetchers typically lack sufficient management of the prediction process, and therefore are prone to overload computational and memory resources when the amount of predicted addresses exceeds what the prefetchers can handle. So to prevent resource overload, traditional prefetchers tend to be conservative in generating predictions so as not to generate an amount of predictions that could overload the prefetcher.
In view of the foregoing, it would be desirable to provide a system, an apparatus and a method for effectively managing predictive accesses to memory.
USPTO Backgrounds
USPTO Backgrounds