This invention relates to a solid state image sensor, more particularly to a solid state image sensor which can improve photic sensitivity of photodiodes by providing only one transmission line between the photodiodes.
As manufacture of high density solid state image sensor advances, there has been significant increase of resistance of the sensor because of the greater area of the chip, and the longer and wider transmission lines. In case where a driving clock signal is transmitted to a transmission gate through a transmission line in the solid state image sensor having high resistance, since the driving clock signal can not be transmitted to the transmission gate fully due to RC delay of the transmission line, perfect shift of signal charge could not have been done. Due to this, the solid state image sensor has had problems that it outputs signals distorted depending on the position.
FIG. 1 shows a plane view of a conventional solid state image sensor, and FIG. 2 is a sectional illustration of a unit cell of the solid state image sensor of FIG. 1.
Referring to FIG. 1, the conventional solid state image sensor is a device driven in 4-phase driving method wherein two tiers of transmission lines are provided between adjacent photodiodes 16-1 and 16-2 to provide four transmission lines to every two photodiodes 16 for transmission of four driving clock signals thereto at a time. That is, of the two photodiodes, with one photodiode 16-1 being assigned a first transmission gate 19-1 for applying a first clock signal thereto and a second transmission gate 19-2 for applying a second clock signal thereto, and with the other photodiode 16-2 being assigned of a third transmission gate 19-3 for applying a third clock signal thereto and a fourth transmission gate 19-4 for applying a second clock signal thereto. The first transmission gate 19-1, the second transmission gate 19-2, the third transmission gate 19-3, and the fourth transmission gate 19-4 are connected to a first transmission line 20-1, a second transmission line 20-2, a third transmission line 20-3, and a fourth transmission line 20-4, respectively.
A plurality of additional transmission lines 21, lengthy extensions over the transmission gates 19 forming a two tiered structure with light shielding films 22, are connected to the transmission gates through contacts 23, and are connected to the light shielding films 22 through the contacts 24. The plurality of additional transmission lines 21, provided on the wide transmission gates for preventing distortion of signals by the RC delay of the transmission lines, are formed of a low resistance conduction material. That is, of the plurality of additional transmission lines 21, a first additional transmission line 21-1 is connected to the first transmission gate 20-1 for applying the first driving clock signal .o slashed.IM1 to the first transmission gate 20-1, a second additional transmission line 21-2 is connected to the second transmission gate 20-2 for applying the second driving clock signal .o slashed.IM2 to the second transmission gate 20-2, a third additional transmission line 21-3 is connected to the third transmission gate 20-3 for applying the third driving clock signal .o slashed.IM3 to the third transmission gate 20-3, and a fourth additional transmission lines 214 is connected to the fourth transmission gate 20-4 for applying the fourth driving clock signal .o slashed.IM4 to the fourth transmission gate 20-4.
In the meantime, as shown in FIG. 2, the unit cell of the solid state image sensor includes a first p-type well 12 formed on a substrate 11, a second p type well 13 formed in the first p-type well 12, an n-type photodiode 16 and an n-type BCCD (Buried Charge Coupled Device) 14 formed in the first, and second p type wells 12 and 13 respectively, and a p.sup.++ type surface isolation layer 17 formed on the n type photodiode 16. And, an additional transmission line 21 is connected to a light shielding film 22 through a contact 24. The reference number 15 represents a p.sup.+ type channel stop region for isolating cells, and reference numbers 18 and 25 represent a gate insulation film and an interlayer insulation film, respectively.
The solid state image sensor has a transmission gate 19 and a transmission line 20 formed by appropriate patterning of a first polycrystalline silicon film and a second polycrystalline silicon film between the photodiodes, and an additional transmission line 21 formed by appropriate patterning of a third polycrystalline silicon film on an electrode. In this time, the transmission line, the transmission gate and the light shielding film are formed to be insulated by the insulation film 25.
The conventional solid state image sensor could have eliminated the RC delay by reducing resistance of the transmission line with the additional transmission line formed on the wide electrode. However, since the driving clock signal transmission lines are formed in two tiers between two adjacent photodiodes, the underside transmission line is wider than the upperside transmission line. Accordingly, this increase of width of the transmission line between the two adjacent photodiodes decreases areas of photodiode regions provided for sensing lights, with decrease of a fill factor. According to this, the conventional solid state image sensor has a problem of degradation of the photic sensitivity, which becomes more serious as the device becomes denser.
USPTO Backgrounds
USPTO Backgrounds