This well separation technique enables a first well formed in a semiconductor substrate to be supplied with a desired voltage different from that applied to the semiconductor substrate, by electrically separating the first well from a second well formed therearound.
This technique is applied to a variety of semiconductor integrated circuit devices such as a DRAM (Dynamic Random Access Memory) in which a memory cell is formed in a first well, for example, to apply a back bias voltage to the MIS.multidot.FET (Metal Insulator Semiconductor Field Effect Transistor) of the memory cell, or a flash memory (EEPROM: Electrically Erasable Programmable ROM), in which a negative voltage is applied to the first well.
Here will be described a semiconductor integrated circuit device having a well separation structure examined by us.
At the well separation region in the semiconductor substrate of a second conductivity type, more specifically, there are formed a deep well of a first conductivity type and a shallow well of the second conductivity type which is formed in the region of the deep well. This deep well is formed by diffusing an impurity from the major surface to a deep position of the semiconductor substrate to encompass the outer periphery of the shallow well and to separate the shallow well and semiconductor substrate electrically. As a result, the shallow well can be fed with a voltage different from that to be applied to the semiconductor substrate.
In another region of the semiconductor substrate, there are formed an ordinary well of the first conductivity type and an ordinary well of the second conductivity type. These wells of the first conductivity type and the second conductivity type are formed by diffusing an impurity from the major surface to a predetermined position of the semiconductor substrate.
USPTO Backgrounds
USPTO Backgrounds