1. Field of the Invention
The invention relates to methods for producing epitaxially coated silicon wafers.
2. Background Art
Epitaxially coated silicon wafers are suitable for use in the semiconductor industry, in particular for the fabrication of large scale integrated electronic components such as microprocessors or memory chips. Starting materials (substrates) with stringent requirements for global and local flatness, thickness distribution, single-side-referenced local flatness (nanotopology) and freedom from defects are required for modern microelectronics.
Global flatness relates to the entire surface of a semiconductor wafer minus an edge exclusion to be defined. It is described by the GBIR (“global backsurface-referenced ideal plane/range,” or magnitude of the positive and negative deviation from a backside-referenced ideal plane for the entire front side of the semiconductor wafer), which corresponds to the TTV (“total thickness variation”) specification that was formerly customary.
The LTV (“local thickness variation”) specification that was formerly customary is nowadays designated according to the SEMI standard by SBIR (“site backsurface-referenced ideal plane/range,” or magnitude of the positive and negative deviation from a backside-referenced ideal plane for an individual component area of defined dimension) and corresponds to the GBIR or TTV of a component area (“site”). Therefore, in contrast to the global flatness GBIR, the SBIR is referenced to defined fields on the wafer, that is to say for example to segments of an area grid of measurement windows having a size of 26×8 mm2 (site geometry). The maximum site geometry value SBIRmax specifies the maximum SBIR value for the component areas taken into account on a silicon wafer.
According to the prior art, a silicon wafer can be produced by a process sequence that essentially comprises separating a single crystal of silicon into wafers, rounding the mechanically sensitive edges of the silicon wafers, and carrying out an abrasive step such as grinding or lapping, followed by polishing. The final flatness is generally produced by the polishing step, which may be preceded, if appropriate, by an etching step for removing disturbed crystal layers and for removing impurities.
In the case of polished silicon wafers, therefore, an attempt is made to achieve the required flatness by suitable processing steps such as grinding, lapping and polishing. However, the polishing of a silicon wafer usually gives rise to a decrease in the thickness of the planar silicon wafer toward the edge (“edge roll-off”). Etching methods also tend to attack the silicon wafer to be treated to a greater extent at the edge and to produce such an edge roll-off.
In order to counteract edge roll-off, it can be expedient for silicon wafers to be polished concavely or convexly. A concavely polished silicon wafer is thinner in the center and then increases in its thickness toward the edge. Silicon wafers polished in this way then have an undesired decrease in thickness only in their outermost edge region.
DE 19938340 C1 describes depositing a monocrystalline layer on monocrystalline silicon wafers, the layer consisting of silicon with the same crystal orientation, a so-called epitaxial layer. Such an epitaxial deposition step is usually preceded by stock removal polishing such as DSP (double-side polishing), final polishing such as CMP (chemomechanical polishing) and a cleaning step. DSP and CMP essentially differ in that a softer polishing cloth is used in CMP and normally only the front side of the silicon wafer is polished in a haze-free manner (“finishing”).
DE 10025871 A1 discloses a method for producing a silicon wafer with an epitaxial layer deposited on its front side, this method comprising the following process steps:
(a) a stock removal polishing step as the sole polishing step;
(b) (hydrophilic) cleaning and drying of the silicon wafer;
(c) pretreatment of the front side of the silicon wafer at a temperature of 950 to 1250 degrees Celsius in an epitaxy reactor; and
(d) deposition of an epitaxial layer on the front side of the pretreated silicon wafer.
It is customary, in order to protect silicon wafers from particle loading, to subject the silicon wafers to a hydrophilic cleaning after polishing. The hydrophilic cleaning produces native oxide on the front and rear sides of the silicon wafer which is very thin (approximately 0.5-2 nm, depending on the type of cleaning and measurement). This native oxide is removed in the course of a pretreatment in an epitaxy reactor under a hydrogen atmosphere (also called H2 bake).
In a second step, the surface roughness of the front side of the silicon wafer is reduced and polishing defects are removed from the surface by usually small amounts of an etching medium, for example gaseous hydrogen chloride (HCl), being added to the hydrogen atmosphere.
Sometimes, besides an etching medium such as HCl, a silane compound, for example silane (SiH4), dichlorosilane (SiH2Cl2), trichlorosilane (TCS, SiHCl3) or tetrachlorosilane (SiCl4), is also added to the hydrogen atmosphere in an amount such that silicon deposition and silicon etching removal are in equilibrium. Both reactions proceed at a sufficiently high reaction rate, however, so that silicon on the surface is mobile and the surface is smoothed and defects are removed on the surface.
Epitaxy reactors, which are used in particular in the semiconductor industry for the deposition of an epitaxial layer on a silicon wafer, are described in the prior art. During all coating or deposition steps, one or more silicon wafers are heated by means of heating sources, preferably by means of upper and lower heating sources, for example lamps or lamp banks, and subsequently exposed to a gas mixture, comprising a source gas, a carrier gas and, if appropriate, a doping gas.
A susceptor, which comprises graphite, SiC or quartz, for example, serves as a support for the silicon wafer in a process chamber of the epitaxy reactor. During the deposition process, the silicon wafer rests on this susceptor or in milled-out portions of the susceptor in order to ensure uniform heating and to protect the rear side of the silicon wafer, on which usually there is no layer deposition, from the source gas.
The process chambers of the epitaxy reactor are designed for one or more silicon wafers. In the case of silicon wafers having relatively large diameters, in particular in the case of silicon wafers having a diameter of 300 mm or 450 mm, single wafer reactors are usually used, wherein the silicon wafers are processed individually especially since this usually results in a uniform epitaxial layer thickness. The uniformity of the layer thickness can be improved in this case by adapting the process conditions, for example by optimizing the gas flows (H2, SiHCl3), by incorporating and adjusting gas inlet devices (injectors), by changing the deposition temperature or else by modifications to the susceptor.
In epitaxy it is furthermore customary, after one or more epitaxial depositions on silicon wafers, to carry out an etching treatment of the susceptor without a substrate, in the course of which the susceptor and also other parts of the process chamber are freed of silicon deposits.
The production of epitaxially coated silicon wafers with good global flatness proves to be extremely difficult since, as mentioned above, a concavely or convexly polished silicon wafer is usually present as the substrate. In the prior art, after the epitaxy, the global flatness and also the local flatness of the epitaxially coated silicon wafer have usually deteriorated compared with those of the polished silicon wafer. This is associated, inter alia, with the fact that the deposited epitaxial layer itself also has a certain, albeit small, thickness irregularity despite all optimization measures.
The deposition of an epitaxial layer of varying thickness (e.g. higher deposition in the center and less deposition at the edge of the wafer) in order to compensate for the non-uniform form of the polished silicon wafer and in this way also to improve the global flatness of the silicon wafer is not considered in the epitaxy of silicon wafers, since the thickness regularity of the epitaxial layer has to vary within defined limits in order to satisfy customer requirements.
DE 102005045339 B4 discloses a method for producing epitaxially coated silicon wafers, in which a multiplicity of silicon wafers which are polished at least on their front sides are provided and are successively coated individually in each case in an epitaxy reactor by a procedure in which a respective one of the silicon wafers provided is placed on a susceptor in the epitaxy reactor, is pretreated under a hydrogen atmosphere at a first hydrogen flow rate of 20-100 slm in a first step and with addition of an etching medium to the hydrogen atmosphere at a second, reduced hydrogen flow rate of 0.5-10 slm in a second step, is subsequently coated epitaxially on its polished front side and is removed from the epitaxy reactor, and an etching treatment of the susceptor is furthermore effected in each case after a specific number of epitaxial coatings.
DE 102005045339 B4 likewise discloses a silicon wafer having a front side and a rear side, wherein at least its front side is polished and an epitaxial layer is applied at least on its front side, and which has a global flatness value GBIR of 0.07-0.3 μm, relative to an edge exclusion of 2 mm. The comparatively good geometry of this epitaxially coated silicon wafer results from the fact that the reduction of the hydrogen flow rate in the second step of the pretreatment with addition of an etching medium makes it possible to etch away material at the edge of the silicon wafer in a targeted manner and to globally level the silicon wafer actually before the epitaxial-coating step. Disadvantages of the method are that although the reduced hydrogen flow rate intensifies the etching effect at the edge of the polished wafer, the gas flow over the semiconductor wafer is not laminar. This obviates further optimization of the global flatness below the best possible GBIR value of 0.07 μm claimed in DE 102005045339 B4.
US 2008/0182397 A1 discloses an epitaxy reactor which provides different gas flows in a so-called “inner zone” and a so-called “outer zone”. For a wafer having a diameter of 300 mm, the “inner zone” is specified as a central region of the 300 mm wafer having a diameter of 75 mm. The setting of the different gas flows in the reactor is effected by setting the diameter of the gas pipes; thus, e.g. reducing the pipe diameter also reduces the gas flow in the direction of one of the two zones. Such gas distribution systems are commercially available from Applied Materials Inc. under the name Epi Centura Accusett™ (Epi Centura is the name of the epitaxy reactor from Applied Materials Inc.). As an alternative, for controlling the gas flows it is also possible to use so-called “Mass Flow Controllers” or similar devices for regulating the flow. The gas distribution in inner and outer zones is designated by I/O in US 2008/0182397 A1. This notation will also be used in the context of the present invention.
US 2008/0182397 A1 specifies two ranges for gas distribution I/O: firstly a range of I/O=0.2-1.0 during the epitaxial coating and secondly an I/O of 1.0-6.0 during the etching step (substrate pretreatment).
US 2008/0245767 A1 discloses a method in which a contaminated or damaged layer of a substrate is removed by means of an etching gas in order to uncover a substrate surface. This cleaned substrate can subsequently be epitaxially coated. The flow rate of the etching gas is 0.01-15 slm. If an inert gas (inert with respect to the substrate material, e.g. silicon) in particular, hydrogen, or else nitrogen, argon, helium or the like is supplied, the flow rate thereof is 1-100 slm. The temperature of the substrate is 600-850° C. 1.0-7.0 (5/5-35/5) is specified as the I/O ratio of the hydrogen flow.
US 2007/0010033 A1 discloses influencing the thickness of an epitaxially deposited layer by regulating the gas distribution in an inner and an outer zone. As mentioned above, however, the deposition of a thicker epitaxial layer in the center of the concavely polished silicon wafer, in order to compensate for the initial geometry of the polished wafer, is unsuitable since the specification of the layer thickness regularity of the epitaxial layer would thereby be exceeded.
The prior art indicates various solution routes for obtaining an improvement in the geometry of the substrate and/or the epitaxially coated silicon wafer by means of a corresponding choice of the processing conditions during the pretreatment steps and during the epitaxial coating.
However, the proposed methods, as described above, are associated with other disadvantages and for example are not suitable at all for improving a likewise frequently encountered geometry of the substrate to be epitaxially coated, namely the so-called “sombrero” form, in this way. The “sombrero” form is distinguished by the fact that the thickness is increased both at the edge and in the center of the wafer. If the total thickness of the substrate is plotted against the diameter, the thickness profile is similar to the form of a sombrero.
USPTO Backgrounds
USPTO Backgrounds