The present invention relates to a high speed complementary MOSFET logic circuit which is interchangeable with a TTL circuit.
An integrated circuit formed of complementary MOSFETs (referred to as CMOSFETs) has many advantages such as low power dissipation, high noise-tolerance and wide dynamic voltage range. Since the operation of a CMOSFET circuit with such advantages is slower than a TTL circuit (transistor-transistor logic), a CMOSFET circuit replaces a TTL circuit only when a relatively slow operation is required. Recently, remarkable progress in microelectric technology has realized high speed operable CMOSFETs. Many attempts have been made to realize a high performance circuit with low power dissipation and high speed operation, in which a low power but high speed CMOSFET circuit, in place of the high power TTL circuit, is combined with an LS (Low power Schottky) TTL circuit having a relatively lower power dissipation.
With respect to an output characteristic of a TTL circuit such as an LS-TTL circuit, when the power source voltage V.sub.DD is 5 V, a high level voltage V.sub.OH is approximately a 2 V minimum and a low level voltage V.sub.OL is approximately a 0.8 V maximum. An input voltage characteristic of a CMOSFET circuit, is that, when the power source voltage V.sub.DD is 5 V, a high level voltage V.sub.IH is approximately 4 V, a low level voltage V.sub.IL is approximately 1 V, and a circuit threshold voltage V.sub.thc is half of the power source voltage V.sub.DD, i.e., approximately 2.5 V.
Referring to FIG. 1, when a high speed CMOSFET circuit 2 is used in a system circuit which is mostly formed of an LS-TTL circuit 1, an interface circuit 3 such as a boost circuit must be provided at the prestage of the CMOSFET circuit 2. For obtaining a high speed CMOSFET circuit which is perfectly compatible with the TTL circuit, without the interface circuit 3, its input characteristic must be modified so as to be adaptable to the output characteristic of the TTL circuit. For example, when V.sub.DD is 5 V, the input voltage characteristic of the CMOSFET circuit must be set such that V.sub.IH .perspectiveto.2 V and V.sub.IL .perspectiveto.0.8 V, in order to comply with the output level of the TTL circuit.
FIG. 2 shows a circuit diagram of a prior CMOS inverter in which a P channel MOSFET (referred to as a PMOSFET) 11 and an N channel MOSFET (referred to as an NMOSFET) 12 are inserted in series between power source voltages V.sub.DD and V.sub.SS, an input signal IN is commonly applied to the gates of the FETs 11 and 12, and an output signal OUT is derived from a junction of the FETs 11 and 12. The inverter thus arranged has an input voltage V.sub.IN vs. output voltage V.sub.OUT characteristic as shown in FIG. 3. An input voltage V.sub.IN, when the output voltage V.sub.OUT shifts from V.sub.SS to V.sub.DD or vice versa, is a circuit threshold voltage V.sub.thc. The circuit threshold voltage, when the FETs 11 and 12 are in a saturated state, is expressed by the following equation: ##EQU1## where V.sub.thN : threshold voltage of the NMOSFET,
V.sub.thP : threshold voltage of the PMOSFET, PA1 K.sub.P : coefficient of the source-drain current of the PMOSFET, and PA1 K.sub.N : coefficient of the source-drain current of the NMOSFET. PA1 W.sub.N : channel width of the NMOSFET, PA1 L.sub.P : channel length of the PMOSFET, PA1 L.sub.N : channel length of the NMOSFET, PA1 t.sub.ox : thickness of the gate oxide film, PA1 .epsilon..sub.ox : dielectric constant, PA1 .mu..sub.p : effective mobility of holes, and PA1 .mu..sub.N :effective mobility of electrons.
These coefficients K.sub.P and K.sub.N are also: ##EQU2## where W.sub.P : channel width of the PMOSFET,
As seen from equation (1), in order to improve the electrical characteristics of the input voltage V.sub.IH and V.sub.IL of the high speed CMOSFET circuit (inverter), that is, to change the input voltage V.sub.IH from 4 V to 2 V when V.sub.DD =5 V or to reduce the threshold voltage V.sub.thc, the V.sub.thP is enlarged and the coefficient K.sub.P is reduced. This may be attained by adjusting the conductance g.sub.m of the PMOSFET 11. When these factors V.sub.thP and K.sub.P are changed as just mentioned, however, a rise time t.sub.r, for example, when the high speed CMOS inverter operates, is made larger than that before these factors were changed, resulting in the deterioration of the operation speed of the inverter. Thus, the prior CMOSFET circuit has difficulty in gaining both high operation speed and perfect compatibility with the TTL circuit.
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