1. Field of the Invention
The principles of the present invention are generally related to resistive memory arrays, and in particular, but not by way of limitation, to a device and method for configuring a resistive memory array, writing and reading from the resistive memory array, and producing the resistive memory array.
2. Description of Related Art
Resistive memory materials have recently been used to produce non-volatile memory cells. Data is stored in the memory cells by changing resistance of the resistive memory materials. Resistive memory materials may include colossal magnetoresistance (CMR) material, high temperature superconductivity (HTSC) materials, or other materials that have a perovskite structure capable of having electrical resistance characteristics altered by external influences. Such external influences may include applying positive and negative or reverse polarity voltages to the resistive memory materials to change the resistance characteristics thereof. The electric field strength or electric current density from one or more pulses is generally sufficient to switch the physical state of the resistive memory materials so as to modify the resistive properties. Alternatively, a pulse with the same polarity, but with different pulse widths, may be utilized to reverse the resistive property of the resistive memory materials previously set. Whichever technique is selected, in applying a pulse to the resistive memory materials, the pulse is to be low enough in energy so as not to destroy or damage the resistive material.
FIG. 1 is a schematic of a resistive memory array 100 provided in U.S. Pat. No. 6,841,833 to Hsu et al. The memory array 100 utilizes a 1-transistor, 1-resistor (1T1R) memory cell configuration and includes sixteen memory cells 102 composed of a resistive memory element in series with a transistor. The memory array 100 includes columns of bit lines BL1-BL4 and rows of word lines WL1-WL4. In addition, a common line CL extends between bit line pairs BL1-BL2 and BL3-BL4 is shared by every two bits (i.e., memory cells) connected between the bit line pairs BL1-BL2 and BL3-BL4. While the memory array 100 is reduced in size by having two bits share a common line CL, the consequence is that the memory array 100 is not a random access memory. Instead, all of the memory cells 102 must be erased before a write operation. By having to erase all of the memory cells, the use of such a resistive memory array 100 is slow and is inefficient.
USPTO Backgrounds
USPTO Backgrounds