Microprocessors perform computational tasks in a wide variety of applications. Improved processor performance is almost always desirable, to allow for faster operation and/or increased functionality through software changes. In many embedded applications, such as portable electronic devices, conserving power is also an important goal in processor design and implementation.
Many modern processors employ dynamic voltage and frequency scaling techniques which include varying the operating frequency and voltage levels of a processor depending on processing demand in order to save energy consumption. When a processor runs off a slower clocking frequency, lower operating voltages may be utilized for charging circuits, resulting in lower power utilization.
One conventional technique for varying frequency includes a programmable phase-locked loop (PLL) which is run at one frequency, suspended from operation, re-programmed to operate at a different frequency while the PLL is suspended, and re-started at the new desired frequency. This approach may cause large current fluctuations between operating frequencies which results in a need to utilize a more robust power supply. It may also result in halting the operation of the processor being driven by the PLL output for many cycles during the re-programming and re-starting phases of operation.
PLLs contain oscillators whose frequency may be voltage controlled or current controlled. Oscillators are designed to operate within a designed operating frequency range. For example, one oscillator may be designed to operate between 400 Mhz and 800 Mhz while another oscillator may be designed to operate between 800 Mhz and 1200 Mhz. A performance tradeoff exists if one were to design an oscillator to operate in the range between 400 Mhz and 1200 Mhz. The width of an operating range for an oscillator is directly proportional to its negative jitter characteristics. Therefore, the larger the operating range for a particular oscillator, the larger its corresponding jitter characteristics. Therefore there is a need to generate varying clock frequencies over a broad range of frequencies having low jitter characteristics.
USPTO Backgrounds
USPTO Backgrounds