1. Field of the Invention
The invention relates to dynamic random access memory (DRAM) devices, and more particularly, to a method for fabricating a DRAM cell having a high capacitance charge storage capacitor, for reliable data storage thereon.
2. Description of Related Art
The dynamic random access memory (DRAM) is a widely used volatile read-write semiconductor memory device. As shown in FIG. 1, the equivalent circuit of a DRAM cell includes a metal-oxide semiconductor field-effect transistor (MOSFET) 10 having its gate connected to a word line WL and one end of its source/drain region connected to a bit line BL and the other end coupled via a capacitor 12 to ground. The MOSFET 10 is a bi-directional switch in which the source and drain are interchanged in roles for read and write operations.
As is well known to those skilled in the art of semiconductor devices, the capacitor 12 is used to store an amount of electric charge representative of binary data. By principle, the larger the capacitance value of the capacitor 12, the more reliable is the data stored on the capacitor 12.
Previously developed DRAM cells have a drawback that the capacitor has low capacitance. This drawback is depicted in FIG. 2 which shows a schematic cross-sectional view of the structure of a conventional DRAM cell which includes a silicon substrate 20, a field oxide layer 21, a gate oxide layer 22, a first polysilicon layer 23, a gate oxide layer spacer 24, and a source/drain region 25. These elements form the MOSFET part of the DRAM cell. The DRAM cell also includes a SiO.sub.2 layer 26 having a contact opening formed above the source/drain region 25. A second polysilicon layer 27 is formed over the contact opening and a dielectric layer 28 based on an NO (nitride/oxide) structure or an ONO (oxide/nitride/oxide) structure is formed over the exposed surface of the second polysilicon layer 27. Further, a third polysilicon layer 29 is formed over the dielectric layer 28. The second polysilicon layer 27, the dielectric layer 28, and the third polysilicon layer 29 constitute the capacitor part of the DRAM cell.
It is a well known principle that the capacitance of a capacitor is proportional to the area of the conducting elements thereof. Accordingly, the capacitance of the capacitor in the DRAM cell is proportional to the area of the second polysilicon layer 27 and the third polysilicon layer 29. As semiconductor technology advances, the feature size of the DRAM cell is continually being reduced for a higher level of integration. A higher level of integration, however, requires a proportional reduction in the area of the conducting elements of the capacitor in the DRAM cell, thus resulting in less capacitance. The reliability of the data stored on the capacitor in the DRAM cell is therefore reduced.
USPTO Backgrounds
USPTO Backgrounds