Technologies referred to as “smart cut” and “wafer-bonding” have been utilized to bond monocrystalline silicon materials onto semiconductor substrates. Smart cut technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized to crack the substrate, and wafer bonding technology generally refers to a process in which a first semiconductive substrate is bonded to a second semiconductor substrate.
In particular applications of smart cut and wafer-bonding technology, hydrogen ions (which can be, for example, H+, H2+, D+, D2+) are implanted into a first monocrystalline silicon substrate to a desired depth. The first monocrystalline silicon substrate comprises a silicon dioxide surface, and is bonded to a second monocrystalline substrate through the silicon dioxide surface. Subsequently, the bonded first substrate is subjected to a thermal treatment, which causes cleavage along the hydrogen ion implant region to split the first substrate at a pre-defined location. The portion of the first substrate remaining bonded to the second substrate can then be utilized as a silicon-on-insulator (“SOT”) substrate. An example of a process is described in U.S. Pat. No. 5,953,622, hereby incorporated by reference. The SOT substrate is subsequently annealed at a temperature of greater than or equal to 900° C. to strengthen chemical coupling within the second substrate.
While silicon-on-insulator (SOT) structures offer a solution to some problems with semiconductor processing, SOT structures introduce a floating body effect. The floating body effect occurs when the body of a FET floats toward Vdd and the threshold voltage reduces. A reduction in the threshold voltage increases the sensitivity of the FET to noise in its input.
Silicon-on-insulator structures further introduce the drawback of kinks. A discussion of “kink” effect is found in “Analysis of kink characteristics in silicon-on-insulator MOSFET's using two-carrier modeling”, IEEE JSSC, vol. SC-20, no. 1, February 1985, pgs. 378-382, by Koichi Kato, Tetsunori Wada, and Kenji Taniguchi, hereby incorporated by reference.
USPTO Backgrounds
USPTO Backgrounds