The present invention relates generally to methods for electroplating copper in damascene integrated circuit trenches to form conductive metal inter-connections between selected semiconductor devices on the integrated circuit.
The damascene process is becoming important for interconnections in integrated circuit design. Currently, electroplating is applied for copper (Cu) trench- fill followed by chemical mechanical polishing (CMP) for planarization.
xe2x80x9cSuppressingxe2x80x9d and xe2x80x9cbrighteningxe2x80x9d agents are two types of organic additives commonly used in electroplating along with chloride. Suppressors, also known as xe2x80x9ccarriersxe2x80x9d or xe2x80x9clevelersxe2x80x9d depending on specific functionality, are macromolecule deposition inhibitors that tend to adsorb over the wafer or substrate and reduce local deposition rates, while brighteners are organic molecules that tend to improve the specularity, or surface smoothness, of the deposit by reducing both surface roughness and grain-size variation. Brighteners interact with suppressors and compete for surface adsorption sites and locally accelerating deposition rates. For acid copper electroplating, most commercial electroplating mixtures use three organic components, i.e. brighteners, suppressors that comprise levelers and carriers, and chloride ions, which adsorb at the cathode during plating.
The general chemical characteristics of brighteners are water-soluble salts of organic acids containing a mercapto or thiol functional group. A typical example would be:
xe2x80x83Hxe2x80x94Sxe2x80x94Cxe2x80x94Cxe2x80x94Cxe2x80x94SO3
present at 1 to 10 ppm concentration. Brighteners adsorb strongly on Cu metal during plating and participate in the charge transfer reaction. They determine Cu growth characteristics with major impact on ductility, smoothness, and hardness. Brighteners are the least stable of all additive components and are subject to oxidation by air (oxygen), electrochemical oxidation at the anode, and catalytic decomposition at the Cu surface. By-products of brighteners are often detrimental to deposit properties and control of brighteners during electroplating is relatively important and is the subject of most acid-Cu additive control.
The general chemical characteristics of levelers are a high molecular weight monomer or polymer with both sulfonic acid and nitrogen containing functional groups and are usually present at 10 to 100 ppm concentrations. The nitrogen containing groups are protonated in acid solution and adsorb strongly on Cu to inhibit plating. The exact chemical composition varies by supplier and application requirements. Levelers reduce Cu growth at edges and protrusions to yield a smoother final surface. They increase polarization resistance at high growth areas by either: inhibiting growth proportional to mass transfer at localized sites; or adsorbing more selectively at more cathodic (fast growing) sites. Levelers are relatively stable compared to brighteners.
The general chemical characteristics of carriers are oxygen-containing polymers containing no sulfur or nitrogen groups. Typical examples are polyethylene glycol or polyoxyethylene glycol of from 3000 to 8000 molecular weight. Carriers adsorb during Cu plating to form a relatively thick monolayer film at the cathode and moderately polarize Cu deposition by preventing diffusion of Cu2+ ions to the surface. A carrier alone, or with Clxe2x88x92, yields good thickness distributions but poor fill and deposit properties. Carrier effect on plating is stable over a wide range of concentrations, from 10 to 1,000 ppm, and molecular weights from 800-1,000. Carriers are gradually broken into lower molecular weight fragments at both the anode and the cathode and tend to lose polarization effectiveness below a molecular weight of 750.
Chloride, as HCl, is an additive for nearly all commercial additive electroplating systems and is present at bath concentrations of 30 to 100 ppm. It adsorbs at both the cathode and anode and modifies adsorption properties of the carrier to influence thickness distribution. It accumulates in anode film and increases anode dissolution kinetics. Chloride does not decompose or complex irreversibly with other bath components and the bath chloride concentrations may shift inversely with the anode film chloride level.
For ultralarge-scale integration (ULSI) interconnect applications, the composition and concentrations of brighteners and suppressors are selected such that brightener surface concentration dominates on the interior surfaces of trenches and vias. Local deposition rates are thus suppressed at the top of topographical features relative to the insides, leading to the desired xe2x80x9cbottom-upxe2x80x9d deposition and void-free metal filing of the trenches and vias. In order to have sufficient Cu to cover the step height and to improve planarity before CMP, the thickness of the Cu layer has to be increased. However, increased thickness of the Cu layer leads to poor uniformity and lower CMP throughput.
U.S. Pat. No. 4,169,018 to Berden et al. describes a one step copper electroplating process for use on a carrier material, such as aluminum, and which yields a uniform, virtually pore-free copper ultra-thin foil with a nodularized surface for strong adherence to an epoxy resin impregnated fiber glass circuit board. The plating process comprises an acidic plating bath containing copper, nitrate, and fluoride ions which can be operated at a single-current density. The nitrate ion promotes nodularizing of the outer surface of the Cu foil while the fluoride ions increase Cu nucleation.
U.S. Pat. No. 5,821,168 to Jain describes a process for forming a semiconductor device in which an insulating layer is nitrided and then covered by a thin adhesion layer before depositing a composite copper layer. This process eliminates the need for a separate diffusion barrier since a portion of the insulating layer is converted to form a diffusion barrier film and the adhesion layer reacts with the interconnect material resulting in strong adhesion between the composite copper layer and the diffusion barrier film formed on the insulating layer. After a copper seed layer is deposited by physical vapor deposition over the adhesion layer using a collimated sputtering chamber, the substrate is taken to an electroplating system where 6,000-15,000 xc3x85 of copper is plated over the copper seed layer forming a composite copper layer with the copper seed layer indistinguishable from the plated copper layer. CMP then removes the composite copper layer overlying the uppermost surface of the insulating layer.
U.S. Pat. No. 5,055,425 to Leibovitz et al. describes a method for the formation of solid vias, preferably made of electroplated copper, which can be stacked, and shows a multi-layer copper and chromium metal line and interconnect structure.
U.S. Pat. No. 5,071,518 to Pan describes a method to fabricate an electrical multilayer interconnect having high density electrically conductive lines in a multilayer interconnect system in which the conductive lines can be protected by a protective coating. Copper may be used as the metal pillar and is plated by, for example, electroplating and electroless deposition.
U.S. Pat. No. 5,801,100 to Lee et al. describes an electroless copper plating method for forming integrated circuit structures within an integrated circuit. Interdiffusion of patterned copper containing conductor layers is avoided by employing patterned nickel containing conductor layers as barrier layers separating the patterned copper containing conductor layers from integrated circuit layers adjoining the copper containing integrated circuit inductor structure.
Accordingly, it is an object of the present invention to form a copper interconnect in an integrated circuit structure using a multiple step copper electroplating process.
Another object of the present invention is to form a copper interconnect in an integrated circuit structure using a multiple step copper electroplating process that reduces the thickness of the copper layer, shortening CMP times.
A further object of the present invention is to form a copper interconnect in an integrated circuit structure using a multiple step copper electroplating process that reduces the thickness of the copper layer, improving uniformity.
Yet another object of the present invention is to form a copper interconnect in an integrated circuit structure using a multiple step copper electroplating process that improves the planarity of the electroplated copper by reducing dishing and erosion.
Other objects and advantages of the present invention will become apparent from the following detailed description thereof, which includes the best mode contemplated for practicing the invention.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a semiconductor structure having a trench formed therein is provided. The semiconductor structure may be a substrate with an overlying interlevel metal dielectric layer having the trench. A first copper containing layer having an upper surface and a predetermined thickness is electrolytically deposited within the trench in an electrolytic bath having a composition and concentrations of brighteners and suppressors selected such that brightener surface concentration dominates on the interior surfaces of trench to enable a xe2x80x9cbottom-upxe2x80x9d trench filing Cu deposition. Then a second copper containing layer having an upper surface and a predetermined thickness is electrolytically deposited over the first copper containing layer in an electrolytic bath having an increased concentration of leveler than in the first electrolytic bath, wherein the second copper containing layer upper surface has a greater planarity than the first copper containing layer upper surface. The structure is then planarized by CMP achieving a greater CMP throughput due to the more planarized second copper containing layer.
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