1. Field of the Invention
The present invention relates to a semiconductor storage device and particularly it relates to a semiconductor storage device adapted to execute a program using a program voltage.
2. Description of Related Arts
A conventional semiconductor storage device comprises a memory cell array and a peripheral circuit. Said peripheral circuit comprises an internal boosted power source generating circuit which, when receiving an external power source voltage Vcc, delivers an internal boosted power source voltage Vpp for transferring "H" data to memory cells, and an internal reset circuit which delivers an internal reset signal ZPOR for starting said internal boosted power source generating circuit.
A conventional semiconductor storage device will now be described with reference to the drawings.
FIG. 8 is a block diagram showing an example of the arrangement of said internal boosted power source generating circuit.
In FIG. 8, the internal boosted power source generating circuit comprises an internal boosted power source voltage Vpp generating circuit 201, an internal boosted power source voltage Vpp supplementing circuit 203, and a clamp 205. The Vpp generating circuit 201 comprises a ring oscillator 207 and a pump 209. The Vpp supplementing circuit 203 comprises a level detector 211, a ring oscillator 213 and a pump 215.
The Vpp generating circuit 201 is connected to an external power source and generates the internal boosted power source voltage Vpp on the basis of the external power source voltage Vcc. The ring oscillator 207 in the Vpp generating section 201 produces and delivers a pulse signal having an amplitude .vertline.GND-Vcc.vertline. from the external power source voltage Vcc. The pump 209 is connected to the ring oscillator 207 and is actuated by a pulse signal from the ring oscillator 207 to generate the internal boosted power source voltage Vpp. The Vpp supplementing circuit 203 is connected to the Vpp generating circuit 201 and generates a voltage which supplements the internal boosted power source voltage Vpp when the latter is at lower level. The level detector 211 in the Vpp supplementing circuit 203 is designed such that when the level of the internal boost source voltage Vpp is lower than a target value, it detects said level and delivers a signal (operating signal) to actuate the ring oscillator 213. The ring oscillator 213 is connected to the level detector 211, and upon receiving an operating signal from the level detector 211, it produces and delivers a pulse signal. The pump 215 is connected to the ring oscillator 213 and is adapted to be actuated by a pulse signal from the ring oscillator 213 to deliver a voltage for supplementing the internal boosted power source voltage Vpp. The clamp 205 is connected to the Vpp generating circuit 201 and to the Vpp supplementing circuit 203 such that if the level of the internal boosted power source voltage Vpp delivered from either the Vpp generating circuit 201 or the Vpp supplementing circuit 203 is higher than a target value, it detects said voltage and delivers the internal boosted power source voltage Vpp after it has controlled the latter to a suitable value.
FIG. 9 is a view showing the internal arrangement of the pumps 209 and 215 shown in FIG. 8.
In FIG. 9, each pump comprises NMOS transistors 301, 311, 313 and 319, a clamp 303, inverters 305 and 307, and capacitors 309, 315 and 317.
Terminal p, q, r and s are connected to an external power source to have an external power source voltage Vcc applied thereto. The NMOS transistor 301 of diode junction sets an initial value for the boosted power source voltage Vpp. The clamp 303 has a plurality (3, in FIG. 9) of NMOS transistors of diode junction and is designed such that when the level of the internal boosted power source voltage Vpp rises too high, it detects said level to control the latter to a suitable value.
The inverter 305 is connected at its terminal u to the ring oscillator 207 or 213 of FIG. 8 and adapted to deliver a pulse signal having an amplitude .vertline.GND-Vcc.vertline.. The inverter 307 is connected to the inverter 305 and adapted to deliver an inverted pulse signal having an amplitude .vertline.GND-Vcc.vertline..
The capacitor 309 is connected to the NMOS transistor 301 and to the inverter 305 and is designed such that when a voltage is periodically applied to one electrode thereof associated with the inverter 305, a voltage is applied to the other electrode from the NMOS transistor 301, whereby the capacitor is charged. The NMOS transistors 311 and 313 have their drains connected to the external power source and their gates connected to the capacitor 309; thus, when the capacitor 309 is charged until the electrode voltage exceeds the threshold voltage of the NMOS transistors 311 and 313, whereupon they are turned on, feeding the voltage from the power source.
The capacitor 315 is connected to the inverter 307 and the drain of the NMOS transistor 311, while the capacitor 317 is connected to the inverter 307 and the NMOS transistor 313. When a voltage is applied, with a period inverted with respect to the capacitor 309, to the electrode associated with the inverter 307, a voltage is applied to the other electrode from the associated NMOS transistor 315 or 317, whereby the capacitor is charged.
The NMOS transistor 319 has its source connected to the drain of the NMOS transistor 311 and to the capacitor 315 and its gate connected to the drain of the NMOS transistor 313 and to the capacitor 317. When this NMOS transistor 319 is turned on, the voltages obtained by charging the capacitors 315 and 317 and the voltages obtained by turning on the NMOS transistors 311 and 313 are added. As a result, a voltage can be obtained which is higher than the power source voltage Vcc necessary for generating the target value Vpp of the internal boosted power source voltage. And the internal boosted power source voltage Vpp thus obtained is delivered from the terminal w connected to the drain of the NMOS transistor 319 and thus delivered from the Vpp generating circuit 201 of FIG. 8.
FIG. 10 is a timing chart showing how the internal boosted power source voltage Vpp is boosted when the power is turned on in a conventional semiconductor storage device.
In the conventional semiconductor storage device, when the external power source is off (time t; to&lt;t&lt;t.sub.1), the external power source voltage Vcc, the internal boosted power source voltage Vpp and the internal reset signal ZPOR are all at the ground voltage GND. When the power is turned on (t.sub.1 &lt;t&lt;t.sub.7), the internal reset signal maintains the ground voltage GND level for a given time, resetting the circuits in the device. When the internal reset signal ZPOR turns to "H" level, the reset time is up and the internal boosted power source generating circuit is started (t.sub.7) elevate the internal boosted power source voltage Vpp from the ground voltage GND to an intended boosted level (t.sub.7 &lt;t&lt;t.sub.11).
In the prior art, however, since the internal boosted power source voltage Vpp rises only after the external power source voltage Vcc has risen when the external power source is turned on, it takes time for the internal boosted power source voltage to reach the intended boosted level. In the semiconductor storage device comprising the internal boosted power source generating circuit and the internal reset circuit as described above, if a substantial time has to elapse before an intended boosted level can be reached after the rise of the internal boosted power source voltage Vpp, then the following problems arise.
(1) The specification telling that the internal boosted power source voltage Vpp will rise in a given time cannot be ensured;
(2) There are adverse effects including latch-up sometimes taking place in a semiconductor;
Latch-up mentioned in (2) will now be described with reference to the drawings.
FIG. 11 shows an example of the peripheral circuit of a semiconductor storage device, said circuit being liable to cause latch-up when the rise of the internal boosted power source voltage is slow. This circuit is used to elevate the potential at the node c from the ground voltage GND to the same voltage as the internal boosted power source voltage Vpp.
In FIG. 11, this circuit comprises PMOS transistors 401, 402 and 403 and NMOS transistors 404, 405 and 406. The terminals k and z connected to the respective sources of the PMOS transistors 401 and 402 and the terminal n connected to the gate of the PMOS transistor 403 are connected to the internal boosted power source, and the terminal m connected to the source of the PMOS transistor 403 is connected to the external power source. The internal boosted power source voltage Vpp is supplied from the node A and the external power source voltage Vcc is supplied from the node B.
One cycle of operation will now be described with reference to a timing chart shown in FIG. 12. However, suppose that the timing chart is an ideal one in which the external power source voltage Vcc and the internal boosted power source voltage Vpp have already risen to a final value and an intended boosted level, respectively.
The nodes A and B are supplied with the ground voltage END and the external power source voltage Vcc (A; t.sub.100 &lt;F t&lt;F t.sub.103, B; t.sub.100 &lt;F t&lt;F t.sub.101). When the supply of the external power source voltage Vcc from the node B is stopped (t.sub.101), the PMOS transistor 403 is turned on to supply the node C with a voltage (Vcc-Vpp). When the internal boosted power source voltage Vpp is supplied from the node A (t.sub.103), the NMOS transistor 404 and the PMOS transistor 402 are turned on to supply the node C with the internal boosted power source voltage Vpp (t.sub.104), and the voltage at the node C becomes equal to the internal boosted power source voltage Vpp (t.sub.105).
Again, the node B is supplied with the external power source voltage Vcc (t.sub.106), and when the node A starts to be supplied with the ground voltage GND (t.sub.107), the voltage at the node C lowers to the ground voltage GND (t.sub.108).
FIG. 13 is a view showing the construction of the PMOS transistor 403 in FIG. 11. Latch-up will now be described using this FIG. 13.
In FIG. 13, the PMOS transistor 403 comprises an n-well 503 formed in a p-type substrate 501, a source 505 in p+ layer form formed in said n-well 503, a drain 507 in p+ layer form, and a gate electrode 509. The terminals m and n correspond to the terminals m and n in FIG. 11.
The gate 509 is connected to the node B. The internal boosted power source voltage Vpp is applied to the n-well 503. The external power source voltage Vcc is fed in from the source 505 and delivered from the drain 507 to the node C.
Here, it is to be noted that while the external power source voltage Vcc rises at a stroke, if the internal boosted power source voltage Vpp takes time to rise, then a forward bias (p.fwdarw.n) is applied longitudinally from the source 505 to the n-well 503, causing latch-up to take place, damaging the device.
USPTO Backgrounds
USPTO Backgrounds