1Field of the Invention
The present invention relates to the field of semiconductor devices and more particularly to a nonplanar tri-gate transistor having a thinned lower body portion and method of fabrication.
2Discussion of Related Art
In order to increase the performance of modern integrated circuits, such as microprocessors, silicon on insulator (SOI) transistors have been proposed. Silicon on insulator (SOI) transistors have an advantage in that they can be operated in a fully depleted manner. Fully depleted transistors have an advantage of ideal subthreshold gradients for optimized ON current/OFF current ratios.
An example of a proposed SOI transistor which can be operated in a fully depleted manner is a tri-gate transistor 100, such as illustrated in FIG. 1. Tri-gate transistor 100 includes a silicon body 104 formed on an insulating substrate 102 having a buried oxide layer 103 formed on a monocrystalline silicon substrate 105. A gate dielectric layer 106 is formed on the top and sidewalls of the silicon body 104 as shown in FIG. 1. A gate electrode 108 is formed on the gate dielectric layer and surrounds the body 104 on three sides, essentially providing a transistor 100 having three gate electrodes (G1, G2, G3), one on each of the sidewalls of the silicon body 104 and one on the top surface of the silicon body 104. A source region 110 and a drain region 112 are formed in the silicon body 104 on opposite sides of the gate electrode 108 as shown in FIG. 1.
An advantage of the tri-gate transistor 100 is that it exhibits good short channel effects (SCE). One reason tri-gate transistor 100 achieves good short channel effects is that the nonplanarity of the device places the gate electrode 108 in such a way as to surround the active channel region. That is, in the tri-gate device, the gate electrode 108 is in contact with three sides of the channel region. Unfortunately, the fourth side, the bottom part of the channel is isolated from the gate electrode by the buried oxide layer 103 and thus is not under close gate control.
USPTO Backgrounds
USPTO Backgrounds