1. Field of the Invention
The invention relates to the field of electronics, more particularly to the wire bonds incorporated into an integrated circuit package.
2. Description of the Related Prior Art
As will be understood by those skilled in the art, an integrated circuit (IC), sometimes called a chip or microchip is a semiconductor material on which thousands of tiny resistors, capacitors, and transistors are fabricated in a particular configuration to perform a desired electronic function. For example, a chip can function as an amplifier, oscillator, timer, counter, computer memory or microprocessor. A particular chip is categorized as either digital or analogue, depending on its intended application.
In the manufacture of a chip a semiconductor wafer (typically 300 mm diameter for silicon) is doped to enhance its electron transfer properties and then etched to provide the desired circuitry. The resulting wafer is diced using scribing tools into dies or chips. The end product is delicate in nature so is incorporated into some form of packaging. Lower quality packages are plastic while higher quality packages are ceramic. The packaging serves a variety of functions, including: (a) physical protection of the chip; (b) the provision of electrical connectivity from the chip to the printed circuit board to which it is mounted; (c) dissipation of heat generated by the chip. Additionally, the electrical characteristics of the package itself are designed to minimally impact device performance.
Several well known packaging techniques have been developed, with two of the most popular being quad flat pack (QFP) and ball grid array (BGA). As shown in FIG. 1, a QFP package comprises a chip 10, which is protected using an epoxy resin 12. From the chip 10 extend wire bonds 14 (typically gold (Au)) which connect to leads 16 (typically lead/tin (Pb/Sn) plated) which may have silver spot plating at the contact point, as shown at 18. The leads 16 are connected (soldered) to a printed circuit board (not shown). An adhesive or solder 20 is used to adhere the chip to the carrier pad 22. FIG. 2 depicts a standard BGA package which comprises a chip 24, which is protected by an epoxy resin 26. From the chip 24 extend wire bonds 28 which connect to contacts 30 which extend through substrate or carrier pad 32 to electrical pads 34. The electrical pads 34 are connected to electrical pads 36 associated with printed circuit board 38, by way of solder balls 40. During manufacture, solder balls 40 are heated to provide a continuous electrical circuit between the chip 24 and printed circuit board 38. The chip 24 may be secured to the carrier pad 32 by means of a dielectric adhesive layer 42. FIG. 3 highlights the arrangement of the bottom of carrier pad 32 which consists of rows of electrical pads 34 extending around the perimeter. The “pitch” or distance between electrical contacts on chip 24, is typically smaller than the pitch between corresponding electrical pads 36 associated with printed circuit board 38. The integrated circuit package provides “tracks” to connect the small chip 24 pitch to the large printed circuit board 38 pitch.
As will also be appreciated, flip-chip assembly is an alternate packaging technique which can be used in a BGA-type assembly. As shown in FIG. 4, in this technique the chip 44 is actually flipped over to allow direct interconnections between the chip 44 and carrier pad 46 by way of solder balls 48. Electrical tracks (not shown) extending through carrier pad 46 to electrical pads 50 allow interconnection to printed circuit board 52 using a second series of solder balls 54. As can be seen in the figure, there are no wire bonds required. Although greater I/O density can be achieved using this packaging technique, problems such as controlling heat dissipation are prevalent making this technique unsuitable for some applications.
As highlighted above, the connection between the chip and the integrated circuit package can be achieved with flip-chip mounting inside the package (which is similar to the BGA between the package and the printed circuit board) or with wire bonds inside the package. Wire bonds are very short ribbons of wire, that are pressure welded from the chip pads to the package pads by machine. As will be appreciated by those in the art, a problem with wire bonds for high frequency circuits is that they also generate a small amount of inductance (e.g. 1 nanoHenry/millimetre of length). As those skilled in the art are aware, inductance is the characteristic of an electrical conductor which opposes a change in current flow. In the case of a wire bond, the inductance is often unpredictable because, typically, the exact length of the wire is inconsistent, as well as its location and termination point on either the chip or carrier pad. Both of these factors (and to some extent the thickness of the wire) affect its inherent inductance. The inconsistencies are largely a result of imprecise manufacturing techniques. As a result, this heretofore undesirable property of wire bonds has presented problems to integrated circuit designers who have tried to design around the inductance produced by wire bonds.
Where an inductor is required in one of the chip's operational circuits, it has heretofore been incorporated into the chip design itself (e.g. as a spiral inductor) and located on the chip (“on-die”) or in the package or printed circuit board (“off-die”). In either case, recognized problems are created for the circuit designer.
In light of the problems and deficiencies of wire bonds highlighted above, there is a need for an improved integrated circuit package in which the wire bond inductance is advantageously used to facilitate operation of the chip.
USPTO Backgrounds
USPTO Backgrounds