The present invention relates generally to memory devices, and more particularly to cache memories.
A cache memory is a random access memory that buffers data from a main memory. A cache memory is typically employed to provide high bandwidth memory accessing to a processor. Power is becoming a critical component in modern microprocessor design because of battery life. An increasing portion of a processor's real estate is dedicated to large caches, thereby increasing cache capacity. However, leakage currents in large data arrays increase power consumption and push power envelopes.
Certain caches are referred to as sequential caches, as data within the cache is sequentially stored and accessed in a predetermined manner. For example, a first portion of data is stored in a first set of the cache, the next data portion is stored in the next set of the cache, and so forth. Types of sequential caches include an instruction cache and a trace cache, which is used to store and deliver instruction traces to a microprocessor. Instruction traces include decoded microoperations or μops, thus improving bandwidth and latency to a processor execution stage.
An instruction trace is stored in the order in which it is executed, rather than in a static order defined by a program. These traces include a head, body, and tail. A traceline includes one or more (depending on line-ending conditions) sequentially executed μops and a trace is formed from one or more tracelines in sequential sets. Trace-ending conditions may include calls, returns, backwards branches, and the like. A trace is originally fetched and decoded during a “build-mode”. Subsequent accesses to the trace are referred to as “stream-mode”.
Storing an instruction trace in a decoded format in a trace cache can reduce power consumption, as decoding power is only used while building the trace. However, power consumption still occurs during operation of the trace cache or other sequential cache.
A need thus exists for improved caching mechanisms and reducing power consumption within a cache.
USPTO Backgrounds
USPTO Backgrounds