1. Field of the Invention
This invention relates to the formation of low dielectric constant (low k) dielectric material for integrated circuit structures. More particularly, this invention relates to the formation of a composite layer of low dielectric material for integrated circuit structures comprising upper and lower conformal barrier layers of low k dielectric material with a low k center layer of carbon-doped dielectric material having good gap filling capabilities.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH3xe2x80x94SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which i annealed at 400xc2x0 C. to remove moisture. The article goes on to state that beyond methyl silane, studies show a possible k of 2.75 using dimethyl silane in the Trikon process. The Peters article further states that in high density plasma CVD (HDP-CVD), dielectric material formed from methyl silane or dimethyl silane and O2 can provide a k as low as 2.75.
The use of this type of low k carbon-doped silicon oxide dielectric material has been found to have good gap filling characteristics, resulting in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k carbon-doped silicon oxide dielectric materials for conventional silicon oxide insulation has not been without its own problems. Formation of the low k carbon doped silicon oxide dielectric material by the Trikon process is much slower than the conventional formation of undoped silicon oxide dielectric material. For example, in the time it takes to form a layer of low k carbon-doped silicon oxide dielectric material by the Trikon process on a single wafer, it may be possible to deposit a conventional silicon oxide dielectric layer of the same thickness on as many as 5 wafers.
However, even more importantly, it has been found that the subsequent formation of vias, or contact openings, through such low k carbon-doped silicon oxide dielectric material to the underlying conductive portions such as metal lines, or contacts on an active device, can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces.
For example, contact openings or vias are usually etched in the low k carbon-doped silicon oxide dielectric layer through a photoresist mask. When the photoresist mask used to form the vias is subsequently removed by an ashing process, damage can occur to the newly formed via surfaces of the low k carbon-doped silicon oxide dielectric material resulting in such via poisoning. Apparently the presence of carbon in the low k carbon-doped silicon oxide dielectric material formed by the Trikon process increases the porosity of the low k carbon-doped dielectric material, thus rendering the material more susceptible to damage during subsequent processing of the structure.
It has also been proposed to deposit low k silicon oxide dielectric material by other processes such as by plasma enhanced chemical vapor deposition (PECVD), using CH4 and/or C4F8 and/or silicon tetrafluoride (SiF4) with a mixture of silane, O2, and argon gases. Plasma enhanced chemical vapor deposition (PECVD) is described more fully by Wolf and Tauber in xe2x80x9cSilicon Processing for the VSLI Eraxe2x80x9d, Volume 1-Process Technology (1986), at pages 171-174 .
While the formation of a low k silicon oxide dielectric material by PECVD is much faster than the formation of the same thickness low k carbon-doped silicon oxide dielectric layer by the Trikon (i.e., at rates approaching the deposition rate of conventional silicon oxide), low k silicon oxide dielectric material deposited by PECVD has poor gap filling characteristics in high aspect ratio regions, resulting in the formation of voids in the dielectric materials deposited by PECVD in the spaces between the closely spaced apart metal lines in such structures.
Therefore, the formation of low k carbon-doped silicon oxide dielectric material is the preferred material for use as electrical insulation between horizontally spaced apart metal lines, and between layers of metal lines to provide low capacitance between such metal lines or other conductive portions of the integrated circuit structure. However, the previously discussed susceptibility of the low k silicon-doped silicon oxide dielectric material to subsequent damage, such as during the removal of photoresist masks after formation of a via pattern in the low k material, or reaction to oxide layers or metal lines beneath the low k dielectric materials, has resulted in the use of barrier layers of dielectric material formed above and below the low k layer of dielectric material to respectively protect the upper and low surfaces of the low k silicon doped silicon oxide dielectric material.
Such barrier layers, while successfully fulfilling their function of protecting the layer of low k carbon-doped silicon oxide dielectric material, are formed of conventional dielectric material such as conventional silicon oxide. The presence of such conventional high dielectric constant material, therefore, detracts from the goal of separating the metal lines from one another, both vertically and horizontally, by electrical insulation comprising low k dielectric material to reduce the capacitance between the metal lines.
To avoid the deleterious effects of using such barrier layers of high k dielectric material, the barrier layers have been formed as thin as possible, ranging in thickness from a minimum thickness of about 50 nanometers (nm) which is sufficient to provide the desired minimum barrier up to a maximum thickness of about 500 nm. The use of thicknesses greater than the minimum needed to protect the low k carbon-doped silicon oxide dielectric material during further processing or reaction with underlying oxide layers and metal lines can have an adverse effect on the overall capacitance of the structure, since the barrier layers are not formed of low k dielectric material.
While such use of very thin barrier layers of conventional (non-low k) dielectric material does protect the upper and low surf-aces of the layer of low k carbon-doped silicon oxide dielectric material while minimizing the contribution to high capacitance, another problem has arisen which the provision of a thin barrier layer does not address. In the prior art, the formation of very thin (narrow) metal lines, and the elimination of xe2x80x9cdog bonexe2x80x9d or enlarged contact regions on such lines for vias to intersect from another layer of metal lines can result in misalignment between the via opening and the underlying metal line, as shown in prior art FIG. 1.
Prior art FIG. 1 shows a fragment 2 of an integrated circuit structure having formed thereon raised metal lines 4a and 4b. Over metal lines 4a and 4b is formed a thin conformal barrier layer 6 of conventional (non-low k) dielectric material such as conventional silicon oxide having a thickness of 500 nm or less. A main dielectric layer 10 of low k carbon-doped silicon oxide dielectric material is then formed over barrier layer 6. Low k main dielectric layer 10 of low k carbon-doped silicon oxide dielectric material, as shown in FIG. 1, has good gap filling characteristics, resulting in a void free filling of the space between metal lines 4a and 4b. An upper barrier layer 20, which also comprises conventional (non-low k) dielectric material, such as conventional silicon oxide, is then formed over low k main dielectric layer 10 to protect the upper surface of low k carbon-doped silicon oxide main dielectric layer 10.
Still referring to FIG. 1, a via 30a is shown formed through dielectric layers 20, 10, and 6 from an upper metal line (not shown) down to raised metal line 4a, with via 30a shown formed in alignment with metal line 4a. However, such a via is not always etched through dielectric layers 20, 10, and 6 in perfect alignment with the underling metal line. Instead, what may happen, is the misalignment shown with respect to via 30b and underlying metal line 4b in FIG. 1. When this happens, the via etch, instead of stopping on the top surface of the metal line, extends down the sidewall of the metal line, as shown at 32. Furthermore, since barrier layer 6 on the sidewall of metal line 4a is formed very thin (to avoid excess capacitance through the non-low k barrier dielectric material), the misaligned etch not only etches away the portion of barrier layer 6 on the sidewall of metal line 4a, but also a portion of low k carbon-doped silicon oxide dielectric layer 10 as well. This, in turn, increases the overall exposed surface area of low k carbon-doped silicon oxide dielectric material of layer 10 to the etching materials used to form the via as well as increasing the surface of low k dielectric material which may be damaged during the subsequent ashing process used to remove the photoresist via mask.
Increasing the thickness of barrier layer 6 beneath main low k carbon-doped silicon oxide dielectric layer 10 would also increase the thickness of barrier layer 6 formed on the sidewall of the raised metal lines, thus inhibiting etching of the portion of the low k carbon-doped silicon oxide dielectric material of layer 10 shown etched away at 32 in FIG. 1. However, this has been avoided in the past because of the increase in capacitance which can occur when the volume of non-low k barrier dielectric material of layer 6 is increase at the expense of a decrease in the volume of low k carbon-doped silicon oxide dielectric material of layer 10 separating, for example, metal lines 4a and 4b from one another, as well as other separating them horizontally from other metal lines lying in the same plane, or other metal lines vertically spaced above or beneath metal lines 4a and 4b. 
The formation and use of composite layers of low k dielectric material have been suggested by others. Copending U.S. patent application Ser. No. 09/426,061 entitled xe2x80x9cLOW DIELECTRIC CONSTANT SILICON OXIDE-BASED DIELECTRIC LAYER FOR INTEGRATED CIRCUIT STRUCTURES HAVING IMPROVED COMPATIBILITY WITH VIA FILLER MATERIALS, AND METHOD OF MAKING SAMExe2x80x9d, was filed by two of us with others on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of U.S. patent application Ser. No. 09/426,061 is hereby incorporated by reference. In one embodiment in that application, low k silicon oxide dielectric material having a high carbon doping level is formed in the high aspect regions between closely spaced apart metal lines and then a second layer comprising a low k silicon oxide dielectric material having a lower carbon content is then deposited over the first layer and the metal lines.
Copending U.S. patent application Ser. No. 09/425,552 entitled xe2x80x9cINTEGRATED CIRCUIT STRUCTURE HAVING LOW DIELECTRIC CONSTANT MATERIAL AND HAVING SILICON OXYNITRIDE CAPS OVER CLOSELY SPACED APART METAL LINESxe2x80x9d, was filed by two of us with another on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of U.S. patent application Ser. No. 09/425,552 is hereby incorporated by reference. In one embodiment in that application, low k silicon oxide dielectric material which exhibits void-free deposition properties in high aspect ratio regions between closely spaced apart metal lines is deposited over and between the metal lines and over silicon oxynitride caps on underlying metal lines. After the formation of such void-free low k silicon oxide dielectric material between the closely spaced apart metal lines and the silicon oxynitride caps thereon, the structure is planarized to bring the level of the low k silicon oxide dielectric material down to the level of the tops of the silicon oxynitride caps on the metal lines. A further layer of standard k silicon oxide dielectric material is then formed over the planarized void-free low k silicon oxide dielectric layer and the silicon oxynitride caps. Vias are then formed through the standard k silicon oxide dielectric layer and the silicon oxynitride caps down to the metal lines. Since the vias are not formed through the low k silicon oxide dielectric material, formation of the vias does not contribute to poisoning of the vias. However, the presence of the low k silicon oxide dielectric material between the horizontally closely spaced apart metal lines reduces the horizontal capacitance between such metal lines.
Copending U.S. patent application Ser. No. 09/426,056 entitled xe2x80x9cLOW K DIELECTRIC COMPOSITE LAYER FOR INTEGRATED CIRCUIT STRUCTURE WHICH PROVIDES VOID-FREE LOW K DIELECTRIC MATERIAL BETWEEN METAL LINES WHILE MITIGATING VIA POISONINGxe2x80x9d, was filed by one of us with another on Oct. 22, 1999, and is assigned to the same assignee as this application. The subject matter of U.S. patent application Ser. No. 09/426,056 is also hereby incorporated by reference. In one embodiment in that application, a void-free low k silicon oxide dielectric material is formed in the high aspect regions between closely spaced apart metal lines by one of several processes, including the process used to form the first low k silicon oxide dielectric material described in the previously cited U.S. patent application Ser. No. 09/426,061. A second layer of low k silicon oxide dielectric material is then deposited over the first layer and the metal lines by a process which deposits at a rate higher than the deposition rate of the void-free dielectric material. In a preferred embodiment, both of the layers are formed in the same vacuum chamber without an intervening planarization step.
The invention comprises a composite layer of low k dielectric material for integrated circuit structures comprising a thick lower conformal barrier layer of low k dielectric material, a low k center layer of carbon-doped silicon oxide dielectric material having good gap filling capabilities, and a thick upper conformal barrier layer of low k dielectric material.
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