1. Technical Field
The present invention relates generally to clock generation circuits, and more particularly, to a fail-safe and restartable phase-lock loop (PLL) clock generating circuit.
2. Description of the Related Art
Present day high-speed processors and other logical devices having a high frequency internal clock typically use a phase-lock loop (PLL) to generate the internal clock from lower frequency external clock source or resonant circuit. The frequency of the internal clock is often programmable via parameters generally set up by initialization parameters set by a service processor or by the primary processor under direction of a boot management program, generally stored in non-volatile memory. Many techniques have been developed for detecting PLL clock failure and providing a redundant clock in the presence of such a failure.
However, under certain conditions, and particularly in high-speed processors where the operating clock is close to the upper limit of circuit operability, the parameters setting the internal clock frequency may be such that the selected frequency is too high for either portions of the PLL circuit or circuits interposed between the PLL clock generator and the final clock distribution. From the oscillator output of the PLL to the points at which the output is applied as a processor clock or clock for other logic, level shifters, dividers and buffers are commonly present in large numbers, and failure of any one of the downstream circuits can occur if the clock distribution to those circuits fails. When operating near the upper frequency limit of the above-mentioned circuits, the programmed frequency of the PLL is critical, and if set such that the generated frequency will be too high, attempts to restart the PLL will continuously fail.
It is therefore desirable to provide a method and apparatus for detecting the above failure conditions in a logical system while operating the system in a fail-safe manner and restarting the clock generator such that the failure condition is avoided so that parameters causing the failure condition can be readjusted.
USPTO Backgrounds
USPTO Backgrounds