1. Field of the Invention
This invention relates to the field of integrated circuit testing. More particularly, this invention relates to the testing of the reset function of integrated circuits.
2. Description of the Prior Art
It is important to test integrated circuits for proper operation once they have been manufactured. As integrated circuits increase in complexity, the extent of the tests that need to be performed to properly check a sufficient degree of the functionality of the integrated circuit increase markedly. These problems are compounded with the move towards system-on-chip designs whereby multiple functional units, possibly designed and provided by different sources, are combined upon a single integrated circuit. The number of available input and output pins provided by an integrated circuit package limits the access that may be made to points within the integrated circuit package for testing purposes.
One way of enhancing the ability to test integrated circuits is to use serial test scan chains, such as those proposed in the IEEE JTAG Standard. Serial test scan chains may be used to scan in test vectors to points deep within an integrated circuit, apply those test vectors and collect result values that may then be analysed to confirm correct operation. Whilst the scan chain approach has significant advantages, and is well suited to system-on-chip designs where different portions can be provided with their own serial test scan chains, it suffers from a difficulty in trying to test proper reset operation.
Serial test scan chain techniques scan in data, apply data and capture data in synchronism with a controlling clock signal. This synchronous type of test operation is reasonably well suited to testing what will be synchronous type normal operation. However, a problem exists in trying to test what are normally asynchronous types of operation of the integrated circuit. A highly significant example of such an asynchronous type of operation is the response to an asynchronous reset signal. It is common that circuit portions within an integrated circuit are responsive to an asynchronously applied reset signal to reinitialise their state. Incorrect reset operation is a significant fault in an integrated circuit and it is important that asynchronous reset operation should be properly tested. One way of achieving this is to route out a reset pin for each circuit portion so that this may be used to test the reset operation of that circuit portion. However, as previously mentioned, the number of pins provided by an integrated circuit package is a frequent limiting factor in system design and allocating these valuable input/output pins for manufacturing test operations is undesirable. Furthermore, with the increased use of system-on-chip designs employing multiple circuit portions/macrocells from different sources that may each be subject to their own reset signal, this approach may lead to the need to express multiple external reset pins on the circuit package purely for manufacturing test purposes.
Viewed from one aspect the present invention provides an integrated circuit comprising:
(i) a circuit portion having at least one circuit portion latch operable to store a signal value that is reset to a predetermined reset value upon receipt of a reset signal by said circuit portion; and
(ii) one or more serial test scan chains each having a plurality of scan chain cells, at least one of said serial test scan chain being operable to store and apply test signals to said circuit portion as part of testing for correct operation of said circuit portion, said test signals being applied to said circuit portion under control of a scan enable signal and synchronously with a clock signal; wherein
(iii) said serial test scan chain includes a reset signal generating scan chain cell operable when storing a predetermined reset signal value to generate said reset signal under control of said scan enable signal and independently of and asynchronous with said clock signal.
The invention recognises that whilst the scan enable signal and the clock signal normally act synchronously to apply test signals, the scan enable can be used in conjunction with a modified scan chain cell for generating the reset signal to generate that reset signal at a time asynchronous with the clock signal and thus check the asynchronous reset operation of the circuit portion under test. The system may contain one or more scan chains (typically more, but a small design may have a single scan chain).
Whilst it will be appreciated that the circuit portion for which the reset operation is tested could take many different forms, and could be the whole of the integrated circuit, the invention is particularly useful when the circuit portion under reset test is a macrocell circuit portion. Such macrocell circuit portions often have their own specific reset operation that requires proper testing. The testing of reset operation is particularly valuable when the macrocell is a microprocessor as the microprocessor is a circuit element that may reasonably be expected to require reset operation due to system crashes.
In the context of system-on-chip designs where the invention is particularly valuable, the serial test scan chain may be conveniently provided in the form of a boundary test scan chain surrounding the circuit portion. The circuit portion and its associated boundary test scan chain will often be sourced from a particular provider and accordingly encapsulating the reset test mechanisms within this provided element is highly convenient.
The scan chain cells may contain storage latches that are updated at a fixed point within the cycle of the clock signal. This provides the normal synchronous type of operation of the scan chain testing. In a particularly preferred embodiment of the reset signal generating scan chain cell, the storage latch within that cell is arranged to store a signal whose value is also gated by gate logic controlled by the scan enable signal. Thus, the signal value required to generate a reset signal may be loaded into the reset signal generating scan chain cell, but be prevented from application to the circuit portion until it is released by an appropriate change in the scan enable signal. The scan enable signal can be controlled asynchronously with the clock signal to release the reset signal to the circuit portion in an asynchronous fashion to the clock signal and accordingly provide improved testing of the reset operation.
Viewed from another aspect the present invention provides a method of testing reset operation of an integrated circuit, said integrated circuit having a circuit portion including at least one circuit portion latch operable to store a signal value that is reset to a predetermined reset value upon receipt of a reset signal by said circuit portion, and one or more serial test scan chains each having a plurality of scan chain cells, at least one of said serial test scan chains being operable to store and apply test signals to said circuit portion as part of testing for correct operation of said circuit portion, said test signals being applied to said circuit portion under control of a scan enable signal and synchronously with a clock signal, said method comprising the steps of:
(i) storing a predetermined reset signal value in a reset signal generating scan chain cell within said serial test scan chain; and
(ii) generating said reset signal from said predetermined reset signal value under control of said scan enable signal and independently of and asynchronous with said clock signal.
The above, and other objects, features and advantages of this invention will be apparent from the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds