The present invention relates generally to amplifiers, particularly to input stages for high-voltage operational amplifiers which are subject to high differential voltages, and more particularly to such input stages which utilize low voltage differential input transistors.
The design of conventional differential amplifiers is well known. A typical input stage includes one or more pairs of differentially coupled input JFETs (junction field effect transistors) and associated current sources. For high voltage amplifier design, so-called high voltage transistors, which have high breakdown voltage parameters that are not exceeded during normal circuit operation, are typically used as the input transistors in order to accommodate high input voltages to which the input transistors may be subjected. So-called “low-voltage transistors” have lower breakdown voltage parameters which can be exceeded by internal node voltages in the integrated circuit input stage. For example, in some integrated circuit manufacturing processes, low-voltage N-channel JFETs can be damaged by a relatively low gate-to-source low breakdown voltage of 10 volts. High-voltage transistors usually have higher threshold voltage, higher parasitic capacitances, etc., than low-voltage transistors. The higher threshold voltages, high parasitic capacitances, etc., limit the design flexibility and the amplifier performance parameters such as bandwidth, slew rate, settling time.
Referring to FIG. 1, a conventional input circuit 1 includes input conductors 2 and 3 to which input voltages Vin+ and Vin−, respectively, are applied. Conductor 2 is coupled by input resistor R1 to conductor 5, which is connected to the gate of a low-voltage N-channel JFET J0, the anode of a clamp diode D0, and the cathode of a clamp diode D2. Conductor 3 is coupled by input resistor R0 to conductor 6, which is connected to the gate of a low-voltage N-channel JFET J1, the anode of a clamp diode D3, and the cathode of a clamp diode D1. The sources of input JFETs J0 and J1 are coupled by conductor 4 to a tail current source I1. The drain of input transistor J0 is connected by conductor 7 to the emitter of an NPN cascode transistor Q3. The drain of input transistor J1 is connected by conductor 8 to the emitter of an NPN cascode transistor Q4. The bases of cascode transistors Q3 and Q4 are coupled to a bias voltage. The collector of cascode transistor Q3 is connected by conductor 9 to the base and collector of a PNP current mirror input transistor Q5, the emitter of which is coupled to VDD. The collector of cascode transistor Q4 is connected by an output conductor 10 to the collector of a PNP current mirror output transistor Q6. The base of current mirror output transistor Q6 is connected to the base of transistor Q5 and its emitter is connected to VDD.
By way of definition, is to be understood that a JFET has two current-carrying electrodes, and that each of those two current-carrying electrodes can function interchangeably as either a source or a drain of the JFET, depending on which one is at the highest voltage relative to the other. For example, in an N-channel JFET, the current-carrying electrode which is at the higher voltage is the drain and the other current-carrying electrode is the source of the JFET. For example, if the voltage of a first current-carrying electrode of a N-channel JFET initially functions as its drain but then goes to a voltage which is lower than that of its second current-carrying electrode, then the second current-carrying electrode becomes the drain and the first current-carrying electrode becomes the source.
In input stage 1 of FIG. 1, low voltage input JFETs J0 and J1, rather than high-voltage input transistors, may be used as the input differential transistor pair in order to meet a desired amplifier bandwidth, slew rate, and/or settling time requirement. The low-voltage input JFETs J0 and J1 need to be fully protected against applied high input voltages. A typical input transistor protection circuit includes the back-to-back diode clamps D0, D1, D2, and D3 as shown in FIG. 1 to prevent the gate-to-source and drain-to-source voltages of various transistors from going high enough to reach their respective breakdown voltage levels. (The same approach can be used to prevent base-to-emitter and/or collector-to-emitter voltages of low-voltage NPN or PNP input transistors from going high enough to reach the various transistor breakdown voltage levels.) However, there is a potential problem with the technique shown in FIG. 1 for protecting the input transistors. When the differential input voltage is sufficiently high, under either DC or transient conditions, the various protection diodes D0-3 are turned on so as to clamp or limit the voltage differences between conductors 5 and 6. As a result, the diode current flows thought the input conductors 2 and 3 of input stage 1. This diode current is usually large (e.g., a milliampere or more, depending on the diode size and the size of input current limiting resistors R1 and R0), and is not acceptable in certain applications.
Various circuits are known for boosting the slew rate of an amplifier, including commonly owned U.S. Pat. No. 6,359,572 entitled “Slew Rate Boost Circuitry and Method”, issued on Mar. 19, 2002 to Ivanov et al. , and commonly owned U.S. Pat. No. 6,437,645 entitled “Slew Rate Boost Circuitry and Method”, issued on Aug. 20, 2002 to Ivanov et al.
Thus, there is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used.
There also is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and which also has approximately the same performance as if high-voltage input transistors are used instead of low-voltage input transistors.
There also is an unmet need for a high-voltage amplifier input stage and method which utilizes low-voltage input transistors and does not require use of clamp diodes to prevent damage to the low-voltage input transistors when high magnitude differential input voltages are applied between inputs of the input stage.
There also is an unmet need for a high-voltage amplifier input stage having a simple slew rate enhancement capability.
USPTO Backgrounds
USPTO Backgrounds