1. Field of the Invention
The present invention relates to a method for fabricating a non-volatile memory cell, and more particularly to a method for improving the gate coupling ratio of a non-volatile memory cell in fabrication.
2. Background of the Invention
According to the related prior art, a conventional method for fabricating a non-volatile memory cell is illustrated in FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2E. FIG. 1A to FIG. 1D are the layout figures of a non-volatile memory cell. FIG. 2A to FIG. 2E respectively shows the corresponding cross-sectional figures of the manufacturing steps of the same non-volatile memory cell. For example, the active region 100 shown in FIG. 1A is defined on the substrate 10 shown in FIG. 2A. FIG. 2A illustrates the cross-sectional view of the memory cell along the line 2a--2a in FIG. 1A.
As shown in FIG. 1A and FIG. 2A, the initial step is to form a field oxide layer 30 on the surface of the substrate 10 to define the active region 100. Subsequently, a channel oxide layer 20 is formed on the surface of the active region 100.
FIG. 2B shows the cross-sectional view of the memory cell along the line 2b--2b in FIG. 1A. This procedure utilizes a chemical vapor deposition process to form a polysilicon layer. Then, photolithography and etching processes are utilized to define the polysilicon layer to form a floating gate 40. Then, an insulating material such as a typical oxide-nitride-oxide ONO structure 50 is conformally deposited over the surface of the substrate 10.
FIG. 2C shows the cross-sectional view of the memory cell along the line 2c--2c in FIG. 1C. In this procedure a chemical vapor deposition process is utilized to form a polysilicon layer; a photoresist layer is coated thereon; and then a controlling gate electrode mask (not shown) is formed. Through exposure and photolithography processes, a patterned photoresist 61 is formed. With this photoresist 61, an etching process is utilized to define the polysilicon layer to form a controlling gate 60.
FIG. 2D shows the cross-sectional view of the memory cell along the line 2d--2d in FIG. 1D. In this procedure, the patterned photoresist 61 is utilized as a mask, and etching steps are sequentially utilized to remove the uncovered portions of the insulating layer 50 and the floating gate 40. Then, the patterned photoresist 61 is removed and the source/drain regions are formed. Thus, the fabrication of a non-volatile memory cell is completed.
As illustrated in FIG. 1D, the slanted-line shadow area depicts the floating gate 40 and the spotted shadow area depicts the controlling gate 60.
Furthermore, FIG. 2E shows the cross-sectional view of the memory cell along the line 2e--2e in FIG. 1D. Therein, the structure along the other direction of the non-volatile memory cell, including the source region 70 and the drain region 80, can be seen.
FIG. 3 illustrates the equivalent circuit diagram of the foregoing non-volatile memory cell. Therein, the equivalent capacitance effect is generated in the memory cell structure which includes a channel oxide layer 20, a floating gate 40, an insulating layer 50, a controlling gate electrode 60, a source electrode S-70, a drain electrode D-80 and a semiconductor substrate B-10.
When the non-volatile memory cell is activated by an appropriate voltage, a capacitance C1 will be formed across the insulating layer 50 between the floating gate 40 and the controlling gate 60 and a capacitance C2 will also be formed across the channel oxide layer 20 between the floating gate 40 and the substrate 10. When the floating gate voltage is Vl and the controlling gate voltage is V2, the relation equation of the capacitance values and the voltage values is as follows: EQU V1=C1/(C1+C2)*V2.
Based on the foregoing relation equation, a larger capacitance C1 has a relatively higher gate voltage coupling ratio. In other words, a larger capacitance C1 decreases the operation voltage required for a non-volatile memory cell to perform the program/erase operation.
The prior art for improving the gate coupling ratio of a non-volatile memory cell is as described in the U.S. Pat. No. 5,646,059. Referring to FIG. 4, the prior art mainly utilizes the polysilicon spacers 148 formed by the liquid phase deposition process to increase the surface area of the insulating region 150 between the floating gate 140 and the controlling gate 160. Thus, the gate coupling ratio is improved.
However, the main disadvantage of the foregoing prior art is that the process is complicated and difficult to control. Thus, it is not suitable for mass production.
USPTO Backgrounds
USPTO Backgrounds