1. Field
This invention relates to a reference voltage, and more specifically, to reducing signal dependence for the reference voltage.
2. Background
In a successive approximation register analog-to-digital converter (SAR-ADC), the reference voltage should be stable during the conversion cycle. Moreover, if the digital-to-analog converter (DAC) inside the ADC is capacitive (i.e., CDAC), some charge needs to be drawn from the reference voltage to the CDAC at every voltage change during the conversion cycle of the ADC. In one conventional solution, the size of the decoupling capacitor is increased such that the output impedance of the reference voltage source stays low enough to keep the reference voltage constant even with a large amount of charge that is needed for the DAC in a short period of time. However, this results in a very large area overhead.
FIG. 1 is a graph 100 showing the reference voltage versus the conversion step of a conventional CDAC. In this figure, the input is sampled at step 1 (110), a most-significant bit (MSB) decision is made at step 2 (112), an MSB-1 decision is made at step 3 (114), and other successive decisions are made in steps 4 through 11 (120), with a least-significant bit (LSB) decision being made at step 11 for a 10-bit ADC. As shown in FIG. 1, the reference voltage drops for the MSB conversion steps rather than staying constant due to discharging of the finite capacitor. At MSB steps, the voltage change needed on the CDAC is the largest and the total capacitance in the CDAC (that is being switched) is also the largest. Consequently, the charge drawn from the decoupling capacitor is so high that the voltage across the capacitor drops (see steps 2-5 in FIG. 1). Although the buffer tries to provide some charge to the decoupling capacitor, the total charge provided by the buffer cannot compensate for the charge drawn by the CDAC, since its bandwidth is limited and the conversion steps are very short in time. If the drop in reference voltage is decision independent (for instance, at the first MSB conversion), it translates to a differential nonlinearity (DNL) in the ADC characteristic curve.
After about steps 5-6, it can be seen that the drops due to the switching CDAC are much smaller and the buffer provides some excess charge to the decoupling capacitor, which results in a climb or slow increase in the reference voltage. This climb translates to a non-linearity in LSB conversions. The size of the non-linearity in LSBs depends on the slope of the climb and the number of appearances on the characteristic depends on an LSB that causes the slope to be the steepest.
After the second MSB decision (i.e., step 3 in FIG. 1), the drops are not equal for different cases. For example, if the comparator decision until step 3 is 00, then the drop in the reference voltage for step 3 is less than the case for 01. These code/input dependent drops in the reference voltage can result in an integral nonlinearity (INL) in the characteristic of the ADC.
USPTO Backgrounds
USPTO Backgrounds