Semiconductor memories are utilized in a variety of applications, including digital communications systems in which the memories may be used for the temporary storage of data transmitted to or received from a communications network. Communications networks increasingly transfer data at faster rates, so the semiconductor memories transferring data to or receiving data from the communications network must be capable of performing such transfers at corresponding faster rates. For example, some local and wide area communications networks may transfer data at a rate of up to 155 million bits per second ("Mbps") in asynchronous transfer mode ("ATM"). Where such high data transfer rates are required, static random access memories ("SRAMs") are typically utilized due to the relatively high bandwidth of SRAMs. The bandwidth of a memory device is the rate, in bits per second, at which data is transferred to and from the device. Although SRAMs provide the necessary bandwidth in such applications, they are relatively costly in terms of price per bit when compared to conventional dynamic random access memories ("DRAMs"). Thus, it is desirable to utilize DRAMs in place of SRAMs in these high-speed communications networks. Conventional DRAMs, however, have insufficient bandwidth to transfer data at the rates required by these high-speed communications networks.
FIG. 1 is a signal timing diagram of a read data transfer operation for a conventional DRAM having an address bus ADDR, a data bus DQ, and a control bus. As known in the art, the DRAM includes a memory-cell array comprising a number of memory cells arranged in rows and columns, each memory-cell storing a binary bit of data. To begin the read data transfer operation, an external circuit, such as a microprocessor or a DRAM controller, drives a write enable signal WE high to define a read data transfer operation and drives an output enable signal OE low to enable the DRAM to place addressed data on the data bus DQ. The external circuit then applies a row address ROWX on the address bus ADDR and drives a row address strobe signal RAS low at a time t.sub.0. In response to the row address strobe signal RAS going low, the DRAM latches the row address ROWX and row address decode circuitry decodes the row address ROWX and activates a corresponding row of memory cells in the memory-cell array. After the external circuit drives the row address strobe signal RAS low, it delays for a fixed amount of time, places a column address COLM on the address bus ADDR, and thereafter drives a column address strobe signal CAS low at a time t.sub.1. The DRAM latches the column address COLM in response to the signal CAS going low and column address decode circuitry begins decoding the column address COLM. At about a time t.sub.2, the row address ROWX and column address COLM have been decoded and the DRAM places on the data bus DQ the addressed data D1 where it is read by the external circuit.
After the external circuit has read the data D1, it drives the signals OE, RAS, and CAS high in preparation for the next data transfer operation with the DRAM. In response to the signal OE going high, the DRAM, after a short delay, removes the data D1 from the data bus DQ. The external circuit must maintain the row address strobe signal RAS high for at least a row precharge time t.sub.RP before beginning the next data transfer operation with the DRAM. The row precharge time t.sub.RP is the time required by the DRAM to precharge and equilibrate the memory-cell array and reset the address decode circuitry in anticipation of the next data transfer operation. In FIG. 1, the row precharge time t.sub.RP lasts from the time t.sub.2 until a time t.sub.3 at which time the external circuit begins the next read data transfer operation by placing a new row address ROWY on the data bus DQ and driving the row address strobe signal RAS low causing the DRAM to latch and begin decoding the new row address ROWY. The external circuitry then places a new column address COLN on the address bus ADDR, drives the column address strobe signal CAS low, and the DRAM, in response to the signal CAS going low, latches and begins decoding the new column address COLN. The DRAM operates as previously described to supply new data D2 on the data bus DQ where it is once again read by the external circuit.
The bandwidth of a conventional DRAM is limited by a cycle time t.sub.RC corresponding to the minimum amount of time the external circuit must wait between consecutive data transfer operations. This is true because data can be read from the DRAM only once during the cycle time t.sub.RC.The cycle time t.sub.RC is approximately equal to the sum of the row precharge time t.sub.RP and a row access time t.sub.RAC which is the amount of time it takes the DRAM to present data on the data bus DQ after a row address has been latched into the DRAM in response to the row address strobe signal RAS going low. The row access time t.sub.RAC includes the time it takes the DRAM to latch, decode, and activate the row of memory cells corresponding to the row address ROWX. Also shown in FIG. 1 is a column access time t.sub.CAC corresponding to the time it takes the DRAM to present data on the data bus DQ after the column address strobe signal CAS goes low. The column access time t.sub.CAC includes the time it takes the DRAM to latch, decode and access the column of memory cells corresponding to the column address COLM. As seen in the signal timing diagram, the column access time t.sub.CAC is much shorter than the row access time t.sub.RAC due to the inherent nature of activating an addressed row of memory cells in the memory-cell array versus accessing an addressed memory-cell in one of the columns within the activated row as known in the art.
Various modes of operation for DRAMs have been developed to take advantage of the shorter column access time t.sub.CAC and thereby increase the bandwidth of the DRAM. One such mode of operation is known as Fast Page Mode and is illustrated in the signal timing diagram of FIG. 2. In Fast Page Mode operation, each row of memory cells is designated a page and data is read from or written to random columns of memory cells contained in an activated page. The increased bandwidth of Fast Page Mode operation is realized by exploiting the much shorter column access time t.sub.CAC when compared to the row access time t.sub.RAC as previously discussed. In Fast Page Mode operation, the external circuit places an initial row address ROWX on the address bus ADDR and drives the row address strobe signal RAS low at time t.sub.0 to latch the row address ROWX in the DRAM. The external circuit then places an initial column address COLM on the address bus ADDR and drives the column address strobe signal CAS low at a time t.sub.1 to latch the column address COLM in the DRAM. As previously described, the DRAM decodes the row and column addresses and at a time t.sub.2 places the corresponding data D1 on the data bus DQ.
Up to time t.sub.2, the Fast Page Mode read operation is identical to the conventional read operation previously described with reference to FIG. 1. In contrast to the conventional read operation, however, at time t.sub.2 the external circuitry maintains the row address strobe signal RAS low keeping the initial addressed row ROWX activated. The external circuit thereafter drives and maintains the column address strobe signal CAS high for at least a column precharge time t.sub.CP. The column precharge time t.sub.CP is the time during which various circuits in the DRAM are precharged and equilibrated in anticipation of placing on the data bus DQ the data corresponding to a subsequent column address. It should be noted that the column precharge time t.sub.CP is significantly shorter than the row precharge time t.sub.RP. The external circuit then places a second column address COLN on the address bus ADDR and drives the column address strobe signal CAS low at a time t.sub.3 causing the DRAM to latch and decode the column address COLN. At a time t.sub.4, the DRAM places on the data bus DQ the data D2 corresponding to the column address COLN where it is read by the external circuity. The external circuitry thereafter drives the column address strobe signal CAS high, places the next column address COLQ on the address bus ADDR and once again drives the column address strobe signal CAS low at a time t.sub.5 causing the DRAM to latch and decode this column address and place on the data bus DQ the corresponding data D3 at a time t.sub.6 where it is likewise read by the external circuitry.
In Fast Page Mode operation, the external circuit reads data from as many columns in the active page as desired by sequentially placing new column addresses on the address bus ADDR and toggling the column address signal CAS at a Page Mode cycle time t.sub.PC as shown. In response to the toggling column address strobe signal CAS, the DRAM sequentially latches and decodes the column addresses and places the corresponding data on the data bus DQ at the appropriate times. In Fast Page Mode operation, as long as data is read from memory cells in the activated page the bandwidth of the DRAM is determined by the Fast Page Mode cycle time t.sub.PC which is substantially less than the cycle time t.sub.RC of a conventional DRAM since no row precharge time t.sub.RP and row access time t.sub.RAC delays are incurred. When data must be read from a different page, however, the external circuit must drive the row address strobe signal RAS high, as shown at time t.sub.7, and delay the row precharge time t.sub.RP before a subsequent row address ROWY is latched into the DRAM as previously described. Moreover, after the row precharge time t.sub.RP the external circuit drives the signal RAS low at a time t.sub.8, but data will not be supplied on the data bus DQ until the row access time t.sub.RAC after the signal RAS is driven low. Thus, in the Fast Page Mode of operation, the bandwidth of the DRAM is negatively affected by the row precharge time t.sub.RP and row access time t.sub.RAC when the external circuit addresses data in a page other than the active page. The accessing of data in a page other than the active page is known as a "Page Miss."
Another mode of operation for increasing the bandwidth of DRAMs is known as Extended Data Output (EDO) Page Mode of operation and is similar to the conventional Page Mode of operation just described with reference to FIG. 2 except that in the EDO Page Mode of operation the DRAM supplies data on the data bus DQ even after the column address strobe signal CAS goes high. With reference to FIG. 2, the transition of the column address strobe signal CAS just after the time t.sub.2 turns off, after a time delay, the data D1 supplied by the DRAM on the data bus DQ. Thus, the external circuit must delay in driving the column address strobe signal CAS high to ensure it has adequate time to read the data supplied by the DRAM on the data bus DQ. In contrast, in the EDO Page Mode of operation the DRAM supplies data on the data bus DQ after the high-going transition of the column address strobe signal CAS thereby allowing the external circuit to drive the signal CAS high at an earlier time. For example, with reference to FIG. 2, in the EDO Page Mode of operation the external circuit drives the column address strobe signal CAS high just before the time t.sub.2 but does not read the data D1 until time t.sub.2 as in conventional Page Mode operation. By driving the column address strobe signal high before the time t.sub.2, the column precharge time t.sub.CP is initiated before the data D1 is output on the data bus DQ thereby enabling the external circuit to more quickly latch a new column address into the DRAM after the external circuit has read the data D1. The Page Mode cycle time t.sub.PC is accordingly reduced, resulting in a corresponding increase in the bandwidth of the DRAM.
FIG. 3 is a signal timing diagram illustrating a read data transfer operation during another mode of operation for increasing the bandwidth of a DRAM known as Burst Mode. A Burst Mode DRAM includes an internal column address counter which develops, in response to the external circuit toggling the column address strobe signal CAS, sequential column addresses starting at the column address placed on the address bus ADDR. In Burst Mode operation, the external circuit places a row address ROWX on the address bus ADDR and drives the row address strobe signal RAS low at a time t.sub.0. In response to the signal RAS going low, the DRAM latches the row address ROWX, and decode circuitry in the DRAM decodes the row address and activates the page corresponding to this row address. The external circuit thereafter places a column address COLM on the address bus ADDR and drives the column address strobe signal CAS low at a time t.sub.1. In response to the column address strobe signal CAS going low, the DRAM latches the column address COLM, and address decode circuitry in the DRAM decodes the column address and activates the column corresponding to this column address. The external circuit thereafter toggles the column address strobe signal CAS at the burst Page Mode cycle time t.sub.PC to clock the internal column address counter.
In operation, after the row address ROWX and column address COLM have been decoded the DRAM first places on the data bus DQ the data DATAM corresponding to the column address COLM. The DRAM then sequentially places on the data bus DQ the data DATAM+1, DATAM+2, and DATAM+3 corresponding to column addresses M+1, M+2, and M+3, respectively, developed by the internal column address counter in response to the external circuit toggling the signal CAS. Note that at a time t.sub.2 the external circuit places a second column address COLN on the address bus ADDR which the DRAM subsequently latches and then places on the data bus DQ the DATAN-N+3 as previously described. In the typical Burst Mode shown in FIG. 3, the external circuit provides one column address on the address bus ADDR for every four bits of data output by the DRAM, but varying burst lengths can likewise be provided. The internal generation of column addresses in Burst Mode reduces the Page Mode cycle time t.sub.PC since the address setup and hold times required in conventional Page Mode or EDO Page Mode operation are eliminated. The reduced Page Mode cycle time t.sub.PC in Burst Mode translates to a higher bandwidth for Burst Mode operation.
In burst mode operation, a burst cycle must be terminated and the row precharge time t.sub.RP must elapse before a new row address ROWY can be latched into the DRAM at a time t.sub.3 to begin another burst cycle. In addition, after the new row address ROWY is latched by the DRAM, data corresponding to this new burst page is not available until after expiration of the row access time t.sub.RAC as previously described. In other words, when a Page Miss occurs, addressed data stored in the newly addressed page cannot be read out of the DRAM until after expiration of the row precharge time t.sub.RP and the row access time t.sub.RAC. As previously described, the sum of the row access time t.sub.RAC and row precharge time t.sub.RP is much greater than the Page Mode cycle time t.sub.PC so Page Misses lower the bandwidth of the Burst Mode DRAM because the external circuit must delay this longer time before reading data from the DRAM. Thus, in Burst Mode operation, as with the other previously described DRAM modes of operation, the bandwidth of the DRAM is decreased by Page Misses.
There is a need for a high-speed DRAM that can access data stored in random pages without the Page Miss penalty associated with conventional DRAMs.
USPTO Backgrounds
USPTO Backgrounds