The present inventive concepts relate to semiconductor devices, and more particularly, to semiconductor field effect transistor devices.
III-V semiconductor-based MOSFETs including III-V channel materials may have good CV/I characteristics and relatively high current at low voltages. This may be attributable to the relatively high mobility achievable in the channel, as well as the relatively low parasitic resistance for some semiconductor/metal combinations. The high mobility may be attributed at least in part to the relatively low electron effective mass. Due to the isotropic nature of the effective mass in many III-V semiconductors, the quantum-confinement mass may also be small, which may result in electron wavefunctions that may be broad and may penetrate into the gate dielectric layer(s) surrounding the channel. The gate dielectric layer(s) may be non-crystalline layers on the channel and/or may separate the channel from a non-crystalline gate electrode. The presence of such non-crystalline layers on the surface of the typically crystalline channel may result in carrier scattering (typically referred to as surface roughness (SR) scattering), which may limit the mobility of confined electrons.
Some III-V semiconductor-based MOSFETs including III-V channel materials may include crystalline buffer layers, such as indium phosphide (InP), around the channel. The crystalline buffer layer(s) may have a thickness that is sufficient to separate the crystalline channel from the non-crystalline layers and help reduce carrier scattering. However, such buffer layers may degrade the short-channel performance of the device, due to the increased separation of the gate electrode and the channel inversion layer. Thus, the use of crystalline buffer layers may limit the use of III-V MOSFETs to relatively long gate lengths (for example, greater than about 40 nm).
USPTO Backgrounds
USPTO Backgrounds