The present invention generally relates to a programmable logic array circuit, and in particular to an improvement of a circuit structure of a programmable logic array circuit.
As is well known, a static random access memory (SRAM) or an erasable programmable read only memory (EPROM) is driven by an address transition detect pulse (ATD pulse) in order to speed up a logic operation thereof. On the other hand, a conventional programmable logic array circuit (hereafter simply referred to as PLA circuit) is driven by two different pulse signals having mutually different phases. This is because the PLA is divided into two parts of an AND array and an OR array. The AND array is driven by one pulse signal and the OR array is driven by the other pulse signal. The above PLA is disclosed in the following publication: T. Sasao, "HOW TO CONSTRUCT AND USE A PLA", Nikkan Kogyo Shinbunsha, pp. 19.
Alternatively, a PLA which is driven by a single pulse signal is proposed: see the Japanese Laid-Open Patent Application No. 51-61256. The disclosed PLA is a dynamic PLA circuit constructed by n-channel metal oxide semiconductor transistors (hereafter simply referred to as n-channel CMOSs). The PLA contains flip-flops for temporarily holding outputs of corresponding product (AND) term lines, and other flip-flops for temporarily holding outputs of OR output term lines. These flip-flops are driven by the single pulse signal.
However, the conventional PLA circuit driven by two different clock signals has the following disadvantages. First, the two different pulse signals must have a constant phase difference which amounts to a time taken for an output of the AND array to become stabilized or settled. For this reason, there is a limit on the operation speed of the PLA. Secondly, in case where the two different clock signals become out of phase, an erroneous operation may be caused and further the yield rate of production of the PLA circuit may be decreased. Thirdly, the two different clock signals are generated by an external circuit irrespective of timing at which input signals are applied to the AND array. This is inconvenient in practical use, and leads to an decrease of the operation speed.
The conventional PLA circuit driven by the single pulse signal has disadvantages described below. First, the size of the PLA circuit cannot be considerably reduced, because a number of flip-flops must be used. Further, the single pulse signal is generated by an external circuit irrespective of timing at which input signals are supplied to the AND array. Therefore, the input signals may be supplied to the AND array before corresponding product term lines are completely charged up. This may cause an erroneous operation and reduce the operation speed.
USPTO Backgrounds
USPTO Backgrounds