This invention relates generally to a method and structure for reducing the capacitive coupling either between lines on the same layer (intralayer) or between lines on superposed layers (interlayer) in VLSI or ULSI circuits. In more particular aspects the present invention relates to a method and structure for yielding an effectively reduced dielectric constant between lines on the surface of a given VLSI or ULSI chip or on lines mounted on various layers or surfaces on VLSI or ULSI structures utilizing air, other gasses, or a partial vacuum as a dielectric medium.
USPTO Backgrounds
USPTO Backgrounds