1. Technical Field
The present invention relates in general to designing and simulating digital devices, modules and systems, and in particular, to a method and system for computer simulation of digital devices, modules and systems utilizing a hardware description language (HDL) model. More particularly, the present invention relates to methods, systems, and program products for recording minimum and maximum events counts of a simulation.
2. Description of the Related Art
Verifying the logical correctness of a digital design and debugging the design, if necessary, are very important steps in most digital design processes. Logic networks are tested either by actually building networks or by simulating networks on a computer. As logic networks become highly complex, it becomes necessary to simulate a design before the design is actually built. This is especially true when the design is implemented as an integrated circuit, since the fabrication of integrated circuits requires considerable time and correction of mistakes is quite costly. The goal of digital design simulation is the verification of the logical correctness of the design.
In a typical automated design process that is supported by a conventional electronic computer-aided design (ECAD) system, a designer enters a high-level description utilizing a hardware description language (HDL), such as VHDL, producing a representation of the various circuit blocks and their interconnections. The ECAD system compiles the design description into a format that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the design prior to developing a circuit layout.
A simulator is typically a software tool that operates on a digital representation, or simulation model of a circuit, and a list of input stimuli representing inputs of the digital system. A simulator generates a numerical representation of the response of the circuit, which may then either be viewed on the display screen as a list of values or further interpreted, often by a separate software program, and presented on the display screen in graphical form. The simulator may be run either on a general-purpose computer or on another piece of electronic apparatus, typically attached to a general purpose computer, specially designed for simulation. Simulators that run entirely in software on a general-purpose computer will hereinafter be referred to as “software simulators”. Simulators that are run with the assistance of specially designed electronic apparatus will hereinafter be referred to as “hardware simulators”.
Usually, software simulators perform a very large number of calculations and operate slowly from the user's point of view. In order to optimize performance, the format of the simulation model is designed for very efficient use by the simulator. Hardware simulators, by nature, require that the simulation model comprising the circuit description be communicated in a specially designed format. In either case, a translation from an HDL description to a simulation format, hereinafter referred to as a simulation executable model, is required.
The results obtained from running a simulation testcase against a simulation model may vary depending upon not only factors within the simulation model, but also factors outside of the simulation model. These external factors may include, for example, those controlling the set up of the simulation model or characteristics of the testcase.
A particular example of an external factor that influences simulation results is testcase strategy. In order to exercise complex simulation models, such as those simulating the logical behavior of microprocessors, testcases are commonly generated by testcase generation software having hundreds or thousands of different input parameters. Each set of testcases created from a menu of common input parameter values is called a testcase strategy. In order to achieve sufficient test coverage, the testcase generation software may generate testcases representing tens of thousands of different testcase strategies.
Understandably, simulation engineers are very interested in determining which testcase strategies provide the most useful simulation results so that the less helpful strategies can be eliminated and the bulk of simulation jobs can be performed utilizing testcases generated utilizing the better testcase strategies. In order to determine which testcase strategies are preferred, it is helpful if simulation engineers can view simulation results, such as event counts, by testcase strategy.
The present invention also recognizes that it would be useful and desirable for a simulation engineer or designer to know not only the aggregate number of occurrences of events in a simulation model, but also the maximum and minimum number of occurrences of selected events during a simulation run.
USPTO Backgrounds
USPTO Backgrounds