With the rapid development of the microelectronics technology, the feature size of the integrated circuit keeps scaling down, and the interconnection density increases. At the same time, the user has an increasing demand for high performance and low power consumption. In this case, the way of further reducing the line width of interconnection line to improve, the performance is limited by the physical properties of the material and the equipment craft. Hence, the resistance and capacitance (RC) delay of the 2D interconnection line gradually becomes the bottleneck of the performance improvement of semiconductor chip. Through silicon via (TSV) process can realize, the 3D interconnection, between wafers (chips) or between a chip and a substrate by producing metal columns in wafers with metal bumps, which can make up for the limitations of traditional 2D wiring of semiconductor chips. Compared with the traditional stacking techniques including the bonding technique, this interconnection method has increased, the 3D stacking density and reduced packaging dimension, thus it can greatly improve the speed of the chip and reduce the power consumption. Therefore, TSV technique is becoming one of the key techniques for the high density packaging.
TSV is a technique that produces vertical via holes between chips or between wafers, and deposits the conductive material in vertical via holes by using the methods including electroplating to realize the interconnection. Specifically, TSV is exposed from the substrate by thinning the back surface of the wafer, and then bumps are formed on the exposed TSV. These bumps are both electrically and mechanically connected with the corresponding bumps (i.e., solder bumps) on prefabricated adjacent substrates or chips. Due to the inevitable non-uniformity problem of the current Si processing techniques, when performing 3D/2.5D integration process on the chip or wafer including fine-pitch bumps (less than 40 μm), there exists a height difference among the exposed TSVs, which is called total thickness variation (TTV) and is usually larger than 2 μm. Hence, to ensure that all the TSVs expose out of the back surface of the wafer and guarantee the effective interconnection between the hump and the TSV metal, the maximum height of the exposed TSV on the wafers should be larger than 2 μm. However, such a height difference is a challenge for the physical vapor deposition (PVD) technique that deposits the 2D electroplating seed layer in the general bump production process. The existing equipment and technology can hardly guarantee the continuity of the seed layer close to the lateral wall of TSV when the TSV backside reveal is perpendicular to the silicon substrate. Especially, since the size of the micro bump is usually slightly larger than that of the TSV, when the micro bumps directly form on the TSV, voids usually form on the lateral wall of the TSV and the junction of the silicon substrate and TSV, which affects the reliability of the interconnection.
The technical scheme for solving the aforementioned problem has not been found in prior art.
USPTO Backgrounds
USPTO Backgrounds