1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a quarter-pitch two intersection-point twin cell array type semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows an example of conventional memory devices. The semiconductor memory device comprises a plurality of word-lines 121 arranged in a predetermined direction (upper-lower direction in FIG. 1) and in parallel to each other, a plurality of bit lines 122 arranged orthogonally to the word lines 121 and in parallel to each other, a plurality of memory-cells 123 (represented by circular marks) provided at predetermined intersection points of a plurality of the word-lines and a plurality of the bit lines, the number of the predetermined intersection points being equal to half of all of the intersection points, a plurality of switches 124 connected to one-side ends (left-hand side in FIG. 1) of a plurality of the bit lines 122, a pair of control-lines 125, one of the control lines 125 being commonly connected to the bit lines 122 provided at the odd-numbered positions counted from the lowest bit line in FIG. 1, the other thereof being commonly connected to the bit lines 122 provided at the even-numbered positions, and a plurality of sense-amplifiers (SA) 126 each connected to two pairs of bit-lines (four bit lines) 122 via a plurality of the switches 124.
In this semiconductor memory device, when one of the control lines 125 is selectively driven by means of a control-line drive circuit (not shown), and moreover, any one of the word lines 121 is selectively driven by means of a word-line drive circuit (not shown), a pair of memory cells 123 Are electrically connected to each sense amplifier 126. For eagle, when the left-side line of the two control lines 125, represented by the bold line in FIG. 1, and also, the word line 121 positioned on the left-side end is selected, the memory cells 123 connected to the bit lines 122 first-numbered and third-numbered counted from the lowest bit-line are connected to the sense amplifier 126 provided at the lowest position. Each sense amplifier 126 writes complementary information corresponding to one bit in the pair of the memory cells 123, or reads the information therefrom.
In the semiconductor memory device of FIG. 1, the memory cells 123 are used in such a manner that two memory cells operate as one set, as described ave. Thus, the device is called a twin-cell array. Moreover, in this semiconductor memory device, the word line 121 for selection of a pair of two memory cells 123 intersects two bit lines 122 for selection of the memory cells 123. Thus, the device is called a two intersection point type. Moreover, it can be assumed that memory cells 123 are arranged in the bit line direction, in a repeated unit (one pitch) based on the intersection points of one bit line and four word lines. In this case, the memory cells 123 connected to each bit line 122 adjacent to the above-described bit line are arranged so as to be shifted by half of the pitch. Accordingly, this device is called a half pitch type.
This type semiconductor memory device is described, e.g., in U.S. Pat. No. 6,272,054 B1.
To increase the memory capacitance per unit area (for high integration and high capacitance) in the semiconductor memory device, it is required to reduce the intervals between the bit lines an much as possible. Moreover, regarding the switches connected to the bit lines, it is also required to configure or arrange the switches (or the bit line selection switches) so that the intervals between the bit lines are prevented from increasing. Thus, in the conventional semiconductor memory device, the bit line selection switches are configured or arranged as shown in FIG. 2.
In particular, according to the switch layout shown in FIG. 2, two adjacent switches 124 are formed as a two-integration type MOS transistor switch 134 which comprises a common source region 131 and drain regions 132 and 133 independent from each other. The integration type MOS transistor switches 134 are arranged in two columns. Thus, the bit lines 122 are formed at the smallest possible interval (pitch), and a plurality of the switches 124 are made to coordinate with the small intervals.
However, in the conventional switch layout, spaces required for formation of dog-bones in the peripheries of contacts 135, 136a, and 136b to reduce the contact resistances. The contact 135 is provided on the integration type MOS transistor switch 134 to connect the switch 134 to a connection line extended to the sense amplifier 126. The contacts 136a and 136b are provided on the integration type MOS transistor switch 134 to connect the switch 134 to the bit lines. Therefore, it is needed to reduce the sizes of the contact-holes or to provide contacts having plugs made of, e.g., a polysilicon with a relatively high resistance. Accordingly, the conventional semiconductor memory devices have problems in that the contact resistant of the switches 124 are large, so that the operating speed has a limitation.
Moreover, according to the conventional switch layout, the distance between the contact 135 for connection of the connection line to the sense amplifier 126 and the contact 136a, i.e., one of the contacts for connection of the bit lines 122 is different from the distance between the contact 135 and the other contact 136b, in the respective integration-type MOS transistor switches 134, as seen in the both-directional broken line arrows in FIG. 2. Therefore, the on-resistances of the two switches 124 of each integration type MOS transistor switch 134 are different from each other. This causes a difference between the operating speeds. Problems occur in that the margin for the operating timing design is reduced.
To solve these problems, it is supposed that sense amplifiers are arranged on both sides of the memory cell array as shown in FIG. 3. Thereby, as shown in FIG. 4 by adoption of this configuration, spaces required for formation of the dog-bones 151 can be ensured without the intervals between the bit lines 122 being increased, and the contact resistances can be reduced. The technique by which sense amplifiers are arranged on both sides of a memory array is described, e.g., in Japanese Unexamined Patent Publication No. 2001-143463.
However, in the case in whit& the configuration is employed, the interval between the contact 135 and the contact 136a and that between the contact 135 and the contact 136b are more different from each other, an soon in the comparison of FIG. 4 with FIG. 2. That is, this configuration has problems in that the difference between the on-resistances of the two switches 124 of each integration type MOS transistor 134 becomes larger. Accordingly, to eliminate the difference between the on-resistances of the two switches, it is necessary to provide a region required for laying a bit line in a curved pattern, as shown in FIG. 5. This is a new problem.
USPTO Backgrounds
USPTO Backgrounds