The present invention relates to a semiconductor device exhibiting a high electrostatic-discharge withstanding capability (hereinafter referred to as an “ESD withstanding capability”) and a high surge withstanding capability. Specifically, the present invention relates to a semiconductor device constituting an integrated intelligent switching device, a combined signal input and transmission IC or a combined power IC.
Integrated intelligent switching devices, which incorporate a plurality of power semiconductor devices and a driving and controlling circuit on a same chip, have been used in on-vehicle electric equipment, various kinds of industrial equipment, motor controllers, office automation (OA) equipment, mobile (portable) equipment, household appliances and such equipment which are required to exhibit high noise withstanding capabilities including a high ESD withstanding capability and an electromagnetic compatibility (hereinafter referred to as an “EMC”).
In the past, two primary methods, the dielectric separation technique and the pn-junction separation technique, have been employed to achieve sufficient isolation of the lateral MOSFET component so as to avoid parasitic malfunctions. FIG. 19 is a cross sectional view of a conventional integrated intelligent switching device that employs the dielectric separation technique. Referring now to FIG. 19, the conventional integrated intelligent switching device includes a lateral power MOSFET section 1 in the surface portion of an n-type layer 7 formed by the epitaxial growth technique, a CMOS circuit section 2 in the surface portion of an n-type layer 8 formed by the epitaxial growth technique and constituting a driving and controlling circuit for driving and controlling the lateral power MOSFET section 1, and a lateral surge absorber section 3 in the surface portion of an n-type epitaxial layer 9 formed by the epitaxial growth technique and including a surge absorber such as a bipolar transistor and a Zener diode. Hereinafter, the layer formed by the epitaxial growth technique will be referred to as the “epitaxial layer”.
Epitaxial layers 7, 8 and 9 are insulated and isolated from each other by a silicon oxide film 5 and silicon oxide films 6 deposited on a p-type semiconductor substrate 4 and constituting a trench insulation and isolation structure. The discrete insulation structure described above prevents lateral parasitic malfunctions of lateral power MOSFET section 1, which would be caused by a surge voltage, applied noises and the operations of lateral power MOSFET section 1 itself.
FIG. 20 is a cross sectional view of a conventional integrated intelligent switching device that employs the pn-junction separation technique. Referring now to FIG. 20, the conventional integrated switching device includes a heavily doped buried epitaxial layer 15 on a p-type semiconductor substrate 4, and n-type epitaxial layers 7, 8 and 9 on heavily doped buried epitaxial layer 15. Heavily doped p-type semiconductor diffusion separation regions 16, biased at the earth potential, are between n-type epitaxial layers 7 and 8 and between n-type epitaxial layers 8 and 9. The heavily doped p-type semiconductor diffusion separation regions 16 and n-type epitaxial layers 7, 8 and 9, biased at a potential higher than that of separation regions 16, constitute a pn-junction reverse-bias separation structure, which prevents lateral parasitic malfunctions of lateral power MOSFET section 1.
When the device employing the dielectric separation technique is applied to automotive use which requires high ESD, noise, and surge withstanding capability, the area of the bipolar transistor or Zener diode constituting the lateral surge absorbing section 3 inevitably becomes large. The large area occupied by the bipolar transistor or Zener diode in the lateral surge absorbing section 3 reduces the effects of down-sizing obtained by narrowing the chip area. For improving the ESD withstanding capability and the surge withstanding capability of the semiconductor device constituting a lateral power MOSFET section 1, it is necessary to dispose a layer doped heavily enough to prevent the parasitic breakdown operation thereof or to widen the area of lateral power MOSFET section 1, sacrificing the on-resistance characteristics per a unit area.
For improving the high-current operations, the ESD withstanding capability and the noise withstanding capability of the semiconductor device constituting lateral power MOSFET section 1 in the device employing the pn-junction separation technique, it is necessary for lateral power MOSFET section 1 to be provided with a plurality of lateral bipolar transistors or a thyristor structure. The current flowing in the lateral devices causes potential variations between the devices or between the wells. The potential variations are liable to cause malfunctions or secondary breakdown. When the devices employing the pn-junction separation technique, which has the disadvantages as described above, are applied to the automotive use, a buried epitaxial layer 15 is disposed, or p-type semiconductor diffusion separation regions 16 are doped more heavily and used for a constituent element of a lateral Zener diode. However, the countermeasures described above do not substantially improve the characteristics of the lateral parasitic bipolar transistors and the thyristor. Since the chip area widened to improve the ESD withstanding capability or the surge withstanding capability is hazardous, the dielectric separation technique has been employed more often.
A combined power IC or a combined communication IC exhibiting a high surge voltage and a high ESD withstanding capability on a same chip requires an increase in the chip area and the manufacturing costse due to the reasons described above and in contradiction to the chip area reduction now in progress based on the down-sizing of the constituent elements. Therefore, a high ESD withstanding capability is realized in many cases by adding diodes, resistors and capacitors externally.
In view of the foregoing, it would be desirable to provide a semiconductor device that t facilitates forming a lateral MOSFET exhibiting a high ESD withstanding capability and a high surge withstanding capability in a smaller chip area, without the need for any complicated isolation structure.
It would be also desirable to provide integrated circuits incorporating such semiconductor devices such as an integrated intelligent switching device incorporating a plurality of power semiconductor devices and a circuit for driving and controlling the plurality of power semiconductor devices on a same chip, a combined signal input and transfer IC incorporating a plurality of digital and analog signal input and transfer circuits on a same chip, and an intelligent power IC further incorporating the device described above or the IC described above and a serial communication circuit for communicating between the device or the IC and a microcomputer.
USPTO Backgrounds
USPTO Backgrounds