The present invention relates in general to complementary metal oxide semiconductor (CMOS) technology, and more specifically, to forming uniform shallow trench isolation (STI) recesses in FinFET devices.
CMOS technology is used to construct integrated circuits such as microprocessors, microcontrollers, static random access memory (RAM) and other digital logic circuits. A basic component of CMOS designs is metal oxide semiconductor field effect transistors (MOSFETs).
A FinFET is a type of MOSFET. The FinFET is a double-gate or multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The term “fin” refers to the narrow channel between source and drain regions. A thin dielectric layer on either side of the fin separates the fin channel from the gate.
FinFET devices are fabricated by forming a “dense” set of fins on a substrate adjacent to an “isolated” region without fins. The fins/devices in the dense region are separated by shallow trench isolation (STI) recesses in the substrate (or STI regions), which are filled with a dielectric oxide.
USPTO Backgrounds
USPTO Backgrounds