Most of the devices used in today's electronic components are based on Complementary Metal Oxide Semiconductor (CMOS). The base building block of all digital CMOS circuits combines a PMOS and NMOS transistor to form an inverter. The CMOS circuit inverts the incoming signal with the complementary action of the NMOS and PMOS transistors. One issue with all CMOS circuits is the fact that the drive capability of the PMOS is several times lower than that of the NMOS device of the same geometry. This effect is due to the fact that the majority carriers in PMOS devices are holes which have lower mobility than electrons.
The most common solution to the asymmetry in PMOS and NMOS drive currents is to design the PMOS devices with wider gates to allow more drive current for a given gate voltage. This simple solution allows balancing of the NMOS and PMOS characteristics but at expense to silicon real estate. In typical implementations a balanced CMOS arrangement would be a PMOS with a gate width two to three times larger than that of the NMOS device, as shown by the prior art device in FIG. 1.
The prior art CMOS inverter layout, shown in FIG. 1, includes source and drain regions 20 and 22 for the PMOS transistor, source and drain regions 24 and 26 for the NMOS transistor, common gate 28, conductive lines 30, 32, and 34, input voltage V.sub.in, output voltage V.sub.out, and reference voltages V.sub.high and V.sub.low. The common gate 28 of the NMOS and PMOS serves as the input. The source 24 of the NMOS and the drain 22 of the PMOS are tied together by conductive line 30 which serves as the inverter output. Finally, conductive line 32 connects the source 20 of the PMOS transistor to voltage reference V.sub.high, and conductive line 34 connects the drain 26 of the NMOS transistor to voltage reference V.sub.low. In the prior art device of FIG. 1, the PMOS width W.sub.p is approximately 2.5 times the NMOS width W.sub.n.
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USPTO Backgrounds