Modern day circuitry usage has used certain types of logic design called programmable array logic units or PALS. PALS provide flexibility and logic design by providing uncommitted and unconnected AND gates, OR gates, in addition to simple D-Type flip-flops.
After the designer decides what functions he would desire, he then implements these functions by interconnecting or disconnecting the various gates and flip-flops in order to implement his desired circuitry. However, the usually provided circuitry in the PALS are not generally flexible enough or sufficient for all the functions required and thus it is desirable to implement many different types of flip-flops in a PAL by merely using only the basic D-Type flip-flops.
The programmable array logic units used are typically those provided by such manufacturers as Advanced Micro Devices of Sunnyvale, CA whose address is 901 Thompson Place, Sunnyvale, CA 94088 and who provides the
types 22V10 and 16R4. However the system and techniques to utilize the variable types of flip-flops can be used with programmable array logic manufactured by other vendors or provided in other configurations.
The invention provides simple types of PALS with D-Type flip-flops and the following features:
(1) The flip-flop can be cleared to a desired state. PA0 (2) The newly developed circuitry provides a mechanism to initiate a "hold" state.
(3) Each of the flip-flops can (programmatically) be made into an active "low" or to active "high" operational state.
It is especially desirable to provide the general flip-flops into operational functions such as a J-K flip-flop and as a toggle flip-flop. The present system and method indicates how this system and method can be effectuated.
The standard logic provided in a PAL is very limited, with no features. By interconnecting the AND gates, OR gates, inverters, buffers and D flip-flops, a very powerful general, useful flip-flop is constructed, with J, K, inputs, direct set, direct clear, and hold inputs. These features are essential and used in certain advanced computer systems.
The PALs as provided by the manufacturers, have only simple D flip-flops and unconnected AND gates, buffers, OR gates and inverters. In these PALs, a D flip-flop output follows its D input at the rising edge of the clock That is if the input is "0" , after the rising edge, the output will be "0" . If the D input is a "1" , then the output will change to a "1" after the next rising edge of the clock. Therefore, the D flip-flop does not have the means to "hold" a value for more than one clock, after the setting value at the D input, is removed. This inability to hold a value can be a problem since it is sometimes desired that the D flip-flop hold its value for a longer period of time.
The problem is solved by configuring the D flip-flops in the PALS to have inputs of direct set, direct clear, J,K, and hold. The newly added features make it possible, so that to set the flip-flop, all is needed is to raise the J input to a ONE (1). Once the flip-flop sets, after the rising edge of the clock, there is no need to maintain the J input at a ONE (1). Yet the flip-flop will hold that value for as many clocks as necessary. When required to clear it, only the K input is raised to a ONE (1) for one clock duration, and the flip-flop will be cleared.
USPTO Backgrounds
USPTO Backgrounds