Electron Beam Lithography (EBL) is a popular technique for patterning electronic devices using electron beams. The Scanning Electron Microscope (SEM) is the main tool used in industrial dopant profiling applications. SEM has been used to image doping layer superlattices, pn-junctions as well as MOSFETs.
The Scanning Tunnelling Microscope (STM) operates in an Ultrahigh Vacuum (UHV) and is therefore not so suitable for industrial scale operations. However the STM can not only image down to the atomic scale, but has also been used to manipulate matter at the atomic scale. For instance, it is possible to use a STM to pattern individual phosphorus donors in silicon with atomic precision.
The Atomic Force Microscope (AFM) is, relevantly, a different type of STM used for imaging, measuring and manipulating matter at the nanosccale. In this specification STM and AFM can be used interchangeably.
For a fully operational device, it is necessary to connect macroscopic leads to the atomic-scale device, made using the STM, after it has been removed from the UHV environment; that is “ex situ”. Many across the world have tried to develop a functional registration process for making accurate macroscopic electrical contacts and control gate electrodes on top of individual buried STM fabricated structures.
The applicant's earlier patent application, PCT/AU2004/001118, describes a method for fabricating atomic scale devices, comprising the steps of:                Creating one or more visible registration markers on a clean silicon surface.        Using a SEM to form an image of at least one of the registration markers and the tip of a STM in the vicinity of the registration marker.        Using the image to position and reposition the STM tip relative to the marker with nanometer or micron resolution in order to pattern the active region of the device structure on the silicon surface.        Forming the device on the surface and then encapsulating it with silicon such that one or more of the registration markers are still visible on the silicon surface ex situ to a SEM.        Depositing a metal layer onto the silicon surface using either optical or electron beam lithography to form one or more macroscopic ohmic or gate electrodes, at one or more locations positioned relative to the visible registration markers.        
Devices fabricated by this technique can be imaged by cleaving or FIB milling of the substrate, and subsequent imaging of the cross-section (the dopants are thus on the surface). The imaging contrast is attributed to electrostatic surface effects caused by the different ionisation energies within the doped regions. They can also be imaged in-situ by the STM tip after a few layers of silicon atoms have been laid down to encapsulate the electrically active dopants; this is done to ensure the dopants have remained in place and not moved.
Electrical characterization of atomic-scale devices patterned in (UHV) requires alignment of ex situ macroscopic contacts to the buried device layers after the samples are removed from the UHV environment.
Prepatterning the initial Si substrate with the registration markers provides a structure that can be used to align the ex situ contacts. However, the high temperature anneal (˜1100° C.) required to prepare atomically flat Si surfaces in UHV for STM imaging places severe constraints on the potential types of markers used. Also, any deterioration of surface quality in the device region due to surface contamination can limit the practical use of the registration markers.
Nevertheless, registration markers that were etched into the Si substrate before the STM lithography step to a depth of 300 nm, have been found to survive all necessary chemical cleaning and high temperature steps so that they can be imaged by an optical microscope after device patterning and growth, giving alignment accuracies of 500 nm.
However, the long term ability to align multiple gates and Ohmic contacts to buried STM-patterned dopants requires much higher alignment accuracies and has remained a key challenge for more complex, gated nano- and atomic-scale devices.
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