Field of the Invention
The present invention generally relates to 3D chip assemblies, and more particularly to selective area heating during 3D chip stacking assembly.
Background of Invention
New integrated circuit technologies include three-dimensional integrated circuits. One type of 3D integrated circuit can include two or more layers of active electronic components stacked vertically and electrically joined with through-substrate vias and solder bumps. The 3D integrated circuit can provide numerous benefits such as increased package density yielding a smaller footprint, and improved bandwidth due to the short connection lengths made possible by the use of through-silicon-vias. The 3D integrated circuit described above may be fabricated in any number of known methods. Some 3D integrated circuits can include a silicon interposer which can be used to re-direct circuitry between a chip carrier and one or more top chips.
Warping of the components of the 3D integrated circuit during typical assembly can result in failed solder bump connections and short circuits. The influence warping has on 3D chip packaging can become more significant as the chip size increases and the component thickness decreases.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds