The present invention relates generally to semiconductor device fabrication and, more particularly, to back gates for SOI devices, methods of forming back gates, and design structures for integrated circuits including the SOI devices.
Semiconductor devices must constantly offer higher performance in a smaller size to satisfy the demand for increased computing power and functionality from integrated circuits. As feature sizes shrink with advances in technology, the dimensions of the spaces between devices are correspondingly reduced. One of the barriers to further improvements in chip densities encountered with standard Complementary Metal-Oxide-Semiconductor (CMOS) technology is maintaining device isolation with increasing device density. Devices sharing the same bulk semiconductor typically rely on p-n junctions for isolation and, as dimensions shrink, leakage currents and latch-up resulting from unwanted interactions between devices can limit the integration densities achievable.
Devices fabricated using semiconductor-on-insulator (SOI) technologies provide certain performance improvements, such as lower parasitic junction capacitance, increased latchup resistance, and reduced power consumption at equivalent performance, in comparison with comparable devices built directly in a bulk silicon substrate. Generally, an SOI wafer includes a thin SOI layer of semiconductor material (e.g., silicon), a bulk substrate (e.g., a bulk silicon substrate or a silicon epilayer on a bulk silicon substrate), and a thin buried insulator layer, such as a buried oxide or BOX layer, physically separating and electrically isolating the SOI layer from the bulk substrate. In one manifestation of SOI technology, the transistor is devised such that if the BOX layer is thin enough that the electrical potential of the silicon bulk can conveniently influence the transistor.
Therefore, there is a need for improved device structures that can be fabricated that provide increased integration densities and improved device performance, as well as methods of making these device structures and design structures for an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds