The present invention relates to a charge pumping circuit and a PLL (Phase-Locked Loop) frequency synthesizer having the charge pumping circuit and, more particularly, to a charge pumping circuit for outputting a control voltage for controlling a voltage-controlled oscillator to oscillate at a target frequency.
FIG. 3 shows a PLL frequency synthesizer having a charge pumping circuit.
The PLL frequency synthesizer comprises a phase comparator 71, a charge pumping circuit 72, a loop filter 23, a voltage-controlled oscillator 73, and a frequency divider 74.
The phase comparator 71 detects the phase difference between a comparison signal fs and a reference signal fr. When the phase of the comparison signal delays from that of the reference signal, the phase comparator 71 outputs a phase error/up signal 101. When the phase of the comparison signal advances from that of the reference signal, the phase comparator 71 outputs a phase error/down signal 102.
The charge pumping circuit 72 charges the loop filter 23 upon reception of the phase error/up signal 101 and discharges it upon reception of the phase error/down signal 102.
Based on the charge and discharge currents output from the charge pumping circuit 72, the loop filter 23 generates and outputs a control voltage Vc for causing the voltage-controlled oscillator 73 to oscillate at a target frequency.
The voltage-controlled oscillator (VCO) 73 outputs, as an oscillation output signal fv, a signal whose frequency is controlled by the control voltage Vc. The frequency divider 74 divides the frequency of the oscillation output signal fv and outputs the comparison signal fs to the phase comparator 71.
This PLL frequency synthesizer operates to make the comparison signal fs in phase with the reference signal fr, and controls the voltage-controlled oscillator 73 to oscillate at a target frequency.
The arrangement of the conventional charge pumping circuit 72 shown in FIG. 3 will be described with reference to FIG. 4.
The charge pumping circuit shown in FIG. 4 comprises a constant current source 20, the loop filter 23, p-channel MOS transistors 41 and 42, and n-channel MOS transistors 43 and 44.
The constant current source 20 is constituted by p-channel MOS transistors 13 and 14, an n-channel MOS transistor 15, and a resistor 16, and generates and outputs a constant current. The p- and n-channel MOS transistors 42 and 43 output the current generated by the constant current source 20.
The source of the p-channel MOS transistor 41 is connected to the power supply, its gate receives the phase error/up signal 101, and its drain is connected to the source of the p-channel MOS transistor 42. When the phase error/up signal 101 becomes active (low level), the p-channel MOS transistor 41 is turned on and outputs the current determined by the p-channel MOS transistor 42 as a charge current I.sub.UP to the loop filter 23.
The source of the n-channel MOS transistor 44 is grounded, its gate receives the phase error/down signal 102, and its drain is connected to the source of the n-channel MOS transistor 43. When the phase error/down signal 102 becomes active (high level), the n-channel MOS transistor 44 is turned on and discharges the current determined by the n-channel MOS transistor 43 as a discharge current I.sub.DOWN from the loop filter 23.
The loop filter 23 is charged and discharged by the charge current I.sub.UP and the discharge current I.sub.DOWN, generates the control voltage, and outputs it to the VCO.
The operation of the conventional charge pumping circuit having this arrangement will be explained.
In the charge pumping circuit shown in FIG. 4, when the phase error/up signal 101 becomes active, the p-channel MOS transistor 41 is turned on. Then, the charge current I.sub.UP determined by the p-channel MOS transistor 42 is output to the loop filter 23 to increase the control voltage output from the loop filter 23.
When the phase error/down signal 102 becomes active, the n-channel MOS transistor 44 is turned on. Then, the discharge current I.sub.DOWN determined by the n-channel MOS transistor 43 is discharged from the loop filter 23 to decrease the control voltage output from the loop filter 23.
In this charge pumping circuit, the phase error/up or down signal 101 or 102 makes a source potential V.sub.GS of the p- or n-channel MOS transistor 42 or 43 change via the gate diffusion capacity of the p- or n-channel MOS transistor 41 or 44.
The charge current I.sub.UP and the discharge current I.sub.DOWN respectively determined by the MOS transistors 42 and 43 fluctuate. Accordingly, noise is superposed on the control voltage Vc output from the loop filter 23 at an interval of 1/reference signal frequency fr, as shown in FIG. 5A. The spectrum of the oscillation output signal fv from the VCO controlled by the noise-superposed control voltage Vc is measured to confirm that reference leakage caused by the reference frequency component is superposed on the signal fv, as shown in FIG. 5B.
In this charge pumping circuit, a constant current output voltage V.sub.DS between the drain and source of the p- and n-channel MOS transistors 42 and 43 depends on the state of the control voltage Vc. For this reason, the current gain varies, and the settling time is unstable.
Another example of the charge pumping circuit for suppressing variations in current gain will be described with reference to FIG. 6. The same reference numerals as in FIG. 4 denote the same parts, and a description thereof will be omitted.
The charge pumping circuit shown in FIG. 6 comprises a first switching circuit 81, a first current source 82, a second switching circuit 83, a second current source 84, an output circuit 85, and inverters 65 and 66.
The first switching circuit 81 is constituted by a p-channel MOS transistor 62, and npn transistors 51 and 55. The first current source 82 is constituted by an npn transistor 52 and a resistor 63. The second switching circuit 83 is constituted by a p-channel MOS transistor 61, and npn transistors 54 and 56. The second current source 84 is constituted by an npn transistor 53 and a resistor 64. The output circuit 85 is constituted by p-channel MOS transistors 57 and 60, and n-channel MOS transistors 58 and 59.
The inverter 65 inverts the logic level of the phase error/up signal 101 and outputs the inverted signal to the first switching circuit 81. The inverter 66 inverts the logic level of the phase error/down signal 102 and outputs the inverted signal to the second switching circuit 83.
In the first switching circuit 81, the source of the p-channel MOS transistor 62 is connected to the power supply; its drain, to the collector of the npn transistor 51; and its gate, to its drain and the gate of the p-channel MOS transistor 57. The collector of the npn transistor 55 is connected to the power supply, its base receives the phase error/up signal 101, and its emitter is connected to the emitter of the npn transistor 51. The base of the npn transistor 51 receives an output from the inverter 65.
In the first current source 82, the collector of the npn transistor 52 is connected to the emitters of the npn transistors 51 and 55, its emitter is grounded via the resistor 63, and its base receives a reference voltage Vref.
In the second switching circuit 83, the source of the p-channel MOS transistor 61 is connected to the power supply; its drain, to the collector of the npn transistor 54; and its gate, to its drain and the gate of the p-channel MOS transistor 60. The collector of the npn transistor 56 is connected to the power supply, its base receives an output from the inverter 66, and its emitter is connected to the emitter of the npn transistor 54. The base of the npn transistor 54 receives the phase error/down signal 102.
In the second current source 84, the collector of the npn transistor 53 is connected to the emitters of the npn transistors 54 and 56, its emitter is grounded via the resistor 64, and its base receives the reference voltage Vref.
In the output circuit 85, the source of the p-channel MOS transistor 57 is connected to the power supply; and its drain, to the loop filter 23. The p-channel MOS transistor 57 constitutes a current mirror circuit together with the p-channel MOS transistor 62. The p-channel MOS transistor 57 outputs, as the charge current I.sub.UP to the loop filter 23, a current having a current value based on the current flowing through the source and drain of the p-channel MOS transistor 62.
The source of the p-channel MOS transistor 60 is connected to the power supply; its source, to the power supply; and its drain, to the drain of the n-channel MOS transistor 59. The p-channel MOS transistor 60 constitutes a current mirror circuit together with the p-channel MOS transistor 61. A current having a current value based on the current flowing through the source and drain of the p-channel MOS transistor 61 flows through the source and drain of the p-channel MOS transistor 60.
The drain of the n-channel MOS transistor 59 is connected to the drain of the p-channel MOS transistor 60, the source of the transistor 59 is grounded, and its gate is connected to its drain and the gate of the n-channel MOS transistor 58.
The source of the n-channel MOS transistor 58 is grounded, its gate is connected to the gate of the n-channel MOS transistor 59, and the drain of the transistor 58 is to the drain of the p-channel MOS transistor 57 and the loop filter 23. The n-channel MOS transistor 58 constitutes a current mirror circuit together with the n-channel MOS transistor 59. The n-channel MOS transistor 58 outputs, as the discharge current I.sub.DOWN to the loop filter 23, a current having a current value based on the current flowing through the source and drain of the n-channel MOS transistor 59.
The operation of the charge pumping circuit having this arrangement will be described.
When the phase error/up signal 101 becomes active (low level), the inverter 65 outputs a high-level signal, and the differential amplifier made up of the npn transistors 51 and 55 operates to flow the current determined by the current source formed by the npn transistor 52 and the resistor 63. This constant current also flows through the source and drain of the p-channel MOS transistor 62. Then, a current having a current value based on the constant current flows as the charge current I.sub.UP through the source and drain of the p-channel MOS transistor 57, and is output to the loop filter 23.
When the phase error/down signal 102 becomes active (high level), the inverter 66 outputs a low-level signal, and the differential amplifier made up of the npn transistors 54 and 56 operates to flow the current determined by the current source formed by the npn transistor 53 and the resistor 64. This constant current also flows through the source and drain of the p-channel MOS transistor 61. Accordingly, a current having a current value based on the constant current flows through the source and drain of the p-channel MOS transistor 60 and the source and drain of the n-channel MOS transistor 59.
A current having a current value based on the current flowing through the source and drain of the n-channel MOS transistor 59 flows as the discharge current I.sub.DOWN through the source and drain of the n-channel MOS transistor 58, thereby discharging the loop filter 23.
In this charge pumping circuit, since the npn transistors 52 and 53 are not arranged on the output stage, the current gain does not depend on the output stage. Therefore, the settling time is stable, and the control voltage Vc does not decrease. Since the npn transistors 52 and 53 respectively constituting the current sources 82 and 84 are not arranged on the output stage, no output current fluctuates by the switching operation.
In this charge pumping circuit, however, when the npn transistor 51 or 54 is turned off, the gate of the p-channel MOS transistor 57 is not quickly charged, or the gate of the n-channel MOS transistor 58 is not quickly discharged. The p- and n-channel MOS transistors 57 and 58 require a long turn-off time. The output current (charge current I.sub.UP and discharge current I.sub.DOWN) for the phase error signal has poor linearity. As a result, the reference leakage and the jitter increase.
In this charge pumping circuit, since the npn transistors 51 and 54 as bipolar transistors receive the phase error signal, they require a CMOS (Complementary Metal-Oxide Semiconductor)-ECL (Emitter Coupled Logic) level converter for connection to a general digital phase comparator, resulting in a large-scale circuit.
The above conventional charge pumping circuit suffers the following problems.
(1) Since the turn-off time of the output transistor is long, the output current linearity for the phase error signal is poor, and the reference leakage and the jitter are large.
(2) A CMOS-ECL level converter is required for connection to a general digital phase comparator.
USPTO Backgrounds
USPTO Backgrounds