Wafer testing and packaging is a back-end process of manufacture semiconductor, wherein the wafer testing is applied to test a probe of a die of a chip, for example, a test head includes the probe fixed thereon and made of gold wire, hence the probe contacts with the pad of the die so as to test electrical characteristics of the die and eliminate unqualified die.
A size of the probe of the wafer is reduced to 24.5 μm from 150 μm, so the probe is assembled difficultly.
In addition, it takes long time to assemble the probe onto a holding tray, thus increasing production cost.
The present invention has arisen to mitigate and/or obviate the afore-described disadvantages.
USPTO Backgrounds
USPTO Backgrounds