1. Field of the Invention
The present invention generally relates to an assembly including plural through wafer vias and more particularly, an assembly including through wafer vias that electrically connect an integrated circuit of a chip and an integrated circuit of a casing having upper and lower portions formed on a side of the chip.
2. Description of the Related Art
Commercially available cold plates for single and multi-chip applications are designed for uniform heat removal. However, the power dissipation of an IC-chip is strongly non-uniform. A cold plate designed for uniform heat flux with the maximal power density as design point is not economical, since its heat removal capability at cache locations is exceeding the needs and results in waste of pumping power and loss of energy. These problems get accentuated in 3D stacked chips since the space for fluid manifolding and for heat removal is constrained.
A related art method for providing heat dissipation in 3D stacked chips intersperses specialized cooling structures at periodic points within the monolithic structure of the chip stack. In this related art method, a special pair of chips is interspersed. One chip has had a trench etched into it, and the other acts as a cap. When the chips are put together and interspersed between active chips, the chips form cooling channels.
C-4 bumps provide electrical connection to the individual chips on one face of the structure, while the cooling channels are exposed on a second face. A fluid manifold is attached to the second face to provide coolant flow. The trenches may be etched in the cooling channels. More than one face may be used for electrical connection to the chip stack.
In another embodiment of this related art method, metal cooling plates of Aluminum, Copper, Molybdenum, etc. are interspersed between active chips. The C-4 bumps provide electrical connection to the individual chips on one side of the face of the structure, while the cooling plates are connected to a heat sink on a second face. More than one face may contain electrical connection to the chip stack.
However, in this related art method, the cap chip and trench chips are not active chips. Thus, this related art method is an inefficient use of space on the system board.
USPTO Backgrounds
USPTO Backgrounds