Conventionally, a voltage amplitude modulation (AM) control or a pulse width modulation (PWM) control has been performed in a drive circuit for a luminescent element (e.g. LED (Light Emitting Diode), EL (Electro Luminescence), FED (Field Emission Display), or SED) whose brightness varies in accordance with an applied voltage, for the purpose of controlling the brightness of the luminescent element.
In the AM control, a voltage value of a drive signal to be applied to the luminescent element is varied in accordance with the display-brightness intended. Further, in the PWM control, a pulse width of a drive signal having a predetermined voltage amplitude is varied in accordance with the display-brightness. In this case, a human senses the length of a luminescent period as a difference in a the brightness, as a result of integrating on a time-basis the length of the luminescent period in the human's vision.
Further, a drive method which is a combination of the AM control and the PWM control is suggested as a method which allows for a high quality grayscale displaying to realize a high expressive power (e.g. Japanese Unexamined Patent Publications No. 015430/1999 (Tokukaihei 11-173159; Published on Jan. 22, 1999; hereinafter, Patent Document 1) and No. 173159/2003 (Tokukai 2003-173159; Published on Jun. 20, 2003; hereinafter, Patent Document 2; corresponding foreign application: US2002/0195966). With the combination of the two control methods, an amplitude resolution and a pulse width resolution are kept from unnecessarily increasing with an increase in the grayscale level, and the high grayscale displaying, therefore, can be easily realized.
Incidentally, the following problems take place if adopting a combination of the PWM control and the AM control as a method for driving a luminous elements which are wired and arranged in a matrix manner. Namely, a ringing occurs due to the inductance of a signal line connected to the luminous elements, and a display quality is deteriorated due to round waveform attributed to resistance component and a capacitance between lines. The Patent document 2 discloses the following drive method, for solving these problems, which uses a drive waveform having a stair-like rising and falling shapes.
The Patent Document 2 describes an example of a drive waveform used for 1024-grayscale (10 bits) displaying performed by combining the 4-grayscale AM control with 259-grayscale PWM control. FIG. 11 illustrates examples of such a drive waveforms. For the sake of easier understanding, FIG. 11 only illustrates drive waveforms of suitably selected grayscale levels having characteristic waveforms, instead of illustrating the waveforms of all the grayscale levels.
In the AM control, an amplitude is controlled to four electric potentials which are: a first grayscale voltage amplitude V1; a second grayscale voltage amplitude V2; a third grayscale voltage amplitude V3; and a fourth grayscale voltage amplitude V4, in an order from lower to higher grayscale levels. Meanwhile, in the PWM control, a pulse width is controlled to be in a range from ΔT to ΔT×259, where ΔT is the smallest unit of the pulse width. As illustrated in FIG. 11, each drive waveform is controlled to have a stair-like shape in which rising and falling portions (i.e. a point at which the voltage amplitude varies) of the drive waveform have a potential difference corresponding to one grayscale level of the AM control. Note that potentials V1 to V4 are determined, based on the brightness of a luminescent element in relation to an applied voltage, so that the respective potential differences from a reference potential V0 corresponding to zero brightness (i.e. V1−V0, V2−V0, V3−V0, and V4−V0) are applied voltages respectively corresponding to four intended grayscale levels.
Here, for the sake of convenience, the concept of grayscale blocks illustrated in FIG. 12 is introduced. In the drive waveform illustrated in FIG. 12, each square surrounded by solid lines is one grayscale block. Here, it is supposed that the potential difference corresponding to each grayscale level of the 4-grayscale AM control is: ΔV1=V1−V0; ΔV2=V2−V1; ΔV3=V3−V2; and ΔV4=V4−V3. This may be also expressed as ΔVk=Vk−V(k−1), where: k is an integer, and is 1≦k≦4; Vk is k th grayscale voltage amplitude; and ΔVk is a potential difference. The grayscale block is a block which is defined by ΔVk×ΔT, where ΔVk is the potential difference corresponding to one grayscale level of the AM control, and ΔT is a minimum pulse width.
With the use of such a grayscale block, an arbitrary drive waveform can be expressed in the form of an outline formed by placing the grayscale blocks with no space, in a 4×259 matrix whose vertical axis is divided into 4 levels (ΔV1 to ΔV4), and whose horizontal axis is divided into 259 ΔTs. Each of the grayscale blocks is equivalent to one grayscale level of the brightness. One grayscale block is added every time the grayscale level increases by one level. As such, in the shape of a drive waveform of a subsequent grayscale level, the number of the grayscale blocks is increased by one.
A waveform having stair-like rising and falling means that every time the voltage amplitude varies in increment of the minimum pulse width ΔT, a step is formed by placing the grayscale block so that the variation in the voltage amplitude correspond to one grayscale block. Since the rising and falling of the waveform form a stair-like shape without an exception, a pulse width of at least 259 columns is needed for allotting 1024 grayscale levels (0 to 1023 blocks).
With the drive waveform formed under such rules, various drive waveforms are possible depending on how the grayscale blocks are placed. Further, Patent Document 2 teaches a preferred example of drive waveform illustrated in FIG. 13, which waveform is obtained by combining the AM control and the PWM control, and which has the stair-like shaped rising and falling. This drive waveform is also an exemplary drive waveform for performing 1024-grayscale (10 bit) displaying by combining the 4-grayscale AM control with the 259-grayscale PWM control.
Firstly, starting from the 1st grayscale level, a grayscale block is placed, every time the grayscale level increase, in the row of the minimum voltage amplitude V1. In the row of the minimum voltage amplitude V1, a maximum of 259 blocks can be placed. As such, the grayscale blocks can be placed in the row of the voltage amplitude V1, until the grayscale level is 259th.
From the 260th grayscale level, the grayscale block is also placed in the row of the voltage amplitude V2. This means that the AM control is also performed in combination with the PWM control, with respect to the drive waveform. Here, the 260th block is placed in the second column, instead of the first column, so that one column (=ΔT) is left open. This forms a stair-like rising portion in the drive waveform. After the 261st grayscale level, the grayscale block is successively placed in the row of the voltage amplitude V2, up to the 258th column: i.e., up to the 516th grayscale level. By placing the grayscale block in the row of the voltage amplitude V2, and leaving the 259th column open, the drive waveform has a falling portion which is also in the stair-like shape.
From the 517th grayscale level, the grayscale block is also placed in the row of the voltage amplitude V3. Here, the 517th block is placed in the third column, leaving two columns (=ΔT×2) opened, so that the drive waveform has the stair-like rising portion. After the 518th grayscale level, the grayscale block is successively placed in the row of the voltage amplitude V3, up to the 257th column: i.e., up to the 771st grayscale level. By placing the grayscale block in the row of the voltage amplitude V3, and leaving the 258th and 259th columns open, the drive waveform has a falling portion which is also in a stair-like shape.
From the 772nd grayscale level, the grayscale block is also placed in the row of the voltage amplitude V4. Here, the 772nd block is placed in the 4th column, leaving three columns (=ΔT×3) opened, so that the drive waveform has a stair-like rising portion. After the 773rd grayscale level, the grayscale block is successively placed in the row of the voltage amplitude V4, up to the 255th column: i.e., up to the 1023rd grayscale level.
By placing the grayscale blocks as described above, it is possible to realize a drive waveform having stair-like rising and falling portions. In this modulation method for realizing such a drive waveform, the voltage amplitude is modulated after the entire pulse width is used. This is advantageous in that the variation in the voltage amplitude within a pulse cycle is made small, and the drive current is equalized.
The Patent Document 2 discloses various examples of such a drive waveform, and further discloses the following drive circuit for efficiently generating the drive waveform. Namely, the drive circuit efficiently generates the drive waveform, by utilizing such a characteristic that a drive waveform having only one rising and one falling (as is the case of the examples shown in FIGS. 12 and 13) through out the entire waveform is easily defined by the respective positions of the left-end block 101 and right-end block 102 in each of the voltage amplitudes.
FIG. 14 is a block diagram for explaining a characteristic of the drive circuit disclosed in Patent Document 2. An output controlling circuit 801 is a circuit which generates, in response to modulation data 802 converted from a brightness signal, a pulse width signal for each of the voltage amplitude of the AM control. This output controlling circuit 801 includes: V1 to V4 start circuits 820 which respectively generate output-start timing signals for the voltage amplitudes V1 to V4; V1 to V4 end circuits 830 which respectively generate output-end timing signals; and V1 to V4 PWM circuits 814 which respectively generate pulse width signals, in response to the output-start timing signals from the start circuits, and the output-end timing signals from the end circuits. The output circuit 807 is so configured as to (i) receive the pulse width signal generated by the output controlling circuit 801, which signal corresponding to each voltage amplitude, and (ii) outputs as a drive signal 808, a period according to the pulse width signal, and a corresponding electric potential. In short, the output circuit 807 is a circuit which generates the final form of the drive waveform.
Each of the start circuits 820 and each of the end circuits 830 have a decoding circuit 821; a counter 822 and a comparator 823 to which respective output signals from the decoding circuit 821 and the counter 822 are input. This configuration is common in all of the start circuits and the end circuits. The modulation data 802 is input to the decoding circuit 821 of the start circuit 820 and the end circuit 830. The drive waveform for each grayscale level is determined in a one-waveform-to-one grayscale-manner. Thus, the decoding circuit 821 is set so as to output, based on the grayscale data in the modulation data 802, data which specifies a waveform corresponding to a grayscale level to be displayed. The counter 822 generates numerical data which is counted up or counted down in sync with a clock signal 805. Here, in the output controlling circuit 801, operations in relation to the voltage amplitudes V1 to V4 are all the same. On this account, the following explanation deals with an operation of the circuit in relation to the voltage amplitude V1 as a representative of operations in relation to the rest of the voltage amplitudes.
The decoding circuit 821 in the V1 start circuit 820 is set so as to output, in response to reception of the grayscale data in the modulation data 802, data which corresponds to a V1 output-start timing: i.e. a position of the left-end grayscale block in the ΔV1 row of the waveform illustrated in FIG. 12. Further, the decoding circuit 821 in the V1 end circuit 830 is set so as to output data which corresponds to a V1 output-end timing: i.e., a position of the right-end grayscale block in the ΔV1 row. Then, in each of the circuits, the comparator 823 compares the positional data with a value of the counter 822. If the value match with the data, each of the circuit outputs a V1 start signal or a V1 end signal which takes “1” as a logical value. The V1 PWM generating circuit 814 is configured by an RS flip-flop circuit. This V1 PWM generating circuit 814 is set by the V1 start signal, and is reset by the V1 end signal, so as to generate a pulse width signal TV1 which (i) rises to “1” at the timing of output-starting, and (ii) falls to “0” at the timing of output-ending, the pulse width signal TV1 corresponding to the voltage amplitude V1.
The output circuit 807 receives thus generated pulse width signals TV1 to TV4 respectively corresponding to the voltage amplitudes. Then, in accordance with the timings of the pulse width signals TV1 to TV4, the output circuit 807 switches over the output, amongst power sources whose respective electric potentials are V1 to V4. Thus, the output circuit 807 is able to output a drive waveform whose pulse width is regulated by the pulse width signal, and which corresponds to four steps of voltage amplitude.
However, the circuit suggested in Patent Document 2 needs to be a large scale circuit, so as to correspond to various drive waveforms. For example, in the case of the circuit which performs 1024-grayscale (10 bits) displaying by combining the 4-grayscale AM control and 259-grayscale PWM control, each output requires eight decoding circuits, eight counters and eight comparators, so as to generate a pulse width signal from the output-start timing and output-end timing for each of the output amplitudes of the 4 electric potentials. In a case of line-sequential driving, these circuits are needed for each pixel in the horizontal direction of a display device, and the circuit scale consequently becomes extremely large. This problem is particularly conspicuous in a large screen or high-quality display device having a large number of pixels.
Here, the drive waveform referred in the explanation of the BACKGROUND ART with reference to FIG. 13 has the following characteristics. Namely, in the AM control, the output-starting position of each amplitude is defined and is not varied. Further, in the AM control, an amplitude smaller than the maximum amplitude of a waveform is always outputted up to an output-ending position (maximum value) which is defined for each amplitude. Accordingly, it is only the maximum amplitude which is subjected to pulse width modulation according to the brightness and grayscale.
Since the output-starting position and the output-ending position (maximum value) of each amplitude are not varied in the AM control, a waveform of a unique drive waveform for each grayscale is regulated simply by supplying, as modulation data for each output, data which indicates pulse width of the maximum amplitude in a drive waveform to be outputted. Based on this new finding, the circuit scale is reduced by the following means.
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