1. Field of the Invention
Embodiments presented herein relate generally to computing systems and processing devices, and, more particularly, to a method and apparatus for determining and executing the oldest load operation in a processing device.
2. Description of Related Art
Electrical circuits and devices that execute instructions and process data have evolved becoming faster and more complex. With the increased performance and low power demands of modern data processor architectures (e.g., multi-core processors), execution of speculative memory operations, as well as non-cacheable (e.g., memory-mapped I/O) instructions has become more complex. Designing a processor capable of executing these instructions efficiently, while avoiding problematic conditions including live-lock states and coherency problems, is particularly problematic.
In some previous solutions, load queues included special flip-flops to hold physical addresses and memory types for each load instruction. In some cases, each load queue included two sets of these flip-flops in case of a misaligned instruction. These previous solutions relied upon saving the TLB information (e.g., physical address and/or memory type) after a TLB hit for each load and using the saved information for subsequent processing. In such an implementation, the saved information would be used even if the TLB would return a different status (e.g., a hit was previously returned by the TLB, but the TLB most recently returned miss). Further, although these implementations may be architecturally correct, the previous solutions require a significant number of extra flip-flops in their respective designs, for holding this TLB information.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.
USPTO Backgrounds
USPTO Backgrounds