The present invention relates to a protection device for an integrated circuit (IC) which protects the input and/or output (I/O) circuits of the IC from noise. More precisely it protects the IC from static charge break down.
Recent ICs especially MOS (metal oxide semiconductor) type ICs are provided with protection device between its input or output pads and I/O circuits, to prevent the damage caused by noise picked up by input or output signal lines or voltage supply lines. Such protection is increasing its importance as the integration rate of the IC becomes high. It is especially important for an MOS IC, since it becomes very susceptible to noise as the gate oxide layer and the diffusion layer are becoming very thin and shallow to increase the packing density of devices in the chip.
Usually the I/O protection device utilizes a diffusion layer of impurities in a substrate as the protection element of the IC. A typical example of a prior art protection circuit is given in FIG. 6 showing its cross sectional view schematically. In the figure, the reference numeral 1 designates an n-type silicon substrate. 2 is a p.sup.- -type well which is lightly doped with p-type impurity to fabricate a complementary device in it. 3 and 4 are respectively a p.sup.+ -type and an n.sup.+ -type diffusion layers which are used as resistive elements. These elements are coated with an insulation layer 5 composed of a silicon dioxide (SiO.sub.2) layer for example, and wired to an I/O pad or the I/O circuit (not shown) with an aluminum wiring layer 6 for example.
A surge protection device of such configuration blunts the wave form of input noise by the CR time constant which is composed of the capacitance (C) and resistance (R) of the diffusion layer. The capacitance C is composed of the junction capacity of a diode between the diffusion layers and the substrate or the well regions.
But the effect of such prior art noise protection devices is becoming inadequate for recent highly integrated ICs. Because the diffusion layers 3 or 4 are fabricated in an IC with a same process at the same time to fabricate the source or drain regions of MOS devices for example, so the diffusion depth becomes shallow as the the integration rate increases, and it tends to be short circuited between the wiring line 6 and the substrate 1 or the well region 2 by high current produced by noise. Moreover as the sheet resistivity of the diffusion layer 3 increases, it has an adverse effect on the high speed operation of the IC.
Recently to overcome such problems, a resistive material of poly-crystalline silicon (polysilicon) has came to be used for fabricating the resistive element. FIG. 7 shows schematically an example of such a protection device illustrating its structure by a cross sectional view. In the figure, 11 is a semiconductor substrate, 15 is an oxide layer covering its surface, 7 is the polysilicon resistive element, 16 is a thin oxide layer covering its surface, 5 is an insulating layer to passivate the surface of the device, such as phospho-silicate glass (PSG) for example, and 6 is a wiring line to connect the resistive element 7 to the bonding pad or to the I/O circuit.
Such structure has the merits of having a lower resistivity of the resistive element 7, and improved characteristics of high speed operation of the circuit. But it has also a disadvantage in that it is difficult to provide enough capacitance between the resistive element 7 and the substrate 11 to provide enough CR value for blunting the noise, because the resistive element 7 is fabricated on the oxide layer 15. Therefore it becomes difficult to make the size of the resistive element 7 small.
The protection devices having a structure like FIG. 7, therefore, often suffer from the problem that the contact part of the wiring line to the polysilicon resistive element is melted, or a leakage current is increased by defects generated in the oxide layer beneath the resistive element by temperature caused by high voltage induced on the outer wiring line.
USPTO Backgrounds
USPTO Backgrounds