1. Field of the Invention
The present invention relates generally to integrated circuit devices, and, more particularly, to a method and apparatus for testing a multibank memory module.
2. Description of the Related Art
Memory modules generally include a plurality of integrated circuit (IC) memory devices for storing data. Typically, the data is stored within these IC devices in a memory array. The array contains many memory cells, each of which stores a bit of data. In many types of memory devices, such as dynamic random access memories (DRAMs), for example, each of the memory cells stores an electrical charge, where the value of the electrical charge is indicative of the logical bit value stored in the cell. The absence of an electrical charge in the memory cell may indicate a logical “zero;” whereas, the presence of an electrical charge in the memory cell may indicate a logical “one.”
During the manufacture of these memory modules, the IC devices are generally tested by applying an input test signal through a plurality of input/output (I/O) lines that couple the IC device to a testing device through an interface, such as an edge connector. The IC devices generally respond to the input test signal by providing a test output signal over the I/O lines to the testing device through the edge connector. The testing device, upon receiving the test output signals from the IC device, evaluates the signals to determine if the integrated circuit device was manufactured in accordance with particular specifications in which it was designed to operate.
Typically, the edge connector that couples the integrated circuit devices to the testing device has a limited number of I/O ports with which to connect with the integrated circuit devices under test. Usually, when the modules are configured with multiple banks, such as two banks, for example, the I/O lines that couple each respective bank to the edge connector are coupled together. Consequently, the control logic is routed from the testing device such that only one bank is active at a time for testing by the testing device over the I/O lines. In this testing fashion, only one bank is reading test input signals and generating test output signals, respectively, from or to the testing device during a given testing session. To effectively check the functionality of the integrated circuit devices, the testing device must generally run a given test multiple times for testing each of the banks of the memory module.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
USPTO Backgrounds
USPTO Backgrounds