1. Field of the Invention
The present invention relates generally to verifying soft error handling in integrated circuit designs. Specifically, the present invention provides a system and method for verification of soft error handling using a diagnostic program run in an integrated circuit simulator.
2. Description of the Related Art
Various subcircuits in microprocessors such as register files and memory buffers store data subject to corruption by soft errors. Soft errors occur when ionizing radiation causes a node in a memory array to invert is logical value. Most hardware has embedded logic to detect, correct and log such errors and notify the software of such an event through exceptions. Instruction set simulators (ISS) are often used to verify the proper functioning of the chip in conjunction with the virtual IC described below which models the physical implementations of the chip. However, an ISS or reference architecture cannot easily model soft error events because they are not always coupled with a specific instruction and because of their inherently random nature. This presents a challenge in verifying hardware functionality pertaining to detection, correction, and logging of such errors, referred to collectively herein as soft error handling.
Typically, the hardware logic associated with soft error handling is verified with short directed self-checking tests. Such directed tests involve testing a very specific error type in a diagnostic program, e.g., just one instruction cache error, and comparing expected results with the actual error log generated by the soft error handling logic. This approach is not adequate for chip multi-threading (CMT) processors because of the presence of multiple concurrent threads, which could be executing completely independent programs. Here, the proper error handling by the error encountering thread could be hampered by events on other threads. Furthermore, an error on one thread could “leak” to another thread causing spurious logging or functional incorrectness. For example, if a thread sees an error which is then improperly reported to a different thread, the second thread will behave as if the error occurred during the execution of its own program, potentially resulting in data corruption. Thus, there exists an unmet and heretofore unidentified need for a robust and reliable means for testing soft error handling in microprocessors, and in particular, CMT processors.
USPTO Backgrounds
USPTO Backgrounds