Semiconductor technologies are continually progressing to smaller feature sizes, down to 65 nanometers, 45 nanometers, and below. Resist materials used to produce such small feature sizes no longer meet the requirement of resolution and process. For example, an existing positive tone resist coated on a substrate surface is irradiated by UV light through a photomask, end up with proton acid generated in the exposed areas. Then, a post exposure baking process is applied to the substrates for enhancing the acid amplification and the acid reaction with resist causes the polarity transformation in the exposed areas. A developer rinse was applied to the resist for dissolving the resist in the exposed areas. However, the resist and the corresponding method are vulnerable due to acid diffusion, especially during the post exposure baking. This leads to the presence of the acid in the unexposed areas, resulting in low imaging contrast and degraded imaging quality. It is difficult to obtain enough optical contrast in narrow trench pattern. There is no existing lithography solution for high mask coverage ratio layers such as metal line layers and via hole layers. Therefore, what is needed is the method and the material to address the above issue.
USPTO Backgrounds
USPTO Backgrounds