1. Field of the Invention
The present invention relates to conductive elements for electrically connecting different semiconductor device components to one another. Particularly, the present invention relates to conductive elements that are carried by semiconductor devices. More particularly, the present invention relates to stereolithographically fabricated conductive elements. The present invention also relates to the conductive lines of carrier substrates, such as circuit boards, and to methods of fabricating such carrier substrates.
2. Background of Related Art
An electronic device typically includes one or more semiconductor devices. The semiconductor devices of an electronic device are electrically connected to a carrier substrate, which, in turn, electrically connects each semiconductor device to other components of the electronic device. In order to fulfill the demands for electronic devices of ever-decreasing size and ever-increasing capability, much of the large, space-consuming circuitry components of conventional electronic devices have been incorporated into semiconductor devices. As a result, many state of the art electronic devices include semiconductor devices that are directly connected to one another.
Conventionally, electrical connections between a semiconductor device and a carrier substrate or another semiconductor device are made by way of wire bonds between bond pads of the semiconductor device and contact pads of the carrier substrate. Wire bonding is somewhat undesirable, however, in that the wire bonds are separately and sequentially formed. As state of the art semiconductor devices typically include large numbers of bond pads positioned closely to one another, wire bonding these semiconductor devices to carrier substrates or other semiconductor devices can be a very time-consuming process.
The semiconductor devices of many state of the art electronic devices are connected to carrier substrates or other semiconductor devices with alternative types of intermediate conductive elements. For example, semiconductor devices can be flip-chip bonded, or bonded by way of a controlled collapse chip connection (C-4) to a substrate or another semiconductor device with conductive structures, such as solder balls. When flip-chip type bonds are used, a minimal amount of the real estate on a carrier substrate or other semiconductor device component is consumed.
Tape automated bonding (TAB) processes, which employ a tape including a dielectric film with conductive traces extending thereacross, have also been used to electrically connect semiconductor devices to other semiconductor device components. Tape automated bonding is useful for forming very thin assemblies of semiconductor devices and substrates.
While all of the bond pads of a semiconductor device may be simultaneously connected with a carrier substrate or another semiconductor device when both flip-chip type bonding and TAB are used, neither of these techniques addresses the need for assemblies of both minimal lateral dimensions and minimal thickness.
Circuit boards are often assembled with semiconductor devices to electrically connect different semiconductor devices to one another or to other components of an electronic device. Typically, circuit boards have one or more layers of metal circuitry carried by the insulating, or dielectric, substrates thereof. When circuit boards have conductive circuits extending across more than one plane thereof, the circuits may be electrically connected by way of through holes that are metal plated or filled.
Typically, reinforced polymeric materials are employed as the dielectric substrates of rigid circuit boards. The most commonly used dielectric substrate material is glass-reinforced epoxy. Some circuit boards are made from polyimide resins so as to withstand higher temperatures. Other dielectric materials have also been developed and used to fabricate the dielectric substrates of circuit boards.
Some applications require that the dielectric substrate of the circuit board bend or flex during assembly of the circuit board with semiconductor or other electronic devices or while a device including the circuit board is being used. While some flexible circuit boards have substrates fabricated from flexible dielectric materials that are reinforced with woven or random fibers, unsupported polymeric films may also be used to form the substrates of flexible circuit boards.
Conventional printed circuit boards having a single-layered substrate are machined to define the edges thereof, to bevel the edges thereof, and to form through holes at desired locations. Metal conductive circuits are then formed on one or both surfaces of the printed circuit boards, in communication with metal plating or vias located in the through holes. Originally, conductive materials, such as silver, were printed onto the substrate to form the metal conductive circuits and to plate the through holes or to form vias therein.
Copper-clad laminates, which include a layer of copper secured to a dielectric substrate, can also be used to fabricate circuit boards. Copper is removed from regions of the surface of the substrate where conductive circuits are not desired. Accordingly, the process is referred to as a xe2x80x9csubtractivexe2x80x9d technique.
Other conventional techniques for forming metal conductive circuits and plating or filling the through holes include electroless plating, electrolytic plating, and plasma-assisted chemical vapor deposition (xe2x80x9cCVDxe2x80x9d) processes. Etching processes may also be used to pattern the conductive circuits of printed circuit boards. As the metal circuits, plating, or vias are formed on the substrate, these processes are referred to as xe2x80x9cadditivexe2x80x9d techniques.
The substrates of state of the art circuit boards have multiple, laminated layers. The conductive circuits of these circuit boards laterally traverse the surfaces of the boards, as well as several different planes through the interior of the substrate to accommodate the increasingly complex semiconductor devices connected to the substrate while maintaining or decreasing the size of the circuit board. In manufacturing such boards, circuit traces are fabricated, as noted above, on one layer of the substrate prior to laminating the next layer of the substrate thereto. Thus, laminated circuit boards are built up, layer by layer. The use of conventional processes to fabricate multilayer circuit boards is, however, somewhat undesirable since each new layer must be aligned with every previously formed layer of the circuit board to provide the desired functionality.
Completed circuit boards may then be tested. Optical or electrical testing may be conducted to determine whether the circuit boards will function properly.
Circuit boards are typically fabricated on a very large scale, with sheets of several circuit boards typically being supplied to semiconductor device manufacturers or electronic device manufacturers for assembly with semiconductor devices and other electronic components. Conventional, large scale circuit board fabrication processes are typically not useful for fabricating prototype circuit boards.
When a new circuit board design is needed, a prototype circuit board is usually fabricated. Due to the complexity of state of the art semiconductor devices and electronic devices, the fabrication of prototype circuit boards is a very time-consuming process. Moreover, production scale circuit boards based on a certain prototype circuit board design may not provide the same electrical performance as intended.
Accordingly, there is a need for a method that can be employed to quickly fabricate simple and multilayered circuit boards in either very small numbers or very large numbers. There is also a need for a process for fabricating multilayered circuit boards that does not require repeated alignment of each of the new layers of the circuit board with the previously fabricated layers thereof.
In the past decade, a manufacturing technique termed xe2x80x9cstereolithography,xe2x80x9d also known as xe2x80x9clayered manufacturing,xe2x80x9d has evolved to a degree where it is employed in many industries.
Essentially, stereolithography as conventionally practiced involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation usually effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or xe2x80x9cslicedxe2x80x9d into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a partially consolidated, or semi-solid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer of the object being fabricated. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed, or a separate binder material may be employed to bond material particles to one another and to those of previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer that can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed may be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design is committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials, and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, preexisting object or component to create a larger product.
However, to the inventor""s knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment or enhance products including other, preexisting components in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results are required. In particular, the inventor is not aware of the use of stereolithography to fabricate intermediate conductive elements between semiconductor device components or on circuit boards. Furthermore, conventional stereolithography apparatus and methods fail to address the difficulties of precisely locating and orienting a number of preexisting components for stereolithographic application of material thereto without the use of mechanical alignment techniques or to otherwise assuring precise, repeatable placement of components.
The present invention includes stereolithographically fabricated intermediate conductive elements. Accordingly, the intermediate conductive elements of the present invention may have one or more layers of conductive material. In multilayer embodiments, the intermediate conductive elements have a plurality of superimposed, contiguous, mutually adhered layers of conductive material. Any known conductive material may be used to form the intermediate conductive elements of the present invention. Exemplary conductive materials include, without limitation, electrically conductive thermoplastic elastomers and metals.
The invention also includes semiconductor device assemblies with one or more semiconductor devices that are electrically connected to one or more other semiconductor device components, such as carrier substrates, leads, or other semiconductor devices, by way of the intermediate conductive elements of the present invention. These intermediate conductive elements are substantially carried upon the semiconductor device and the component to which the semiconductor device is connected. For example, when used to connect one semiconductor die to another semiconductor die, an intermediate conductive element of the present invention contacts a bond pad of the first semiconductor die, extends across a portion of the active surface of the first semiconductor die towards the second semiconductor die, extends over the active surface of the second semiconductor die, and contacts a corresponding bond pad of the second semiconductor die. As another example, when the intermediate conductive elements of the present invention are used to connect a semiconductor die to a carrier substrate, one end of an intermediate conductive element may contact a contact (e.g., a bond pad) of the semiconductor die, extend over an active surface of the semiconductor die, down a peripheral edge thereof, and over a surface of the carrier substrate, and contact a contact pad of the carrier substrate at a second end of the intermediate conductive element.
In another aspect, the present invention includes a printed circuit board with a substrate that carries one or more stereolithographically fabricated conductive traces. Each conductive trace may have one or more layers of conductive material. The conductive material may be, for example, a thermoplastic conductive elastomer or a metal.
According to another aspect of the present invention, the substrate of the printed circuit board has two or more superimposed, contiguous, mutually adhered layers of dielectric material. One or more of these layers of the substrate may be fabricated using stereolithography techniques. For example, each stereolithographically formed layer of the substrate may be defined by, first, forming a layer of unconsolidated (i.e., uncured or particulate) dielectric material, then consolidating (i.e., curing or bonding particles) of the dielectric material in selected regions of the layer. Alternatively, each of the layers of the substrate may be fabricated by spraying dielectric material so as to define the desired configuration of the layer, permitting the dielectric material to at least partially harden or solidify, then using the same technique to form and stack one or more additional layers of dielectric material to complete the substrate.
When both the intermediate conductive elements and the substrate are fabricated by stereolithographic techniques, layers of the intermediate conductive elements and of the substrate residing in the same planes can be fabricated substantially simultaneously or sequentially.
The materials of both the intermediate conductive elements and the substrate may be either rigid or flexible. Accordingly, the methods of the present invention can be used to fabricate both rigid and flexible circuit boards.
The stereolithography, or xe2x80x9clayered manufacturing,xe2x80x9d processes that are used to fabricate the intermediate conductive elements or circuit board substrates of the present invention are initiated and controlled by a 3-D CAD-programmed computer.
When stereolithography is used to fabricate intermediate conductive elements between assembled semiconductor device components, the stereolithographic method of fabricating the intermediate conductive elements of the present invention preferably includes the use of a machine vision system to locate the assembled semiconductor device components on which intermediate conductive elements are to be fabricated, as well as the various features of the semiconductor device components. The use of a machine vision system directs the alignment of a stereolithography system with each substrate or layer for material disposition purposes. Accordingly, the assembled semiconductor device components need not be precisely mechanically aligned with any component of the stereolithography system to practice the stereolithographic embodiment of the method of the present invention.
As noted previously herein, in a preferred embodiment, the intermediate conductive elements of the present invention are preferably fabricated using three-dimensional printing techniques, wherein a conductive material having the desired properties and that is solid at ambient temperatures is heated to liquify same. Exemplary materials that are useful for forming intermediate conductive elements according to the present invention include thermoplastic conductive elastomers and metals. The liquified conductive material is then disposed, in a precisely focused spray (e.g., through an ink jet type nozzle) under control of a computer and, preferably, responsive to input from a machine vision system, such as a pattern recognition system, to form a layer of each of the intermediate conductive elements. The conductive material is then permitted to at least partially harden.
A circuit board substrate may be similarly manufactured, except with a dielectric material rather than a conductive material. Alternatively, other stereolithographic processes may be employed to fabricate the substrate. For example, the substrate may be fabricated using precisely focused electromagnetic radiation in the form of an ultraviolet (UV) wavelength laser to fix or cure selected regions of a layer of a liquid photopolymer material disposed on the semiconductor device or other substrate.
Other features and advantages of the present invention will become apparent to those of skill in the art through consideration of the ensuing description, the accompanying drawings, and the appended claims.
USPTO Backgrounds
USPTO Backgrounds