1. Field of the Invention
The present invention relates to a buffer apparatus with an insertion data control function, an insertion data controlling method, and a data insertion apparatus with data insertion control function. More particularly, the invention relates to a buffer apparatus with a data insertion control function, an insertion data controlling method, and a data insertion apparatus with a data insertion control function, all of which are suitable for insertion of different types of OAM (Operation, Administration, and Maintenance) cells, which are used in ATM (Asynchronous Transfer Mode), one communication system in broadband ISDN, into a transmission medium.
2. Description of the Related Art
In an ATM communication network, as is well known, ATM cells (OAM cells) are generated according to purposes, such as maintenance, administration, and control of the network. In insertion of the generated cells into an ATM communication highway (transmission medium), a buffer is used to wait an idle cell available for the insertion so as to avoid erroneous modification to a user communication cell (user cell).
Suppose that generated (to be inserted) are different types of ATM cells [such as AIS (Alarm Indication Signal) cell, FERF (Far End Receive Failure) cell, RDI (Remote Defect Indication) cell, and LB (Loop Back) cell]. In such a case, there is a possible method in that, as shown in FIG. 27, insertion buffers 20-1 to 20-n are prepared corresponding to cell types #1 to #n (where n: natural number of 2 or more, and of the order, at most, of 10 or less with the current state of the art), and are connected in parallel with an ATM communication highway 5, thereby carrying out the cell insertion.
In FIG. 27, reference numerals 6-1 to 6-n denote cell information generating sections for generating information for the cell types (OAM cell types) #1 to #n (hereinafter referred to as cell generating information), and reference numerals 7xe2x80x2-1 to 7xe2x80x2-n denote cell assembling/inserting sections for assembling cells of the cell types #1 to #n from information generated in the cell information generating sections 6-1 to 6-n to be temporarily held in the insertion buffers 20-1 to 20-n, and inserting the resultant cell into an idle portion of a cell flow on the ATM communication highway 5.
A more specific description will now be given of the operation of the buffer apparatus shown in FIG. 27. The cell assembling/inserting section 7xe2x80x2-i (where i: 1 to n) keeps monitoring whether or not an idle cell (insertable slot) is available on the ATM communication highway 5, and finds the idle cell to post a message to this effect (insertability information) to the corresponding insertion buffer 20-i.
The insertion buffer 20-i receiving the message transfers, if cell generating information waiting insertion is held therein, cell generating information of cell type #i (hereinafter referred to as cell generating information #i) to be subsequently inserted to the posting cell assembling/insertion section 7xe2x80x2-i. In such a way, the cell assembling/insertion section 7xe2x80x2-i assembles an ATM (OAM) cell of cell type #i (hereinafter sometimes described as cell #i) from the cell generating information #i received from the insertion buffer 20-i, and changes the idle cell into the assembled cell #i, thereby carrying out the cell insertion into the ATM communication highway 5.
That is, in the device shown in FIG. 27, the cell assembling/insertion sections #i carry out the cell insertion sequentially from the upstream of the ATM communication highway 5 (from the left-hand side of FIG. 27).
Next, a detailed description will now be given of a configuration of the insertion buffer 20-i. Suppose that input (stored) is only one cell type (cell generating information) #i, and only one output line [physical line (associated with, for example, an ATM exchange)] is handled by the ATM communication highway 5. In this case, as shown in FIG. 28, each insertion buffer 20-i includes a memory 201 of FIFO (First-In First-Out) type in which write and read addresses can be administered by simple increments of read and write pointers.
In the insertion buffer 20-i, when the cell generating information #i is input from the cell information generating section 6-i, the cell generating information #i is written on an address area (shown by reference numeral a6 in FIG. 28) indicated by the write pointer, thereafter incrementing the write pointer. On the other hand, when idle cell (insertability) information is received from the cell assembling/insertion section 7xe2x80x2-i, the contents (cell generating information #i) of an address area (shown by reference numeral a2 in FIG. 28) pointed by the read pointer are read and transferred to the cell assembling/insertion section 7xe2x80x2-i, thereafter incrementing the read pointer. As a result, the written information are read out sequentially from first one, and are sequentially transferred to the cell assembling/insertion section 7xe2x80x2-i.
If input is one cell type (cell generating information) #i and a plurality of output lines (L output lines, where L: natural number of 2 or more) are handled, a band control is needed for each line so that the insertion buffer 20-i must be operated independently for each line. However, a mass memory is required to mount for each line the memory 201 described with reference to FIG. 28. For multiple line effect, it is general to employ a shared buffer configuration in which an insertion buffer memory 202 is shared by the lines as shown in FIG. 29.
In FIG. 29, reference numeral 203 denotes an idle address administration section, 204 is a pointer chain memory, and 205 is a buffer controller. In this case, at least, the pointer chain memory 204 has the same address configuration as that of the insertion buffer memory 202. Further, the buffer controller 205 controls I/O of the insertion buffer memory 202 according to a pointer chain system using the pointer chain memory 204.
A description will now be given of the write process to the insertion buffer memory 202. For example, when cell generating information #i for a line numbered 1 is input from the cell information generating section 6-i, the buffer controller 205 receives from the idle address administration section an address (for example, address a0) which is currently in an xe2x80x9cidlexe2x80x9d state, and writes the received cell generating information #i onto an area at the address a0. Subsequently, the idle address administration section 203 sets the used address a0 to a xe2x80x9cbusyxe2x80x9d state.
Next, since four (not zero) cells are stored for the line numbered 1, the buffer controller 205 changes to the current write address (a0) an address (a9) of the pointer chain memory 204 corresponding to a tail pointer (shown by reference numeral a9 in FIG. 29), thereby incrementing the number of stored cells (from 4 to 5). Simultaneously, the tail pointer is changed to the current write address (a0), thereby updating the tail side of the pointer chain.
That is, the buffer controller 205 writes the cell generating information #i onto a certain address area of the insertion buffer memory 202, thereafter writing the address (current write address) of the insertion buffer memory 202 at which the cell generating information #i is currently written onto the same address area of the pointer chain memory 204 as that of the insertion buffer memory 202 at which the previous write process was performed. Thus, the buffer controller 205 links, in a chain form, pointers (addresses) pointing respective write positions of the same buffer memory 202 at which the cell generating information #i are written to create a pointer chain.
If the number of stored cells is zero, the current write address becomes a starting point of the pointer chain. Consequently, the buffer controller 205 changes both a head pointer and a tail pointer to the current write address, and sets the number of stored cells to 1. In addition, when the idle address administration section 203 has no xe2x80x9cidlexe2x80x9d address, no write process is executed.
On the other hand, in the read process, suppose that, for example, idle cell information for a line numbered 2 is input from the cell assembling/insertion section 7xe2x80x2-i. In this case, since three (not zero) cells are stored for the line numbered 2, the buffer controller 205 reads the contents (cell generating information #i) of the insertion buffer memory 202 at an address (shown by reference numeral a2 in FIG. 29) pointed by the head pointer, and transfers the contents to the cell assembling/insertion section 7xe2x80x2-i. The read address (a2) is reported to the idle address administration section 203, and is put in the xe2x80x9cidlexe2x80x9d state.
Subsequently, the buffer controller 205 refers to data (shown by reference numeral a6 in FIG. 29) in the pointer chain memory 204 corresponding to the head pointer (a2) to set the data to a new head pointer, and decrements the number of stored cells (from 3 to 2), thereby updating the head side of the pointer chain. If zero is the number of cells stored for a line corresponding to the idle cell information, no read process is performed.
As set forth above, because the insertion buffer memory 202 is shared between the lines, even in the case of a plurality of output lines, it is possible to carry out the cell insertion independently for each of the lines while minimizing the amount of memory.
With the insertion buffer memory 202 shared between the lines, when the ATM communication highway 5 has only one congested line, the insertion buffer memory 202 may be occupied by cell generating information #i for the congested line, thereby causing inequality between the lines. In order to avoid such a phenomenon, there is one possible method in that an upper limit is set to the number of stored cells for each line, and the write process is stopped when the number of stored cells given for each line exceeds the upper limit.
However, in the device described with reference to FIG. 27, the idle cells on the ATM communication highway 5 are used sequentially from the upstream side. Hence, when excessive cell insertion is made by a cell assembling/insertion section 7xe2x80x2-i disposed in the upstream of the own cell assembling/insertion section 7xe2x80x2-i, no idle cell is available unless the insertion buffer 20-i disposed in the upstream of the own insertion buffer 20-i is freed (the number of stored cells being zero).
That is, according to the configuration as shown in FIG. 27, even with equal priority of insertion of each cell type #i into the ATM communication highway 5, higher priority is forcedly given to the cell type #i toward the farthest upstream (i.e., top priority being given to the cell type #1). As long as no congestion is caused on the ATM communication highway 5, the priority makes no major problem because the insertable idle cell is available for any cell type #i in a short time after the cell generating information is stored in the insertion buffer 20-i. However, in the event of the congestion on the ATM communication highway 5, all the insertable idle cells are used only for the cell type #i in the upstream so that the cell insertion can not be carried out by the insertion buffer 20-i disposed in the downstream, resulting in a possibility in that overflow may occur in the insertion buffer 20-i.
Meanwhile, when the cell type #i includes a PM cell, the PM cell is generally inserted into a last block (i.e., the block for the cell type #n in FIG. 27) for the following reason. The PM cell is inserted into connection in which the specified number of cells have been received. The receiving side compares the number of actually reaching (received) cells with information in the PM cell, thereby collecting statistical information such as bit error rate, cell loss ratio, and the number of erroneous insertions. If the PM cell is inserted into any intermediate block, another OAM cell is inserted in the next and later stages so that the receiving side may erroneously detect an error.
In this case, since almost all other OAM cells are typically generated in a cycle of one second, it is a substantially negligible to insert the PM cell into the last block as stated above as long as the number of support connections [the number of VCs (Virtual Channels) handled by the ATM communication highway 5] is small. This is because it is possible to substantially completely insert the PM cell within a period specified by M M+M/2 (where M: natural number such as 256, and 512) , that is, before M cells in a certain connection (VCI: Virtual Channel Identifier) are received, and M/2 cells in the same connection are thereafter received.
However, as typified by the Internet, rapid development of information society in recent years results in massive amounts of information in communication networks, and an increase in the number of support connections. Therefore, according to the configuration as shown in FIG. 27 in which the idle cells on the ATM communication highway 5 are used sequentially from the upstream, it is necessary to frequently execute the idle cell writing in the upstream, resulting in a longer time for the writing. Hence, it is very difficult to ensure the allowable insertion delay (=M/2) for the PM cell.
In view of the foregoing problems, it is an object of the present invention to provide a buffer apparatus with a data insertion control function, an insertion data controlling method, and a data insertion apparatus with a data insertion control function, all of which can control the insertion order in which different types of data (cells) equal in insertion priority are to be inserted into a transmission medium based on the order in which the data have been stored in the buffer, thereby always providing reliable data insertion in a minimum delay time.
According to a first aspect of the present invention, a buffer apparatus with a data insertion control function comprises: a plurality of buffers for holding different types of data which are to be inserted into a predetermined transmission medium and are equal in insertion priority; and a data insertion controller for controlling the data insertion order in which the different types of data are to be inserted into the transmission medium by controlling the read process order in which the different types of data are to be read from the buffers based on the write process order in which the different types of data have been stored in the buffers.
According to a second aspect of the present invention, a data insertion control method comprises the steps of: administering the storage order in which different types of data to be inserted into a predetermined transmission medium and equal in insertion priority are accumulated in a buffer; and controlling the data insertion order in which the different types of data are to be inserted into the transmission medium, based on the administered storage order.
With the buffer apparatus and insertion data insertion control method according to the first and second aspects of the invention, it is possible to arrange the insertion order in which data to be inserted in the transmission medium are inserted depending upon the write process (storage) order in which the different types of data are written. As a result, irrespective of the amount of data stored in each buffer for each data type, it is possible to surely insert, if data of every data type is to be stored, the data into the transmission medium within a time corresponding to a store time. It is thereby possible to always realize exact data insertion in a minimum delay time.
According to a third aspect of the present invention, a data insertion apparatus with a data insertion control function comprises: a plurality of buffers for holding different types of data, which are to be inserted into a predetermined transmission medium and equal in insertion priority; a common data inserting section shared by said plurality of buffers for receiving the data in said buffers, and inserting the data into said transmission medium; and a data insertion controller for controlling the data output order in which the data are to be output to said common data inserting section by controlling the read process order in which the different types of data are to be read from said buffers, based on the write process order in which the different types of data have been stored in said buffers.
With the data insertion device of the third aspect of the invention, it is similarly possible to surely insert data of any one of all the data types into the transmission medium within a time corresponding to a store time. It is thereby possible to always realize reliable data insertion in a minimum delay time. Further, since a data insertion block serves as a common data inserting section shared by the different types of data, it is unnecessary to prepare a dedicated data insertion block for each data type, resulting in great contribution to downsizing of the device.
USPTO Backgrounds
USPTO Backgrounds