1. Field of the Invention
The present invention relates to a scan path, and more particularly to a scan path provided in the periphery of an asynchronous RAM core.
2. Description of the Background Art
FIG. 20 is a block diagram showing a test method on a RAM which has been often used in a background art. A scan test is used as the test method.
Flip flops (represented as "FF" in figures) provided inside a semiconductor chip are replaced by scan flip flops (represented as "SFF" in figures) and the scan flip flops constitute a scan path. In FIG. 20, for example, logic units 80 and 81 and a RAM core 91 which is an asynchronous RAM are surrounded by the same scan path. The scan path receives test data in a form of scan-in signal SI which is a serial signal and outputs a test result in a form of scan-out signal SO which is a serial signal after test execution.
In FIG. 20, scan flip flops are provided both on the input and output sides of the asynchronous RAM core 91. The device including the RAM core 91 and the scan flip flops on the whole performs reading/writing operations as a synchronous (complete synchronous) RAM 92. When a scan test is performed, the test data and test result are propagated on the scan path constituted of the scan flip flops.
FIG. 21 is a circuit diagram showing a configuration of the scan path in the periphery of the RAM 91 in detail. Each of the scan flip flops consists of a pair of a selector which switches the input in response to a shift mode signal SM and a flip flop. Storing/reading operations of an output (test result) of the logic unit 80 are performed by the scan flip flops each consisting of a pair of a selector 10 and a flip flop 30, a pair of a selector 11 and a flip flop 31 or a pair of a selector 12 and a flip flop 32, all of which are disposed on the input side of the RAM 91. Storing/reading operations of an input (test pattern) of the logic unit 81 are performed by the scan flip flops each consisting of a pair of a selector 20 and a flip flop 40, a pair of a selector 21 and a flip flop 41 or a pair of a selector 22 and a flip flop 42, all of which are disposed on the output side of the RAM 91.
Selectors 50 to 52 selectively output either respective outputs of the flip flops 40 to 42 disposed on the output side or outputs of the RAM core 91. In execution of the scan test, a test-mode signal TEST is set to "1", and in a normal operation, it is set to either "1" or "0". In the execution of the scan test, the RAM 92 performs both the reading and writing operations in a synchronous mode. On the other hand, in the normal operation, the RAM 92 performs the reading operation in an asynchronous mode and the writing operation in a synchronous mode.
In the configuration of FIG. 21, when the RAM 92 performs the reading operation in the asynchronous mode (the test-mode signal TEST is "0"), the flip flops 40 to 42 disposed on the output side are used only during the test. That raises a problem of poor area-efficiency (area overhead).
USPTO Backgrounds
USPTO Backgrounds