The present invention relates to a semiconductor processing method and structure, and more specifically to a notched gate field effect transistor having a plurality of different material semiconductor layers in which an underlying layer is etched selective to a material of an overlying layer to create a notched gate transistor structure for enhanced performance.
A metal oxide semiconductor field effect transistor (MOSFET) includes an insulated gate having one or more gate conductor layers overlying a gate dielectric layer, over a substrate of single crystal semiconductor. The gate conductor usually includes a layer of polysilicon material, and the gate dielectric layer is often composed of an oxide such as silicon dioxide when the substrate is silicon. A metal silicide layer is usually formed over the polysilicon layer to reduce the resistance of the gate conductor. Sometimes an overlying metal layer (e.g. tungsten) forms part of the gate conductor.
The MOSFET is electrically isolated from other integrated circuit devices within the semiconductor substrate by isolation structures, e.g. shallow trench isolations. The area between shallow trench isolations determines the active device area within the semiconductor substrate in which MOSFETs, and possibly other devices are fabricated.
On either side of the gates of MOSFETs, source-drain regions as well as source-drain extensions regions are formed within the substrate. The MOSFET source-drain extensions are shallow regions having shallow junctions to minimize short-channel effects. The source-drain extensions are usually lightly doped, as opposed to source-drain regions, which are more heavily doped regions. In general, doped regions are regions that contain a higher concentration of P-type or N-type dopants than the substrate.
An important objective, long recognized in the advancement of integrated circuit (IC) technology, is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces component and signal line capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions and create even smaller MOSFET designs as a basic building block of the IC. As the dimensions of MOSFETs are scaled down to tens of nanometers, however, the parasitic capacitance due to overlap of the gate dielectric over the drain extension and the source extension, known as the “Miller capacitance, becomes significant in limiting the speed performance of the MOSFET, as is known to those skilled in the art. As one way of solving this particular problem, notched gate structures are formed. MOSFETs having notched gates have gate conductors in which a lower layer is etched to become narrower. In such manner, the length of the transistor channel is reduced, thereby leading to increased on current and improved device performance.
A problem often encountered in the fabrication of notched gate structures, however, stems from the issues created when the length of gate conductor is reduced. Since the width of the gate conductor determines the corresponding length of the transistor channel, the transistor channel length when reduced horizontally, is also reduced in the vertical direction. Accordingly, the vertical thickness of the shallow source-drain extension regions must also be reduced. However, controlling the vertical thickness of the shallow source-drain extensions requires precise control of dopant distribution on a fine scale, which is becoming prohibitively difficult within the limitations and reliability considerations for the design of notched gate and other gate conductor structures.
In most instances, the design of notched gates is dependent on the reliability of the gate dielectric that is used. Unfortunately, the available gate dielectrics are not proven to be reliable to provide consistent and uniform dielectric strength, low leakage, and protection against premature breakdown. Therefore, a new structure and method is sought for providing MOSFETs having notched gates.
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