1. Field of the Invention
The present invention relates to a semiconductor testing jig and a semiconductor testing method performed by using the same.
2. Background Art
According to technique generally employed for measurement of the electrical characteristics of a semiconductor wafer or a semiconductor chip, for example, a surface of a measurement target where the measurement target is to be placed on a chuck stage is fixed under suction to the chuck stage. If the measurement target is a vertical semiconductor that flows a current in the vertical direction, namely, in the out-of-plane direction of the measurement target, how tightly the measurement target and the chuck stage contact each other affects a contact resistance, and eventually, affects the electrical characteristics of the measurement target.
However, increasing the tightness of contact for reducing the contact resistance, namely, increasing a degree of vacuum of the vacuum suction in turns degrades electrical characteristics. If a foreign matter such as dust exists on the chuck stage, the measurement target is placed on the foreign matter and the surface of the measurement target where the measurement target is placed on the chuck stage is pressed strongly against the foreign matter under vacuum suction. If the foreign matter has a large size, a defect such as a crack is generated in a contact part with the measurement target and the vicinity of the contact part, so that the measurement target is damaged partially. The damaged measurement target is counted as a defective. Meanwhile, even if the foreign matter has a relatively small size such as tens of μm or less that is hard to recognize visually, distortion due to pressure is still generated in the measurement target in the contact part with the measurement target and the vicinity of the contact part. This generates the piezoelectric effect to increase a leakage current, so that the measurement target is also counted as a defective (see Japanese Patent Application Laid-Open No. 2008-4739).
For purposes such as enhancement of electrical characteristics, reduction of the thickness of a semiconductor wafer has been in progress in recent years. The semiconductor wafer is held on the chuck stage under vacuum suction through a vacuum suction groove formed in the chuck stage. Increasing a degree of vacuum of the vacuum suction sucks the semiconductor wafer easily into the vacuum suction groove, especially if the semiconductor wafer is a thin wafer. Hence, part of the thin wafer existing near the vacuum suction groove is deformed to generate distortion. If a contact probe to make electrical contact for measuring electrical characteristics is brought into contact with the semiconductor wafer existing on the vacuum suction groove, the semiconductor wafer is also deformed due to contact pressure from the probe, thereby generating distortion.
Japanese Patent Application Laid-Open No. 2008-4739 describes technique as a remedy for increase of a fraction defective due to a foreign matter on the chuck stage. According to this technique, a stress buffering film is provided on the rear surface of a semiconductor substrate to relax stress applied by the foreign matter. Japanese Patent Application Laid-Open No. 2011-49337 also describes technique of providing a conductive and elastic sheet on the rear surface of a semiconductor substrate, and removing the sheet after manufacturing steps and evaluating steps.
According to the techniques described in Japanese Patent Application Laid-Open Nos. 2008-4739 and 2011-49337, a film or a sheet is provided on a semiconductor substrate targeted for a test of electrical characteristics by a semiconductor testing device to relax stress on the semiconductor substrate due to a foreign matter, thereby reducing a fraction defective. Providing the film or the sheet for stress relaxation also makes it possible to alleviate deformation of a semiconductor wafer due to the vacuum suction groove.
However, providing a film or a sheet to all semiconductor substrates targeted for measurement leads to the problem of cost increase as it involves more manufacturing steps and an additional material.
Reducing the width of the vacuum suction groove may be a different way of suppressing distortion of a semiconductor substrate. However, the minimum possible width is about some hundred micrometers in consideration of restraints on processing of the vacuum suction groove. So, the width cannot be reduced sufficiently enough to suppress deformation especially of a thin semiconductor wafer. Additionally, reducing the width of the vacuum suction groove is additional work on an existing check stage, so that it involves interruption of a testing step and eventually, interruption of manufacturing steps. This acts disadvantageously in terms of cost.
USPTO Backgrounds
USPTO Backgrounds