1. Field of the Invention
This invention relates to a device for control of a reference voltage generation circuit. More precisely, this control device is a means of switching reference voltages as a function of a logical control signal, to be applied particularly as cascode transistor bias voltages in a high voltage level translator.
2. Description of Related Art
One example application relates to integrated circuits comprising non-volatile electrically programmable memories.
These memories are programmed using a voltage higher than the logic power supply voltage Vcc of the integrated circuit. The nominal value of this high programming voltage depends essentially on the technology considered.
This high voltage is usually applied to an element of the integrated circuit, for example a memory row, using a high voltage translator, also called a level translator.
This translator receives a logical control signal and a high voltage input as inputs. Either the ground or the high voltage input level will be obtained at the output from the translator, depending on the logical level Vcc or 0 of the logical control signal, which in the case of a memory will be derived from a write control signal. These translators are well known to those skilled in the art.
These translators usually comprise an intermediate stage, between the high transistors stage and the low transistors stage. This intermediate stage comprises one or several cascode stages. It limits voltage at internal nodes in the translator to intermediate levels, such that no transistor in the translator will have an excessively high voltage applied to its terminals.
One example of a translator with this type of cascode stage using the CMOS technology is shown in FIG. 1.
In this example, the high stage comprises a P type MOS transistor M1 in the first branch, and a P type MOS transistor M2 in the second branch. The source of these transistors is connected to the high voltage input node EHV.
The low stage comprises an N type MOS transistor M3 in the first branch, and an N type MOS transistor M4 in the second branch. The source of these transistors is connected to the ground GND.
The cascode stage comprises four MOS transistors: two P type MOS transistors M5 and M6, one in each branch, under each high transistor and two N type MOS transistors M7 and M8, one in each branch above each low transistor. The reference voltage VREFP is applied to the grid of P MOS transistors M5 and M6. The reference voltage VREFn is applied to the grid of N MOS transistors M7 and M8.
The translator output VOUT is taken between the N and P cascode transistors of one branch, at the drains of transistors M6 and M8 in the example.
The grid of the low transistor M3 of the first branch of the translator receives a logical switching signal denoted IN, and the grid of the low transistor M4 of the second branch of the translator receives the inverse signal denoted /IN.
The role of the cascode stage is to limit voltages applied to transistors in the translator to intermediate levels.
Cascode transistors in a translator are usually biased by logic power supply voltages VCC (N MOS cascode transistors) and GND (P MOS cascode transistors). In other translators they are biased by reference voltages VREFn, VREFP generated from the high voltage.
In French patent application No. 99 09970 deposited on Jul. 30, 1999, it is shown that neither of the two bias modes is satisfactory. If the translator is not used, the standby level of the high voltage node EHV is less than or equal to VCC. The high voltage is applied in the form of a voltage ramp that moves the high voltage node from its standby value to a nominal high voltage value, VPP. Thus, the voltage level at node EHV is firstly less than or equal to the logic power supply voltage level VCC and then increases to become equal to its nominal value VPP. Regardless of the method chosen to bias the cascode transistors, this bias is fixed and determined. The application shows that the bias of the cascode transistors then has an influence on the operating range of the translator, or on the stress of the translator transistors, related to the increase in voltage on the high voltage node EHV.
In the application mentioned above, and as shown in FIG. 1, a control device is provided comprising a voltage reference circuit REF and a control circuit COM, so as to obtain voltage references as a function of the level of the high voltage input EHV. This control device is applied to the high voltage translator to make the translator switch over in the low values of the high voltage input (standby level), by switching reference voltages equal to the logic power supply voltages VCC and GND, as cascode transistor bias voltages. Once the transistors have switched over, the level of the high voltage input may increase to its nominal value VPP at no risk for the translator transistors. The control device then switches the reference voltages VREFn, VREFP defined by putting the transistors in the reference circuit mounted as a diode between the high voltage node and the ground in series, as the bias voltages for the cascode transistors.
The translator output then follows the increase in voltage of the high voltage input EHV with the advantages of a bias of cascode transistors by the reference voltages VREFn, VREFP. As long as node EHV remains at its nominal value VPP, the translator can switch over in one direction or the other, with these bias voltages. As soon as node EHV returns to its standby level, VCC in the example, the voltages VCC and GND are applied as the bias voltages. Thus, the translator operating window is made wider (switching at low voltage) and its translators are no longer subjected to any stress due to the high voltage node changing from its standby position, VCC in the example, to its nominal value VPP. 
As shown in detail in FIG. 1, according to the application mentioned above, the circuit REF also comprises three P type MOS transistors M12, M13 and M14 connected in series between the node N carrying the high voltage input EHV and the ground GND. The grids of the first and third transistors M12 and M14 are each connected to their drain. The second transistor M13 is controlled through a control circuit COM. Its drain and its source supply a first reference voltage VPOL1 and a second reference voltage VPOL2 respectively. These voltages are applied in the example as bias voltages for the cascode transistor grid in the high voltage translator.
The control circuit COM controls the grid, drain and source voltage of the second transistor M3 as a function of the level of a control signal /WR.
Operation of this type of control device is shown in FIGS. 2 and 3, in an example in which the standby level of the high voltage input EHV is VCC.
When the control signal /WR is at a first logical level, “1” in the example, the transistor M13 is blocked and its drain and its source are forced to VCC and GND respectively, by means in the control circuit COM. We then have VPOL1=VCC and VPOL2=GND. 
When the control signal /WR is at the second logical level, “0” in the example, the drain and grid of transistor M13 are connected together such that it is installed as a diode, like the other two transistors M12 and M14 in the reference circuit. These reference transistors M12, M13 and M14 in the reference circuit then set up voltage levels at nodes A and B, depending on the level on the high voltage input EHV. The result is then VPOL1=VREFn and VPOL2=VREFP.
Thus, the different reference voltages are switched depending on the level of the logical control signal /WR. In the example of an application to the bias of cascode transistors of a high voltage translator, the first operating mode (/WR equal to “1”), corresponds to the high voltage input at its standby level, VCC in the example, and the second operating mode (/WR equal to “0”) corresponds to the high voltage input increasing to its nominal value VPP. 
The control circuit COM comprises mainly four MOS transistors M15, M16, M17 and M18 as shown in FIG. 1.
The P type MOS transistor M15 is connected between the logic power supply voltage VCC and the first intermediate node A in the reference circuit REF connected to the source of transistor M13.
The N type MOS transistor M16 is connected between the second intermediate node B in the reference circuit connected to the drain of transistor M13, and the ground GND. 
The P type MOS transistor M17 is connected between the logic power supply voltage VCC and the grid of transistor M13.
The transistor M18 is connected between the grid and the drain (node B) of the second transistor M13.
The transistors M16 and M18 are controlled on their grid by the logical control signal /WR of the control circuit and the transistor M15 is controlled by a signal VNP referenced to the high voltage input VNP and output from the signal /WR and with inverse logic.
The grid of transistor M17 is connected to the second intermediate node B.
This control circuit operates as follows:
When the /WR signal is equal to “1”, transistor M16 is conducting and pulls the second intermediate node B to zero, and consequently also pulls the grid of transistor M17.
Transistor M18 is blocked. Transistor M17, that is conducting, carries the voltage VCC to the grid of transistor M13, which is then forced into the blocked state.
Transistor M15 is also conducting, since the signal VNP has the inverse logic to signal /WR. Therefore, it carries the voltage VCC to the first intermediate node A.
Since transistor M13 is forced to the blocked state by transistors M16 and M17 in the control circuit, the intermediate nodes A and B are consolidated at their levels VCC and GND respectively, regardless of the voltage level on the high voltage input.
When the signal /WR changes to “0”, corresponding to an increase in the voltage of the high voltage input EHV from VCC to its nominal value VPP, transistors M15 and M16 change to the blocked state and consequently transistor M17 changes to the blocked state as well. Transistor M18 becomes conducting and actively connects the grid of transistor M13 to the second intermediate node B, in other words to its drain. Transistor M13 is then connected as a diode like the other transistors M12 and M14 in the reference circuit. The result is normal operation of the reference circuit; voltages at nodes A and B follow the rise in voltage of the high voltage input EHV.
Since the transistor M15 in the control circuit is connected between the logic power supply voltage VCC and node A, and transistor M12 in the reference circuit is connected between the high voltage input EHV and node A, when this high voltage input EHV reaches high values, it is important to be sure that transistor M15 is actually blocked, to avoid sending the high voltage to the logic power supply voltage VCC.
This is why transistor M15 must receive the voltage output from a high voltage input EHV on its grid and not the high level corresponding to the logic power supply voltage VCC. When the high voltage input reaches its nominal value VPP, this value VPP also appears on the grid of transistor M15.
This is obtained in the example by means of an inverter circuit with three MOS transistors. A first P type MOS transistor M19, a second N type MOS transistor M20, and a third N type MOS transistor M21, are connected in series between node N carrying the high voltage input EHV and the ground GND. 
Transistor M21 is controlled on its grid by the /WR control signal.
The grids of transistors M20 and M19 are connected together to the first intermediate node A;
The inverse logical signal VNP referenced to EHV by the inverter is supplied by the serial connection point between the two transistors M19 and M20. This is the signal applied to the grid of transistor M15.
Operation is as follows: when the /WR binary signal is equal to 1, transistor M21 is conducting and connects transistor M20 to the ground. Node A is at VCC. Since the high voltage input EHV is then at its low voltage standby level (in the example equal to VCC, see FIGS. 2 and 3), and therefore transistor M19 is blocked. Transistor M20 is conducting. Therefore, the voltage on the grid of transistor M15 is equal to 0: VNP=0.
The sizes of MOS transistors 19, 20 and 21 are such that, even if the value of the high voltage input EHV is greater than VCC, VNP remains below VCC−Vtp, such that the translator operates even for high values of the high voltage input (in other words it can flip over).
When the /WR binary signal is equal to “0” and the high voltage input EHV rises from VCC to VPP, transistor M21 is not conducting and the transistor M20 source is put to a floating potential.
The potential VNP is not pulled to the ground. Therefore, transistor M15 is blocked. If input EHV is equal to VPP, node A is biased by transistor M12 at a voltage less than VPP−Vtp. Transistor M19 is conducting and VNP is pulled to VPP. The stable position is given by VNP=VPP, with M15 blocked and VREFn is less than VPP−Vtp.
One problem with this control device is due to the complex control of transistor M15, requiring three transistors M19, M20 and M21 to reliably block it or to make it conducting, depending on the /WR control signal.
One purpose of the invention is to reduce the number of transistors in the control circuit while maintaining the function of the control device, in other words a reference voltage source.
USPTO Backgrounds
USPTO Backgrounds