The semiconductor industry has seen tremendous advances in technology in recent years that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of several gigahertz (GHz), to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high density and high functionality in semiconductor devices has been an ongoing pressure to further miniaturize the individual circuit features within an integrated circuit and packaging substrate, such as a microprocessor or a chip set component or the like.
There are many different features within an integrated circuit packaging substrate. One feature is a via. An integrated circuit packaging substrate contains several levels of circuitry. A via is a vertical opening filled with conducting material used to connect conductor trace on one layer to the next layer. Vias can also provide conductive paths from a layer of integrated circuit to the exterior of the package. As vias are made smaller, there are some occurrences where the structure within the via fails to provide an electrical connection. This is the type of failure that may not occur immediately. Rather, this type of failure may occur after the integrated circuit within a die has been packaged and shipped. One form of this type of failure is delamination of the via structure. This may be due to excessive mechanical stress, contamination of dielectric residues trapped from laser drilling of the via opening, or sulfur contamination on electroless copper (Cu) plating.
The description set out herein illustrates the various embodiments of the invention, and such description is not intended to be construed as limiting in any manner.
USPTO Backgrounds
USPTO Backgrounds