To produce MOSFET as one example of the MOS type semiconductor device, for example, p base regions are formed by diffusing impurities into selected areas of a surface layer of an n type semiconductor substrate such that pn junctions are exposed onto the surface of the substrate, and n source regions are similarly formed in surface layers of the p base regions. A gate electrode layer is then formed on an insulating film over surfaces of channel regions provided by surface layers of the p base regions each interposed between the adjacent n source region and the n type semiconductor substrate, and a source electrode is formed in contact with both of the p base regions and n source regions. A drain electrode is formed on the other surface of the n type semiconductor substrate. By applying a suitable voltage to the gate electrode, an inversion layer appears in each channel region, to reduce resistance between the drain electrode and the source electrode, and current is allowed to flow between the drain electrode and the source electrode through the inversion layer.
To produce IGBT as another example, an additional p type region is formed on one side of the MOSFET where the drain electrode is formed. With the p type region thus added, the IGBT is capable of modulating the conductivity by utilizing injection of minority carriers from the p type region.
The MOS type semiconductor device as described above is widely used in a switching circuit because the device has low ON-state resistance and high switching speed, and is easy to be controlled by use of voltage.
In recent years, the MOS type semiconductor device used as a switching device in a switching circuit is more likely to receive surge voltage, which may be generated due to simplified configuration of the switching circuit from which snubbers are eliminated, for example, and reduction in the size of the semiconductor device. In a circuit in which inductive load current is to be cut off, for example, the voltage applied to the MOS type semiconductor device is increased due to energy stored in an inductor, and sometimes becomes even higher than power supply voltage. This excessive voltage stress may cause breakdown of the MOS type semiconductor device, and it has been thus desired to increase the breakdown voltage (avalanche current) of the semiconductor device.
As one method for improving the capability of the MOS type semiconductor device to withstand avalanche breakdown, a part of the p base region is formed with a larger diffusion depth. The increase in the diffusion depth, however, affects the ON-state resistance and other characteristics of the semiconductor device. For example, if the depth of a part of the p base region is changed from 5 .mu.m to 7 .mu.m in a certain MOSFET, the avalanche current increases by 25%, but at the same time the ON-state resistance increases by 15%. Thus, this method is not altogether desirable.
FIG. 11 is a cross-sectional view of MOSFET (as disclosed in U.S. Pat. No. 5,365,099) that employs another method for increasing the breakdown voltage.
An ordinary MOSFET is shown in the left-side portion of FIG. 11. In this MOSFET, an n drift layer 13 is superposed on an n.sup.+ drain layer 11, and a plurality of p base regions 14 and p.sup.+ contact regions 15 inside the regions 14 are formed in a surface layer of the n drift layer 13. Further, n source regions 16 are formed in surface layers of the p base regions 14. A gate electrode layer 18 made of polycrystalline silicon, for example, is formed on a gate oxide film 17 over portions of the p base regions 14 that are interposed between the n source regions 16 and an exposed face of the n drift layer 13. A source electrode 19 made of Al alloy is formed in contact with both the p base regions 14 (p.sup.+ contact regions 15) and the n source regions 16. The source electrode 19 extends over the gate electrode layer 18 such that these electrodes 18, 19 are insulated from each other by an interlayer insulating film 21 made of boron phosphorous silica glass (BPSG). A drain electrode 20 made of Al-Si alloy is formed on the rear surface of the n.sup.+ drain layer 11. A unit structure having n source region 16, source electrode 19 and other elements above and below the p base region 14 will be called a cell structure. The cell structure is often formed in polygonal or rectangular shape, and a multiplicity of such cell structures are arranged in parallel with each other in an actual MOSFET.
A means for increasing the avalanche current is illustrated in the right-side portion of FIG. 11. An n.sup.+ contact region 7 is formed in a surface layer of the n drift layer 13, and an auxiliary electrode 8 is formed in contact with the n.sup.+ contact region 7. An array of a plurality of pairs of Zener diodes 10 that are connected in series is provided on a relatively thick oxide film 9 on the surface of the n drift layer 13. Each pair of the Zener diodes are reversely connected to each other. The above auxiliary electrode 8 is connected to one end of the series Zener diode array 10, and an electrode taken out from the other end of the Zener diode array 10 is connected to the gate electrode layers 18 of the MOSFET.
In this structure, the auxiliary electrode 8 and drain electrode 20 are held at the same potential. When a voltage applied to the drain electrode 20 increases to be higher than a clamping voltage of the series Zener diode array 10, therefore, a difference between the high voltage and the clamping voltage is applied to the gate electrode layers 18 of the MOSFET, to turn on the MOSFET thereby to protect the device.
To provide the construction of FIG. 11, however, a window must be formed through the thick oxide film 9 so that the n.sup.+ contact region 7 is formed in the surface layer of the n drift layer 13, and the n.sup.+ contact region 7 must be given a sufficiently large area so as to assure reliable operations.
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