1. Technical Field of the Invention
The present invention relates to a liquid crystal display control circuit for controlling the display of a liquid crystal display.
2. Description of the Related Art
In recent years, liquid crystal displays (LCDs) are most widely used as display apparatuses in computers, office automation equipment, and mobile terminals. A prior art thin-film transistor (TFT) liquid crystal display in a computer is generally described below with reference to the drawings.
FIG. 1 shows the general configuration of a liquid crystal display system, while FIG. 2 shows signal waveforms at various points in the system.
As shown in FIG. 1, the liquid crystal display system comprises: a computer 7 for outputting digital display data (display data, hereafter) together with a clock signal and a control signal; a liquid crystal display 6; and a liquid crystal display control circuit 5 for inputting the signals which have been received from the computer 7 and thereby drive and control the liquid crystal display 6.
The liquid crystal display 6 comprises: a liquid crystal display panel 61 in which pixel electrodes for displaying and TFT transistors for applying a voltage on each pixel electrode are arranged in a matrix form on a substrate; a source driver 62 arranged on the top side of the liquid crystal display panel 61; and a gate driver 63 arranged on the left side. Display data latched by the source driver 62 on a per-horizontal-line basis is D/A-converted into gradation voltages. The gradation voltages are written into the pixel electrodes of the liquid crystal display panel 61 sequentially from top to bottom on a per-horizontal-line basis. Accordingly, the voltage for each pixel is applied between each pixel electrode and a common electrode. As a result, the transmissivity of the liquid crystal between each electrode pair is controlled in response to the applied voltage, whereby displaying is carried out.
The computer 7 comprising a graphic chip controller 71 processes image data and thereby outputs: display data segmented into each line; a single synchronization control signal (data enable signal, hereafter) DE in synchronization with the display data; and a dot clock signal DCK; through a bus to the liquid crystal display.
In response to the three signals (DATA, DE, and DCK), the liquid crystal display control circuit 5 generates various signals for the liquid crystal display 6, and thereby controls the source driver 62 and the gate driver 63. Accordingly, the drivers 62 and 63 drive the liquid crystal display panel 61.
Signal processing in the liquid crystal display control circuit and the drive method of the liquid crystal display are generally described below with reference to FIG. 2.
In FIG. 2, display data is display-use data of image data segmented into each line along the time axis. A dot clock signal DCK is a clock signal having the same data rate (repetition frequency) as that of the display data. A data enable signal DE is a synchronization control signal. In this signal, a data period for each line of the display data is indicated as a valid display data period by a high level, and a data intermission is indicated as an invalid period by a low level. Further, a frame intermission between the last line of a frame and the first line of the next frame is indicated by a low level at a longer time. That is, in the data enable signal DE, horizontal synchronization control is carried out in response to a rise from low to high, while vertical synchronization control is carried out in response to a long low level period. These signals are provided from the computer as described above.
The liquid crystal display control circuit 5 outputs: a reference signal HRST composed of a reference signal generated in response to the detection of a rise timing to the high level of the data enable signal DE in each line or a later-described dummy reference signal generated in the long low level period after the last line of a frame; a horizontal start pulse signal HSP which is generated after several dot clock signals in synchronization with the HRST and thereby controls the start of a horizontal scan; a horizontal clock signal HCK; and a vertical start pulse signal VSP of a vertical scan which is generated in response to the detection of a long low level period of the signal DE.
In each occurrence of a reference signal HRST, the time distance from the preceding reference signal HRST is measured, whereby the maximum time distance (maximum value) is successively renewed and stored. Then, the above-mentioned dummy reference signal HRST is generated when the next DE rise does not occur after the maximum value has elapsed after the tail edge of the last high level period of the DE signal of a frame.
The liquid crystal display control circuit 5 is reset by the reference signal HRST and the dummy reference signal HRST, and then, using a counter for counting the signal DCK, outputs: a vertical clock signal (gate clock signal) VCK generated slightly before a tail edge of the signal DE and thereby used for vertical synchronization; and a data latch pulse signal DLP generated slightly after a tail edge of the signal DE and thereby latching the display data on a per-line basis.
FIG. 3 shows a detailed example of a liquid crystal display control circuit for generating the above-mentioned signals. The circuit comprises: a rise detection circuit 21; a horizontal counter 22; a decoder 25; a TD value (maximum value) determination circuit for detecting the above-mentioned maximum time distance (maximum value); a coincidence detection circuit 27; and a data conversion circuit 30. The horizontal counter 22 is reset by the reference signal HRST outputted from the rise detection circuit 21 via an OR circuit 23, then counts the signal DCK, and thereby outputs the count value continuously. The TD value (maximum value) determination circuit comprises: a register 26 for latching the count value of the horizontal counter 22 at the time of an occurrence of the reference signal; a register 28 (having an initial value of zero) for retaining the maximum time distance data; and a greater value detection circuit 29 for comparing the outputs of the two registers and thereby renewing and retaining the greater value in the register 28; whereby the count value (maximum value) corresponding to the maximum time distance until that point is renewed and stored. When the count value in the horizontal counter 22 during a long low level period of the signal DE exceeds the registered data (TD value) in the register 28, the coincidence detection circuit 27 outputs a dummy reference signal HRST to the OR circuit 23. As a result, the OR circuit 23 outputs a signal HRST composed of the dummy reference signal. The count value outputted from the horizontal counter 22 during the above-mentioned operation is compared with a predetermined count value by the decoder 25, whereby the above-mentioned signals HSP, HCK, DLP, and VCK are outputted in synchronization with a rise timing of the signal DE. In synchronization with the dot clock signal DCK, the data conversion section 30 receives the above-mentioned display data which is 18-bit (6 bits×3) serial data composed of three pieces (for R, G, and B, respectively) of 6-bit data for each pixel. Then, the data conversion section 30 converts the display data into parallel data, and then outputs the data in synchronization with the horizontal clock signal HCK (see Japanese Unexamined Patent Publication No. Hei-10-301544).
The signal DCK is an external clock signal in synchronization with the display data inputted to the liquid crystal display control circuit 5, while the signal HCK is an internal clock signal in synchronization with the display data outputted from the liquid crystal display control circuit 5. The signal HCK is generated according to the signal DCK, in a form corresponding to an output display data form determined by the driver group configuration of the source driver and the input form for the source driver. The vertical clock signal VCK defines the pulse width of the gate drive signal outputted from the gate driver.
The source driver 62 and the gate driver 63 for the liquid crystal display panel 61 are controlled with the above-mentioned signals. The operations of the source driver 62 and the gate driver 63 are described below.
Using the horizontal start pulse signal HSP as a start (horizontal synchronization) signal, the source driver 62 sequentially reads DATA during a high level period of the signal DE according to the horizontal clock signal HCK. When data for one line has been read, the data is latched in an internal latching circuit according to the signal DLP, and then D/A-converted into gradation voltages in the number of pixels per line. The voltage signals are provided to the source wires of the corresponding TFT transistors. Such operation is repeated.
Using the signal VSP as a start (vertical synchronization) signal, the gate driver 63 outputs gate drive signals having the same pulse spacing as that of the vertical clock signal VCK, sequentially to the gate wires. Accordingly, TFT transistors for the line are driven sequentially, whereby the transistors for the line turn ON. Such an operation is repeated.
FIG. 4 shows signals for a driving operation of a specific gate wire and a specific source wire. The figure shows a data latch pulse signal DLP, a vertical clock signal VCK, a gate drive signal for the gate wire (a signal for controlling the gate-ON period), and the charging voltage (simply a data output, hereafter) for the source wire according to the data output (gradation voltage). The source driver 62 outputs the gradation voltage to the source wire during a DLP pulse spacing, while the gate driver 63 drives the gate wire during a VCK pulse spacing. The gradation voltage provided to the source wire serves as a charging voltage waveform for charging the source wire and the pixel electrode. The final charging voltage for the pixel electrode is the charging voltage at the tail edge of the gate-ON period. This voltage is retained to the next frame, and thereby determines the transmissivity of each pixel of the liquid crystal display panel.
As such, the period in which the source driver 62 reads one-line of data and thereby outputs them as the gradation voltages is the period from a DLP pulse after the reading of the one-line of data to the next DLP pulse. That is, the previous one-line data is written in a period overlapping the next line period. The signal DLP for defining the last timing of the output of the gradation voltage and the signal VCK for defining the tail edge of the gate-ON period are outputted by using rising of the signal DE as the reference and then counting the signal DCK. Thus, the dummy reference signal HRST is indispensable at the rise for the last line of a frame which has no next line.
Nevertheless, in a display data providing apparatus (such as a computer) which outputs display data for liquid crystal display by using a data enable signal DE, the process of converting image data into a per-line based display data corresponding to the resolution of the liquid crystal display panel can cause a delay in the line data spacing of the outputted display data, that is, a delay in a rise timing of the data enable signal DE (equivalently, the tail edge of a low level period). Further, the timing of the pseudo signal HRST (dummy signal HRST) generated in a long low level period for vertical synchronization in the data enable signal can suffer a delay relative to the preceding rise (HRST) of the signal DE in comparison with the other preceding HRST pulse spacing (see Japanese Unexamined Patent Publication No. Hei-10-301544).
As described above, the timing of generation of the signal HRST varies depending on the delay variations in the timing of a rise of the data enable signal DE and the timing of generation of the dummy reference signal HRST. This causes a delay in the timing of generation of the signals DLP and VCK, and thereby affects the displaying of the liquid crystal display panel.
FIG. 5 illustrates the mechanism of affecting the displaying of the liquid crystal display panel. As shown by the broken lines in FIG. 5, when a low level period for horizontal synchronization of the signal DE is extended, or when a delay occurs in the dummy reference signal HRST generated at a long low level period for vertical synchronization, the signals DLP and VCK also delay. As shown by the broken lines in FIG. 5, the delay in the signals DLP and VCK extends the duration of charging with the gradation voltage, and hence the ON-period of the TFT transistors. This causes a variation in the final charging voltage for each pixel electrode. This affects the transmissivity of the liquid crystal display panel, and thereby causes degradation in the display quality such as display inhomogeneity.
USPTO Backgrounds
USPTO Backgrounds