1. Field of the Invention
This invention relates generally to improved circuit configuration and methods for compensating for the junction leakage current of a semiconductor device and, more specifically, to a method and circuitry for compensating for the gate leakage current of junction field effect transistors.
2. Description of the Prior Art
With the advent of semiconductor devices, sophisticated electronic functions have been provided at extremely low cost. One of the major contributing factors to reducing cost is the ability to test and/or trim such devices before final assembly. Trimming enhances performance; pre-assembly testing eliminates defective or low-performance devices before additional costs are incurred.
A major reason for the utilization of the junction field effect transistor (JFET) is its very low input current, which arises from the reverse-bias junction leakage current of the gate which controls the output current of the device. This is in contradiction to a bipolar transistor, whose base input is forward biased at a current value which may be appreciable if the low current gain of the device is poor. This is a commonplace manufacturing problem involving cost-yield tradeoffs. By contrast, for JFETs the reverse-bias junction leakage can be made and maintained at an extremely low current value. Room temperature current values of one picoampere are routine in a JFET and even lower current values may be achieved.
A pronounced problem, however, is engendered in any reverse-bias JFET during higher temperature operation due to the doubling of leakage current for about every 10.degree. C. rise in temperature. Thus, the leakage at 0.degree. C. for reverse-biased JFETs becomes approximately 5700 times greater at 125.degree. C., for example.
While this dramatic increase in leakage current for reverse-biased junction type semiconductor devices is usually somewhat less troublesome in differential amplifier configurations, the mismatch in the input device leakage currents is similarly exacerbated by temperature rise, i.e. a 10% leakage mismatch between input devices having nominal one picoampere current leakage at 0.degree. C. will become a current leakage mismatch of almost 1 nanoampere at 125.degree. C.
In the past, it has been commonplace to reduce current leakage mismatch between JFETs over temperature by a priori compensation schemes, such as the use of a second reverse-biased JFET to compensate for the leakage of the input device or devices. This type of approach suffers from the same general problem as described above, viz, it is difficult to manufacture two reverse-biased JFETs with the same leakage current. Also known are various a posteriori compensation schemes, such as trimming active and/or concomitant passive devices (e.g. load elements) on the basis of measured current leakage values subsequent to initial fabrication, but prior to final device packaging. However, current wafer probe measurement techniques cannot accurately measure, and hence appropriately compensate for, leakage currents or leakage current mismatches on the order of 100 picoamperes or less. The ambient electrical noise and ambient light both contribute to this current leakage mensuration problem. Thus, a need exists for improved leakage current compensation techniques for small currents in reverse-biased JFETs such as junction leakage currents.
USPTO Backgrounds
USPTO Backgrounds