The present invention relates to a semiconductor integrated circuit composed of scaled MOS transistors, and more particularly to a circuit suitable for high-speed and low power operation and an electronic device using the same.
As the size of MOS transistors is scaled down, the breakdown voltage thereof is lowered as stated, for example, in the 1989 International Symposium on VLSI Technology, Systems and Applications, Proceedings of Technical Papers, pp. 188-192 (May 1989). Accordingly, the operating voltage thereof has to be lowered. In particular, the operating voltage is lowered even more for the purpose of achieving low power consumption for semiconductor devices used in a battery-operated portable equipment and the like.
USPTO Backgrounds
USPTO Backgrounds