This invention relates, in general, to microprocessor interface units, and more particularly, to an asynchronous microprocessor interface unit.
It is often desirable to operate a plurality of microprocessors with a single input/output (I/O) unit; or it may be desirable to operate a single microprocessor with a plurality of input/output devices. In such cases, it is preferred that some microprocessors have priority over other microprocessors or in the case where multiple input/output units are used it is desirable that some I/Os have priority over others. Interface units to accomplish the above have been available in the past; however, such interface units operated in a synchronous manner and were relatively slow in operation.
With the asynchronous operation, the system containing the interface unit adapts itself to receipt of the data, whereas, with synchronous operation the information must be in a form compatible with fixed timing characteristics.
Accordingly, it is an object of the present invention to provide a new and improved asynchronous interface unit useful with the operation of a microprocessor.
Another object of the present invention is to provide an improved asynchronous microprocessor interface unit which operates at relatively high speeds.
Yet a further object of the present invention it is to provide a microprocessor interface unit which is asynchronous in operation and does not use a synchronous device.
USPTO Backgrounds
USPTO Backgrounds