1. Field of the Invention
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a single chip semiconductor package and a method of manufacturing the same, and a stack-type semiconductor package comprising the single chip semiconductor package and a method of manufacturing the same.
2. Description of the Related Art
Packaging is the final stage in a semiconductor manufacturing process. Packaging electrically connects semiconductor chips to external devices, protects semiconductor chips from potential damage, and dissipates heat generated by semiconductor chips. The packaged semiconductor chip is then installed in an electronic device, such as a computer or mobile device.
Recent developments have made electronic devices smaller, lighter and thinner, while the devices are becoming higher performance. In order to meet these requirements, several methods of packaging have been introduced. Among them, a flip chip package (FCP) method, a chip scale package (CSP) method, and a multi-chip package (MCP) method are widely used. Recently, a wafer level package (WLP) method has been developed.
The multi-chip package comprises two or more semiconductor chips, which are packed together on a substrate. Multi-chip packages may also comprise different kinds of semiconductor chips. Chip arrangements for a multi-chip package include a planar arrangement and a vertically stacked arrangement. Vertical stacking is advantageous in chip scale packages (CSP) since it (hereinafter, stack-type chip semiconductor package) reduces semiconductor package area. However, thickness is a drawback in the stack-type chip semiconductor package. Therefore, it is desirable that the thickness of the stack-type chip semiconductor package be reduced.
Generally, in a conventional semiconductor package comprising bonding wires, a semiconductor chip is attached to a substrate with its active surface facing away from the substrate. Bonding wires electrically connect bonding pads formed on the active surface to connection terminals on the substrate or to leads of a lead frame. Since the wires protrude from the active surface of the semiconductor chip, and thus the substrate, reduction in thickness of the semiconductor package is difficult. For example, to avoid damage to the bonding wires of a lower semiconductor chip, a thick bonding material may provide an appropriate space between the lower semiconductor chip and an upper semiconductor chip. However, bonding material increases the overall thickness of the stack-type semiconductor package.
FIG. 1 is a cross-sectional view of a conventional stack-type chip semiconductor package. Referring to FIG. 1, using adhesives, two semiconductor chips 110 and 120 are attached to a substrate 100 where connection pads 102 are formed. Active surfaces of the semiconductor chips 110 and 120 face away from the substrate 100, and bonding pads are formed on the active surfaces. The bonding pads 112 and 122 are electrically connected to the connection pads 102 by bonding wires 124 and 114.
Referring to FIG. 1, the thickness of the adhesive 134 between the semiconductor chips 110 and 120 could be minimized by modifying the structure of the upper semiconductor chip 120, which in turn reduces the overall thickness of the semiconductor package. Since the wires of the upper semiconductor chip 120 protrude upwards however, a practical limit exists for reducing overall thickness of the semiconductor package.
USPTO Backgrounds
USPTO Backgrounds