The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of improving read performance for processor to system memory read transactions.
Today""s microprocessors continue to increase in processing power with every new generation of devices. In order to keep up with the increase in processing power of the processors and to avoid system bottlenecks, improvements must also be made to other subsystems within the computer system. One area where increased performance is desirable is the memory subsystem. In particular, it is desirable to improve the rate at which data can be retrieved by a processor from the computer system""s main memory. One way to improve memory subsystem performance is to reduce the number of clock cycles it takes for a memory read cycle to complete once the read request is issued by the processor.
Many processors, including the Pentium(copyright) II and Pentium(copyright) III processors from Intel(copyright) Corporation, utilize a dual phase address when communicating with a system logic device where the system logic device includes a system memory interface. With dual phase addressing, an address for a read request is communicated to the system logic device in a first clock period while the length of the requested transfer is communicated in a second clock period. Prior system logic devices wait to receive both the address and the length information before the system logic device can issue a read request to the system memory. These prior system logic devices fail to take advantage of the fact that a large majority of read cycles to main memory have a length equal to that of a cacheline.
USPTO Backgrounds
USPTO Backgrounds