1. Field of the Invention:
The present invention relates to a flip-flop circuit, more particularly to a data flip-flop circuit and T flip-flop circuit.
2. Description of the Prior Art:
The prior flip-flop circuit of this sort is disclosed, for example in "DESIGN OF FLIP-FLOP CIRCUIT AND COUNTER CIRCUIT" in pp 84-89 published by Tokyo Electrical Engineering College. The prior flip-flop circuit will be described hereafter with reference to FIGS. 3 and 4.
A D flip-flop circuit shown in FIG. 3 comprises 6 NOR gates 31 through 36. Designated at CL is an input terminal of clock pulse (hereafter referred to as a clock pulse terminal). D, D denote respectively data pulse input terminal and inverse data pulse input terminal
(hereafter referred to as data terminals), Q and Q denote respectively output terminal and inverse output terminal. FIG. 4 shows waveforms for assistance in explanation of the operation of the flip-flop circuit in which the output terminal Q is connected to the inverse data input terminal D, and the inverse output terminal Q is connected to the data input terminal D as shown in dotted line in FIG. 3 constituting a T flip-flop circuit. An axis of abscissa shows times t1-t5 while an axis of ordinate shows logical output levels respectively at the clock pulse terminal CL, nodes N1-N4, the output terminal Q, and the inverse terminal Q.
Assuming that at the time of t0, a clock pulse at the clock pulse terminal CL (hereafter referred to as clock pulse) is high level (hereafter referred to as H) an output condition at the output terminal Q (hereafter referred to as Q output) is low level (hereafter referred to as L), and an output condition at the inverse output terminal Q (hereafter referred to as Q output) is H. Output conditions at the nodes N2, N3 (hereafter referred to respectively N2, N3 output) are respectively forced to L since the clock pulse goes H. The output condition at the node N1 (hereafter referred to as N1 output) is forced to H since the Q output and the N2 output are respectively L. An output condition at the node N4 (hereafter referred to as N4 output) is forced to H since the Q output is H. The flip-flop circuit is stable at this state.
When the clock pulse goes L at the time of t1, N2 output is determined by the N1 output since the clock pulse and the N3 output are respectively L. Similarly, the N3 output goes H since the N4 output is L at the time of t1. The Q output changes L while the N3 output is H to thereby cause the Q output to change H since the N2 output and the Q output respectively change L. The N1 output changes L since Q output is H. The N4 output changes L since the N3 output is H. The flip-flop circuit is stable at this state.
Subsequently, when the clock pulse goes H at the time of t2, the N2 output and the N3 output are respectively L. Hence, the Q output and the Q output do not change. While the N1 output is kept L, the N4 output changes H since the N3 output and the Q output are respectively L. The flip-flop circuit is stable at this state.
Still subsequently, when the clock pulse goes L at the time of t3, the N2 output is determined by the N1 output. The N2 output changes H since the N1 output is L. The N3 output is determined by the N4 output. The N3 changes H since the N4 output is H. The Q output changes L since the N2 output changes H while Q output changes H since both the Q output and the N3 output change L respectively. While the N1 output is kept L since the N2 output changes H, the N4 output changes L since the Q changes H. The flip-flop circuit is stable at this state.
Still subsequently furthermore, when the clock pulse goes H at the time of t4, the N2 output and the N3 output change respectively L whereby the Q output and the Q output do not change. The N1 output changes H since the Q output and N2 output respectively change L. The N4 output is kept L since the Q output is H. The flip-flop circuit at the time of t4 changes same state as that at that time of t0, namely to be stable.
As described above, the prior T flip-flop circuit is employed as a frequency divider enabling to effect 1/2 frequency dividing operation in which the Q output repeats an operation to switch L or H at the trailing edge of the clock pulse. When the N1 output is, for example, H, a critical path is constituted by the path starting from the node N1, passing through the node 4, the NOR gate 32, the node N2, the NOR gate 35, the NOR gate 36, and reaching the NOR gate 34. A frequency where the flip-flop circuit operates at maximum speed is determined by a delay time characteristic in the critical path.
However, the prior flip-flop circuit has a shortcoming that a delivering delay time is increased since the NOR gates 32, 33 have respectively three fun-outs. Furthermore, inasmuch as many NOR gates are employed in the flip flop circuit, the delay time is increased as a whole of the circuit. Accordingly, the prior flip-flop circuit can not effect as the frequency divider when the input clock pulse is a high frequency.
USPTO Backgrounds
USPTO Backgrounds