Integrated circuit (semiconductor) memory devices are widely used in consumer and commercial applications. Semiconductor memory devices may be characterized as volatile random access memories (RAMs), or non-volatile memory devices. In RAMs, the logic information is stored either by setting up the logic state of a bistable flip-flop such as in a static random access memory (SRAM), or through the charging of a capacitor as in a dynamic random access memory (DRAM). In either case, the data are stored and can be read out as long as the power is applied, and are lost when the power is turned off. Hence, they are called volatile memories.
Non-volatile memories, such as widely used Mask Read Only Memory (MROM), Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), and Electrically Erasable Programmable Read Only Memory (EEPROM), are capable of storing the data even with the power turned off. The non-volatile memory data storage mode may be permanent or reprogrammable, depending upon the fabrication technology used. Non-volatile memories may be used for program and microcode storage in a wide variety of applications. A combination of single-chip volatile as well as non-volatile memory storage modes is also available in devices such as non-volatile SRAM (nvRAM) for use in systems that desire fast, programmable non-volatile memory. In addition, many special memory architectures have evolved which contain some additional logic circuitry to tailor their performance for application-specific tasks.
MROM, PROM and EPROM non-volatile memories may not be erasable and programmable by the end user. On the other hand, EEPROM devices are capable of electrically being erased or written. Accordingly, the EEPROM devices may be used in an auxiliary memory or for system programming where continuous update is desired. In particular, a flash EEPROM may have a higher integration density than a conventional EEPROM and thus may be used for a large auxiliary memory. A NAND-type flash EEPROM (hereinafter, referred to as a “NAND-type flash memory”) may have a higher integration density than the well-known NOR-type flash EEPROM.
A non-volatile memory device such as a flash memory device includes a memory cell array as a storage area for storing information, which includes a plurality of memory blocks BLK0–BLKn, as illustrated in FIG. 1. Each memory block is divided into a main field 10 and a spare field 20. The spare field of each memory block stores information related to both the main field 10 and the flash memory device, such as error correction codes, device codes, other codes, block information, page information, and the like. Each memory block includes a plurality of cell strings (also referred to as NAND strings) which are configured as illustrated in FIG. 1. A page buffer circuit is provided in the flash memory device to store and read out data in and from the memory cell array. As is well known, memory cells of the NAND-type flash memory device may be programmed and erased by means of Fowler-Nordheim (F-N) tunneling current. Erase and program methods of the memory device are disclosed in U.S. Pat. No. 5,473,563 entitled “Nonvolatile Semiconductor Memory” and U.S. Pat. No. 5,696,717 entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability” the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
As is well known, a flash memory device includes a memory cell array that is divided into a number of memory blocks. A read/erase/program operation of respective memory blocks is made individually. A time taken to erase memory blocks may be a factor limiting the performance of a system comprising a flash memory device as well as the performance of the flash memory device itself. In attempts to solve this potential drawback, techniques for erasing a plurality of memory blocks simultaneously are disclosed in U.S. Pat. No. 5,841,721 entitled “Multi-Block Erase And Verification Circuit In A Nonvolatile Semiconductor Memory Device And A Method Thereof” and U.S. Pat. No. 5,999,446 entitled “Multi-State Flash EEPROM System With Selective Multi-Sector Erase”, the disclosures of which are hereby incorporated herein by reference in their entirety as if set forth fully herein.
Once memory blocks are erased, information indicating that the memory block is erased is stored in a spare field of the erased memory block. Such information is called “block information”. In other words, block information of a memory block is stored at a specific location of its spare field. The block information can be 1-bit data. Conventionally, in all memory blocks, this block information is stored at the same location of a spare field of a corresponding memory block. For example, as illustrated in FIG. 1, block information is stored at a memory cell (marked by a dotted line) which is arranged at an intersection of a first word line WL0 of each memory block and a spare bit line SBL0.
USPTO Backgrounds
USPTO Backgrounds