A fuse has been used for providing access to redundant cells in a semiconductor memory device. Using the fuse can increase the yield of the semiconductor memory device. In addition, a cell transistor in a non-volatile memory device typically has a dual gate electrode comprising a floating gate electrode and a control gate electrode. Therefore, when fabricating a non-volatile memory device, the fuse and the control gate electrode may be formed using the same layer.
In forming the fuse, a trench may be formed by patterning a predetermined region of a semiconductor substrate, and then an insulating layer may be formed on the semiconductor substrate in which the trench has been formed. Subsequently, the insulating layer may be planarized by a chemical mechanical polishing (CMP) process so that an isolation layer may be formed in the trench. After a control gate conductive layer is formed on the isolation layer, the fuse may be obtained by patterning the control gate conductive layer. Because patterning the control gate conductive layer forms the fuse, the fuse may be formed during formation of the control gate. Therefore, additional processing may be unnecessary to form the fuse.
Unfortunately, when the CMP process is carried out, a dishing (that is, a dented shape) may occur in the isolation layer. Particularly, the dishing may be more severe in an isolation layer filling a trench having a relatively wide width. The wide trench, however, may be required so as to form a fuse box including a plurality of fuses.
The dishing may cause polishing damage at active regions arranged near the fuses when the CMP process is carried out. Particularly, the fuses may be electrically connected to sensing transistors. Because the sensing transistors may be closely arranged with the fuses, the sensing transistors may be damaged during the CMP process.
A method for preventing dishing is disclosed in U.S. Pat. No. 6,531,757 issued to Shiratake entitled “Semiconductor device fuse box with fuses of uniform depth.” According to U.S. Pat. No. 6,531,757, a trench is formed in a semiconductor substrate comprising silicon. Subsequently, an oxide layer is formed on the semiconductor substrate with the trench, and then the oxide layer is planarized by a CMP process. As a result, isolation layers filled with the oxide layer in the trench are formed. The isolation layers are formed adjacent to the field regions constituting semiconductor regions. By decreasing the area of the isolation layer, dishing can be suppressed. The fuses are formed on the isolation layer so as to be arranged thereon. An oxide layer deposited on the isolation layer may cover the fuses.
According to the above-described method, the fuses may be formed on the same level as a control gate because dishing is reduced. The formation of the fuses as described in U.S. Pat. No. 6,531,757 may have some disadvantages, however. Fuse window regions expose the fuses and the surface of the field regions simultaneously. When a laser beam blows the fuses, the laser beam may irregularly reflect from the field regions. It may be difficult to blow the fuses because of the irregular reflection of the laser beam. Also, the fuses blown by the laser beam may be electrically connected to the field regions arranged near the blown fuses. As a result, the blown fuses may generate a short circuit. In addition, the field regions exposed while the fuses are formed by patterning the control gate conductive layer may be damaged by etching. As a result, pitting may occur in the field regions.
Thus, the method described in U.S. Pat. No. 6,531,757 may be difficult to apply to non-volatile memory device processing for forming a fuse and a control gate electrode by patterning the control gate conductive layer.
USPTO Backgrounds
USPTO Backgrounds