1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly, to a circuit to detect clock delay.
2. Description of the Related Art
As speed increases in a master circuit, such as a central processing unit (“CPU”), the operational speed of memory or a system bus that interfaces with the master circuit also increases. However, the operational margin of data clocking decreases due to clock delay caused by the circuit structure of a motherboard.
In order to solve such a problem, a clock forwarding method is used wherein the clock signal of a master circuit is transmitted to a slave circuit when data is transmitted from the master circuit to the slave circuit. This allows the slave circuit to fetch data, wherein the clock delay between the master circuit and the slave circuit is analyzed and compensated.
FIG. 1 is a timing diagram for explaining the relationship between a clock signal outputted from a master circuit and a clock signal inputted to the master circuit.
An output clock signal CLK_OUT is outputted from the master circuit (not shown) and sent to the slave circuit (not shown). An input clock signal CLK_IN is outputted from the slave circuit and sent to the master circuit.
The master circuit uses the input clock signal CLK_IN to load data that is sent from the slave circuit and uses the output clock signal CLK_OUT to internally process the loaded data.
Referring to FIG. 1, a timing diagram of CLK_OUT and CLK_IN versus time is indicated generally by the reference numeral 100. A clock delay occurs between the output clock signal CLK_OUT and the input clock signal CLK_IN. The clock delay occurs due to the circuit configuration of a motherboard, which includes the master circuit and the slave circuit. The clock delay is not an important factor when the input clock signal CLK_IN and the output clock signal CLK_OUT are slow. When the input clock signal CLK_IN and the output clock signal CLK_OUT are slow, the operational margin obtained is enough to load or unload data by the master circuit.
FIG. 2 shows a timing diagram indicated generally by the reference numeral 200, describing the output clock signal CLK_OUT and input clock signal CLK_IN at increased speed compared to the timing diagram 100 of FIG. 1.
As the speed of the master circuit and the slave circuit are increased, the operational margin necessary for loading and unloading data by the master circuit is reduced. As a result, errors may occur in data transmission from the slave circuit to the master circuit.
FIG. 3 shows a timing diagram indicated generally by the reference numeral 300, for explaining the case where the operational margin is eliminated due to an increase in speed of the output clock signal CLK_OUT and the input clock signal CLK_IN.
If the speed of the clock signals is increased so that the operational margin is eliminated, it is very difficult to safely transmit data from the slave circuit to the master circuit. In FIG. 3, the output clock signal CLK_OUT precedes the input clock signal CLK_IN, and the operational margin is eliminated. Here, data is processed before data is loaded in the master circuit, indicating an abnormal operation.
In a highly efficient computer operating at a high speed, it becomes difficult to prevent such abnormal operation from occurring. In order to solve such problems, a clock forwarding method has been suggested.
FIG. 4 shows a timing diagram indicated generally by the reference numeral 400, for explaining the relationship between the input clock signal CLK_IN and the output clock signal CLK_OUT according to the clock forwarding method.
Several clock periods transpire according to clock delay and prior to transmission of the output clock signal CLK_OUT. Therefore, data processing by the master circuit is performed after the data loading operation, so that data inputted from the slave circuit can be correctly transmitted to the master circuit.
In the clock forwarding method, fixed initial parameters necessary for data loading and unloading must be determined. In general, the fixed initial parameters are manually determined by a designer of the motherboard and permanently stored in external read-only memory (ROM) (not shown). After power is turned on, the fixed initial parameters are loaded to a clock forwarding circuit (not shown) for forwarding clock signals when the master circuit is initialized. Data, which is inputted to the master circuit by the clock forwarding circuit, can be processed without any abnormal operation.
The clock forwarding method is shown in several U.S. patent documents, including U.S. Pat. No. 4, 811, 364, issued to Seger et al. on 7 Mar. 1989, entitled “METHOD AND APPARATUS FOR STABILIZED DATA TRANSMISSION”; U.S. Pat. No. 4, 979, 190, issued to Seger et al. on 18 Dec. 1990, entitled “METHOD AND APPRATUS FOR STABILIZED DATA TRANSMISSION”; and U.S. Pat. No. 4, 525, 849, issued to Wolf on 25 Jun. 1985, entitled “DATA TRANSMISSION FACILITY BETWEEN TWO ASYNCHRONOUSLY CONTROLLED DATA PROCESSING SYSTEMS WITH A BUFFER MEMORY”.
However, since the initial parameters used in the clock forwarding method are determined by the designer of the motherboard, production cost increases. In addition, given that the initial parameters are stored in ROM, errors may occur in data transmission of some products.
Further, when the clock forwarding method is used, the clock forwarding circuit and the slave circuit included in the master circuit, e.g., a memory or a chip set, must be reset at the same time, which only occurs through a system reset. Also, due to noise in the slave circuit, errors can occur in data transmission.
USPTO Backgrounds
USPTO Backgrounds