The present invention relates to a method for fabricating a semiconductor device.
Various photoresist masking treatments have heretofore been proposed and practised for formation or semiconductor devices. For example, electrodes or wiring layers are selectively formed by such photoresist masking treatment. In the art of semiconductor integrated circuits, there is recently observed a tendency to reduce areas occupied by elements such as transistors and decrease the sizes of electrodes or wiring layers. For this purpose, it is necessary to remarkably diminish a spacing between adjoining electrodes or wiring layers.
However, in the case where electrodes or the like are formed according to the above-mentioned photoresist masking treatment, since margins for the mask alignment are necessary, it is impossible to form electrodes having a high size precision or maintain a precise spacing between adjoining electrodes disposed closely to each other. Therefore, semiconductor devices having minute and precise sizes or dimensions cannot be prepared according to these conventional photoresist masking treatments.
As the semiconductor device in which the electrode spacing is narrowed as much as possible so as to increase the operation speed, there is known a charge coupled device (hereinafter referred to as "CCD"). In connection with formation of electrodes in this semiconductor device, a method for reducing a spacing between electrodes by utilizing a technique of oxidizing the surfaces of electrodes is known from Japanese Patent Application Laid-Open Specification No. 15078/72. According to this method, a first electrode is selectively formed on a semiconductor substrate on the surface of which an oxide film has been formed, and then, a second electrode is formed on the semiconductor substrate so that the second electrode is partially superimposed on the first electrode. In this method, the electrode spacing is defined by the thickness of the oxide film on the side of the first electrode. The second electrode is selectively etched at the portion superimposed on the first electrode, and a photoresist masking treatment is necessary for this selective etching. Accordingly, it is impossible to reduce the size of this superimposed portion at a high precision, and therefore, the capacity of the capacitor at the superimposed portion is increased. Consequently, it is impossible to obtain high-speed CCD.
USPTO Backgrounds
USPTO Backgrounds