1. Field of the Invention
The present invention generally relates to the field of semiconductor manufacturing, and, more particularly, to a method for automating the evaluation and analysis of defects in masks used in the semiconductor manufacturing process to determine which defects would cause product failure.
2. Background Description
As technology in the computer manufacturing field matures, the physical size of semiconductor chips continues to decrease dramatically. Accordingly, increasingly precise techniques and tools are required to manufacture the chips and the circuitry that is to be packaged on the chips. These techniques include the use of masks to create the circuit pattern corresponding to the chip design. It is a common practice in the industry to use masks in the manufacturing process for semiconductor chips. The design and layout of the circuit for the chip can be stored in the form of a mask, which can then be transferred to the surface of a silicon wafer. This process is referred to as photolithography. As the chips become smaller and smaller, the precision required in the masks increases. Therefore, the process for evaluation and inspection of the masks becomes increasingly important to the efficiency of the manufacturing operation.
Accepted techniques for inspection of masks use optical inspection tools to determine the presence of defects on the mask. The output of these tools can then be used in conjunction with pre-established criteria to determine if the defects require the masks to be scrapped, repaired or accepted. The most commonly used criterion is based on the size of the defect; however, defects can also be classified as to location and type (clear or opaque). In any event, the standard inspection process will tend to result in the rejection of masks when the size of the defect exceeds some maximum pre-established criterion. This approach is non-discriminating, however, because it is well known that not all defects in a given mask will necessarily lead to failure of the chip. For example, shorts between dummy fill shapes are generally harmless unless they merge to create a single shape larger than several microns. Also, via to via shorts between vias on the same net are harmless if they do not also cause the vias to expand outward beyond the underlying and overlying metal shapes. Accordingly, the standard approach can lead to the rejection of masks with defects in non-critical regions of the chip layout.
Based on this standard approach, otherwise acceptable masks would be scrapped unnecessarily. Alternatively, such masks must be analyzed manually by a human operator or a defect classification tool. Manual classification of defects, via an optical device or scanning electron microscope, can resolve issues such as whether a particular defect falls on or near dummy fill shapes rather than active circuit elements. However, in general, such techniques cannot resolve issues involving nets because simple inspection of the mask or the layout data does not suffice to accurately define the nets. In any event, either option is labor intensive and expensive and can be detrimental to the manufacturing process.
To improve the manufacturing process it is desirable to have an automated system for analyzing and evaluating the results from the inspection of the masks. An automated system would eliminate unnecessary scrapping of otherwise acceptable masks and would reduce the possibility of human error. Such a system will enhance both the pre-shipment inspection and repair process as well as the pre-acceptance inspection process. By identifying only those mask defects that will lead to chip failure, thereby ignoring the remainder of defects, the efficiency of the inspection/repair and acceptance process will be improved. Moreover, an automated system will allow manufacturers to concentrate on systemic errors that lead to defects in the masks, thereby improving the overall manufacturing process.
USPTO Backgrounds
USPTO Backgrounds