There are several tools available for verification of hardware description language (HDL) designs in simulation. Most of the functional bugs can be detected and fixed in simulation where each bit in the design can be observed at every clock transition. However, once the design goes into field-programmable gate array (FPGAs) the observability is typically reduced.
The most difficult bugs to find are those that are difficult to reproduce. These are typically due to either unexpected data values that occur in deployment (but not in testing) or to subtle timing-dependent properties that are due to non-deterministic behavior of various physical components of the system.
Generally tools are used to record values of various signals in the chip instead of a simulation program.
USPTO Backgrounds
USPTO Backgrounds