Field of the Invention
The invention relates to a semiconductor structure and a manufacturing method thereof; particularly, the invention relates to a memory having a shallow trench isolation (STI) structure and a manufacturing method of the memory.
Description of Related Art
As the level of integration of semiconductor devices increases, sizes of the semiconductor devices continuously decrease, thus leading to increasing mutual influence on the semiconductor devices. Generally, isolation structures are applied to isolate the semiconductor devices from one another, so as to avoid significant influences and improve the reliability of the devices. In memory devices, the excessively small heights of the isolation structures may easily cause the mutual interference during programming actions and cause potential damages to tunneling dielectric layers, such that the reliability of the memory devices is deteriorated. If the heights of the isolation structures are excessively large, however, the gate coupling ratio (GCR) may decrease, and thus the performance of the memory devices is lowered.
USPTO Backgrounds
USPTO Backgrounds