1. Filed of the Invention
The present invention relates to a semiconductor integrated circuit and a method of manufacturing the same, and more particularly to a semiconductor integrated circuit including a multi-input logic circuit constituted by a plurality of voltage-activated transistors which are connected in series, and a method of manufacturing such a semiconductor integrated circuit.
2. Description of the Related Art
Generally, a multi-input logic circuit such as a NAND or NOR circuit comprises a plurality of n-channel and p-channel MOSFETs (metal oxide semiconductor field effect transistors) which are electrically connected in series between a power supply terminal and a grounding terminal. Referring to FIG. 16 of the accompanying drawings, a 2-input NAND circuit comprises n-channel MOSFETs 100 and 101 electrically connected in series between a grounding power supply terminal Vss and a signal output terminal Pout, and p-channel MOSFETs 102 and 103 electrically connected in parallel between a circuit operation voltage terminal Vcc and the signal output terminal Pout. Gate electrodes of the n-channel MOSFET 100 and p-channel MOSFET 102 are electrically connected to a signal input terminal Pin2 while gate electrodes of the n-channel MOSFET 101 and p-channel MOSFET 103 are connected to a signal input terminal Pin1.
When this 2-input NAND circuit is constituted by a bulk-type element in which the n-channel MOSFETs 100, 101 and the p-channel MOSFETs 102, 103 are formed on a main surface of a silicon single crystal substrate, a threshold voltage is increased in the n-channel MOSFET 101 at the output terminal Pout due to a body effect. The increase of the threshold voltage adversely affects the current-activated performance of the 2-input NAND circuit, and lowers the overall operation speed of the semiconductor integrated circuit.
The use of the SOI (silicon on insulator) or SOS (silicon on sapphire) structure is effective in reducing the body effect in the semiconductor integrated circuit. In the SOI structure, an SOI substrate includes a silicon single crystal layer which is formed on a silicon single crystal substrate via an insulator, and elements are mounted on the silicon single crystal layer. With the SOS structure, an SOS substrate is provided with a silicon single crystal layer which is formed on a sapphire substrate, and elements are mounted on the silicon single crystal layer. In either structure, the elements are isolated, and potentials of body regions depend upon a built-in potential between the body region and a source region. Therefore, it has been expected that the increase of the threshold voltage due to the body effect can be prevented in the n-channel MOSFET 101 of the 2-input NAND circuit.
However, the logic circuit including the foregoing SOI elements suffers from variations of element characteristics due to a varying body potential (substrate bias effect), and a reduced noise margin. As a result, each SOI element needs a body contact. If the body contacts are provided for the SOI elements in a structure identical to that of existing bulk-type elements, it is not possible to reduce the body effect. As a result, the operation speed of the semiconductor integrated circuit will be lowered.
USPTO Backgrounds
USPTO Backgrounds