1. Field of the Invention
The Present invention is related to a method for manufacturing a known good die array(hereinafter, referred to as "KGD" array ) and more particularly it is related to a method for producing a KGD array having solder bumps suitable for use on flip-chips which may be advantageously employed for producing multi-chip modules.
2. Prior Art
Various semiconductor devices are manufactured through practicing a wafer process and a packaging process. A starting substrate, usually a thin wafer of silicon or gallium arsenide, is masked, etched, and doped through several process steps, the steps depending on the type of devices being manufactured. This process, called a "wafer process", yields a number of die on each wafer produced. The die are divided and packaged into individual components.
Recent trends of compactation of electronic appliances encourage developments in compact mounting technologies for semiconductor devices. The so-called multi-chip module is a representative example of compact mounting. In multi-chip module technology, a plurality of bare chips are interconnected to each other on a printed wiring board.
Multi-chip module technology may be classified depending on the patterns of mounting bare chips on the printed wiring board into three groups: wire bonding, tape automated bonding, and flip-chip technologies. The flip-chip technologies, wherein the electrical interconnection lengths between the dies and the printed wiring board are shorter than those of other two technologies, are widely employed because handling is easy, the circuit performance is good and the cost is low.
In multi-chip module technology, the dies are subjected to alternating current (AC) and burn-in tests before being interconnected to each other. The tests may be conducted by employing a probe during the wafer process; by employing a tape automated bonding which is removed after testing; or by temporarily bonding the chip lead wires to ceramic packages for the chips.
In conventional multi-chip module manufacture using flip-chip technologies, solder bumps cannot be formed until the tests are conducted. Rather, they are formed on individual dies after the testing has been connected because the electrical connections are made between bare chips and test sockets. This causes a decrease in the workability and reliability of devices and an increase of production costs.
The reason why solder bumps cannot be formed until the tests are conducted is that, although the above-described test methods need a removal of wire or electrical interconnection members after the tests are conducted, the physical bonding or electrical interconnection between solder bumps and wires or mechanical properties thereof, did not allow a manufacturer to do so. Therefore, solder bumps cannot heretofore have not been able to be formed during the wafer process before the tests were conducted.
Thus, there has been a need to provide a method or apparatus to allow solder bumps to be formed the bonding pads of die during the wafer process before the tests are conducted.
USPTO Backgrounds
USPTO Backgrounds