Computing devices have clock generator components which generate timing information that is used to coordinate the execution of functions within the device. Additionally, when a computing device communicates data with another computing device over a connection, the timing information is shared over the connection to synchronize the clock generator components of the two computing devices. Example methods in wireless communication are frequency hopping and time division channel multiplexing. If one or more of the clock generator circuits of the two communicating devices go out of synchronization, transfer of data fails to function properly.
In the event that the computing device experiences a power loss, the device may be configured to have reserve power. However, existing computing devices are designed to use the reserve power to operate the microcontroller and communications unit (such as a radio transceiver) during the power loss. This results in the stored power becoming exhausted in a relatively short amount of time. Once stored power is exhausted, the clock generator of the computing device will shut down, and the computing device will lose timing synchronization with any computing device(s) it was communicating with prior to the power loss. Accordingly, once power is restored, the computing device must reacquire the timing synchronization data. This is disadvantageous as reacquiring synchronization data takes a substantial amount of time.
What is needed is a system and method for maintaining clock synchronization between computing devices during a power loss by selectively shutting down/suspending non-essential components while maintaining operation of the clock generator component.
USPTO Backgrounds
USPTO Backgrounds