1. Field of the Invention
The present invention relates to a semiconductor memory device, more particularly to a semiconductor memory device having a serial data input circuit and a serial data output circuit. It also relates to a semiconductor memory device operable at high-speed using data in a first-in first-out (FIFO) mode.
2. Description of the Related Art
An image data processing system or the like requires a large capacity memory. To meet the requirement for a large capacity memory at low cost, a dynamic random-access memory (RAM) is extensively used. In addition, in order to display a large amount of image data on a cathode ray tube (CRT) display unit and to compute a large amount of image data, such as gradients and in filtering, high-speed data store and/or read-out are also required. A normal semiconductor memory device having a dynamic RAM, however, suffers from a disadvantage of low-speed data store and/or read-out.
In order to overcome the above disadvantage, there are known in the prior art, semiconductor memory devices including one or more shift register sets provided outside the dynamic RAM, as described in detail later. A shift register set is used for data store into and/or data read-out from the dynamic RAM of a group of data, e.g., 256 bits, shortening the data store and/or data read-out time.
These prior art semiconductor memory devices, however, still suffer from the disadvantages of low speed, or high power consumption when improving the operation speed, and occupation of a considerably large space on the semiconductor chip, which means low integration density.
Furthermore, a data FIFO system using a register is known. This system, however, suffers from the disadvantage of low amount of data handling capability. On the contrary, a data FIFO system for performing group data accessing of the memory cells is also known. The latter suffers from the disadvantage of low processing speed.
USPTO Backgrounds
USPTO Backgrounds