A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimension of metal lines are scaled down, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
The location and size of copper metallization on an integrated circuit is defined using a damascene etch process because copper cannot be readily patterned using conventional reactive ion etching techniques. Referring to FIG. 1, a multi-level copper metallization structure in an integrated circuit includes a bottom copper line 102 defined within a bottom trench-line 104 in a bottom insulating layer 106. After deposition of copper onto the integrated circuit having the bottom trench line 104, the surface of the integrated circuit is polished to remove the copper deposited on the surface of the integrated circuit and to confine the copper to be within the bottom trench line 104.
After polishing the integrated circuit surface, a copper via plug 108, defined within a via hole 110 in a via insulating layer 112, and a top copper line 114, defined within a top trench line 116 in a top insulating layer 118, are added. The top copper line 114 is on a different metallization level from the bottom copper line 102, and the via plug 108 interconnects the copper lines 102 and 114 on the different metallization levels. FIG. 2 shows a top-view of the damascene metallization structure of FIG. 1, and the cross-sectional view of FIG. 1 is taken along line AA of FIG. 2.
In a dual damascene etch process, the via hole 110 and the top trench line 116 are etched out to form contiguous openings before copper is deposited into the via hole 110 and the top trench line 116. Hardmask layers are used in the dual damascene etch process for etching out the via hole 110 and the top trench line 116.
In a damascene etch process, hardmask layers are used to define openings in insulating layers. Referring to FIG. 3, a bottom hardmask layer 302 is deposited on the bottom insulating layer 106 to define the bottom wall of the via hole 110. In addition, a via hardmask layer 304 is deposited on the via insulating layer 112 to define the via hole 110. Also, a top hardmask layer 306 is deposited on the top insulating layer 118 to define the location and size of trench lines in the top insulating layer 118.
During etching of the trench lines and via holes, a photoresist layer 308 is deposited on the top hardmask layer 306 which is the top-most layer of the integrated circuit. As known to one of ordinary skill in the art of integrated circuit fabrication, the photoresist layer is exposed to light for defining the pattern of openings to be etched in the layers below the photoresist layer 308. If the top hardmask layer 306 which abuts the photoresist layer 308 is antireflective to the light used for exposing the photoresist layer 308, then the patterning of the photoresist layer 308 from such light conforms better to a desired pattern. Such high conformance is especially important for small dimension integrated circuit fabrication.
The present invention is described for etching a dual damascene opening having a trench line and a via hole for integrated circuit metallization. However, one of ordinary skill in the art may readily use the present invention for etching any type of opening with a hardmask within an integrated circuit from the description herein.
USPTO Backgrounds
USPTO Backgrounds