The invention relates generally to semiconductor devices and in particular to semiconductor devices for use in amplifiers for high frequency applications. FIG. 1 depicts a cross section of a conventional BJT 100. As shown in FIG. 1, the conventional BJT 100 is formed on a silicon substrate 102 of a second conductivity type (e.g., N type) upon which an epitaxial layer 104 is deposited. The epitaxial layer 104 may be a second conductivity type and form part of the collector. A base region 106 having a first conductivity type (e.g., P type) is formed in the epitaxial layer 104. An insulating layer 108, such as SiO2, is formed over the base region 106. Windows are formed in insulative layer 108 to provide access for metallic connections 110 to the base region and for the emitter region. An emitter region 112 made of polysilicon having a second conductivity type is formed in connection with the base region 106 and an emitter contact 114 is provided. Substrate 102 provides a sub-collector, contact with which may be made from the bottom surface of the substrate. Multiple BJT""s 100 may be formed on a common substrate with the subcollectors typically isolated from each other by suitable technology.
A drawback to the conventional BJT 100 is that the whole transistor is fabricated on the subcollector area 102. Such a design yields high parasitic collector capacitance which results in poor performance of BJT 100 in high frequency applications. The variation of collector capacitance with bias results in poor linearity in power amplification applications.
An exemplary embodiment of the invention is a semiconductor device comprising a substrate of a first conductivity type and a subcollector of a second conductivity type provided on the substrate. An intrinsic epitaxial layer is formed on the substrate. A collector region of the second conductivity type is adjacent the subcollector and a base region of the first conductivity type is adjacent the collector region. An emitter region of the second conductivity type is adjacent the base region and the emitter region has an emitter size. The subcollector and collector region both have a size not substantially greater than the emitter size. An alternate embodiment includes a spacer layer formed between the emitter region and the base region.
USPTO Backgrounds
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