In the field of data communication systems, recovering of a transmitted signal is an important aspect. An information signal is transmitted by impressing modulation symbols onto a carrier, where the modulation scheme is chosen in such a way that the carrier is not suppressed at the receiving device. As a result, a carrier is available in the received signal for a carrier recovery circuit to lock on, and a coherent demodulation can take place.
The transmitted symbols are at a given phase and frequency relation with respect to the carrier. Normally the relation between symbol and carrier frequencies is known to the receiver. Therefore, based on the recovered carrier signal, the receiver can reconstruct a symbol clock, with the correct frequency but with an unknown phase with respect to the symbol transitions. Recovery of the correct symbol phase is a crucial function for reliable data detection.
U.S. Pat. No. 5,789,988 A discloses a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system. An analog/digital (A/D) converter performs an A/D conversion upon a coherent-detected baseband analog signal in synchronization with a sampling clock signal having a time period half of a symbol time period. A phase detector receives successive first, second and third sampled data from the A/D converter, determines whether or not a signal transition formed by the first and second sampled data crosses a zero value within a predetermined time deviation, and compares a polarity of the second sampled data with a polarity of one of the first and second sampled data to generate a phase detection signal. Further, a loop filter is connected to an output of the phase detector, and a voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.
U.S. Pat. No. 6,127,897 A discloses a clock recovery circuit in a demodulator of a multi-level quadrature amplitude modulation (QAM) system. An analog/digital (A/D) converter performs an A/D conversion upon an analog baseband signal in synchronization with a sampling clock signal having a time period that is a symbol time period. A phase detector receives successive first and third data sampled from the A/D converter, calculates second data by addition of the first and third data, determines whether or not a signal transition formed by the first and third data crosses a zero value within a predetermined deviation, and compares a polarity of the second data with a polarity of one of the first and third data, and generates a comparison result as a phase detection signal when the signal transition crosses the zero value. A loop filter passes a low-frequency component of the phase detection signal there through. A voltage controlled oscillator supplies the sampling clock signal to the A/D converter in accordance with an output signal of the loop filter.
U.S. Pat. No. 5,642,243 A discloses a timing recovery phase-locked loop (PLL) in a synchronous read channel for magnetic recording. The timing recovery phase-locked loop comprises a discrete time frequency error detector for locking the PLL to a sinusoidal reference signal. The sinusoidal reference signal is sampled, and a frequency error is computed using three sample values which span more than half a period of the reference signal.
USPTO Backgrounds
USPTO Backgrounds