1. Field of the Invention
The present invention relates generally to the field of semiconductor manufacturing. More specifically, the present invention relates to system architecture of semiconductor manufacturing equipment for ultra high system throughput with reduced cost.
2. Description of the Related Art
Semiconductor substrates (wafers) typically have many layers deposited thereon for device fabrication. Depositing many layers of various films is typically performed using deposition systems with multiple chambers designed for various processes. One of the most important performance indexes of the semiconductor manufacturing system is the system throughput, which is typically described as number of wafers per hour (wph). A single bottleneck point typically limits the system throughput, and this bottleneck can be a process chamber or a cluster robot (either a buffer robot or a transfer robot). If the chamber process times are short enough, the theoretical limit of maximum system throughput of such process sequencing is mainly by robot swap speed and the number of swaps each robot needs to complete full sequencing.
Conventionally, the system architectures for depositing Cu barrier and seed layers on semiconductor wafers have 3 or 4 wafers swaps for buffer robot and 3 swaps for transfer robot. For the configuration having 3 swaps each for buffer robot and transfer robot, the robot-limited system throughput is much higher than the one with 4 swaps for buffer robot. However, problems occur when maximum allowed chamber time become too short to complete the process required.
Therefore, the prior art is deficient in the lack of a n effective system or means for depositing Cu barrier and seed layers on semiconductor wafers with ultra high system throughput while the chamber time is sufficient for performing the processes. The present invention fulfills this long-standing need and desire in the art.
USPTO Backgrounds
USPTO Backgrounds