The present disclosure herein relates to a semiconductor device and a method of forming the same.
A major technological development trend in the semiconductor industry is the miniaturization of semiconductor devices. Also, in the semiconductor device package field, semiconductor device packages such as a Fine pitch Ball Grid Array (FBGA) or Chip Scale Package (CSP), which have a small size and a plurality of pins, are being developed due to the rapid increase in demand for small computers and portable electronic devices.
While semiconductor device packages currently being developed such as Fine pitch Ball Grid Arrays and Chip Scale Packages have the physical advantages of small size and light weight, their reliability may not yet match that of typical plastic packages, and the high cost raw materials and processes used in their fabrication lowers their cost-competitiveness. In particular, the so-called micro Ball Grid Array (μBGA) package, a representative chip scale package, while having more favorable characteristics than the fine pitch ball grid array or chip scale package, may suffer from low reliability and cost-competitiveness.
As a type of package developed to overcome these limitations, the so-called Wafer Level CSP (WL-CSP) is based on the redistribution or rerouting of a bonding pad of a semiconductor chip.
A wafer level chip scale package employing redistribution may include a bonding pad on a semiconductor chip that is connected to another pad of greater size during semiconductor device fabrication (FAB), after which an external connection terminal such as a solder ball or bonding wire is formed on the pad.
USPTO Backgrounds
USPTO Backgrounds