In order to fabricate integrated circuits (ICs), such as memory devices and logic devices of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions of the device while maintaining the device's electrical properties. Additionally, all dimensions of the device are typically scaled simultaneously in order to optimize the electrical performance of the device.
As the size of MOSFETs and other devices decreases, the dimensions of source/drain regions, channel regions, and gate electrodes of the devices, also decrease. The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, with a thickness of about 30 nm to 100 nm, are generally required for acceptable performance in short channel devices. Silicon-on-insulator (SOI) technology allows the formation of high-speed, shallow junction devices. In addition, SOI devices improve performance by reducing parasitic junction capacitance.
In an SOI substrate, a buried oxide (BOX) film made of silicon oxide is formed on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known, one of which is Separation-by-Implanted Oxygen (SIMOX), wherein oxygen is ion implanted into a single crystal silicon substrate to form a BOX film. Another method of forming an SOI substrate is by wafer bonding, wherein two semiconductor substrates with silicon oxide surface layers are bonded together at the silicon oxide surfaces to form a BOX layer between the two semiconductor substrates.
Scaling CMOS devices has pushed the number of parameters out of a negligible region to the point of becoming a significant circuit design factors. One of the important device parameters is the short-channel control. Fully depleted silicon-on-insulator (FDSOI) devices are a new class of MOSFETs where the short channel control is achieved by making the transistor channel thin. Extremely thin Silicon-On-Insulator (ETSOI), is a fully depleted SOI transistor device that uses an ultra-thin silicon channel wherein the majority carriers are fully depleted (FD) during operation. Typically, the thickness of an ETSOI layer ranges from 3 nm to 20 nm. In an ETSOI device since the junction depth is essentially equal to the thickness of the ultrathin silicon channel a very shallow junction is achieved. Hence, ETSOI offers superior short channel control compared to conventional MOSFETs.
Unlike conventional MOSFETs, where high doping concentration in the channel is needed to control the short channel effects, in an ETSOI device there is no need to channel doping. This leads to better device matching in ETSOI devices compared to conventional MOSFETs due to the fact that there is no dopant-fluctuation effect in undoped channel ETSOI.
In addition, it is desired that the ETSOI device is fabricated with a thin buried oxide (BOX) and a back gate is formed underneath the BOX. The back gate can be formed for example by doping the substrate underneath the BOX. In an ETSOI transistor with a back gate and thin BOX, the electrical characteristics of the MOSFET can be controlled by applying a voltage to the back gate. By doing so, the threshold voltage of the ETSOI transistor is changed and as a result the transistor current in the off- and on-states is modulated.
Such modulation of the electrical characteristics of the MOSFET by a voltage applied to the back gate finds many applications, including power management, reduction in the chip-to-chip device variation, and fine tuning of the chips after manufacturing. Multiple Vt devices can also be achieved by applying different back bias at the back gate.
Generally, a prior art back gate butting the entire device including channel and source/drain regions, results in a large parasitic capacitance, i.e., (source/drain back gate overlap capacitance). This disadvantageously decreases the transistor speed and increases the power consumption.—This is also ok here, describes the problem with the prior art.
Referring to FIG. 1 a side cross-sectional view of an illustrative prior art MOSFET device 100 is shown formed on a semiconductor-on-insulator (SOI) substrate having a raised source/drain (S/D) 21, 22 formed atop the source and drain regions 11, 12. The illustrative structure forms a semiconductor FET device on the semiconductor-on-insulator (SOI) substrate having an extremely thin semiconductor-on-insulator layer (ETSOI). The ETSOI layer is deposited atop the buried oxide layer 25, the ETSOI layer having a thickness preferably ranging from 3 nm to 20 nm. The raised source regions and raised drain regions are formed on an upper surface of ETSOI layer 20 in which the semiconductor is present, and which are formed using an epitaxial deposition process. A back gate region 30 is formed underneath the buried oxide 20 for example by implanting dopant atoms into the substrate 40 and annealing.
The prior art ETSOI semiconductor device includes a back gate 30 butting across the entire device including a channel 10 and source and drain region 11,12.
The disadvantage of such a constructed device, particularly referring to back gate layer 30 is that it displays a significant parasitic capacitance between the back gate 30 and source and drain region 11, 12.
Several methods have been proposed in the art to reduce the parasitic capacitance between the back gate and the source and drain regions, such as a method for implanting fluorine atoms into the buried oxide region directly underneath the source and drain. However, due to finite scatter in the position of the fluorine ions, known as lateral implant straggle, some of the implanted atoms are also formed underneath the channel. This is especially important in deeply scaled MOSFETs where the spacing between the source and drain region, i.e. the channel length, has a length comparable to the thickness of the buried oxide.
Although it is known in the art the use of a back gate for a fully depleted SOI technology, as described above the parasitic capacitance between the back gate and the source and drain region is high. The prior art attempts to reduce the parasitic capacitance but it has not been found to be suitable for a deeply scaled MOSFET.
USPTO Backgrounds
USPTO Backgrounds