1. Field of the Invention
The embodiments presented herein generally relate to integrated circuit structures and more particularly, to methods and structures that utilize high pressure deuterium treatment to improve the interface quality of silicon germanium high-K insulators.
2. Description of Related Art
As integrated circuit structures such as transistors evolve, it has been discovered that placing physical strain (compression or tensile stress) upon the channel region of field effect transistors (FETs) can improve the performance of some types of transistors. Such stress producing or straining layers generally change their size as they cool, which produces the physical strain on the transistors.
Further advances in transistor technologies have developed dual stress liner applications where one type of transistor is covered where one type of strain producing layer and a complimentary type of transistor is covered with a different type of straining layer. For complete discussion of such dual stress liner features, see U.S. Pat. No. 7,525,162, incorporated herein by reference.
USPTO Backgrounds
USPTO Backgrounds