1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate having gate and data lines with a double-layered structure.
2. Discussion of the Related Art
In general, since flat panel display devices are thin, low weight, and have low power consumption, they are increasingly being used for displays for portable devices. Among the various types of flat panel display devices, liquid crystal display (LCD) devices are widely used for laptop computers and desktop monitors because of their superiority in resolution, color image display, and display quality.
LCD devices use the optical anisotropy and polarization properties of liquid crystal molecules to produce a desired image. Liquid crystal molecules have a definite intermolecular orientation that results from their peculiar characteristics. The specific orientation can be modified by an electric field that is applied across the liquid crystal molecules. In other words, electric fields applied across the liquid crystal molecules can change the orientation of the liquid crystal molecules. Due to optical anisotropy, incident light is refracted according to the orientation of the liquid crystal molecules.
Specifically, the LCD devices have upper and lower substrates with electrodes that are spaced apart and face each other, and a liquid crystal material is interposed therebetween. Accordingly, when a voltage is applied to the liquid crystal material by the electrodes of each substrate, an alignment direction of the liquid crystal molecules is changed in accordance with the applied voltage to display images. By controlling the applied voltage, the LCD device provides various transmittances for rays of light to display image data.
The liquid crystal display (LCD) devices have wide application in office automation (OA) and video equipment because of their light weight, thin design, and low power consumption characteristics. Among the different types of LCD devices, active matrix LCDs (AM-LCDs), which have thin film transistors and pixel electrodes arranged in a matrix form, offer high resolution and superiority in displaying moving images. A typical LCD panel has an upper substrate, a lower substrate and a liquid crystal material layer interposed therebetween. The upper substrate, commonly referred to as a color filter substrate, includes a common electrode and color filters. The lower substrate, commonly referred to as an array substrate, includes switching elements, such as thin film transistors (TFT's), and pixel electrodes, for example.
As previously described, operation of an LCD device is based on the principle that the alignment direction of the liquid crystal molecules is dependent upon an applied electric field between the common electrode and the pixel electrode. Accordingly, the liquid crystal molecules function as an optical modulation element having variable optical characteristics that depend upon polarity of the applied voltage.
As shown in FIG. 1, gate lines 33 are disposed in a transverse direction and data lines 53 are disposed in a longitudinal direction. The data lines 53 perpendicularly cross the gate lines 33 such that the crossing of the gate and data lines 33 and 53 defines a matrix of pixel regions P. A switching device such as a thin film transistor T is disposed in each pixel region P near a crossing of the gate and data lines 33 and 53. A gate pad electrode 35 is formed at the end of each gate line 33. This gate pad electrode 35 has a wider width than the gate line 33. A data pad electrode 55 is formed at the end of each data line 53, and similarly has a wider width than the data line 53. On each gate pad electrode 35, a gate pad terminal 71 is formed of a transparent, electrically conductive material. A data pad terminal 73 of transparent conductive material is likewise formed on each data pad electrode 55. The gate and data pad terminals 71 and 73 receive electrical signals by way of the external driving circuits.
In each pixel region P, a pixel electrode 69 is disposed so as to come into contact with the thin film transistor T. A storage capacitor C is also formed in a portion of each pixel region P. In each pixel region P in this example, the storage capacitor C is formed over the gate line 33 and is connected in parallel with the pixel electrode 69.
Each thin film transistor T includes a gate electrode 31 extending from the gate line 33, an active layer 39 formed of silicon, a source electrode 49 extending from the data line 53, and a drain electrode 51 contacting the pixel electrode 69. Meanwhile, the storage capacitor C includes a portion of the gate line 33 as a first electrode, a capacitor electrode 57 as a second electrode, and an insulator (not shown) disposed therebetween. The capacitor electrode 57 is formed of the same material as the source and drain electrodes 49 and 51 and communicates with the pixel electrode 69 through a storage contact hole 63.
In the related art shown in FIG. 1, the gate electrode 31 and the gate line 33 are generally formed of aluminum or aluminum alloy in order to prevent signal delay. Alternatively, the gate electrode 31 and the gate line 33 can be formed of a double-layer of an aluminum layer that can be formed of an aluminum alloy layer and an additional metal layer because the aluminum and aluminum alloy are weak at acid during the process. Furthermore, all of the source electrode 49, the drain electrode 51, the data line 53 and the data pad electrode 55 can also be formed of aluminum or aluminum alloy. At this time, an additional metal layer is also formed on the aluminum or aluminum alloy layer.
Now with reference to FIGS. 2A-2J and FIGS. 3A-3J, fabrication process steps of forming an array substrate will be explained in detail according to a related art. FIGS. 2A to 2J are cross sectional views taken along a line II-II′ of FIG. 1 and illustrates a process of forming a pixel according to the related art. FIGS. 3A to 3J are cross sectional views taken along a line III-III′ of FIG. 1 and illustrates a process of forming pads according to the related art. In the process shown in FIGS. 2A-2J and FIGS. 3A-3J, the gate line, the gate electrode and the gate pad electrode have a double-layered structure including aluminum. The aluminum in the gate line reduces the RC delay because it has a low resistance. However, aluminum is delicate to acidity and susceptible to developing hillocks during a high temperature manufacturing or patterning process, possibly resulting in line defects. For this reason, molybdenum or chromium is formed on the aluminum or aluminum alloy, thereby forming the double-layered structure as follows.
Referring to FIGS. 2A and 3A, aluminum (Al) or aluminum neodymium (AlNd) is deposited on a substrate 21, thereby forming a first metal layer 23a. Then, molybdenum is deposited on the first metal layer 23a, and thus a second metal layer 23b is formed. Thereafter, a photoresist layer 25 is formed on the second metal layer 23b of molybdenum. After forming the photoresist layer 25, a mask M having light-transmitting portions A and light-shielding portions B is disposed over the photoresist 25, and then a light exposure is performed to the photoresist 25. Thereafter, the photoresist 25 is developed to form a photoresist pattern on the double layer of first and second metal layers 23a and 23b. 
In FIGS. 2B and 3B, after developing the photoresist 25, photoresist patterns 27 remain and the second metal layer 23b is exposed. Thereafter, the substrate 21 having the photoresist patterns 27 is baked in an oven to form the semicircular shape as shown in FIGS. 2B and 3B.
Now referring to FIGS. 2C and 3C, the exposed portions of the second metal layer 23b and the underlay first metal layer 23a are etched under a wet etching process. Therefore, first and second metal patterns 29a and 29b are formed underneath the photoresist patterns 27. During the wet etching process, since the first metal layer 23a of aluminum or aluminum alloy is etched faster than the second metal layer 23b of molybdenum by the etching solution, the second metal patterns 29b overhang on the first metal patterns 29a, as shown in FIGS. 2C and 3C. This overhang phenomenon of the second metal patterns 29b causes the later-formed insulator to have deposition defects. Namely, if the insulator (not shown) is formed in a later step to cover the first and second metal patterns 29a and 29b of FIGS. 2C and 3C, the insulator may have defects caused by the overhanging brims of the second metal patterns 29b. 
To overcome this problem, an additional dry etch of the first and second metal patterns 29a and 29b is required. FIGS. 2D and 3D show the photoresist patterns 27, the first metal patterns 29a and the second metal patterns 29b after the dry etching process. The dry etch slightly removes and laminates the side portions of the photoresist patterns 27 and the side portions of the first and second metal patterns 29a and 29b. Therefore, the first and second patterns 29a and 29b have a smooth taper shape without any steps or overhangs on their sides.
After the dry etch process, the photoresist patterns 27 are stripped away as shown in FIGS. 2E and 3E. Therefore, the gate electrode 31, the gate line 33 and the gate pad electrode 35 are formed to have a double-layered structure of aluminum or aluminum alloy and molybdenum. As described in FIG. 1, the gate electrode 31 extends from the gate line 33 and the gate pad electrode 35 is at the end of the gate line 33.
Now referring to FIGS. 2F and 3F, a gate insulation layer 37 is formed on the substrate 21 to cover the double-layered gate electrode 31, line 33 and pad electrode 35. The gate insulation layer 37 is an inorganic material, such as silicon nitride (SiNX) or silicon oxide (SiO2). Thereafter, amorphous silicon (a-Si:H) and n+ doped amorphous silicon (n+a-Si:H) are sequentially formed on the gate insulation layer 37 and then patterned to form an active layer 39 and an ohmic contact layer 41 over the gate electrode 31.
Next in FIGS. 2G and 3G, third to fifth metal layers 43, 45 and 47 are sequentially formed on the gate insulation layer 37 to cover both the active layer 37 and the ohmic contact layer 41. Here, the third and fifth metal layers 43 and 47 are molybdenum (Mo) and the fourth metal layer 45 interposed therebetween is aluminum (Al). Therefore, the triple-layered structure of Mo/Al/Mo is disposed on the gate insulation layer 37.
Thereafter, the third to fifth metal layers 43, 45 and 47 are simultaneously patterned as shown in FIGS. 2H and 3H. Thus, a source electrode 49, a drain electrode 51, a data line 53, a data pad electrode 55 and a capacitor electrode 57, all of which have the triple-layered structure, are formed over the substrate 21. The source electrode 49 extends from the data line 53 and contacts the ohmic contact layer 41. The drain electrode 51 is spaced apart from the source electrode 49 and also contacts the ohmic contact layer 41. As mentioned with reference to FIG. 1, the data pad electrode 55 is at the end of the data line 53, and the capacitor electrode 57 is shaped like an island and disposed above the double-layered gate line 33. After forming the source and drain electrodes 49 and 51, a portion of the ohmic contact layer 41 between the source and drain electrodes 49 and 51 is removed to form a channel region.
Meanwhile, the source and drain electrodes 49 and 51 and the data line 53 can be formed of a single layer of molybdenum or chromium. However, doing so may result in signal delay in those electrodes and ion the data line such that it is hard to obtain uniform image quality all over the liquid crystal panel.
In contrast, when the source and drain electrodes 49 and 51 and the data line 53 include metal having a low resistance, such as aluminum, the electrical signals flow without the signal delay such that the array substrate can be fabricated in a large size. Therefore, the source and drain electrodes 49 and 51 and the data lines 53 herein include the aluminum layer therein. Further, when aluminum is used for the source and drain electrodes 49 and 51, the molybdenum layers are formed on both upper and lower surfaces of the aluminum layer. The third metal of molybdenum formed underneath the aluminum layer acts to prevent a spiking phenomenon in which the aluminum layer penetrates into the active layer 39 or the ohmic contact layer 41. The fifth metal of molybdenum formed on the aluminum layer acts to reduce contact resistance between the aluminum layer and a later-formed transparent electrode. For these reasons, the source and drain electrodes 49 and 51 and the data line 53 are formed to have the triple-layered structure of Mo/Al/Mo.
Now in FIGS. 2I and 3I, a passivation layer 59, which is an insulation material, is formed all over the substrate 21. The passivation layer 59 covers the source and drain electrodes 49 and 51, the data line 53, the data pad electrode 55 and the storage capacitor 57. By patterning the passivation layer 59, a drain contact hole 61, a storage contact hole 63, a gate pad contact hole 65, and a data pad contact hole 67 are formed. The drain contact hole 61 exposes a portion of the drain electrode, the storage contact hole 63 exposes a portion of the capacitor electrode 57, the gate pad contact hole 65 exposes a portion of the gate pad 35, and the data pad contact hole 67 exposes a portion of the data pad 55.
In FIGS. 2J and 3J, a transparent conductive material is deposited on the passivation layer 59 having the above-mentioned holes, and then this transparent conductive material is patterned to form a pixel electrode 69, a gate pad terminal 71 and a data pad terminal 73. The transparent conductive material is one of indium tin oxide (ITO) and indium zinc oxide (IZO). The pixel electrode 69 contacts the drain electrode 51 and the capacitor electrode 57 through the drain contact hole 61 and storage contact hole 63, respectively. Further, the gate pad terminal 71 contacts the gate pad 35 through the gate pad contact hole 65, and the data pad terminal 73 contacts the data pad 55 through the data pad contact hole 67. Accordingly, the array substrate of the related art is complete.
The above-mentioned process includes five mask processes. Further, the gate electrode 31 and the gate line 33 need to undergo the double-etching process (the wet etching process and the dry etching process). Therefore, the method of forming the array substrate according to the related art requires a lot of process time.
In the related art shown in FIGS. 2A-2J and 3A-3J, the source and drain electrodes 49 and 51, the data line 53 and the data pad electrode 55, all of which have the triple-layered structure, are formed by an etching solution that simultaneously etches aluminum and molybdenum. Thus, an electrochemical reaction, such as a Galvanic Reaction, will be caused by the etching solution during this etching process. As the molybdenum layer becomes thicker, it is much difficult to overcome the electrochemical reaction. During the etching process of patterning the third to fifth metal layers, the molybdenum layers disposed on the upper and lower surfaces of the aluminum layer are overetched. Especially, when the third molybdenum layer underlying the fourth aluminum layer is overly etched, the fourth aluminum layer collapses and contacts the active layer in the thin film transistor. The connection between the aluminum layer and the active layer will increase the leakage current and deteriorate the operating characteristics of the thin film transistor.
FIG. 4 is an enlarged cross-sectional view of a portion D of FIG. 2J and illustrates an overetching in the third and fifth metal layers of the drain electrode. As shown, the molybdenum layers 43 and 47 are overetched rather than the aluminum layer 45. This phenomenon of overetching also occurs in the source electrode 51, the data line 53 and the data pad electrode 55. The overetching of the molybdenum layers 43 and 47 causes the passivation layer 59 to not be formed properly over the substrate 21. Furthermore, the overetching of the molybdenum layer 43 causes the aluminum layer 45 to contact the active layer 39 and/or the ohmic contact layer 41 because the aluminum layer 45 is pressed by the passivation layer 59, thereby increasing the leakage current in the thin film transistor. The increase of the OFF current deteriorates the electrical characteristics of the thin film transistor.
USPTO Backgrounds
USPTO Backgrounds