The implementation of a logic design is traditionally divided into sub-problems including synthesizing a high-level description of the logic design into a list of nets connecting basic logic elements, placing the logic elements, and routing the nets between the placed logic elements.
Placement generally places connected logic elements close together to reduce implementation area and to increase the probability that routing can successfully complete the interconnections between the logic elements. In addition, placing connected logic elements close together generally improves implementation performance, because long interconnect paths have more capacitance and resistance, resulting in longer propagation delays.
Routing creates wiring for implementing the nets between the placed logic elements. Because placement attempts to place connected logic elements close together, routing will result in many nets with short wires. Short wiring is generally advantageous for routing. However, localized areas of dense wiring can prevent successfully routing some of the nets.
The present invention may address one or more of the above issues.
USPTO Backgrounds
USPTO Backgrounds