1. Technical Field of the Invention
The present invention relates to receivers for communications systems, and particularly to providing equalization to multiphase receivers in communications systems.
2. Description of Related Art
Receivers for handling information transported over a communications link generally fall into any of a number of different categories. In a single-phase communications receiver, a single decision circuit operates at the fill bit rate of the received signal in order to determine the state of each bit therein. Because the demands placed on the bandwidth of full bit rate decision circuits, such decision circuits are very difficult to design and implement, especially for high speed operation.
A multiphase communications receiver utilizes a plurality of decision circuits to determine the state of received signals. As shown in FIG. 1, the decision circuits D of a conventional multiphase communications receiver R sample the received signal at equally spaced phases of a clock signal. Each decision circuit D is adapted to operate at a fraction of the bit rate of the received signal.
Some communications links over which signals are transported, such as cable and/or copper traces disposed on a printed circuit board, exhibit low-pass frequency transfer characteristics. Because these low-pass frequency transfer characteristics may be very pronounced, equalization techniques have been utilized in receivers to prevent or reduce intersymbol interference caused by the pronounced low-pass frequency transfer characteristics.
Equalization, within the context of the present application, refers to optimizing the frequency response of the overall system for minimum intersymbol interference by compensating for an undesirable frequency response of the communication link. Equalization is typically performed by use of a decision feedback circuit for a single-phase receiver, or a filter. Because single-phase receivers operate at the full bit rate of the received signal, decision feedback circuitry for single-phase receivers are also undesirably required to operate at a higher bandwidth. Employment of passive filters, either in single-phase or multiphase receivers, is undesirable because the passive filter further attenuates the transmitted signal that has already been attenuated due to channel loss. The use of active or amplifying filter-type equalizers in multiphase receivers is also undesirable because amplifier circuitry operating at the full bit rate is difficult to achieve using existing technologies.
A prior equalizer is described in the paper entitled “A 0.3 um CMOS 8-Gb/s 4-PAM Serial Link Transceiver” by Ramin Farjad-Rad et al.1 The equalizer is described as a one-tap half-symbol-spaced FIR filter and is said to sharpen the transition edges of the transmitted signal in the time domain. However, the equalizer is relatively complex and the circuitry therefor may disadvantageously slow the operation of the receiver. 1 IEEE Journal of Solid State Circuits, vol. 35, no. 5, pp. 757–764 (May, 2000).
Based upon the foregoing, there is a need for a receiver with more effective equalization and, concomitantly, reduced intersymbol interference.
USPTO Backgrounds
USPTO Backgrounds