The present disclosure relates to the formation of semiconductor devices. More specifically, the disclosure relates to the formation of stair-step semiconductor devices.
During semiconductor wafer processing, stair-step features are sometimes required. For example, in 3D flash memory devices, multiple cells are stacked up together in chain format to save space and increase packing density. The stair-step structure allows electrical contact with every gate layer. Such stair-step structures may be formed by a plurality of alternating layers of silicon oxide and silicon nitride, where such stacks are designated as ONON stacks. ONON stacks may also be used to form other semiconductor devices in addition to stair-step semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds