Metal-oxide-semiconductor field-effect transistors (MOSFETs) are well-known. In particular, power MOSFETs have been commercialized and are expected to be widely used in power systems. For traditional MOSFET structures, such as power MOSFETs on Silicon Carbide (SiC), one potential issue is the presence of a high electrical field at the gate oxide in the center of the junction field effect (JFET) region of the device. A JFET region generally is an active portion of an N-type drift layer which may include an N-type dopant and is located between two P-type wells. The JFET region may refer to a region in contact with channel regions coming up to the surfaces of the P-type wells by applying a gate voltage. The JFET region makes up a conduction path for electrons with the N+ source region, the channel region, the N-type drift region, the substrate, and the drain electrode. Under operation conditions at which a high bias is applied to the drain (close to the operational maximum) and in which the gate is held near ground potential, a high electrical field is created in the gate oxide that sits just above the JFET region. Imperfections in the interface material and gate oxide could result in a gate oxide failure during long-term blocking operation, in which the drain is placed under a high positive bias. Second, traditional MOSFETs also may suffer from possible hot carrier injection during long-term blocking operation, in which the drain is placed under a high positive bias.
USPTO Backgrounds
USPTO Backgrounds