(a) Technical Field
The present invention relates to a Lateral Double Diffusion Metal-Semiconductor (LDMOS) device, and a method for manufacturing the same. More particularly, the present invention relates to an LDMOS device, which is configured to reduce an electric field concentrated to a gate oxide film, and lower ON-resistance produced when the device conducts a forward action, and a method for manufacturing the same.
(b) Background Art
Recently, as devices and application appliances employing one or more power semiconductor devices tend to become bigger and larger in terms of size and capacitance, there has been high demand for power semiconductor devices, such as an Insulated Gate Bipolar Transistor (IGBT) or a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). Further, there has been also a high demand for high efficiency power semiconductor devices.
Among the above-mentioned power semiconductor devices, an LDMOS type power device applicable to an integrated circuit has a channel region of an existing MOS device, and a low-concentration drift region durable against a high breakdown voltage. In particular, since a high voltage up to several hundred volts may be applied to a drain when the LDMOS type power device is operated, the drift region should maintain a high breakdown voltage, and an ON-voltage between the channel region and the drain should be low. Therefore, in order to obtain a high breakdown voltage at the drift region and a low ON-resistance, devices to with a Reduced SURface Field (RESURF) structure are developed, in which the RESURF structure is capable of reducing the surface field.
Conventional power devices with the RESURF structure involve devices with a source field plate structure, in which a source electrode extends from the source region to a part of the drift region, devices with a gate field plate structure, in which a source electrode extends from the gate region to a part of the drift region, and devices with a structure, in which p-type impurities are implanted into the surface of an n-type drift region. However, the above-mentioned conventional power devices cannot realize both of the high breakdown voltage and low ON-resistance.
An LDMOS transistor, which is a high voltage power device, has rapid switching velocity, high input impedance, low power consumption, compatibility with a Complementary Metal-Oxide-Semiconductor (CMOS) process, etc., and are widely employed in display drive Integrated Circuits (ICs), power converters, motor controllers, automotive power supplies, etc. In such a power device, specific ON-resistance and breakdown voltage are critical factors, by which the performance of the device is greatly influenced. As such, various technologies have been proposed for increasing the breakdown voltage while maintaining the ON-resistance.
FIG. 6 is a cross-sectional view showing a conventional LDMOS transistor structure. In FIG. 6, the LDMOS transistor includes, in a P-type substrate 100, a deep n-drift region 102 used as a drift region of the LDMOS transistor, a p-body 104, on the top of which a channel of the LDMOS transistor will be formed, an n+ source 106 and drain 108, a p+ source 110 for to body contact, a field oxide film 112 with a LOCal Oxidation of Silicon (LOCOS) structure, a gate oxide film 114, a drain electrode 116, and a source electrode 118.
In such a conventional LDMOS transistor, the length (LD) and doping concentration of the n-drift region are important factors for determining the ON-resistance and breakdown voltage of the device. That is, as the length of the n-drift region, LD, indicated by arrow in FIG. 6 increases, the breakdown voltage increases and the ON-resistance also increases, and as the concentration of the drift region increases, the ON-resistance decreases and the breakdown voltage also decreases. In other words, the length and concentration of the drift region have a trade-off relationship. As a result, with such a conventional LDMOS transistor structure, it is difficult to increase the breakdown voltage without increasing the ON-resistance.
Many reports have indicated that the breakdown voltage can be improved by forming a trench filled with an oxide instead of LOCal Oxidation of Silicon (LOCOS) as the field oxide film in the drift region of the LDMOS transistor. As an example, LDMOS transistors have been developed which exhibit an improved breakdown voltage without increasing the ON-resistance by forming a trench through etching of a silicon trench, gap-fill of an oxide film, and Chemical Mechanical Polishing (CMP) in the drift region of an LDMOS transistor instead of LOCOS (Won-So Son, Young-Ho Sohn and Sie-young Choi, “SOI RESURF LDMOS transistor using trench filled with oxide”, Electronics Letters, Vol. 39, pp. 1760-1761 (2003)).
However, due to the rather complicated steps involved in the above process, such as CMP, required for forming such a trench structure, the entire process becomes more complicated an expensive that most in the industry would desire.
USPTO Backgrounds
USPTO Backgrounds