The present invention relates to a method of producing capacitive elements for integrated circuits.
In densification of dynamic random access memories (DRAM), despite of the minimized area per bit a larger capacitance value per unit area is still required since the capacitance value of the capacitor for storing data is difficult to decrease because of limitation caused by a desired resistivity against alpha ray. A thinner insulating film for the capacitor may be applicable as a measure of avoiding the foregoing problem, notwithstanding a reduction of the insulating film thickness is limited. For a large capacity DRAM of four megabits or more, there has been proposed a method wherein the capacitance is obtained on the inside wall of the aperture provided in the substrate (trench capacitance) or the capacitance is obtained at the side wall of the capacitive electrode of a taller height (stack capacitance). Those methods, however, may not be applied for the DRAM of 64 megabits or more due to its excess depth and height. Thus, a method of employing laminated capacitive electrodes is proposed for the DRAM of 64 megabits or more to obtain the enlarged surface area of the stack capacitive electrodes but without increasing the height. An example of such structure includes "a memory cell having fin type capacitors" proposed by T. Ema et al at "the International Electron Devices Meeting" in 1988, the Meeting Papers, p. 592.
In FIG. 1, an installation of impurity on a silicon substrate 201 provides a silicon active layer 202. A layer-to-layer insulating film 210 made of silicon nitride and a spacer 211 made of silicon dioxide are sequentially deposited. With a contact aperture which reaches an active layer 202 and through the contact aperture there is provided a polysilicon capacitive electrode 214 forming a storage node electrode (so called fin) of memory cell capacitance connected to the silicon active layer 202.
In FIG. 2, the spacer 211 is selectively removed to expose the lower surface of the polysilicon capacitive electrode 214 and a capacitive insulating film 205 is formed on the entire exposed surface of the polysilicon capacitive electrode 214. A polysilicon capacitive electrode 204 is formed by a vapor phase growth procedure for embedding the periphery of the capacitive insulating film 205 and actuating as an opposing electrode to the polysilicon capacitive electrode 214 through the capacitive insulating film 205.
The polysilicon capacitive electrode 204 is a cell-plate electrode of memory-cell capacitance to be commonly connected to all the cells for fixing at a reference voltage. By this arrangement the polysilicon capacitive electrode 204 embraces the polysilicon capacitive electrode 214 from the above and below thereof to increase the capacitive value. Further, the capacitive insulating film 205 and the polysilicon capacitive electrode 204 may continuously be formed to produce a capacitive insulating film of high quality.
However, in the conventional method hereinbefore described, a part of the electrode, during its production process, has no support thereunder to float unstably in the atmosphere with a problem of weakened mechanical strength for the positioning. A high grade of capacitive insulating film is required to be formed in a narrower gap by a complete embedding with an electrode material. The production process, therefore, is not so conveniently that a thicker material with a wider gap are needed with limitation of the shape available to the electrode.
USPTO Backgrounds
USPTO Backgrounds