1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Background Art
With the recent trend toward low-voltage, down-sized semiconductor devices, reduction in source/drain resistance becomes important to increase the operating speed of MOS transistors and to improve current driving capability.
FIGS. 37 through 40 are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device in order of successive steps. An element isolation insulation film 102 formed of a silicon oxide film is first formed in an element isolation region of a silicon substrate 101 and a silicon oxide film 103 is formed on the main surface of the silicon substrate 101 in an element forming region. A polysilicon film 104 is then formed over the entire surface (FIG. 37). The polysilicon film 104 is patterned by photolithographic techniques to form a gate electrode 105 (FIG. 38).
The silicon oxide film 103 except that under the gate electrode 105 is removed to form a gate insulation film 106, and sidewalls 107 formed of silicon oxide films are formed on the side faces of the gate insulation film 106 and of the gate electrode 105. The exposed main surface of the silicon substrate 101 is doped with impurities by ion implantation. Following this, heat treatment is carried out to form source/drain regions 108 (FIG. 39).
After a cobalt film is formed across the surface by a sputtering method, cobalt silicide layers 109 and 110 are formed by heat treatment in the upper surfaces of the source/drain regions 108 and of the gate electrode 105, respectively. The unreacted cobalt film is then removed (FIG. 40). This will reduce the source/drain and gate resistances, thus increasing the operating speed of MOS transistors and improving current driving capability.
In this method of manufacturing a conventional semiconductor device, however, the cobalt silicide layers 109 are formed only in the upper surfaces of the source/drain regions 108 exposed from the sidewalls 107 and the gate electrode 105, so there is a problem that the effect of reducing the source/drain resistance may not be sufficient.
A first aspect of the present invention is directed to a semiconductor device comprising: a substrate; a gate structure selectively formed on a main surface of the substrate, having a laminated structure with a gate insulation film and a gate electrode stacked in this order; a sidewall formed on a side face of the gate structure; a source/drain region selectively formed in the main surface of the substrate, having an impurity concentration of over 1xc3x971019/cm3 under the sidewall; and a metal-semiconductor compound region formed in the main surface of the substrate, extending to a point at least under the sidewall from a portion of the source/drain region exposed from the gate structure.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, an end portion of the metal-semiconductor compound region on the gate structure""s side is located under an end portion of the gate structure.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, an end portion of the metal-semiconductor compound region on the gate structure""s side is located under the sidewall.
According to a fourth aspect of the present invention, in the semiconductor device of either of the first through third aspects, an end portion of the metal-semiconductor compound region on the gate structure""s side is located within the source/drain region.
A fifth aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: (a) selectively forming a gate structure on a main surface of a substrate, the gate structure having a laminated structure with a gate insulation film and a gate electrode stacked in this order; (b) forming an amorphous region in a portion of the main surface of the substrate where a metal-semiconductor compound region is to be formed; and (c) forming the metal-semiconductor compound region by silicidation of the amorphous region.
According to a sixth aspect of the present invention, in the step (b) of the method of the fifth aspect, the amorphous region is formed by implanting heavy ions into the substrate with the gate structure as a mask.
According to a seventh aspect of the present invention, in the method of the fifth aspect, the step (b) comprises the steps of: (b-1) forming a sidewall on a side face of the gate structure; and (b-2) implanting heavy ions into the substrate with the gate structure and the sidewall as masks.
According to an eighth aspect of the present invention, in the step (b) of the method of either the sixth or seventh aspect, the heavy ions are angularity implanted into the substrate with respect to a normal to the main surface of the substrate.
According to a ninth aspect of the present invention, the method of the fifth aspect further comprises the steps of: (d) forming a sidewall on a side face of the gate structure; (e) doping the substrate with impurities using the gate structure and the sidewall as masks; and (f) forming a source/drain region in the main surface of the substrate by thermal diffusion of the impurities in the substrate, wherein, in the step (b), the amorphous region is simultaneously formed by doping with the impurities in the step (e), wherein the step (c) is performed between the step (e) and the step (f).
According to a tenth aspect of the present invention, in the step (b) of the method of the fifth aspect, the amorphous region is formed by forming a sidewall on a aside face of the gate structure, the sidewall being made of a material that produces, with the substrate, such high stress that the substrate becomes amorphous.
An eleventh aspect of the present invention is directed to a method of manufacturing a semiconductor device, comprising the steps of: (a) selectively forming a gate structure on a main surface of a substrate, the gate structure having a laminated structure with a gate insulation film and a gate electrode stacked in this order; (b) forming a sidewall on a side face of the gate structure; (c) forming a depression by digging in a portion of the main surface of the substrate where the gate structure and the sidewall are not formed; and (d) forming a metal-semiconductor compound region by silicidation of the substrate from a surface of the depression.
According to a twelfth aspect of the present invention, in the step (c) of the method of the eleventh aspect, the depression is formed by isotropic etching of the substrate.
According to a thirteenth aspect of the present invention, in the method of the eleventh aspect, the step (b) comprises the steps of: (b-1) forming an insulation film on a structure obtained by the step (a); and (b-2) etching the insulation film by a high etch rate of anisotropic etching in a depth direction of the substrate, wherein, in the step (c), the depression is formed by the anisotropic etching.
According to a fourteenth aspect of the present invention, in the method of the eleventh aspect, the step (d) comprises the steps of: (d-1) forming a metal film on a surface of the depression by sputtering of a metallic material; and (d-2) inducing a reaction between the metal film and the substrate by heat treatment to form the metal-semiconductor compound region, wherein, in the step (d-1), the metallic material is angularity sputtered on the surface of the depression with respect to a normal to the main surface of the substrate.
According to a fifteenth aspect of the present invention, the method of the eleventh aspect further comprises: (e) digging in an upper surface of the gate electrode to a predetermined depth; and (f) after the step (e), forming a metal-semiconductor compound layer by silicidation of a resultant upper surface of the gate electrode.
According to a sixteenth aspect of the present invention, in the method of the eleventh aspect, the gate structure formed in the step (a) has a laminated structure with the insulation film, the gate electrode, and a mask insulation film stacked in this order. The method further comprises the steps of: (e) after the step (b), removing the mask insulation film; and (1) forming a metal-semiconductor compound layer by silicidation of an upper surface of the gate electrode exposed by the removal of the mask insulation film.
According to a seventeenth aspect of the present invention, the method of either of the fifth through sixteenth aspects further comprises the step of: (g) after the step (a), forming a source/drain region in the main surface of the substrate by doping the substrate with impurities using the gate structure as a mask, wherein an end portion of the metal-semiconductor compound region on the gate structure""s side is located within the source/drain region.
In the semiconductor device of the first aspect, the metal-semiconductor compound region having the effect of reducing the source/drain resistance is formed, extending to a point at least under the sidewall from a portion of the source/drain region exposed from the gate structure. The device thus has reduced sheet resistance in the source/drain region and improved propagation delay velocity, resulting in higher operating speed, and further has reduced source/drain resistance, resulting in improved current driving capability.
In the semiconductor device of the second aspect, the metal-semiconductor compound region having the effect of reducing the source/drain resistance is formed, extending to a point under the end portion of the gate structure from a portion of the source/drain region exposed from the gate structure. This enhances the effect of reducing the source/drain resistance, thus achieving higher operating speed and improved current driving capability.
In the semiconductor device of the third aspect, the nonexistence of the metal-semiconductor compound region under the gate structure prevents a short circuit through the gate insulation film in the gate electrode and in the metal-semiconductor compound region.
In the semiconductor device of the fourth aspect, the metal-semiconductor compound region is formed within the source/drain region. This suppresses leakage current flowing from the metal-semiconductor compound region to the substrate.
In the method of the fifth aspect, since silicidation is more likely to proceed in an amorphous region than in a single crystalline substrate, the metal-semiconductor compound region can appropriately be formed by silicidation of the amorphous region which was previously formed in a portion where the metal-semiconductor compound region is to be formed.
In the method of the sixth aspect, lateral scattering of heavy ions in the substrate causes an amorphous region to be formed even under the end portion of the gate structure. This allows the metal-semiconductor compound region to extend to a point under the end portion of the gate structure.
In the method of the seventh aspect, lateral scattering of heavy ions in the substrate causes an amorphous region to be formed even under the sidewall. This allows the metal-semiconductor compound region to extend to a point under the sidewall.
In the method of the eighth aspect, in order to form an amorphous region, heavy ions are angularity implanted into the substrate with respect to the normal to the main surface of the substrate. This increases the amount of extension of the amorphous region to a point under the gate structure or under the sidewall, as compared with the case where heavy ions are implanted almost in parallel to the normal to the main surface of the substrate.
In the method of the ninth aspect, by utilizing the fact that the amorphous region is formed together with the source/drain region by impurity doping, the metal-semiconductor compound region is formed before thermal diffusion of impurities in the substrate. This makes it easy to form the metal-semiconductor compound region which extends to a point under the sidewall from a portion of the source/drain region exposed from the gate structure and the sidewall.
In the method of the tenth aspect, a high stress between the substrate and the sidewall allows the formation of a crystal defect region in the substrate. This makes it possible to form the metal-semiconductor compound region which extends to a point under the sidewall or under the end portion of the gate structure.
In the method of the eleventh aspect, a metallic material used for the formation of the metal-semiconductor compound region is likely to adhere on the side faces of a depression. This encourages lateral silicidation, thus allowing the metal-semiconductor compound region to extend to a point under the sidewall.
In the method of the twelfth aspect, even a portion of the substrate under the end portion of the sidewall on the opposite side of the gate structure is etched to form a depression. This increases the amount of extension of the metal-semiconductor compound region to a point under the sidewall.
In the method of the thirteenth aspect, the depression is formed by the anisotropic etching for the formation of the sidewall. This facilitates the formation of a depression.
In the method of the fourteenth aspect, a metallic material can also adhere to the side faces of a depression properly.
In the method of the fifteenth aspect, the metal-semiconductor compound layer is formed after the upper surface of the gate electrode is dug to a predetermined depth. Thus, the upper surface of the metal-semiconductor compound layer is lower than the upper end portion of the sidewall. This prevents a short circuit in the metal-semiconductor compound layer and in the metal-semiconductor compound region.
In the method of the sixteenth aspect, the metal-semiconductor compound layer is formed after the removal of the mask insulation film. Thus, the upper surface of the metal-semiconductor compound layer is lower than the upper end portion of the sidewall. This prevents a short circuit in the metal-semiconductor compound layer and in the metal-semiconductor compound region.
In the method of the seventeenth aspect, the metal-semiconductor compound region formed within the source/drain region allows suppression of the leakage current flowing from the metal-semiconductor compound region to the substrate.
An object of the present invention is to provide a semiconductor device capable of further reducing source/drain resistance, thereby ensuring higher operating speed of MOS transistors and improved current driving capability, and also to provide a method of manufacturing such a semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds