Conventional negative bitline write assist (NBWA) circuits use a pull-down voltage to provide a negative voltage supply or a negative ground reference for a write driver on one of the bitlines coupled to a memory cell. Such techniques are useful in writing a zero (“0”) value into the memory cell storing a one (“1”) value at a first time and receiving a zero (“0”) value at a second time. The pull-down voltage can be provided by a capacitive structure as a step of a write operation. Conventional NBWA circuits often use a single voltage source as the pull-down voltage: a memory voltage or a core voltage. During operation, the single voltage source can vary significantly at any instant of time depending on local demands, conditions, and particular physical structures in the memory circuit. In some situations, the pull-down voltage is too low to provide a sufficient write assist to the memory cell resulting in a failed write to the memory cell. In other situations, the pull-down voltage is too high leading to other problems including causing stability issues on non-selected neighboring memory cells and reliability issues for the device.
Various solutions to these problems have been suggested. One solution is to add a bigger capacitive structure to boost the negative bitline. Such solution comes at the cost of a higher power requirement and higher capacitive area, which may not be physically adjustable in particular circuit architectures due to highly optimized placement of components within known memory circuits. Using a single voltage source with a bigger capacitive structure also does not address the problem inherent at the high source voltage condition.
USPTO Backgrounds
USPTO Backgrounds