1. Field of the Invention
The invention relates to a subfield coding circuit and a subfield coding method for converting R, G, and B image data into subfield-coded data in a plasma display panel.
2. Description of the Related Art
One of important characteristics required for a terminal unit such as a computer to have is a characteristic of displaying gradation.
In a display unit such as a cathode ray tube (CRT) which can be controlled in its operation in analogue manner, it would be possible to control an electron beam current by applying a voltage of an input signal to a grid without deforming a waveform of the voltage. Since a brightness is defined by an intensity of an electron beam current, it would be possible to continuously control gradation.
In a display unit which displays images in binary code, such as a plasma display unit which display images by means of memory effect, gradation is displayed in a particular way.
Hereinbelow is explained the above-mentioned particular way in which gradation is displayed in a plasma display unit.
For instance, it would be possible in a printer to apparently increase a number of gradation by means of error diffusion. However, the error diffusion is accompanied with a problem of little practicability, because it would be necessary to fabricate a cell having high definition, if both of desired gradation and desired resolution were to be accomplished.
In a display unit which displays images in a binary code, a subfield process is usually carried out for displaying images. A subfield process is applicable to a display unit having a high response speed, such as a plasma display unit. In a subfield process, an image signal is quantized or converted into a digital form from an analogue form, and then, data about obtained one field is displayed in time division in each of gradation bits.
In a subfield process, one field period is divided into a plurality of segmented fields each of which is called “subfield” and each of which weighted by the number of light emission in association with each of gradation bits. Then, images are successively reproduced by means of the thus obtained subfields, and images across one field are accumulated by visual integration effect. This results in images having natural intermediate gradation.
For instance, when an image is to be displayed in sixty-four gradation in a subfield process, an analogue image signal input into a display unit is quantized or analogue-to-digital converted into a brightness signal having six bits in association with gradation brightness data in which a brightness is different twice in a level from others.
The thus quantized image signal data is accumulated in a frame buffer memory. Assuming that the most significant bit (MSB) which means a bit having the highest brightness is represented as B1, and bits having lower brightness than the most significant bit are represented as B2, B3, B4, B5 and B6, a brightness ratio among those bits is represented as 32:16:8:4:2:1. Each of pixels selects one of those bits, and resultingly, an image can be displayed in sixty four gradation, that is, in the level of brightness 0 to brightness 63.
Hereinbelow is explained a subfield process, for instance, in AC type color plasma display unit in which scanning electrodes and sustaining electrodes are driven independently of each other, with reference to FIG. 1A.
One field is usually designed to be about one sixtieth in order to avoid flickers from appearing. As illustrated in FIG. 1A, one field is divided into six subfields, a first subfield SF1 to a sixth subfield SF6, each comprised of a scanning period and a charging period.
In a scanning period of the first subfield SF1, data is written into each of pixels in accordance with data about the uppermost bit B1. After data has been written into all pixels, a charge pulse is applied entirely to a panel for causing pixels into which data has been written, to emit a light.
Then, pixels are driven in the second subfield SF2 and the subsequent subfields SF3 to SF6 in the same way as the first subfield SF1.
In order to ensure a sufficient brightness, for instance, 256, 128, 64, 32, 16 and 8 pulses are applied to a panel for light emission in each of charging periods in the first to sixth subfields SF1 to SF6, respectively.
Pixels are driven substantially in the same way as mentioned above also in a process in which a scanning step and a charging step are carried out in combination, as illustrated in FIG. 1B, and in a process in which a scanning step and a charging step are successively carried out in combination across fields.
The reason of selecting a subfield process is necessity of modulating a brightness of an emitted light and the number of light emission with a period of time in which a light is emitted. In order to carry out scanning a plurality of times in one field, it is necessary to scan pixels and write data into pixels in a short period of time.
With significant progress in performance of writing data into a plasma display panel, it is now possible to write data in 3 microseconds or smaller. Thus, it is presently possible to display images in full color in 256 gradation by means of eight subfields.
In the above-mentioned subfield process, subfield coding is carried out for charging to sustain image signals.
FIG. 2 is a partial circuit diagram of a conventional subfield coding circuit to carry out subfield coding.
A subfield coding circuit is fabricated as one of circuits constituting a LSI, and, as illustrated in FIG. 2, is comprised of a first static random access memory (SRAM) 51, a second static random access memory 52, and a third static random access memory 53. Each of the first to third SRAMs 51 to 53 is designed to have one port and acts as a memory for carrying out subfield conversion.
The first SRAM 51 includes a look-up table (LUT) for red (R) signals, the second SRAM 52 includes a look-up table for green (G) signals, and the third SRAM 53 includes a look-up table for blue (B) signals. Data about subfield coding is written in advance into each of the first to third SRAMs 51 to 53 from an external memory (not illustrated) such as EEPROM.
As illustrated in FIG. 2, the first to third SRAMs 51 to 53 receive R, G and B image data, respectively. On receipt of the R, G and B image data, an address in the first to third SRAMs 51 to 53 is designated (herein, the address is common to the first to third SRAMs 51 to 53), and resultingly, subfield coding data is read out of each of the look-up tables included in the first to third SRAMs 51 to 53. As a result, subfield conversion is carried out to each of the R, G and B image data.
The thus subfield-converted R, G and B image data is output from the first to third SRAMs 51 to 53, as illustrated in FIG. 2.
The conventional subfield coding circuit illustrated in FIG. 2 is designed to include three look-up tables in association with R, G and B image data in order to carry out subfield conversion. As a result, the conventional subfield coding circuit unavoidably has high capacity as total capacity of the first to third SRAMs 51 to 53 in proportion to the number of look-up tables. This further results in a large size in a LSI including a subfield coding circuit, and an increase in fabrication costs.
Japanese Unexamined Patent Publication No. 6-276540 (A) has suggested a gamma correcting circuit including a first circuit which switches an input port among a first input terminal through which a red signal is input, a second input terminal through which a green signal is input, and a third input terminal through which a blue signal is input, concurrently switches an output port among a first output terminal through which a red signal is output, a second output terminal through which a green signal is output, and a third output terminal through which a blue signal is output, gamma-corrects a signal received through the switched input terminal, in accordance with a coefficient read out of a memory, latching circuits each of which is electrically connected to the first to third output terminals and which latches the input signal for a certain period of time, a clock circuit which transmits a clock signal as a reference signal, and a controller which transmits a control signal at a timing of one-third of the clock signal. The input and output ports in the first circuit are switched in accordance with the control signal transmitted from the controller. Each of the latching circuits latches the input signals until a signal is input into a final latching circuit. When a signal is input into the final latching circuit, each of the latching circuits all transmit signals.
Japanese Unexamined Patent Publication No. 8-56292 (A) has suggested an image processor which converts an input color image signal in a certain color space into an output color image signal in another color space, and outputs the converted color image signal. The image processor is comprised of tables each associated with each of colors in the output color image signal, and each used for converting the input color image signal into color data of the output color image signal, a data selector which repeatedly selects data associated with a color of the output color image signal, from the tables, and a color converter which converts the input color image signal into the output color image signal by means of data selected by the data selector.
Japanese Unexamined Patent Publication No. 10-124001 (A) has suggested a method of displaying gradation in a display unit, including the steps of dividing one field period into a plurality of subfields having a relative brightness ratio different from one another, and displaying an image having gradation in accordance with combination of brightness of each of the subfields. Assuming that the number of all gradation bits is equal to N wherein N is a positive integer equal to or greater than three, a subfield of a M-th gradation bit is arranged almost at the center of a time axis in all subfield periods. Herein, M is a positive integer, indicates an uppermost bit when M is equal to one, and is equal to or smaller than N. A subfield of at least two gradation bits among gradation bits other than the above-mentioned M-th gradation bit is divided into subfields presenting almost the same light-emission brightness, and the thus divided subfields are arranged at opposite sides of the subfield associated with the M-th gradation bit, in linear symmetry about the time axis.
Japanese Unexamined Patent Publication No. 2000-98959 (A) has suggested a display unit which divides a field into a plurality of subfields, and displays gradation by emitting a light and stopping light emission in a display period in each of the subfields. The display unit is comprised of first means for assigning optimal light-emission pattern to each of the subfields in order to suppress generation of pseudo-frame, based on data about image signals in a field period, and second means for converting image signals into light-emission pattern data in accordance with a control signal transmitted from the first means.
USPTO Backgrounds
USPTO Backgrounds