In current tuner systems digital processing is generally implemented in complimentary metal-oxide-semiconductor (CMOS) only processes. Additionally, in the tuner industry, as with many industries, there is a general trend to miniaturize and compact all circuitry onto a single circuit which is capable of accomplishing a manufacturer's design and performance goals. Accordingly, current tuner systems and their corresponding digital processing needs are normally implemented within a single circuit (e.g. CMOS) framework. Moreover, when design issues occur, solutions to these problems are sought within this single circuit framework.
Current analog-to-digital converters (ADCs) in tuner systems are also generally implemented in a CMOS only process. FIG. 1 illustrates a prior art CMOS implementation of an ADC architecture 100. Prior art CMOS ADC systems include sample and hold circuitry 110 which samples a varying analog input signal and then holds it for a particular amount of time while ADC 120 can implement processing. The converted signal is then sent to digital processing circuitry 130. Prior art ADCs which are implemented in CMOS processors generally implement sample and hold circuitry 110 using a switch 111 and a capacitor 112 such that when switch 111 closes, the capacitor 112 charges at which point switch 111 opens. In such prior art ADC systems, a designer is able to achieve a high resolution, e.g. a high number of effective bits, generally at low frequencies such as at a 200-300 megahertz sampling frequencies. One problem with such prior art systems is that there is a settling time involved within sample and hold circuitry 110 because switch 111 is resistive. Because of this, such systems cannot implement an acceptable sample and hold that can function at high frequencies, e.g. between 2.5 to 3.5 gigahertz.
Accordingly, when implementing an ADC at these higher frequencies, the ADC requires much quicker response within the sample and hold than is possible with the architecture of FIG. 1. In order to accomplish an ADC that is able to function at an acceptable rate, most prior art systems implement what is called a time interleaved approach which utilize multiple ADCs 120. A time interleaved method generally utilizes multiple parallel ADCs 120 where each ADC receives sample data from respective circuits 110 at pre-specified intervals within a sampling clock cycle. While this approach increases the response speed of ADC devices, such an approach creates further design problems. For example, such implementations may have errors introduced into the sample and hold circuitry which originates from switching noise of the digital processing circuitry 130. Additionally, if a device has multiple ADCs but has several slower sample and hold circuits (such as shown in FIG. 1), difficult timing issues arise when lining up the samples. Because of these timing problems, a designer must be extremely accurate in order to avoid errors. If timing errors occur at the ADC stage, such errors are generally not correctable in the digital processing circuitry 130. In some instances, an optional sample and hold circuit 140 may be implemented to assist in remedying these timing errors.
Attempts have been made to produce ADC systems which network at higher frequencies. For example, ADCs have been implemented on non-CMOS substrates at very high frequency sampling rates. However, such systems are generally not capable of achieving sufficiently high resolution (e.g. 2-3 effective bits) for applications that require a high number of effective bits to be transmitted for further digital processing. Further, such systems generally have higher power requirements then similar CMOS counterparts, which makes them unacceptable in many design applications.
USPTO Backgrounds
USPTO Backgrounds