1. Field of the Invention
The present invention relates to a multilayer wiring (interconnection) structure of a semiconductor integrated circuit and a method for producing the same, and particularly to a structure of a layer insulation film for electrically separating wirings of different layers and a method for producing the same.
2. Description of the Prior Art
Heretofore, in a multilayer wiring structure of a semiconductor integrated circuit, as shown in FIG. 1(a), a lower layer wiring 502 is disposed on a semiconductor substrate 501. An insulation film 510 is formed on the lower layer wiring 502, and an upper layer wiring 509 is connected to the lower layer wiring 502 through a through hole 508 which is made in the insulation film 510. The insulation film 510 is for electrically separating the upper and lower layer wirings. Therefore a single layer or plural layers of an insulation film such as a silicon oxide film, a silicon nitride film and the like which is produced by a chemical vapor deposition (CVD) method or a plasma CVD method. In recent years, with miniaturization and multiplication of layers in wiring patterns, there has been used a structure in which, for the purpose of flattening a surface, as shown in FIG. 1(b), an insulation film 504 formed by coating, for example, a glass film, an organosilicon compound film, a polyimide film and the like, is combined with insulation films 503 and 505 obtained by a CVD method or a plasma CVD method to be applied to a part of a layer insulation film.
For a method for forming a multilayer wiring of a semiconductor integrated circuit, there has been adopted a method for forming a multilayer wiring by: depositing a lower layer wiring metal such as aluminium by a sputtering method, etc., on the semiconductor substrate 501 on which elements are formed and in which contact holes are made; executing patterning process to the wiring metal by a photo-etching technique so as to form element electrodes, the lower layer wiring 502 and the portion intended to make a through hole, simultaneously, thereafter, growing layer insulation film 501, for example, by a plasma CVD method; and after making a through hole 508 in the portion formed by the lower layer wiring material, which portion is intended to make a through hole, by the photo-etching technique, depositing an upper layer wiring metal thereon by, for example, a sputtering method and the like, and executing a patterning process to the deposit by the photo-etching technique thereby forming connection portions on the upper layer wiring 509 and the through hole 508, simultaneously, so as to connect the upper and the lower layers to each other through the through hole. In recent years, with miniaturization and multiplication of layers in wiring patterns, for the purpose of flattening the surface, an insulation film 504 formed by coating, for example, a glass film, an organosilicon compound film, a polyimide film and the like, is applied to a part or the whole of the layer insulation film. For example, in Japanese Patent Laid-open No. 100,748/82, No. 124,246/83, and No. 295,437/87, there is proposed a method in which a glass film formed by coating and a multilayer constitution of insulation films obtained by a CVD method or an SiO.sub.2 film formed by coating an organosilicon compound is used.
In recent years, the increase in the operation speed is remarkable in integrated circuits. In active elements constituting the integrated circuit, the operation speed of the integrated circuit is adopted to be increased by decreasing parasitic resistance and increasing a cutt-off frequency by means of miniaturization of the size and the shallower junction of the p-n junction portion. However, even if the size of the element is miniaturized, the current required to the high speed operation cannot be decreased from a standpoint of the driving capability. Therefore, the thickness and the width of the wiring film cannot be decreased below the limit restricted with respect to the reliability due to resistance to electromigration, etc.
On the other hand, with the high speed operation, the rate of the signal delay within the chip has been increased due to the load of the wiring. The load of the wiring is determined by the resistance of the wiring itself and the parasitic capacitance of the wiring. In order to decrease the resistance of the wiring, a large cross sectional area of the wiring is required. This is an impediment to miniaturization. Also, in order to decrease the capacitance of the wiring, the dielectric constant of a layer insulation film is required to be low, below a certain limit for the reason described above. However, since all the properties demanded, such as insulation property, chemical stability, resistance to moisture, coating property and the like, must be satisfied in the layer insulation film of the integrated circuit, the material having low dielectric constant cannot be always used as a substitute for the CVD insulation film which is widely used.
Next, applying the CVD film is applied to the layer insulation film in the conventional method for forming the multilayer wiring is considered. Since the single layer of the CVD film generally has a property in which unevenness of the ground and the lower layer wiring is increased, when the thickness of the lower layer wiring metal is set to over 1.0 .mu.m, the coating property of the upper layer wiring at the steps of the lower layer wiring deteriorates and the yield and reliability of the semiconductor integrated circuit drop. Also, it is difficult to miniaturize the circuit. The CVD films which are frequently used for layer insulation films of integrated circuits are a silicon nitride film, a silicon oxide film and the like. The dielectric constant .epsilon.' of the silicon nitride film is nearly equal to 8 and the dielectric constant .epsilon.' of the silicon oxide film is nearly equal to 4. Therefore, the wirings wiring capacitance tends to be an obstacle to a high speed operation.
On the other hand, when a glass film, an organosilicon compound film, a polyimide film or the like obtained by a coating method is applied to a part or the whole of the layer insulation film, excellent flatness can be realized. In these coated films, the dielectric constant .epsilon.' is generally smaller than that of the CVD film. The films of which dielectric constant .epsilon.' is equal to 2 to 3 can be easily obtained. Therefore, these coated films are also advantageous from a viewpoint of a wiring capacitance. When the film formed by coating has been exposed upon making a through hole for connecting the upper and lower layer wirings to each other, it is feared that moisture and the like are released due to dehydration condensation reaction of the coated film from the exposed portions and the wiring material suffers corrosion. Such films are short of stability and reliability. In order to avoid such disadvantages, when etching back process is applied to the coated film over the entire surface thereof for the film not to be left on the lower layer wiring, only the thickness of the coated film corresponding to the steps of the ground remains except for wiring portions. Therefore, sufficient use of the advantage of a small dielectric constant cannot be made.
USPTO Backgrounds
USPTO Backgrounds