The present invention relates to a compound semiconductor device which can be turned on/off by an MOS gate and which has saturation characteristics. It also relates to an electric power converting apparatus using such a device.
Hitherto, a semiconductor device in which a thyristor is controlled by an MOS gate and a current of the thyristor is controlled by saturation characteristics of an MOSFET has been disclosed in IEEE, "Electron Device Letters", Vol. 11, No. 2, pages 75 to 77, February, 1990. FIG. 9 shows the compound semiconductor device disclosed in FIG. 1 of the above paper. In the diagram, reference numeral 10 denotes a semiconductor substrate having a pair of main surfaces 100 and 101. A p.sup.+ layer 11, an n.sup.- layer 12 formed on the p.sup.+ layer 11, and a p layer 13 and a p.sub.1.sup.+ layer 130 which are formed on the n.sup.- layer 12 and whose surfaces are exposed to the main surface 101 are formed between the pair of main surfaces 100 and 101. An insulating gate 300 comprising an insulating film 31 and a gate electrode 32 are formed on the main surface 101. An n.sub.1.sup.+ layer 15 and an n.sub.2.sup.+ layer 16 are respectively independently formed in the main surface 101 while extending from the main surface 101 into the p layer 13 so as to reach the portions under the insulating gate 300. The p.sub.1.sup.+ layer 130 having a high carrier density is formed under the n.sub.2.sup.+ layer 16, thereby reducing a resistance r of the p layer. The p.sub.1.sup.+ layer 130 and the n.sub.2.sup.+ layer 16 are short-circuited by a cathode electrode 22. An anode electrode 21 is in ohmic contact with the main surface 100. The above compound semiconductor device has therein a thyristor comprising a pnp transistor which is constructed by the p.sup.+ layer 11, n.sup.- layer 12, and p layer 13; and an npn transistor which is constructed by the n.sup.- layer 12, p layer 13, and n.sub.1.sup.+ layer 15. The device also has the insulating gate 300 and an n channel MOSFET comprising the n.sub.1.sup.+ layer 15, p layer 13, and n.sub.2.sup.+ layer 16. Further, the device has a parasitic thyristor, as a parasitic element, comprising the n.sub.2.sup.+ layer 16, p.sub.1.sup.+ layer 130, n.sup.- layer 12, and p.sup.+ substrate 11. FIG. 10 shows an equivalent circuit of the compound semiconductor device of FIG. 9. The operation principle will now be described hereinbelow with reference to FIGS. 9 and 10. First, to turn on the compound semiconductor device, a negative potential is applied to a cathode terminal K and a positive potential is applied to an anode terminal A. The positive potential is applied from the cathode terminal K to a gate terminal G, thereby forming an inversion layer at the surface of the p layer 13 under the insulating gate. Thus, the n.sub.1.sup.+ layer 15 and n.sub.2.sup.+ layer 16 are short-circuited.
In such a state, a base current (hole current .sym.) is further supplied from the cathode terminal K to the p layer 13. A potential difference occurs between both edges of the resistor of the p layer 13 and the p.sub.1.sup.+ layer 130 by the hole current. When the potential difference exceeds a diffusion potential (about 0.7 V at a room temperature in case of silicon) of the p layer 13 and n.sub.1.sup.+ layer 15, electrons .crclbar. are implanted from the n.sub.1.sup.+ layer 15 into the p layer 13. When the electrons .crclbar. pass through the n.sup.- layer 12 and flow into the p.sup.+ layer 11, a great number of holes .sym. are implanted from the p.sup.+ layer 11 into the n.sup.- layer 12. When the hole current reaches the p layer 13 and flows into the cathode electrode 22, the electrons .crclbar. are further implanted from the n.sub.1.sup.+ layer 15 and the thyristor comprising the n.sub.1.sup.+ layer 15, p layer 13, n.sup.- layer 12, and p.sup.+ layer 11 is ignited (latched up), so that the compound semiconductor device is turned on.
To turn off the compound semiconductor device, it is sufficient to eliminate the potential at the gate terminal G. For instance, by short-circuiting the gate terminal G and the cathode terminal K, the inversion layer on the surface of the p layer 13 under the insulating gate is extinguished and the supply of the electrons .crclbar. which are implanted from the n.sub.1.sup.+ layer 15 into the p layer 13 is shut off. Consequently, the implantation of the holes .sym. from the p.sup.+ layer 11 is also stopped and the compound semiconductor device is turned off.
It is a feature of such a compound semiconductor device that by using the thyristor operation, a great amount of electrons .crclbar. and holes .sym. are implanted into the n.sup.- layer 12 of a high resistance to thereby reduce the resistance of the layer 12, and a loss of resistance upon conduction which occurs in the compound semiconductor device can be significantly decreased. Moreover, (although a gate structure to supply the hole current to the p layer 13 at the time of turn-on is not described in detail in the foregoing paper), there are features such that the device can be easily turned on or off by applying or eliminating the potential to the insulating gate 300, eliminating the necessity for a large amount of current to be supplied or pulled out by the gate, for instance, which is normally required for a conventional gate turn-off (GTO) thyristor. As such, the gate circuit is greatly simplified. Further, the electrons .crclbar. which are implanted from the n.sub.1.sup.+ layer 15 can be limited by using the output characteristics (called saturation characteristics) in which the insulating gate 300 and the MOSFET comprising the n.sub.1.sup.+ layer 15, p layer 13 (p.sub.1.sup.+ layer 130), and n.sub.2.sup.+ layer 16 are saturated. The current limiting action due to the saturation characteristics can be provided in spite of the fact that the compound semiconductor device executes the operation of the thyristor. In the power semiconductor device, ordinarily, the structure of FIG. 9 is used as one cell and a large number of such cells PG,6 (for example, hundreds of cells to tens of thousands of cells) are integrated and are operated in parallel. In this instance, if each cell has the current limiting action, the current is not concentrated to one cell and each cell uniformly bears the share of the current, so that a breakdown of the power semiconductor device due to the current concentration can be prevented. Since the compound semiconductor device has the current limiting action in spite of the fact that the device executes the thyristor operation, a uniform current flow without current concentration can be realized in the ON state. In addition, even at the time of turn-off, the current of each cell can be uniformly reduced and a large current can be also easily shut off.
The above compound semiconductor device, however, has a problem such that it is difficult to implant the electrons .crclbar. from the n.sub.1.sup.+ layer 15 and to ignite. That is, although the n.sub.1.sup.+ layer 15 is short-circuited to the cathode electrode 22 through the inversion layer of the insulating gate 300 and the n.sub.2.sup.+ layer 16, the resistance of the inversion layer is so large as to be a few k.OMEGA. as a sheet resistance. Such a resistance obstructs the current supply of the electrons .crclbar. which are implanted from the n.sub.1.sup.+ layer 15. In other words, when a potential difference between the p layer 13 and the n.sub.1.sup.+ layer 15 reaches the diffusion potential or higher and the implantation of the ions .crclbar. from the n.sub.1.sup.+ layer 15 is started, the potential of the n.sub.1.sup.+ layer 15 becomes higher than that of the n.sub.2.sup.+ layer 16 due to the electron current and the resistance of the inversion layer. Thus, the potential difference between the n.sub.1.sup.+ layer 15 and the p layer 13 decreases, the implantation of the electrons .crclbar. from the n.sub.1.sup.+ layer is suppressed, and it becomes difficult to ignite. To prevent such a problem, there is a method of increasing the resistance R of the p layer 13. However, when a carrier density of the p layer 13 is reduced and the p layer is made thin in order to increase the resistance R, a new problem is created that the depletion layer extending in the p layer 13 reaches the n.sub.1.sup.+ layer 15 and punch through occurs, thereby deteriorating the withstanding voltage. To prevent such a problem, a method of increasing the resistance R by extending the n.sub.1.sup.+ layer 15 in such a direction as to be away from the cathode electrode 22 is considered. In such a case, another problem occurs. Namely, there is a problem that latch-up can be easily occur in the n.sub.2.sup.+ layer 16, p.sub.1.sup.+ layer 130, n.sup.- layer 12, and p.sup.+ layer 11 which exist as a parasitic thyristor. An extremely large amount of holes .sym. which reach from the p.sup.+ layer 11 and an extremely large amount of holes .sym. generated so as to satisfy the neutral conditions of the electrons .crclbar. which had been implanted from the n.sub.1.sup.+ layer 15 exist in the p layer 13 because the p.sup.+ layer 11 is wide due to the foregoing reasons. All of such holes .sym. pass through the p.sub.1.sup.+ layer 130 and flow into the cathode electrode 22. In this instance, although the p.sub.1.sup.+ layer 130 has a low resistance r due to a high carrier density, since a hole current which flows into the layer 130 is large, a large potential difference occurs across the resistor r. When such a potential difference is equal to or higher than the diffusion potential of the p.sub.1.sup.+ layer 130 and n.sub.2.sup.+ layer 16, the parasitic thyristor latches up. Once the parasitic thyristor latches up, the compound semiconductor device cannot be turned off by the insulating gate 300 any more and the current continuously flows. Finally, the apparatus is broken by the current and a Joule heat which is generated due to the conduction loss.
In the conventional compound semiconductor device as mentioned above, the large resistance of the inversion layer and the operation of the parasitic thyristor has not been adequately considered. Therefore, the device is difficult to ignite, and is easily broken down.
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