The present invention relates to field effect transistors (FETs) and more particularly to heterostructure field effect transistors (HFETs) such as, for example, GaN HFETs.
FIG. 5 schematically shows a cross section of a conventional GaN power HFET fabricated in accordance with the disclosure of a literature entitled “Normally-off AlGaN/GaN HEMT with Recessed Gate for High Power Applications” (Extended Abstracts of the 2005 International Conference on Solid State Devices and Materials, Kobe, pp. 206-207). In the GaN power HFET, a buffer layer 2002, a channel layer 2003 composed of undoped GaN and a layer 2004 composed of Al0.25Ga0.75N are stacked on a sapphire substrate 2001 in this order. A Ti/Al source ohmic contact 2006 and a Ti/Al drain ohmic contact 2008 are formed on the Al0.25Ga0.75N layer 2004. The Al0.25Ga0.75N layer 2004 has a recess 2010 formed by the process of etching, and a Schottky gate electrode 2007 is formed in the recess 2010.
The GaN power HFET is of the n-channel “normally off” type, which means that the gate threshold voltage is equal to or greater than 0 V.
The threshold voltage of the conventional HFET described above depends on the thickness of the AlGaN layer 2004 remaining between the Schottky gate electrode 2007 and the undoped GaN channel layer 2003.
The thickness of the AlGaN layer 2004 remaining beneath the Schottky gate electrode 2007 varies due to recess etching because the etching rate is difficult to control accurately. Therefore, disadvantageously, there is some variation in the threshold voltage between different devices at different positions on the same wafer and also between different parts of an individual FET especially when the FET has a broad area.
USPTO Backgrounds
USPTO Backgrounds