Digital-to-analog (DA) conversion is a technique for converting information expressed in digital format into analog signals. Digital-to-analog converters (DAC) is indispensable for digital electronic equipment that need to process information obtained in the form of analog signals. As is known, voice, audio and video signals, information closely related to our daily life, are inherently analog in form. Contemporary technologies have, however, employed digital form for the processing and storage of these most-used information. For example, a music Compact Disc (CD) player retrieves sound information stored on a CD in digital format for playback. Before this high-fidelity music can be played back, however, its retrieved digital representation must be converted into analog electrical signal that can be used to drive a loudspeaker system. Good digital-to-analog conversion is crucial to high-fidelity music playback.
In another example, an LCD (liquid crystal display) panel of a computer system also requires similar digital-to-analog conversion. Much like a pair of loudspeakers is to the ears of a music lover, the LCD panel is the instrument for presenting visual information to the operator/user of the computer. Information in the form of either text, graphics or video to be displayed on the LCD panel is stored and processed in the computer system in digital. To drive the transistors in a matrix that correspond to the screen pixels of a TFT LCD, the digital display information must be converted into analog.
Two categories of DAC, the resistor and capacitor DAC's, are frequently used for such DA conversion. Resistor DAC (hereafter referred to as RDAC) are relatively simpler to make but consume static power. Electric power is consumed across the resistor of the RDAC even as the converter is in static status. By contrast, capacitor DAC (CDAC) are inherently more complex to fabricate, and their operation require more precise timing control, but they consume virtually no static power, which is an important characteristics of advantage in portable electronic devices.
There are in general three causes of wrong voltage levels in a CDAC that lead to conversion inaccuracy. The first is the voltage difference between CDAC capacitor and gate input of the output buffer. The second is caused by charge injection for CDAC control signal. The third cause is charge injection from output buffer node voltage transition. In general, the conversion accuracy of a CDAC is greatly affected by the charge sharing and the charge injection phenomena inherent to CDAC.
To overcome these problems and increase CDAC conversion accuracy, a straight-forward solution is the use of large capacitors in CDAC in order to secure large capacitance. Unfortunately, large capacitors increase die sizes for these CDAC. As the conversion voltage increases, this problem becomes even more significant. This prevents the successful application of CDAC in applications such as TFT LCD because conversion voltage required in TFT driver circuitry is typically high.
For the purpose of the description of the invention, it suffices to examine the circuit configuration of the conventional CDAC devices and the principle problems they encounter. FIG. 1 is a schematic diagram of a conventional N-bit CDAC with an output buffer. The illustration of FIG. 1 also outlines the charge sharing problem these conventional CDAC have.
As is seen in the drawing, an N-bit CDAC converter 100 is essentially consisted of a converter capacitor network 110 and an output buffer 120. Output of the capacitor network 110, as extracted at node 112, is connected to input of the buffer 120. The capacitor network 110 requires a total of 2N capacitors C1, C2, . . . , C2N and 2N+1 MOS switches, including the low and high input switches SL and SH, as well as the 2N−1 network switches S1, S2, . . . , S2N−1. All the 2N+1 MOS switches are connected in a series chain at their respective source/drain, with the two, SL and SH respectively for the low and high input voltages VL and VH, at each of the far ends of the chain controlling the input to the converter capacitor network 110.
Each of the 2N capacitors has its one electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain. For example, capacitor C2 has an electrode connected to the node where switches S1 and S2 are connected together at their respective source/drain terminals. The other electrode of all the capacitors are tied together to a common node—the common ground node in the example of the system. All the 2N capacitors need to be constructed within a specified tolerance to the same capacitance.
For the N-bit CDAC 100 of FIG. 1 to achieve high-precision digital-to-analog conversion, at least two problems, charge injection and charge sharing, must be handled properly. FIG. 1 itself schematically outlines the charge sharing problem in the N-bit CDAC. The output buffer 120 coupled to the N-bit capacitor network 110 introduces an inevitable input capacitance, as is schematically represented by the equivalent capacitor 125, to the system such that the analog voltage as converted by the converter capacitor network 110 becomes essentially drifted away at the output node 128 of the buffer 120. In order to reduce this drift, larger capacitors must be used. However, larger capacitors lead directly to increased device surface area.
On the other hand, FIG. 2 is a schematic diagram of the capacitor network of a conventional N-bit CDAC outlining the problem of charge injection. Charge injection into the capacitors C1, C2, . . . , C2N of the converter capacitor network 210 is caused by junction coupling across the gate-source and/or gate-drain terminals while any of the MOS devices SL, S1, S2, . . . , S2N−1, SH are switching. This charge injection phenomenon is schematically illustrated in the drawing by the capacitance CGS and CGD of the equivalent gate-source and gate-drain capacitors CGL, CG21, CG22 and CGH connected across the gate and either source or drain of a MOS switch device. This charge injection is sometimes considered a clock feedthrough, a phenomenon in which the gate control signal applied to a MOS switch of a converter capacitor network is coupled across its equivalent gate-source or gate-drain capacitance into the network capacitor.
Traditionally, two approaches have been employed to tackle this charge injection problem. The first utilizes a companion switch for each of the converter MOS switches that has half the size of its master device. The companion switch is controlled to operate against its master so as to cancel the charge injection introduced by the activation of the master utilizing its own inherent injection. However, the only function of the additional companion switch is the provision of a cancellation injection of charge for its master and nothing else. Overall circuitry complexity and device size are substantially increased as a result of this additional device.
A second approach employs the concept of a transmission gate for each of the MOS switch devices of the converter. A device of the reverse polarity as that of the switch whose charge injection was to be cancelled is connected in parallel. When both devices functions, the reversed injections cancels each other. However, this approach not only requires an additional MOS devices for each switch in the converter, there were also introduced additional problems of mismatched CGS/CGD capacitance for the pair.
Thus, as the charge injection and sharing problems are not effectively resolved in the prior-art CDAC, it is therefore an object of the invention to provide a CDAC that resolves these problems simultaneously.
It is another object of the invention to provide a CDAC that is free from the charge injection and sharing problems while is simple to construct.
It is still another object of the invention to provide a CDAC that is free from the charge injection and sharing problems while is low in cost to construct.
USPTO Backgrounds
USPTO Backgrounds