1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having an SOI (silicon on insulator) structure.
2. Description of Related Art
As a semiconductor device having an SOI structure, an SOI substrate having a structure in which two wafers are bonded together is known. In such a structure, a wafer of a support substrate and a wafer of an active layer substrate are bonded together with a buried oxide film interposed therebetween.
On the other hand, in a general semiconductor device, impurities such as heavy metal have an adverse effect on device properties during a manufacturing process of the semiconductor device. Therefore, it is necessary to carry out a gettering to eliminate the impurities. In the general semiconductor device composed of a single silicon substrate, internal defects existing in the silicon substrate function as gettering sites for gettering metal impurities. However, in the above-described substrate having the SOI structure, the buried oxide film exists between the support substrate and the active layer substrate. Therefore, the impurities mixed during the manufacturing process do not diffuse into a lower portion of the buried oxide film, which makes it impossible to obtain sufficient gettering ability. FIG. 2 schematically shows this state.
As shown in FIG. 2, in a general Si substrate, the metal impurities can be trapped at the gettering sites formed in the Si. On the other hand, the buried oxide film in which diffusion coefficients of metals are small exists in the SOI substrate. Therefore, the metal impurities mixed into the active layer side are not trapped by the gettering sites on the support substrate side and the metal impurities are accumulated in a thin active layer region. When the accumulated metal impurities reach a gate oxide film, a gate oxide film defect occurs such as bonding leak or deterioration in withstand voltage of the gate oxide film. As a way to overcome this problem, Japanese Unexamined Patent Application Publication No. 2006-5341 discloses a technique that injects dopant for forming gettering sites in an active layer substrate.
In the technique disclosed in Japanese Unexamined Patent Application Publication No. 2006-5341, the gettering sites are formed in the active layer which forms a device. However, when the gettering sites are formed above the buried oxide film as in this technique, the withstand voltage deteriorates in the device having a fully-depleted SOI structure in which a depletion layer reaches the buried oxide film.
Another technique is disclosed in Japanese Unexamined Patent Application Publication No. 5-346592. In this technique, a silicon single crystal layer is thinned and a device such as a transistor is formed in this thinned layer. Japanese Unexamined Patent Application Publication No. 5-346592 discloses a technique for forming a TFT (Thin Film Transistor) by forming the device on a silicon wafer, thinning the silicon wafer, and then bonding the thinned silicon wafer to a glass substrate.
However, in the technique disclosed in Japanese Unexamined Patent Application Publication No. 5-346592, defects may occur in the single crystal silicon layer which is around an interface between the glass substrate and the single crystal silicon. Therefore, an increase in leak current or deterioration in withstand voltage of the device occurs in the device having a perfect depletion type structure as in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2006-5341.
When the semiconductor device having the SOI structure is formed, the impurities that are mixed during the manufacturing process cannot sufficiently be gettered due to the provision of the buried oxide film, which may cause an adverse effect on the device properties.
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