1. Field of the Invention
The present invention relates to monolithic ceramic capacitors, and more particularly, to facilitating control of the equivalent series resistance (ESR) of a monolithic ceramic capacitor including external terminal electrodes including a resistive component.
2. Description of the Related Art
In a power supply circuit, when a voltage change in a power supply line increases due to the impedance existing in the power supply line and ground, the operation of circuits to be driven may become unstable, interference between the circuits may occur via the power supply circuit, and oscillation may occur. To avoid these problems, a decoupling capacitor is often connected between the power supply line and the ground. The decoupling capacitor reduces the impedance between the power supply line and the ground and suppresses changes in the power supply voltage and interference between the circuits.
Recently, the speed of processing signals has been increased in communication apparatuses, such as mobile phones, and information processing apparatuses, such as personal computers, in order to process a large amount of information. Accordingly, the clock frequency of an integrated circuit (IC) used has been increased. Noise including many harmonic components is likely to be generated. Thus, stronger decoupling must be provided in the IC power supply circuit.
Use of a decoupling capacitor with an excellent impedance frequency characteristic is effective to increase the decoupling effect. Such a decoupling capacitor includes a monolithic ceramic capacitor. Since the equivalent series inductance (ESL) of the monolithic ceramic capacitor is small, the monolithic ceramic capacitor can absorb noise over a broad frequency band better than an electrolytic capacitor.
Another function of the decoupling capacitor is to supply a charge to the IC. The decoupling capacitor is usually provided near the IC. When there is a change in the voltage of the power supply line, the decoupling capacitor quickly supplies a charge to the IC, thereby preventing a delay in the activation of the IC.
When a capacitor is charged or discharged, a counterelectromotive force (CEMF) dV expressed by the equation dV=L·di/dt is generated in the capacitor. A large dV results in a delay in supplying a charge to the IC. Since the clock frequency of the IC has been increased, the amount of change in current per unit time di/dt tends to increase. That is, the inductance L must be reduced in order to reduce dV. To reduce the inductance L, the ESL of the capacitor must be further reduced.
A known example of a low-ESL monolithic ceramic capacitor with a reduced ESL is an LW-inverted monolithic ceramic capacitor. In a general monolithic ceramic capacitor, the size in a two-dimensional surface in which ceramic layers extend of two end surfaces of a capacitor body on which external terminal electrodes are provided, that is, the width of the capacitor body, is less than the size in the two-dimensional surface in which the ceramic layers extend of two side surfaces of the capacitor body, that is, the length of the capacitor body. The side surfaces are adjacent to the end surfaces. In contrast, in the LW-inverted monolithic ceramic capacitor, the width of the capacitor body is greater than the length of the capacitor body. Since a current path in the capacitor body of such an LW-inverted monolithic ceramic capacitor is wide and short, the ESL is reduced.
Another known example of a low-ESL monolithic ceramic capacitor is a multi-terminal monolithic ceramic capacitor. In the multi-terminal monolithic ceramic capacitor, there is a plurality of current paths in a dispersed arrangement in a capacitor body, and thus, the ESL is reduced.
In low-ESL monolithic ceramic capacitors, as has been described above, a current path is widened and shortened, or a plurality of current paths are utilitzed in the dispersed arrangement. As a result, the ESR is reduced at the same time.
In contrast, monolithic ceramic capacitors are required to have an increased capacitance. In order to increase the capacitance of a monolithic ceramic capacitor, the number of ceramic layers and the number of internal electrodes that are laminated on one another may be increased. In this case, the number of current paths is increased, and thus, the ESR is reduced.
That is, there is an increased demand on monolithic ceramic capacitors to have a reduced ESL and an increased capacitance. In order to meet these demands, the ESR of the monolithic ceramic capacitors must be further reduced.
When the ESR of a capacitor is reduced too much, impedance mismatching occurs in a circuit, and thus, it is known that damped oscillation called “ringing” in which the rising portion of a signal waveform is distorted is likely to occur. When the ringing occurs, a distorted signal may cause a malfunction of the IC.
When the ESR of a capacitor is reduced too much, the impedance frequency characteristic of the capacitor becomes too steep near the resonant frequency. That is, the valley of an impedance curve becomes too steep. Accordingly, noise may be difficult to be absorbed over a broad frequency band.
Ringing can be successfully prevented or the impedance frequency characteristic can be successfully broadened by connecting a resistive element in series to the line. In recent years, capacitors have been required to have a resistive component. Attention has been paid to techniques of controlling the ESR of capacitors.
For example, Japanese Unexamined Domestic Patent Application Publication No. 2004-47983 and Japanese Unexamined PCT Patent Application Publication No. 2006/022258 disclose ways of controlling the ESR by including a resistive component in external terminal electrodes electrically connected to internal electrodes. In particular, Japanese Unexamined PCT Patent Application Publication No. 2006/022258 describes a monolithic ceramic capacitor including external terminal electrodes including a resistive component, which is formed by soaking a capacitor body in a resistive paste including a resistive material, such as an indium tin oxide (ITO), for example, and baking the resistive paste applied on the capacitor body.
When the external terminal electrodes include a resistive component, such as in Japanese Unexamined Domestic Patent Application Publication No. 2004-47983 and Japanese Unexamined PCT Patent Application Publication No. 2006/022258, the ESR of the capacitor can be controlled by adjusting the resistivity of the resistive material or by adjusting the thickness of the resistive paste that is applied.
It is troublesome to prepare a plurality of types of resistive pastes in order to adjust the resistivity of the resistive material. When the composition of a resistive paste is changed in order to adjust the resistivity, other factors, such as the reactivity with the internal electrodes or the fixing strength to the capacitor body, may be adversely affected.
In order to adjust the thickness of a resistive paste that is applied, the viscosity of the resistive paste must be adjusted. In this case, the above-described other factors may be affected as a result of changing the composition of the resistive paste. A thick application of a resistive paste is technically limited, and thus, there is a limit to controlling the ESR to be increased.
USPTO Backgrounds
USPTO Backgrounds