1. Field of the Invention
The present invention relates to the field of integrated circuit (IC) manufacturing.
2. Prior Art
Vertical feedthroughs are heavily used in 3D IC technologies wherein multiple ICs are stacked and packaged as a single circuit board device. Typical feedthroughs used in embedded wafer level or panel level packaging technologies use through silicon vias (TSVs) or holes drilled or etched through the substrate that are filled or lined with a metal layer that is insulated from the substrate. Feedthroughs are also currently made with Cu pillars in WLP (wafer level processing) technology. While these techniques provided for compact wiring, cross talk (inductive and capacitive) between densely pack TSVs (through silicon vias) is becoming a problem, in part because of the nature of the signals being transferred and in part because of the density of the feedthroughs needed to accommodate the number of such signals.
Feedthroughs are also currently made with Cu pillars in WLP (wafer level processing) technology and drilled vias filled with Cu are used in embedded wafer level or panel level packaging technologies.
The prior art solution addresses only coaxial through silicon vias to reduce inter TSV coupling. (See “High RF Performance TSV Silicon Carrier for High Frequency Application”, Soon Wee Ho et al, 2008 Electronic Components and Technology Conference.) No mention of Coaxial connections using Cu pillar or embedded die technology has been found in the prior art.
Thus the problem to be solved is to eliminate or at least substantially reduce the electrical and magnetic cross talk between through vias commonly used in 3D integration technologies.
USPTO Backgrounds
USPTO Backgrounds