This invention relates to a technique for eliminating transmit memory underruns, particularly upon start-up.
In computer systems, it is common to employ a transmit memory such as a transmit first-in-first-out memory (FIFO) for storing data to be transmitted. In most designs, the transmitter would start the transmission of data from the transmitter FIFO after one byte of data has been written into the FIFO. If another byte of data is not written into the transmit FIFO during the time required for the first byte of data to be transmitted by the transmitter, the transmitter will underrun and the frame sent will be corrupted, so that the frame needs to be re-sent. The failure to write a second byte after the first is written can be caused, for example, by the fact that control of the data bus may be preempted by another function in the computer system, such as by the receipt of data originating from a remote location. The problem is particularly acute at high data rates where the instantaneous response time of the microprocessor or direct memory access controller (DMA) is longer than the time it takes to transmit one byte of data. Normally the FIFO allows for this because the peak data transfer rate into the FIFO is much higher than the rate at which the transmitter transmits data. However, when the FIFO is not at least partially filled as in a start-up situation, the microprocessor may receive an interrupt (such as when data is received) or the DMA may lose control of the data bus, after a first byte of data is written into an otherwise empty FIFO. In such events, where the instantaneous response time of the microprocessor or DMA is longer than the time it takes to transmit one byte of data, the transmitter is likely to underrun. It is therefore desirable to provide a system for transmitting data which is not subject to the above-described problems.
USPTO Backgrounds
USPTO Backgrounds