1. Field of the Invention
The present invention relates generally to CMOS image sensors, and more particularly to pixel circuits for imaging System-on-Chip (iSoC) sensors capable of imaging under a variety of lighting conditions including low light.
2. Description of the Related Art
Visible imaging systems implemented using CMOS image sensors significantly reduce camera cost and power while improving resolution and reducing noise. The latest cameras use CMOS iSoC sensors that efficiently marry low-noise image detection and processing with a host of supporting blocks including timing controller, clock drivers, reference voltages, A/D conversion and key signal processing elements. High-performance video cameras are now produced using a single CMOS integrated circuit supported by only a lens and battery. These improvements translate into smaller camera size and longer battery life. The improvements also translate to dual-use cameras that simultaneously or successively produce high-resolution still images and high definition video.
The advantages offered by system-on-chip integration in CMOS visible imagers for emerging camera products have spurred considerable effort to further improve active-pixel sensor (APS) devices. Active-pixel sensors with on-chip analog and/or digital signal processing provide temporal noise superior to scientific-grade video systems using CCD sensors.
Most currently available image sensors use an architecture wherein the pixel establishes the sensor's intrinsic sensitivity and base ISO speed per Industry Organization for Standardization specification ISO 12332-2006, which is used for determining the standard exposure index for electronic image sensors. In order to boost sensitivity or ISO speed, amplifiers downstream of the pixel normally amplify the nominal pixel sensitivity. This approach typically degrades dynamic range for video applications or exposure latitude for still capture use. Post-pixel amplification also raises the requisite gain-bandwidth requirement for the signal processing chain and thereby often increases sensor noise. Consequently, while the sensitivity-based ISO speed is set higher, the noise-based ISO speed often actually degrades. In-camera signal processing is hence used to reduce the noise in trade for actual resolution.
FIG. 1 illustrates a four transistor (4T) pixel circuit of the prior art that is supported with correlated double sampling in the iSoC for low-noise imaging in rolling shutter designs. In operation, the reset transistor M1 is reset to clear the charge from the pixel. In this circuit, the pixel signal is stored as a charge on a floating diffusion (shown as CFD). The readout transistor M3 reads out a first signal from the pixel. This first signal is not photo-generated signal from the photodiode, but is instead reset noise associated with circuit operation. Then the transfer transistor M4 transfers a charge from the photodiode PD1 to the floating diffusion CFD, which in turn is amplified by the amplifier transistor M2, configured as a source-follower. The signal is then read out by the readout transistor M3. The two signals are differenced to efficiently remove the reset noise component. This process is repeated on a row-by-row basis for each row in an image sensor array.
This basic circuit requires four transistors for each pixel cell and the floating diffusion sets the nominal sensitivity for the pixel and image sensor. Prior to any amplification in the column buffer, the detector voltage, Vdet, generated by reading out the photodetector immediately after a specific integration time, tint, is:
      V    det    =            Q              C        FD              =                            i          det                ⁢                  t          int                            C        FD            
Typically, any required boost in sensitivity is normally accommodated by post-pixel amplification. For example, FIG. 2 is a column buffer circuit taught in U.S. Pat. No. 5,892,540 and fully incorporated herein by reference; it provides: 1) a multitude of selectable gain settings to boost or decrease sensitivity along with: 2) a means for supporting the correlated double sampling required for subtracting reset noise; and 3) column buffer dc offset nonuniformity cancellation. Unfortunately, particularly under condition of the higher gain settings and for high frame rate applications such as high definition television, the requisite gain-bandwidth product of the amplifier stages can be especially challenging to support and thereby generate nonlinearity, excess noise, or other artifacts. Furthermore, generation of excess white noise is likely since gain is applied after signal is transferred to the column buffer.
USPTO Backgrounds
USPTO Backgrounds