1. Technical Field
The present invention relates in general to computational methods utilized in analyzing circuits and in particular to a method, program, and data processing system that can efficiently and accurately measure delays in an RC circuit. Still more particularly, the present invention relates to a method, program and data processing system that can efficiently and accurately measure interconnect delays in an RC circuit to permit optimization of circuit designs.
2. Description of the Related Art
Faster performance and predictability of responses are elements of interest in circuit designs. As process technology scales to the sub-micron regime, interconnect delays increasingly dominate gate delays. Consequently, physical design optimization tools such as floorplanning, placement, and routing are becoming more xe2x80x9ctiming-drivenxe2x80x9d than the previous generation of tools. For such a tool to be effective, it must be able to efficiently compute interconnect delay since several million delay calculations are required to optimize a design.
In certain types of circuits, delays exist based on circuit topology and circuit components. Delays are particularly acute in circuits having resistive and capacitive elements, or RC circuits, as they are called in the art. Circuit designers continually search for efficient techniques for accurate estimation of these delays, while determining the particular circuit""s response to a load. In particular, circuit designers want to be able to calculate reliable delay information when designing the circuit. To this end, several prior art metrics (i.e., computational methods) have been developed.
The Elmore delay metric, which calculates the first moment of the impulse response, is the most widely applied and simplest interconnect delay metric that still captures some amount of metal resistance effects. The Elmore metric provides an upper bound on delay given any input waveform because the RC circuit impulse response is unimodal and positively skewed. The Elmore delay metric is commonly utilized for performance optimization tasks such as floorplanning, placement, buffer insertion, wire sizing in part and global routing. The widespread use of the Elmore delay metric is due to its closed form expression, fast computation speed, and fidelity with respect to simulation. Closed form delay equations, such as Elmore delay metric, are certainly preferable due to both efficiency and ease of implementation, as long as they are sufficiently accurate.
Despite its wide usage, the Elmore delay metric is known to be extremely inaccurate at times because it ignores the resistive shielding of downstream capacitance. For example, in a simple RC network as shown in FIG. 3, the Elmore delay to capacitor, C1, is independent of the resistors (R2 to R10). The higher the value of the resistors, the more downstream capacitance is shielded, i.e., the larger the error is for the Elmore approximation. Particular values may be chosen for the various circuit elements in FIG. 3, which results in arbitrarily large errors when analyzed with the Elmore delay metric. Errors of up to several hundred percent have been recorded when the Elmore delay metric is utilized for sub-micron technologies. Errors from Elmore delay metric are generally much more pronounced for near-end nodes (nodes relatively close to the power source) than for far-end nodes (nodes relatively far from the power source) since resistive shielding is not as much of a factor for far-end nodes.
To achieve greater accuracy than the Elmore delay metric can provide requires additional moments of the impulse response. However, moment matching does not directly produce a delay approximation, but rather a reduced order response, which can be solved via nonlinear iterations. These iterations tend to dominate the runtime of the entire delay computation method. Thus, several prior art methods have sought to circumvent iterations by proposing delay approximations metrics that are direct functions of the circuit moments.
Several of the other traditional metrics are known to be more accurate but are either CPU intensive or difficult to implement. For example, (1) moment matching via asymptotic waveform evaluation (AWE) is very accurate but too computationally expensive to use within a tight optimization loop, (2) two-pole variants of AWE are considerably faster and recognized to be more accurate than the Elmore delay metric, but are still relatively expensive, as Newton-Raphson iterations need to be run to find a solution. Also, their solutions may be unstable, i.e., poles may be positive; hence special care has to be taken to ensure stability, (3) xe2x80x9cfirst order delay estimatexe2x80x9d, which is derived from the dominant pole and corresponding residue, also requires subsequent Newton- Raphson iterations; (4) PRIMO, which fits the moments of the impulse response to probability density functions utilizing a table lookup operation; (5) h-gamma metric which subsumes PRIMO by avoiding time-shifting the distribution functions and matching moments to the circuit""s homogenous response; and (6) scaled Elmore delay metric, which shifts the Elmore approximation and the error but does not change the relative delay error problem.
Thus, there are inherent drawbacks with using the various metrics currently available for measuring delays in RC circuits. The present invention recognizes the need for greater reliability and accuracy in computing delays in a RC circuit of any topology. A method and program product and/or data processing system, which allows for efficient, reliable and non-complex computation of delay in an RC circuit to permit optimization in circuit design would be a welcome improvement. These and other benefits are presented in the present invention.
An efficient method for optimizing RC circuit design to reduce delay is disclosed. The method comprises: calculating a first moment and a second moment of impulse response for an RC circuit; (2) computing a delay value for each node of the RC circuit utilizing the first and second moments by multiplying the natural logarithm of 2 with a division of the squared power of the first impulse moment by the square root of the second impulse moment; and (3) analyzing each node to determine if the delay at that node is at a desired optimization condition for optimizing the circuit response.
In one preferred embodiment, the calculations may be utilized for optimization of the circuit design. When a node has a greater delay than the desired optimization condition, the circuit components may be changed or adjusted so that the circuit yields the desired optimization condition.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
USPTO Backgrounds
USPTO Backgrounds