1. Field of the Invention
The present invention relates to a clock recovery circuit for recovering a clock signal from a change in the data transmitted from a device.
2. Description of the Related Art
When data is transmitted at such a high speed as 1 gigabits/sec, pulses are delayed or reflected and signal pulses interfere with reflected pulses. The delay or reflection of pulses and the interference of pulses result from the characteristics of the receiving and transmitting circuits used or from the characteristics of the transmission path connected to the transmitting and receiving devices and including connectors. Inevitably, a skew develops between the time the data arrives and the time the clock signal arrives, in the receiving device. The skew makes it difficult to determine the contents of the data received in the receiving device. To determine the contents of the data, the technique called “clock data recovery (CDR)” is employed. In CDR, the transmitting device does not transmit a clock signal, and the receiving device recovers the clock signal from a high-to-low or low-to-high level transition of the data received.
In the CDR, the receiving device cannot recover the clock signal if no level transition has occurred in the data received. To cause a level transition in the data, the communications standard that puts importance on reliable data transmission describes that the transmitting device should encode the byte data into 10-bit codes, each containing at least one high-level bit and at least one low-level bit, before starting serial transmission of the data.
Here arises a problem. If the data is so encoded, the data-transmitting efficiency will decrease to 80%. Thus, the communications standard that imposes importance on high data-transmitting efficiency describes that the data bytes should be transmitted in series. Such communications standard allows for a so-called “consecutive identical digit (CID) period,” in which bits of the same level, high or low, follow one after another.
The phase difference between the clock signal recovered and the data received increases with time if the clock signal generated in the transmitting device and the clock signal generated in the receiving devices may have different frequencies. In view of this, a tolerance is set for the clock frequency of the clock generator provided in the transmitting device. A tolerance is set for the clock frequency of the clock generator provided in the receiving device, too. These tolerances are of such values that the phase difference between the clock signals generated in the transmitting device and receiving device, which occurs during the longest CID period possible, is ½ bit or less for all bits that form the serial data.
Jpn. Pat. Appln. KOKAI Publication No. 4-127737 discloses a related technique. More precisely, this publication teaches a clock-generating circuit that can output a complete clock signal even if some bits are missing in any input signal that has been supplied from a transmitting device.
This clock-generating circuit may generate a clock signal the frequency of which exceeds the preset tolerance, because of the characteristics different from the designed ones or because of changes in temperature or voltage. If the CID period is based on statistical data, it may exceed the longest CID period at a particular probability. Consequently, the contents of the data received cannot be accurately determined.
To make matters worse, the data received has fluctuation known as “jitter.” The jitter lowers the reliability of the data even if the receiving circuit that receives the data operates at so high a precision as described in the standard.
USPTO Backgrounds
USPTO Backgrounds