The disclosed embodiments of the present invention relate to power amplification, and more particularly, to a multi-stage digitally-controlled power amplifier.
A polar transmitter offers some advantages, such as a potential for reducing complexity and current consumption in the modulator path as well as eliminating the problem of image rejection, thus the polar transmitter is more suitable for implementation in advanced complementary metal oxide semiconductor (CMOS) processing technologies. More specifically, the polar transmitter is a transmitting device that splits a complex baseband signal explicitly represented by an amplitude-modulated (AM) contented component and a phase-modulated (PM) contented component, instead of an explicit in-phase component and a quadrature component. These two orthogonal components are then recombined into a radio-frequency (RF) output signal to be transmitted over the air.
An all-digital radio-frequency (RF) transmitter front-end circuit may be employed by the polar transmitter to enhance power efficiency, reduce the hardware cost and reduce the chip size. One conventional implementation of the all-digital RF transmitter front-end circuit is a digitally-controlled power amplifier (DPA), acting as an RF digital-to-analog converter (RF-DAC). The DPA may include a plurality of DPA cells for combining the AM signal and the PM signal and delivering an integral signal having a desired RF carrier frequency and a required power level. Therefore, how to arrange and control these DPA cells to achieve the desired DPA functionality is a significant concern in the pertinent field.
Regarding a conventional design of a DPA cell, a high-efficiency switching-mode (inverse class-D/class-E) power amplifier is employed. However, current switching-mode DPAs are inductor-loaded. Thus, due to the inherent characteristics of the inductor-loaded switching-mode amplifier, the voltage swing will be greater than π×VDD, where VDD is the supply voltage. To reduce the voltage swing, a lower supply voltage VDD must be used. For example, a DC-DC converter and/or a low-dropout (LDO) regulator may be used to convert a high DC voltage provided by a battery into a low supply voltage VDD needed by the DPA. Unfortunately, the battery efficiency would be degraded due to the power conversion.
Besides, the AM sampling using a periodic sampling clock would introduce out-of-band (OOB) noise/replica. One conventional solution to reduce the OOB noise/replica is to use a higher sampling rate. However, this would lead to larger power consumption. Another conventional solution is to use a higher digital-to-analog converter (DAC) resolution. However, this would have layout and physical limit. Yet another conventional solution is to use an RF bandpass filter. However, such an RF bandpass filter has a low quality factor and consumes a large area.
Thus, there is also a need for an innovative DPA cell design which has improved efficiency and can effectively reduce the undesired OOB noise/replica.
Moreover, due to the feedback path established by magnetic coupling and/or direct coupling (e.g., coupling via the printed circuit board (PCB) ground and/or the package ground), the transmitter output may be fed back to a clock source in the transmitter, which may degrade the transmitter performance. Thus, there is also a need for a pulling mitigation mechanism employed to improve the transmitter performance.
USPTO Backgrounds
USPTO Backgrounds