The present invention relates to a data retaining circuit such as a latch circuit. More particularly, the present invention relates to a data retaining circuit that reduces the occurrence of soft errors due to alpha rays, neutrons and so forth.
The semiconductor devices used in space or in aircraft have a problem of the occurrence of soft errors due to radioactive rays such as alpha rays, neutrons and so forth. Recently, semiconductor devices have been developed into those with higher integration and lower voltages, resulting in a problem that the occurrence of soft errors due to radioactive rays begins to have influence even on semiconductor devices used on the ground.
FIG. 1 is a diagram that shows the relationship between the amount of critical charge and the soft error rate due to alpha rays and neutrons in a latch circuit that is manufactured in 0.35˜im process and operates at 3.3V. The soft error rate is expressed by 1 FIT=1 error/109 device time. As shown schematically, when the amount of critical charge is equal to or less than 75 fC, the occurrence frequency of soft errors due to alpha rays is high and when the amount of critical charge is equal to or greater than 75 fC, the occurrence frequency of the soft errors due to neutrons is high. The amount of critical charge of a latch circuit that is manufactured in 0.35·m process and operates at 3.3V is approximately 150 fC, therefore, the problem of soft errors due to neutrons is more serious in this circuit. Devices used in space equipment or in aircraft have problems such as an increase in the failure rate of pacemakers in an aircraft. It is obvious that the increase in the occurrence of soft errors due to radioactive rays can be expected also in the semiconductor device used on the ground and the influence cannot be neglected if the structure of a semiconductor device becomes finer in the near future. Moreover, not only neutrons but also alpha rays are expected to bring about a problem of soft errors. With the above-mentioned fact as the background, countermeasures against the soft errors are required in various fields of the semiconductor device.
Although the occurrence of soft errors in a memory can be detected and corrected by providing redundant bits, countermeasures against soft errors are required also in logic circuits. In logic circuits, a data retaining circuit such as a latch circuit has largest influence when soft errors occur therein. Even if the data in such as a combinational circuit is temporarily reversed, it returns to the original one as long as the data in the former stage is not reversed, therefore, the range of the influence can be limited, but if the retained data is reversed and retained as it is the reversed data propagates and produces a far-reaching influence. Because of this, the countermeasures against soft errors in a data retaining circuit are especially required and the present invention relates to countermeasures against soft errors in a data retaining circuit.
FIG. 2A and FIG. 2B are diagrams that illustrate the mechanism of occurrence of soft errors. As shown in FIG. 2A, a transistor comprises a gate G, a source S and a drain D, and a channel is formed between the source and the drain under the gate and a depletion layer E is formed around the source and the drain. When particles such as alpha rays and neutrons enter the drain region of the transistor, many pairs of holes and electrons are generated on the trajectory of the particles due to the collision with atomic nuclei. At this time, the shape of the depletion layer becomes enlarged by the pairs of hole and electron. This region is called the funneling region F.
In the depletion layer and funneling region, electrons and holes move by drifting as shown in FIG. 2B. As movement by drifting is performed at a high speed, one group of generated charges quickly moves in the direction toward the drain, as a result. Electrons and holes generated in other than the depletion layer and the funneling region move by diffusion, but movement by diffusion is performed at a lower speed than that by a drift, therefore, almost all of the pairs of holes and electrons disappear, in pair annihilation, by annihilating each other, but part flows into the depletion layer and the funneling region and moves by drifting in the direction toward the drain.
The direction of movement of electrons is different from that of holes in NMOS and in PMOS, that is, electrons flow into the drain node in NMOS and holes do so in PMOS. At this time, when the amount of charge that flows into the drain node is larger than the amount of critical charge of the node, a phenomenon occurs in which the data retained by the transistor is reversed, which is called a soft error. In a MOS transistor, a soft error occurs characteristically in such a way as to reverse from a high logical level (data: 1) to a low logical level (data: 0) in NMOS, and in such a way as to reverse from a low logical level (data: 0) to a high logical level (data: 1) in PMOS because of each structure.
As samples of countermeasures against the soft errors in a data retaining circuit, K. Joe Hass, Jody W. Gamples: ‘Mitigating Single Event Upsets From Combinational Logic” 7th NASA Symposium on VLSI Design 1998 has disclosed the circuit as shown in FIG. 3, and U.S. Pat. No. 6,026,011, the circuit as shown in FIG. 4. Each circuit has a structure in which the node that retains the latched data is divided into a portion composed only of NMOS and the other portion composed only of PMOS, each having the same data and correcting the retained data for each other, the characteristic that only errors from 1 to 0 occur in NMOS and only those from 0 to 1 occur in PMOS being taken into consideration. Because each has the same data, soft errors occur only in one of them and the errors do not occur in the other, therefore, the data in which the error occurs is corrected by the data in the other portion where no error occurs.
To put it concretely, in the circuit in FIG. 3, when input data D is 0, data PP and NN to be taken in are also 0, and QP and QN become 1 and an output Q becomes 0. In this case, PP retained in the data retaining section composed of a PMOS has a possibility of the occurrence of a soft error of changing from 0 to 1, and QN retained in the data retaining section composed of an NMOS has a possibility of that of changing from 1 to 0, but it is unlikely that NN and QP reverse, When QN changes from 1 to 0, the NMOS transistor of the output section turns off, the PMOS transistor of the output section is off because QP is 1, and the output Q enters a state of floating, but the data does not reverse because of the parasitic capacitance. Then QN is brought back to the original data 1 due to NN and QP, therefore, the normal state returns. As for PP, it is also brought back to the original data 0 due to NN and QP. When the input data D is 1, there is a possibility that a soft error occurs in NN and QP, but since no soft error occurs in PP and QN, the original stage returns similarly.
In the circuit in FIG. 4, the data PP and NN are the same as the input data D and, as they are retained in the data retaining section composed of a PMOS and in that composed of an NMOS, respectively, a soft error will occur only in one of them, therefore, it is possible for them to return to the original state because they correct each other. On the other hand, the possibility that data HLD in the output data retaining section changes is very low because the outputs of two inverters, the gate inputs of which are the data PP and NN, are connected commonly and if one of the outputs changes temporarily due to a soft error, the other output is maintained correctly.
In the circuits in FIG. 3 and in FIG. 4, when the amount of charge to cause a soft error is small and the reversion of the data due to the soft error is returned to the original state in a brief time by correction, it is possible to maintain a correct state, but if the state of reversion of the data lasts a long time, the reversed data propagates to all over the circuit and the retained data is completely reversed as a result. In this case, the reversed data is retained as is. It is unlikely in actual use that the state of reversion of the data lasts so long that the retained data is completely reversed, and it does not bring any problem from a practical viewpoint. In the future, however, as semiconductor devices become finer, resulting in the reduction in capacitance components and voltages becoming lower, resulting in the reduction in the amount of critical charge, the state of data reversion caused by a soft error becomes longer accordingly and there is a possibility that the occurrence of soft errors cannot be prevented sufficiently even by using the circuits in FIG. 3 and FIG. 4.
In the circuit structures in FIG. 3 and FIG. 4, the node of the NMOS side and that of the PMOS side are connected so as to feed back each other, therefore, a problem occurs that the operation speed is slow. Moreover, another problem occurs that the structure is complicated and the size of the circuit becomes larger because many transistors are used.
The semiconductor device is required to become more dense in circuit integration, speedier, and more economical in power consumption, and the data retaining circuit such as a latch is in the same situation. It is proposed, therefore, that a pulse latch is used as a flip-flop in a structure as shown in FIG. 5. Such a latch, however, retains data dynamically, therefore, it has a characteristic that it is very weak to a soft error. It is, therefore, required that the data retaining circuit as shown in FIG. 5 has an improved resistance to soft errors.
USPTO Backgrounds
USPTO Backgrounds