1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display (LCD) device and a method of fabricating a driving circuit for an LCD device, and more particularly, to a polycrystalline LCD device.
2. Description of the Related Art
In general, a driving circuit device can be an individual type comprising a display unit for displaying images and a driving circuit unit for driving the display unit, wherein the display unit and the driving circuit unit are connected to each other by a tape carrier package (TCP), for example. Alternatively, the driving circuit device can be an integrated type comprising a display unit and a driving circuit unit formed on the same substrate. Accordingly, the integrated type driving circuit device can be more easily fabricated than the individual type driving circuit device. In the integral type driving circuit device, polysilicon is commonly used as a channel layer since polysilicon has better electric mobility an amorphous silicon. Thus, an LCD using the polysilicon integral type driving circuit device can operate at high speeds. For example, electric mobility of an amorphous thin film transistor (TFT) is 0.1˜1 cm2/Vsec, an electric mobility of a polysilicon TFT fabricated using an excimer laser exceeds 100 cm2/Vsec.
FIG. 1 is a schematic plan view of a polysilicon LCD device according to the related art. In FIG. 1, an integral type driving circuit device includes a display unit 101 having unit pixels arranged in a matrix configuration, and a driving circuit unit 102 arranged along an outer periphery of the display unit 101 for driving devices of the display unit. The driving circuit unit 102 is provided with a gate driver 104 and a data driver 103, and the display unit 101 and the driving circuit unit 102 are formed on the same substrate. In the driving circuit unit 102, a complementary metal oxide semiconductor (CMOS) device includes an PMOS TFT and an NMOS TFT that are connected to the unit pixels of the display unit.
FIGS. 2A to 2I are cross sectional views of a fabrication process for a polysilicon LCD device according to the related art. In FIG. 2A, a substrate 201 is prepared, and a buffer layer 202 formed of a silicon oxidation layer (SiO2) is formed on the substrate 201. Then, an amorphous silicon layer 203 is deposited onto the silicon oxidation layer (SiO2) by a plasma enhanced chemical vapor deposition (PECVD) process at a low temperature. Next, a heat treatment is performed at approximately 400° C. during a dehydrogenation process for removing hydrogen included in the amorphous silicon layer. The dehydrogenation is performed in order to prevent hydrogen included in the amorphous silicon layer from corrupting a crystallization process of the amorphous silicon layer and thereby prevent the substrate from being damaged.
In order to crystallize the amorphous silicon layer, glass is used as a substrate and the substrate is heated. However, during fabrication of the LCD device by the heat treatment, the glass used as the substrate may be deformed by the heat. Therefore, during fabrication of a polysilicon TFT on a glass substrate, a laser annealing method is used to convert the amorphous silicon into polycrystalline silicon by an instantaneous heat treatment at a low temperature. For example, an excimer laser beam is irradiated onto the substrate where the amorphous silicon is formed, thereby converting the amorphous silicon layer into a crystalline silicon layer by annealing. Next, the polysilicon is dry-etched to define an active layer.
In FIG. 2B, a TFT active layer 203a is formed within a display unit region, and an N-type TFT active layer 203b and a P-type TFT active layer 203c are formed within a driving circuit unit region.
In FIG. 2C, a gate insulating layer 204 formed of SiO2 or SiNx and the active layers 203a, 203b, and 203c are formed on the entire surface of the substrate 201. The gate insulating layer 204 protects the active layers 203a, 203b, and 203c and insulates a subsequently-formed upper layer. Then, a gate metal layer is formed on the gate insulating layer 204 by a sputtering method. Next, the gate metal layer is patterned by photolithographic processes to form a gate electrode 205. The gate electrode may be composed of a double layer of Al and Mo in order to provide excellent conductivity and excellent ohmic contact characteristics with an indium tin oxide (ITO) material used as a pixel electrode. Alternatively, the gate electrode may be composed of a single layer of only Mo.
Since the N-type TFT makes use of electrons as carriers, it may generate a leakage current due to the electrons. Accordingly, the N-type TFT is fabricated as a lightly doped drain (LDD) type that effectively prevents the leakage current. Thus, the LDD-type TFT is formed by injecting impurity ions into a polysilicon source/drain region, wherein the impurity ions may include an element, such as Phosphorus or Arsenic, corresponding to the fifth group of the periodic table.
In FIG. 2D, a photo resist pattern 206 is formed to shield the P-type TFT region by a photomasking process that includes exposing and developing processes. Then, N-type ions of a low concentration are injected into the active region of the N-type TFT pixel unit and circuit unit regions. During the phosphorus ion injection, the gate electrode 205 is positioned to function as a blocking mask so that the N-type ions are injected into the source/drain regions. After injecting the N-type ions, the photoresist pattern 206 is removed.
In FIG. 2E, a photoresist pattern 207 is formed to shield the gate electrode 205 and portions of the source/drain region of the N-type TFT pixel unit and circuit unit regions, and the entire P-type TFT circuit unit region. By applying the photoresist 207 as a blocking mask of the injected ions, N-type impurity ions of a high concentration are injected into the source/drain regions of the N-type TFT pixel unit and circuit unit regions, thereby forming LDD-type TFTs. For example, the LDD-type TFTs both include LDD regions 208 having a low impurity concentration and source and drain regions 209 having a high impurity concentration.
In FIG. 2F, a photoresist 210 is formed to cover the completed N-type TFT pixel unit and circuit unit regions. Then, P-type impurity ions are injected into the portions 211 of the active layer of the P-type TFT circuit unit region. Since holes are used as charge carriers, leakage current due to hot carriers is not easily generated in the P-type TFT. Accordingly, the P-type TFT may not include LDD regions. Then, the photoresist 210 is removed.
In FIG. 2G, an insulating layer 214 comprising SiO2 or SiNx is formed on the gate electrode 205, and a contact hole 220 is formed in the insulating layer 214 corresponding to the source/drain regions in the N-type and P-type TFTs.
In FIG. 2H, a conductive layer for a source/drain electrode is formed in the contact hole 220 and patterned, thereby forming source/drain electrodes 215 and 216.
In FIG. 2I, a passivation layer 217 of an organic layer or an inorganic layer is formed on the source/drain electrodes 215 and 216. Then, the passivation layer 217 on the drain electrode of the TFT is removed to form a contact hole 219. Next, a pixel electrode 218 is formed on the passivation layer 217 and connected to the drain electrode 216 through the contact hole 219, thereby completing the LCD device.
Formation of the polysilicon TFTs is a very complicated process although the polysilicon TFTS have excellent operation characteristics. In addition, a plurality of masks are required to fabricate the polysilicon TFT LCD device. For example, since each mask process accompanies a photolithography process, the fabrication process is delayed and results in possible environmental contamination.
USPTO Backgrounds
USPTO Backgrounds