A device such as Motorola's planar NPN power transistors, identified as PLE 36 are theoretically capable of operating at a bulk breakdown voltage in excess of 1000 volts. However, in actual practice using existing processing and assembly techniques the devices are surface limited to a 500 to 600 volt maximum operating capacity.
Although not completely understood, it is theorized that a limiting factor occurs in connection with the surface inversion of the device, or the creation of charged particles in the SiO.sub.2 passivation layer. For an NPN device the SiO.sub.2 layer will become positively charged at high voltage operation and similarly a negative layer is created at the interface of the base junction and extending outwardly therefrom. The intensities and depths of these charged layers apparently depend upon the voltage level at which the device is being operated. It is felt that these high intensity or excess charges cause current crowding and create parasitic resistors deleteriously affecting expected high voltage operation.
Another purpose of the encapsulating layers is to prevent ambient contamination and "operational" contaminants caused by high voltage operation. Known prior art techniques employ encapsulants or die coatings comprising polymers having suitable polar characteristics combined with silicon oxide material. This approach, however, is not effective over a wide range of conditions. More specifically, this combination of materials becomes thermally unstable at higher temperatures and as a result its beneficial properties as an encapsulant are diminished.
USPTO Backgrounds
USPTO Backgrounds