The invention relates in general to electronic circuit testing and more particularly to an apparatus and a method utilizing enhanced test data compression techniques.
Electronic circuits have become more and more complex and appropriate circuit testers need more and more functionality in order to be able to perform a sufficient test.
As the electronic circuits to be tested comprise more and more electrical connections, such as pins, the equipment needed for the functional test of an electronic circuit increases significantly. Furthermore, there is a need to modify the test data or test-data-sequences to be applied to the electrical connections of an electronic circuit under test or a board with several integrated circuits to be tested. Such modification parameters of the signals to be applied to or received from a device under test (DUT) are voltage, frequency, duty cycle etc.
An electronic circuit or board tester should be easily adaptable to the test of various electronic circuits or boards having different numbers of electrical connections and functionality. Test parameters should be easily programmable. Each DUT comprises several input and output electrical connections, such as pins. An electronic circuit or board tester applies digital signal patterns to the electrical connections of the DUT being created by the chip designer of the DUT, for example by CAE tools, taking the specifications of the respective DUT into account. Digital output signals or digital patterns generated by the DUT are compared with a signal pattern of the same DUT having full functionality.
As an electronic circuit or board tester comprises a large quantity of electronic memories, such as expensive RAMs, there is a need to reduce the amount of memories and/or memory capacity needed for carrying Gut a functionality test on various electronic circuits or boards, such as those comprising integrated circuits (ICs).
From U.S. Pat. No. 4,652,814 of the applicant, it is known to analyze a test matrix with regard to redundancy. The test matrix describes the test-data-sequences or test data being received from or supplied to each electrical connection of a DUT at each clock cycle. Each column of the test matrix describes the test signal being applied to one electrical connection of the DUT at different clock cycles. Each row of the test matrix describes the test signal at all electrical connections or pins of the DUT during one clock cycle. A row of the test matrix is called a test vector and an element of the test matrix is called a segment of a test vector.
U.S. Pat. No. 4,652,814 proposes to check the test matrix with regard to identical test vectors. In case two or more identical test vectors exist, such a test vector is stored only once in the memory of the circuit tester. All other test vectors being non-identical with other test vectors are also stored in the memory of the circuit tester, such as in one or more RAMs. Sequencing of this data is controlled by a single sequencer which provides to these RAMs the address of the data vector to be utilized at any given time.
From U.S. Pat. No. 5,402,427 of the applicant, it is known to use a set of vector storage units each storing a segment of a test vector. In case that one test vector comprises two or more identical segments, this segment is stored only once. If for example the test data (segment) at pin 1 and pin 2 are the same at the same clock cycle, this segment is stored only once. Furthermore, U.S. Pat. No. 5,402,427 proposes to use several sequencers. It will be understood that a combination of a vector storage unit and an associated sequencer, each combination working independently except with regard to the same clock signal, cannot be used. Otherwise identical segments would have to be stored in more than one vector storage unit each being associated with a different electrical connection or pin of the DUT.
When using a modular circuit or board tester with a vector storage unit and an associated sequencer per electrical connection or pin of a DUT, there is a need for an electronic circuit or board tester having another concept. Further there is a need for a different method of testing an electronic device (DUT).
USPTO Backgrounds
USPTO Backgrounds