1. Field of the Invention
The present invention relates to an image exposure apparatus and an image forming apparatus, particularly to an image exposure apparatus using an LED array and an image forming apparatus provided with the image exposure apparatus.
2. Related Background Art
A conventional self-scanning light emitting diode array (hereinafter referred to simply as SLED) is disclosed in Japanese Patent Application Laid-open Nos. 1-238962, 2-208067, 2-212170, 3-20457, 3-194978, 4-5872, 4-23367, 4-296579, and 5-84971, Japan Hard Copy '91 (A-17) Proposal of Light Emitting Element Array for Optical Printer with integrated Drive Circuit, the Society of Electronic Information Communication ('90. 3. 5) Proposal of Self-scanning Light Emitting Element (SLED) using PNPN Thyristor Structure, and the like, and has been noted as a recording light emitting element.
Here, the conventional SLED will be described with reference to FIG. 3. FIG. 3 is a partial circuit diagram of the conventional SLED, and an operation will be described.
In FIG. 3, character VGA denotes a power source voltage of SLED, and connected, as shown in FIG. 3, to diodes cascade-connected to φS via a resistance R of FIG. 3.
As shown in FIG. 3, SLED comprises transmitting thyristors ST1 to ST5 arranged in an array and light emitting thyristors SL1 to SL5 arranged in an array, gate signals of the respective thyristors are connected, and a first thyristor is connected to a signal input portion of φS. Additionally, the number of thyristors is not limited to five as shown in FIG. 3, and any other arbitrary number of thyristors may be disposed.
In a constitution, a second thyristor gate is connected to a diode cathode connected to a terminal of φS, and a third thyristor gate is connected to the next diode cathode.
(Operation of SLED)
An operation of SLED shown in FIG. 3 will next be described with reference to FIGS. 3 and 4. FIG. 4 is a timing chart of a signal for controlling SLED shown in FIG. 3, and FIG. 4 shows an example in which all elements (SL1 to SL5) are lit.
Transmitting and light emitting will be described with reference to the timing chart of FIG. 4. The transmitting starts by changing φS to 5 V from 0 V.
When φS turns to 5 V, in FIG. 3, Va=5 V, Vb=3.7 V (a diode forward direction voltage fall is set to 1.3 V), Vc=2.4 V, Vd=1.1 V, 0 V on and after Ve, and gate signals of the transmitting thyristors ST1 and ST2 change to 5 V, 3.7 V, respectively, from 0 V.
When φ1 is changed to 0 V from 5 V in this state, respective potentials of the transmitting thyristor ST1 are obtained as anode: 5 V, cathode: 0 V, gate: 3.7 V, thyristor ON conditions are obtained, and the transmitting thyristor ST1 turns on.
Even when φS is changed to 0 V in this state, the transmitting thyristor ST1 is still on and Va≅5 V is nearly obtained (when the thyristor turns on, the potential between the anode and the gate substantially becomes equal).
Therefore, even when φS is set to 0 V, the ON conditions of the first thyristor are held and a first shift operation is completed.
When φI signal of the light emitting thyristor to be inputted to an input terminal of image data φD in FIG. 3 is changed to 0 V from 5 V, the same conditions as conditions on which the transmitting thyristor turns on are obtained, the light emitting thyristor SL1 therefore turns on, and a first LED is lit.
For the first LED by resetting φI to 5 V, a potential difference between the anode and the cathode of the light emitting thyristor is eliminated, a thyristor minimum held current cannot be passed, and the LED therefore turns off by turning off the light emitting thyristor SL.
The transmitting of the thyristor ON conditions to ST2 from ST1 will next be described. Even when the light emitting thyristor SL1 turns off, φ1 stays at 0 V, the transmitting thyristor ST1 is therefore on, a gate voltage of the transmitting thyristor ST1 is nearly Va≅5 V, and Vb=3.7 V.
When φ2 is changed to 0 V from 5 V in this state, the potentials of the transmitting thyristor ST2 are obtained as anode: 5 V, cathode: 0 V, gate: 3.7 V, and the transmitting thyristor ST2 turns on.
After the transmitting thyristor ST2 turns on, by changing φ1 to 5 V from 0 V, the transmitting thyristor ST1 turns off in a similar manner as when the light emitting thyristor SL1 turns off.
The transmitting thyristor to turn on shifts to ST2 from ST1 in this manner. Subsequently, by changing φI to 0 V from 5 V, the light emitting thyristor SL2 turns on to emit light.
Additionally, a reason why only the light emitting thyristor whose transmitting thyristor turns on can emit light lies in that when the transmitting thyristor is not on, the gate voltage of the thyristor other than the thyristor adjacent to the thyristor having turned on is 0 V, and the thyristor ON conditions are not obtained.
Also for the adjacent thyristor, when the light emitting thyristor turns on, the potential of φI turns to 3.4 V (light emitting thyristor forward direction voltage fall amount), and the adjacent thyristor cannot turn on because there is no potential difference between the gate and the cathode.
Additionally, it has been described above that by setting φI to 0 V, the light emitting thyristor turns on to emit light, but in an actual print operation, it is naturally necessary to control whether or not to actually emit light at the timing in accordance with the image data φD.
The image data φD shown in FIGS. 3 and 4 is a signal indicating the aforementioned condition, and for φI terminal of SLED, a logical sum of φI and image signal is taken in the outside. Only when the image data is 0 V, the SLED φI terminal actually turns to 0 V to emit light. When the image data is 5 V, the SLED φI terminal stays at 5 V and no light is emitted.
(SLED Mounting State)
A case in which the conventional SLED described with reference to FIGS. 3 and 4 is mounted on an image forming apparatus will next be described with reference to FIG. 5.
FIG. 5 is a structure diagram of the image forming apparatus of an electrophotographic recording system, on which the SLED shown in FIG. 3 is mounted.
In FIG. 5, numeral 701 denotes an exposing portion with an SLED semiconductor chip mounted thereon, 702 denotes a photosensitive drum as a light receiving portion, 703 denotes a drum charging device, 704 denotes a developing device for attaching a toner, 705 denotes a transferring device for transferring the toner on the drum to a sheet 708 on a transferring belt 707, and 706 denotes a cleaner for removing the toner remaining on the photosensitive drum 702 after transferring.
For the exposing portion 701, an internal structure will next be described. Numeral 710 denotes an SLED array semiconductor chip, 711 denotes a ceramic base as a reference for laying a chip array, and 712 denotes an aluminum frame serving as an optical system reference.
Moreover, numeral 713 denotes Selfoc Lens Array (trade name, hereinafter referred to simply as SLA) having a focus on a light emitting spot array of the SLED array semiconductor chip 710 and on the photosensitive drum 702, 714 denotes an electrode for generating an electric field to prevent the toner from flying (details will be described later), 715 denotes a mold member for covering and supporting the aluminum frame 712 on the opposite side of the exposing portion 701, 716 denotes a power source for applying a direct-current voltage to the electrode 714, and 717 denotes a switch.
(Image Forming Process)
A flow of image formation onto the sheet 708 will next be described. First, the drum charging device 703 uniformly applies a negative charge onto the photosensitive drum 702.
Subsequently, the surface of the photosensitive drum 702 is exposed to light in accordance with an image pattern by the exposing portion 701, and an electrostatic latent image is formed. Next the developing device 704 applies a negatively charged toner to the electrostatic latent image, attaches the toner to a portion exposed to light by the exposing portion 701, and forms a toner image on the photosensitive drum 702.
Subsequently, the transferring device 705 transfers the toner image onto the sheet 708, and forms the toner image on the sheet 708.
After transferring, the cleaner 706 wipes off the remaining toner from the photosensitive drum 702, and the flow returns to a charging process.
(Flying and Preventing)
The toner flying will next be described. When the remaining toner is insufficiently collected by the cleaner 706 in the electrophotographic process, the toner as charged particles remains on the photosensitive drum 702, and the flow shifts to the next process as it is.
Here by an electrostatic field distribution formed on the photosensitive drum 702 passed under the drum charging device 703 and exposed to light by the exposing portion 701, the remaining toner whose potential is unstable on the photosensitive drum 702 leaves the photosensitive drum 702 and flies, and adheres to the surface of SLA 713. It is seen that the toner deteriorates the subsequent exposing state and causes image defects.
The exposing portion 701 shown in FIG. 5 will next be described in more detail with reference to FIG. 6. FIG. 6 is an enlarged view of the exposing portion in FIG. 5, and shows means for preventing exposure defect by toner flying.
In FIG. 6, numeral 802 denotes a photosensitive drum, 810 denotes an SLED array semiconductor chip, 811 denotes a ceramic base as a reference for laying a chip array, 812 denotes an aluminum frame as an optical system reference, 813 denotes SLA, and 815 denotes a mold member for covering and supporting the exposing portion.
Moreover, numeral 816 denotes a power source for a flying preventing electrode 814, and 817 denotes a switch. Furthermore, by disposing the electrode 814 for preventing the residual toner from flying, and generating a negative electric field, the scattered residual toner is prevented from flying to the SLA 813.
Numeral 818 denotes scattered charged particles (toner). FIG. 6 schematically shows that the charged particles 818 change tracks by the electric field of the flying preventing electrode 814 and fail to adhere to the SLA 813.
(SLED Destruction by Mold and Electrostatic Discharge)
On the other hand, in the conventional art shown in FIG. 6, there is a problem that electrostatic destruction of the SLED array semiconductor chip 810 with a low electrostatic pressure resistance easily occurs in the flying preventing electrode 814.
Specifically, when the switch 817 turns off, and static electricity discharge occurs in the flying preventing electrode 814 from the outside, current flows via the surface of the mold member 815 and the destruction of the SLED array semiconductor chip 810 sometimes occurs (hereinafter, the static electricity discharge occurs when the switch 817 is off and no voltage is applied to the flying preventing electrode 814).
Specifically, the static electricity discharge is caused, for example, by human body contact with the electrode 814 or the like. The static electricity discharge may also occur in the aluminum frame 812, but the aluminum frame 812 is subjected to sufficient grounding, and therefore the destruction of the SLED array semiconductor chip 810 by the static electricity discharge does not result.
(Countermeasure against Static Electricity Discharge Accident of Conventional System)
The following means has been heretofore used to solve the problem. One means comprises replacing the mold member 815 with a member which is more difficult to energize, and preventing electricity from being discharged to the chip.
Another means comprises replacing the mold member 815 with a metal or another member which can easily be energized, sufficiently grounding the member similarly as the aluminum frame 812, and partially placing individual insulators between the member and the electrode 814.
This means will be described with reference to FIG. 7. FIG. 7 is a schematic view showing the conventional SLED countermeasure against the static electricity discharge.
In FIG. 7, since members denoted by numerals 910 to 914, 816, 817 are similar to the corresponding members shown in FIG. 6, the description thereof is omitted.
Moreover, 916 denotes a metal cover fixed to an aluminum frame 912, and 915 denotes an insulation member for insulation between the metal cover 916 and electrode 914.
According to the constitution shown in FIG. 7, in the conventional apparatus, the SLED array semiconductor chip can be protected from the static electricity discharge.
However, for the means using the member difficult to energize in the conventional art, there is a problem that the material and surface processing become expensive as compared with the mold member.
Moreover, for the means in which the easily energized member is used and grounded, two members, that is, the insulation member and metal member are used, an assembly process is added, and there is also a problem that the metal member is more expensive than the mold member.
Furthermore, since the electrode is disposed in the vicinity of the photosensitive drum, during application of a bias voltage to the electrode by the power source, spark discharge supposedly occurs between the electrode and the photosensitive drum.
USPTO Backgrounds
USPTO Backgrounds