The present invention is generally related to the fields of computers and digital analysis and, more particularly, is related to a system and method for comparing values from a target system during logic analysis.
Current manufacturers of high-speed computer equipment often need to access data information that is communicated on a data bus or other conductors within the equipment for testing or other reasons. Conventional approaches to accessing data on a bus include the use of logic analyzers that provide probes that are placed in electrical contact with the particular conductors in question.
In a typical arrangement, the probes are positioned to obtain the data signals from the target system and the target system is operated to produce the desired data values that are captured by the probes. These data values are acquired and stored in a memory in the logic analyzer. However, many of the target systems that are analyzed using logic analyzers operate at speeds measured in hundreds of megahertz. Consequently, the data values obtained from such a target system will quickly fill up the memory of the logic analyzer. In many cases, this occurs within a few milliseconds.
As a result, logic analyzers have employed circuitry to perform a quick comparison between the values obtained from the target system and desired values specified by the user to detect specific data values from the target system. Generally, only those data values from the target system are stored in the memory of the logic analyzer. In this manner, a reduced number of data values are then stored in the memory of the logic analyzer, thus preventing the memory from becoming full prematurely.
The approaches employed to perform this comparison typically employ logic circuits and other devices of significant size and complexity. Accordingly, such circuits are costly and the number of desired values that may be employed by a single logic analyzer are limited.
In light of the foregoing, the present invention provides for a system and method to compare logical values from target systems. According to one embodiment, the system includes a configuration in a field programmable gate array for comparing logical values. The configuration advantageously facilitates determining when values are greater than or less than a predefined value while employing a reduced number of lookup tables in the field programmable gate array. The configuration includes an input interface to receive a parallel logical value. The system also includes a number of equality lookup tables configured to detect an equality between a portion of the logical value and a portion of a predefined value. The system also includes a number of inequality lookup tables configured to determine a type of an inequality between the portion of the logical value and the portion of the predefined value. The predefined value is preprogrammed and downloaded to the equality lookup tables at startup. The inequality lookup tables each include an output that is applied to an OR function, thereby producing an output.
Another embodiment of the present invention includes a method in a field programmable gate array for comparing logical values. Broadly stated, the method includes the steps of receiving a logical value, detecting an equality between a portion of the logical value and a portion of a predefined value, and determining a type of an inequality between the portion of the logical value and the portion of the predefined value.
The various embodiments of the present invention provide a significant advantage in that a single FPGA may be employed to perform a greater number of comparisons than prior art configurations. Thus, a logic analyzer that employs the present invention has much greater capacity to evaluate specific logical values based on predetermined criterion at lower cost.
USPTO Backgrounds
USPTO Backgrounds