The present invention relates to a process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information.
To increase the security of the stored information, it is known to protect at least some of the data stored within cells of a semiconductor memory from easy outside accessibility. This is, for example, the case of memories embedded in Smart Cards or other memory devices containing data for limited access. Therefore, it is necessary to provide suitable shielding layers to protect the data from being read, modified, or erased.
In particular, as far as electrically programmable non-volatile semiconductor memory devices such as EPROM, Flash EEPROM or EEPROM devices, shielding of the memory matrix, or of a portion thereof wherein reserved information is to be stored is conventionally generally obtained by forming a metal layer over the surface to be shielded, to prevent intrusion from the outside. Such metal layer is an additional metal layer other than those necessary to form interconnections, and significantly increases the cost and the manufacturing time of memory devices.
It is also known that electrically programmable non-volatile semiconductor memory cells such as EPROM, Flash EEPROM and EEPROM cells can be formed with a single level of polysilicon (SP) or with a double level of polysilicon (DP).
An example of single-polysilicon level electrically programmable non-volatile memory cells are single-polysilicon level FLOTOX EEPROM memory cells comprising a sensing transistor with a floating gate and a selection transistor for selecting the cell to be programmed in a group of cells of a matrix. The floating gate is capacitively coupled to an N+ diffusion forming the control gate of the sensing transistor. The floating gate of the sensing transistor and the gate of the selection transistor are formed in a same, unique layer of polysilicon. The cell also comprises, in a portion of its area, a tunnel oxide between the floating gate and the drain of the sensing transistor, wherein the passage of electrons during write and erase operations of the cell.
An example of single-polysilicon level EEPROM cell is provided in the U.S. Pat. No. 5,307,312 assigned to SGS-Thomson Microelectronics S.r.l., whose content is incorporated herein by reference.
An example of double-polysilicon level electrically programmable non-volatile memory cells are double-polysilicon level FLOTOX EEPROM memory cells, well known to the skilled person, comprising a floating gate transistor and a selection transistor for selecting the cell to be programmed inside a group of cells of a matrix. The gate of the transistor comprises a floating gate over which a control gate is insulatively disposed, with the interposition of a layer of oxide. The two gates are respectively formed in two different layers of polysilicon.
Single-polysilicon level cells have the advantage that they can be fabricated by means of simpler process steps with respect to double-polysilicon level ones, but for a same technological resolution they occupy an area at least twice that of the double-polysilicon level cells. They require more area because the single-polysilicon level cells are to be formed with the control gate and the floating gate one beside the other, instead of superimposed. It is apparent that double-polysilicon level cells are more suitable for applications where high integration degrees are desirable.
An object of the present invention is to provide a process for producing a semiconductor memory device comprising storage memory cells and shielded memory cells for preventing reading from the outside of information contained therein, said process not affected by the drawbacks of the known processes.
According to an embodiment of the present invention, such object is achieved by means of a process for manufacturing a semiconductor memory device comprising the formation, in a same semiconductor material chip, of at least a first memory cell comprising a MOS transistor with a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material, and of at least a second memory cell shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell comprises a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of said first layer of conductive material, and the layer of shielding material is formed by definition of said second layer of conductive material.
Thanks to the present invention, it is possible to obtain a semiconductor memory device comprising both storage memory cells and shielded memory cells, without additional process steps for forming the shielding layer. In fact, the shield is advantageously obtained using the second level of conductive material by means of which the control gate of the storage memory cell is formed.
The features of the present invention will be made apparent by the following detailed description of one embodiment thereof, described as a non-limiting example in the annexed drawings.
USPTO Backgrounds
USPTO Backgrounds