Dynamic Random Access Memory (DRAM) cells are well known. A DRAM cell is essentially a capacitor for storing charge and a pass transistor (also called a pass gate or access transistor) for transferring charge to and from the capacitor. Data stored in the cell is determined by the absence or presence of charge on the storage capacitor. Because cell size affects chip density and cost, reducing cell area is one of the DRAM designer's primary goals.
One way to accomplish this density goal without sacrificing storage capacitance is to use trench capacitors in the cells. Trench capacitors can be formed by etching deep trenches in a semiconductor wafer and forming vertically orientated capacitors within each deep trench. Thus, the surface area required for the storage capacitor is dramatically reduced without sacrificing capacitance, and correspondingly, storable charge. In order to further decrease the density of the device, the access transistor can also be positioned in a vertical orientation, as opposed to a planar orientation.
Trench type memory cells have a connection between the trench filled polysilicon electrode and the source/drain (S/D) of an access transistor, commonly known as a strap. The strap resistance is determined by process control rather than design. One key process step occurs during dry etching of trenched polysilicon. Because it is difficult to control the end point mechanism of the process, a problem exists with the polysilicon etch rate variation between wafers, lots and tools. This causes varying strap resistance levels, which is a key problem for trench type memory fabrication.
Therefore, what is needed in the art is a structure and method which provides a more uniform etch profile to regulate strap resistance.
USPTO Backgrounds
USPTO Backgrounds