As metal-oxide-semiconductor field-effect transistors (“MOSFETs”) in integrated circuits have become nanosized, i.e., having device dimensions of less than a 100 nm, silicon-on-insulator (“SOI”) MOSFETs have been found to have improved functionality relative to Bulk MOSFETs. In particular, the improved transistor electrostatics of SOI MOSFETs result in comparatively low inter-device noise coupling and comparatively low substrate interference in radio frequency and mixed voltage circuits. As such, SOI MOSFETs have been adopted for system-on-chip (“SoC”) applications that can require the integration of analog, digital, mixed-signal, and/or radio frequency circuits on a single chip.
Referring to FIG. 1, a three-dimensional view of an H-gate body-contacted partially-depleted SOI MOSFET is illustrated. The SOI MOSFET 100 can be nanosized and includes a substrate 102, a buried oxide layer 104 over the substrate 102, a source 106 and a drain 108 opposing one another, and a polysilicon gate 110 having gate spacers 112 and 114 between the source 106 and drain 108. Two oxide extensions 116 and 118 are located at opposite ends of the polysilicon gate 110 and two p+ doped body contacts 120 and 122 are located at opposite ends of the SOI MOSFET 100.
Because of the buried oxide layer 104 located beneath the silicon device layer including the source 106, drain 108, polysilicon gate 110, oxide extensions 116 and 118, and p+ doped body contacts 120 and 122, the performance characteristics of SOI MOSFETs are considerably different from Bulk MOSFETs. In particular, the movement of generated holes in the impact-ionization process under the polysilicon gate 110 towards the body contacts 120 and 122 creates a potential buildup in the body of SOI MOSFETs, leading to elevated body voltage. As such, SOI MOSFETs experience floating body effects and self-heating effects. To eliminate the floating body effects and the resulting variations in body potential, the bodies of SOI MOSFETs are typically connected to either the source in a body-tied-source structure or an independent body voltage through an external contact in a T-gate or H-gate configuration.
Referring to FIG. 2, a cross-section of an example H-gate body-contacted partially-depleted SOI MOSFET showing its body contacts is illustrated. In an H-gate body-contacted configuration, the p+ doped body contacts 120 and 122 are connected to the body of the SOI MOSFET 100 under the polysilicon gate 110, as illustrated in FIG. 2, creating a path for generated holes to escape. For example, in the partially-depleted SOI MOSFET 200 of FIG. 2, the regions of the p+ doped body contacts 120 and 122 each include two contacts 202.
The key MOSFET device characteristics for the design of mixed-signal, analog integrated circuits are the drain-source current, the gate transconductance, and the output conductance. Variations in the output conductance directly affect the intrinsic gain and degrade the transistor linearity of a device. The transition due to the finite body resistance occurs in the radio frequency range and affects the linear behavior of a device by, for example, increasing the total harmonic distortion and lowering the third-order intercept point of the device.
There is typically a transition in the output conductance of SOI MOSFETs due to their non-zero body resistance. Therefore, to improve the linearity of SOI MOSFET circuits, the transition due to finite body resistance should be eliminated. As such, a new method for designing SOI MOSFET circuits with improved linear characteristics is needed.
USPTO Backgrounds
USPTO Backgrounds