1. Field of the Invention
The present invention generally relates to a method and apparatus for controlling a period of a second clock signal generated by counting the number of periods of a first clock signal.
2. Description of the Related Art
An IC card equipped with external terminals is called "a card". The IC card has substantially the same size as a credit card or the like, and internally contains an integrated circuit (IC), and also can transfer data via the external terminals formed on a card surface from or to an external device. In general, this IC card equipped with the external terminals is called a smart card. A memory, a microcomputer, and other various control circuits are built in this IC card. This type of IC card is widely utilized. For instance, an IC card equipped with external terminals and containing only a memory is used as an auxiliary and easily detachable storage apparatus for another apparatus. Another type of IC card equipped with external terminals and containing a microcomputer is used as a master of an external apparatus, or as an apparatus which operates independent from an external apparatus, and can transfer data from or to the external apparatus, if required.
The interfaces for a type of IC card equipped with external terminals and another type of IC card equipped functioning as an external apparatus, and the transfer protocol for them and a read/write interface apparatus are defined by ISO/IEC 7816-3 (and also JIS X 6304). The data transfer is performed in accordance with the transfer protocol using serial data transfer.
Now, this definition on "IC card equipped with external terminals: Electric signals and Transfer protocol" will be described.
As an IC card equipped with external terminals, there are two types of IC cards. Namely, there are an external clock signal IC card to which a clock signal is externally supplied, and an internal clock signal IC card containing a clock signal generator therein and not necessitating that any clock signal is supplied from an external device. When a unit time required to transfer 1-bit data is represented by an element time unit (etu), the data transfer rate between an IC card equipped with external terminals and an interface apparatus is defined as follows. That is, a reciprocal of the transfer rate, namely, one (etu) in an initial response of the internal clock signal IC card is defined as 1/9600 seconds. 1 (etu) in an initial response of an external clock signal IC card is equal to 372 times longer than a time period of a clock signal externally supplied to the IC card. Also, in an initial response, 1 character must be composed of a start bit of 1 bit, data bits of 8 bits subsequent to this start bit, a parity bit of 1 bit, and further a protection period of 2 bits at its minimum.
Also, the interface apparatus executes a parity check within this protection period. Then, the interface apparatus must output this parity check result to the IC card equipped with the external terminals within a time period of 1 (etu) at a minimum to 2 (etu) at a maximum after 0.5 (etu) has passed from start of the protection period. The length of 1 character is equal to 12 (etu) at a minimum. In order to correctly transmit/receive data, the interface apparatus must execute the sampling operations as follows. The first bit of the data must be sampled within a range of (1.5.+-.0.2) etu from start of a start bit. The second bit of the data must be sampled within a range of (2.5.+-.0.2) etu from the start of the start bit. In this manner, the range within each of the subsequent bits must be sampled is successively increased by 1 etu. The eighth bit of the data must be sampled within a range of (8.5.+-.0.2) etu from the start of the start bit. The parity bit must be sampled within a range of (9.5.+-.0.2) etu from the start of the start bit. On the other hand, in such a case that the parity check result informed from the interface apparatus indicates an error, the IC card equipped with the external terminals must immediately send the character again.
In the initial response, the characters selected from among 7 characters at a minimum to 33 characters at a maximum are transmitted/received. The IC card equipped with the external terminals may designate various parameters subsequent to the initial response such as a data transfer mode, a transfer rate, a ratio of data transfer clock signal period to card operation clock signal period when the IC card is an external clock signal IC card and the like to the interface apparatus based on these transmitted/received data.
For the data transmission/reception subsequent to the initial response, 83 different kinds of ratios of data transfer clock signal period to card operation clock signal period are allowed, specifically, in case of the external clock signal IC card. Therefore, in order that the interface apparatus transmits/receives data to/from all types of the IC cards equipped with external terminals generated based on the above standard ISO/IEC 7816-3, the interface apparatus must generate clock signals for 83 different kinds of
TABLE 1 ______________________________________ UNIQUE PERIOD FACTOR- SERIAL RATIO IZATION OF NO. RAT! PERIOD RATIO ______________________________________ 1 11.62500 3 .times. 31 .div. 2.sup.3 2 16.00000 2.sup.4 3 17.43750 3.sup.2 .times. 31 .div. 2.sup.4 4 18.60000 3 .times. 31 .div. 5 5 23.25000 3 .times. 31 .div. 2.sup.2 6 24.00000 23 .times. 3 7 25.60000 2.sup.7 .div. 5 8 27.90000 3.sup.2 .times. 31 .div. 2 .div. 5 9 31.00000 31 10 32.00000 2.sup.5 11 34.87500 3.sup.2 .times. 31 .div. 2.sup.3 12 37.20000 2 .times. 3 .times. 31 .div. 5 13 38.40000 2.sup.5 .times. 3 .div. 5 14 42.66667 2.sup.7 .div. 3 15 46.50000 3 .times. 31 .div. 2 16 48.00000 2.sup.4 .times. 3 17 51.20000 2.sup.8 .div. 5 18 55.80000 3.sup.2 .times. 31 .div. 5 19 58.12500 3 .times. 5 .times. 31 .div. 2.sup.3 20 62.00000 2 .times. 31 21 64.00000 2.sup.6 22 69.75000 3.sup.2 .times. 31 .div. 2.sup.2 23 74.40000 2.sup.2 .times. 3 .times. 31 .div. 5 24 76.80000 2.sup.7 .times. 3 .div. 5 25 85.33333 2.sup.8 .div. 3 26 93.00000 3 .times. 31 27 96.00000 2.sup.5 .times. 3 28 102.40000 2.sup.9 .div. 5 29 116.25000 3 .times. 5 .times. 31 .div. 2.sup.2 30 124.00000 2.sup.2 .times. 31 31 128.00000 2.sup.7 32 139.50000 3.sup.2 .times. 31 .div. 2 33 155.00000 5 .times. 31 34 170.66667 2.sup.9 .div. 3 35 186.00000 2 .times. 3 .times. 31 36 192.00000 2.sup.6 .times. 3 37 232.50000 3 .times. 5 .times. 31 .div. 2 38 256.00000 2.sup.8 39 279.00000 3.sup.2 .times. 31 40 372.00000 2.sup.2 .times. 3 .times. 31 41 384.00000 2.sup.7 .times. 3 42 465.00000 3 .times. 5 .times. 31 43 512.00000 2.sup.9 44 558.00000 2 .times. 3.sup.2 .times. 31 45 744.00000 2.sup.3 .times. 3 .times. 31 46 768.00000 2.sup.8 .times. 3 47 930.00000 2 .times. 3 .times. 5 .times. 31 48 1024.00000 1.sup.10 49 1116.00000 2.sup.2 .times. 3.sup.2 .times. 31 50 1488.00000 2.sup.4 .times. 3 .times. 31 51 1536.00000 2.sup.9 .times. 3 52 1860.000000 2.sup.2 .times. 3 .times. 5 .times. 31 53 2048.00000 2.sup.11 54 2232.00000 2.sup.3 .times. 3.sup.2 .times. 31 55 2976.00000 2.sup.5 .times. 3 .times. 31 56 3072.00000 2.sup.10 .times. 3 57 3720.00000 2.sup.3 .times. 3 .times. 5 .times. 31 58 4096.00000 2.sup.12 59 4464.00000 2.sup.4 60 5952.00000 2.sup.5 .times. 3 .times. 31 61 6144.00000 2.sup.11 .times. 3 62 7440.00000 2.sup.4 .times. 3 .times. 5 .times. 31 63 8192.00000 2.sup.13 64 8928.00000 2.sup.5 .times. 3.sup.2 .times. 31 65 11904.00000 2.sup.7 .times. 3 .times. 31 66 12288.00000 2.sup.12 .times. 3 67 14880.00000 2.sup.5 .times. 3 .times. 5 .times. 31 68 16384.00000 2.sup.14 69 17856.00000 2.sup.8 .times. 3.sup.2 .times. 31 70 23808.00000 2.sup.8 .times. 3 .times. 31 71 24576.00000 2.sup.13 .times. 31 72 29760.00000 2.sup.5 .times. 3 .times. 5 .times. 31 73 32768.00000 2.sup.15 74 35712.00000 2.sup.7 .times. 3.sup.2 .times. 31 75 47616.00000 2.sup.9 .times. 3 .times. 31 76 49152.00000 2.sup.14 .times. 3 77 59520.00000 2.sup.7 .times. 3 .times. 5 .times. 31 78 65536.00000 2.sup.16 79 71424.00000 2.sup.8 .times. 3.sup.2 .times. 31 80 95232.00000 2.sup.10 .times. 3 .times. 31 81 98304.00000 2.sup.15 .times. 3 82 119040.00000 2.sup.8 .times. 3 .times. 5 .times. 31 83 131072.00000 2.sup.17 ______________________________________
transfer rates as the card operation clock signal.
The 83 different kinds of ratios of data transfer clock signal period to card operation clock signal period are represented in the above Table 1. It should be noted that the ratio of data transfer clock signal period to the card operation clock signal period is equal to a value of (1 etu)/(1 card operation clock signal period).
In general, conventionally, interface apparatuses are provided which are exclusively used for IC cards equipped with external terminals for specific purposes. For example, there is a combination of an interface apparatus and an IC card equipped with external terminals for an automatic cash dispenser of a financial institution. Also, there is another combination of a mobile telephone functioning as an interface apparatus and an IC card equipped with external terminals functioning as an ID (identification) card. In these combination cases, the IC card equipped with external terminals is normally provided to be fitted with a function of an interface apparatus. Accordingly, this interface apparatus need not be designed to accept all of the above-described 83 different kinds of ratios of data transfer rate clock signal period to card operation clock signal period.
However, application fields of IC cards equipped with external terminals have been expanded. For example, when an IC card equipped with external terminals is utilized as one of peripheral devices of a personal computer system, a general-purpose interface apparatus is necessarily required such that data can be transmitted and/or received to/from any kind of available IC cards.
In order to realize such a general-purpose interface apparatus satisfying the above requirement, the system of utilizing the universal asynchronous receiver/transmitter (UART) shown in FIG. 1 is disclosed in Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-227147).
FIG. 1 is a schematic block diagram of a circuit arrangement of an interface apparatus disclosed in Japanese Laid Open Patent Disclosure (Heisei JP-A-5-227147). The interface apparatus can perform a data transfer operation with an IC card 50 equipped with external terminals by using the UART 102. In this circuit arrangement, the interface apparatus is composed of a control unit 106 such as a central processing unit (CPU), a host bus 107, a clock signal generating circuit 101 for generating an operation clock signal 105 for the UART 102 from a source clock signal 103, a programmable frequency dividing circuit 100 for generating a card operation clock signal 104 from the source clock signal 103, and the IC card 50 equipped with external terminals. The control unit 106 sets proper values for the programmable frequency dividing circuit 100 and the clock signal generating circuit 101 via the host bus 107. Then, the control unit 100 transfer data via the UART 102 to the IC card 50 equipped with external terminals.
Now, the operations when data is written from and to the control unit 106 to and from the IC card 50 equipped with the external terminals will be described below.
The control unit 106 writes the 1-byte (8 bits) transfer data in a parallel form via the host bus 107 to the UART 102. The UART 102 converts the 1-byte data from in the parallel form to in a serial form, and then sends out this transfer data in the serial form to the IC card 50 equipped with the external terminals.
When data is read from the IC card 50 equipped with the external terminals, the UART 102 converts a serial transfer data received from the IC card 50 equipped with the external terminals into a parallel transfer data. Then, the control unit 106 reads this parallel transfer data via the host bus 107.
In the previously listed Table 1 of the ratios of data transfer clock signal period to card operation clock signal period, necessary frequency division is carried out by the programmable frequency dividing circuit 100 as to ratios having a prime factor of 3 or 5 in a numerator. On the other hand, necessary frequency division is carried out in either a programmable frequency dividing circuit 101a or a programmable frequency dividing circuit 101d as to ratios having a prime factor of 3, 5, or 31 in a denominator. It should be understood that it is defined that the frequency of the operation clock signal of the UART must be a frequency (16.times.n) times (n is a positive integer) higher than frequency in the data transfer rate of the serial transfer data. In other words, the transfer rate becomes 1/16 or less of the input operation clock signal 105 of the UART 102. Therefore, the operation clock signal generating circuit 101 for the UART 102 includes a 1/4 frequency dividing section composed of a phase & frequency comparing circuit 101b, a voltage controlled oscillator (VCO) 101c, and a 1/4 frequency dividing circuit 101e, and prevents the transfer rate from being decreased.
Next, the method for calculating a desirable ratio of data transfer clock signal period to card operation clock signal period in the system shown in FIG. 1 will now be described with reference to an example.
For example, in the case where the ratio of data transfer clock signal period to card operation clock signal period of 18.6 (=3.times.31.div.5) is to be realized, the control unit 106 sets a frequency division ratio of 20 (=2.sup.2 .times.5) through the host bus 107 to the programmable frequency dividing circuit 100, another frequency division ratio of 93 (=3.times.31) to the programmable frequency dividing circuit 101a, and another frequency division ratio of 1 to the programmable frequency dividing circuit 101d. As a result, a clock signal generated by dividing the frequency of the basic clock signal by (3.times.31.div.2.sup.2) is outputted as the UART operation clock signal 105. Thus, the time required to transfer 1 bit data, namely "one etu" is equal to the time obtained by multiplying the time period of the operation clock signal 105 by at least 16. That is, this 1 etu becomes multiplication of (3.times.31.div.2.sup.2 .times.16=3.times.31.times.2.sup.2). Accordingly, as the ratio of data transfer clock signal period to card operation clock signal period, (3.times.31.div.2.sup.2)/(2.sup.2 .times.5), namely (3.times.31.div.5)=18.6 can be obtained.
As described above, it is possible to realize the general-purpose interface apparatus. However, to this end, there is a problem in that it is rather difficult to generate the necessary high-speed basic clock signal. Moreover, there is another problem in that power consumption is increased and also electromagnetic interference is increased.
In other words, in view of the specification of the UART, the frequency of the operation clock signal for the UART must be made 16 times, or more higher than the transfer rate. For this reason, for instance, when it is assumed that the ratio of data transfer clock signal period to card operation clock signal period after the initial response of the external clock signal IC card is equal to 11.625 (=3.times.31.div.2.sup.3), if the card operation clock signal frequency is selected to be 1, the transfer rate capable of realizing this ratio becomes (2.sup.3 .div.(3.times.31)) times higher than this card operation clock signal frequency. Accordingly, the operation clock signal supplied to the UART must have the frequency of 16 times of the transfer rate, namely, 2.sup.7 .div.(3.times.31)=128/93 time the card operation clock signal frequency. However, in the above-described conventional circuit containing the 4-multiplication phase synchronization loop (PLL) circuit, it is not possible to generate a clock signal having a frequency higher than 2.sup.2 .div.(3.times.31). Therefore, the operation clock signal for the UART must be generated by frequency-dividing the card operation clock signal by 2.sup.5, namely 32. In other words, the basic clock signal should has the frequency at least 32 times higher than that of the card operation clock signal. For example, in order to transfer data to an IC card with external terminals operating with a clock signal having a frequency of 5 MHz, the basic clock signal having a frequency of 160 MHz at least is required. This requirement would cause the following problems. That is, for instance, in a system such as a battery-operated type portable computer, not only the power consumption is increased, but also the electromagnetic interference to external devices is increased. Also, it is rather difficult to generate such a basic clock signal having a properly selected high frequency.
In the above-described conventional technique as described in the Japanese Laid open Patent Disclosure, the PLL circuit required for the clock signal generating circuit is constituted by the analog voltage controlled oscillator (VCO) and the analog phase comparator. Therefore, there is a problem in that the space required for these analog circuits becomes several thousands to tens of thousands times larger than the space required for a digital circuit made of the digital transistors elements. Also, there is another problem in that the power consumption caused by stationarily flowing currents is large.
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