In recent years, with an increase in the size of an information processing system, the capacity of a memory to be installed in the system has increased, and there has been a demand for high reliability of a memory. In order to ensure high reliability of a large-capacity memory, there is a demand to quickly detect the location of a failure that occurs in the memory.
For the detection, there is a known technique for detecting a memory failure that is a defective connection of a data bus, a defective connection of an address bus or the like, which occurs during implementation of a board. Japanese Laid-open Patent Publication Nos. 2004-334707 and 2008-171287 are examples of related art.
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