1. Field of the Invention
The present invention relates to a plastic-encapsulated semiconductor device with the Lead-On-Chip (LOC) package structure and more particularly, to a plastic-encapsulated semiconductor device equipped with an Integrated Circuit (IC) chip and lead fingers extending over the chip and electrically connected to the bonding pads of the IC chip through metal wires, in which at least one of the lead fingers serving as a power/ground line has a bus-bar extending over the chip and electrically interconnecting the power/ground line with one of the pads of the chip serving as a power/ground terminal.
2. Description of the Prior Art
In recent years, as the operation speed of Dynamic Random-Access Memories (DRAMs), in which a memory IC chip is typically encapsulated by a plastic package, has been becoming higher, the need of reinforcing the power and ground lines in the plastic package of the DRAM has been becoming important more and more in the package design operation. This is due to the following reason.
Specifically, if the electric resistance of the power and ground lines in the plastic package is high, the electric potentials at the power and ground terminals of the memory IC chip tend to fluctuate. This electric potential fluctuation will lower the access speed to the memory cells in the chip. Therefore, the electric resistance of the power and ground lines needs to lower by reinforcing or thicken the power and ground lines according to the increasing operation speed.
A conventional LOC package structure of a plastic-encapsulated semiconductor device (e.g., a DRAM) is shown in FIGS. 1 and 2. In this conventional package, the bonding pads of a memory IC chip are arranged in the central area of its upper surface. Therefore, this arrangement of the bonding pads is termed the "center pad structure".
As shown in FIG. 1, this semiconductor device is comprised of an IC chip 107, bonding pads 101 provided on the top surface 107a of the chip 107, lead fingers 122a, 122b, 122c, and 122d, metal bonding wires 105, and a plastic package 108. Since the chip 107 has the center pad structure, the bonding pads 101 are arranged along a straight line at regular intervals in a central area 110 of the top surface 107a of the chip 107.
First and second double-coated, non-conductive adhesive tapes 106a and 106b are arranged on the top surface 107a of the chip 107 at each side of the central area 110. The coated lower faces of the tapes 106a and 106b are attached to the top surface 107a to be fixed thereon. The tapes 106a and 106b extend in parallel to the row of the bonding pads 101.
The lead fingers 122a, 122b, 122c, and 122d are formed by a metallic leadframe. The inner ends of the lead fingers 122a, 122b, 122c, and 122d serve as bonding areas 103a, 103b, 103c, and 103d, respectively. These bonding areas 103a, 103b, 103c, and 103d are termed "stitches".
The lead fingers 122a and 122b provided on the left side of FIG. 1 are attached at their stitches, 103a and 103b to the coated upper face of the first tape 106a, thereby fixing the lead fingers 122a and 122b to the chip 107. The lead fingers 122c and 122d provided on the right side of FIG. 1 are attached at their stitches 103c and 103d to the coated upper face of the second tape 106b, thereby fixing the inner ends of the lead fingers 122c and 122d to the chip 107.
One of the lead fingers 122a located at the top of FIG. 1 serves as a first power line through which a power supply voltage VCC is supplied to the IC chip 107. One of the lead fingers 122b located at the bottom of FIG. 1 serves as a second power line through which the power supply voltage VCC is supplied to the IC chip 107. The inner end (i.e., the stitch 103a) of the lead finger 122a serving as the first power line and the inner end (i.e., the stitch 103b) of the lead finger 122b serving as the second power line are mechanically and electrically connected to one another through a first bus-bar 104a.
The first bus-bar 104a, which is made of the same material as that of the lead fingers 122a, 122b, 122c, and 122d, is located between the row of the pads 101 and the first tape 106a to extend along them. The first bus-bar 104a has a protruding portion serving as a bonding area (i.e., stitch) 103a' at its middle. This stitch 103a' is located between the group of the lead fingers 122a and the group of the lead fingers 122b. The first bus-bar 104a is attached to the coated upper face of the first tape 106a, thereby fixing the central part of the first bus-bar 104a to the chip 107.
One or the lead fingers 122c located at the top of FIG. 1 serves as a first ground line through which a specific ground potential GND is supplied to the IC chip 107. One of the lead fingers 122d located at the bottom of FIG. 1 serves as a second ground line through which the specific ground potential GND is supplied to the IC chip 107. The inner end (i.e., the stitch 103c) of the lead finger 122c serving as the first ground line and the inner end (i.e., the stitch 103d) of the lead finger 122d serving as the second ground line are mechanically and electrically connected to one another through a second bus-bar 104b.
The second bus-bar 104b, which is made of the same material as that of the lead fingers 122a, 122b, 122c, and 122d, is located between the row of the pads 101 and the second tape 106b to extend along them. The second bus-bar 104b has a protruding portion serving as a bonding area (i.e., stitch) 103b' at its middle. This stitch 103b' is located between the group of the lead fingers 122c and the group of the lead fingers 122d. The second bus-bar 104b is attached to the coated upper face of the second tape 106b, thereby fixing the central part of the second bus-bar 104b to the chip 107,
Each of the lead fingers 122a, 122b, 122c, and 122d is electrically connected to a corresponding or adjoining one of the bonding pads 101 at their bonding areas or stitches 103a, 103b, 103c, and 103d by a stitch-bonding process through a metallic bonding wire 105. One of the bonding pads 101, which is located near the center of the chip 107, is electrically connected to the first bus-bar 104a designed for the first and second power lines through a metallic bonding wire 105. Another of the bonding pads 101, which is located near the center of the chip 107, is electrically connected to the second bus-bar 104b designed for the first and second ground lines through a metallic bonding wire 105.
The IC chip 107, the bonding wires 105, the first and second bus-bars 104a and 104b, and the inner portions 102a, 102b, 102c, and 102d of the lead fingers 122a, 122b, 122c, and 122d are encapsulated in the plastic package 108. The inner portions 102a, 102b, 102c, and 102d are termed "inner leads".
Only the outer portions 109a, 109b, 109c, and 109d of the lead fingers 122a, 122b, 122c, and 122d are located outside the package 108, thereby providing input/output (I/O) terminals of this semiconductor device, The outer portions 109a, 109b, 109c, and 109d are termed "outer leads".
With the above-described conventional plastic-encapsulated semiconductor device shown in FIG. 1, as seen from FIG. 2, it is necessary for the bonding wires 105 to be bonded to extend over the intervening bus-bar 104a or 104b. This means that the over-lead bonding technique is essential in the wire-bonding operation for this device.
Therefore, unless the loop height of the bonding wires 105 is large enough, there is a possibility that some of the bonding wires 105 may contact with the bus-bar 104a or 104b in the molding operation of the plastic package 108. As a result, a thin package such as the popular Thin Small Outline L-leaded Package (TSOP) is difficult to be used for the plastic package 108.
On the other hand, a thick package such as a Small Outline J-Leaded Package (SOJ) may be applied to the package 108 by using the over-lead bonding technique, because the satisfactory loop height of the bonding wires 105 is ensured in the thick package. In this case, however, there is a problem that the post-molding spacing between the bonding wires 105 and the bus-burs 104a and/or 104b is unable to be observed or inspected three-dimensionally by the use of a known two-dimensional non-destructive inspection method such as the X-ray inspection in the testing operation.
Moreover, when the over-lead bonding technique is actually applied to a package such as the TSOP, some measure needs to be used to avoid the touch or contact of the bonding wires 105 with the bus-bars 104a and 104b after the molding process of the package 108. Two examples of the measures are shown in FIGS. 3 and 4.
In FIG. 3, half-etched bus-bars 104a' and 104b' are used to increase the post-molding spacing between the bonding wires 105 and the bus-burs 104a' and 104b'. In this case, however, there arises another problem that the fabrication cost of the leadframe becomes higher.
In FIG. 4, insulating layers 114a and 114b are formed or coated to cover the upper faces of the bus-burs 104a and 104b, respectively. In this case, however, there arises another problem that the fabrication cost of the leadframe becomes higher and that the insulating layers 114a and 114b tend to be separated from the molding plastic of the package 108. The separation of the layers 114a and 114b degrades the reliability of the package 108.
USPTO Backgrounds
USPTO Backgrounds