The present invention relates to a fault simulation method and, more particularly, to a fault simulation method adapted to perform fault simulation of a logic circuit at a high speed.
Logic simulation is a known technique for realizing the operation of a logic circuit on a computer and analyzing the operation of the logic circuit. Logic simulation has been performed at a high speed by using a vector processor capable of implementing the operation of a large amount of vector data. This technique implements integration of gates in order to reduce the number of loading and storing operation for performing the vector operation at a high speed. In performing the vector operation by the vector processor, it is preferred that a record length of data as an object for the operation is a fixed length, so that the logic modification is implemented to fix the number of input and output pins of each of the logic gates for performing the logic simulation. The logic circuit to be the object for the logic simulation is logically modified into a logic circuit configuration using logic gates in which the number of input and output pins is constant, and the logic gate data for describing the logic gate is assigned a fixed data length so that the length of each of the data to be operated on by the vector processor is a fixed length.
A logic simulation method of the logic circuit of this type is disclosed, for example in Japanese Patent Unexamined Publication (kokai) No. 221,745/1987 entitled "Logic Circuit Simulation Method". This logic circuit simulation method provides a logic simulator for simulating a logic operation of the logic circuit to carry out the simulation in accordance with three steps. First, the number of input signals (the number of input and output pins) of a gate forming a simulation circuit to be simulated is processed to agree with a predetermined basic gate form. In the second step, an output signal value of the gate is propagated in sequence from one gate to another and all of the propagating gates in the logic circuit are divided into units of destinations of the propagating gates. The third step performs a batch calculation of output signal values of an aggregate of the divided gates.
A fault simulation method is known in which fault simulation is performed by injecting a fault value into a fault assumption portion of a logic circuit to which fault simulation is to be proformed and by implementing simulation in a manner similar to the logical simulation. This fault simulation method has the difficulty that a fault propagates as it expands through the logic circuit so that the processing for following a path of the propagation of the fault becomes very complicated. The logic circuit to which the fault simulation is performed in this case is restricted to a gate having only one output and a fault logic value is set in the pin of the gate, thereby injecting the fault into the logic circuit.
It is noted that in order to implement processing at a high speed in performing logic simulation by using a vector processor, the logic circuit is logically modified into the logic circuit configuration using logic gates of a basic gate form in which the number of the input and output pins of each logic gate is fixed, so that the positions of the pins of the gate of the actual logic circuit to which logic simulation is performed may not correspond to the pins of the gate subsequent to the logical modification in a 1-to-1 manner. Therefore, the fault value cannot readily be injected into the fault assumption portion of the logical circuit concerned, so that the fault simulation cannot appropriately be executed. In order to enable a 1-to-1 correspondence of the positions of the pins of the gate of the actual logic circuit as the object for the logic simulation to the positions of the pins of the gate subsequent to the logical modification, the logic circuit can be logically modified by the logic gate of a basic gate form in which the number of input and output pins is fixed. However, this logical modification requires a surplus of fixed value gates and generating gates, thereby having the difficulty that the fault simulation of a large-scale logic circuit cannot be performed at a high speed.
It is further noted that the injection of the fault logic value for performing the fault simulation requires the fault logic value of the gate or pin which assumes a fault to be changed during the fault simulation, so that if the fault logic value cannot easily be injected, it is required that conditions should be branched off in a complex manner during the fault simulation. This cannot take advantage of the high-speed processing ability of a vector processor to a sufficient extent.
USPTO Backgrounds
USPTO Backgrounds