1. Field of the Invention
The present invention relates to a method for controlling a semiconductor storage device, and also to a memory card. For example, the present invention relates to signal processing performed for read and write operations of a flash memory.
2. Description of the Related Art
Conventionally, there is known a NAND-type flash memory including memory cells each configured to hold 2-bit information, an example of which is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2001-93288 (which will be referred to as a multi-level NAND-type flash memory, hereinafter). A write operation of data to a multi-level NAND-type flash memory is performed by first writing lower bits and then writing upper bits. At this time, in general, writing of the upper bits takes longer time than writing of the lower bits.
Further, in a system LSI or the like provided with a multi-level NAND-type flash memory, signal processing of various kinds is performed in conjunction with writing and reading of data relative to the multi-level NAND-type flash memory.
In general, according to the conventional method, the upper bit writing and the lower bit writing in a multi-level NAND-type flash memory are designed to use the same length of one cycle period for signal processing. However, the upper bits and lower bits require different time lengths for data writing. Accordingly, there is a problem in that the processing efficiency is decreased due to, e.g., the occurrence of a useless latency time for signal processing.
USPTO Backgrounds
USPTO Backgrounds