Charge trapping non-volatile memory cells are typically based on an n-MOSFET with the gate dielectric replaced by a memory layer stack having a charge trapping layer. Insulator layers separate the charge trapping layer from the gate electrode and the semiconductor channel region of the n-MOSFET.
In charge trapping memory cells of the TANOS structure (tantalum-alumina-nitride-oxide-semiconductor), the charge trapping layer is a silicon nitride layer. An alumina layer separates the silicon nitride layer from a tantalum nitride gate electrode. In a charge trapping memory cell of the SONOS structure (silicon-oxide-nitride-oxide-silicon) the charge trapping layer is a silicon nitride layer sandwiched between two silicon oxide layers, wherein the gate electrode is a polysilicon electrode.
In addition to the memory cells, an integrated circuit with memory functionality includes logic and interface circuits based upon cost-efficient CMOS transistors. Integration concepts are needed which allow integrating the fabrication of non-volatile memory cells into standard CMOS process flows. Due to the different materials used for the peripheral circuitry on one hand and the memory array on the other hand, the process requirements concerning the memory cells and the CMOS circuitry differ significantly from each other, for example, if the non-volatile memory cells include materials which are not used in the standard CMOS process flow, such as alumina or tantalum nitride.
A need exists for an integration scheme which combines the manufacture of both CMOS circuitry and non-volatile memory cells and which may be applied to different types of memory cells without essential modifications, for example with regard to the photolithographic masks.
For these and other reasons, there is a need for the present invention.
USPTO Backgrounds
USPTO Backgrounds