This invention relates to memory circuits, and more particularly, to memory circuits which detect an address transition.
A technique for improving memories has developed by using a pulse generated from an address transition. In many memory circuits the only time it is necessary to execute a read of data is when a transition of the address occurs. If the address does not change, the data that is being provided on the output is still valid. Consequently, there is no reason to prepare any of the circuitry associated with sensing stored data. This fact has been used to advantage to wait until the address changes to make such preparation. Speed can be increased by precharging bit sense lines in response to an address transition. It is also possible to save power by waiting until an address transition before enabling certain circuitry which is not necessary during steady state operation. In order to implement any of these advantages it is necessary to be able to quickly and reliably detect an address transition.
U.S. Pat. No. 4,099,265, Abe, discloses a technique for address transition detection which uses two series connected transistors for each address bit. One of the transistors receives the true address signal and the other receives the complementary address signal of the particular address bit. For any steady state condition, one of the transistors will be turned on and one will be turned off. During a transition of the address bit, the true and complementary signals will switch states but not instantly. There will be a finite rise and fall time. During this rise and fall time there is a short time during which both transistors are conducting, thereby establishing a conductive path. The establishment of the conductive path provides the detection of the address transition. One of the problems with this technique is that in practice one of the true or complementary signals will begin changing before the other. This can result in a very short duration when the transition is in one direction and a somewhat longer duration when the transition is in the other direction. Consequently, substantial additional circuitry may be required for signal shaping to ensure that the detection pulse is of sufficient duration to be useful.
Another technique is to provide a delay for each of the true and complementary signals. Each delayed signal is coupled to the control electrode of a transistor. Each undelayed address signal is coupled to a current electrode of the transistor which receives the delayed address signal of the opposite logic state. In a steady state condition one of the transistors, the one with a logic high on its control electrode, is conducting while the other transistor is turned off. Because the transistor which is conducting has a logic low on a current electrode, it does not cause a detection signal to be generated. When the address signal changes, however, the current electrode receives a logic high before the control electrode switches to a logic low because of the delay to the control electrode. Consequently for the duration of the delay to the control electrode, the transistor conducts a logic high to its other current electrode. Such presence of the logic high constitutes detection of an address transition. One disadvantage of this technique is that a substantial amount of circuitry is required. One implementation of this technique for a static RAM is described in U.S. Pat. No. 4,355,377, Sud et al.
USPTO Backgrounds
USPTO Backgrounds