1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various methods of removing a fin when forming FinFET semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially field effect transistors (FETs), are provided and operated on a restricted chip area. Such field effect transistors (both NFETs and PFETs) operate in a switched mode, that is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
FETs come in a variety of configurations, planar devices, nanowire devices, FinFET devices, etc. A planar transistor device is normally manufactured in an active region of a substrate having a substantially planar upper surface. In contrast to a planar FET, a so-called FinFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device “A” that is formed above a semiconductor substrate B that will be referenced so as to explain, at a very high level, some basic features of a FinFET device. In this example, the FinFET device A includes three illustrative fins C, a gate structure D, sidewall spacers E and a gate cap layer F. Trenches T are formed in the substrate B to define the fins C. The gate structure D is typically comprised of a layer of gate insulating material (not separately shown), e.g., a layer of high-k insulating material (k-value of 10 or greater) or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device A. The fins C have a three-dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device A when it is operational. The portions of the fins C covered by the gate structure D are the channel regions of the FinFET device A. In a conventional process flow, the portions of the fins C that are positioned outside of the spacers E are the source/drain regions of the device A. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device.
Both planar and FinFET semiconductor devices are typically electrically isolated from adjacent transistor devices so that they can perform their intended function. This is typically accomplished by forming an isolation structure, e.g., a shallow trench isolation structure, in the semiconducting substrate around the transistor device. Traditionally, isolation structures were typically the first structure that was formed when manufacturing semiconductor devices. The isolation structures were formed by etching the trenches into the substrate for the isolation structures, and thereafter filling the trenches with the desired insulating material, e.g., silicon dioxide. After the isolation structures were formed, various process operations were performed to manufacture the transistor devices.
In the case of FinFET devices, these process operations involved masking the previously formed isolation structure, and thereafter etching the trenches into the substrate that defined the fins. However, as the dimensions of the fins became smaller, problems arose with manufacturing the isolation structures before the fins were formed. As one example, trying to accurately define very small fins in regions that were separated by relatively large isolation regions was difficult due to the non-uniform spacing between various structures on the substrate. One manufacturing technique that is employed in manufacturing FinFET devices is to initially form a plurality of “fins” that extend across the entire substrate, i.e., sometimes referred to as a “sea of fins,” and thereafter remove some of the fins where larger isolation structures will be formed. Using this type of manufacturing approach, better accuracy and repeatability may be achieved in forming the fins to very small dimensions due to the more uniform environment in which the etching process that forms the trenches is performed.
There are two commonly employed techniques for accomplishing the goal of removing the desired number of fins (or portions thereof). One such removal process is typically referred to as “Fins-cut-First.” In this process, one or more features of a patterned masking layer that is formed above the initial substrate is selectively exposed and removed prior to performing a fin formation etching process through the patterned masking layer. As a result, in the region where the masking feature(s) was removed from the patterned masking layer, the substrate is etched to define a wider trench that is free of any fin structures. This wider trench is then filled with an insulating material, e.g., silicon dioxide.
Another fin removal process is typically referred to as “Fins-cut-Last.” In this process, a patterned masking layer with features corresponding to the desired sea-of-fins is formed above the initial surface of the substrate. Thereafter, a fin-formation etching process is performed through the patterned masking layer to form the trenches across the entire substrate and thereby define the sea-of-fins. Next, the portions of the sea-of-fins that are to be removed are exposed by another patterned masking layer and removed by performing an etching process. This defines a larger trench that is free of fin structures. The larger trench is then filled with an insulating material, such as silicon dioxide.
FIG. 1B depicts a problem that may arise when using a Fins-cut-Last fin removal process when trying to remove only a single fin so as to form a desired isolation structure between adjacent FinFET devices. FIG. 1B depicts a device 10 at a point in fabrication wherein a plurality of trenches 17 were etched into a substrate 12 so as to define a plurality of fins 13. The etching process was performed through a patterned etch mask 14. FIG. 1B also depicts the device 10 after a layer of insulating material 19 was deposited into the trenches 17, and after a CMP process was performed using the patterned etch mask 14 as a polish-stop layer. In the example depicted in FIG. 1B, it is desired to remove only the single fin 15 so as to form a portion of an isolation region (not shown) in its place after removal. A patterned masking layer 22, e.g., a patterned layer of photoresist, with an opening 22A is formed on the device 10.
In earlier generation devices, the dimensions of the fins 13 and the width of the trenches 17 were such that one or more etching processes could be performed though the opening 22A to remove the single fin 15. However, device dimensions have continued to shrink, e.g., the lateral width of the fins 13 may be on the order of about 10 nm or less, and the width of the trenches 17 may be on the order of about 20 nm or less. Accordingly, the size 18 of the opening 22A that is needed to remove only the single fin 15 is so small, e.g., 30 nm or less, that an opening 22A with the desired smaller size 18 cannot be formed using a single patterned photoresist masking layer, such as the patterned photoresist layer 22. One possible solution would be to use more complex and expensive double patterning techniques to define a patterned masking layer (typically a hard mask layer) with an opening having the desired size 18. Another possible solution would be to simply increase the number of fins being removed from say one to three, thereby making the size of the opening 18 one that can be formed using a single patterned photoresist masking layer. However, this latter approach would result in undesirable consumption of extremely valuable plot space on the substrate, and be counter to the desire by all integrated circuit manufacturers to increase packing densities and reduce the physical size of the overall final integrated circuit product. The problems discussed above apply equally to the so-called “Fins-cut-First” fin removal process.
The present disclosure is directed to various methods of removing a fin when forming FinFET semiconductor devices.
USPTO Backgrounds
USPTO Backgrounds