FIG. 19 is a cross-sectional view illustrating a resistor element of a prior art semiconductor device. In the figure, reference numeral 101 designates a semi-insulating GaAs substrate, reference numeral 103 designates a stripe-shaped resistor region having a prescribed width and length at the surface of the semi-insulating GaAs substrate 101, and reference numerals 102a and 102b designate electrodes comprising metal (terminals).
The method of fabricating a resistor element of a prior art semiconductor device will be described. First, the region of the surface of the semi-insulating GaAs substrate 101 where the resistor region 103 is to be formed is ion-implanted with dopant impurities using a photoresist (not shown in the figure) as a mask. Then, annealing is performed to electrically activate the implanted ions, thereby forming the stripe-shaped resistor region 103 having a prescribed width. Furthermore, the electrodes 102a and 102b are disposed on both ends of the stripe-shaped resistor region 103 preferably by evaporation, thereby completing the resistor element.
In the prior art semiconductor device, the electrodes 102a and 102b are connected to electrodes of other circuit elements with lines or the like to make use of the resistor region 103 as a resistor element, and the resistance is determined by the quantity of ions implanted into the resistor region, the width and the length of the resistor region, and the like.
If the quantity of ions implanted is constant, the resistivity of the resistor element is constant. Since there is a limit to changing widths, lengths, and the like, within the limited area of a chip or the like, it is extremely difficult to form multiple resistor elements with resistances that differ considerably, by a factor of a hundred, for example, on the chip in a single ion implantation step. Although it is possible to change the resistivity of the resistor element by changing the quantity of ions implanted, thereby changing the resistance, it would, however, be necessary in this case to perform multiple implantation steps, which would complicate processing.
On the other hand, a semiconductor device having a structure including a one-dimensional carrier distribution has been proposed, and research aimed at its realization has been conducted. FIG. 20 is a cross-sectional view illustrating a structure of a high electron mobility transistor as an example of a prior art semiconductor device having this one-dimensional carrier distribution. In the figure, reference numeral 111 designates a semi-insulating GaAs substrate the surface of which is tilted from the (100) surface by a prescribed angle so that atomic steps, i.e., steps with a height corresponding to a single atom, are formed on its surface. Reference numerals 112 and 114 designate an AlGaAs layer, reference numeral 113 designates a one-dimensional electron channel layer, reference numeral 115 designates a gate electrode, reference numeral 106 designates a source electrode, and reference numeral 117 designates a drain electrode.
FIGS. 21(a)-21(e) are views illustrating a method of the fabricating the high electron mobility transistor shown in FIG. 20. In the figures, the same reference numerals used in FIG. 20 designate the same or corresponding parts. Reference numeral 118 designates an AlAs layer, reference numeral 119 designates a GaAs layer, and reference numeral 120 designates atomic steps. FIG. 21(a) is a view illustrating a cross-section of the high electron mobility transistor of FIG. 20 sectioned perpendicular to the gate length direction. FIGS. 21(b)-21(e) are views magnifying the surface of the AlGaAs layer 112 of FIG. 21(a).
A fabricating method will be described. First, as shown in FIG. 21(a), the semi-insulating GaAs substrate 111 is held tilted from the (100) surface by a prescribed angle (several degrees), and the AlGaAs layer 112 is grown on the GaAs substrate 111, preferably by metal organic chemical vapor deposition (MOCVD). During this process, as shown in FIG. 21(b), the multiple atomic steps 120, which are separated by the same distance from each other and are parallel, are formed on the surface of the AlGaAs' layer 112 along the line where the surface of the AlGaAs layer 112 and the (100) surface intersect.
The AlAs layers 118 are grown at the atomic steps 120 by "step flow growth" described in Applied Physics Letters, Volume 50, Page 824 (1987). The "step flow growth" mechanism is a process of crystal growth of an atomic layer along an atomic step of a semiconductor substrate crystal layer in which atoms supplied to the semiconductor substrate layer diffuse along the surface and become attached with priority to the atomic steps. In the present case, the AlAs layers 118 are grown by a single atomic layer along the atomic steps 120 until the width becomes half the distance between two neighboring atomic steps (FIG. 21(c)). The GaAs layers 119 are grown next to the AlAs layer 118 by the step flow growth mechanism until they reach the neighboring atomic step 120 (FIG. 21(d)). This step flow growth, as shown in FIG. 21(e), is repeated a number of times so that the AlAs layer and the GaAs layer are stacked on the AlAs layer 118 and the GaAs layer 119, respectively, thereby forming the one-dimensional channel layer 113.
The AlGaAs layer 114 is formed on the one-dimensional layer 113. The openings for forming the source electrode 106 and the drain electrode 117 are formed by etching the AlGaAs layer 114 along the direction in which the atomic steps 120 extend. The source electrode 106 and the drain electrode 117 are formed at the portions of the one-dimensional conduction layer 113 which are exposed by the etching step. The gate electrode 115 is formed on the AlGaAs layer 114 at a mid-point between the source electrode 106 and the drain electrode 117, preferably by evaporation, thereby completing a high electron mobility transistor having the source electrode 106, the gate electrode 115, and the drain electrode 117 along the direction in which the atomic steps 120 extend as shown in FIG. 20.
In the prior art high electron mobility transistor described above, the multiple AlAs layers 118 which have a stripe shape and extend along the direction in which the atomic steps 120 extend are formed within the one-dimensional channel layer 113. The band gap energy of the AlAs layer 118 is smaller than both the band gap energy of the neighboring GaAs layer 119 and the band gap energies of the AlGaAs layer 112 and the AlGaAs layer 114 which sandwich the AlAs layers 118. Therefore, the electrons are confined in the AlAs layers 118 in a one-dimensional state. By forming the source electrode 106 and the drain electrode 117 along the stripe direction of the AlAs layer 118, the AlAs layer 118 can be used as a one-dimensional electron channel, and this makes it possible to drive the electrons at high speed, thereby operating the high electron mobility transistor at high speed.
However, in the prior art high electron mobility transistor, as described above, it is necessary to perform the step flow growth repeatedly when the AlAs layers 118 and the GaAs layers 119, which form the one-dimensional layer 113, are formed, making the fabricating process extremely complicated. Furthermore, in order to stack the AlAs layers 118 with high precision, exact control of the step flow growth is necessary, requiring an expensive growth facility having a high degree of controllability.
As described above, the resistivities are the same for resistor elements that are formed through the same processes in the prior art semiconductor device. Therefore, it is extremely difficult to simultaneously form multiple resistor elements having considerably different resistances in a single chip. In order to form multiple resistor elements having considerably different resistances in a single chip, it is necessary to form the resistor elements through multiple processes, complicating fabrication of a semiconductor device.
Furthermore, in the prior art semiconductor device, in order to form a structure that can produce a one-dimensional carrier distribution that is effective in improving characteristics of the semiconductor device, it is necessary to use step flow growth or the like. This step flow growth considerably complicates the fabricating process and it is difficult to improve the productivity of the semiconductor device to a practical level.
USPTO Backgrounds
USPTO Backgrounds