1. Technical Field
The present invention relates to a circuit and method for controlling a sense amplifier of a semiconductor memory apparatus, and more particularly, to a circuit and method for controlling a sense amplifier of a semiconductor memory apparatus that prevents a malfunction due to lack of an operation voltage for bit line sensing during a refresh operation.
2. Related Art
In general, a DRAM (Dynamic Random Access Memory) performs a data input/output operation by sensing a pair of bit lines BL and /BL, that is, a bit line BL and a sub bit line /BL connected to a memory cell as a core voltage level Vcore and a ground voltage level VSS, respectively. In a bit line sense amplifier that performs a bit line sensing operation, a sense amplifier driving signal that applies the core voltage level is referred to as RTO, and a sense amplifier driving signal that applies the ground voltage level is referred to as SB. In order to sense a bit line of an arbitrary memory bank, it is necessary that an active command and a precharge command are input from the outside of a memory apparatus to a sense amplifier control circuit and then a sense amplifier driving signal is generated and transmitted to each sense amplifier. The sense amplifier driving signal is generated on the basis of a sense amplifier control signal. The sense amplifier control signal is a general term for an RTO enable signal and an SB enable signal, which will be described below.
In a general semiconductor memory apparatus, one-by one, a plurality of memory banks perform a bit line sensing operation during a normal operation. However, in a refresh operation, the plurality of memory banks simultaneously perform the bit line sensing operation. When a refresh signal is enabled, each area in the semiconductor memory apparatus goes into a refresh operation mode.
Hereinafter, a sense amplifier control circuit according to the related art will be described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram illustrating the structure of a circuit for controlling a sense amplifier of a semiconductor memory apparatus according to the related art.
The illustrated circuit for controlling sense amplifier includes a sense amplifier control unit 10 and a sense amplifier driver 20. The sense amplifier control unit 10 receives an active command act and a precharge command pcg and generates and outputs an RTO enable signal RTO_enb and an SB enable signal SB_enb, which are sense amplifier control signals. The sense amplifier driver 20 generates an RTO signal and an SB signal, which are sense amplifier driving signals, in response to the RTO enable signal RTO_enb, the SB enable signal SB_enb, and a bit line equalization signal bleq.
When the active command act input to the sense amplifier control unit 10 is enabled, the RTO enable signal RTO_enb and the SB enable signal SB_enb are enabled and output. The enabled states of the RTO enable signal RTO_enb and the SB enable signal SB_enb are held until the precharge command pcg is enabled.
When the bit line equalization signal bleq input to the sense amplifier driver 20 is enabled, the voltage level of the RTO signal and the SB signal is equal to the bit line precharge voltage level. However, when the bit line equalization signal bleq is disabled, the supply of the bit line precharge voltage is cut off. Thereafter, when the RTO enable signal RTO_enb is enabled, the voltage level of the RTO signal is equal to a core voltage level, and when the SB enable signal SB_enb is enabled, the voltage level of the SB signal is at the ground voltage level.
In this case, the bit line equalization signal bleq is a signal enabled by the precharge command pcg. The bit line equalization signal bleq is disabled in an active mode and enabled in a precharge mode.
The RTO signal and the SB signal generated by the sense amplifier driver 20 are transmitted to a sense amplifier and convert the voltage levels of a pair of bit lines BL and /BL into the bit line precharge voltage level in the precharge mode and into the core voltage level and the ground voltage level in the active mode, respectively.
FIG. 2 is a graph that explains a bit line sensing operation according to the related art and illustrates a process in which the bit line BL and the sub bit line /BL are sensed as the level of the core voltage Vcore and the level of the ground voltage VSS, respectively.
In FIG. 2, a variation in the voltage levels of the pair of bit lines BL and /BL during the bit line sensing operation of the sense amplifier is shown. When a word line WL is enabled after the active command act is enabled, the bit line sensing operation starts. Thereafter, when sense amplifier control signals ctrl, that is, the RTO enable signal RTO_enb and the SB enable signal SB_enb, are enabled, a voltage difference between the pair of bit lines BL and /BL is amplified. When the voltage difference between the pair of bit lines BL and /BL is amplified to at least a predetermined level, it is possible to perform a read or write operation in a memory cell. When the precharge command pcg is enabled after a predetermined time has elapsed, the pair of bit lines BL and /BL are precharged to have a voltage level of Vcore/2. In FIG. 2, the bit line sensing process for only one period is illustrated.
As described above, in the refresh operation, all the sense amplifiers provided to a plurality of memory banks simultaneously perform the bit line sensing operation. Therefore, the driving power of the sense amplifier is lower than a normal operation in which only one memory bank is operated. As a result, the voltage difference between the pair of bit lines BL and /BL is smaller or is amplified later, as compared to the normal operation. When the voltage difference between the pair of bit lines BL and /BL is not amplified to the predetermined level, a malfunction can occur in the read or write operation of a memory cell. The bit line sensing process in the refresh operation is the same as shown by dotted lines (A) in FIG. 2.
In order to improve the driving power of the sense amplifier, an initial voltage difference dV between the pair of bit lines BL and /BL should be a predetermined level or more from after the word line WL is enabled to before the sense amplifier control signal ctrl is enabled. In the refresh operation in which the driving power of the sense amplifier decreases, an initial time for a bit line sensing operation longer than that in the normal operation is required in order to ensure the initial voltage difference dV of the predetermined level or more. However, in the related art, since the initial voltage difference dV is not sufficiently ensured in the refresh operation, the potential difference between the pair of bit lines BL and /BL is not sufficiently amplified. Therefore, a malfunction may occur in the read or write operation of the memory cell.
USPTO Backgrounds
USPTO Backgrounds