Integrated circuits are typically fabricated on a flat semiconductor substrate or wafer, via lithography processes, for example, and include layers of active elements, such as transistors, for example, insulating material layers, and metallization layers of active conductive traces to connect the transistors and other devices together. Maintaining the planarity of the semiconductor wafer surface during fabrication is crucial to insure that there is no accidental coupling of active conductive traces of integrated circuits on the wafer, and to reduce depth-of-focus problems by providing a surface with a constant height for subsequent lithography processes.
Chemical mechanical polishing (CMP) is one technique employed for planarizing the top surface of an in-process wafer or substrate prior to deposition of a next layer. One drawback to CMP, however, is that removal rates are different for different materials, such as oxide or copper, for example. As such, if large areas of material with high removal rates are present on the wafer surface, it will lead to non-uniform removal rates, often referred to as “dishing” and “erosion”. Thus, in order to achieve a uniform average removal rate, it is important to have approximately the same average material composition over the surface of the chip and wafer. CMP requires less effort and provides better results if the average composition (i.e. spatial density of various materials) of the surface is uniform on a large scale (for example, some hundreds of microns). However, plasma etching and lithography are sensitive to even small range non-uniformities (below some microns).
One technique presently employed in attempts to achieve a uniform layer density is the addition of dummy or fill structures. Fill structures are structures that are not necessary for the main electrical functionality of a device and are positioned in spaces between active conductive traces which would otherwise be filled only with insulating material. After the active components of a layer have been configured, fill structures are laid out in the gaps or spaces by either an automated fill algorithm or by hand. Fill structures are generally metal elements which are not connected or activated, but in some instances, may be grounded (i.e. “connected”).
In the upper metal layers, two types of fill are generally used: “square fills” and “track fills”. Square fills are relatively large and have relatively small capacitive side effects, but do not fit effectively into many gaps and, as result, even after filling, density uniformity is often still poor. Track fills are similar in shape to active conductive traces and generally fit better into smaller gaps than square fills. Each of these fills requires extensive calculation efforts in the chip layout, particularly for layers not having a “simple” geometry. Routing layers, such as the upper metals, are typically of simple geometry (e.g. having long parallel conductive traces) so that adding the fill is relatively easy. However, layers forming the standard logic cell wiring, such as the first metal layer, and sometimes the second metal layer, are much more complicated.
Unfortunately, for cost purposes, the acceptable calculation time available for calculating fill layouts is limited, so that fill layout solutions created by automated fill algorithms are generally sub-optimal and do not achieve the quality of a hand-drawn layout or even the quality of automated layout solutions resulting from fill algorithms having long calculation times. Additionally, the electrical effect of fills on the integrated circuit can, at best, be only approximately anticipated and may lead to unexpected timing problems.
USPTO Backgrounds
USPTO Backgrounds