Embodiments of the present invention relate to a method for forming a semiconductor device, and more particularly to a method for forming a bit line in a semiconductor device including a buried gate.
Among semiconductor memory devices, a dynamic random access memory (DRAM) device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal applied through a word line. The data transfer occurs by using a semiconductor property where an electrical conductivity changes depending on environments. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region. The semiconductor property is used in the channel.
In a typical method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities into both sides of the gate. In this case, a channel region of the transistor is defined between the source and the drain under the gate. The transistor having a horizontal channel region occupies a predetermined area of a semiconductor substrate. With this conventional planar structure, it is difficult to reduce a unit cell area and enhance integrity.
If a unit cell area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer is increased, thereby improving the productivity. Several methods for reducing the total area of the semiconductor memory device have been proposed. One method is to replace a conventional planar gate having a horizontal channel region with a recess gate in which a recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. Furthermore, a buried gate has been studied which can reduce a parasitic capacitance of a bit line by burying the entire gate within the recess.
USPTO Backgrounds
USPTO Backgrounds