The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor.
When DMOS transistors are inserted into circuit configurations in which there are at least two supply voltages available, in case of a fault, for instance a short-circuit, it may happen that a short-circuit current runs backwards via the DMOS transistor. Especially in the case of large short-circuit currents, this can lead to the destruction of the DMOS transistor or to a voltage supply arranged in front of it.
A circuit configuration is known from DE 195 02 731 C2 in which a polarity-reversal protecting DMOS transistor is allocated to a DMOS transistor that is in series with a load circuit to be switched. In this case, the transistors are connected antiserially and monolithically integrated in a common substrate. Because both the switching transistor and the polarity reversal protection transistor are integrated in a common substrate having a certain charge carrier doping, both transistors have the same resistance to blocking. This resistance to blocking is selected so that the maximum voltage possible may be blocked. Besides the high area requirement, it is disadvantageous in this circuit configuration that the high resistance to blocking of the switching transistor leads to a correspondingly high forward resistance in the conducting case, which leads to a voltage drop that is undesirable per se.
By contrast, the circuit configuration according to the present invention, having the features recited in claim 1, offers the advantage that protection against polarity reversal of the DMOS transistor is achieved in a simple manner. A reverse blocking ability of the DMOS transistor is advantageously achieved, essentially without additional area requirement, by having a charge carrier zone situated in the drift zone of the DMOS transistor that is made up of individual charge carriers at a distance from one another and conductively connected to one another, the charge carrier having an opposite charge carrier doping compared to the drift zone, and being able to have a potential applied to it which is negative to a potential that may be connected at the drain terminal of the DMOS transistor. By application to the buried charge carrier, forming a JFET structure of a negative potential compared to the drain potential, the pn junction between the drain region and the charge carrier situated in the drain region is polarized for blocking, so that a so-called reverse current, such as in the case of a short-circuit, is pinched off. Thus the polarity reversal protection of the entire circuit configuration is ensured.
Further preferred embodiments of the present invention follow from the remaining features specified in the subclaims.
USPTO Backgrounds
USPTO Backgrounds