Impact ionization has been known for several years. U.S. Pat. No. 4,432,075 to B. Eitan and U.S. Pat. No. 4,821,236 to Hayashi et al. describe an EEPROM transistor adjacent to a charge generator, creating a substrate current near the EEPROM, creating excess charge or holes, resembling space charge, near subsurface electrodes of the EEPROM. Assume that the holes are generated and accelerated toward one of the electrodes of the EEPROM. Resulting secondary electrons are sufficiently energetic to penetrate gate oxide over the substrate and become injected into a conductive floating gate. For very small EEPROMs, the floating gate becomes charged by band-to-band tunneling, a situation which eliminates the need for a control gate over the floating gate.
U.S. Pat. Nos. 5,126,967 and 4,890,259 to R. Sinks describe a memory array made of non-volatile transistors that can store analog waveforms.
The ability of EEPROM transistors to directly record analog waveforms, without A-to-D conversion, gives rise to new applications, such as use in neural networks. This has been pointed out in U.S. Pat. No. 6,125,053 where C. Dioris and C. Mead describe use of EEPROMs storing variable amounts of charge generated by impact ionization to represent an analog value. This is in contrast to a conventional EEPROM where a floating gate either stores charge or does not store charge, thereby indicating a digital value. In the '053 patent, an EEPROM is described that permits simultaneous writing and reading.
An analogous problem is simultaneous programming and erasing operations in an array. An object of the invention was to devise a memory array that has simultaneous programming of one memory region and erasing of another memory region.
USPTO Backgrounds
USPTO Backgrounds