The present invention relates to semiconductor integrated circuits. More specifically, the present invention relates to memory latch cells for use in gate array type integrated circuits.
Semiconductor integrated circuit memories have a plurality of memory cells arranged in rows and columns. The area consumed by each memory cell limits the size of memory that can be fabricated on an integrated circuit. This area is determined by the number of transistors in the cell and the physical layout of the transistors on the integrated circuit. It is desirable to have each memory cell consume as little area as possible on the integrated circuit. It is also desirable to have the highest performance in terms of access speed. Read performance is typically limited by the output capacitance and output resistance of the output driver in each memory cell.
Improved memory cells are therefore desired, which consume a smaller area and have a lower output resistance and capacitance. This is particularly true with gate array type integrated circuits, which are known for consuming a larger area and being less optimizable than other semiconductor technologies, such as standard cell integrated circuits. Gate array architectures have a repeated layout pattern of transistors that allows for reduced design and fabrication time but typically results in a less dense and less optimized integrated circuit.
The present invention addresses these and other problems and offers other advantages over the prior art.
One embodiment of the present invention is directed to a gate array integrated circuit, which includes first and second voltage supply rails and a row of P-channel type transistors and adjacent N-channel type transistors located between first and second voltage supply rails. Adjacent ones of the P-channel and N-channel transistors have common control terminals. A multiple-bit memory cell is fabricated in the row and includes first and second latches, a read output, a first pass gate coupled between the first latch and the read output, and a second pass gate coupled between the second latch and the read output. The first pass gate includes a first one of the P-channel or N-channel transistors. The second pass gate includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.
Another embodiment of the present invention is directed to a multiple-bit memory cell layout definition for a semiconductor gate array. The layout definition includes a row of P-channel type transistors and adjacent N-channel type transistors. Adjacent ones of the P-channel and N-channel type transistors have common control terminals. First and second latches, a read output and first and second pass gates are defined within the row. The first pass gate is coupled between the first latch and the read output and includes a first one of the P-channel or N-channel transistors. The second pass gate is coupled between the second latch and the read output and includes a second one of the same type of the P-channel or N-channel transistors. The first and second same type transistors share a common diffusion region.
USPTO Backgrounds
USPTO Backgrounds