1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a semiconductor device and particularly, to LSI (Large Scale Integrated Circuit).
2. Description of the Related Art
Recently, the clock frequency of LSI has been acceleratingly increased, and now it is about to exceed 1 GHz. On the other hand, LSI testers for measuring LSIs have not been able to measure them any more when the LSIs operate at their normal clock frequencies. This is not only because the clock frequencies of LSIs exceed the measuring capability of the LSI testers, but also because reduction of the cost of the LSI test is required and thus LSI testers which are low in price and have low performance are often used.
In general, the measurement using an LSI tester is carried out by a screening test based on an operation check at a low frequency, and thus no AC speed screening test is not carried out. Here, the speed means the operable frequency of LSI. In the following description, The test of the operable frequency to screen LSI will be hereinafter referred to as xe2x80x9cspeed screeningxe2x80x9d. There occurs such a case that the speed of a gate element or the like of LSI is greatly varied due to a slight manufacturing error in a manufacturing process of LSI. Accordingly, the speed screening has been increasingly needed for LSI which aims to achieve high specification performance.
The speed screening is separately carried out. A first method for the speed screening is to carry out the test under the same environment as the condition under which LSI is actually used. Accordingly, according to this method, LSI is measured while it is mounted on a print board or in a device such as a computer device.
A second method for the speed screening is to estimate the performance of the whole LSI from the performance of a correlated circuit without actually measuring the speed itself. This method performs the measurement at the LSI tester level.
In general, the frequency measurement of a ring oscillator in which NAND circuits 31 to 3n (n=2 m+1 when m is a natural number) at odd-number stages are linked to one another in the form of a ring as shown in FIG. 1 is utilized for the estimation. Signal EN is input to input terminal of NAND circuit 31. Signal FB is negatively fed back from the output of NAND circuits 3n to the input of NAND circuits 31. The speed of a gate element per stage can be measured by measuring the oscillation frequency of the ring oscillator, and the operating frequency of LSI is estimated from this value.
In the first method of the conventional LSI speed screening method described above, a cost is needed to fabricate LSI into a package because LSI must be actually mounted, and thus the fabrication cost needed for LSI which is detected as a defective by the speed screening is wasted.
Further, another cost is needed to prepare the estimation environment for the device and the print board, and also a using cost of a measuring device and labor costs are needed. These costs finally reflect and increase the prices of LSI and the device such as the computer device.
On the other hand, the disadvantage of the second method resides in that the frequency of the ring oscillator and the LSI performance cannot be fully correlated with each other. The LSI performance is substantially determined by the delay between specific circuits which are called as a critical path. When gate elements (such as inverter and NAND circuit) constituting the critical path is positionally dispersed in LSI, the gate elements are connected to one another through wires.
On the other hand, the ring oscillator is usually constructed under the state that there is substantially no wire because it suffers size restriction or the like. Therefore, in a micro-processing manufacturing process popularly called as 0.18 xcexcm/0.15 xcexcm rule, the wire delay is increased to a larger value which is not negligible as compared with the gate element delay.
Accordingly, it is estimated that the precision of the correlation between the gate element delay calculated from the frequency measurement of the ring oscillator and the delay of the critical path is not high. Further, it is difficult to design the ring oscillator so that the precision is high.
Therefore, an object of the present invention is to provide a semiconductor integrated circuit and a semiconductor device in which LSI performance can be examined at the LSI tester level.
A semiconductor integrated circuit according to the present invention contains a critical path representing a signal path and has a ring oscillator which is constructed so as to negatively feed back the output of the critical path to the input of the critical path.
A semiconductor device according to the present invention comprises first and second semiconductor integrated circuits; and first and second transmission paths connecting to each other between the first semiconductor and the second semiconductor, wherein at least one circuit element of the first semiconductor integrated circuit, the first transmission path and at least one circuit element of the second semiconductor integrated circuit construct a first critical path, at least one circuit element of the first semiconductor integrated circuit, the second transmission path and at least one circuit element of the second semiconductor integrated circuit construct a second critical path, and the first and second critical path is connected to construct a ring oscillator.
That is, the semiconductor integrated circuit of the present invention is characterized in that the ring oscillator is constructed by using the critical path. It is easy to measure the oscillation frequency of the critical path-ring oscillator from the outside as in the case of the measurement of a normal ring oscillator, and it is easy to calculate the speed of the circuit concerned on the basis of the frequency measurement.
In addition, the circuit concerned is a critical path for determining the whole performance of LSI, and the performance thereof can be measured at high precision, whereby the performance of LSI can be examined at the LSI tester level. When the distance between a first flip-flop circuit and a second flip-flop circuit is long, a relay buffer is inserted into between the output of the second flip-flop circuit and the input of the first flip-flop circuit at the minimum and requisite number. However, the performance delay caused by the insertion of the circuit concerned to the critical path is required to be set to such a range that it is remarkably small and negligible.
A high-performance/high price LSI test is not required for the measurement, and it would be sufficient if only a frequency counter is provided. The wafer test can be measured at the LSI tester level, so that a speed defective is prevented from being packaged and a screening test on a device is not required. Further, the cost can be reduced. Accordingly, there can be provided means for performing the LSI speed screening at the LSI tester level.
USPTO Backgrounds
USPTO Backgrounds