FIG. 1 is an illustration of a conventional imaging system 100. The system 100 includes an N×M array 110 of pixels P. The system 100 may be monochromatic or color. If the system 100 is a color system, the pixels P in the array 110 would be sensitive to the primary colors of red, green, or blue, and would typically be arranged in a Bayer pattern (i.e., alternating rows are comprised of green/red and blue/green sensitive pixels in adjacent columns).
Each pixel P in the array 110 converts incident light into electrical energy, which is output as an electrical signal. The signals from the N pixels forming a row in the array 110 are typically simultaneously output on respective column lines to respective sample-and-hold circuits 120, which store the electrical signals. These signals are then selected, one pixel at a time, for further processing by a driver 130, and then converted into a digital signal by an analog-to-digital (A/D) converter 140. The digital signals are further processed by a digital processing section 150, and then stored by a storage device 160. When all the signals stored in the sample-and-hold circuits 120 have been processed, another row of signals is output and stored in the sample-and-hold circuit 120 and the processing continues until each row of the N×M array 110 has been processed. The above described processing may be controlled by a control circuit 170. Alternatively, control circuit 170 may include a plurality of control circuits.
An ideal pixel would output an analog pixel signal with no noise component in a manner consistent with the amount of incident light upon the pixel. In order to achieve a high fidelity image, a conventional high resolution (e.g., 12 to 14 bits) A/D converter is typically used to convert the pixel signal into a digital signal. However, one drawback associated with conventional high resolution A/D converters is that they require a relatively long time to perform each A/D conversion. For example, converter 140 might be based on a “ramp” design, which requires many processing steps in the A/D conversion.
Now referring to FIGS. 2A and 2B, it can be seen that a ramp type A/D converter 200 operates by sampling and holding the input signal (Vs) over a sampling period (ts) comprised of a plurality of clock cycles (1 tc, 2 tc, . . . , 8 tc). The A/D converter 200 is initialized when the start pulse control 201 generates the logical high portion of a start pulse. This resets the value stored in counter 204, resets the state of the ramp generator 205, and causes the AND gate 203 to output a low logical state. Thereafter, during each clock cycle (1 tc-8 tc), the value of the counter 204 is incremented by one, and the state of the ramp generator 205 is changed to cause the ramp generator 205 to generate a new reference signal Vr. A comparator 206 compares the reference signal Vr against the input signal Vs. If the magnitude of the reference signal Vr does not exceed that of the input signal Vs, the comparator 206 outputs a logical high state to the AND gate 203, which when combined with a clock pulse generated by clock 202 and the low logical state portion of the start signal, toggles the clock inputs of counter 204 and ramp generator 205.
Each time counter 204 is toggled, it increases its value by one. Thus, on each successive cycle, the ramp generator 205 generates a higher magnitude reference voltage Vr until the magnitude of the reference voltage Vr exceeds the magnitude of the sample signal. Thereafter, the comparator outputs a low logical state to AND gate 203, causing the AND gate 203 to continually output a low logical state, thereby freezing the counter value. When enough clock cycles have elapsed to constitute an entire sample period, the counter value is equal to the digitally converted value. Once the counter value has been read out, the start pulse control can generate a new start pulse to cause the A/D converter 200 to being the conversion process again.
It should be apparent from the discussion above with respect to FIGS. 2A-2B that an I-bit ramp type A/D converter requires a minimum sampling time equal to 2I clock cycles in order to permit sufficient time to compare the maximum ramp value with the input signal. Thus, the throughput of an imaging system 100 (FIG. 1) is at least partially limited by the speed of the A/D converter 140, especially when high resolution (e.g., I=12 or more) A/D conversion is employed. Accordingly, there is a need for a method and mechanism for performing high resolution A/D conversion at a faster rate.
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USPTO Backgrounds