Enclosed cavities may be found in a number of devices formed by semiconductor processing. For example, devices such as micro-fluidic devices, nano-fluidic devices, or other types of devices are formed with enclosed cavities, such as capillaries and chambers. Also, micro-electromechanical systems (MEMS) devices may by formed with enclosed cavities with or without internal device structures such as cantilever beams and/or bridges.
Conventional semiconductor processing forms enclosed cavities by complex methods. For example, a substrate may be etched to form trenches and a cap wafer may be bonded to the substrate to enclose the trenches as enclosed cavities. For example, the substrate and cap wafer may be bonded through direct bonding or through eutectic bonding in which an adhesion layer and a eutectic material are used between the substrate and cap wafer to assist in bonding. Such bonding methods typically require an anneal process. Further, such bonding methods require the substrate and cap wafer to have smooth, flat surfaces for bonding. Also, such methods may require grinding of the cap wafer to a desired thickness. Such methods are not used to form enclosed cavities over complementary metal-oxide-semiconductor (CMOS) devices. Other methods also include complex processing to form enclosed cavities.
Accordingly, it is desirable to provide simpler and more efficient CMOS compatible integration schemes and enabling methodology. Also, it is desirable to provide improved methods for fabricating semiconductor devices with enclosed cavities, with or without internal structures. It is desirable to provide methods for etching enclosed cavities through a permeable layer. Further, it is desirable to provide methods for fabricating semiconductor devices in which cavity-encapsulating layers are formed together before the enclosed cavity is formed therebetween. It is also desirable to provide methods for fabricating semiconductor devices in which enclosed cavities are formed in a substrate without a planar top surface. Also, it is desirable to provide improved semiconductor devices with enclosed cavities. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
USPTO Backgrounds
USPTO Backgrounds