This invention relates to computer memory construction, and more particularly to memory cards arranged to be mounted back-to-back on a backplane board.
Computer systems are designed to meet an ever-increasing demand to operate memory and processor busses at higher and higher frequencies. One feature which is used to meet these requirements is the use of an active backplane, i.e., circuitry which functions as both memory control and as a bridge between the CPU bus and the I/O bus is mounted directly on the backplane or motherboard. This circuitry buffers and routes data between various devices on the processor and I/O busses as well as maintains the coherency of cacheable data. Because this memory controller and bridge circuitry communicates with processor, memory and I/O subsystems, it resides on the backplane, centered between the main busses (processor bus, memory bus, I/O bus) to minimize the lengths of interconnect wires. The CPU is mounted on a daughter card, and the memory devices (SIMMs or DIMMs) are also mounted on daughter cards. These daughter cards are mounted at right angles to the backplane or motherboard, in connector slots.
To accommodate additional memory, a backplane is usually designed to support multiple memory cards. For example, there may be two slots for mounting two memory cards, in a typical construction, and these two memory cards are mounted in a front-to-back arrangement, i.e., both facing the same way. When laying out the backplane with this type of memory card, sufficient separation must be maintained between edge connectors for the cards to accommodate clearance required for the SIMMs or DIMMs which extend at right angles from the memory cards. This separation distance between memory cards adds to the overall length of the path for each memory data, address and control signal between the memory controller and the memory cards. The increased path length contributes to the RC wire delay, which increases the memory bus cycle time, degrading overall memory bandwidth and system performance. In one example of a typical contemporary construction, using connectors made by AMP called High Speed Card Edge Connectors (HSCE), with 200-pin SDRAMs Memory DIMMs (JEDEC standard number 21-C of JC42.5), and nominal memory card thickness of 0.070 inch, allowing 0.170 inch for card sway, yields a card separation of 1.50 inches. With typical propagation delays of printed circuit card wires at 180 picoseconds per inch, the 1.50 inches of card wire contributes at least 270 picoseconds of delay to each memory net.
USPTO Backgrounds
USPTO Backgrounds