1. Field of the Invention
The present invention relates to an optical input/output (I/O) bus system, and more particularly, to an optical I/O bus system that is implemented using an optical printed circuit board (PCB) and optical connection technology in a computer system, etc. and thus can transfer a high-capacity signal without a bottleneck and signal distortion occurring in a conventional I/O bus system.
2. Discussion of Related Art
In general, a computer bus system refers to an information transmission channel that is used in common by a central processing unit (CPU) and external devices including a memory and I/O device to transfer information between them in a computer.
Information transferred via such a bus system may be an address of each device or an address in a memory at which information exists, that is, information of an address, information of data, or so on. Each piece of information is transferred and received over an appropriate bus.
Also, buses may be classified into an internal bus that is used to connect several arithmetic units in a CPU with various registers or a plurality of arithmetic units with each other, and an external bus that connects a plurality of CPUs with each other, a CPU with an external device including a memory, or external devices with each other. The present invention relates to the external bus, and more particularly, to a connection method and structure in the physical layer of the external bus.
Due to an increase in the speed of microprocessor units (MPUs) and memory chips, a rapid increase in the amount of information to be processed by peripheral devices, and an increase in the number of required peripheral devices, the amount of information to be transferred over a bus rapidly increases. However, the bandwidths of I/O buses are not so improved that a bottleneck frequently occurs in the I/O buses. Also, since a plurality of external devices are connected in parallel, a severe signal distortion occurs.
I/O buses are intended to connect external devices with the CPU of a computer, and classified into a first generation bus, a second generation bus, and a third generation bus according to a data throughput, standard, and time. The first generation bus includes an Industry Standard Architecture (ISA) bus, Extended ISA (EISA) bus, MicroChannel Architecture (MCA) bus, etc., and the second generation bus includes a Video Electronics Standards Association (VESA) bus, Peripheral Component Interconnect (PCI) bus, Accelerated Graphics Port (AGP) bus, etc. A PCI extended (PCI-X) bus and 64-bit PCI bus modified from the PCI bus were developed, but could not support a sufficient bandwidth to resolve a bottleneck. For this reason, the third generation bus such as PCI-express and Hyper-transfer has been developed. However, as long as a bandwidth required in a computer continuously increases, a next-generation bus is necessary.
In such a conventional I/O bus system, asymmetric computer information transmission occurs due to the different speeds of respective devices and a characteristic of a transmission structure. The asymmetric information transmission leads to a bottleneck, and a bottleneck at a specific part decreases the speed of a whole system.
Also, when a conventional I/O bus system transfers an electrical signal at a rate of about 5 Gbps or more, mutual interference occurs due to an electromagnetic (EM) field generated by rapid movement of electrons and results in a signal loss.
Furthermore, since a plurality of different external devices are simultaneously connected to a conventional computer I/O bus system, an impedance mismatch occurs. Thus, signals are severely distorted, and the number of connectable external devices is limited.
USPTO Backgrounds
USPTO Backgrounds