In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
One type of semiconductor device that can be fabricated is a Fin Field Effect Transistor (FinFET). In a FinFET, a fin-shaped semiconductor structure is formed on a substrate. A gate device that wraps around the fin structure can then be formed. Additionally, active regions such as source/drain regions are then formed within the fin structure adjacent the gate structure. The gate device and adjacent source/drain regions thus form a transistor with the channel extending through the fin structure underneath the gate. It is desirable that the fin structure has characteristics that provide it with sufficient mechanical strength as well as good carrier mobility.
USPTO Backgrounds
USPTO Backgrounds