The present invention relates generally to the synthesis of high-frequency signals. More particularly, the present invention relates to the synthesis of high-frequency local oscillator signals for wireless communication applications.
Wireless communication systems typically require frequency synthesis in both the receive path circuitry and the transmit path circuitry. For example, cellular phone standards in the United States and Europe define a cellular telephone system with communication centered in two frequency bands at about 900 MHz and 1800 MHz. For example, United States cellular phone standards include (1) the AMPS (analog), IS-54 (analog/digital), and IS-95 (analog/digital) standards in the 900 MHz frequency band, and (2) PCS (digital) standards in the 1800 MHz range. European cellular phone standards include (1) the TACS (analog) and GSM (digital) standards in the 900 MHz frequency band, and (2) the DCS1800 (digital) standard in the 1800 MHz range. A dual band cellular phone is capable of operating in both the 900 MHz frequency band and the 1800 MHz frequency band.
Within the frequency bands, the cellular standards define systems in which base station units and mobile units communicate through multiple channels, such as 30 kHz (IS-54) or 200 kHz (GSM) wide channels. For example, with the IS-54 standard, approximately 800 channels are used for transmitting information from the base station to the mobile unit, and another approximately 800 channels are used for transmitting information from the mobile unit to the base station. A frequency band of 869 MHz-894 MHz and a frequency band of 824 MHz-849 MHz are reserved for these channels, respectively. Because the mobile unit must be capable of transmitting and receiving on any of the channels for the standard within which it is operating, a frequency synthesizer must be provided to create accurate frequency signals in increments of the particular channel widths, such as for example 30 kHz increments in the 800-900 MHz region.
Phase-locked loop (PLL) circuits including voltage controlled oscillators (VCOs) are often used in mobile unit applications to produce the desired output frequency (fOUT). The output frequency may be made programmable by utilizing an output frequency feedback divider (÷N) and a reference divider (÷R) for an input reference frequency (fREF) The output frequency produced is a function of the values selected for xe2x80x9cNxe2x80x9d and xe2x80x9cRxe2x80x9d in the divider circuits, such that fOUT=N(fREF/R). The PLL circuitry typically utilizes a phase detector to monitor phase differences (xcex94xcex8) between the divided reference frequency (fREF/R) and the divided output frequency (fOUT/N) to drive a charge pump. The charge pump delivers packets of charge proportional to the phase difference (xcex94xcex8) to a loop filter. The loop filter outputs a voltage that is connected to the VCO to control its output frequency. The action of this feedback loop attempts to drive the phase difference (xcex94xcex8) to zero (or at least to a constant value) to provide a stable and programmable output frequency.
The values for the reference frequency and the divider circuits may be chosen depending upon the standard under which the mobile unit is operating. For example, within the United States IS-54 system, a PLL could be built such that fREF/R=30 kHz and such that N is on the order of 30,000. The output frequency, therefore, could then be set in 30 kHz increments to frequencies in the 900 MHz frequency band. Similarly, within the European GSM system, a PLL could be built such that fREF/R=200 kHz and such that N is on the order of 4,500. The output frequency, therefore, could then be set in 200 kHz increments to frequencies in the 900 MHz frequency band.
The performance of the communication system, however, is critically dependent on the purity of the synthesized high-frequency output signals. For signal reception, impure frequency sources result in mixing of undesired channels into the desired channel signal. For signal transmission, impure frequency sources create interference in neighboring channels. A frequency synthesizer, therefore, must typically meet very stringent requirements for spectral purity. The level of spectral purity required in cellular telephone applications makes the design of a PLL synthesizer solution and, in particular, the design of a VCO within a PLL synthesizer solution quite demanding.
Three types of spectral impurity will typically occur in VCO circuits that are used in PLL implementations for frequency synthesis: harmonic distortion terms associated with output frequency, spurious tones near the output frequency, and phase noise centered on the output frequency. Generally, harmonic distortion terms are not too troublesome because they occur far from the desired fundamental and their effects may be eliminated in cellular phone circuitry external to the frequency synthesizer. Spurious tones, however, often fall close to the fundamental. In particular, spurious tones at frequencies of xc2x1fREF/R from the output frequency (fOUT) are often found in the output frequency spectrum. These are called reference tones. Spurious tones, including reference tones, may be required by a cellular phone application to be less than about xe2x88x9270 dBc, while harmonic distortion terms may only be required to be less than about xe2x88x9220 dBc. It is noted that the xe2x80x9ccxe2x80x9d indicates the quantity as measured relative to the power of the xe2x80x9ccarrierxe2x80x9d frequency, which is the output frequency.
Phase noise is undesired energy spread continuously in the vicinity of the output frequency, invariably possessing a higher power density at frequencies closer to the fundamental of the output frequency. Phase noise is often expressed as dBc/Hz or dBc/Hz. Phase noise is often the most damaging of the three to the spectral purity of the output frequency. Because of the effect phase noise has on system performance, a typical cellular application might require the frequency synthesizer to produce an output frequency having phase noise of less than about xe2x88x92110 dBc/Hz at 100 kHz from the output frequency.
Because the phase noise specifications are so stringent in cellular phone applications, the VCOs used in cellular phone PLL synthesizer solutions are typically based on some resonant structure. Ceramic resonators and LC tank circuits are common examples. While details in the implementation of LC tank oscillators differ, the general resonant structure includes an inductor (L) connected in parallel with a fixed capacitor (C) and a variable capacitor (CX). In the absence of any losses, energy would slosh between the capacitors and the inductor at a frequency fOUT=(xc2xdxcfx80)[L(C+CX)]xe2x88x92xc2xd. Because energy will be dissipated in any real oscillator, power in the form of a negative conductance source, such as an amplifier, is applied to maintain the oscillation. It is often the case that the series resistance of the inductor is the dominant loss mechanism in an LC tank oscillator, although other losses typically exist.
While it is highly desirable to integrate the VCO with the other components of the PLL onto a single integrated circuit for cost, size, power dissipation, and performance considerations, barriers to integration exist. One of the more significant barriers is the lack of precision in the values of the inductors and capacitors used in the LC tank of the PLL. This tolerance problem typically forces most PLL synthesizer implementations to modify the inductor or capacitor values during production, for example, by laser trimming. Further complicating integration is the difficulty in integrating an inductor with a low series resistance and a capacitor with a reasonably high value and with low loss and low parasitic characteristics. In integrating capacitance values, a significant problem is the high value of a typical loop filter (LF) capacitor component, which is often on the order of 1-10 xcexcF. Another significant problem is the absence of a variable capacitance (CX) component that possesses a highly-variable voltage-controlled capacitance that is not also a high loss component that causes phase noise. To provide this variable capacitance (CX) component, a high-precision reverse-biased diode or varactor is typically utilized. However, such high-performance varactors require special processing and, therefore, have not been subject to integration with the rest of the PLL circuitry. In short, although integration onto a single integrated circuit of a PLL implementation for synthesizing high-frequency signals is desirable for a commercial cellular phone application, integration has yet to be satisfactorily achieved.
In accordance with the present invention, a method and apparatus for synthesizing high-frequency signals is disclosed that overcomes the integration problem associated with prior implementations and meets the demanding phase noise and other impurity requirements. The present invention achieves this advantageous result by implementing a phase-locked loop (PL frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired output frequency. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired output frequency and to provide compensation for post-calibration drift of the PLL circuitry. The present invention avoids the need for a traditional varactor implementation in the VCO, for a traditional large capacitor component in the loop filter, and for component trimming during processing and thereby provides a high-frequency frequency synthesizer that may be fully integrated on a single chip except for an external inductor.
In one embodiment, a wireless communication frequency synthesizer having a phase locked loop is provided. The synthesizer may comprise a controllable oscillator, a first clock node coupled to an output of the controllable oscillator, and a second clock node coupled to a reference clock. The synthesizer also comprises a plurality of phase shifted signals, the phase shifted signals being generated from, at least in part, a first clock signal on the first clock node, and a plurality of variable control signals, the variable control signals being generated from a detected phase difference between at least some of the plurality of phase shifted signals and a second clock signal on the second clock node, the control signals coupled to inputs of the controllable oscillator.
In another embodiment, a method of operating a wireless communication frequency synthesizer having a phase locked loop is provided. The method may include generating a plurality of phase shifted signals utilizing a first clock signal, the first clock signal being generated from an output clock signal of phase locked loop, detecting a phase difference between at least some of the plurality of phase shifted signals and a second clock signal, the second clock signal being generated from a reference clock signal of phase locked loop. The method also includes generating a plurality of control signals from the detected phase differences, and controlling the output frequency of a controllable oscillator of the phase locked loop with the control signals.
In yet another embodiment, a wireless communication frequency synthesizer having a phase locked loop is provided. The synthesizer may include a controllable oscillator, a first clock node coupled to an output of the controllable oscillator, and a second clock node coupled to a reference clock. The synthesizer further includes a plurality of analog control signals, the analog values of the analog control signals being related to a phase difference between a first clock signal on the first clock node and a second clock signal on the second clock node, and a plurality of controllable oscillator inputs coupled to the plurality of analog control signals, data on the controllable oscillator inputs controlling the output frequency of the controllable oscillator.
In still another embodiment, a method of operating a wireless communication frequency synthesizer having a phase locked loop is provided. The method includes detecting a phase difference between at least two signals within the phase locked loop, and generating a plurality of analog control voltages from a result of the phase difference detection. The method also includes providing the plurality of analog control voltages to inputs of a controllable oscillator, and controlling the output frequency of the oscillator with the plurality of analog control voltages.
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