1. Field of Use
This invention pertains to data processing systems in which a system bus network is shared by a plurality of units and more particularly to a method and apparatus for limiting the use of such system bus network.
2. Prior Art
In many data processing systems, a bus network is frequently used to interconnect the different elements together. In certain types of these systems, the access of one or more master controllers to the bus network is controlled through a single bus arbitration module which grants access to the master controllers on a priority basis. The bus master granted access performs the specified request which, in certain instances, involves the performance of burst type transfers. Depending upon the types of requests being performed by the plurality of master controllers, the system's central processing unit, normally granted low priority, has been effectively precluded from using the bus network.
To prevent this, the system disclosed in U.S. Pat. No. 4,719,567 includes apparatus within the bus master controller which limits its activity during a particular time interval based upon the bus activity during a preceding time interval. However, the arrangement requires a centralized arrangement which operates in a synchronous manner. Also, the arrangement determines the activity of the bus by dividing the activity of the bus master controller into a succession of sample intervals comprising a selected number of clock cycles of the bus master controller. During each such sample interval, the bus master controller determines the utilization rate of the bus network as the ratio of the number of clock cycles during which the grant acknowledge signal of such controller is active to the number of clock cycles comprising the sample interval. If the utilization rate of the bus network during a particular sample interval is determined to be above a selected threshold, the bus master controller is prevented from arbitrating for the use of the bus network during the next successive sample interval. If the utilization rate is determined to be below the predetermined threshold, the bus master controller will be allowed to contend for the right to use the bus network. This form of measurement involving measuring ratios of intervals has been found somewhat ineffective in that it reduces system performance.
Also, the system of U.S. Pat. No. 4,558,428 is of interest in that it discloses how a high priority unit, such as a memory controller, during the execution of a burst type transfer operation which could saturate an asynchronous bus network, is able to skip a cycle of the burst type transfer operation, enabling a lower priority unit access to the memory controller's memory. While this arrangement improves overall system performance by enabling a lower priority unit access to memory, during a burst type transfer, it does not prevent the bus network from being saturated by other units competing for bus network access.
Accordingly, it is a primary object of the present invention to provide a method and apparatus for limiting the utilization of an asynchronous bus system by a user bus unit.
It is a more specific object of the present invention to provide a method and apparatus for limiting access to an asynchronous bus network by any one of a plurality of units connected to the network which are granted access by priority logic network distributed among such units.
USPTO Backgrounds
USPTO Backgrounds