The present disclosure relates to semiconductor device fabrication, and more specifically, to a semiconductor device having an airgap spacer for a transistor. The airgap spacer extends the entire thickness of the gate.
Reduction in off capacitance is a challenge in designing semiconductor devices. A high capacitance is attributable to the relative size of the first metal to first contact to gate body region in a field effect transistor (FET). A high first metal level and zero via level capacitance limits certain FETs off capacitance (Coff) such as n-type FETs. Consequently, reduction in the capacitance of the material in this region helps reduce the overall Coff for the FET. One conventional approach to address this situation includes using airgap spacers at the gate level, i.e., adjacent part of the gate body. While this approach helps reduce capacitance, current approaches form the zero via level after forming airgap spacers. When the zero via level is formed over the airgap spacers and the gates, it reduces the efficacy of the airgap spacers. For example, when the airgap spacers are capped off with an interlayer dielectric (ILD) for the zero via level, the ILD fills part of the airgap spacer, reducing its efficacy to reduce capacitance of the material. Current techniques to address this latter challenge create complex shaped airgap spacers and/or require various additional and oftentimes complex processing steps. Where airgap spacer formation has been attempted after zero via level formation, it has resulted in very large airgaps that create structural integrity issues.
USPTO Backgrounds
USPTO Backgrounds