1. Field of the Invention
The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of fabricating a self-aligned contact (SAC) window.
2. Description of the Related Art
During the fabrication of a self-aligned contact window, the contact window can be defined without limitations imposed by photolithography, so that the distance between the gates is reduced and the device integration is raised. Therefore, self-aligned contact process is widely used in ULSI.
FIG. 1 is a schematic, cross-sectional view of a self-aligned contact window. Referring to FIG. 1, a silicon nitride layer with a thickness of about 1500 angstroms serving as a cap layer 100 is formed on the gate structure 102. A spacer 104 is formed on the sidewall of the gate structure 102 and is made of silicon nitride. A liner oxide layer 106 is formed between the nitride spacer 104, the nitride cap layer 100 and the gate structure 102 and the substrate 112 to insulate therebetween. The main principle of the self-aligned contact process is to use two kinds material having different etching rates, such as silicon oxide and silicon nitride, with an etching selectivity of about 10. Accordingly, when the oxide layer serving as a dielectric layer 110 is etched, the self-aligned contact window 108 is formed due to the nitride spacer 104 and the cap layer 100. which serve as etching stops.
The substrate 112 should be completely exposed to allow the substrate 112 to be electrically connected with the conductive layer 114, therefore the dielectric layer 110 is often over etched in the etching process for SAC. This easily causes the nitride cap layer 100 and spacer 104 to be partially etched. In addition, the liner oxide layer 106 is formed by chemical vapor deposition and results in an incompact structure thereof. The cap layer 100, the spacer 104 and the liner oxide layer 106 are easily attacked by the etchant, which leads to unsuitable contact of the gate structure 102 and the conductive layer 114 deposited in the SAC window 108. As a result, a short occurs therebetween and the performance of the device is decreased.
Moreover, although the attack can be ameliorated by an increased thickness of nitride cap layer 100, the whole height of the gate structure 102 then increases and therefore the etching process for SAC window 108 cannot be smoothly performed.
USPTO Backgrounds
USPTO Backgrounds