1. Field of the Invention
The invention relates generally to methods and apparatus for organizing cache units and more particularly relates to methods and apparatus for organizing an integrated cache unit which may be used to implement a variety of multi-processor support schemes in a flexible manner. The resulting cache unit is programmable, can be operated in both single and multiprocessor modes, and achieves cache data consistency in multiprocessor mode by allowing a plurality of user selectable multiprocessor support schemes to be implemented and tailored to cache system application. The novel system supports high speed instruction and data processing in a Reduced Instruction Set Computer (RISC) environment and is capable of supporting all of the aforesaid functions with an architecture suitable for integration on a single chip.
2. Description of the Related Art
Cache memories and controllers for cache memories are well known. Devices integrating both the memory and control features on a single chip are also known. These include the commercially available: 43608 manufactured by NEC. Such devices are hereinafter referred to as "Integrated Cache Units (ICUs).
Prior art ICU devices utilize predetermined algorithms for caching data and instructions i.e., the devices are not programmable. Heretofore, integrating cache memory, a cache controller and programmability features on a single chip has not been achieved due in part to circuit density and data path requirement. In addition to not being programmable, no known ICU architecture has overcome the circuit density and data path requirement problems associated with supporting high speed RISC systems having multiprocessor capabilities.
A programmable integrated cache unit would be desirable since it would have the inherent flexibility to permit the selection and/or modification of caching algorithms. Additionally, a programmable ICU which incorporates a plurality of user selectable multiprocessor support schemes would allow cache data consistency to be assured in a flexible manner.
A single chip ICU architecture with the aforementioned features would also be desirable to minimize space and unit power requirements. Still further, it would be desirable to be able to use such an integrated cache unit to support high speed processing operations in both single and multiprocessor modes, for both RISC and non-RISC environments.
USPTO Backgrounds
USPTO Backgrounds