1. Field of the Invention
The present invention relates to a liquid crystal driving circuit for driving a liquid crystal display system by the multi-line selection (MLS) method, and a liquid crystal display system driven by the liquid crystal driving circuit.
2. Related Background Art
In recent years, liquid crystal display systems are widely noticed as light flat panel displays of low electric power consumption. As one of methods for driving such liquid crystal display systems, the MLS method for simultaneously selecting a plurality of scanning lines, i.e., a plurality of common electrodes connected to the scanning lines, is known. Referring to FIGS. 9 through 16, a conventional liquid crystal display system driven by the MLS method will be described.
FIG. 9 is a block diagram showing a typical construction of a liquid crystal display system driven by the MLS method. As shown in FIG. 9, the liquid crystal display system driven by the MLS method comprises a liquid crystal display part 2, a common electrode driving circuit 10, a segment electrode driving circuit 30, a function generating part 50, and a random access memory (RAM) 70 for display data.
The liquid crystal display part 2 comprises: a first transparent substrate, on which a plurality of common electrodes are arranged in parallel to each other; a second transparent substrate, on which a plurality of segment electrodes are arranged in parallel to each other, the second transparent substrate facing the first transparent substrate so that the segment electrodes intersect the common electrodes; and a liquid crystal layer sandwiched between the first and second transparent substrates. Each of the common electrodes is connected to a corresponding one of different scanning lines COMi (i=1, . . . , m), and each of the segment electrodes is connected to a corresponding one of different signal lines SEGj (j=1, . . . , n).
The common electrode driving circuit 10 is designed to simultaneously select a plurality of scanning lines to drive the common electrodes connected to the selected scanning lines.
FIG. 10 shows the details of the common electrode driving circuit 10 and the function generating part 50. The common electrode driving circuit 10 is designed to simultaneously select four scanning lines. The common electrode driving circuit 10 comprises: a shift register 11; a plurality of logic parts 13, each of which is provided for each scanning line COMi (i=1, . . . , m); and a plurality of sets of three analog switches 15, 16 and 17, each set of which is provided for each scanning line COMi (i=1, . . . , m). The function generating part 50 has a 2-bit binary counter 51 and a function generator circuit 55.
The 2-bit binary counter 51 is designed to operate in response to a field start signal and count the pulse number of the field start signal in synchronism with a shift clock to transmit counted values FS1 and FS0 to the function generator circuit 55. The FS0 and FS1 are indicative of the low-order bits and high-order bits of the counted values, respectively, and also called field select signals.
The function generator circuit 55 is designed to generate 4-bit values FD0, FD1, FD2 and FD3, which correspond to an alternating signal ALT and the output signals FS1 and FS0 of the 2-bit binary counter 51, on the basis of these signals. For example, as shown in FIG. 11, when ALT=xe2x80x9c0xe2x80x9d, FS1=xe2x80x9c0xe2x80x9d and FS0=xe2x80x9c0xe2x80x9d, then FD0=FD1=FD2=FD3=xe2x80x9c1xe2x80x9d, i.e., values shown in a column 61 are generated, and when ALT=xe2x80x9c0xe2x80x9d, FS1=xe2x80x9c0xe2x80x9d and FS0=xe2x80x9c1xe2x80x9d, then FD0=FD2=xe2x80x9c1xe2x80x9d and FD1=FD3=xe2x80x9c0xe2x80x9d, i.e., values shown in a column 62 are generated.
Furthermore, the functions FD0, FD1, FD2 and FD3 shown in FIG. 11 are called Hadamard functions. The column 61 is used for selecting a first field which forms one frame, and the column 62 is used for selecting a second field. In addition, a column 63 is used for selecting a third field, and a column 64 is used for selecting a fourth field. Moreover, columns 7i (i=1, . . . , 4) are formed by inverting the respective values of the column 6i. The column 71 is used for selecting the first field, and the column 72 is used for selecting the second field. The column 73 is used for selecting the third field, and the column 74 is used for selecting the fourth field. The use of these columns 71 through 74 prevents charges from being stored in the liquid crystal layer.
On the other hand, the shift register 11 of the common electrode driving circuit 10 is designed to sequentially select the first through fourth fields on the basis of a field start signal, and simultaneously select four successive scanning lines on the basis of a shift clock signal in each of the selected fields to sequentially carry out the simultaneous selection. For example, as shown in FIG. 12, when the shift register 11 receives a first field start signal, a first field is selected. Thereafter, when the shift register 11 receives a shift clock, the shift register 11 outputs a signal OA for simultaneously selecting scanning lines COM1 through COM4. Then, on the basis of the next shift clock, the shift register 11 outputs a signal OB for simultaneously selecting scanning lines COM 5 through COM8. Thus, the operations for simultaneously selecting four successive scanning lines within a selection period for the first field are sequentially carried out.
Each of the logic parts 13 comprises two inverter gates and two AND gates. The logic part 13 corresponding to the scanning line COM1 is designed to select one analog switch, which is connected to the scanning line COM1 and which is one of the three analog switches 15, 16 and 17, on the basis of the output signal OA of the shift register 11 and the output FD0 of the function generator circuit 55. The logic part 13 corresponding to the scanning line COM2 is designed to select one analog switch, which is connected to the scanning line COM2 and which is one of the three analog switches 15, 16 and 17, on the basis of the output signal OA of the shift register 11 and the output FD1 of the function generator circuit 55.
The logic part 13 corresponding to the scanning line COM3 is designed to select one analog switch, which is connected to the scanning line COM3 and which is one of the three analog switches 15, 16 and 17, on the basis of the output signal OA of the shift register 11 and the output FD2 of the function generator circuit 55. The logic part 13 corresponding to the scanning line COM4 is designed to select one analog switch, which is connected to the scanning line COM4 and which is one of the three analog switches 15, 16 and 17, on the basis of the output signal OA of the shift register 11 and the output FD3 of the function generator circuit 55.
Similarly, each of the logic parts 13 corresponding to the scanning lines COM5 through COM8 is designed to select one analog switch, which is connected to the corresponding scanning line and which is one of the three analog switches 15, 16 and 17, on the basis of the output signal OB of the shift register 11 and the output of the function generator circuit 55.
Each of the analog switches 15, 16 and 17 is designed to supply a voltage Vr (xe2x89xa00), 0 or xe2x88x92Vr to the corresponding scanning lines when it is selected by the corresponding logic part 13.
Therefore, as shown in FIG. 12, when the first field is selected, if the signal OA is outputted from the shift register 11 (OA=xe2x80x9c1xe2x80x9d), the voltage Vr is supplied to the scanning lines COM1, COM2, COM3 and COM4, so that the voltage Vr is applied to the common electrodes connected to the scanning lines COM1, COM2, COM3 and COM4. Furthermore, when the signal OA is not outputted, voltage 0 is supplied to these scanning lines. In addition, when the second field is selected, if the output signal OA is outputted from the shift register 11, the voltage Vr is supplied to the scanning lines COM1 and COM3, and the voltage xe2x88x92Vr is supplied to the scanning lines COM2 and COM4.
Thus, after the first through fourth fields are sequentially selected, the first through fourth fields are sequentially selected on the basis of, e.g., the column 71 through 74 shown in FIG. 11.
FIG. 13 shows the details of the conventional segment electrode driving circuit 30. The conventional segment electrode driving circuit 30 has a latch circuit 40i, an arithmetic circuit 90i, and a switch circuit 93i comprising five analog switches 93a through 93e, for each signal line SEGi (i=1, . . . , n). Each of the latch circuits 40i has two registers 41 and 42 as shown in FIG. 14.
The RAM 70 for display data stores therein data displayed on the liquid crystal display part. Each of the latch circuits 40i (i=1, . . . n) receives 4-bit data DD0, DD1, DD2 and DD3, which are to be transmitted to the corresponding signal lines SEGi, from the RAM 70 for display data to latch the data. These 4-bit data DD0, DD1, DD2 and DD3 are serially transmitted from the RAM 70 for display data. Thereafter, these data are transferred from the register 41 to the register 42 in parallel to be held therein. The 4-bit data DD0, DD1, DD2 and DD3 held in the register 42 of each of the latch circuits 40i (i=1, . . . , n) are transferred to the corresponding arithmetic circuit 90i at a predetermined timing. Furthermore, the data DD0 is a value displayed on a pixel corresponding to a common electrode connected to a scanning line COMj which is one of the simultaneously selected four scanning lines COMj (j=1, . . . , m), COMj+1, COMj+2 and COMj+3, and the data DD1 is a value displayed on a pixel corresponding to a common electrode connected to the scanning line COMj+1. The data DD2 is a value displayed on a pixel corresponding to a common electrode connected to the scanning line COMj+2, and the data DD3 is a value displayed on a pixel corresponding to a common electrode connected to the scanning line COMj+3. Each of the data DDi (i=0, 1, 2, 3) represents xe2x80x9c1xe2x80x9d when the corresponding pixel is ON, and xe2x80x9c0xe2x80x9d when it is OFF.
Each of the arithmetic circuits 90i (i=1, . . . , n) is designed to operate a value I, i.e., I=DD0@FD0+DD1@FD1+DD2@FD2+DD3@FD3, on the basis of the 4-bit data transferred from the corresponding latch circuit 40i, and the outputs FD0, FD1, FD2 and FD3 of the function generator circuit 55, and output a selection signal for selecting one of the five analog switches 93a through 93e of the corresponding switch circuit 93i. Furthermore, the symbol @ means an operation symbol indicative of an exclusive OR. FIG. 15 shows an example of the arithmetic circuit 90i (i=1, . . . , n). As shown in FIG. 15, each of the arithmetic circuits 90i has four exclusive OR gates 92, a full adder 93, half-adders 94 and 95, and a decoder 100 which comprises three inverter gates 96, three inverter gates 97, five NAND gates 98 and five inverter gates 99.
When the value I is xe2x80x9c0xe2x80x9d, the analog switch 93a is selected, and when the value I is xe2x80x9c1xe2x80x9d, the analog switch 93b is selected. When the value I is is xe2x80x9c2xe2x80x9d, the analog switch 93c is selected, and when the value I is xe2x80x9c3xe2x80x9d, the analog switch 93d is selected. When the value I is xe2x80x9c4xe2x80x9d, the analog switch 93e is selected.
Each of the switch circuits 90i (i=1, . . . , n) is designed to supply a voltage of xe2x88x92V0 (V0xe2x89xa00) volts when the analog switch 93a is selected, a voltage of xe2x88x92V0/2 volts when the analog switch 93b is selected, a voltage of 0 volt when the analog switch 93c is selected, a voltage V0/2 volts when the analog switch 93d is selected, and a voltage of V0 volts when the analog switch 93e is selected.
FIG. 16 shows a conventional RAM 70 for display data. The conventional RAM 70 for display data comprises a cell array 71 comprising a plurality of RAM cells 72 arranged in the form of a matrix, an address decoder 75, a display data read counter and decoder 77, an I/F control circuit 80, a data I/O circuit 82, and an oscillator circuit 85. Each of the RAM cells 72 comprises two transistors, a latch circuit comprising two inverter gates, and a three-state driver.
In the conventional RAM 70, when data are read out of or written in the cell array 71, one of selection signals is usually selected by the address decoder 75 to read or write data. However, when data are read out to be transferred to the latch circuit 40, the following operations are carried out. First, a clock is generated from the oscillator circuit 85. On the basis of this clock, selection signals are sequentially outputted from the display data read counter 77 at four times. Then, data are read out of the corresponding RAM cell 72 by each of the selection signals. The read data are serially transmitted to the latch circuits 401, . . . , 40n. Furthermore, each of the latch circuits 40i (i=1, . . . , n) is designed to sequentially hold data, which have been read out of the RAM cells 72 by a shift signal transmitted from the display data read counter 77, in the first register 41. The 4-bit data are held in the second register 42 at a time by a latch enable signal transmitted from the display data read counter 77 when all of 4-bit data are held.
Thus, the conventional liquid crystal display system has one arithmetic circuit 90i for each of the signal lines SEGi (i=1, . . . , n). The number n of signal lines SEG1 through SEGn is generally 100 or more. In addition, since each of the arithmetic circuits is formed as shown in FIG. 15, the number of elements (transistors) is large (e.g., about 230). Therefore, there are problems in that the chip size is large, and the yields of products deteriorate to increase the manufacturing costs.
In addition, in the conventional RAM for display data, it is required to quickly read display data four times, so that there is a problem in that electric power consumption increases.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a liquid crystal display system capable of preventing the manufacturing costs from increasing.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a liquid crystal driving circuit comprises: a function generating part for generating k (xe2x89xa72) kinds of function values for k fields on the basis of a field start signal, a shift clock and an alternating signal; a common electrode driving circuit for simultaneously selecting k common electrodes on the basis of the field start signal and the shift clock and for applying a plurality of kinds of common voltages to the selected k common electrodes; a RAM for display data, in which data to be displayed on a liquid display part are stored; and a segment electrode driving circuit including: data storing means for storing therein k+1 values in accordance with the k function values and 2k k-bit data and for simultaneously outputting 2k values on the basis of the alternating signal and a field select signal; 2k power supply lines provided so as to correspond to 2k outputs of the data storing means; a first analog multiplexer for connecting each of the 2k power supply lines to one of k+1 power supplies, each of which has a potential different from each other, on the basis of a corresponding one of the 2k outputs of the data storing means corresponding to a corresponding one of the 2k power supply lines; and a second analog multiplexer, provided for each of segment electrodes, for receiving k display data corresponding to the selected k common electrodes from the RAM for display data, and for selecting one of the 2k power supply lines on the basis of the k display data to connect the selected one of the 2k power supply lines to a corresponding one of the segment electrodes.
The first analog multiplexer may comprise: a decoder circuit for decoding each of the 2k outputs of the data storing means; and a switching part, provided for each of outputs of the decoder circuits, for connecting a corresponding one of the 2k power supply lines to one of the k+1 power supplies on the basis of a corresponding one of the 2k outputs of the data storing means.
The second analog multiplexer may comprise: decoder means for decoding the k display data received from the RAM for display data, as k-bit data; and a switching part for selecting one of the 2k power supply lines on the basis of an output of the decoder means to connect the selected one of the 2k power supply lines to a corresponding one of the segment electrodes.
The data storing means may be a data table.
The data storing means may have a first RAM, and the function generating part may have a second RAM, in which the function values are stored.
The common electrode driving circuit may be operated so as to sequentially shift the simultaneously selected k common electrodes, and the function generating part may further comprise field changing means for changing a field of a generated function every time the simultaneously selected k common electrodes are shifted.
The RAM for display data serially may output k display data which are to be transmitted to each of the segment electrodes, and the segment electrode driving circuit may further comprise latch circuits, each of which is provided for each of the segment electrodes and each of which comprises a first register for serially receiving k display data, which are to be transmitted to a corresponding one of the segment electrodes, from the RAM for display data, and a second register for receiving and latching, in parallel, the k display data, which are stored in the first register, to supply the latched display data to the second analog multiplexer.
The RAM for display data may output, in parallel, k display data, which are to be transmitted to each of the segment electrodes, and the segment electrode driving circuit may further comprise latch circuits, each of which is provided for each of the segment electrodes for latching k display data which are read out of the RAM for display data in parallel.
According to another aspect of the present invention, a liquid crystal driving circuit comprises: a function generating part for generating k (xe2x89xa72) kinds of function values for k fields on the basis of a field start signal, a shift clock and an alternating signal; a common electrode driving circuit for simultaneously selecting k common electrodes on the basis of the field start signal and the shift clock and for applying a plurality of kinds of common voltages to the selected k common electrodes; a RAM for display data, in which data to be displayed on a liquid display part are stored; an arithmetic circuit including: k+1 power supply lines, to each of which a voltage different from each other is supplied; and a counter circuit, provided for each of segment electrodes, for receiving k display data corresponding to the k common electrodes, one by one, in synchronism with a predetermined clock and for receiving the k function values outputted from the function generating part, one by one, in synchronism with the predetermined clock to be operated in accordance with an exclusive OR of the k display data and the k function values in synchronism with the predetermined clock; and a segment electrode driving circuit having an analog multiplexer, provided for each of the segment electrodes, for selecting one of the k+1 power supply lines on the basis of an output of the arithmetic circuit and for connecting the selected one of the k+1 power supply lines to a corresponding one of the segment electrodes.
The analog multiplexer may comprise: decoder means for decoding a value received from the arithmetic circuit; and a switching part for selecting one of the power supply lines on the basis of an output of the decoder means to connect the selected one of the power supply lines to a corresponding one of the segment electrodes.
USPTO Backgrounds
USPTO Backgrounds