1. Technical Field
The present invention relates generally to integrated circuit design, and more particularly, to a method, system and program product for improving IC design performance by analyzing IC timing based on a slack sensitivity to variations in parameters that affect timing.
2. Related Art
A wide variety of methods are employed in the optimization of integrated circuit designs. One of these methods includes evaluation of the static timing of parts of the circuit. Methodologies used today for static timing analysis are based on different parameters that affect timing. The parameter values used are typically based on nominal values of parameters or on extreme values of the range of values for a parameter, for example, a minimum and maximum value corresponding to +/−3 standard deviation units. In order to evaluate the impact that a given parameter will have on timing, a timing run is performed with the parameter set to a minimum value, and then another timing run is performed with the parameter set to a maximum value.
As technology offerings become richer in terms of increased features (e.g., the number of devices offered, increased metal layers or increased number of voltage islands), the number of parameters that affect timing grows accordingly. For example, the number of parameters can easily exceed 10 or more in today's technologies. Unfortunately, conventional techniques to evaluate timing over all parameters, requires 2N timing runs, where N represents the number of parameters. Each of the 2N timing runs uses a different combination of minimum and maximum settings for different parameters. Any one combination is referred to herein as a “parameter/process permutation.” Where the number of parameters exceeds 10, timing analysis can require more than 1000 timing runs for a complete evaluation, which is extremely time and resource consuming.
In addition to the above problem, conventional timing analysis approaches also do not satisfactorily address timing errors because they typically focus exclusively on timing endpoint (latch) slack, i.e., the difference between a timing requirement and an actual timing caused by the circuit. FIG. 1 shows one illustrative conventional approach. In this approach, in step S1, a timing run is conducted using a single parameter/process permutation to determine endpoint slacks. These slacks are not necessarily bounding (i.e., extreme values) since other choices for parameter/process permutations could easily lead to more conservative slacks. As a result, the conventional approach may yield circuit timing analysis results that fail to detect potential timing errors and lead to non-zero failure probabilities.
In step S2, these non-bounding slacks are then compared to a slack threshold. Slacks less than slack threshold S(threshold), where S(threshold) is typically chosen as zero, are considered failures that require correction. Unfortunately, timing endpoints with the largest negative slacks may not represent the most critical slacks in terms of maximizing product yield because their sensitivities to parameter variations may result in a smaller probability of failure as compared to other timing endpoints. In other words, using a single parameter/process permutation does not adequately address the sensitivities to parameter variations that may lead to failure. In addition, the conventional approach provides no insight relative to parameter non-tracking sensitivities, i.e., situations where two or more parameters that are normally expected to vary together in a particular manner do not vary together. Therefore, using slack values to prioritize timing endpoints for correction can lead to poor utilization of resources.
In step S3, the failing endpoints and corresponding slack values are targeted for correction. Since only the slack value from a timing analysis at a single parameter/process permutation is available to guide correction, the correction cannot improve design robustness against parameter variations or maximize chip performance under all variations. After correction, the conventional methodology returns to step S1 for validation.
In view of the foregoing, there is a need in the art for a way to address the problems of the related art.
USPTO Backgrounds
USPTO Backgrounds