1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to an interconnection layout of a semiconductor integrated circuit which eliminates or reduces errors that result from a capacitive coupling between data transfer interconnection lines.
A claim of priority is made to Korean Patent Application No. 2001-59573, filed Sep. 26, 2001, the contents of which are incorporated by reference in their entirety.
2. Description of the Related Art
A plurality of interconnections such as a signal line, a power interconnection, a ground interconnection, and the like are formed on a substrate of a semiconductor integrated circuit. These interconnections exhibit an electrical resistance (or interconnection resistance). Also, an interconnection capacitance is present between each interconnection and the substrate, and between each interconnection and an adjacent interconnection. When a signal is transferred through a signal line, a signal delay occurs which is dependent upon the product of the interconnection resistance of the signal line and the interconnection capacitance thereof. As such, the signal delay is largely influenced by the magnitude of the interconnection capacitance.
The interconnection capacitance is generally equal to the sum of a capacitance between a top side or a bottom side of an interconnection and a substrate (side element capacitance), a capacitance between a lateral side of the interconnection and the substrate (fringe capacitance), and a capacitance between adjacent interconnections (coupling capacitance).
Prior to the introduction of micron-sized semiconductor integrated circuits, the interconnection-substrate capacitances (side element and fringe capacitances) were more significant than the coupling capacitance. In recent years, however, as semiconductor integrated circuits have been continuously scaled down, the upper and lower areas of the interconnections have been reduced in size. On the other hand, the interconnection spacing has become narrower. Therefore, the coupling capacitance has increased in significance, to the point now where the coupling capacitance accounts for 50% or more of the total interconnection capacitance.
Also, since a substrate potential is generally fixed in the interconnection-substrate capacitance, it is unnecessary to consider the change in the substrate potential when calculating a degree of signal delay caused by the interconnection capacitance. On the other hand, the potential of a signal line transitions between different values according to the state of the transferred signal. The transition of the signal line potential leads to a change in the degree of signal delay caused by the coupling capacitance between the signal lines. When the potentials of two adjacent signal lines transition between high and low voltages at a same timing, or transition between high and low voltages at opposite timings, the degree of signal delay caused by the coupling capacitance changes. The resultant variability in signal delay makes circuit design difficult.
FIG. 1 shows an interconnection layout of a semiconductor memory device that has separate data-write lines and data-read lines.
Referring to FIG. 1, data inputted through data input terminals (not shown) is provided to a memory cell array (not shown) through data-write lines WL0 and WL1. Data read out from the memory cell array is outputted to data output terminals (not shown) through data-read lines RL0 and RL1. In a conventional interconnection layout, the data-write lines WL0 and WL1 are disposed to be adjacent to each other and the data-read lines RL0 and RL1 are disposed to be adjacent to each other. Accordingly, a coupling capacitance Cc is produced between the data-write lines WL0 and WL1 when the data is inputted through the data input terminals, and a coupling capacitance Cc is produced between the data-write lines RL0 and RL1 when the data read out from the memory cell array is loaded on the data-read lines RL0 and RL1.
The coupling capacitances Cc between interconnections distorts and/or variably delays the data, inhibiting an effective operation of the semiconductor memory device.
The present invention provides an interconnection layout which reduces the adverse effects of a coupling capacitance between interconnections in a semiconductor integrated circuit.
According to an aspect of the present invention, a semiconductor memory device includes a first group of first interconnection lines and a second group of second interconnection lines. The first interconnection lines and the second interconnection lines are alternately arranged one by one. In a preferred embodiment, the interconnection lines belonging to the first group are driven to a power supply voltage level when the interconnection lines belonging to the second group are held in a ground state, and the interconnection lines belonging to the second group are driven to the power supply voltage when the interconnection lines belonging to the first group are held in the ground state.
Also, in the preferred embodiment, signals transferred onto the interconnection lines belonging to the first group transition between voltage levels at different timings. Likewise, in the preferred embodiment, the signals transferred onto the interconnection lines belonging to the second group transition between voltage levels at different timings.
Further, in the preferred embodiment, the interconnection lines belonging to the first group are data write lines for transferring externally inputted data to the semiconductor memory device. Likewise, in the preferred embodiment, the interconnection lines belonging to the second group are data read lines for transferring data from the semiconductor memory device to the exterior of the semiconductor memory device.
USPTO Backgrounds
USPTO Backgrounds