1. Field of the Invention
This invention relates to integrated circuit manufacture and, more particularly, to a circuit, apparatus and method for electrically programming test outcome information upon and retrieving test outcome information from a circuit being tested.
2. Description of the Related Art
An integrated circuit is often referred to as a die or chip. Henceforth, those terms are interchangeably used. A die generally contains several thousand active and passive devices formed on a monolithic substrate. Those devices are generally interconnected to form an overall circuit.
The monolithic substrate is derived from what is called a semiconductor wafer which may embody several hundred die across that wafer. After the active and passive devices are formed and selectively interconnected, each die is then tested both visually and electrically. The die which fail testing may then be marked with a visually detectable imprint or marking. Die which are not marked can then be separated from the wafer and forwarded to an assembly operation.
Assembly involves placing electrically and visually viable die into a semiconductor package. Conventional assembly operations draw die from anywhere across a wafer, or from any wafer within a set of wafers or wafer lot. After assembly, the packaged die are tested. Leads extending from the package are electrically connected to a test socket which supplies stimuli to the die and receives an electrical result. The test performed after assembly may be similar to or slightly different from those performed before assembly.
FIG. 1 illustrates an exemplary, conventional sequence of tests 10 performed prior to and after assembly 12. The first test operation 14 performed on die within a wafer includes various parametric and functional tests. For example, the test parameters may include determining the current draw of the integrated circuit through the power supply conductor (i.e., I.sub.CC) Additionally, test 14 may determine "high" and "low" output levels of various output pins for specific input stimuli (i.e., V.sub.OH and V.sub.OL). Yet further, test 14 may include test parameters used to check propagation delay (i.e., T.sub.PD) and/or operating speed of the integrated circuit. If the integrated circuit embodies non-volatile storage elements, then a test of those elements may be needed. In particular, the elements may lose their program state or a non-programmed element may gain program status. Charge loss or gain may occur when the unpackaged die or packaged die is stressed either through electrical interactions or when a heat cycle is applied thereto.
Test operation 14 may therefore encompass numerous tests which may be similar to, partially similar to, or possibly altogether different from tests within subsequent test operations. In many instances test 14, being the first test operation, should encompass more test parameters than subsequent tests and/or encompass tighter test limits than subsequent tests. Accordingly, each of the sequence of tests 10 produces a quantifiable test result for each parameter being tested. Also, each of the sequence of tests 10 includes and tests limits for each test parameter. For example, V.sub.OH and V.sub.OL are represented as a quantifiable voltage value. The quantifiable test result for each test parameter is typically compared against a test limit. If the test results surpasses the test limit, then the die or packaged die will be placed in a "bin" as a failure 16. Thus, the test sequence 10 will check to see if the die being tested is within the test limit or range of (i.e., passes) each of the tested parameters. If a pass 18 occurs, then the die may undergo temperature stress before being tested again or, in the alternative, be tested at a different temperature subsequent to the first test 14. Temperature cycling the die before or during the second test 20 helps determine reliability of the die. Test 20 is similar to test 14 in that it represents an electrical test comprising a plurality of electrical test parameters. Second test 20 may contain parameters which are partially the same as, entirely the same as, or altogether different from the parameters used for test 14. If the test results of each test parameter are within the corresponding test limits, then the die is said to pass 22 the second test 20.
There may be numerous tests performed at wafer sort, often called wafer probe. In the example shown, two tests are performed possibly at different temperatures and possibly with interim temperature cycling. The die which pass both tests may then be assembled as good, packaged die. The assembly operation itself may harm or destroy the packaged die. Thus, tests must be performed after assembly and before shipping the final product to a customer. Shown in FIG. 1 is an exemplary pair of test operations 24 and 26 performed after assembly. If the first test 24 passes 28, then the second test 26 is undertaken. The parameters used in test 24 may be the same as or dissimilar to the parameters used in test 26. Likewise, the tests limits may be different. In many instances, the parameters may be the same, but the limits are preferably loosened for subsequent tests relative to earlier tests. In this way, failures can be screened earlier in the test sequence. Test 26 can suffice as possibly the final tests performed at limits defined by the specification published by the integrated circuit manufacturer. The results of each parameter being tested at test 26 are compared against the specification limits to determine if the packaged integrated circuit passes 30. If the packaged die does pass, then the packaged produc t is shipped 32 to a customer.
An unfortunate outcome of a conventional test sequence is a lack of quality control. For example, a test result may be stored within a database which tracks the products being tested. The database is, however, maintained remote from the integrated circuit. If t he integrated circuit fails in the field, then the only way in which to determine if the product was shipped as a failure is to examine the database. This assumes that the database is maintained by the manufacturer and traceability between the identified integrated circuit and the test result is not corrupted. As shown in FIG. 1, test outcome 34 is stored within a database and is generally attributed to a wafer lot or wafer run, and not necessarily to each and every packaged integrated circuit tested and/or shipped.
Absent traceability to a particular integrated circuit shipped, the manufacturer cannot easily control the quality of the shipped product either after it is shipped or, more importantly, before it is shipped. Thus, an integrated circuit which fails in the field may not have attributed to it data stored within a database. Even if there is data attributed, attribution occurs only after the packaged product is shipped. The database therefore suffers as a failure analysis tool prior to shipping the product. A comparison of test results from one test to another may be difficult since the database information is not always recalled at each test operation. Determination of how, when, and the magnitude of each failure at specific test operations is difficult unless data within the database can be quickly and easily recalled at each and every, subsequent test operation. Currently, mechanisms to easily program the database and recall information unique to each and every test operation, and possibly each and every test parameter used at those operations, are lacking.
USPTO Backgrounds
USPTO Backgrounds