The present invention relates to an improvement of techniques for constructing a receiver circuit for receiving a packet FSK (Frequency Shift Keying) signal by a receiver having frequency scanning faculty.
There are various kinds of types of packet FSK signals. One of them is a packet FSK signal of such type that a duration to issue a center frequency is provided in a head portion of a packet.
In a case that a packet FSK signal having frequency error is received, in general, firstly, frequency scanning of a local oscillator is done and then when the frequency of a received signal becomes within the pass band of an IF (Intermediate Frequency), a carrier detector detects this situation to render the frequency scanning stop. However, at this time, the frequency of the IF signal does not coincide with that of an object signal, so that frequency error remains yet. So, it is necessary to remove this frequency error by causing an AFC (Automatic Frequency Circuit) to operate at the same time with stop of frequency scanning or to correct a DC offset component provided in a base band portion owing to remained frequency error.
Various correcting circuits for a packet signal having packet construction wherein a bit synchronizing signal is provided in a head portion thereof are proposed to attain the above mentioned object. However, there is no correcting circuit to correct said frequency error for a packet FSK signal such type that a duration to issue a center frequency is provided in a head portion of a packet in general a frequency error correcting circuit for a packet signal having packet construction wherein a bit synchronizing signal exists in a head portion thereof is used.
Followings are known for correcting methods in employed in these correcting circuits.
As representatives thereof there are known 1) a method in which there are disposed a positive and a negative peak hold circuit and the center level is obtained, starting from an average of peak values held therein; 2) a method in which there are disposed a positive and a negative dead zone circuit having dead zone voltage widths, which are in accordance with a positive and a negative peak value width, respectively, of the base band signal, and the center error is obtained by taking out components outputted, exceeding these dead zone voltage widths, in the base band signal; 3) a method in which the center level obtained by integrating a bit synchronizing signal, which is at a beginning of the packet signal, over a 2 bit length (a period of time of 2/baud sec (baud being transmission speed)); 4) a method in which the bit synchronizing signal is sampled twice with an interval of 1/baud sec and the center level is obtained, starting from an average of these sampled values; etc.
However these methods have such disadvantages that two circuits have same faculty are required or construction of a control circuit is complicated because these methods do not make use of a center frequency information in a head portion of a packet.
An object of the present invention is therefor to provide a correcting circuit capable of correcting a center frequency error or an error in the center level of a base band signal with a simple function and construction.
A frequency scanning receiver for a packet FSK signal of such a type that a duration,to issue a central frequency is provided in a head portion thereof according to the present invention comprises conversion point detecting means for detecting a time point when a demodulated base band signal obtained by demodulating said packet FSK signal pass through a conversion point in said duration; and hold means for holding a scanning voltage to scan said packet FSK signal.
In said frequency scanning receiver, said conversion point detecting means may include a comparator for comparing said demodulated base band signal with a reference voltage and a carrier detector for detecting whether there is said base band signal or a IF signal or not, a conversion point detector for detecting inversion of an output signal from the comparator at said time point, and a flip-flop circuit set by an output signal of said conversion point detector and reset by an output signal from said carrier detector representing that there is no said packet FSK signal, and said hold means may include a sample and hold circuit a sample value of said scanning voltage by a set output from said flip-flop circuit.
USPTO Backgrounds
USPTO Backgrounds