1. Field of the Invention
The present invention generally relates to a method for manufacturing a device isolation film of a semiconductor device, and more specifically, to a method for manufacturing a device isolation film of a semiconductor device wherein a liner nitride film exposed by etching a liner oxide in a peripheral region is oxidized using plasma prior to the formation of the device isolation film to prevent or reduce a Hot Electron Induced Punchthrough (HEIP) phenomenon and/or to improve characteristics of a semiconductor device.
2. Description of the Related Art
FIGS. 1a through 1e are cross-sectional diagrams illustrating a conventional method for manufacturing a device isolation film of a semiconductor device.
Referring to FIG. 1a, a pad oxide film 20 and a pad nitride film 30 are sequentially formed on a semiconductor substrate 10. The semiconductor substrate 10 includes a cell region 1000a and a peripheral region 1000b. 
Referring to FIG. 1b, a predetermined region of the pad nitride film 30, the pad oxide film 20 and the semiconductor substrate 10 where a device isolation film is to be formed is etched to form a trench 40.
Referring to FIG. 1c, a sidewall oxide film 50 is deposited on a surface of the trench 40. Thereafter, a liner nitride film 60 and a liner oxide film 70 are sequentially formed on the entire surface of the semiconductor substrate 10.
Referring to FIG. 1d a gap-filling oxide film 80 is formed on the entire surface of the semiconductor substrate 10 to fill up the trench 40.
Referring to FIG. 1e, the gap-filling oxide film 80 is planarized until the pad nitride film 30 is exposed. Thereafter, the pad nitride film 30 and the pad oxide film 20 are removed to form a device isolation film 90.
The conventional method discussed may reduce a leakage current due to the liner nitride film and the liner oxide film. However, an electron trap is formed at an interface of the nitride film and the oxide film in the pMOS region where a pMOS transistor is formed to trap hot electrons.
Trapped hot electrons may induce a HEIP phenomenon. The HEIP phenomenon refers to a state when a current flow is generated in a channel region even though a voltage is not applied to a gate of the PMOS transistor. The HEIP phenomenon increases a stand-by current of a DRAM, which degrades device characteristics and yield.
In order to address these problems, manufacturing methods have been proposed that increase the thickness of the sidewall oxide film. However, as the thickness of the sidewall oxide film increases, gap-fill characteristics deteriorate and active region width decreases. The deterioration of gap-fill characteristics and decrease in active region width reduces the current driving capability and threshold voltage of a transistor, and degrades refresh characteristics of the transistor. As such, a need exists for an improved method for manufacturing a device isolation film of a semiconductor device.
Other problems with the prior art not described above can also be overcome using the teachings of the present invention, as would be readily apparent to one of ordinary skill in the art after reading this disclosure.
USPTO Backgrounds
USPTO Backgrounds