The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing at least one void-free metallization region (interconnect metallic region and/or metallic contact region) having a biconvex shape and exhibiting a low wire resistance, and a method of forming the same.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structures typically include copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
As the interconnect metal feature sizes shrink, it is necessary to scale diffusion barrier thickness in order to minimize the volume of the interconnect metallic region and to enable low line and via resistance. The diffusion barrier cannot, however, be scaled to zero thickness, thus dimensional changes such as, for example, asymmetric line/space methods (i.e., wide metal lines and narrow spaces) are being pursued to reduce the back-of-the-line (BEOL) interconnect resistance. Since the resistance, R, increases more rapidly than capacitance, C, as dimensions are reduced, these approaches are attractive in order to lower RC for advanced technologies nodes. However, asymmetric line/space methods suffer from dielectric flopover risks as well as increased leakage and electrical shorts.
Similar to BEOL, middle-of-the-line (MOL) resistance reduction is essential to meet overall circuit performance.
There is thus a need for providing metallization structures which exhibit an enlarged metal conductor volume created without dielectric flopover. Such metallization structures would enable low resistance for the next generation of devices.
USPTO Backgrounds
USPTO Backgrounds