A low package resistance and good thermal performance is often desirable for semiconductor devices. This is particularly the case for metal oxide semiconductor field effect transistor (MOSFET) devices, especially vertical conduction power MOSFET devices having gate and source electrodes on one surface of a semiconductor chip and a drain electrode on the opposite surface. It is also generally desirable to have simple, quick and efficient methods of packaging semiconductor devices. Thus, numerous packaging concepts and methods have been developed in the prior art.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old packaging technology continues as the primary packaging means. Epoxy or solder die attachment along with aluminum or gold wire bonding to a lead frame is still the dominant semiconductor packaging methodology. Advances in semiconductor processing technology, however, have made parasitics (e.g., resistances, capacitances and inductances) associated with conventional packaging techniques more of a performance-limiting factor. In the case of conventional flip chip technology, among other shortcomings, electrical connection to the back side of the die is not easily facilitated. These limitations become quite significant in high current applications such as power switching devices.
U.S. Pat. No. 6,767,820 discloses a chip scale package of semiconductor MOS-gated device. A source side of a MOS-gated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. The material is then dried and the coated wafer is exposed using standard photolithographic techniques to image the wafer and openings are formed in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. The openings in the passivation layer are typically made through to a conventional underlying solderable top metal such as titanium, tungsten, nickel, or silver. After the openings are formed, the wafer is then sawn or otherwise singulated into individual die. The solderable drain side of the die is then connected to a U-shaped or cup-shaped drain clip, using a conductive epoxy or solder, or the like to bond the bottom drain electrode of the die to the drain clip. The bottoms of the legs of the drain clip are coplanar with the source-side surface (that is the tops of the contact projections) of the die. U-shaped clip is usually made of a copper alloy with at least partially plated silver surfaces and is actually very thin. However, connecting dies to individual clips tends to be time consuming compared with wafer level process. In addition, different U-shaped clips are typically needed for different die sizes, and the clips take extra space on the PC board.
US publication number 2003/0052405 discloses a vertical power MOSFET device with the drain electrode formed on the bottom surface of the silicon substrate connected to the lead frame above it whereas the gate electrode and the source electrode exposed to the bottom of the device. The MOSFET device is sealed by a resin, such as epoxy or silicone, such that the MOSFET device and an inner part of the lead frame are covered. On the bottom surface of the MOSFET device, the surface of the resin is approximately flush with surfaces of the lead frame and gate/source electrodes. That is, on the bottom surface of the semiconductor device, the bottom surface of outer lead portions of the lead frame and bottom surfaces of gate/source electrodes are exposed for connection to a conductor land (mount surface) of the mounting substrate. Then the perimeter of these gate/source electrodes is covered by the resin.
U.S. Pat. No. 6,133,634 discloses a flip chip package having a power MOSFET device including a drain terminal, a source terminal and a gate terminal. The drain terminal connects to a conductive carrier and an outer array of solder balls. The source terminal and gate terminal connect to an inner array of solder balls. The conductive carrier and the outer array of solder balls provide electrical connection between the printed circuit board and the drain terminal.
U.S. Pat. No. 6,469,384 discloses a method of packaging semiconductor devices, such as MOSFET device, which does not require a molded body. The MOSFET device is coupled to a substrate such that the source and gate regions of the die are coupled to the substrate. The MOSFET device is placed on a printed circuit board (PCB) and the surface of the die is coupled directly to the PCB with solder paste or suitable electrically conductive interconnect, and thus serves as the drain connection. The surface of the die coupled to the substrate comprises the gate region and the source region of the die. Thus, the solder ball in the gate region of the substrate serves to couple the gate region of the die to the PCB while the remaining solder balls couple the source region of the die through the substrate to the PCB.
The preceding prior art package designs for vertical power MOSFET devices can provide electrical interconnection for source, gate and drain for individual MOSFETs. However, additional assembly steps are needed after a wafer has been singulated into individual dies, which increases costs and fabrication time. In addition, the use of metal clips to provide drain contacts from the back to front sides of the die can reduce the available space for the die on a PCB. It would be desirable to produce a package design and process for its manufacture which permits wafer level processing with lower costs and a reduced footprint for individual part.
It is within this context that embodiments of the present invention arise.
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