1. Field of the Invention
The invention relates generally to non-volatile memory devices, and in particular to flash memory and manufacturing of flash memory devices.
2. Description of Related Art
In memory cells using dielectric charge trapping structures, the device can be planar because there is no coupling ratio engineering involved in the design. Because of the planar structure, and very little coupling between adjacent cells, memory cells using dielectric charge trapping structures are forecast to overtake floating gate memory cells in importance as the minimum feature size for the manufacturing processes goes beyond about 45 nanometers.
In some planar memory cells, the floating gate is combined with a dielectric charge trapping structure between the control gate and the floating gate. In such cases the dielectric charge trapping structure has been very difficult to erase, the device is considered difficult to erase and impractical. A planar memory cell can use ONONO for the dielectric charge trapping structure, although at the cost of additional fabrication steps to add the extra layers. In cases where ONONO is used for the dielectric charge trapping structure, charge is programmed and erased primarily on the dielectric charge trapping structure rather than the floating gate.
One problem with planar floating gate devices is that charge is easily injected into the interpoly dielectric because of the presence of a large electric field during programming. However, is very difficult to remove the charge in the interpoly dielectric, making the device very hard to erase, and as a result unusable as in applications of flash memory devices.
It is desirable to make a planar memory cell with a simple dielectric charge trapping structure and yet remain practical to use with satisfactory erase and program performance.
USPTO Backgrounds
USPTO Backgrounds