The present invention generally relates to serial bus speed-up circuits, and more particularly to a serial bus speed-up circuit which increases a data transfer rate of a serial bus.
Conventionally, serial buses such as I.sup.2 C, Access Bus and SM Bus make data transfers using a small number of signal lines, by transmitting a clock and a data using 2 signal lines. In such a serial bus, each drive employs an open-collector drive output system and a wired-OR connection system, so that a plurality of devices can be connected to the serial bus.
FIGS. 1A and 1B are block diagrams showing an example of a serial bus circuit. In FIG. 1A, devices 12.sub.1 through 12.sub.N are connected to a signal line 10 of a serial bus. The signal line 10 is connected to a power supply Vcc via a pull-up resistor R, and the data or the clock is transferred using this signal line 10. In each of the devices 12.sub.1 through 12.sub.N, a transceiver 16 shown in FIG. 1B uses an open-collector transistor, and a collector of an output transistor is connected to the signal line 10 by a wired-OR connection. In addition, each of the devices 12.sub.1 through 12.sub.N has a receiver 14 which is connected to the signal line 10. In each of the devices 12.sub.1 through 12.sub.N, the transceiver 16 and the receiver 14 are connected to a function part 18.
One of the devices 12.sub.1 through 12.sub.N in which a data transfer request is generated sets a clock signal line of the serial bus to a low level, and transmits to a data signal line of the serial bus a data shown in FIG. 2(B) in synchronism with a clock shown in FIG. 2(A). Another one of the devices 12.sub.1 through 12.sub.N which receives the data inputs the data at a rising timing of the clock.
Conventionally, there is a bus system which varies a clock frequency in order to increase the data transfer rate of the bus. For example, a Japanese Laid-Open Patent Application No. 63-81556 proposes a bus system provided with a bus which is connected to a plurality of devices, a variable period clock generating means for supplying to each of the devices, as a common clock which restricts transmission and reception timings of the data transferred via the bus, a clock signal having a period which dynamically changes during operation of the bus, and a selecting means for selecting the period of the clock signal to be used for each data transfer operation depending on a data transfer operation condition.
In the serial bus described above, when the signal such as the data and the clock makes a transition from a low-level state to a high-level state, the signal rising time depends upon the resistance of the pull-up resistor R. In other words, if a total capacitance of a stray capacitance of the signal line 10 and input/output capacitances of the devices 12.sub.1 through 12.sub.N connected to the signal line 10 is denoted by C and the resistance of the pull-up resistor R is denoted by R, a level V of the signal when the signal makes the transition from the low-level state to the high-level state can be described by the following formula, where t denotes the time. EQU V=Vcc(1-exp(-t/C.multidot.R))
The input of the data is started with respect to the edge of the clock, and at the receiving end, it is necessary to guarantee a sufficient set up time of the data with respect to the edge of the clock. On the other hand, at the transmitting end, the data output is prescribed by a valid delay time from the edge of the clock. Hence, at least a sum of the valid delay time and the set up time becomes a minimum value of the clock period on the bus on the assumption that data flight time and transition time are equal to zero, and it is impossible to further increase the data transfer rate.
FIG. 2(B) shows the set up time, the valid delay time, and a transition time of the data, with respect to the clock shown in FIG. 2(A).
It is conceivable to reduce the resistance of the pull-up resistor R in order to increase the data transfer rate, but this would result in problems such as increased power consumption and increased sink current of the transceiver 16 of each device.
In the bus system proposed in the Japanese Laid-Open Patent Application No. 63-81556, the distances among each of the devices connected to the bus are known in advance, and a high-frequency clock is used when the distance between the devices transferring the data is short, and a low-frequency clock is used when the distance between the devices transferring the data is long. In other words, the clock frequency used for the data transfer between two devices is fixed in advance. For this reason, there is a problem in that it is difficult and troublesome to cope with a modification of the system such as an addition of a device connected to the bus and a change in a position where the device is connected to the bus. In addition, there is a problem in that it is impossible to increase the data transfer rate depending on a pattern of the data to be transferred.
USPTO Backgrounds
USPTO Backgrounds