A selective oxidation process is widely used in the semiconductor device industry for isolating individual semiconductor devices produced on a single semiconductor substrate. The selective oxidation process is based on an idea to employ a film of Si.sub.3 N.sub.4 which scarcely allows O atoms to pass through, as an oxidation mask, includes "planox" developed by SGA of Italy, "LOCal Oxidation of Silicon (LOCOS)" developed by Philips of the Netherlands and "iso-planer" developed by Fair Child of the U.S.
In the wake of increasingly severe requirements to enhance the integration of an integrated circuit, an improvement applicable to the selective oxidation process was disclosed in one of the Japanese patent publication, Toku Kai Hei 4-105346 or JP-A-4-105346, in 1992.
Described below, referring to drawings, will be the improved technology which uses the SiO.sub.2 layer which absorbs or relaxes stress caused by oxidation and a wall-shaped Si.sub.3 N.sub.4 mask which suppresses horizontal growth of an SiO.sub.2 layer ultimately for preventing a bird's beak from extending into an active area.
Referring to FIG. 1, a thermal oxidation process is conducted to produce an SiO.sub.2 layer (601) having a thickness of several tens of nm on the top surface of a conductive Si substrate (600). The function of this SiO.sub.2 layer (601) is to absorb or relax stress caused by oxidation of the Si substrate (600) or to prevent the stress from spreading toward under a mask employed for the oxidation. In this sense, the SiO.sub.2 layer (601) is called a stress relaxing layer. A CVD process is conducted to produce an SiO.sub.2 layer (602) having a thickness of several tens of through several hundreds of nm on top of the SiO.sub.2 stress relaxing layer (601). The function of this SiO.sub.2 layer (602) is to increase the height of the Si.sub.3 N.sub.4 layer (603) to be produced in the next step, with respect to the top surface of the Si substrate (600). A CVD process is conducted to produce an Si.sub.3 N.sub.4 layer (603) having a thickness of several tens through several hundreds of nm on top of the SiO.sub.2 layer (602). A photo lithography process is conducted to remove the SiO.sub.2 layer (602) from a field (or isolation) area or an area on which a thick SiO.sub.2 layer (605) is scheduled to be produced in a following step for the ultimate purpose to isolate each of semiconductor elements produced on the Si substrate (600). An exemplary width and a thickness of the field area are respectively 1.2 through 1.5 .mu.m and 300 through 400 nm. An impurity having a conductivity identical to that of the Si substrate (600) is implanted, in an area of the SiO.sub.2 layer (602) corresponding to the field area for the ultimate purpose to produce a channel stopper layer (604) illustrated in FIG. 2.
Referring to FIG. 2, a thermal oxidation process is conducted, employing the patterned Si.sub.3 N.sub.4 layer (603) as a mask. As a result, a thick SiO.sub.2 layer (605) having a thickness of several hundred nm is produced in the field area. The thickness of the SiO.sub.2 layer (605) is approximately a half of the ultimate thickness of the insulator layer of a field area. Incidentally, the impurity having a conductivity identical to that of the Si substrate (600) is moved downward to produce the channel stopper layer (604) under the thick SiO.sub.2 layer (605).
Referring to FIG. 3, an anisotropic etching process is conducted to reduce the thickness of the SiO.sub.2 layer (605) and to produce grooves along the edges of the SiO.sub.2 layer (605). The groove turns out to surround the active areas. After an Si.sub.3 N.sub.4 layer (606) is produced to cover the SiO.sub.2 layer (605) and the Si.sub.3 N.sub.4 layer (603), an anisotropic etching process is conducted to leave the Si.sub.3 N.sub.4 layer (606) exclusively along the edges of the SiO.sub.2 layer (605). The Si.sub.3 N.sub.4 layer (606) remaining along the edges of the SiO.sub.2 layer (605) has a shape of a wall which surrounds the active area.
Referring to FIG. 4, a thermal oxidation process is conducted again, employing the patterned Si.sub.3 N.sub.4 layer (603) of which the edges are lined with the Si.sub.3 N.sub.4 layer (606). As a result, the thickness of the SiO.sub.2 layer (605) is inflated to 300 through 400 nm to produce an SiO.sub.2 layer (607) forming a field area.
Since the edges of the SiO.sub.2 layer (607) do not extend in the horizontal direction, due to the Si.sub.3 N.sub.4 walls (606) arranged along the vertical edges of the piled layer of the Si.sub.3 N.sub.4 layer (603), the SiO.sub.2 layer (602) and the SiO.sub.2 layer (601), the dimension of bird's beaks (608) turns out to be relatively small or in the range of several tens of nm.
The improved technology disclosed in the foregoing prior art, JP-A-4-105346, however, has drawbacks tabulated below.
1. In the improved technology, a wall-shaped Si.sub.3 N.sub.4 mask (606) must be produced to line the vertical sides of the mask made of a piled layer of the Si.sub.3 N.sub.4 layer (603), the SiO.sub.2 layer (602) and the SiO.sub.2 layer (601) to prevent horizontal growth of the SiO.sub.2 layer (607) or of the bird's beak. Further, the SiO.sub.2 layer (602) must be produced between the SiO.sub.2 layer (601) and the Si.sub.3 N.sub.4 layer (603) for the purpose of making the height of the wall-shaped Si.sub.3 N.sub.4 mask (606) sufficiently large. Thus, the number of steps necessary for the foregoing improved technology is larger than that of the traditional selective oxidation process. In addition, since CVD processes which inherently require a long process time must be employed for some steps of the foregoing improved technology, the length of time required for the process is very long. PA0 2. The oxidation processes to produce the SiO.sub.2 layers (605) and (607) are inevitably accompanied by a phenomenon to gather SiO.sub.2 molecules to produce grains thereof. During the etching process to remove the wall-shaped Si.sub.3 N.sub.4 mask (606), the SiO.sub.2 grains become dust, resultantly causing adverse results to make the yield or the throughput of the process less satisfactory. PA0 3. Since the surface of the channel stopper layer (604) is covered by the wall-shaped Si.sub.3 N.sub.4 mask (606) during the oxidation process, minute grooves (609) are made along the line separating the SiO.sub.2 layer (607) from the channel stopper layer (604). Thus, the crystalline orientation of the surface becomes different for the channel stopper layer (604) from that of the Si substrate (600). Accordingly, the edges of the active areas can not be utilized for producing a semiconductor element. This resultantly reduces the integration of an IC to some extent. PA0 4. Due to the foregoing minute grooves produced along the line separating the SiO.sub.2 layer (607) from the channel stopper layer (604), a portion of a conductive Si layer which will be produced in a later step on the active area remains on the minute grooves during an etching process to be conducted in a later step. This remaining conductive Si layer causes various adverse results, e.g., a short circuit to bridge a source and a drain of an FET produced on the active area.
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