An integrated circuit (IC) typically includes numerous connections between electrical components. These connections are often designed with the assistance of an electronic design automation (EDA) tool. The EDA tool typically includes software instructions operating on an engineering workstation to provide visualization of the IC design. A design engineer manipulates modular design cells from a cell library to build up a design database. An autorouter within the EDA tool determines the connection paths between the design cells. When the design layout is complete, the layout data are used in a pattern generation (PG) step that generates pattern data suitable to produce a set of pattern masks used in photolithographic steps of an IC manufacturing process.
Among the connections made on the IC are input/output redistribution connections formed between IO cells and corresponding wirebond pads and/or bump pads, collectively referred to as IO pads. The redistribution connections are typically formed in a redistribution layer. Signal routing within the redistribution layer is often constrained by factors including the congestion of the connection and the mapping of IO signals to the IO pads. In many cases these constraints cause the routing of the IO connections to be deficient in some way, such as being is undesirably circuitous. In some cases the autorouter may even fail to find a path between an IO cell and its corresponding IO pad.
Such cases may require manual intervention by a design engineer, consuming valuable engineering resources and increasing the design cost. Improved methods of forming connections within the redistribution layer are needed to reduce these costs.
USPTO Backgrounds
USPTO Backgrounds