Phase detectors are an essential component of phase-lock-loops (PLLs) which are used in a variety of communication systems. One type of phase detector uses a pair of flip-flops that each receive an input signal and each generate an output signal. The phase detector relies on the common-mode rejection of circuitry within the PLL to extract a differential output pulse from the two output signals. The differential output pulse has a pulse width equal to the time delay between the input signals which indicates the phase difference between the input signals. High performance of the communication system is dependent on high common-mode rejection of the circuitry in the PLL, which is difficult to maintain over a wide signal bandwidth. This type of phase detector is also susceptible to spurious signals from power supplies and other sources which produce unwanted differential-mode spurious signals at the outputs of the flip-flops. The circuitry coupled to the flip-flops is responsive to differential-mode signals in order to extract the differential output pulse, but the circuitry also responds to the unwanted differential-mode spurious signal, degrading the performance of the communication system in which this type of phase detector is used. In addition, mismatches in propagation delays through the flip-flops also generate differential-mode spurious signals, further degrading the system's performance.
USPTO Backgrounds
USPTO Backgrounds