In the field of data compression, there exist techniques implementing variable-length compression codes, such as, for example, Huffman codes. These variable-length codes are well known to the person skilled in the art and widely used in the field of data storage and transmission. By way of example, such codes are used in combination with others in compression standards such as MPEG2 or MPEG4, for digital video broadcasting.
The principle of a variable-length compression code comprises replacing binary words of fixed length by binary symbols of variable length. For a data packet to be compressed, a statistical study makes it possible to ascertain for each fixed length word its probability of occurrence in the packet. A correspondence table is thereafter created so as to match each fixed length word up with a corresponding variable length symbol. A word having a high probability of occurrence is coded on a symbol of small size while a word having a low probability of occurrence is coded on a bigger size symbol.
Compressed data encoding with the aid of a variable length code is conventionally done with a processing device using a processor. FIG. 1 represents a known example of a processing device comprising a processor 100 of RISC type coupled to a programme memory 200 and to a data memory 300. The processor 100 mainly includes an instruction decoding circuit 110, a bank of registers 120, buffer registers 130, an address calculation circuit 140, an arithmetic and logic unit (ALU) and a data memory interface 160. This microprocessor 100 is of “pipeline” type, that is to say an instruction is processed in several clock cycles. In the example described, a first clock cycle serves to decode the instruction and to load the buffer registers 130, and a second cycle serves to perform the operation corresponding to the instruction. By exception, however, a data write can be performed in a single clock cycle.
As is known to the person skilled in the art, processors use words of fixed size to perform operations, for example words of m bits where m is a determined positive integer. When data are compressed in the form of symbols of variable size, the symbols are concatenated into words of m bits so as to be stored in the data memory 300.
FIG. 2 shows an exemplary memory plane of a data memory organized as words of m bits, for the storage of symbols. By way of example, five symbols S0 to S5 are stored on (2×m)+1 bits belonging to three memory words of consecutive addresses (i+1) to (i+3) respectively.
To be able to retranscribe the bits of a symbol read from the memory into a single word of m bits, the processor should ideally read the word or words of m bits containing the bits of the symbol then perform a bit masking operation so as to conserve only the bits of the symbol, and thereafter a bit shift operation so as to set the bits of the symbol either to low-order bits, or to high-order bits in a word of m bits. If the symbol is written in tandem on two words of the memory, as is the case for example for the symbol S3, two read operations, two masking operations and two shift operations are necessary as well as a logic operation of OR type to obtain the symbol without the form of a single word. It is only thereafter that the symbol can be decoded to obtain the corresponding decoded word.
The storage (writing) of a symbol in the memory also necessitates a certain number of operations, a symbol having to be shifted so as to arrive next to the previous symbol before being added by an operation of OR type. It is only then that the write can take place. If the shifted symbol is distributed over two words, additional masking operations are necessary.
Thus the reading or the writing of a symbol may necessitate three to seven elementary operations. In the case of a “pipeline” processor using two clock cycles per operation, four to eight clock cycles are necessary with interlaced operations.
The reading or the writing of a symbol therefore necessitate a non-negligible processing time for a processor dedicated to variable-length compression coding/decoding. Now, in a video stream broadcasting chain, the number of symbols transmitted per second is very high (several million symbols per second). This is why solutions are sought for reducing the processing time related to the reading or to the writing of a variable size symbol in a memory.
A solution is proposed in the document EP-A-0 849 709. This solution comprises supplementing the arithmetic and logic unit of a processor with means for supporting operations dedicated to the shaping of symbols. Three specific operations are proposed making it possible to reduce the reading or the writing of a symbol to a number of elementary operations of between three and six. In the case of a “pipeline” processor using two clock cycles per operation, only four to seven clock cycles are then necessary with interlaced operations.
USPTO Backgrounds
USPTO Backgrounds