The present invention relates to printed circuit board (PCB) design and, more particularly, to a method and apparatus for determining an optimum clock offset of the PCB bus clock to thereby maximize the permissible range of bus trace lengths in cases where external factors limit the maximum speed of the bus.
A typical PCB comprises several electrical components, such as, for example, microprocessors, memory elements and interface components, which communicate with each other via a globally clocked bus of the PCB. When integrated circuits (ICs) are designed, the IC designer sometimes increases the lengths of certain traces, or routes, from the pads of the die of the IC to the pins of the IC in order to equalize the lengths of the traces. The traces are conductive paths that comprise the bus of the IC package. Increasing certain trace lengths ensures that the signals traveling on the traces require the same amount of time to travel from the die to their respective pins, and vice versa.
When the PCB designer designs the PCB, the PCB designer sometimes increases the lengths of certain traces of the PCB bus in order to provide all of the traces of the PCB bus with equal lengths. However, the PCB and the IC design processes are performed independent of one another. Although the PCB designer typically utilizes the timing specifications of the IC packages in designing the PCB, these specifications normally do not provide information regarding the individual trace lengths within the IC package. Therefore, the PCB designer typically adds trace lengths to the PCB bus without having knowledge about the individual trace lengths of the IC package, which may not result in the best overall optimization of the PCB bus, but will result in more work for the PCB designer.
FIG. 1A is a block diagram of two different ICs 1 and 2 that are located on a PCB (not shown) and that communicate with each other via a PCB bus 3. The bus 3 is a globally clocked bus. The ICs 1 and 2 are xe2x80x9cdifferentxe2x80x9d in that they at least have different timing parameters (e.g., setup and hold times, clock-to-Q, etc.). FIG. 1B is a more detailed illustration of the ICs 1 and 2 and the PCB bus 3 shown in FIG. 1A. IC 1 has a die 4 and each signal is routed from a particular location on the die 4 to one of the pins 5. The signals are routed by traces 6 that connect the particular locations on the die to respective pins 5. The locations at which the traces or wire bonds are connected on the die 4 typically correspond to bus drivers (not shown). The pins 5 on IC 1 are connected to IC 2 at respective pins 8 of IC 2 via traces 9 of the PCB bus 3. The pins 8 are connected to particular locations on the die 11 of IC 2 by traces 12 of the IC 2.
As stated above, the PCB board designer typically does not utilize information relating to the lengths of the traces 6 and 12 of the ICs 1 and 2, respectively. Therefore, adding trace lengths to the PCB bus traces 9 in order to equalize the lengths of the traces 9 may not result in optimization of the PCB bus 3 because doing so will not necessarily equalize the pad-to-pad trace lengths (i.e., the routing distances between the locations on the die 4 at which the traces 6 are connected and the locations on the die 11 at which the traces 12 are connected).
It would be desirable to provide a method for designing a PCB that takes into account the effects of the trace lengths within the IC packages and the timing parameters of the IC packages (e.g., setup-and-hold time, clocked Q, etc.) in determining the trace lengths of the PCB bus. In cases where the speed of the PCB bus is limited by external factors, the speed of the PCB bus cannot be increased by optimizing the trace lengths of the PCB bus. In fact, increasing or decreasing a trace length by a particular amount may result in violating the setup and/or hold times of an IC. It would be desirable to provide a technique that would enable the range of the PCB bus trace lengths to be maximized without violating the setup and/or hold times.
Accordingly, a need exists for a method and apparatus for maximizing the range of trace lengths of the PCB bus without violating the setup and/or hold times of ICs communicating over the PCB bus.
The present invention provides a method and apparatus that enables the range of trace lengths of the bus of a mounting surface, such as a PCB, for example, to be maximized without violating setup and/or hold times. The method of the present invention utilizes information relating to certain timing parameters of the ICs and the package delays of the ICs to maximize the range of trace lengths of the PCB bus as a function of a selected clock offset. The clock offset is inserted into the global clock of the PCB bus to maximize the range of the PCB bus trace lengths. The apparatus of the present invention is a computer that performs the calculations needed to perform the method of the present invention. For example, the computer receives the information relating to the timing parameters and the package delays of the ICs and processes the information to determine the minimum and maximum trace lengths for each signal of the ICs. The computer then determines a clock offset that maximizes the difference between the minimum and maximum trace lengths.
The determinations that are made by the computer may instead be made by a human, as will be understood by those skilled in the art. However, it is desirable to use a computer for this purpose since calculations need to be performed for many signals. Once these determinations have been made, the packages are positioned and the signals routed so that the trace lengths fall between the minimum and maximum trace lengths. If necessary, the clock offset is adjusted so that none of the signals violate the setup time specification (maximum length) and the least number of signals violate the hold time specification (minimum length). If the hold time specification is violated, the trace length(s) associated with the signal(s) that violate the hold time specification will be lengthened to prevent the hold time specification from being violated.
USPTO Backgrounds
USPTO Backgrounds