1. Field of the Invention
The present invention relates to a method for forming a metal silicide layer in a semiconductor device. More particularly, the present invention relates to a method for forming an improved metal silicide layer in a semiconductor device having an N type metal oxide semiconductor (MOS) transistor and a P type MOS transistor.
2. Description of the Related Art
In a semiconductor device having rapid processing speed requirements, certain regions of the device, such as an active region and a gate region, are formed to include a metal silicide layer. The metal silicide layer operates to decrease the contact resistance of the region. The metal silicide layer may include a compound of metal and silicon, for example, such as titanium silicide (TiSi2), platinum silicide (PtSi2), lead silicide (PbSi2), cobalt silicide (CoSi2) or nickel silicide (NiSi2).
As the design rule of semiconductor device continues to be reduced, the metal silicide layer has become indispensable in the semiconductor device. Since the margin for forming the metal silicide layer becomes increasingly narrow as the design rule is reduced, the process for forming the metal silicide layer in the semiconductor device becomes more difficult. For example, when a cobalt silicide layer is formed in a semiconductor device having a critical dimension (CD) of about 90 nm, the margin for forming the cobalt silicide layer becomes extremely small. As a result, the cobalt silicide layer may not be stably formed on a gate electrode and source/drain regions of the device.
To overcome this limitation, it is necessary to broaden the area of the metal silicide layer formed on a gate structure. To accomplish this a method for concavely etching an upper surface of the gate structure has been developed. In another example, a method for increasing the exposed portion of the gate electrode formed in the metal silicide layer thereon has been developed. The exposed portion of the gate electrode is broadened by performing a space recess process on the gate structure. In this space recess process, an upper portion of a space disposed on a sidewall of the gate electrode is partially etched to expose the upper portion of the gate electrode, which includes polysilicon. The area of the metal silicide layer may also be broadened using the space recess process.
FIGS. 1A to 1E are cross-sectional views illustrating a conventional method for forming a cobalt silicide layer. FIG. 2 is a flow diagram illustrating a conventional method for forming a cobalt silicide layer.
Referring to FIG. 1A and FIG. 2, in step S11, a field isolation layer 115 is formed on a substrate 110 by a shallow trench isolation (STI) process so that an N type MOS in a first region and a P type MOS in a second region are formed on the substrate 110. An N type MOS structure and a P type MOS structure, each having a size on the nanometer scale, respectively, are formed in the first and second regions of the substrate 110.
First and second oxide layers 112 and 122 are formed on the first and second regions. Gate electrodes 130 and 140 of N type and P type MOS transistors are formed on the first and second oxide layers 112 and 122, respectively. Oxide layers 152 and 162, formed of middle temperature oxide (MTO), are provided on sidewalls of the N type and P type gate electrodes 130 and 140.
To form a cobalt silicide layer on the N type and P type gate electrodes 130 and 140, a recess process is performed. Lateral spacers 150 and 160, for example formed of silicon nitride, are formed on the sidewall oxide layers 152, 162. In step S12, upper portions of the spacers 150 and 160, respectively, are partially removed thereby exposing upper portions of the N type and P type gate electrodes 130 and 140. The recess process increases the exposed portions of the N type and P type gate electrodes 130 and 140, thereby broadening the contact area with a later-formed cobalt silicide layer formed on the exposed portions of the N type and P type gate electrodes 130 and 140.
Referring to FIG. 1B, in step S13, a photoresist pattern 120 is formed on the P type MOS transistor region, thereby protecting the P type MOS transistor region. Arsenic (As) ions are implanted into the N type MOS transistor region so that source/drain regions 142 are formed on the substrate 110 adjacent to the N type gate electrode 130. Here, while the N type gate electrode 130 has a small CD of below about 90 nm, arsenic ions have relatively a larger size and heavier weight than the CD of the N type gate electrode 130. Accordingly, when arsenic ions are implanted, the upper portion of the N type gate electrode 130 may be deformed into a dome shape. Also, when a high thermal process is performed for later forming the cobalt silicide layer, the cobalt silicide layer may be positioned adjacent to the spacer 150, causing mechanical stress between the spacer 150 and the applied to the cobalt silicide layer. Furthermore, voids may be formed in the cobalt silicide layer, thereby increasing the resistance of the cobalt silicide layer.
Referring to FIG. 1C, in step S14, the photoresist pattern 120 formed on the P type MOS transistor region is removed. A photoresist pattern 121 is formed on the N type MOS transistor region, thereby protecting the P type MOS transistor region. Boron (B) ions or gallium (Ga) ions are implanted into the P type MOS transistor region, thereby forming source/drain electrodes 142 adjacent to the P type gate electrode 140.
Referring to FIG. 1D, the photoresist pattern 121 formed on the N type MOS transistor region is removed. Cobalt is deposited on the N type and P type MOS transistor regions by a sputtering process to thereby form a cobalt layer 170. To prevent the resulting cobalt silicide from oxidizing, a titanium nitride (TiN) layer may be formed on the cobalt layer 170.
Referring to FIG. 1E and FIG. 2, in step S15, the cobalt layer 170 and the titanium nitride layer are treated through a rapid thermal process (RTP) so that a cobalt silicide layer 180 is formed on the N type and P type MOS transistor regions.
Remaining cobalt silicide layer and titanium nitride layer are removed using a rinsing solution including H2O2 and H2SO4.
In the above-mentioned conventional method for forming a cobalt silicide layer, when the spacer is over etched to a depth greater than about 300 Å, the silicon in the source/drain regions and the field isolation layer may be partially removed along with the spacer, resulting in increased leakage current.
To prevent the over-etching, when the spacer is etched to the depth of less about 300 Å, the cobalt layer may be stably formed. However, when the cobalt layer is treated through a successive RTP process, an agglomeration may be generated in the silicide layer formed on the P type MOS gate electrode, resulting in increased gate resistance. Since P type polysilicon doped with impurities is thermally more unstable than N type polysilicon doped with impurities, the agglomeration of the cobalt silicide may be readily generated in the P type structures, though under the same conditions.
As a result, the conventional method for forming a cobalt silicide layer by the aforementioned recess process does not apply well to highly-integrated semiconductor devices having a design rule of below approximately 90 nm. To overcome the above-mentioned problem, a method of forming a metal silicide layer using nickel silicide has been developed. However, the resulting nickel silicide layer has been found to be thermally unstable.
Also, when impurities such as arsenic ions are implanted into the N type MOS gate structure on the nanometerscale, the upper portion of the N type MOS gate structure may be deformed, resulting in electrical degradation in the gate structure. Furthermore, since the P type polysilicon doped with impurities in the P type gate structure has inferior thermal stability, the cobalt silicide may become agglomerated during the RTP.
USPTO Backgrounds
USPTO Backgrounds