(1) Field of the Invention
The present invention relates to the fabrication of integrated circuits, and more particularly to a method for making improved fuse structures on semiconductor integrated circuits such as on Random Access Memory (RAM) devices. This method and structure utilize an etch-stop layer to accurately remove the non-uniformly thick multilayer insulation over the fuse areas across the substrate. This allows for reliable and repeatable repair yields when fuses are opened to disable defective circuits and to replace them with redundant circuits, such as for enabling additional rows of memory cells on a RAM device.
(2) Description of the Prior Art
Advances in semiconductor processing technologies, such as high-resolution photolithography and anisotropic plasma etching, are dramatically reducing the feature sizes of semiconductor devices and increasing the device packing density. Unfortunately, as the density of the semiconductor devices increases and the number of discrete devices increases on the chip, the final product yield for many integrated circuit devices (chip yield) can decrease. For example, one circuit device that can experience this increase in yield loss with increased circuit elements is dynamic random access memory (DRAM) currently having 64 megabits of memory on a chip. After the year 2000 the number of memory cells is expected to increase further to about 1 to 4 gigabits, and high final product yield will be difficult to achieve without utilizing cell redundancy and repair yield methods.
One method of overcoming this lower yield on RAM devices is to provide additional rows of memory cells and fusing each row of cells. Currently lasers are used to routinely open connections (fuses) in the multimegabit RAMs, such as in DRAM or SRAM devices, to disable defective rows of memory cells and to modify the address decoder so that spare rows of memory cells are selected instead.
To better appreciate the problem associated with making and selectively opening the more conventional fuse, a schematic cross-sectional view of a fuse structure is depicted on substrate 10 in FIG. 1. Typically the fuse 14 is formed as part of a first polysilicon layer 14 at the same time the conductively doped polysilicon layer is patterned to form part of the semiconductor devices, such as the FET gate electrodes on device areas and the local interconnections on the field oxide regions 12. Only the fuse 14 is shown in FIG. 1 to simplify the drawing and discussion. The patterned first polysilicon layer 14 with the fuse area (also labeled 14) is then insulated with a first interpolysilicon oxide (IPO) layer 16, for example using a silicon oxide (SiO.sub.2) deposited by chemical vapor deposition (CVD). A conductively doped second polysilicon layer (not shown) is then patterned to form the next level of interconnections (such as bit lines for SRAM and DRAM devices), and a second IPO layer 20 is deposited, such as a CVD SiO.sub.2, as an insulating layer. Each of the IPO layers (layers 16 and 20) has contact openings (not shown) to provide interlevel electrical connections between conducting layers. When the semiconductor devices are completed, including the local polysilicon interconnections with fuses, the circuit integration is completed by forming a multilevel of metal interconnections. Four levels of metal are depicted in FIG. 1, but the number of metal layers varies between about 3 and 6, and is expected to increase further on future product. Each layer of patterned metal interconnections is formed by depositing metal layers, such as an aluminium/copper alloy, and patterned by plasma etching. Each patterned metal layer is insulated with an interlevel dielectric (ILD) layer in which via holes are etched and filled with metal (plugs). For example, as shown in FIG. 1, a first metal layer 22 is deposited and patterned to form the patterned first metal layer 22(M1). An ILD layer 24 is deposited and planarized in which via holes are etched and filled with metal plugs 26. In like fashion and repeating the process, a patterned second metal layer 32(M2) with ILD layer 34 and metal plugs 36 are formed, and a third patterned metal layer 42(M3) with an ILD layer 44 and via holes with metal plugs 46 are formed. After completing the metal interconnections with a patterned fourth metal layer 52(M4), the multilevel metallurgy is passivated using a silicon nitride 60, a spin-on glass 62, and a thicker silicon oxynitride layer 64.
To access the fuses 14, a patterned photoresist layer and plasma etching are used to form openings 2 (fuse windows), as depicted by the vertical arrows 4, to a controlled depth D in the passivation layers 64, 62, and 60, and in the thick multilayer of ILD layers 44, 34, 24, and 20 over the fuses 14. This opening 2 must be etched to an accurate depth over the fuse to reliably blow (open) the desired fuse, for example, by laser evaporation.
Unfortunately, because of the very thick multilayer of insulating layers, it is difficult to accurately etch the opening 2 to exactly control the thickness H of the remaining insulating layer (SiO.sub.2) over the fuse 14. For example, if the thickness of layer 16 is 4000 Angstroms, then variations in the ILD layers and the passivation layers can result in variation of +/-2600 Angstroms in the thickness of the oxide layer 16 in the opening 2 over the fuse 14. Further exacerbating the problem is the nonuniformity in the ILD layers across the substrate. For example, just a +/-5% variation in the overlying ILD insulating layers and passivation layers (about 8 micrometers) can result in a variation of +/-4000 Angstroms. This makes it very difficult to repeatedly and reliably blow open the required fuses across the substrate 10.
One method of forming fuses on high performance BiCMOS integrated circuits for programmable devices is described by Keller et al., U.S. Pat. No. 5,457,059. However, the method uses titanium/tungsten fuses for field programmable logic (FPL) and does not address the need for forming reliable and repeatable fuse structures for redundant circuits, such as SRAM and DRAM devices. Another reference for utilizing etch-stop layers to make via holes of various depths is described by Sandhu et al. in U.S. Pat. No. 5,258,096. A method for making buried and shallow contacts using an etch-stop layer is described by Rhodes et al. in U.S. Pat. No. 5,232,874. However, the method for making reliable fuse structures is not addressed.
There is still a strong need in the semiconductor industry to further improve the method for making reliable and repeatable fuse structures for improved repair yields on integrated circuits with redundant circuits, such as on DRAM and SRAM devices and the like.
USPTO Backgrounds
USPTO Backgrounds