Traditional charge pumps provide an integer multiple of the input alternating current (AC) voltage Vin (usually square-wave). A popular approach used to integrate the charge pumps relies on the silicon PN or Schottky barrier diodes voltage multiplier. Its two-phase variant is shown in FIG. 1. In fact, this circuit realizes a full-wave rectification and multiplication of two complementary inputs Vin and −Vin. In FIG. 1, the first direct current (DC) node Vin is delivered by the DC voltage Vin directly.
The main advantage of this configuration is the operation with two complementary phases. This decreases the output voltage ripple and allows for a decrease in the total capacitor area. In fact, the output node is continuously supplied by one of the top or bottom floating capacitors resulting in double output ripple frequency.
The low-value middle capacitors CMID are used only to filter the spikes during the phase transitions.
On the other hand, the operation of this charge pump involves the use of two serially connected diodes D1, D2 per stage that decreases the conversion efficiency.
When several multiplication stages are used, the diode voltage drops are multiplied accordingly.
Solutions with diode-connected MOS transistors replacing the passive diodes are encountered mainly for Dickson type charge pumps requiring, however, high-voltage capacitors. Such a Dickson type charge-pump is, for example, disclosed in the article of D. S. Hong, M. El-Gamal, “Low operating voltage and short settling time CMOS charge pump for MEMS applications,” in Proceeding of Circuits and Systems, 2003. ISCAS 2003 (incorporated by reference).
A solution allowing the implementation of active switches for a topology such as the one illustrated in FIG. 1, is disclosed in the article of A. Emira et al. “All-pMOS 50-V charge pump using low voltage capacitors,” IEEE Transactions on Industrial Electronics, Vol. 60, No. 10, 2013 (incorporated by reference).
This solution is based on an active level shifter chain that provides fast control signals for transistors' gates. In this solution, the level shifter chain is connected in parallel with the main charge pump. However, the complication in such design is to create reliable isolated (floating) level shifters operating at high voltage. This design approach is difficult namely because the high operation voltages (>10V) which requires careful N-well and P-well isolation and post-layout verification of the level shifters.
Another solution using active switches, such as MOS transistors, in a charge-pump is a Pelliconi cascade charge-pump architecture disclosed in the article of J-F. Richard, Y. Savaria, “High voltage charge pump using standard CMOS technology,” in Proceeding of Circuits and Systems, NEWCAS 2004 (incorporated by reference), in which the MOS transistors of the charge-pump stage are controlled by signals present at two control nodes of the charge-pump stage.
However, the use of these control signals can lead to an internal lock of the charge-pump due to the short cross-conduction of the complementary switches. This occurs namely for switches with very-low RON. Indeed, during the transitions of the clock signals, complementary MOS transistors may be turned-on simultaneously. And the simultaneous conduction of complementary switches slows the fall/rise edges of the signal, resulting in the discharge of the capacitors during the phase transitions.
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