In the microelectronics industry there is a continuing desire to electrically mount to substrates, such as printed circuit boards, increased lead-count, faster switching-speed VLSI (very large scale integration) integrated circuit (IC) devices by structures which reduce the cost of manufacture of electronic components. In the past, electronic devices were surface mounted to substrates by techniques such as individually wire bonding a device contact pad to a substrate contact pad. Tape Automated Bonding (TAB) was later developed to eliminate the need for individual wire bonding. In TAB a metallic layer is fabricated into a pattern of beam leads. The beam leads can be fabricated on a flexible dielectric film which holds the leads together, or in the absence of a dielectric film, the beam leads are held together by parts of the metallic layer which interconnect the beam leads, the interconnecting parts being removed subsequent to bonding the leads to an electronic device.
As the IC circuit density increases, generally the IC input/output (I/O) count increases, requiring an increased beam lead count for electrical connection thereto. Increased circuit count is generally achieved by a decrease in size of the component devices of the circuits. This size decrease generally results in increased circuit switching speed. Waveforms of circuits having fast switching speed are more susceptible to distortion from the signal line impedance than are waveforms of slower switching speed circuits.
One technique to attain a high number of electrical interconnections to an IC and at the same time provide some impedance adjustment to avoid waveform distortion is to mount the IC onto a multilevel ceramic packaging substrate which has a plurality of metal layers. Some of these layers can be used to reduce the problem of waveform distortion. The ceramic substrate can then be mounted onto a printed circuit board.
Although the ceramic substrate may solve some of these problems, these substrates are very costly to fabricate. In addition, the automated bonding capability provided by a TAB-type tape fabrication technique is lost. Ceramic substrates have to be individually handled for bonding to IC and printed circuit boards.
Alternatively, a multilevel metal TAB tape can be used for bonding to an IC.
U.S. Pat. No. 4,064,552 to Angelucci et al. shows a multilevel metal TAB-type tape structure which is fabricated as shown in FIG. 5 thereof. Two tapes are used. Each tape has a single metal layer on a dielectric layer. The sides of the dielectric layer of each tape without a metal layer are glued together to form a single tape having a composite dielectric layer with a metal pattern on both sides. The composite dielectric layer is formed from the two dielectric layers of the individual tapes and the glue there between. FIG. 1 of Angelucci et al. shows a semiconductor chip 18 bonded to the inner ends of flexible conductive fingers 14 of one metal layer. The two metallurgical layers are electrically interconnected as shown in FIG. 4 of Angelucci et al. Conductor 94 on one side of the two-level metal tape is connected through connection apertures 90 and 90', in the dielectric layers of each tape, to conductor 92 on the opposite side of the composite dielectric layer 80. This approach requires the use of large apertures through the dielectric layers to electrically interconnect a metal conductor on one surface of the composite dielectric to another conductor on the other surface of the composite dielectric.
U.S. Pat. No. 4,538,210 to Schaller shows a circuit board having a window for receiving an electronic device. The device is in the form of a plate having electrical contact locations on both sides and along the edge of the plate. The circuit board has elastic holding tabs of at least two different lengths which project into the window. The tabs form the ends of conductive rows on the circuit board. Upon pushing the plate through the window, the short holding tabs snap back and the plate becomes clamped to the circuit board by the holding tabs. The tabs additionally provide electrical connections between conductor runs of the circuit board and contacts on the plate. There are four variations of this snap coupling shown in FIG. 2 to FIG. 5 of Schaller. In each, the ends of the snap couplings lie in two separate planes in order to provide the clamping feature. The electrical connection between the tabs and plate contacts is by pressure.
An alternative approach is to fabricate a multilevel metal TAB tape using conductive vias or through-holes in the dielectric layers to electrically interconnect a conductor on one metallic layer to an adjacent metal layer. All metal layers are thereby electrically connected to a single metal layer which has beam leads which project inwardly into an aperture in the dielectric layers. The beam leads project inwardly from one metal layer. An IC can be bonded by standard bonding techniques to the inner ends of the beam leads from a single layer. Vias have certain inherent problems. If a via is used to electrically connect a conductor on one layer to a conductor on another layer, there is a statistical variation in the location of the conductors relative to the position of the via. The statistical variation arises from the processes and tools used to fabricate the structures. Because of this variation in alignment, there can be a minimal overlap of the via and conductor which results in a high contact resistance between the conductor and via. To avoid this, either the via or conductor has to be made wider. If the conductor is made wider space is consumed and, therefore, a smaller number of beam leads can be fabricated to project into the aperture for electrical connection to the IC. If the via is made wider, to avoid the via shorting to adjacent beam leads, the spacing between adjacent beam leads has to be increased which also results in fewer beam leads for connection to the IC. In addition, the region of electrical connection of the beam lead to via provides a location where residues of processing can accumulate, resulting in a high contact resistance, an electrical open, or a potential for a reliability failure, all of which result in a reduced manufacturing yield of the multilevel beam lead structure. Reduced yield increases the cost of the fabricated structures.
The multilevel metal structures of the present invention avoid the problems associated with the use of vias. Quite surprisingly, it has been found that beam leads can project inwardly from more than one metallization layer in cantilevered fashion into an aperture and can be formed so that the inner ends of the leads lie in substantially the same plane for bonding to contact locations on an IC. The forming operation can be done simultaneously with bonding of the inner ends to the IC pads as part of an automated process when the multilayered structures are fabricated on a TAB-type tape. The via-free multilayered structure permits electrical connection to state-of-the-art high density VLSI IC devices having a large number of I/O connectors. Also the via-free structures have a higher degree of reliability than structures which use vias.
The multilevel structures of the present invention differ from the structures of Angelucci et al. which describes structures having beam leads projecting into an aperture from one metal layer for electrical connection to an IC and which uses large apertures to electrically connect a second metal layer to the first metal layer.
The multilevel structures of the present invention differ from the structures of Schaller which describes two metal layer structures from which project resilient snap couplings whose ends are not in a single plane, for electrically connecting to and for support of a plate.
Therefore it is an object of this invention to provide improved multilevel IC packaging structures used to electrically interconnect an electronic device to a substrate wherein the structure has more than one metallurgical layer from which beam leads project inwardly toward and in cantilevered fashion over an aperture in the dielectric layers of the structure. The inner ends of the beam leads lie substantially in one plane for bonding to contact locations on the electronic device.
It is another object of this invention to provide an improved TAB tape having a plurality of these multilevel metal structures useful for a low-cost automated process for electrically interconnecting a plurality of electronic devices to a substrate.
Further improvement in the impedance characteristics of a multilayer metal packaging structure can be achieved by varying the dielectric thickness between conductors on adjacent metallization layers.
It is another object of this invention to provide improved multilayered IC packaging structures having variable dielectric thickness to electrically interconnect an electronic device to a substrate.
Further improvement in the impedance characteristics of a multilayered metal packaging structure can be achieved by symmetrically arranging signal lines between power and ground lines.
It is another object of this invention to provide improved multilayered IC packaging structures having improved impedance characteristics by symmetrically arranging signal lines between power and ground lines.
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