1. Field of the Invention
The present invention relates to a test pattern generating circuit and a semiconductor memory device incorporating same. More particularly, the invention relates to a test pattern generating circuit providing a variety of test patterns facilitating more precise testing and a semiconductor memory device incorporating same.
2. Description of the Related Art
As the operating speed of semiconductor memory devices increases generally, the frequency of system clocks operating within such devices also increases. Further data processing techniques designed to transmit a greater number of data bits per unit time at a defined clock frequency are also becoming more commonly used in semiconductor memory devices. These techniques include, as examples, double data rate (DDR), quad data rate (QDR) and octal data rate (ODR) approaches to data processing. Unfortunately, it is now common for test equipment used to check the operation of semiconductor memory devices following fabrication to actually run at a slower speed than the data transmission speed of the devices. As a result, the practical capabilities of conventional test equipment relative to contemporary high-speed semiconductor memory devices is rather restricted.
One complicating factor in the testing of high-speed semiconductor memory devices using relatively low-speed test equipment is the fact that actual data transmission is faster than the frequency of system clock within these devices. That is, test equipment must provide test patterns to a semiconductor memory device being tested at a rate 2 to 8 times (or even 16 times) faster than the device system clock due to the use of such techniques as DDR, QDR and ODR. Much of the available test equipment is simply unable to provide test patterns at this rate.
Examples of test patterns being generated for a high-speed semiconductor memory device using conventional low-speed test equipment will now be described with reference to the attached drawings.
Figures (FIGS.) 1 and 2 are tables showing examples of test patterns generated by conventional test equipment. FIG. 1 shows an example when the test equipment runs at a clock speed of 200 megahertz (MHz), but data input/output speeds for a semiconductor memory device being tested is 800 MHz.
The test patterns provided to a memory array of the semiconductor memory device are generated using an externally provided test signal. For example, a first test pattern having 2 bits per clock cycle of the 200 MHz system clock is input, and a second test pattern having 8 bits per clock cycle of the operation clock is generated in response to the first test signal.
The generated test pattern is loaded into a register and transmitted through an input/output pin of the semiconductor memory device. For example, the test pattern ‘00001111’ is transmitted to the memory array through input/output pin DQ0. Then, the test pattern is shifted by one bit, and the test pattern ‘10000111’ is transmitted to the memory array through input/output pin DQ1. Similarly, the test pattern ‘00011110’ is transmitted to the memory array through input/output pin DQ7.
FIG. 2 is a table showing another example of test patterns generated by conventional test equipment. Referring to FIG. 2, a test signal having 2 bits per cycle of the 200 MHz operation clock is provided, and an 8-bit test pattern is generated in response to the test signal. For example, if a 2-bit test pattern is formed of ‘Early=0’/‘Late=1’, an 8-bit pattern ‘01010101’ is formed by repeating the 2-bit pattern, and the generated test pattern is transmitted to the memory unit. Similarly, if the 2-bit test pattern is formed of ‘Early=1’/‘Late=1’, an 8-bit pattern ‘11111111’ is formed.
In view of the foregoing exemplary accommodations, precise testing can not be performed due to the small range of possible test patterns capable of being transmitted to the memory array. All possible test patterns generated by the conventional test equipment correspond to test signals having a fixed identical pattern length. Such a range of possible test patterns is insufficient to fully test contemporary and emerging semiconductor memory devices.
USPTO Backgrounds
USPTO Backgrounds