(1) Field of the Invention
The present invention relates to an associative memory device capable of determining by the contents of information, addresses into which the information has been stored to prevent the same information from being stored in different addresses of the associative memory device as well as capable of performing high speed access to the information.
(2) Description of the Prior Art
In recent computers, there is a tendency that high speed operation of the computers is required in order to improve the processing capability, and this in turn necessitates a high speed operation of memories, as well. To this end, high speed cache memories are being widely used as an auxiliary memory of a main memory although they have a smaller memory capacity respectively compared with the main memory having a large capacity but a low speed operation.
Since only information which is frequently used is stored in this cache memory, when a processor has access to the main memory, the information thus accessed is to be stored in the cache memory at random. It is therefore necessary to determine in which address among addresses of the cache memory the information demanded by the processor is being stored and to obtain access thereto.
In processing these cache memories, there is used, for instance, an associative memory wherein an address in which particular information has been stored, can be known from the contents of the memory. It is constructed in such a manner that addresses of the cache memory are related to the addresses of the associative memory (having the same memory capacity as that of the cache memory) where the information has been stored, and the addresses of the information in the cache memory are stored into the addresses of the associative memory which correspond to those of the cache memory.
With this construction, the associative memory is accessed by each of the addresses of the main memory where the information has been stored, i.e., by the information to be stored in the associative memory in order to obtain necessary information for the processor. In this case, when it is found that the information has been stored in the associative memory, a particular address in the associative memory can be determined by the associative memory function. As a result, when access to the cache memory is carried out by the address thus determined, the information necessary for the processor can be obtained from the cache memory at high speed.
However, there are often such cases that the same information might be stored in different addresses in the associative memory. Consequently, when retrieval operation of the information stored in the different addresses is carried out in this case, a plurality of addresses corresponding to the same information are to be produced. Therefore, when such a case as described above occurs in the associative memory used in the processing of the cache memory, it becomes no longer possible to access the cache memory.
In order to prevent the drawbacks or disadvantages described above, when a plurality of occurrences of the same information are determined by detecting the output information in the reading-out of the information from, for instance, the associative memory, it becomes necessary to stop the subsequent operation or to take some measures for producing the selected information in accordance with a predetermined priority order preliminarily set up. As a result, it also becomes necessary to provide a specific means for that operation as well as resulting in a problem that a high speed performance of the cache memory is lowered by the operation time necessary to provide a specific means for that operation as well as resulting in a problem that a high speed performance of the cache memory is lowered by the operation time necessary for operating the specific means.
USPTO Backgrounds
USPTO Backgrounds