1. Field of the Invention
The present invention relates generally to computer network communications and more particularly to methods and systems that allow analog transversal FIR filters to operate at ultra high frequencies. More particularly, the present invention relates to a method and a system that allows the use of double-edge clocking to reduce the frequency of operation of a transversal FIR filter whose general functionality can be used to implement a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). The invention is particularly relevant for systems that operate at 10 Gb/s or above, where the reduction in operating frequency of a sub-block will result in reduced power consumption.
2. Description of Related Art
A standard transversal FIR filter includes a set of latches, a set of respective multiplication elements, and a summing node. The order of the filter defines that number of latches contained in the data FIFO, where each latch output can be used to drive a co-efficient value/gain required for the FIR filter functionality to be realized.
The latches of the transversal filter all operate using the same clock, referred to as the High Speed Clock, which has a period T which is equal to the Unit Interval (UI) of the serial data stream. In practical applications, the delay element is implemented using a Flip-Flop that samples data present on an input on a given clock edge, and holds the data value on an output for the duration of a clock period.
In certain cases, it is advantageous to reduce the operating frequency of the clock signal for reasons of technical feasibility or power consumption optimization. It is possible to split the delay elements in the transversal filter into two groups, one of which latches data on the rising edge of the clock signal, the other latching data on the falling edge of the clock signal. This will allow a High Speed clock signal with a period T which is effectively twice the duration of a UI, it also implies that the data sample is held by the delay element for two UI.
In order to improve Bit Error Rate performance in communications systems, a transversal FIR filter is sometimes used in the receiver or the transmitter to correct for InterSymbol Interference (ISI). An FFE is commonly used in a transmitter, while a receiver will generally contain a DFE.
An FFE is an extension of a standard serializer transmit block, where data bits are shifted through delay elements to be transmitted one at a time, but with a partial contribution from other bits contained in the delay structure. An FFE serial transmitter includes a set of delay elements, a set of multipliers, and a summing node. The delay elements all operate using the same High Speed clock signal, and shift data forward on only one edge (usually rising) of the clock. An FFE requires that the output of a delay element be held for no more than one UI. Thus, the period T of the High Speed clock is generally equal to one UI for proper functionality.
A DFE receiver block is an extension of a standard serial bit receiver block. A DFE receiver block includes a slicer, a set of delay elements, a set of multipliers, and a summing node. The slicer and delay elements all operate using the same High Speed clock signal, and sample data on only one edge (usually rising) of the clock. A DFE requires that the data sample be held at the output of a delay element for not more than one UI. Thus, in order for a DFE receiver block to function correctly, the period T of the High Speed clock signal must be equal to the Unit Interval of the incoming data stream.
In both the case of the FFE and DFE, increasing the High Speed clock period by a factor of two would cause a functional failure. Therefore, there is a need to have an efficient method and system that will allow a DFE to function using a double edge clocking scheme, so that the frequency of operation of the transversal filter in an FFE or DEE can be reduced.
USPTO Backgrounds
USPTO Backgrounds