Semiconductor memory devices may be categorized as volatile memory devices and non-volatile memory devices depending on whether data can be conserved or not when a power supply is cut off. Dynamic random access memory (D-RAM) devises and static random access memory (S-RAM) devices are volatile memory devices, and flash memory devices are examples of non-volatile memory devices. Typical memory devices may indicate logic “0” or “1” according to the presence of stored charges.
A volatile D-RAM may require periodic refresh operations and relatively high capacity for storing charges. There have thus been efforts to improve memory cell capacitances of DRAM devices. For example, surfaces of memory cell capacitor electrodes may be increased to increase capacitance, but the increase of the capacitor electrode surface area may be an obstacle to improving device integration densities.
A conventional flash memory cell may include a gate insulating layer, a floating gate, a dielectric layer and a control gate that are sequentially stacked on a semiconductor substrate. Writing and/or erasing data in a flash memory cell may include tunneling electrons through a gate insulating layer, and an operating voltage higher than a power voltage may need to be provided. A flash memory device may require a booster circuit for applying a required voltage during write and/or erase operations.
Accordingly, new memory devices having non-volatile and random access characteristics and simple structures have been developed. An example of such a new memory device is a phase-changeable memory device. A phase-changeable memory device may use a phase changeable material that changes its crystalline structure depending on heat provided thereto. Conventionally, the phase-changeable material may be a chalcogen compound including germanium (Ge), antimony (Sb) and/or tellurium (Te) (i.e., GST or Ge—Sb—Te). Phase-changeable materials are also discussed in U.S. Pat. No. 5,933,365 (to Klersy et al., entitled “Memory Element With Energy Control Mechanism”, issued Aug. 3, 1999), the disclosure of which is hereby incorporated herein in its entirety by reference.
When a current is applied to the phase-changeable material layer to heat the phase-changeable material, a crystal state of a predetermined portion of the GST may change depending on the amount and/or duration of the current provided. In this case, a crystalline state may have a relatively low resistance and an amorphous state may have a high resistance. The resistance may vary according to the state of crystal, such that logical information can be determined by detecting differences of the resistance.
If GST is heated up to a melting point (about 610° C.) by applying a relatively high current flux to the GST for a relatively short time (1-10 ns) and then quenched quickly in a short time (1 ns or less), the heated portion of the GST may take an amorphous state (i.e., a reset state). If GST is heated up to maintain a crystalline temperature (about 450° C.) lower than the melting point temperature by applying a relatively low current flux for a relatively long time (i.e., about 30-50 ns) and cooled down, the heated portion of GST may take a crystalline state (a set state). The current flux for programming is thus related to a structure of the phase-changeable memory cell.
FIG. 1 is a cross-sectional view showing a phase-changeable memory cell disclosed in U.S. Pat. No. 5,933,365. In FIG. 1, reference numbers 11 and 17 indicate insulating layers, reference numbers 13 and 23 indicate electrical contact layers, reference number 19 indicates a phase-changeable layer, and reference numbers 15 and 21 indicate heating layers for providing heat for the phase-changeable layer. As illustrated in FIG. 1, a small hole is formed in the insulating layer 17 to expose the heating layer 15. The phase-changeable layer 19 and the heating layer 15 are in contact with each other through the small hole. Accordingly, when heat is applied to the phase-changeable material layer 19 through the heating layer 15, a crystalline state of a portion of the phase-changeable layer contacting the heating layer 15 in the hole may change. That is, a crystalline state of the phase-changeable layer at a contacting area between the heating layer 15 and the phase-changeable layer 19 may change.
In the structure discussed above, heat provided for the phase-changeable layer 19 through the heating layer 15 may also diffuse through the heating layer 15, because the heating layer 15 has a widely spreading plate-shape. Current flux for programming may thus become high.
Accordingly, the heating layer may be provided in a plug-shape penetrating an insulating layer to reduce heat diffusion. FIG. 2 is a cross sectional view showing a phase-changeable memory device with the plug-shaped heating layer. In FIG. 2, reference number 11′ indicates an insulating layer, reference number 15′ indicates a plug-shaped lower electrode for heating a phase-changeable layer, reference number 19′ indicates a phase-changeable layer, and reference number 23′ indicates a second electrode.
Referring to FIG. 2, a plug-shaped lower electrode 15′ provides heat for a phase-changeable layer 19′ different from the plate-shaped heating layer 15 illustrated in FIG. 1. An intensity of the current provided to the phase-changeable layer 19′ by the plug-shaped lower electrode 15′ may increase and heat diffusion may decrease as compared with a plate-shaped heating layer. In the plug-shaped lower electrode structure, however, the phase-changeable layer 19′ and the second electrode 23′ may have a same diameter as was the case in the phase-changeable memory device of FIG. 1. Therefore, a relatively high program currently may still be required.
USPTO Backgrounds
USPTO Backgrounds