1. Field of the Invention
The present invention relates to a semiconductor device capable of being suitably used for a surface-mounted package such as a TCP (tape carrier package) where a semiconductor chip is mounted on a carrier tape, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, with improving performance and decreasing size and weight of electronic apparatuses, LSI (large scale integration) packages are required to have more pins, finer pitches, smaller sizes and smaller thicknesses. As a semiconductor device highly likely to realize these requirements, a tape carrier package (abbreviated as TCP) which is a surface-mounted semiconductor device is frequently used. To further reduce the thickness of this semiconductor device, it is necessary to reduce the thickness of the semiconductor chip mounted on the chip substrate. Most semiconductor devices are used as liquid crystal driving circuits also called liquid panel drivers, and are directly connected to liquid crystal panels. By reducing the thickness of such semiconductor devices, the thickness of the liquid crystal panels on which the semiconductor devices are mounted can be reduced, and therefore, the liquid crystal panels being reduced in thickness are mounted. For example, the thickness of electronic apparatuses such as portable personal computers also called notebook computers and portable word processors can be also reduced.
In reducing the thickness of the semiconductor devices, for a semiconductor chip with a low aspect ratio between the chip length and the chip width where the chip width is not less than 1.5 mm and the chip length is not more than 16 mm, the semiconductor chip is ground until the thickness thereof becomes approximately 400 xcexcm to manufacture a semiconductor device. In connection with grinding a semiconductor chip having such a low aspect ratio, in preprocessing for formation of the semiconductor chips from a semiconductor wafer on one surface of which are formed semiconductor elements, another surface of the wafer, opposite to the one surface, is ground to reduce the thickness of the wafer to approximately 400 xcexcm, and thereafter using the semiconductor wafer having a thickness of approximately 400 xcexcm, assembly is performed without applying any processing to the ground surface to manufacture the semiconductor device.
FIG. 8 is a cross-sectional view showing a typical prior art semiconductor device 1. In the above-described semiconductor device 1, no die pad is provided, but a semiconductor chip 3 elongated in a direction perpendicular to the plane of FIG. 8 is only covered with an encapsulating resin 2 and no mechanical reinforcement is provided. For this reason, the semiconductor chip 3 itself is responsible for the overall mechanical strength of the semiconductor device 1. Therefore, thickness reduction of the semiconductor chip 3 reduces the mechanical strength of the semiconductor device 1. The semiconductor device 1 tends to increase in the chip length in the direction of the length perpendicular to the plane of FIG. 8 like an SST (super slim TCP). The chip length is, for example, approximately 20 mm. The semiconductor chip 3 tends to decrease in the width in the horizontal direction of FIG. 8 conversely to the length thereof. The chip width is, for example, not more than 1 mm. Thus, the mechanical strength of the semiconductor chip 3 tends to decrease.
The semiconductor chip 3 has an input side wiring 4 and an output side wiring 5, and is connected to an inner lead 7 of a carrier tape 6 made of a polyimide base material by inner lead bonding (abbreviated as ILB). The input side wiring 4 and the output side wiring 5 are covered with solder resists 8 and 9. A bump 11 is formed at the terminal of a surface 10 of the semiconductor chip 3 where semiconductor elements are formed. An end of the inner lead 7 is connected to the bump 11. The semiconductor chip 3 has grinding scratches 14 including cracks 13 caused by grinding for flattening the semiconductor wafer, on another surface 12 opposite to the surface 10 where the semiconductor elements are formed, and has dicing scratches 16 of side surfaces 15 of the chip caused by dicing the semiconductor wafer.
When the width of the semiconductor chip 3 is not less than 1.5 mm where the mechanical strength of the semiconductor chip 3 is comparatively high, grinding of the surface 12 causes no problem of strength. However, when the width is approximately 1.0 mm, chip cracking occurs when the semiconductor device 1 is assembled and when the semiconductor device 1 is mounted on the mounting substrate of an electronic apparatus. With respect to such cracking of the chip of the semiconductor device 1, the inventor of this application has verified that in addition to the reduction in mechanical strength due to the insufficient cross section of the semiconductor chip 3 itself because of the grinding of the surface 12, the grinding scratches 14 caused by grinding and the dicing scratches 16 caused in the dicing process are main factors of the reduction in the mechanical strength of the semiconductor chip 3.
When the mechanical strength of the semiconductor chip 3 is low as described above, chip cracking occurs in the ILB process including a process in which an external force due to contact with another semiconductor chip acts on the semiconductor chip 3 in the assembling process, and in the marking process. Moreover, when the semiconductor device 1 is mounted on the mounting substrate, the semiconductor device 1 where the semiconductor chip 3 having been ground is mounted cracks with a slight external force, so that the electronic apparatus does not function.
FIG. 9 is a cross-sectional view showing the structure for measuring the mechanical strength of the semiconductor device 1. In the measurement of the mechanical strength of the semiconductor chip 3, the semiconductor device 1 in which the semiconductor chip 3 was ground to a thickness of 400 xcexcm and the grinding scratches 14 were formed on the surface 12 of the semiconductor chip 3 with a width of 1.2 mm in a direction (horizontal direction of FIG. 9) vertical to the direction of the chip length was fixed so that both ends in the direction of the width of the semiconductor chip 3 were supported by a stage 17, and the central part in the direction of the width of the semiconductor chip 3 was pressed by a jig 18 from above. The mechanical strength of the semiconductor chip 3 was only 1.47 N/cm (=150 gf/cm). The inventor of this application has verified that when 3"sgr" is added, the semiconductor chip can crack with a pressure F=0N.
FIGS. 10A to 10C are views of assistance in explaining the difference in grinding scratches among the positions of cutting of the semiconductor chip 3 from a semiconductor wafer 19. FIG. 10A is a plan view showing the semiconductor wafer 19 having been surface-ground. FIG. 10B is a perspective view showing grinding scratches 14a and dicing scratches 16a when a semiconductor chip 3a cut from a first area 20 of the semiconductor wafer 19 is mounted on a chip substrate 6. FIG. 10C is a perspective view showing grinding scratches 14b and dicing scratches 16b when a semiconductor chip 3b cut from a second area 21 of the semiconductor wafer 19 is mounted on the chip substrate 6.
The grinding scratches 14 formed after the grinding of the surface 12 of the semiconductor wafer 19 are spiral as shown in FIG. 10A, and the direction of the grinding scratches 14 formed on the surface 12 of the semiconductor chip 3 differs according to the cutting position on the semiconductor wafer 19. When the semiconductor chip 3a cut by dicing from the first area, represented by reference numeral 20, of the semiconductor wafer 19 shown in FIG. 10A is assembled on the chip substrate 6 without any processing being performed after the surface grinding, as shown in FIG. 10B, the grinding scratches 14a are formed on the surface 12 of the semiconductor chip 3a in a direction substantially parallel to the direction of the length of the semiconductor chip 3a. 
When the semiconductor chip 3b cut by dicing from the second area, represented by reference numeral 21, of the semiconductor wafer 19 shown in FIG. 10A is assembled on the chip substrate 6 without any processing being performed after the surface grinding, as shown in FIG. 10C, the grinding scratches 14b are formed on the surface 12 of the semiconductor chip 3b in a direction substantially perpendicular to the direction of the length of the semiconductor chip 3b. 
The inventor of this application has verified that the grinding scratches 14b formed in the direction substantially perpendicular to the direction of the length of the semiconductor chip 3b as shown in FIG. 10C particularly significantly reduces the mechanical strength of the semiconductor chip 3b. The grinding scratches 14a formed in the direction substantially parallel to the direction of the length of the semiconductor chip 3a as shown in FIG. 10B does not significantly reduce the mechanical strength of the semiconductor chip 3a. 
As described above, factors responsible for the reduction in the mechanical strength of the semiconductor chip 3 are the grinding scratches 14 and the dicing scratches 16, and it has been found that the cracks 13 caused in grooves between scratches are a significant cause.
As described above, although the prior art is effective in reducing the thickness of the semiconductor device 1 by the grinding of the semiconductor chip 3 to thereby reduce the thickness of the liquid crystal panel using the semiconductor device 1, the mechanical strength of the semiconductor device 1 is reduced. For this reason, in mounting the semiconductor device 1 on various electronic apparatuses such as a liquid crystal panel, handling is extremely difficult because of action of an external impactive force at the time of conveyance and supply of the semiconductor device 1 and the generation of internal stress at the time of mounting onto the substrate, and it is desired to solve such a problem.
An object of the invention is to provide a semiconductor device having a semiconductor chip or semiconductor-chip-carrying package part which is reduced in thickness and increased in mechanical strength, and a method of manufacturing the same.
The invention provides a semiconductor device comprising a semiconductor substrate including a semiconductor element formed on a first surface thereof, wherein the semiconductor substrate is reduced in thickness by grinding a second surface thereof, opposite to the first surface, grinding scratches of the second surface caused by the grinding are removed to smooth the second surface of the semiconductor substrate.
The invention provides a method of manufacturing a semiconductor device comprising a semiconductor substrate including a semiconductor element formed on a first surface thereof, comprising the steps of grinding a second surface of the semiconductor substrate, opposite to the first surface, to reduce the semiconductor substrate in thickness; and removing grinding scratches of the second surface caused by the grinding to smooth the second surface of the semiconductor substrate.
According to the invention, by removing the grinding scratches on the second surface of the semiconductor substrate which is a semiconductor wafer or semiconductor chip having a semiconductor element on the first surface thereof, which element is formed through a diffusing process or the like, the semiconductor substrate is reduced in thickness and increased in mechanical strength, with the result that cracking does not occur even when an external force acts on the semiconductor substrate. The semiconductor substrate may be either a semiconductor wafer or a semiconductor chip obtained by dicing the semiconductor wafer. By using a semiconductor substrate simultaneously solving two contradictory problems of the reduction in thickness and the enhancement in mechanical strength, a package part reduced in thickness and enhanced in mechanical strength can be obtained as an end product.
In the invention it is preferable that the grinding scratches caused by the grinding of the second surface are removed by at least any one of etching, melting and chemical mechanical polish (CMP) surface treatment processes.
According to the invention, by using one or more of relatively frequently used known surface treatment technologies such as etching, melting and CMP, the second surface of the semiconductor substrate can be easily and stably smoothed.
In the invention it is preferable that the semiconductor substrate having the smoothed second surface has a thickness of 40 to 400 xcexcm.
According to the invention, the thickness of the semiconductor substrate having the smoothed second surface is selected to be 40 to 400 xcexcm, which is a significantly reduced thickness compared to an original thickness of the semiconductor substrate without deteriorating the mechanical strength required of a package part carrying a semiconductor chip comprising the semiconductor substrate.
In the invention it is preferable that the semiconductor substrate is a semiconductor chip which is formed by dicing, and side surfaces of the semiconductor chip are smoothed by removing dicing scratches formed thereon by the dicing.
According to the invention, since not only the grinding scratches on the second surface of the semiconductor substrate but also the dicing scratches on the side surfaces thereof are removed, the mechanical strength can be enhanced with higher reliability than in the case where only the grinding scratches are removed.
In the invention it is preferable that a terminal of the semiconductor element is connected to a wiring formed on a carrier tape by inner lead bonding.
According to the invention, since the semiconductor chip where the grinding scratches on the second surface are removed or the dicing scratches on the side surfaces are additionally removed is connected to the carrier tape by inner lead bonding, no crack due to a mechanical external force occurs in the semiconductor chip at the time of inner lead bonding. This improves the yield, so that a thinner package part with high reliability can be obtained.
In the invention it is preferable that the semiconductor chip is bonded to the carrier tape by encapsulation with resin.
According to the invention, by bonding the semiconductor chip to the carrier tape by encapsulation with resin, the moisture resistance between the semiconductor chip and the carrier tape is improved and the impact resistance is improved, so that the mechanical strength can be further enhanced.
In the invention it is preferable that the semiconductor element is a liquid crystal driving circuit.
In the method of manufacturing a semiconductor device of the invention it is preferable that in the case where the grinding scratches are removed by a etching surface treatment process, a depth of etching is selected to be not less than 3 xcexcm and not more than 50 xcexcm.
According to the invention, since the depth of etching of the second surface of the semiconductor wafer or the semiconductor chip is selected to be not less than 3 xcexcm and not more than 50 xcexcm, the grinding scratches on the second surface can be removed with reliability without the mechanical strength being reduced more than necessary.
In the method of manufacturing a semiconductor device it is preferable that in the case where an etching surface treatment process is selected to remove the grinding scratches, an etchant is supplied to the second surface by spraying.
According to the invention, since the etchant is supplied by spraying to the second surface of the semiconductor chip having not been etched yet, only a part of the semiconductor chip that requires etching can be removed by the etching surface treatment process with reliability without the need for much etchant compared to a case where the semiconductor chip is soaked, so that the cost can be reduced.
In the method of manufacturing a semiconductor device it is preferable that in the case where a melting surface treatment process is selected to remove the grinding scratches, a depth of melting is selected to be not less than 3 xcexcm and not more than 15 xcexcm.
According to the invention, since the depth of melting of the semiconductor chip is selected to be not less than 3 xcexcm and not more than 15 xcexcm, the grinding scratches of the semiconductor chip can be removed with higher reliability.
The invention provides a method of manufacturing a semiconductor device comprising a semiconductor wafer including semiconductor elements formed on a first surface thereof, comprising the steps of grinding a second surface opposite to the first surface to reduce the semiconductor wafer to a predetermined thickness, thereafter coating the first surface with a protective film which is resistant to an etchant for use in first and second etching surface treatment processes to be performed later, removing grinding scratches caused by the grinding by the first etching, covering the second surface of the semiconductor wafer the first surface of which is coated with the protective film, with a dicing tape which is resistant to the etchant, to dice the semiconductor wafer, and thereafter removing dicing scratches caused by the dicing, by the second etching surface treatment process.
According to the invention, since the dicing scratches can be removed by etching after the grinding scratches on the second surface of the semiconductor wafer are removed by etching, a semiconductor chip can be obtained in which the second surface and the side surfaces are smoothed without damaging the semiconductor element formed on the first surface of the semiconductor wafer or the semiconductor chip.
The invention provides a method of manufacturing a semiconductor device comprising the steps of bonding a protective tape which is resistant to an etchant, directly or with a resist in between, to a first surface of a semiconductor wafer on which surface semiconductor elements are formed; grinding a second surface of the semiconductor wafer to drop the semiconductor wafer to a predetermined thickness; and removing grinding scratches caused by the grinding, by etching.
According to the invention, even when the second surface is ground in the state of the semiconductor wafer, since the semiconductor element formed on the first surface of the semiconductor wafer is covered with the protective tape, the etchant is prevented from adhering to the semiconductor element exposed out of the surface, so that the semiconductor element can be protected.
The invention provides a method of manufacturing a semiconductor device comprising the steps of dicing a semiconductor wafer including semiconductor elements formed on a first surface thereof so as to be separated into a plurality of elongated semiconductor chips; and grinding a second surface of the semiconductor wafer separated into the semiconductor chips to thereby reduce the semiconductor chips in thickness, wherein the grinding is performed in a direction substantially parallel to a longitudinal direction of each semiconductor chip; and removing grinding scratches of the second surface caused by the grinding to smooth the second surface.
According to the invention, since the grinding is carried out along the longer side of each semiconductor chip, the grinding scratches can be formed substantially parallel to the direction of the longer side of each semiconductor chip, with the result that all the semiconductor chips have a uniform mechanical strength for cracking. Consequently, more stable crack strength distribution can be obtained. Since the mechanical strength for cracking can be significantly enhanced compared to a case where the grinding scratches are formed substantially parallel to the direction of the shorter side of each semiconductor chip, the reliability and the yield can be improved.
USPTO Backgrounds
USPTO Backgrounds