1. Field of the Invention
The present invention relates to a high integrated Bi-CMOS logic circuit using bipolar transistors and MOS transistors to perform a logic operation, and more specifically to a Bi-CMOS logic circuit configured as a NOR gate and NAND gate.
2. Description of the Prior Art
In general, the widely known logic symbol and truth table of NOR gate and NAND gate are as illustrated in FIG. 1. FIGS. 1 (a) and (b) show NOR gates having two and three input terminals, respectively. FIGS. 1 (c) and (d) show NAND gates having two and three input terminals, respectively.
As shown by the truth tables of FIG. 1, a NOR gate outputs high level(1) only when all the input signals are low level(0) regardless of the number of input terminals. A NAND gate outputs low level(0) only when all the input signals are high level(1) regardless of the number of input terminals.
In other words, a multi-input NOR gate outputs a low level(0) signal when at least one of input signals is high level(1), and a multi-input NAND gate outputs a high level(1) signal when at least one of input signals is low level(0).
In the past, we have constructed the logic gate of FIGS. 1 (a)-(d) using circuits as shown in FIGS. 2 (a)-(d). But there was a problem in that the circuit structures of the NOR gate and NAND gate of FIG. 2 were complicated. That is, if there were a number N input terminals in the prior art NOR gate and NAND gate, 3N+1 MOS transistors and two bipolar transistors were necessary in order to construct the corresponding circuit.
Thus in the past, the greater the number of NOR gate and NAND gate input terminals, the more complicated the circuit became. There resulted a problem in that the chip area became large to accommodate numerous transistors, and the wiring of the logic circuit became complicated.
USPTO Backgrounds
USPTO Backgrounds