1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory devices and, more particularly, to a nonvolatile semiconductor memory device including a redundant structure.
2. Description of the Background Art
Semiconductor memory devices (hereinafter, referred to as semiconductor memories or semiconductor memory chips) are tested for proper operation after the fabricating processes have been completed and prior to shipment, and as the results of such tests, devices capable of proper operations are sorted out from defective devices.
In such tests, even if there partially exists a defective circuit portion, the defective portion is substituted with a specific defective-portion substituting circuit to eliminate the defection and then fine adjustments for ensuring proper operation (hereinafter, referred to as trimming) are made. In general, such a defective-portion substituting circuit is referred to as a redundant circuit and substitution relief utilizing a redundant circuit is referred to as redundant substitution.
Further, in the aforementioned tests, there may be a case where semiconductor memory devices to be tested have electric characteristics which are out of specs required for proper operations. In this case, similarly, trimming of electric characteristics is performed using specific adjustment circuits to satisfy the required specs for these devices and these devices are shipped as devices capable of normal operation. Such adjustment circuits are also one type of redundant circuits in a broad sense.
As a trimming method for use in redundant substitution as described above, a laser trimming method is often employed. The laser trimming method is a method which, based on the results of operation tests performed after the semiconductor fabricating processes, programs the fuse element by laser blowing for electrically substituting the defective portions with redundant circuits or for adjusting the electric characteristics of the detective portions. In the fuse element, there is nonvolatily stored redundant information including information about the presence or absence of defective circuit portions and information for identifying the defective portions (see, for example, Japanese Patent Laying-Open Nos. 10-241396 and 08-249900).
While the laser trimming method may ensure excellent fabrication quality, it has the following problems since it involves a laser blow process for programming.
The first problem is that the layout size can not be reduced since there are restrictions that the size of fuse element can not be reduced to be smaller than the spot diameter of the directed laser and that there must be a sufficient clearance in the layout for preventing influences of the thermal fuse blowing on the adjacent fuse element. Particularly, in order to program a large amount of information, the layout size of the redundant circuit must be large, and accordingly the chip area of the device itself must be increased. Increases in the chip area directly result in increases in the fabricating cost.
The second problem is that since wirings can not be run through the layers over the area in which the fuse element is provided, an area for diverting wirings is further required. This is because the laser blowing process is performed by directing a laser light ray onto the upper surface of the chip. This also requires increasing the chip area.
The third problem is that redundant substitution can not be performed for defections generated after a molding process. Once the chip has been encapsulated into a mold package, a laser light ray can not be directed to the upper surface of the chip, and therefore programming can not be performed.
The fourth problem is that redundant substitution can not be performed for defections generated after programming. Programming is performed by blowing out the fuse element by laser blowing, and therefore once the programming has been completed, programming can not be performed again even if a further defection is generated.
The fifth problem is that the laser programming requires a specific laser blowing device, thereby increasing the cost of the device.
The aforementioned problems may induce increases in the fabricating cost of the semiconductor device.
Therefore, as a means for avoiding these problems, there has been suggested a redundant circuit employing nonvolatile memory cells as program elements. Particularly, in nonvolatile semiconductor memory devices such as flash memories, the main part of the storage element is constituted by volatile memory cells, and therefore the nonvolatile memory cells may be utilized as the program element of the storage element.
In redundant substitution for a nonvolatile semiconductor memory device, as previously described, nonvolatile memory cells may be utilized as a program element to perform programming without involving a laser blowing process, thereby avoiding the aforementioned problems. On the other hand, in nonvolatile semiconductor memory devices, new problems will be generated as follows.
Generally, writing into nonvolatile memory cells involves complex programming sequences and therefore requires a number of specific circuits for realizing the programming operations. Particularly, flash memories and EEPROMs (Electrically Erasable Programmable Read-Only Memories) require a relatively high electric voltage for the programming operation, and therefore the specific circuits for programming require a significantly large layout area. Accordingly, it is desirable that the circuits for performing reading/writing/erasing operations for the areas which performs normal memory operations (hereinafter, referred to as normal memory cell areas) are also utilized as the circuits for performing reading/writing/erasing operations for the nonvolatile memory cell area (hereinafter, referred to as a PROM area) for use as the storage element for redundant information (information about redundant substitution and electrical characteristics adjustments).
The reading of program information for the PROM area must be performed at power-on of the volatile semiconductor memory device. This is because when performing the normal memory operations from outside, namely the reading/writing/erasing operations for the normal memory cell areas, it is required that redundant information has been already read out and the setting of the redundant circuit has been completed. Therefore, at power-on of the volatile semiconductor memory device, the program information must been read out from the PROM area in advance to complete various setting.
However, at power-on, the power supply voltage VCC supplied from outside (hereinafter, referred to as an external power supply voltage) and the power supply voltage which is generated within the chip by supplying the external power supply voltage to the chip (hereinafter, referred to as an internal power supply voltage INTVCC) have not been stabilized. This makes difficult to perform the reading operation for the PROM area using the same procedure as that for the data reading operation for the normal memory cell area, which is performed under a stable external power supply voltage and stable internal power supply voltage. Therefore, it is desirable that the reading operation for the PROM area is performed using paths separated from those for the reading operation for the normal memory cell areas and also using a specific reading circuit for the PROM area.
However, if data reading for the PROM area is performed using paths separated from those for reading for the normal memory cell area, it is a new task to ensure stable reading operation under unstable biasing conditions at power-on.
USPTO Backgrounds
USPTO Backgrounds