Generally, semiconductor chips are small pieces of silicon or a similarly-suitable material on which a large number of interconnected electrical devices have been fabricated to form integrated circuits. The circuits are capable of performing a variety of tasks, such as the computations necessary to the operation of personal computers, mobile telephones, and digital cameras. The devices making up the integrated circuits are very small, and there are typically a great number of them on a single chip, which is often less than a square centimeter in area and very thin. Usually, a thin slice of substrate material called a wafer is used as a base for fabricating many chips at the same time, using a number of process steps. The individual chips are then separated from each other and packaged for installation into the appliance for which they are intended.
On any wafer, and therefore on any one chip it contains, there are sometimes many layers of different materials that are added to the wafer substrate and shaped to form the individual devices. Electrical devices may be, and usually are formed on any level, and each device often occupies more than one layer. As might be expected, both conductive and insulating layers are required. Conductive layers may be largely devoted to interconnects (usually metal) that couple electrical devices to one another, or to other interconnects.
The integrated circuits formed on the chip require external connections to be useful. An external connection may used for operation, or testing, or both, and usually consists of a bond pad or similar structure. One example is illustrated in FIG. 1. FIG. 1 is an elevation, or side view illustrating in cross-section an exemplary semiconductor device 100. Semiconductor device 100 is formed on a substrate 115, in this example a silicon wafer (only a small portion of which is shown). A number of separate devices have been formed on the surface 116 of the substrate 115, and are in FIG. 1 referred to as devices 121 through 124. These devices may be, for example, transistors, capacitors, or diodes, although other types of devices are possible. The devices are connected in various ways to form electrical circuits that enable the overall device 100 to perform its intended function. Note that although four devices are shown for the purpose of illustration, in most modern applications, there are thousands, if not millions of such devices. And while devices 121 through 124 are formed on the surface 116 of substrate 115, these may in some cases be formed on an appropriately-prepared higher layer as well. In the example of FIG. 1, the active devices 121 though 124 and any other proximate and connected devices (not shown) are referred to for convenience as an active area 120.
Active area 120, and possibly some of the individual devices constituting it, are connected to other active areas, active devices, or to an external component. Such connections are often accomplished using an interconnect of some kind. In FIG. 1, via 126 and via 127 are recesses formed in a layer 125 of dielectric material and filled with a conductor such as copper to establish a vertical electrical connection. Vias 126 and 127 are in contact with the active area 120 at their lower end and with conducting lines 31 and 32 at their upper end. Lines 31 and 32, and typically many other conductors like them on the same vertical level, are often formed at the same time at part of a metal layer 130. The separate conductive elements of metal layer 130, which may or may not be in contact with each other, may be formed in a number of ways such as selectively etching away unneeded portions of the a layer of conductive material that was previously-formed on top of dielectric layer 125.
Note that for convenience the spatial designations such as “top” or “above” refer to the orientation shown in FIG. 1 (and other Figures). This is generally though not necessarily the orientation of the device as it is being fabricated, and components are generally though not necessarily formed from the bottom to the top. In operation, of course, a typical device may be used in almost any orientation.
The necessary external connection referred to above is provided, in the example of FIG. 1, by pad 105. Pad 105 is located at a level near the top surface of semiconductor device 100. Here, it is actually disposed within an opening formed through a passivation layer 175, and may be one of several hundred such pads. As should be apparent, the pad 105 is relatively large compared to the active devices 121 through 124. This is typical, though FIG. 1 is not intended to be drawn to scale. The pad's relatively-large size is often necessary for the pad to be used for its intended purpose.
Pad 105 may be used in a number of different ways, for example as a connection point for a bond wire or solder ball (in which cases it might be referred to as a bond pad or a bump pad, respectively). It may also be used as a contact point for a small probe, which is not permanently installed but simply placed in contact with pad 105 for running an electrical test. In the configuration of FIG. 1, the pad 105 is located laterally at a (relatively) significant distance from the active area 120. This is not atypical; in many applications the active areas are formed in the center of the chip and the pads are grouped together around the chip periphery. The pad 105 is connected to the active area 120, or other areas with which it is associated, by one or more lines of metal or other conductive material. Because there are so many connections to be made, these lines must be routed in ways that avoid unwanted intersections. To accomplish this, several metal layers are frequently used, with each layer separated from the adjacent ones by a layer of insulating material. Vias, which are basically vertical connectors, are used to connect lines at different levels. Many connections pass through a number of lines and vias. A line and its associated vias may be referred to an interconnect.
The example of FIG. 1 includes a number of layers to generally illustrate how these interconnects may be arranged. Atop the dielectric layer 125 and metal layer 130, whose top surfaces are not atypically coplanar, is an inter-metal dielectric (IMD) layer 135 and a metal layer 140. As should be apparent, the metal layers are not uniform and solid, but rather form a pattern of conductive elements that are disposed at substantially the same level. Elements in metal layer 140 may be connected to elements in metal layer 130 by one or more vias, as is generally illustrated in FIG. 1. In some instances, however, an undesirable electrical connection, that is, a short circuit, may be caused by a defect in the pad structure. Because they connect two or more vertically-disposed layers, these are sometimes referred to as “vertical shorts”. Despite their relatively-large size compared with other semiconductor devices, the pads are nevertheless fairly small and fragile, and damage to them or the underlying layers can be caused by simply by application of a test probe or by attachment of a bond wire or solder ball. Since such damage may be hidden under the pad, it may be difficult to detect.
Inspection for such defects may be made through “deprocessing”, where the layers previously-deposited on the wafer surface are removed, one by one, with the device being examined between each removal. Not only is this a destructive inspection, however, but it is both time-consuming and subject to be inaccurate. At any given removal step, too much material may be removed and a formed defect lost, or artifacts may remain and the view of a defect obstructed. What is needed, then, is a manner of electrically testing the pad structure to more easily and reliably detect any vertical shorts. The present invention provides just such a solution.
USPTO Backgrounds
USPTO Backgrounds