1. Field of the Invention
The present invention generally relates to integrated circuits and, in particular, to systems and methods for facilitating automated test equipment functionality within integrated circuits.
2. Description of the Related Art
Heretofore, integrated circuit (IC) devices have been tested and verified using a variety of test methods. For example, IC devices have been tested and verified to be defect free using functional test vectors, such as those applied to the IC by the use of automated test equipment (ATE), which stimulate and verify the IC device functionality at the pin-level of the device. A practical limitation to the utilization of ATE for testing IC""s, however, is that the number of IC pins (or pads) that can be tested by a particular ATE has, heretofore, been limited by the physical configuration of the ATE. For instance, the number of pads of the IC to be tested may exceed the number of test channels provided by an ATE, or the number of pads may exceed the capacity of the ATE support hardware, such as by exceeding the maximum number of probes on a probe card, among others. As utilized herein, the term xe2x80x9cpadxe2x80x9d is used to refer collectively to both a physical site, which serves as an electrical contact for an IC, as well as circuitry associated with the physical site for enabling electrical communication between components of the IC and components external to the IC.
Additionally, performance limitations of an ATE may impose certain other testing restrictions. For example, the frequency of IC inputs and outputs may exceed the maximum frequency of the ATE, thereby limiting the test frequency of the IC to be tested to the maximum frequency of the ATE. Although configuring an ATE with additional test channels and/or a higher operating frequency may be accomplished, providing an ATE with an appropriately high pin count and/or an appropriately high operating frequency in order to eliminate the aforementioned deficiencies is, oftentimes, cost prohibitive.
In light of the foregoing and other deficiencies, it is known in the prior art to test IC devices utilizing a variety of xe2x80x9cstop-gapxe2x80x9d testing procedures, including: (1) connecting an ATE to less than all of the pins of an IC device; (2) connecting multiple pins of an IC device to a single ATE test channel; (3) testing the IC device in multiple passes of the ATE, with each pass testing a subset of the pins of the entire IC device; (4) testing the device at less than maximum frequency, and; (5) limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE, among others. As should be readily apparent, many of these xe2x80x9cstop-gapxe2x80x9d testing procedures may result in a loss of test coverage and, thereby, may lead to an increase in numbers of defective IC devices being shipped. Moreover, the practice of limiting, through design implementation, the pin count and/or frequency of the IC device to accommodate existing ATE is, oftentimes, an unacceptable constraint on IC design.
Therefore, there is a need for improved systems and methods which address these and other shortcomings of the prior art.
Briefly described, the present invention provides automated test equipment functionality within integrated circuits. In this regard, some embodiments of the present invention may be construed as providing integrated circuits (IC""s). In a preferred embodiment, the integrated circuit includes a first pad electrically communicating with at least a portion of the IC, with the first pad being configured as a signal interface for components external to the IC. A first parametric test circuit also is provided, internal to the IC, and is adapted to measure at least one parameter of the first pad.
In an alternative embodiment, the integrated circuit includes first means for interfacing the IC with components external to the IC, and first means for measuring at least one parameter of the first means for interfacing.
Some embodiments of the present invention may be construed as providing systems for measuring a parameter of a pad of an IC. Preferably, the system includes automated test equipment (ATE) configured to electrically interconnect with the IC and to provide at least one signal to the IC. A first parametric test circuit, internal to the IC, also is provided. The first parametric test circuit is adapted to electrically communicate with the ATE so that, in response to receiving a signal from the ATE, the first parametric test circuit measures at least one parameter of the first pad.
Embodiments of the present invention also may be construed as providing methods for testing an IC. In a preferred embodiment, the IC includes a first pad configured as a signal interface for components external to the IC, and a first parametric test circuit, internal to the IC, and adapted to test at least one parameter of the IC. The method includes the steps of: electrically interconnecting ATE with the IC; providing at least one stimulus from the ATE to the IC so that the first parametric test circuit measures at least one parameter of the first pad; and receiving information corresponding to the at least one parameter measured by the first parametric test circuit.
In an alternative embodiment, a method for forming an integrated circuit includes the steps of providing a first pad configured as a signal interface for components external to the IC and providing a first parametric test circuit internal to the IC that is adapted to measure at least one parameter of the first pad.
Additionally, some embodiments of the present invention may be construed as providing computer readable media. In a preferred embodiment, the computer readable medium includes a computer program for facilitating testing of an IC and incorporates logic configured to enable ATE to provide at least one signal to the IC so that a first parametric test circuit of the IC measures at least one parameter of a first pad of the IC. Logic configured to enable the ATE to receive, from the first parametric test circuit, data corresponding to the at least one parameter of the first pad also is provided.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such features and advantages be included herein within the scope of the present invention, as defined in the appended claims.
USPTO Backgrounds
USPTO Backgrounds