The present invention relates generally to battery control and fault detection, and more particularly to monitoring of batteries and battery arrays for state of health and fault isolation.
Battery monitor circuits are known as shown in the following U.S. Pat. No. 4,316,185 to Watrous et al discloses a battery monitor circuit that provides an indication of battery failure independent of temperature, load and age, by continuously comparing the impedance of the cells of the battery against each other. U.S. Pat. No. 4,217,645 to Barry et al shows a system for automatically monitoring cells in a battery system using a microprocessor. The information is stored and averaged within the microprocessor and an alarm provided if any cell exceeds specified limits. In U.S. Pat. No. 3,872,457 to Ray et al the battery monitor continuously scans individual cells in succession. U.S. Pat. No. 4,198,597 to Sawyer employs light emitting diode indicators which identify individual faulty cells. Finger in U.S. Pat. No. 4,388,618 senses the state of charge of a battery by operating on bidirectional integrations of terminal voltage.
Usually set control limits or failure criteria are used in battery control/monitoring systems. As the battery ages, the temperature changes, or the charge and discharge rates change, the control limits must be modified.
USPTO Backgrounds
USPTO Backgrounds