The present invention is related to a method for determining the lifetime characteristics of submicron metal interconnects.
In the microelectronics industry scaling refers to the miniaturisation of active components and connections on a chip. It has followed Moore's law for many decades. Despite many advantages, scaling also strongly influences the reliability and time to failure of interconnects, i.e. the (metal) conductor lines connecting elements of the integrated circuit. Electromigration (EM), i.e. the mass transport of a metal due to the momentum transfer between conducting electrons and diffusing metal ions, is one of the most severe failure mechanisms of on-chip interconnects. A major problem when testing the reliability of new components is that their time to failure under real life conditions (Tmax=125° C.; j=1-3 105 A/cm2 for a standard type IC) is always extremely long (in order of years). For that reason, the physical failure mechanisms are studied and methods are established for accelerating these mechanisms. The failure times of the devices in operation are measured and models are developed for extrapolating these results to real life conditions. The electromigration accelerating conditions for these tests are the temperature T and the current density j. Reliability tests are usually performed on identical interconnects at accelerating conditions (j,T) (170° C.<T<350° C. and 106<j<107 A/cm2 instead of T=125° C. and j=1-3.105 A/cm2). All interconnects are each individually connected with an own power supply and provided with a multiplexer. Moreover, each interconnect can be found on a different IC package, which is an expensive and time-consuming activity. In order to derive the activation energy, which is a parameter describing the temperature dependence of the observed degradation, these tests must be performed at three temperatures, therefore tripling the number of power supplies, multiplexers and IC packages. This makes the tests more complex and expensive. Nevertheless these reliability tests are of great importance to manufacturers because on the one hand continuously operational IC's are indispensable and on the other hand the competitive strength of manufacturers strongly depends on the reliability of their products. Therefore such tests should provide a large amount of statistical information in a relatively short period of time, while keeping costs under control. It is hard to lower the costs without decreasing the accuracy of the experiments. To solve this problem one need to look for a test structure that can provide a large amount of accurate data in a short period of time at low cost.
Patent document US-2002/0017906-A1 discloses a method for detecting early failures in a large ensemble of semiconductor elements. It employs a parallel test structure. A Wheatstone bridge arrangement is used to measure small resistance changes. The criterion for failure of the test structure is the time to first discernible voltage imbalance ΔV(t).
USPTO Backgrounds
USPTO Backgrounds