The present invention relates generally to electronics packaging. More particularly, the present invention relates to an electronic package that includes a die packaged on a thin interposer, and to manufacturing methods related thereto.
Integrated circuits (ICs) have typically been assembled into electronic packages by physically and electrically coupling them to a substrate made of organic or ceramic material. One or more such IC packages can be physically and electrically coupled to a secondary substrate such as a printed circuit board or motherboard to form an electronic assembly. The electronic assembly can be part of an electronic system. An electronic system is broadly defined herein as any product having an electronic assembly. Examples of electronic systems include computers (e.g., desktop, laptop, hand-held, server, etc.), wireless communications devices (e.g., cellular phones, cordless phones, pagers, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders or MP3 players.
Manufacturers of electronic systems constantly try to improve product performance while reducing production costs. This is particularly true regarding the packaging of ICs, where each new generation of packaging must provide increased performance at decreased sizes. Therefore, manufacturers of high-end ICs, such as processors, continually develop IC packages that are thinner, lighter-weight, and/or more resilient because such packaging is useful for many applications. A typical package includes an IC, such as a die, that is mounted on an interposer which functionally connects the die through a hierarchy of electrically conductive paths to the other elements that make up the electronic system.
Power delivery is an area of microprocessor development that will be crucial to improving future microprocessors. One of the major limitations associated with power delivery is the inductive path, or loop, between a die and one or more capacitors that provide power to the components in the die before another source, such as a voltage regulator, is able to provide a steady supply of power. This limitation is typically addressed by attaching the capacitors to the underside of a thin interposer that is positioned between the die and the capacitors in order to minimize the distance between the die and the capacitors. Reducing the distance between the capacitors and the die minimizes the inductive loop that is generated when supplying power to the die. However, the thin interposer leads to another problem as the thin interposer is unable to handle the mechanical loads that are generated on the interposer during operation of the integrated circuit.
FIGS. 1 and 2 show two different types of prior art packages. The package 10 illustrated in FIG. 1 includes a die 12 that is mounted onto a thin interposer 14 using a conventional C4 (solder-ball) joint that is supplemented by a conventional underfill 15. A pin carrier 16 is attached to the underside of the interposer 14 to support the interposer 14 along at least the entire area of the die 12. The design of the package 10, in particular the pin carrier 16, does not permit any type of electronic component to be mounted to the underside of the interposer 14 in that area of the interposer which is opposite to the die 12. Therefore, the prior art package 10 shown in FIG. 1 suffers from an inductive path problem.
FIG. 2 shows a prior art package 20 that overcomes the inductive path problem. Package 20 includes a die 22 that is mounted onto a thin interposer 24. Die 22 is similarly mounted to interposer 24 using a conventional C4 joint that is supplemented by a conventional underfill 25. A pin carrier 26 that includes a cavity 27 is mounted to the underside of the thin interposer 24. The cavity 27 in pin carrier 26 is positioned underneath die 22 such that electronic components 28 may be mounted to the underside of interposer 24 opposite to die 22. Placing the electronic components 28 against interposer 24 within cavity 27 of the pin carrier 26 reduces the distance between die 22 and electronic components 28. This reduced distance minimizes the inductive loop problem. However, thin interposer 24 is incapable of withstanding the mechanical load that is applied to package 20 by heat sinks and/or other thermal elements within the integrated circuit. The mechanical load generates package deflection that results in multiple failure modes, including internal damage to the package circuitry and/or damage to the joints that connect the electronic components to interposer 24.
As the internal circuitry of processors operates at higher frequencies, and processors operate at higher power levels, the amount of loop inductance produced within processor packages often increases to unacceptable levels. In addition, the smaller physical size of processor packages makes the packages more fragile and less able to carry higher power loads. Therefore, there is a significant need for a reliable electronics package, and methods of fabricating an electronics package that generates minimal loop inductance within the package yet is mechanically stable.
USPTO Backgrounds
USPTO Backgrounds