Embodiments of the present invention relate to microprocessors and computers in general. More particularly, embodiments of the present invention relate to memory record updating.
Microprocessor performance can be improved by collecting information related to the processing of instructions and storing that information in memory records, e.g., in a cache, in a buffer in memory, in an address predictor, etc. Aspects of the behavior of executed instructions can be stored in a memory record to improve performance when one or more of those instructions (and/or other related instructions) is subsequently executed.
For example, memory operands of instructions can be stored in a main memory or a cache. A cache is typically a small, fast memory that is closer to (and/or part of) a microprocessor than the larger, slower main memory. Retrieval of the operands from the cache can be significantly faster than retrieval of the operands from main memory. The amount of time required to execute an instruction can be dependent on the amount of time required to retrieve the operands of the instruction. Reduced operand retrieval times can increase microprocessor performance because instructions can be executed faster. In known systems, instructions that have been recently executed can be likely to be executed again within a certain period of time. Thus, to increase microprocessor performance, the cache can store the operands of the most recently executed instructions. When one or more of the most recently executed instructions are again executed and the necessary operands are stored in the cache, microprocessor performance can be improved due to reduced operand retrieval times.
In another example, the instruction pointer of a branch instruction and the target address of the branch instruction can be stored in an entry of a branch target buffer. An instruction pointer can be an identifier of an instruction that identifies the memory address where an instruction is stored prior to its retrieval and execution. A branch instruction of a program is an instruction that can redirect the path of execution of a program being executed by a microprocessor. In a simple example, a branch instruction can redirect the path of execution of the program based on an operand value, and the target address of the branch instruction can specify where the redirected execution is to begin (e.g., at which address the redirected execution is to begin, etc.). The target address is typically calculated at least a first time a branch instruction is executed, and target address calculation can delay execution of the branch instruction.
Storing the instruction pointer and the target address of an executed branch instruction in a branch target buffer can allow branch address prediction. When a branch instruction is fetched, the branch target buffer can be accessed to determine if a target address is stored corresponding to the instruction pointer of the branch instruction. When such a target address is stored in the branch target buffer, the target address can be used as a predicted branch address. Using predicted branch addresses can increase microprocessor performance by allowing earlier execution of addresses subsequent to the predicted branch address.
A limitation of data records that store information related to the processing of instructionsxe2x80x94such a data caches, branch target buffers, and other event recordsxe2x80x94is that their size is usually limited (e.g., by the size of the cache, the buffer memory allocation, etc.) to a certain number of data entries. When each of the data entries of the data record are full and a new data value is received to be written to the data record, known allocation methods can decide which one of the old data values will be evicted to allow storing of the new data value.
One known allocation policy decides which data value is evicted based solely on temporal locality, e.g., based on how long a data value has been stored in the data record. For example, an allocation policy can cause the least recently used data value to be evicted from the data record so that the new data value can be stored. A temporal allocation policy can be inefficient because older, more critical data values can be evicted so that newer, non-critical data values can be stored. Older, more critical data values can include data relating to regular events that are regularly executed. At times, however, a series of non-regular events (e.g., rare events, unique events, non-typical events, etc.) can be executed. When a data record is operated according to a temporal allocation policy, the regular event data can be evicted from the data record to allow storing the non-regular event data, even though the non-regular event data will not likely be accessed again and the regular event data will likely be accessed again. Thus, after the non-regular event data has been written into the data record, subsequent execution of the regular events can be delayed because the regular event data has been evicted from the data record and must be reloaded from main memory, recalculated, etc. Replacing relevant data stored in a data record with non-relevant data has been termed xe2x80x9cpollutingxe2x80x9d or xe2x80x9ctrashingxe2x80x9d the data record.
In view of the foregoing, it can be appreciated that a substantial need exists for methods and apparatus which can advantageously filter memory record updating.
Embodiments of the present invention include apparatus and methods to filter memory record updating. A microprocessor can include a memory record update filter. The memory record update filter can include a table memory populated by a plurality of data entries. Each data entry can include a data tag field to store a data tag, a data field to store a data value, and a filter field to store a filter value. A first comparator can be in communication with the data tag field of the table memory and a data accessing information input to perform a data tag comparison. A second comparator can be in communication with the filter field of the table memory and a data value input. A control circuit can be in communication with the table memory, the first comparator, and the second comparator.
USPTO Backgrounds
USPTO Backgrounds