A MIM capacitor is a component of an IC commonly used in high performance applications in complementary metal-oxide-semiconductor (CMOS) technology. The CMOS technology is used, for example, in microprocessors, microcontrollers, static RAM, and other digital logic circuits.
Typically, the MIM capacitor has a sandwich structure and can be described as a parallel plate capacitor. The capacitor top metal (CTM) is separated from the capacitor bottom metal (CBM) by a thin insulating dielectric layer. Both parallel plates are typically formed from Al or AlCu alloys that can be patterned and etched through the use of several photolithography photomasking steps. The thin insulating dielectric layer is typically made from silicon oxide or silicon nitride deposited by chemical vapor deposition (CVD).
With the development of the integrated circuit technology, the MIM capacitor has been widely used to improve the performance of the integrated circuit. Currently, in order to electrically connect the MIM capacitor with other electronic components of the IC, the MIM capacitor is usually integrated with an interconnection structure. However, in a conventional process for integrating the MIM capacitor with the interconnection structure, it is necessary to form a number of insulating layers and a number of metal layers. Thus, the conventional process for integrating the MIM capacitor with the interconnection structure requires a number of depositing steps and etching steps, thereby increasing the production cost and causing the final integrated structure to be complicated.
Copper-based chips are semiconductor integrated circuits that use copper for interconnections between the metallization layers of the IC. Since copper is a better conductor than aluminum, chips using this technology can have smaller metal components and use less energy to pass electricity through them. Together, these effects lead to higher performance processors.
Subtractive etch, the approach used in fabricating aluminum-based interconnects is inapplicable in the fabrication of copper-based interconnects (or interconnections), due to the lack of volatility of copper-halide complexes at moderate temperatures. As a result, copper interconnect fabrication requires a damascene approach whereby the metallization is inlaid into interconnect geometries which are pattern-transferred into the dielectric of interest. A dual damascene process also offers lower fabrication cost due to the limited use of chemical-mechanical planarization (CMP) processes compared to the multiple uses of this unit process in the subtractive etch fabrication of interconnects. However, the dielectric etches and metal fill processes of the dual damascene process face higher aspect ratios due to the dual damascene structure.
Dual Damascene copper interconnects may be fabricated using two primary schemes; via first scheme or trench first scheme. In the self-aligned approach the via level dielectric, or interlayer dielectric (ILD) and an etch stop layer (typically silicon nitride or silicon carbide for inorganic ILDs and oxide for organic ILDs) are sequentially deposited, followed by pattern and etch of via into the etch stop layer. The trench features are delineated into this dielectric and the trench etch is extended to complete transferring the via pattern from the etch stop layer into the interlayer dielectric. The etch stop layer defines the trench height, while maintaining a vertical profile of the via sidewall. The etch stop layer is removed from the bottom of the trench during the final etch step, which simultaneously clears the dielectric barrier from the bottom of the via.
Disadvantages of the self-aligned approach include the need for an etch stop layer (which increases sidewall capacitance), the need for high etch selectivity to the etch stop layer and susceptibility to partial via definition if trench and via are misaligned. Partial vias present a potential reliability issue and, thus, this integration scheme should be avoided unless ample alignment tolerance is provided in the product design.
Intervening etch stop layers in via/trench architecture degrade the effective capacitance of the structure and such layers are undesirable.
USPTO Backgrounds
USPTO Backgrounds