This invention relates to a summing circuit, and more particularly, to a binary summing circuit for use in carrying out multiplication of two binary numbers
Multiplication of two binary numbers is normally carried out as addition of a number of summands which include, for example, zeroth through n-th input data signals, where n represents a first predetermined natural number. Each of the zeroth through the n-th input data signals is, for example, (m +k +1) bits long, where m represents a second predetermined natural number which is not less than the first predetermined natural number n and k represents a predetermined integer which is not less than zero.
In order to sum up the zeroth through the n-th input data signals, a summing circuit is already known By way of example, a known summing circuit is described by C. S. Wallace to IEEE TRANSACTION ON ELECTRONIC COMPUTERS, February 1964, pages 14 to 17, under the title of "A Suggestion for a Fast Multiplier". The known summing circuit comprises a carry save adder tree circuit and a carry propagate adder (CPA). The carry save adder tree circuit comprises a number of carry save adders (CSA's) and sums up the zeroth through the n-th input data signals to produce two intermediate results of summation. The carry propagate adder adds the two intermediate results together to produce a final result of the summation as a sum signal. Each of the carry save adders consists of full adders which are equal in number to the second predetermined natural number plus one, namely, (m +1). The carry propagate adder includes a carry look ahead (CLA) circuit for generating a carry data signal and produces the sum signal with reference to the carry data signal.
In the known summing circuit, the carry save adder tree circuit is composed in dependence upon the first and the second predetermined natural numbers n and m. As a result, the known summing circuit is disadvantageous in that an increased number of full adders are necessary when the first and the second predetermined natural numbers n and m increase. In addition, the carry propagate adder consumes a large add time.
USPTO Backgrounds
USPTO Backgrounds