1. Field of the Invention
The present invention relates to a programmable logic device. The present invention further relates to a semiconductor device using the programmable logic device, and an electronic device using the semiconductor device.
2. Description of the Related Art
Programmable logic devices show flexibility in a reduction in development period and a change in design specification as compared to conventional application specific integrated circuits (ASIC) and gate arrays, which is advantageous. Therefore, a semiconductor device including the programmable logic device has been developed actively.
The programmable logic device includes, for example, a plurality of logic blocks each including a plurality of logic elements, wirings connecting the a plurality of logic blocks, and an input/output block. When the functions of the logic elements are changed, the function of the programmable logic device can be changed.
The logic element is formed using, for example, a look-up table or the like. The look-up table performs arithmetic processing based on setting data when an input signal is input to the look-up table, and then the look-up table outputs a signal. Here, the setting data is stored in a memory element that corresponds to each of the logic elements. Further, the look-up table can perform different arithmetic processing in accordance with the data stored in the memory element. Thus, the function of the logic element can be specified when specific setting data is stored in the memory element.
The setting data or the like of the look-up table is referred to as configuration data. In addition, the storage circuits that correspond to the logic elements and store the configuration data are referred to as configuration memories. The circuit structure of the programmable logic device can be changed into a circuit structure suitable for a user's request when desired configuration data is produced (programmed) and configuration is performed.
The configuration memory has been formed using a volatile memory such as a static random access memory (SRAM). However, in the case of using a volatile memory, information (configuration data) held in the configuration memory is lost when supply of power is stopped. Therefore, information needs to be written to the configuration memory after the beginning of supply of power; thus, time from the beginning of supply of power to the beginning of operation of the programmable logic device (hereinafter, referred to as start-up time) is long.
In order to shorten start-up time after supply of power is stopped, the programmable logic device is proposed in which the configuration memory is a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM) or a ferroelectric RAM (FeRAM) (see Patent Document 1).
USPTO Backgrounds
USPTO Backgrounds