The present invention generally relates to methods of making extremely thin semiconductor on insulator complementary metal-oxide-semiconductor (ETSOI CMOS) devices, and more specifically to methods of making ETSOI CMOS having n-type and p-type metal oxide semiconductor field-effect transistors (MOSFETs) prepared from semiconductor films of different strain, size, and geometry.
ETSOI (SOI thickness, for example, <8 nanometers (nm)) is considered as a viable device option for scaling to 20 nm node and beyond. ETSOI is a planar structure and thus device fabrication and process characterization of ETSOI devices are often easier than 3-dimensional devices. ETSOI devices are attractive for low power applications.
The MOSFET is a transistor used for amplifying or switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or glass, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
N-type field effect transistors (NFET) and p-type field effect transistors (PFET) are two types of complementary MOSFETs. The NFET uses electrons as the current carriers and is built with n-doped source and drain junctions. The PFET uses holes as the current carriers and is built with p-doped source and drain junctions.
USPTO Backgrounds
USPTO Backgrounds