1. Field of the Invention
Generally, the present disclosure generally relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to a semiconductor device, such as an illustrative PMOS transistor, with a work function adjusting layer that has a thickness that varies in the gate width direction, and various methods of making such a device.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors (NMOS) and/or P-channel transistors (PMOS), are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
FIG. 1A depicts an illustrative prior art device 100 that is generally comprised of a partially formed NMOS transistor 100N and a partially formed PMOS transistor 100P formed in and above a semiconducting substrate 10. The illustrative transistors 100N, 100P are separated by an illustrative isolation structure 12, e.g., a shallow trench isolation structure, formed in the substrate 10. In one illustrative embodiment, the semiconducting substrate 10 is comprised of silicon. The substrate 10 may have a variety of configurations, such the depicted silicon-on-insulator (SOI) structure having a bulk silicon layer 10A, a buried insulation layer 10B and an active layer 10C. The substrate 10 may also have a simple bulk silicon configuration.
At the stage of manufacture depicted in FIG. 1A, the transistors 100N, 100P are each comprised of a gate structure 20 and source/drain regions 30. The gate structure 20 may include a gate insulation layer 22, a high-k insulation layer 24, a gate electrode 26 and sidewall spacers 28. The gate electrode 26 may be made of a variety of materials, such as lanthanum (for the NMOS transistor 100N) and aluminum (for the PMOS transistor 100P). In some cases, the PMOS transistor 100P may have an additional work function layer 25, such as titanium nitride, that may not be present in the NMOS transistor 100N. Typically, during the formation of the PMOS transistor 100P, a work function adjusting layer 32, such as a layer of epitaxial silicon germanium, is selectively grown on the active layer 10C in the P-active region where the PMOS transistor 100P will be formed in an attempt to control the threshold voltage of the PMOS transistor 100P, and thereby enhance the performance and controllability of the PMOS transistor 100P. Typically, the work function adjusting layer 32 is not formed for the NMOS transistor 100N. Typically, depending upon the particular application, the target thickness of the work function adjusting layer 32 may be about 100 nm. FIG. 1B is a plan view of just the PMOS transistor 100P. The transistor has a gate length direction 10L and a gate width direction 10W. Along the gate width direction 10W, the work function adjusting layer 32 has opposite ends 32A, 32B and a middle region 32M.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel is controlled by the gate electrode formed adjacent to the channel region and separated therefrom by the gate thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction 10W, the distance between the source and drain regions 30, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer 22 upon application of the control voltage to the gate electrode 26, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode 26, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. In field effect transistors, silicon dioxide is typically used as a gate insulation layer 22 that separates the gate electrode 26, frequently comprised of polysilicon or other metal-containing materials, from the channel region 31. In steadily improving device performance of field effect transistors, the length of the channel region 31, the so-called “gate length,” has been continuously decreased to improve the switching speed and the drive current capability of the resulting devices. Since the transistor performance is controlled by the voltage supplied to the gate electrode 26 to invert the surface of the channel region 31 to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode 26, the channel region 31 and the insulating layers disposed there between, has to be maintained. It turns out that decreasing the channel length 31 requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage, and thus reduced threshold voltage, may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode 26 to the channel region 31 that is accomplished by decreasing the thickness of the gate insulation layer 22. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel length may be restricted to high-speed signal paths, whereas transistor elements with a longer channel length may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer 22 may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include so-called high-k materials (k value greater than 10) that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5) with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode 26 to replace the typical polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration may be required.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., NMOS transistors 100N and PMOS transistors 100P, which may require an additional band gap offset for the PMOS transistors 100P. For this reason, as noted above, the PMOS transistor 100P usually includes a metal-containing gate electrode material, and the work function adjusting layer 32 between the high-k dielectric material 24 and the channel region 31 of the PMOS device 100P, in order to appropriately modulate the work function of the PMOS device 100P. More specifically, by including this work function adjusting layer 32, the threshold voltage of the PMOS device 100P is shifted or lowered to acceptable levels for use in modern high-performance integrated circuit devices. That is, the threshold voltage of a PMOS device 100P without such a work function adjusting layer 32 would tend to be too high for use in high-performance devices.
Another technique that device designers have employed to enhance the performance of transistor devices involves the use of channel stress engineering techniques on transistors. More specifically, designers use various techniques to create a tensile stress in the channel region 31 of the NMOS transistors 100N and to create a compressive stress in the channel region 31 of the PMOS transistors 100P. These stress conditions improve charge carrier mobility of the devices—electrons for NMOS devices 100N and holes for PMOS devices 100P. As it relates to PMOS devices 100P, the work function adjusting layer 32 typically provides a significant portion of the desired compressive stress to the channel region 31 of the device. With reference to FIG. 1B, one problem with current state of the art work function adjusting layer 32 is that the stress within the work function adjusting layer 32 tends to relax toward the opposing ends 32A, 32B of the work function adjusting layer 32 as compared to the stress of the work function adjusting layer 32 toward the middle 32M of the work function adjusting layer 32. This is especially true as gate widths get smaller. This lack of a consistent stress along the gate width direction 10W causes mobility degradation and an increase of the threshold voltage of such a device, since applying the desired compressive stress in the channel region 31 of a PMOS device 100P may, in some cases, account for almost half of the shift in the threshold voltage, e.g., 150 mV of a total 300 mV shift. Both of these problems result in less drive current and reduced device performance capabilities of the resulting PMOS device 100P and consumer electronic products incorporating such devices.
FIGS. 1C and 1D are partial cross-sectional views of illustrative examples of prior art work function adjusting layers. In FIG. 1C, the work function adjusting layer 32 may have a generally rounded profile at the edges 32A, 32B of the work function adjusting layer 32. Typically, the region 32L is a region that exhibits a relatively lower compressive stress level as compared to the illustrative region 32H, which exhibits a relatively higher compressive stress level. The thickness of the work function adjusting layer 32 depicted in FIG. 1C tends to vary along the gate width direction 10W. For example, in one illustrative example, the thickness of the work function adjusting layer 32 depicted in FIG. 1C may be approximately uniform in the middle region 32M (three readings of approximately 9.6, 9.3, and 9.4 nm from left to right in FIG. 1C) and thereafter taper off significantly at the very edges 32E of the work function adjusting layer 32. The illustrative work function adjusting layer 32 depicted in FIG. 1D tends to be somewhat flatter as compared to the one depicted in FIG. 1C. More specifically, the work function adjusting layer 32 depicted in FIG. 1D may also be approximately uniform in the middle region 32M (three readings of approximately 6.0, 5.7, and 6.0 nm from left to right in FIG. 1D) and thereafter taper off sharply at the very edges 32E of the work function adjusting layer 32.
The present disclosure is directed to various devices and methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds