1. Field of the Invention
The present invention relates to charge trapping dielectric structures and to non-volatile memory based on such structures.
2. Description of Related Art
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as EEPROM and flash memory are used in a variety of modern applications. A number of memory cell structures are used for EEPROM and flash memory. As the dimensions of integrated circuits shrink, greater interest is arising for memory cell structures based on charge trapping dielectric layers, because of the scalability and simplicity of the manufacturing processes. Memory cell structures based on charge trapping dielectric layers include structures known by the industry names NROM, SONOS, and PHINES, for example. These memory cell structures store data by trapping charge in a charge trapping dielectric layer, such as silicon nitride. As negative charge is trapped, the threshold voltage of the memory cell increases. The threshold voltage of the memory cell is reduced by removing negative charge from the charge trapping layer.
One problem associated with charge trapping structures used in non-volatile memory is data retention. For commercial products it is desirable for such devices to hold data for at least ten years without loss. However, leakage of trapped charge occurs in such devices due to defects in the materials which accumulate over long use, or which are inherent in the structures.
It is desirable to provide charge trapping structures for non-volatile memory with improved charge retention characteristics.
USPTO Backgrounds
USPTO Backgrounds