There is no doubt that the future will be overwhelmed with exciting information processing technologies and applications driven not only by the internet but also by many new emerging concepts such as the Internet of Things (IoT), Internet of Human Body, wireless and wired sensor networks, and many others. However, to drive all these technologies at their full capacity, it is imperative to create a new hardware technology. It is recognized that current complementary metal-oxide-semiconductor (CMOS) devices have run out of steam and that Moore's Law cannot continue with CMOS alone. The next-generation energy-efficient information processing applications will require unprecedented high data rates, data storage densities, and energy efficiency that cannot be matched by the existing CMOS based hardware. Quantum computing—the holy grail of computation—will likely be required at some point and will likely prevail in the information industry. However, achieving the capabilities of this new computing paradigm today is still out of the question because of the fundamental challenges associated with enabling quantum input and output. Some hybrid technologies should emerge as a stepping stone towards achieving quantum computing.
Indeed, spintronic/nanomagnetic nanotechnologies are widely considered as a promising alternative to current semiconductor microprocessor and memory technologies, which today are facing fundamental limitations in scaling and power consumption. Spintronic nanodevices have advantages of non-volatility in both logic and memory, an ultra-low power consumption, radiation hardness, scalability to the sub-5-nm size range, and a capability for multilevel three-dimensional (3D) integration with a significantly improved thermal management. Despite all these advantages, spintronic devices have been used only for a few relatively small niche applications. The reason for the current inadequate market penetrability of spintronics is the relatively low “On/Off” ratio of spintronic devices compared to existing CMOS technologies. In spintronic devices, it is the giant magnetoresistance (GMR) that defines the “On/Off” ratio. Considering the GMR value in state-of-the-art demonstrations is on the order of 100% (equivalent to an “On/Off” ratio of 1), it is still at least three orders of magnitude smaller than typical values in CMOS technologies. One of the main challenges to create such small devices is the fabrication limitation. Even with state-of-the-art nanofabrication approaches such as electron beam lithography (EBL), focused ion beam (FIB) etching and deposition, and imprint lithography, it is difficult to fabricate high quality spintronic devices in this size range.
USPTO Backgrounds
USPTO Backgrounds