MMUs, by mapping of virtual addresses to physical addresses, may increase the total size of data stacks to exceed the size of a physical memory. An MMU's page table, e.g., a conversion table of virtual addresses and physical addresses, may be stored in a memory. Since the conversion from a virtual address to a physical address requires multiple accesses to memory, the performance of data access is greatly reduced. A TLB unit may be provided to improve the efficiency of data access. The TLB unit stores a part of page entries retrieved from the page table. When a data process device sends a virtual address, MMU first accesses the TLB unit. If the TLB unit contains the page which may be used to convert this virtual address, this page is used to generate the physical address. If the TLB unit does not include the page indicated by the virtual address, MMU may access the page table in the memory to find the page of corresponding address and update this page into the TLB unit. Thus, TLB units may reduce the frequency of accessing the memory, largely improve the performance of data access.
However, conventional TLB units may not work for streaming applications such as data streams in artificial neural networks. The data streams in artificial neural networks may include multiple consecutive virtual addresses and only accessing each corresponding page once in a period. As such, TLB misses may frequently occur in conventional TLB units and the MMU may access the memory to retrieve the corresponding page. Therefore, for streaming applications, conventional TLB units may not improve the performance of data access.
USPTO Backgrounds
USPTO Backgrounds