1. Field of the Invention
The present invention relates to a semiconductor memory device and a blank page search method therefor and, more particularly, a search method of searching for a page (blank page) in a data initial state in a write in, e.g., a NAND flash memory.
2. Description of the Related Art
In a NAND flash memory, as described in, e.g., U.S. Pat. No. 6,507,508, a plurality of memory cells are connected in series. Each memory cell has, e.g., an n-channel MOSFET structure including a floating gate as a charge accumulation layer and a control gate. Adjacent memory cells share the drain or source. First and second select gate transistors (MOSFETs) are formed between a bit line and one terminal of this series circuit and between its other terminal and a source line, respectively, to form one NAND string. The NAND strings are laid out in an array. The control gates of memory cells of the same row are commonly connected to a word line. The gates of the first and second select gate transistors of the same row are commonly connected to first and second select gate lines, respectively.
A group of NAND strings which share word lines forms a block as an erase unit. In the erase mode, all memory cells in a block are erased. In the read and write modes, one first select gate transistor in a plurality of blocks is selected and rendered conductive to connect series-connected memory cells to a bit line. In this state, a selection voltage is applied to one word line, and a non-selection voltage is applied to the remaining word lines on the same NAND string. A sense amplifier and a write bias circuit (the write bias buffer and a data buffer that holds read and write data are called a page buffer as a whole) are connected to each bit line. The read and write are executed for a unit called a page that shares the selected word line. The size of one page is, e.g., 2,112 bytes. The size of one block is 128 KB.
On the other hand, the host accesses data stored in the memory cells through an IO bus. When the bit width of the IO bus is, e.g., 8 bits (1 byte), the host accesses the page buffer for every byte, like an SRAM.
In the NAND flash memory, the write is executed in the order of page addresses to guarantee the reliability of data stored in the memory cells. For this purpose, the host must search for a page (blank page) in the initial state before a new write.
However, the host can access data only for every byte. To confirm whether a page is a blank page, data of 2,112 bytes must be read out sequentially byte by byte. For this reason, 2,112 clocks are necessary for confirming a blank page.
USPTO Backgrounds
USPTO Backgrounds