1. Field of the Invention
The present invention relates to a static memory cell of the type comprising two transfer transistors of the first conductivity type, two inverters, two data lines and at least one first word line and in which a first terminal of the first transfer transistor is connected to the first data line, a first terminal of the second transfer transistor is connected to the second data line, an input of the first inverter is connected to a second terminal of the first transfer transistor and an output of the first inverter is connected to a second terminal of the second transfer transistor, and in which one input of the second inverter is connected to the output of the first inverter and an output of the second inverter is fed back to the input of the first inverter and a gate terminal of the first transistor is connected to the first word line.
2. Description of the Prior Art
Metal-oxide-semiconductor (MOS) memories belong to a type of integrated circuits having a high degree of integration; they can be divided into the following main groups according to the type of their information storage: MOS memories having dynamic information storage; MOS memories having static information storage; and MOS memories having non-volatile information storage. In the present case, the middle group of MOS memories, i.e. the static memories are of special interest. The information that was written into the memory cell was thereby stored, whereby the memory cell retains its condition once set until the supply voltage is disconnected or is no longer applied to the memory cell for other reasons. It is possible to structure the memory cells with various MOS techniques. Complementary metal-oxide-semiconductor (CMOS) technology has proven particularly advantageous with reference to low-loss technology. A typical 6-transistor memory cell constructed in accordance with CMOS technology is shown by H. Weiss, K. Horninger, "Integrierte MOS-Schaltungen" Springer-Verlag, 1982, p. 229, FIG. 4.73c. It is composed of a cross-coupled flip-flop, whereby two selection transistors produce the connection between the two data lines and the memory nodes. The 6-transistor memory cell is addressed via the word line when reading and writing and is connected to a pair of data lines. A logical "0" or "1" is stored in the memory cell dependent on whether the left-hand memory node lies at the reference potential or at the potential of the supply voltage. Transverse current between the supply voltage and the reference potential does not flow through the memory cell in either case since one of the transistors in the two flip-flop branches inhibits and the other is activated.
In arrangements of this type, there is the risk when reading out a memory cell, that the condition thereof will be changed due to charge transfer from the one or other memory node onto the data lines. The widths of the selection transistors therefore must not be excessively great in relationship to the n-channel transistors in the storage flip-flop. On the other hand, the selection of the selection transistors must be large enough in relationship to the p-channel transistors in the storage flip-flop in order to enable the write-in operation. These p-channel transistors serve the purpose of keeping the cell information static and can be dimensioned with a minimum channel width. The original requirements in the dimensioning of the symmetrical 6-transistor cell lead to the necessity of reliability analyses of parasitic signals for the design of such a memory cell, particularly with respect to influence of technology fluctuations. Existing designs must be checked and generally modified given variation of the technology parameters, when switching to dimensionally-diminished geometries (shrink) and when changing the supply voltage. The limitation in the width of the selection transistors also limits the obtainable speed. In practice, the static semiconductor memories having six-transistor memory cells, data lines that are not selected are frequently pre-charged to a fixed potential. After a write access, the data line pair used for writing is additionally connected by a transistor in order to shorten the write recovery time by charge balancing between these two lines. The disturb reliability, the speed and the access time are increased as a result of these measures. It is also set forth in the aforementioned publication, Pages 244 through 255, that the data lines are generally supplied to a differential amplifier for fast ignition of the cell signal during reading. The discharging of one of these two data lines is then recognized in the differential amplifier. The evaluation occurs at a time at which the data lines have not yet reached a logical level, but only have a potential difference of a few hundred millivolts. The time thereby gained, however, is purchased at the expense of using an analog circuit that uses a large area and that, like the memory cell, is susceptible to technology-caused fluctuations of the operating point.
USPTO Backgrounds
USPTO Backgrounds