1. Field of the Invention
The invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device capable of suppressing a short channel effect and reducing a source/drain junction capacitance, and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor devices are developed having a high degree of integration, an active region becomes smaller in size. Thus, a gate length of a MOS transistor formed on the active region becomes shorter. As the gate length decreases, the influence of the source/drain upon the electric field or the potential in the channel region of the MOS transistor correspondingly increases. This is known as the “short channel effect” and a lowering of the threshold voltage is a typical result. This is because the channel region is greatly influenced by the depletion charge, the electric field, and the potential distribution of the source/drain regions as well as the gate voltage.
In addition to lowering the threshold voltage, a “punchthrough effect” between the source/drain is a severe problem accompanying the short channel effect.
Specifically, the drain depletion layer is widened in proportion to the increase in the drain voltage, so that the drain depletion layer comes close to the source region. Thus, the drain depletion layer and the source depletion layer are completely connected to each other when the length of the gate electrode is decreased. The electric field of the drain may eventually penetrate into the source region and thus reduce the potential energy barrier of the source junction. When this occurs, more major carriers in the source region have enough energy to overcome the barrier, and then, an increased current flows from the source region to the drain region. This is known as the “punchthrough” phenomenon. When the punchthrough occurs, the drain current is not saturated but dramatically increases in the saturation region.
The short channel effect becomes more severe as the source/drain junction depth is increased and the channel doping concentration is decreased. Various methods have been developed to form a shallow source/drain junction depth, whereby the short channel effect can be suppressed to some degree.
In general, the shallow source/drain junction is obtained with a low energy ion implantation process that lessens the physical junction depth in a silicon substrate, resulting in a decrease in the transistor current.
Furthermore, methods in which metal silicide layers are formed on the surface of the source/drain regions through a self-aligned silicide (i.e., salicide) process so as to reduce parasitic resistances in the source/drain regions, e.g., sheet resistance and contact resistance, with the decrease in the gate length have been used. However, as the source/drain junction depth becomes shallower, it becomes more difficult to apply the salicide process.
Accordingly, in order to obtain a high-performance transistor, the parasitic resistances in the source/drain regions should be minimized to increase the transistor current, while also suppressing the short-channel effect. The typical method is one where the MOS transistors are formed on a silicon-on-insulator (SOI) substrate. In the SOI transistor, a buried oxide layer is located under the source/drain junctions to remove a depletion capacitance of the source/drain junctions. However, the SOI transistor has a floating body because no body contact is formed on the SOI substrate. Therefore, a layer of accumulated holes is formed at the interface in the rear of the SOI layer, thereby generating floating body effects such as parasitic bipolar breakdown, latch-up, etc.
USPTO Backgrounds
USPTO Backgrounds