1. Field of the Invention
The present invention relates to a MOS analog NOR amplifier, and particularly relates to a CMOS analog NOR amplifier which employs CMOS analog amplifier technique to perform digital operations for use in building a programmable array logic (PAL) or other usages.
2. Description the Prior Art
The high speed programmable array logic (PAL) has been a key integrated circuit in building high speed digital systems such as supermini and supermicro computers. The requirement of access time for these high speed PALs is usually less than 15 ns (nanoseconds). Because of this requirement, commercially available high speed PALs are typically fabricated by advanced bipolar technology. Bipolar technology, however, is much more complicated and expensive than CMOS technology, but CMOS technology generally can not offer very high performance characteristics as those from bipolar technology, i.e., PALs constructed using CMOS technology have a much greater access time than those using bipolar technology.
A conventional CMOS NOR gate which may be used to build a PAL is illustrated in FIG. 1. As shown, there are two NMOS transistors connected in parallel forming NMOS drivers and two PMOS transistors attached in series constituting PMOS loads. With either terminal A or B at logic 1 the output terminal Y is at ground. No path is permissible between the output terminal and the power supply V.sub.DD. In case that the input terminals A and B are at logic 0, both NMOS transistors are closed and both PMOS transistors are opened, thus rendering the output terminal Y a logic 1.
In addition to the speed problem, the conventional CMOS NOR gate also has another drawback called "power bouncing problem". When the input terminal A is at logic 1 and input terminal B at logic 0, the output terminal Y is at logic 0. Then, if the input terminal A shift from logic 1 to logic 0, arises in that during the shifting of the status of input and output terminals, there will be an instant when all the NMOS and PMOS transistors are conducting and thus a current spike flowing from the V.sub.DD power supply to the ground produced. Similarly, when the output terminal Y shifts from logic 1 to logic 0, there will also be an similar current spike occurring but in reverse direction. These current spikes, because of the natural inductance within the logic circuits, produce noise voltage in the CMOS NOR gate, thus degrading the performance thereof. Furthermore, when the conventional CMOS NOR gates are employed to build an address decoder or the like, the CMOS NOR gate will consume an alternating current power from the V.sub.DD power supply due to the current spike aforementioned. Since the frequency of the spike depends on the frequency of addresses sent by the CPU, the alternating current power consumed also depends on the frequency of address signals delivered from the CPU, which is constantly varied. Hence, the needed power budget, i.e., the necessary V.sub.DD power capacity, cannot be easily controlled.
USPTO Backgrounds
USPTO Backgrounds