A conventional flash memory cell includes a gate stack, a source, a drain, and a channel disposed between the source and the drain. To form a conventional memory cell, a tunnel oxide is grown or deposited on a semiconductor substrate. Typically, the gate stack is formed on the tunnel oxide and reoxidized. Reoxidation exposes the gate stack to an oxidizing agent at a high temperature, growing a layer of oxide on the gate stack. The reoxidation of the gate stack of the conventional memory cell improves erase characteristics.
After the growth of the oxide layer is completed in reoxidation, the source and drain are implanted and annealed. Annealing electrically activates and diffuses the source and drain implants.
A conventional memory cell formed using the above-described process includes a bird's beak shaped tunnel oxide and a source dopant which decreases in concentration closer to the center of the gate stack. The "bird's beak" shaped tunnel oxide is thicker near the edge of the gate stack than closer to the center of the gate stack. Note that the edge is actually a three dimensional face of the gate stack. Consequently, as used herein, edge is a three dimensional face. Only closer to the center of the floating gate does the oxide have a relatively constant thickness. The concentration of source dopant is highest at the surface of the semiconductor adjacent to the gate stack in part as a result of the annealing step. Consequently, the concentration of source dopant decreases toward the center of the gate stack.
Although the conventional memory cell functions, erase of the conventional memory cell may not be well controlled. To erase a conventional memory cell, tunneling of charge carriers between the floating gate and the source is used. Tunneling of charge carriers between the floating gate and the source depends on the thickness of tunnel oxide through which the charge carriers tunnel and on the doping profile of the source. Both the thickness of the tunnel oxide and the concentration of the source dopant vary under the gate stack. The appropriate combination of tunnel oxide thickness and source doping profile may be difficult to control. Tunneling of charge carriers between the floating gate and the source is, therefore, difficult to control. As a result, the erase characteristics of conventional memory cells may vary between cells on the same semiconductor.
Accordingly, what is needed is a system and method for better controlling erase characteristics. The present invention addresses such a need.
USPTO Backgrounds
USPTO Backgrounds