Electrical erasable programmable read only memory (EEPROM) devices are continuously being developed to provide improved characteristics. Some of these developments include improving the ease of manufacturing the device, or adding new improvements without significantly compromising the manufacturing process of the device; increasing the density of the memory cells of the device to provide higher memory capacity for a given integrated circuit (IC) chip area; improving the reliability of the device to improve data retention and extend erase and programmable life span; improving the program efficiency and flexibility of the device to achieve lower programmable voltages and currents, and provide bit and byte programming of memory cells; and improving the erase efficiency and flexibility of the device to similarly achieve lower erase voltages, and provide bit, byte, sector, and/or array erasing of memory cells.
In the past, EEPROM devices have had shortcomings with respect to at least some of these characteristics. For instance, their memory cell structure and layout are generally inefficient resulting in relatively large memory cell size, relatively low data retention, limited erasing and programming life span, relatively high programmable voltages and currents, and relatively high erase voltages. These shortcomings are better explained below with reference to a particular conventional EEPROM device.
FIG. 1A illustrates a schematic diagram of an exemplary conventional EEPROM device 100. In this example, the EEPROM device 100 is shown to include an array of four (4) memory cells 102a-d for illustrative purposes. However, it is well known that typical EEPROM devices include arrays with much more memory cells (e.g., 103-106 memory cells, or higher). In this example, memory cells 102a and 102b share word line WL1, and memory cells 102c and 102d share word line WL2. Also, memory cells 102a and 102c share bit line BL1, and memory cells 102b and 102d share bit line BL2. In this example, the memory cells 102a-d are formed in and on a p-doped substrate (P-substrate) 104.
Each memory cell (102a-d) consists of an erase p-doped channel metal oxide semiconductor (PMOS) transistor (110a-d), a program PMOS transistor (114a-d), and an access n-doped channel metal oxide semiconductor (NMOS) transistor (118a-d). Each erase PMOS transistor (110a-d) is formed in a separate n-doped well (N-Well) (112a-d) formed in the P-substrate 104. Each program PMOS transistor (114a-d) is also formed in a separate N-Well (116a-d) in the P-substrate 104. Each access NMOS transistor (118a-d) is formed in a separate p-doped well (P-Well) (120a-d) formed in the P-substrate 104.
The sources (S), drains (D), and N-Wells 112a-b of the erase PMOS transistors 110a-b of the memory cells 102a-b are respectively electrically connected together, and connected to Erase Line 1. Similarly, the sources (S), drains (D), and N-Wells 112c-d of the erase PMOS transistors 110c-d of the memory cells 102c-d are respectively electrically connected together, and connected to the Erase Line 2. The sources (S) of the program PMOS transistors 114a and 114c of the memory cells 102a and 102c are electrically connected to the bit line BL1. Similarly, the sources (S) of the program PMOS transistors 114b and 114d of the memory cells 102b and 102d are electrically connected to the bit line BL2. The gate of each of the PMOS erase transistor (110a-d) is electrically connected to the gate of the corresponding program PMOS transistor (114a-d), which forms the floating gate (FG) for the memory cell (102a-d).
The drain (D) of each program PMOS transistor (114a-d) is electrically connected to the drain (D) of the corresponding access NMOS transistor (118a-d). The sources (S) of the access NMOS transistors 118a-d are electrically connected to ground potential (Gnd). The gates (G) of the access NMOS transistors 118a-b of the memory cells 102a-b are electrically connected to the word line WL1. The gates (G) of the access NMOS transistors 118c-d of the memory cells 102c-d are electrically connected to the word line WL2.
FIG. 1B illustrates a layout of the exemplary conventional memory cell 102a. The layout of the memory cell 102a is typically the same for the other memory cells 102b-d of the EEPROM device 100. As shown, the source (S) and drain (D) of the erase PMOS transistor 110a, in addition to being electrically connected together and to the Erase Line 1, is connected to the N-well 112a via a highly n-doped contact 111a. The source (S) of the program PMOS transistor 114a, in addition to being connected to the bit line BL1, is connected to the N-Well 116a via a highly n-doped contact 115a. Also, the source (S) of the access NMOS transistor, in addition to being electrically connected to ground potential, is connected to the P-Well 120a via a P+ contact 119a. 
FIG. 1C illustrates a schematic cross-section of the erase PMOS transistor 110a and program PMOS transistor 114a of conventional EEPROM device 100. As shown, the sources (S) and drains (D) of both the erase and program PMOS transistors 110a and 114a comprise a P+ contact region adjacent to a lighter P-doped region within the channel. The lighter P-doped region is typically employed to prevent avalanche breakdown due to high electric fields along the edges of the source (S) and drain (D) regions.
As discussed above, the conventional EEPROM device 100 has some shortcomings with regard to memory cell density, reliability, programming and erasing characteristics. For example, with regard to memory cell density, the memory cell includes separate N-Wells for the erase and program PMOS transistors. In addition, the spacing between the adjacent N-Wells is relatively large to ensure proper electrical isolation. Further, the memory cell includes a relatively large NMOS access transistor to carry the relatively large voltage and current needed for programming the cell while keeping the voltage drop Vds in the NMOS relatively small. These factors result in a memory cell occupying a relatively large chip area, which makes it difficult to provide higher memory cell density for this type of EEPROM device.
With regard to reliability, the large floating gate (FG) including the erase and program PMOS transistors results in a relatively large area, which results in larger current leakage. This adversely affects the data retention capability of the conventional EEPROM device. Because of the relatively large floating gate area, larger voltages and currents are generally needed for programming the memory cells. The relatively large program voltages also generally have an adverse effect on the programmable lifespan. Additionally, higher erase voltages are needed for erasing the memory cells.
USPTO Backgrounds
USPTO Backgrounds