Flip chip technology plays an important role in the packaging of semiconductor devices. A flip chip microelectronic assembly includes a direct electrical connection of face down electronic components onto substrates, such as circuit boards, using solder bumps as the interconnects. The use of flip chip packaging has dramatically grown as a result of the flip chips advantages in size, performance and flexibility over other packaging methods.
Recently, conductive pillar technology has been developed. Instead of using solder bumps, electronic components are connected to substrates by means of copper pillars. The copper pillar technology achieves a finer pitch with a lower probability of bump bridging, reduces the capacitance load of the circuits and allows the electronic components to perform at higher frequencies.
However, the standard pillar manufacture processes have a number of shortcomings. For example, standard conductive pillar manufacturing processes can create stress in the microelectronic assembly leading to cracks. The cracks may propagate to the underlying electronic components in the chip. The cracks can damage or destroy the electronic components thereby increasing the failure rate of the overall assembly.
Accordingly, there is a need for an improved structure and method to form conductive pillar for a semiconductor wafer with robust electrical performance.
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