As is well known, a non-volatile memory is able to continuously retain data after the supplied power is interrupted. A flash memory is one of the most popular non-volatile memories. Generally, each storage cell of the flash memory has a floating gate transistor. The storing status of the floating gate transistor may be determined according to the amount of the stored charges.
Recently, a novel non-volatile memory with a resistive element as the main storage element has been introduced into the market. This non-volatile memory is also referred as a resistive random access memory (RRAM).
FIG. 1 is a schematic cross-sectional view illustrating a conventional non-volatile memory with a resistive element. This non-volatile memory is disclosed in U.S. Pat. No. 8,107,274 for example. As shown in FIG. 1, the non-volatile memory 300 has a (1T+1R) cell. The term “1T” denotes one transistor. The term “1R” denotes one resistor. That is, the non-volatile memory 300 comprises a transistor 310 and a resistive element 320. The resistive element 320 is connected to the transistor 310. In addition, the resistive element 320 is a variable and reversible resistive element.
The transistor 310 comprises a substrate 318, a gate dielectric layer 313, a gate electrode 312, a first source/drain region 314, a second source/drain region 316, and a spacer 319.
The resistive element 320 comprises a transition metal oxide layer 110, a dielectric layer 150, and a conductive plug module 130. The dielectric layer 150 is formed on the first source/drain region 314. The conductive plug module 130 is disposed on the transition metal oxide layer 110.
The conductive plug module 130 comprises a metal plug 132 and a barrier layer 134. The metal plug 132 is vertically disposed over the transition metal oxide layer 110, and electrically connected with the transition metal oxide layer 110. The barrier layer 134 is arranged around the metal plug 132. The transition metal oxide layer 110 is formed by reacting a portion of the dielectric layer 150 with the barrier layer 134. The transition metal oxide layer 110 is capable of changing resistance.
Since the transistor 310 occupies the layout area of the substrate, the cell density of the (1T+1R) cells of the non-volatile memory 300 is relatively lower.
Therefore, there is a need of providing a non-volatile memory with high cell density in order to overcome the problems of the conventional technology.
USPTO Backgrounds
USPTO Backgrounds