1. Field of the Invention
The invention relates to an arrangement for decoding a stereo multiplex signal, comprising a baseband stereo sum signal (L+R), a stereo difference signal (L-R) which is amplitude-modulated on a suppressed subcarrier, and a pilot signal located between the frequency bands of the two signals, said arrangement having an input for the stereo multiplex signal and left and right stereo signal outputs, said input being coupled at one end via a pilot selection circuit to a phase-locked loop for regenerating the sub-carrier and, at the other end, to a multiplier circuit for multiplying at least the modulated stereo difference signal (L-R) by the regenerated subcarrier.
2. Description of the Related Art
An arrangement of this type is known from U.S. Pat. No. 4,249,038.
In the multiplier circuit of the known arrangement, the stereo difference signal (L-R) is synchronously demodulated to the baseband by means of a locally regenerated 38 kHz sub-carrier. In a dematrixing circuit, this baseband stereo difference signal (L-R) is subsequently both added to and subtracted from the baseband stereo sum signal (L+R). Consequently, decoded left and right stereophonic signals L and R are obtained which are available for further signal processing at the left and right stereo signal outputs.
In the known arrangement, the sub-carrier applied to the multiplier circuit is amplitude-controlled in dependence upon a mono-stereo control signal. Consequently, the demodulated baseband stereo difference signal also varies in amplitude resulting in a continuously controlled stereo channel separation. The local 38 kHz sub-carrier is supplied from the controllable oscillator of the loop and for a maximum stereo channel separation, it should be accurately in phase or an anti-phase with the suppressed 38 kHz sub-carrier in the stereo multiplex signal. To this end a 19 kHz oscillator signal is derived from this local sub-carrier by means of frequency division, which oscillator signal is locked in phase via the phase detector and the loop filter with the 19 kHz stereo pilot signal selected in the pilot selection circuit. This phase lock is established in that phase differences deviating from 90.degree. between the two latter signals result in a d.c. phase control signal which controls the phase of the oscillator signal after selection in the loop filter in such a way that the said phase differences are reduced. A selective amplification of the stereo pilot signal is obtained with the pilot selection circuit so that the phase quadrature relation between the stereo pilot signal and the oscillator signal in the phase-locked state of the loop is disturbed to a smaller extent by stereo signal components of the stereo multiplex signal and d.c. offset occurring in the loop.
However, in practice, an unpredictable, constant phase error between the local sub-carrier from which the oscillator signal is derived and the suppressed subcarrier in the stereo multiplex signal is found to occur. This phase error is mainly caused by the fact that the pilot selection circuit modifies the phase of the stereo pilot signal in a fixed and unpredictable quantity and direction, and moreover, because the phase disturbance due to d.c. offset occurring in the loop is not negligibly small in spite of the selective amplification of the stereo pilot signal. Since the stereo difference signal to be demodulated with the local sub-carrier is not an exact double sideband signal due to the filtering operations (for example in the IF filter) preceding the stereo decoding arrangement, the phase error gives rise to an unwanted crosstalk between the decoded left and right stereo signals, which crosstalk cannot be reduced by means of an amplitude correction. This crosstalk limits the maximum attainable stereo channel separation.
USPTO Backgrounds
USPTO Backgrounds