The present invention deals with an electronic data processing system of the type known in the art as a microprogrammed processor wherein a plurality of macroinstructions are stored in an addressable memory. In this type of system these macroinstructions are typically executed by a central processing unit which is controlled by a plurality of microinstructions similarly stored in an addressable memory.
In a microinstruction controlled data processing system of the type described herein the central processing unit typically contains an arithmetic logic unit for performing arithmetic and logical operations on data necessary to execute the various macroinstructions. The results of these arithmetic and logical operations must be stored for use in subsequent arithmetic and logical operations by the arithmetic logic unit. For example, one of the microinstructions used in executing a given macroinstruction may cause the arithmetic logic unit to output a result which will be temporarily stored and later retrieved to be operated on by the arithmetic logic unit under the control of a subsequent microinstruction. Typically, the storage means used for these results consists of a number of dedicated storage registers each of such registers being dedicated to the storage of a particular result and arranged to each be accessible to only one operand input of the arithmetic logic unit, and a general register or plurality of addressable general registers for storing those results for which there are no dedicated registers. It would be desirable in a data processing system of this type to minimize the number of dedicated storage registers required in the central processing unit and to make a plurality of addressable general registers accessible to each operand input of the arithmetic logic unit. It is also desirable in a system of this type to have the capability of directly addressing the general registers by way of microinstructions or by way of an address computed by the arithmetic logic unit. Further, it is desirable in a system of this type to have an interim data storage register independent of the general registers capable of storing a result outputted by the arithmetic logic unit.
Microprogrammed data processing systems are frequently used for controlling myriad external devices having differing real time control information requirements. Therefore, in many such systems, priority levels are assigned to the macroprogram sub-routines used for controlling various external devices, higher priority levels being assigned to those devices requiring shorter response times from the data processing system and lower priority levels being assigned to the devices where response time is less critical. In such systems dedicated hardware is typically included in the central processing unit which enables external devices needing control information to interrupt the execution of lower priority level macroinstruction sub-routines. Since it is desirable in small data processing systems to minimize hardware within the central processing unit, it would be desirable in such a system to have interrupts controlled by hardware not dedicated to that purpose but rather by the general purpose hardware already available.
Data processing systems are typically arranged to handle multibit binary data words consisting of a particular number of data bits, that is, the various buses for carrying data and the various registers and the other elements comprising the microprocessor system are arranged to handle a particular number of data bits. In order to minimize the use of dedicated hardware for addressing memory location, such addressing is frequently carried out using multibit binary data words consisting of the same number of data bits as other binary data words used in the system, thus limiting the number of addressable word locations in memory. It would be desirable therefore, to have in a processor system having a small word size memory, addressing means capable of addressing a number of word locations which is larger than the largest possible number which can be represented by the binary data word size chosen for the processor.
USPTO Backgrounds
USPTO Backgrounds