In integrated circuit (IC) designs middle of the line (MOL) contacts electrically connect the nodes of field effect transistors (FETs) to back end of the line (BEOL) metal levels. Specifically, a FET (e.g., a fin-type field effect transistor (FINFET), a gate-all-around FET (GAAFET), a planar FET, etc.) can include at least one channel region positioned laterally between source/drain drain regions and a gate adjacent to the channel region(s). The MOL contacts for such a FET can include: a gate contact on the gate; metal plugs (TSs) on the source/drain regions, positioned laterally adjacent to the gate and isolated therefrom by gate sidewall spacers; and source/drain contacts (CAs) on the metal plugs. Recently techniques have been developed for forming self-aligned metal plugs. However, with device size scaling, these techniques can result in metal plug to gate shorts and/or source/drain contact to gate shorts.
USPTO Backgrounds
USPTO Backgrounds