The present invention relates generally to programmable logic devices (PLDs). More particularly, the invention relates to a PLD having embedded random access memory.
Programmable logic devices (PLDs) generally include an array of uncommitted elements that can be interconnected in a general way. PLDs provide storage, logic, and wires in a standard package that can be programmed by the user according to the specification of the user to make an application specific integrated circuit (ASIC). When first introduced, PLDs had simple designs and were costly. Therefore, they were primarily used in prototypes and emulation systems. Currently, PLDs are relatively inexpensive and include all the features needed to implement highly complex hardware designs. As a result, they are used in preproduction applications as well as in marketed products.
It has become common to provide on-board random access memory (RAM) as part of the PLDs. When RAM is provided on a PLD, it may be configurable as logic elements, or it may be used to satisfy other memory requirements of the user's logic configuration. The RAM may be of a single-port or a dual-port. In case of a single-port RAM, the read and write operations are conducted through a single port, whereas, in case of a dual-port RAM, the read and write operations are conducted through separate ports thereby allowing simultaneous read and write operations.
However, a problem arises with the dual port memory when both the read and write ports access the same address simultaneously. If the write operation reaches the address prior to the read operation, then the data in the address would be over-written, which may result in data loss. One of the known approaches to ensure that the read operation occurs prior to the write operation includes, adding a delay to the write address enable signal. The delay ensures that there is enough timing separation between the read-port turn on and the write-port turn on. In order to ensure that the time margin between the read-port turn on and the write-port turn on is large enough to cover all the process corners, PLD designers assume a worst case and incorporate a number of delay elements to handle the worst case. These delay elements occupy valuable real estate space on the PLD. Additionally, the implementation of the delay elements restricts the minimum cycle time needed to support a “read-before-write” operation from the different ports since the worst case is always assumed. Moreover, there is additional work involved for the test engineers and production engineers to estimate the number of delay elements required and then evaluate whether the estimated delay elements are sufficient to cause the read operation to occur before the write operation.
Accordingly, there exists a need for a system and a method for a PLD with an embedded memory that provides read-before-write without the drawbacks described above.
USPTO Backgrounds
USPTO Backgrounds