For the design of digital circuits, designers often employ computer aided techniques. Standard languages, such as Hardware Description Languages (HDLs), have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
After the HDL code is written and compiled, the design of an integrated circuit (IC) or a system which includes multiple ICs must be verified to be correct. Continually advancing processing technology and the corresponding explosion in design size and complexity have led to verification problems for complex circuit designs, such as Application Specific Integrated Circuits (ASICs) that are difficult to solve using traditional simulation tools and techniques.
As a result, some designers build prototype boards using multiple ICs such as field programmable gate arrays (FPGAs) to verify their ASIC designs. However, there are still problems with debugging the hardware design. When an error is detected during debug, designers may attempt to tap signals of interest from the circuit and use a logic analyzer to determine the cause of the error. However, this is a difficult process and is often not effective, especially in the case of intermittent errors. Errors that have already occurred are often difficult to repeat and reconstruct.
USPTO Backgrounds
USPTO Backgrounds