Forming semiconductor devices typically includes subjecting a semiconductor substrate or assembly to a series of processing steps, each directed to adding, removing, and/or altering material. Cumulatively, these processing steps can form electrical components, e.g., transistors, capacitors, and diodes, precisely and at very high densities. Networks of electrical connections between the electrical components can be complex and, in modern semiconductor devices, typically extend over multiple layers. Connections from one layer to another layer can be formed in openings, which can be selectively etched in desired patterns. Openings can also be used to form electrical connections extending to bond pads or other contacts between semiconductor devices and associated packaging components. Openings typically are lined with a dielectric material, e.g., silicon dioxide, to electrically isolate metal within the openings from nearby structures. Depositing dielectric liners exclusively in openings can be technically challenging, so dielectric liners are generally formed by depositing a blanket or continuous dielectric layer and performing an etch-back process.
Conventionally, after a continuous dielectric layer is deposited, the dielectric material around the openings is removed using chemical-mechanical planarization with a suitable slurry. Conventional planarization processes with sufficient precision to remove a continuous dielectric layer without damaging underlying structures typically remove dielectric materials and metals at significantly different rates. This can lead to undesirable topography when dielectric materials and metals are planarized simultaneously. To avoid this, the wafer is typically planarized before filling the openings with metal. After planarization, a wet cleans process, e.g., a piranha etch, can be used to remove residual slurry in the openings. This conventional approach, however, can have certain disadvantages, at least some of which have heretofore been unrecognized or inadequately addressed. Accordingly, there is a need for innovation in this area and in related areas of semiconductor device manufacturing.
USPTO Backgrounds
USPTO Backgrounds