Current techniques to form solder bumps on an integrated circuit (IC) substrate such as a die, wafer, or package substrate may include, for example, plating, paste printing and/or ball placement techniques. Such solder bumping techniques are expensive and complex, particularly for solder bumps having different geometries on a same IC substrate.
Current techniques to form conductive traces such as copper traces of circuits and/or devices may use multiple processes and tools that utilize subtractive processes, which may waste material, resulting in high costs, particularly for low volume production. Screen printing processes have been used to simplify formation of conductive traces; however, screen printing may suffer from yield and/or conductivity issues relative to higher reliability sputter seed and plated traces, which are more costly to produce.
USPTO Backgrounds
USPTO Backgrounds