Field of the Invention
The present invention relates, in general, to voltage regulation circuits and, more particularly, to a bias-starving circuit for improving the stability of an LDO (Low-Drop Out) voltage regulator driving a switched capacitive load.
Relevant Background
Voltage regulation circuits are used to modify, tune, and stabilize off-chip voltages towards usage for on-chip supply rails. Besides the elimination, or substantial reduction, of RLC (Resistor, Inductor, Capacitor) package-induced voltage disturbances, regulators allow designs for a single supply voltage level without having to cover the ±5% to ±10% external supply variations. Such regulation circuits are often implemented with a topology comprised of an error amplifier OTA (Operational Transconductance Amplifier) and a driver device, and their output feeds a storage, or decoupling, capacitor Cout. The size of the driver device allows minimization of the ΔV between the externally provided supply rail V+ and the regulated voltage Vout, which justifies the name LDO's (Low Drop Out) used for such circuits.
A typical LDO regulation circuit 100 is shown in FIG. 1, and includes an operational amplifier 102 having a negative input for receiving an external VREF reference voltage, and a positive input having a VREFL reference voltage. The VREFL reference voltage is substantially equal to the VREF reference voltage due to the feedback circuitry described in further detail below. The output of amplifier 102 drives the gate of the P-channel driver transistor 104. The source of driver transistor 104 is coupled to the V+ supply voltage. The drain of driver transistor 104 is the output of the regulator, providing the VOUT output voltage. A feedback resistor RF is coupled between the VOUT output terminal and the positive input of amplifier 102. A trimmable resistor RS coupled between the positive input of amplifier 102 and ground allows adjustment of the VOUT voltage level. The controlling signal for setting the resistance of RS is often a digital word. The output of the regulator circuit 100 drives a load Z(s), as well as a storage, or decoupling, capacitance COUT. As is known by those skilled in the art, the regulated output voltage VOUT=VREF*(RF/RS+1), and is substantially immune from variations in the V+ power supply voltage.
The impedance nature of the load Z(s) determines by and large the AC, i.e., the stability, characteristic of the regulation loop. LDO's feeding analog circuits often drive a
            Z      ⁡              (        s        )              =          R      +              1                  s          ·          C                      ,due to a part of the load drawing a continuous DC current and a part drawing a frequency-dependent current, usually associated with a capacitive load. The usually large (hundreds of milliAmps) currents drawn into the driver device guarantee a predictable bias current, and therefore, gm, of the driver device (or circuit).
However, the LDO can be used to regulate an internal supply rail that feeds, e.g., only digital logic. In this case, if the logic is of the ECL (bipolar) type, its current consumption is also predictable; but in the CMOS case, the Z(s) load is exclusively of the capacitive kind, i.e.
            Z      ⁡              (        s        )              =          1              s        ·        C              ,which is entirely frequency-dependent. The gm of the second stage, or driver, of the LDO, is therefore substantially changing with the switching frequency of the digital circuitry, since the DC current drawn by the switching capacitive loads is ILOAD(f)=Cload·VDD·f.
The load-dependent nature of the ILOAD, and therefore of the gm, of the driver stage of the LDO leads to stability issues of the regulator loop. It has been observed in the prior art that an increase in gm of the driver stage requires a compensating decrease in gm, and slow-down of the poles, of the error amplifier in front of it. A technique of current-starving of the OTA controlling the driver performs a dominant-pole compensation of the loop, when the stabilizing effect of the R-C zero added to the Miller compensation scheme is diminished due to gm increase. In fact, two approaches can be followed for the regulator loop.
Firstly, a broad-band approach with fast poles in the amplifier requires cascading a number of low-gain stages, that adds a number of singularities in the Bode plot and can lead to lower precision of the loop (i.e. lower GLOOP values).
Secondly, a high-gain approach with a high-impedance OTA entails the presence of two poles (the main Cout and Rout, and the OTA output impedance into the gate capacitance of the driver device), both quite slow, that is usually stabilized by way of a Left-Half Plane LHP zero, found at
  Z  =      1                  C        COMP            ·              (                              1                          g              m                                -                      R            COMP                          )            
Some prior art techniques sense the changing load on the regulator by paralleling a second device to the main driver and feeding back its own current, to either modify a pole/zero compensation network or adaptively vary the driver current and/or the OTA current. These techniques inherently slave the loop bias to the desired output voltage, which however can be varied independent of the load's switching frequency.
While these known techniques provide some benefit for stabilizing an LDO regulator circuit, they all suffer from potential under or over correction. What is desired is a circuit and method of stabilizing an LDO regulator while monitoring the final precision of the regulated voltage against the desired set-up point, with even greater precision and control than is possible given the current state of the art.
USPTO Backgrounds
USPTO Backgrounds