1. Technical Field
The subject of the present disclosure is a voltage shifter for high voltage operations, in particular for nonvolatile storage devices.
2. Description of the Related Art
As is known, storage devices include a memory array formed by rows and columns, in which each row of the array is associated with a wordline connected to a row driver or row buffer, which is part of a row decoder and has the purpose of controlling the voltage level supplied to the respective wordline. In particular, according to the operation that it is desired to execute, each row driver supplies the appropriate voltage for reading the cells connected to the respective wordline; i.e., it enables the paths that, through access transistors (selection transistors and byte switches), supply the cells with suitable writing or programming voltages.
To this end, each row driver includes an output stage forming a voltage shifter that is able to transform information of a digital (on/off) type, generated by a control-logic circuitry, into an analog output voltage, the value of which can vary, in some embodiments, between 3 and 16 V.
The basic structure of a voltage shifter 1 available on the market and that can be used in a row driver is illustrated in FIG. 1. The voltage shifter 1 includes a latch 2, formed by a first latch transistor 3 and by a second latch transistor 4 (both of a PMOS type); an inverter 5; an intermediate biasing stage 11, formed by a first and a second biasing transistor 12, 13 (both of an NMOS type); and an output branch 6, including a first output transistor 7, of a PMOS type, and a second output transistor 8, of an NMOS type.
A supply line 10 supplying a high supply voltage VH (typically, generated by a charge-pump circuit—not illustrated) is connected to the drain terminals of the latch transistors 3, 4 (defining a first and a second input node 16, 17) and to the respective bulk terminals; a selection signal SEL is supplied on an intermediate biasing input 15 and is supplied directly to the first input node 16 and, after being inverted by the inverter 5, to the second input node 17.
The latch transistors 3, 4 have gate terminals connected in a crossed way to the drain terminal of the other latch transistor 4, 3 (second input node 17 and first input node 16). The drain terminal of the second latch transistor 4 is further connected to the output branch 6, which includes a first output transistor 7, of a PMOS type, and a second output transistor 8, of an NMOS type, connected in series between the supply line 10 and a first reference potential line (ground). The output transistors 7 and 8 have gate terminals connected together and to the second input node 17, and define, in the common connection point, an output terminal 9, for example connected to a wordline (not illustrated), supplying an output signal OUT.
The first and second biasing transistors 12, 13 are connected in series respectively to the first and to the second latch transistors 3, 4; they have gate terminals connected together and to a biasing input 14 and source terminals connected respectively to the input and to the output of the inverter 5. The biasing input 14 receives a biasing voltage VP generated by a supply stage (not illustrated) and has approximately a value equal to Vdd+Vth-200 mV (where Vdd is the general supply voltage of the device that englobes the voltage shifter 1, and Vth is the threshold voltage at 10 nA of the MOS transistors 12, 13). The biasing voltage VP, by increasing the overdrive of the transistors 12, 13, enables a proper operation thereof also for supply voltages Vdd close to the threshold of the transistors, improving the switching speed thereof; it moreover minimizes the leakage current thereof, thus reducing absorption by the charge pump (not illustrated) that generates the operating supply voltage VH. For further information on the operation of this stage see the U.S. Pat. No. 7,504,862 filed in the name of De Sandre et al., in particular with reference to FIG. 6 and the corresponding description (transistors M1, M2 and voltage VG).
Consequently, when the selection signal SEL is high, the first latch transistor 3 is on, the second latch transistor 4 is off, and the first output transistor 7 connects the output terminal 9 to the supply line 10. Instead, if the selection signal SEL is low, the latch 2 switches and the second output transistor 8 grounds the output terminal 9.
In this way, when the selection signal SEL is high (at Vdd), the output terminal 9 receives the operating supply voltage VH, which can assume values of up to 15-16 V.
The known voltage shifter 1 is very simple but, in some applications, may present the following disadvantages:
1. it includes only high voltage transistors, which have a considerable bulk (due to the tolerances, to the biasings, etc.) and can have high parasitic capacitances;
2. when the operating supply voltage VH reaches high values (15-16 V), the drain/bulk junctions of the transistors 3, 4, 7 and 8 may undergo breakdown; moreover the gate oxides are subject to voltage drops equal to the entire value of the operating supply voltage VH; this gate stress, in the long run, can generate trapping of charges on the oxide/semiconductor interface and bring about a worsening of the gain and a raising of the threshold voltage of the transistors.
USPTO Backgrounds
USPTO Backgrounds