1. Field of the Invention
The present invention relates to a memory circuit which requires a refresh operation for maintaining stored data, such as a dynamic RAM (DRAM), and more particularly to a dynamic memory circuit which automatically performs a refresh without requiring a refresh instruction from outside.
2. Description of the Related Art
A DRAM, which is widely used as a large capacity memory device, uses a volatile memory cell which consists of one transistor and one capacitor, so a periodic refresh is necessary to maintain stored data.
Generally speaking, refresh is classified into auto refresh, which is performed by responding to an external command in normal mode, and self refresh, which the memory device automatically performs in power down mode.
Before describing refresh, a configuration of a conventional synchronous type dynamic memory circuit will be described. FIG. 24 shows a configuration of a conventional synchronous type dynamic memory circuit. The memory circuit shown in FIG. 24 comprises two memory banks BANK0 and BANK1, which are the memory core. The peripheral circuits shared by these memory banks are, a clock input buffer 10 which inputs a clock CLK from outside according to the state of a clock enable signal CKE and supplies an internal clock CLK1 to internal blocks, a command decoder 12 which latches a command input CMD from outside and decodes it, an address buffer 14 which latches an address from outside, a data input/output buffer register 16 which outputs or inputs data to the data input/output terminal DQ, a self refresh control part 18 which generates an internal self refresh signal S-REF1 responding to a self refresh command S-REF, and a refresh address counter 22.
In each memory bank, a plurality of blocks BLK which have a memory cell array MC, a row decoder RDEC and a sense amplifier SA and a column decoder CDEC respectively, a command latch 24 shared by the blocks BLK, a control circuit 26 which supplies control signals corresponding to the block responding to various commands RD, WR and REF from the command latch 24, and a selector 28 which selects either a refresh address from the refresh address counter 22 or an external address from the address buffer 14, are disposed. The blocks BLK are connected to the input/output data bus I/ODB, which is shared by the banks, via the data bus DB, and the sense buffer/write amplifier SB/WA.
Auto refresh is performed in normal mode where data is read or written, responding to an external command. In this case, refresh refers to a procedure to select a memory cell MC, amplify the information by the sense amplifier SA, and rewrite it back to the memory cell. Therefore a write or read operation cannot be instructed to the memory cell block during refresh. So in normal mode, a refresh operation is executed responding to an auto refresh command from outside, so that the refresh operation does not collide with a read or write operation. An address to select a memory cell to be refreshed, however, is automatically generated inside the memory device. This is xe2x80x9cauto refreshxe2x80x9d.
Specifically, in a prior art in FIG. 24, a refresh signal REF is latched by the command latch 24 when the auto refresh command A-REF is input from outside, and the control circuit 26 controls the refresh operation based on the refresh signal REF. The refresh address is automatically generated by the refresh address counter 22, and the selector 28 selects and supplies a refresh address to the memory block BLK responding to a select signal SEL supplied by the control circuit 26 during refresh. The refresh address counter 22 is counted up eachtime refresh is performed.
Self refresh, on the other hand, is. a refresh automatically performed by the device in power down mode. In power down mode, the memory device deactivates input buffers 10, 12 and 14, so as to stop receiving input signals from outside, and also stops supplying the clock CLK1 to the inside. In this state,a periodic refresh is necessary. So the self refresh control part 18 starts the operation when the device enters power down mode by a clock enable signal CKE to instruct power down. The self refresh control part 18 generates a self refresh instruction signal S-REF1 responding to a timing signal which the oscillator 20, mounted on the device, generates at a predetermined cycle, and the control circuit 26 controls the refresh operation based on the signal S-REF1. The operation of the refresh address counter 22 and the selector 28 is the same as auto refresh.
When such a memory device (DRAM) is mounted in a computer system, refresh has a problem. Especially when auto refresh is performed in normal operation mode, the controller device controlling the memory device must manage the refresh timing of the memory device and supply a refresh command periodically. This control becomes a burden for the controller device.
Also, the memory controller cannot issue a read or write command during the period of auto refresh, which interferes with increasing the speed of the system. To solve this problem, it is discussed in Japanese Patent Laid-Open No. 61-71494 that one write or read operation cycle is divided into two time zones, wherein a write or read operation is performed during one of the time zones, and a refresh operation is performed during the other time zone. However, the semiconductor storage device of this patent has a relatively slow operation speed, and this invention cannot be simply applied to current synchronous type memory devices.
In the case of a synchronous type memory device (SDRAM), where the command cycles are controlled synchronizing with the clocks to be supplied, the activation of the memory core and a read or write operation are all controlled by commands to be supplied, synchronizing with the clocks. Also the operation cycle is fast. Therefore during a normal operation mode period, a voluntary refresh operation by the memory device is inhibited so that a read or write command to be supplied at an arbitrary timing can be handled, as mentioned above. As a result, the outside memory controller controls refresh during the normal operation mode period, and supplies an auto refresh command at a predetermined timing.
Also, in the case of a synchronous type memory device, a read operation and a write operation are not always controlled at the same timing. So it is difficult to execute a read or write operation during one of the two time zones and execute a refresh operation during the other time zone, as in the above mentioned prior art.
With the foregoing in view, it is an object of the present invention to provide a dynamic memory circuit which does not require refresh control by the memory controller.
It is another object of the present invention to provide a dynamic memory circuit which can automatically perform a refresh operation even in normal operation mode.
It is still another object of the present invention to provide a dynamic memory circuit where increasing the speed of the system is not interfered by a refresh operation.
It is still another object of the present invention to provide a dynamic memory circuit which has a new internal operation cycle and can automatically perform a refresh operation internally.
To achieve the above objects, a first aspect of the present invention is that in a dynamic memory circuit, first and second internal operation cycles are assigned to one external operation cycle according to external commands, a memory core performs a read operation which corresponds to a read command at the first internal operation, and performs a refresh operation which responds to a refresh command at the second internal operation cycle. Also the memory core performs a refresh operation which responds to a refresh command at the first internal operation cycle, and performs a write operation which corresponds to a write command at the second internal operation cycle. It is preferable that when the read or write command is not input, the refresh operation is performed at the earlier internal operation cycle. And a refresh command generation circuit which generates the refresh command at a refresh time is created in the memory circuit.
According to the above first aspect of the invention, the refresh operation is performed responding to the refresh signal generated in the memory circuit, so the memory controller need not supply a refresh command to the memory circuit, which eliminates the burden of managing the refresh operation. The refresh operation is performed at one of the internal operation cycles, and the other internal operation cycle is used for an operation responding to a command from the memory controller, so the memory controller can supply such a command as a read and write command without considering the refresh timing of the memory circuit. Also, the internal operation corresponding to the command does not delay according to the refresh time.
The memory core performs a read operation, which can be executed relatively quickly, at the first internal operation cycle, performs a write operation, which is executed relatively slowly after inputting the write data, at the second internal operation cycle, and during the read operation, the memory core performs a refresh operation at the second operation cycle, and during the write operation, the memory core performs a refresh operation at the first internal operation cycle.
A second aspect of the present invention is a dynamic memory circuit wherein the memory core is logically comprised of a plurality of blocks, for example, a first and second block. And first and second internal operation cycles are assigned to one external operation cycle according to external commands. Responding to one command (read or write) from outside, this command is executed for the first block at the first internal operation cycle, and this command is executed for the second block at the second internal operation cycle. On the other hand, responding to a refresh signal internally generated, refresh for the first block is executed at the second internal operation cycle, and refresh is executed for the second block at the first internal operation cycle.
According to the above mentioned second aspect, the command is executed in the first and second blocks at the first and second internal operation cycles respectively, responding to the external command, so that a fast speed can be maintained. In the first and second blocks, a refresh operation which responds to the refresh signal is executed using the internal operation cycle where operation for a command is not executed, so operation corresponding to the command and the refresh operation do not conflict with each other. In this case as well, the memory controller need not manage the refresh of the memory circuit, and can issue regular commands without concern for the refresh operation.
A third aspect of the present invention is a dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising a memory core. having the memory cells and a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein first and second internal operation cycles are assigned to one external operation cycle according to an operation command including a read command and a write command, the memory core, responding to the read command, performs a read operation at the first internal operation cycle, and then performs a refresh operation responding to the refresh command at the subsequent second internal operation cycle, and the memory core, responding to the write command, performs a refresh operation responding to the refresh command at the first internal operation cycle, and performs a write operation at the second internal operation cycle.
A fourth aspect of the present invention is a dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising a memory core having a plurality of memory blocks including the memory cells, and a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein a plurality of internal operation cycles are assigned to one external operation cycle according to an operation command, the memory core, responding to the operation command, performs an internal operation corresponding to the operation command in the plurality of memory blocks at each one of the plurality of internal operation cycle respectively, and performs the refresh operation corresponding to the refresh command in the memory block at an internal operation where a corresponding internal operation is not performed.
A fifth aspect of the present invention is a dynamic memory circuit which has volatile memory cells and performs a refresh operation at a predetermined timing, comprising a memory core having first and second memory blocks which include the memory cells respectively, and a refresh command generation circuit which generates a refresh command responding to a refresh signal generated at a predetermined timing, wherein 2N (N is an integer of 1 or more) internal operation cycles are assigned to one external operation cycle according to an operation command, the above mentioned memory core, responding to the operation command, performs an internal operation corresponding to the operation command of the first and second memory blocks at each one of the 2N internal operation cycles respectively, and performs a refresh operation corresponding to the refresh command in the memory blocks at an internal operation cycle where a corresponding internal operation is not performed.
The above mentioned fifth aspect of the present invention may comprise 2M memory blocks in the memory core.
In a preferred embodiment of the above mentioned invention, the memory core further comprises word lines, bit lines crossing thereof, a sense amplifier to be connected to the bit lines, and the memory cells in association to the word lines and the bit lines, and the memory core activates the word line and the sense amplifier then precharges the bit lines during the internal operation cycle, responding to the operation command.
USPTO Backgrounds
USPTO Backgrounds