1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and, more particularly, to a reference fail bit verification circuit in a non-volatile semiconductor memory device that checks for un-erased memory cells
A claim of priority is made to Korean Patent Application No. 10-2006-1803 filed on Jan. 6, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
In non-volatile semiconductor memory devices, the data programmed in the memory cells of a unit block is simultaneously erased during the erase operation. The erase operation generally includes two processes—an erasing process and an erase verifying process. In the erasing process, the trapped charges in the floating gate of the memory cell are returned to the bulk by the potential difference between the control gate and the bulk of the memory cell. In the erase verifying process, a verification is made as to whether the data of the memory cells is erased or not. The erase verifying process usually uses a fail bit number and a reference fail number to determine whether the memory cells have been satisfactorily erased.
For example, if the fail bit number is equal to or more than the reference fail number, the erasing process is repeated. In this specification, the ‘fail bit number’ means the number of memory cells that are not erased despite the performance of the erasing process.
The erase operation can be divided into two modes. In the first mode, if it is detected in the erase verifying process that the ‘fail bit number’ is equal to or more than the ‘reference fail number’, the voltage induced in the bulk is increased in steps during the erasing process. On the other hand, in the second mode, if it is detected in the erase verifying process that the fail bit number is equal to or more than the reference fail number, the voltages of the bulk and the control gate are maintained at a constant level in the erasing process.
Meanwhile, as is well known to one skilled in the art, the non-volatile semiconductor memory device includes a reference fail bit verification circuit to check whether the fail bit number is equal to or more than the reference fail number.
FIG. 1 is a block diagram showing a conventional reference fail bit verification circuit 10. Referring to FIG. 1, a fail bit counter 12 counts fail bits (i.e., un-erased memory cells) with a fail check signal XFUR At this time, when the amount of fail bits equals the reference fail number, a counting signal FCNT<i> is activated. Furthermore, a fail bit verification latch unit 14 generates a reference bit verification signal VLTF by latching the counting signal FCNT<i>.
While the conventional reference fail bit verification circuit may be used to determine whether the fail bit number is equal to or more than the reference fail number, it has several shortcomings. For example, in the conventional reference fail bit verification circuit 10, the reference bit verification signal VLTF is activated in response to the activation of the counting signal FCNT<i>. That is, in the conventional reference fail bit verification circuit 10, the reference fail number is set as one value without considering the type of mode used in the erase operation. Setting the reference fail number irrespective of the mode of erase operation used may lead to a number of problems.
For example, when the reference fail number is set as one value without considering the kind of mode, as described above, the overall time required to perform the erase operation may be very long. That is, when the reference fail number is set high, the time required for one erase cycle may be short but because a number of memory cells may not have been properly erased, the erase distribution may become worse.
On the other hand, if the reference fail bit number is set low, the erase distribution may be improved. However, some of memory cells may be over-erased. This over-erasure of some of the memory cells may increase the post-program time. Thus, the overall erase time is increased.
As described above, it may be difficult to set the reference fail number appropriately in the conventional reference fail bit verification circuit. This may lead to an overall increase in the time taken for an erase operation of the memory cells in a semiconductor device.
The present disclosure is directed towards overcoming one or more problems associated with the conventional reference fail bit verification circuit.
USPTO Backgrounds
USPTO Backgrounds