The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a bipolar transistor having a so-called base self-alignment structure, and a method of manufacturing a semiconductor device in which a so-called narrow-base heterojunction bipolar transistor using silicon germanium mixed crystal for a base layer and a general silicon homojunction bipolar transistor are formed on the same substrate.
There has been proposed a silicon-based narrow-base type heterojunction bipolar transistor which uses a base of silicon germanium (Si.sub.1-x Ge.sub.x) as a material which can narrow the band gap in order to further increase the maximum cut-off frequency of the bipolar transistor (hereinafter referred to as fTmax), and fTmax of about 100 GHz or more has been reported. An information communication field has been considered as an application field because the multimedia age has come and much attention has been paid to the market possibilities thereof.
The high-speed bipolar transistor uses a so-called double polysilicon structure in which polysilicon thin films are used for an emitter electrode and a base electrode and an emitter/base self-alignment structure. The adoption of the self-alignment technique provides advantages that the emitter length can be set to the limit value of the exposure light width or less, and also that a parasite transistor portion is removed.
The heterojunction bipolar transistor which adopts a silicon germanium thin film for the base layer in the above structure is disclosed in Japanese Examined Patent Application No. Hei-6-66325.
However in a manufacturing method as disclosed in Japanese Examined Patent Application No. Hei-6-66325, in order to form a silicon germanium base region in a link base region 142 as shown in FIG. 1A, a part of the thin link region 142 is oxidized to form a thermal oxide layer 152 by a high-pressure oxidation technique. Thereafter, the thermal oxide layer 152 is removed by an etching treatment to remove the link base region 142 (a portion indicated by two-dotted chain line) which will serve as the silicon germanium base region as shown in FIG. 1B, which complicates the process.
Thereafter, a layer 154 which will serve as a P-type silicon germanium base region is formed on the overall surface as shown in FIG. 2A, and then an N-type emitter region 162 is formed by diffusion from a polysilicon layer 160 formed of N.sup.+ -type polysilicon on the layer 154 as shown in FIG. 2B.
Therefore, if the N-type emitter region 162 is formed shallowly, the P-type silicon germanium microcrystal layer on a side wall 148 would remain, so that a base leak current may increase. Here, the microcrystal means such a state that minute crystalline layers are contaminated in an amorphous layer. Accordingly, it is difficult to independently control the width of the layer 154 serving as the silicon germanium base region and the depth of the N-type emitter region 162.
Further, when a bipolar transistor LSI is actually implemented, an LEC (Lightly Emitter Concentration) type bipolar transistor which has a higher grounded emitter current amplification factor .beta. and a high emitter/base withstand voltage, a bipolar transistor which is not so high in speed, but high in precision, etc. are needed on the same substrate in addition to the high-speed narrow-base heterojunction bipolar transistor using the silicon germanium layer as the base, if occasion demands. Accordingly, it is necessary to form a bipolar transistor in accordance with an application.
The present invention is directed to a method of manufacturing a semiconductor device in order to solve the above problem.
That is, according to a semiconductor device manufacturing method, the first bipolar transistor and the second bipolar transistor are formed on a semiconductor substrate, and a link base layer for connecting a graft base layer of the first bipolar transistor and an intrinsic base layer formed by an epitaxial growth method, and at least a part of a base layer of the second bipolar transistor are formed at the same time.
The above manufacturing method further includes a step of removing the link base layer which will serve as a region where the intrinsic base layer of the first bipolar transistor is formed, and a step of forming the intrinsic base layer in the region where the link base layer is removed, by the selective epitaxial growth method.
As another manufacturing method, after a side wall for separating the base and the emitter of the first bipolar transistor is formed on the side wall of an opening portion which is formed on the area where the intrinsic base is formed, and then the link base layer which will serve as the region where the intrinsic base layer of the first bipolar transistor is formed is removed. The film which is formed at the lower portion of the side wall and used as a buffer layer when the link base layer is formed is removed, and then the intrinsic base layer is formed in the area where the link base layer and the film used as the buffer layer are removed, by the selective epitaxial growth method.
In the above manufacturing method, since the link base layer for connecting the graft base layer of the first bipolar transistor and the intrinsic base layer formed by the epitaxial growth method, and at least a part of the base layer of the second bipolar transistor are formed at the same time, a large number of steps are not required to be added, and thus two kinds of bipolar transistors can be formed on the same substrate.
Since the intrinsic base layer is formed in the link base layer removed region by the selective epitaxial growth method, no P-type silicon germanium microcrystal is formed in an area other than the region where the intrinsic base layer is formed, for example, on the side wall which is formed to separate the emitter and the base. Therefore, the base width of the intrinsic base layer of silicon germanium and the depth of the emitter layer formed on the upper side of the intrinsic base layer are controlled independently of each other.
Further, since the intrinsic base layer of the first bipolar transistor is formed after the film which is formed at the lower portion of the side wall for separating the base and the emitter of the first bipolar transistor and used as the buffer layer when the link base layer of the first bipolar transistor is formed. The end portion of the intrinsic base layer formed by the selective epitaxial growth is far away from the emitter layer formed on the upper side of the intrinsic base layer by the distance corresponding to the thickness of the film which is used as the buffer layer and removed. Therefore, the end portion of the intrinsic base layer in which some defect is liable to occur is sufficiently far away from the emitter/base junction portion, so that the emitter/base junction can be stably formed.
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