The manufacture of integrated circuit devices involves intricate processes for creating circuit patterns on semiconductor wafers. Along with the highly developed technologies used to manufacture the integrated circuitry, highly developed testing processes are also necessary. The extremely small scale at which the circuitry is created demands such testing techniques in order to detect electrical failures earlier in fabrication processes. This is increasingly important to shorten product development cycles and to increase product yield and productivity.
Test processes for semiconductor manufacturing involves inspection and review stages. First, a semiconductor wafer can be inspected with an electron beam inspection system that detects electrical failures, for example as voltage contrast defects. The inspection process involves a high level scan of a wafer to identify and locate potential defects. Then, after the potential defects are located, a review process is conducted. The review process involves a much more detailed examination of individual potential defects. Through the review process, additional information regarding each potential defect can be obtained. For instance, the size, shape, general nature, and cause of a defect can be determined.
Typically, scanning electron microscopes (SEM) used for review processes are set to emit an electron beam at a much lower current level than that used by SEM inspection systems. For example, a typical SEM inspection tool generates an electron beam in the range of 20 to 200 nano-Amps and a typical SEM review system generates an electron beam in the range of 10 to 50 pico-Amps. The lower beam current allows the SEM review system to obtain higher resolution data. However, this also makes it more difficult to locate the voltage contrast defects found by the inspection system. The low beam current cannot provide the sufficient charge required for the voltage contrast defects to manifest themselves for review. Unfortunately, the inability to locate a voltage contrast defect during the review process eliminates any possibility of reviewing the defect and gaining any additional information about particular manufacturing processes.
In view of the foregoing, semiconductor review process that can more effectively locate and review voltage contrast defects at high resolution levels would be desirable.
USPTO Backgrounds
USPTO Backgrounds