1. Field of the Invention
The present invention relates generally to a display device, and particularly, to a liquid crystal display device capable of suitably displaying an image irrespective of the total number of dots in a horizontal period of an input image signal.
2. Description of the Prior Art
In a liquid crystal display device, one of dots represented by dot data of an input image signal and one of pixels composing a liquid crystal panel are synchronized with each other in one horizontal scanning period, to display an image. Line data representing one horizontal scan line out of an arbitrary number of line data in one vertical scanning period of the input image signal is displayed in correspondence with one line in the vertical direction of the liquid crystal panel. The line data is a set of dot data.
In recent years, computers with a large variety of specifications have been fabricated. An image signal shown in FIG. 6 and an image signal shown in FIG. 7 differ in the total number of dots in a horizontal period (hereinafter referred to as the total of horizontal dots), for example, even if they are XGA (Extended Graphic Array) image signals outputted from various types of computers. In the XGA image signals, the respective total numbers of dots within an image effective period in the horizontal period (hereinafter referred to as the number of horizontal effective dots) are common. That is, the number of horizontal effective dots of the XGA image signal is 1024. The position where the image effective period starts shall be referred to as a horizontal image start position, and the position where the image effective period ends shall be referred to as a horizontal image end position.
Sampling clocks for sampling 1024 dots within the image effective period in the horizontal period of the inputted XGA image signal are generated on the basis of a horizontal synchronizing signal of the inputted XGA image signal. Consequently, a method of generating the sampling clocks must be changed depending on the total number of horizontal dots of the inputted XGA image signal. Therefore, it is necessary to recognize the total number of horizontal dots of the inputted XGA image signal in order to generate the sampling clocks.
Conventionally, a table storing the total number of horizontal dots has been prepared for each type of XGA image signals, where the type of the XGA image signal is judged from the characteristics of the XGA image signal inputted from the computer, and the total number of horizontal dots corresponding to the judged type is selected from the table, thereby recognizing the total number of horizontal dots of the inputted XGA image signal. However, this method cannot cope with the XGA image signal generated by a computer with a new specification.
An object of the present invention is to provide a display device capable of generating suitable sampling clocks with respect to a plurality of types of image signals whose respective numbers of horizontal effective dots have been known and whose respective totals of horizontal dots differ from each other and which is, therefore, capable of displaying a suitable image with respect to a plurality of types of image signals whose respective numbers of horizontal effective dots have been known and whose respective totals of horizontal dots differ from each other.
A first display device according to the present invention comprises a clock generation circuit for generating sampling clocks, whose frequency is variable, on the basis of a horizontal synchronizing signal of an input image signal; an analog-to-digital converter for sampling the input image signal on the basis of the sampling clocks generated from the clock generation circuit; calculation means for calculating the number of sampling clocks outputted from a horizontal image start position to a horizontal image end position in image data outputted from the analog-to-digital converter, comparison means for comparing the number of sampling clocks calculated by the calculation means with a previously set value; and control means for controlling the frequency of the sampling clocks outputted from the clock generation circuit on the basis of the results of the comparison in the comparison means.
An example of the clock generation circuit is one comprising a voltage control oscillator for outputting the sampling clocks, a frequency divider for dividing the frequency of the sampling clocks outputted from the voltage control oscillator, phase detection means, to which an output signal from the frequency divider and the horizontal synchronizing signal of the input image signal are inputted, for outputting a detection signal corresponding to the phase difference between both the inputted signals, and filter means for integrating the detection signal outputted from the phase detection means, to output the integrated detection signal to the voltage control oscillator. In this case, the frequency division ratio of the frequency divider is controlled by the control means.
An example of the calculation means is one comprising a detection circuit for respectively detecting the position where the horizontal image starts and the position where the horizontal image ends on the basis of the data outputted from the analog-to-digital converter, a counter for calculating the number of first sampling clocks outputted from the clock generation circuit from the timing at which the horizontal synchronizing signal of the input image signal is outputted to the position, where the horizontal image starts, detected by the detection circuit and the number of second sampling clocks outputted from the clock generation circuit from the timing at which the horizontal synchronizing signal of the input image signal is outputted to the position, where the horizontal image ends, detected by the detection circuit, and a subtractor for subtracting the number of first sampling clocks from the number of second sampling clocks.
An example of the comparison means is one for comparing the number of sampling clocks calculated by the calculation means with the number of horizontal effective dots of the input image signal previously set and a number larger by one than the number of horizontal effective dots, to output a first judgment signal depending on whether the number of sampling clocks calculated by the calculation means coincides with either the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots or coincides with neither of them, and output a second judgment signal dependent on whether the number of sampling clocks calculated by the calculation means is smaller than the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots.
An example of the control means is an up-down counter respectively receiving a vertical synchronizing signal of the input image signal as a clock, the first judgment signal from the comparison means as an enable signal, and the second judgment signal from the comparison means as an up-down control signal, and having a predetermined default value preset therein.
The up-down counter inhibits a clock counting operation when the first judgment signal indicates that the number of sampling clocks calculated by the calculation means coincides with either the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots, while performing an up-counting operation every time the vertical synchronizing signal is inputted when the second judgment signal indicates that the number of sampling clocks calculated by the calculation means is smaller than the number of horizontal effective dots of the input image signal, and performing a down-counting operation every time the vertical synchronizing signal is inputted when the second judgment signal indicates that the number of sampling clocks calculated by the calculation means is larger than the number which is larger by one than the number of horizontal effective dots of the input image signal. The frequency of the sampling clocks outputted from the clock generation circuit is controlled on the basis of a count value of the up-down counter.
A second display device according to the present invention is characterized by comprising a clock generation circuit for generating sampling clocks, whose frequency is variable, on the basis of a horizontal synchronizing signal of an input image signal; an analog-to-digital converter for sampling the input image signal on the basis of the sampling clocks generated from the clock generation circuit; detection means for comparing image data outputted from the analog-to-digital converter with a predetermined threshold value, to detect a horizontal image start position and a horizontal image end position for each horizontal period; calculation means for calculating, on the basis of a horizontal image start position nearest to the position, where the horizontal period starts, specified by the horizontal synchronizing signal out of horizontal image start positions detected for each field and a horizontal image end position farthest from the position, where the horizontal period starts, specified by the horizontal synchronizing signal out of horizontal image end positions detected for each field, the number of sampling clocks corresponding to the distance from the horizontal image start position and the horizontal image end position of the input image signal for the field; comparison means for comparing the number of sampling clocks calculated by the calculation means with a previously set value; and control means for controlling the frequency of the sampling clocks outputted from the clock generation circuit on the basis of the results of the comparison in the comparison means.
An example the clock generation circuit is one comprising a voltage control oscillator for outputting the sampling clocks, a frequency divider for dividing the frequency of the sampling clocks outputted from the voltage control oscillator, phase detection means, to which an output signal from the frequency divider and the horizontal synchronizing signal of the input image signal are inputted, for outputting a detection signal corresponding to the phase difference between both the inputted signals, and filter means for integrating the detection signal outputted from the phase detection means, to output the integrated detection signal to the voltage control oscillator. In this case, the frequency division ratio of the frequency divider is controlled by the control means.
An example of the comparison means is one for comparing the number of sampling clocks calculated by the calculation means with the number of horizontal effective dots, previously set, of the input image signal and a number larger by one than the number of horizontal effective dots, to output a first judgment signal dependent on whether the number of sampling clocks calculated by the calculation means coincides with either the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots, and a second judgment signal dependent on whether the number of sampling clocks calculated by the calculation means is smaller than the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots.
An example of the control means is an up-down counter respectively receiving a vertical synchronizing signal of the input image signal as a clock, the first judgment signal from the comparison means as an enable signal, and the second judgment signal from the comparison means as an up-down control signal, and having a predetermined default value preset therein.
The up-down counter inhibits a clock counting operation when the first judgment signal indicates that the number of sampling clocks calculated by the calculation means coincides with either the number of horizontal effective dots of the input image signal or the number larger by one than the number of horizontal effective dots, while performing an up-counting operation every time the vertical synchronizing signal is inputted when the second judgment signal indicates that the number of sampling clocks calculated by the calculation means is smaller than the number of horizontal effective dots of the input image signal, and performing a down-counting operation every time the vertical synchronizing signal is inputted when the number of sampling clocks calculated by the calculation means is larger than the number which is larger by one than the number of horizontal effective dots of the input image signal. The frequency of the sampling clocks outputted from the clock generation circuit is controlled on the basis of a count value of the up-down counter.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
USPTO Backgrounds
USPTO Backgrounds