The process of building integrated circuits (ICs) is a multi-step process. The designer or design team initially has a purpose and an associated functionality for that purpose, for example, contained in a specification. The designer or design team then uses a computer aided design (CAD) tool to design logic structures to implement that functionality. These logic structures, as well as the wires connecting the logic structures, are referred to as one or more of the “design” and the “netlist”. When completed, the netlist is manufactured, or “fabricated” in a foundry by building transistors using a semiconductor, such as silicon, resulting in an IC chip. The ICs produced by the foundry are then used in different systems and products.
When creating the design, more than just the functional aspect of the IC must be considered. Both the design process and fabrication are complex processes. For example, to ensure that the IC is manufactured correctly and functions as specified, additional logic is added to the design. This additional logic is called the “test logic” and the set of techniques to make ICs more testable are called design-for-test (DFT). In many design processes, the test logic is added to the design by a test engineer or test team, rather than by the designer or design team.
The netlist of the design by itself is very complex and becomes more complex with size. When further adding DFT test logic, the netlist becomes yet more complex, and therefore even more challenging. For the purposes of simplicity, reference to the design refers both to the design as it exists prior to the inclusion of DFT test logic and the design as it exists after the inclusion of DFT test logic. When managing various considerations for the design and test logic; for example, design size, transistor density, thermal management, and structural integrity; it is crucial that everyone involved with the DFT planning, design and test logic debugging, including both the design and test teams, has clear communications and a clear understanding of the design and changes to the design. Although graphical tools are available to support these tasks, the vast amount of information contained in the design and test logic can overwhelm and/or obscure details relevant to the proper functioning of the ICs for the teams managing these considerations.
FIG. 10 is an example prior art report 1000 for two scan modes for a simple circuit of 1000 flops. Report 1000 for the current mode 1014 which is an internal scan mode includes report header information 1005, summary information 1016 and scan chain information 1018. The summary information 1016 displays information that four scan chains were built and scan chain information 1018 lists the scan ports connected to each of the scan chains. Scan chain information 1018 also reports the length of these registers, and if enabled, has the capability to show all the flops in the verbose mode (not shown).
In operation, typically a user is not interested in a particular flop in the scan chain until a failure is recorded during pattern simulation. In such a situation, a tool such as the TetraMAX from Synopsys, Inc. identifies the failing flop in a chain using the diagnostic capability built into it.
Report 1000 for the current mode 1052 equivalent to Scan Compression mode includes summary information 1054, scan chain information 1056, sub scan chains 1058, in/out ports 1060, test point report 1062 and controller information 1064. For Scan Compression mode 1052, report 1000 is an example output for a tool similar to the DFTMAX Ultra from Synopsys, Inc. The report indicates that based on the current specifications, the associated tool will build 105 chains (in header information 1054) with a maximum length of 32 (max of lengths in scan chain information 1056 and sub scan chains 1058) and identifies the scan ports that will be used to build those chains (in/out ports 1060). Unfortunately, much information relevant to the user is not captured by this report.
While report 100 is a summary of a very simple circuit, it is easy to extrapolate the expanded difficulty to read and understand an equivalent report when it represents the output from a design with 100 k flops (1000 times more complex).
USPTO Backgrounds
USPTO Backgrounds