1. Field of the Disclosure
The present disclosure is generally related to methods of forming semiconductor device structures and the resulting device structures, and, more particularly, to the fabrication of semiconductor device structures in FDSOI techniques implementing flash devices.
2. Description of the Related Art
In systems requiring a significant amount of non-volatile solid state storage, flash memory devices became the dominant memory type due to the low costs as compared to byte-programmable EEPROM, and the relatively simple structure of flash memory cells. As flash memories are generally a type of nonvolatile memory storage, which may be electrically erased and programmed, recent applications for flash memory devices aim at a replacement for hard discs, as flash memory devices do not have the mechanical limitations and latencies of hard drives, so a solid state drive (SSD) implemented by flash memory devices is attractive when considering speed, noise, power consumption and reliability.
Generally, information is stored in a flash memory via an array of memory cells fabricated in accordance with floating gate techniques or charge trap flash (CTF) techniques. Herein, CTF is a term that will be used to generally refer to a semiconductor memory technology used in creating non-volatile NOR and NAND flash memory, a technology that differs from the more conventional floating gate technology in that a silicon nitride film is used to store electrons rather than the doped polycrystalline silicon typical of a floating gate structure. In a CTF device, electrons are stored in a trapping layer just as they are stored in the floating gate, however, the nitride layer, in accordance with CTF being an insulator, while the floating gate is made from a conductor. Therefore, upon high stress being imposed on the tunnel oxide layer of floating gate transistors (the floating gate is separated from a general region formed between source and drain by the tunnel oxide), disruptions in the crystal lattice of the tunnel oxide layer are created, resulting in so-called “oxide defects.” If a large number of such disruptions are created, a short circuit is very likely to develop between the floating gate and the transistor's channel, causing the floating gate to no longer hold a charge. By contrast, CTF devices are immune to such difficulties, since charges are trapped in a nitride layer acting as a charge trapping layer instead of the floating gate. In case oxide defects appear in the oxide layer separating the charge trapping layer from the channel region below, charges of the charge trapping layer will only be drained off at regions in immediate contact with the site of the oxide defect, leaving the other electrons in place to continue to control the threshold voltage of a CTF transistor.
In CTF devices, electrons are moved onto the charge trapping layer similarly to the way that floating gate NOR flash may be programmed, i.e., through channel hot electron (CHE) injection, which is also known as hot carrier injection. Briefly, a high voltage is applied to the control gate, while a medium high voltage is applied to source and drain, and a current is induced from source to drain. As a result, electrons having sufficient energy in traversing through the high field region near the drain will be injected into the charge trapping layer where they come to rest. Charges may be removed from the charge trapping layer via hot hole injection as opposed to the well-known Fowler-Nordheim tunneling approach used in NAND and NOR/devices for erasing information. Accordingly, erasing information in CTF devices rather uses an electric field than a current that is necessary for Fowler-Nordheim tunneling, to move holes towards the charge trapping layer.
Manufacturing floating gate devices and CTF devices is very similar as both techniques use a stacked gate structure in which a floating gate or charge trapping layer lies immediately above the channel and below a control gate. In both techniques, an oxide layer is formed in between the floating gate or charge trapping layer and the channel, and between the control gate and the floating gate or charge trapping layer. Therefore, aside from the storage layer made of a conductive material in the case of a floating gate or of nitride in the case of CTF, the materials for all the remaining layers of the stacked gate structure are actually very similar in both approaches.
Currently, fully depleted silicon-on-insulator (FDSOI) is a favorite basis for next generation technologies in the fabrication of semiconductor devices at 22 nm and beyond. Herein, a semiconductor device, such as a MOSFET, is formed on a semiconductor layer having a thickness such that a depletion region covers the whole semiconductor layer and a buried oxide layer (BOX) is interposed between the semiconductor layer and a substrate material. Although FDSOI techniques are simple (when compared to 3-dimensional techniques, such as FINFETs and the like), the implementation of flash devices in FDSOI techniques raises several challenges, such as an excessive topography.
In view of the above, it is desirable to provide a method of forming a semiconductor device structure and a semiconductor device structure that allow the implementation of flash memory in FDSOI techniques at advanced technology nodes.
USPTO Backgrounds
USPTO Backgrounds