The invention relates to a method of manufacturing an integrated lateral transistor, in which emitter and collector regions of a first conductivity type laterally spaced apart are obtained from the surface of a region of a second conductivity type opposite to the first conductivity type, the lateral space of said region of the second conductivity type between the emitter and collector regions forming a base region of the transistor, in which method there are then formed through windows of an insulating layer deposited at least on said emitter and collector regions electrical emitter and collector connections, each of which has a zone in electrical contact with said emitter region and with said collector region, respectively.
Such a method is generally known from French Utility Model FR 2254106 (National Semiconductor) in FIG. 1 thereof.
It is known to a person skilled in the art that the current amplification of lateral transistors is limited because of the phenomenon of vertical injection. The solutions proposed hitherto consist of reducing the surface of the emitter in order to reduce the vertical injection and hence to increase the current amplification. In order to obtain a lateral transistor, a person skilled in the art generally chooses an emitter contact surface as small as permitted by the manufacturing technology and consequently realizes an emitter also as small as possible while taking into account positioning tolerances corresponding to the method chosen in order to avoid the emitter contact causing an emitterbase shortcircuit.
A certain number of solutions have been proposed to reduce the phenomenon of vertical injection by limiting the effective surface of the emitter. These solutions have the consequence that they necessitate either a modification of the method or the addition thereto of a supplementary step.
French Patent 2 028 146 (N.V. Philips) envisages for limiting the vertical injection to form the emitter zone as a very small superficial zone. Since such a small zone cannot possibly be realized, this Patent proposes as a solution to form an emitter zone thicker than the collector zone in order that only the emitter zone attains a buried layer.
This known method requires a supplementary diffusion and has the disadvantage that the emitter-base capacitance is increased.
French Patent 2365213 (Thomson-C.S.F.) proposes to diffuse into the emitter a very highly doped zone of a type opposite to that of the emitter, an electrical contact covering at least in part the surface of the junction between this very highly doped zone and the emitter. It is clear that this solution also implies a supplementary processing step.
USPTO Backgrounds
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