With the decreasing of size and cost of electronic products, miniaturization of IC chips and 3D stack packaging have become a major direction for the development of the semiconductor technology in the future. Therefore, major semiconductor manufacturers around the world invest a lot of manpower to develop a through silicon via (TSV) process technology of the 3D IC, in the hope of packaging various digital logics, memories, and analog chip circuits into a single package, so as to significantly improve operating speed and functions of the IC. The main objective of the 3D IC is to thin a chip to be stacked, meanwhile use a TSV structure to run through a silicon wafer, and use a micro bump to transmit a circuit signal to a chip of a next layer. The increasing number of stacked layers results in more powerful functions of the IC.
With the chip becoming thinner and with the number of the stacked layers becoming bigger, some problems of bad circuit characteristics emerge. For example, FIG. 1 is a schematic sectional view illustrating a conventional multi-chip stack structure 100. The multi-chip stack structure 100 includes a plurality of mutually stacked chips, such as a chip DIE-1, a chip DIE-2, a chip DIE-3, and a chip DIE-4. An interconnecting line 133 represents an interconnecting line transmitting a data signal on the chip DIE-3, and an interconnecting line 134 represents an interconnecting line transmitting a data signal on the chip DIE-2.
The chips DIE-1 to DIE-4 are mutually stacked, as shown in FIG. 1. Under-fill is filled between two adjacent chips. With TSV structures and micro bumps, various signals, such as a power supply voltage VDD and a ground voltage GND, can be transmitted between various chips. For example, TSV structures 111 and micro bumps 112 are responsible for transmitting the power supply voltage VDD needed by the chips DIE-1 to DIE-4. A TSV structure 131 and a micro bump 132 are responsible for transmitting a data signal between the chip DIE-2 and the chip DIE-3.
FIG. 1 does not illustrate a layout structure of active areas inside the chips DIE-1 to DIE-4. The TSV structures 111 and the micro bumps 112 are responsible for transmitting the power supply voltage VDD needed by the active areas inside the chips DIE-1 to DIE-4. FIG. 1 does not illustrate any interconnecting line between the TSV structure 111 and the active area. Since the TSV structure 111 has a certain internal resistance (as shown in FIG. 1), a voltage level error may occur between the power supply voltages VDD of the layers of the chips.
Furthermore, with the chips becoming thinner, a problem of noise interference generated between signal lines of different chips and signal coupling becomes much more serious. For example, a data signal of the interconnecting line 134 of the chip DIE-2 and a data signal of the interconnecting line 133 of the chip DIE-3 interfere with each other due to a close distance.
However, in the future, high degree of circuit integration and downsizing are the trend of the development of the 3D IC chip stack technology. Thinner wafers and the increased number of stacked layers make the integration of transistor components, circuits, and signals more complex, and even digital circuits, analog circuits, high-frequency circuits, and power circuits are also integrated into the 3D IC chip, which makes the seriousness of the problem of electromagnetic, static, electrostatic, and noise interference coupling more obvious. In addition, with the increasing number of the stacked layers, a circuit density increases, thus resulting in a more serious problem of heat dissipation.
USPTO Backgrounds
USPTO Backgrounds