1. Field of the Invention
The present invention generally relates to the field of random data generation in computer systems and, more particularly, to the allocation of random data bandwidth among a plurality of processing cores in a processing device.
2. Relevant Background
In many applications in the field of computers and other electronic devices, there is a need for a physical source of true random data such as random numbers and/or random symbols. Such applications include computer simulations of various probabilistic algorithms and processes (e.g., Monte Carlo numerical analysis), computer games, cryptographic algorithms and protocols whose security relies on the ability to generate unpredictable secret keys. High-speed truly random sequences are also needed for setting up countermeasures against so-called side-channel attacks that target specific electronic devices (e.g., microelectronic devices, security schemes, integrated chip cards). For example, such countermeasures include random masking of cryptographic functions as well as generation of secret keys for the encryption of internal links and memories in such devices.
In this regard, microprocessors typically include or otherwise incorporate a Random Number Generator (RNG) whose output is typically a binary sequence that, in principle, needs to be unpredictable in the sense of the information theory. Stated differently, it should be possible to statistically model the RNG output as a purely random sequence, i.e., a sequence of mutually independent, uniformly distributed binary random variables (bits), with maximal possible entropy per bit. In particular, it should be computationally infeasible to distinguish the RNG output sequence from a purely random sequence or, equivalently, it should be computationally infeasible to predict the RNG output sequence.
Microprocessors that include two or more independent processing cores manufactured on a single chip or integrated circuit die are often referred to as multi-core processors and may be implemented as a System on a Chip (SoC). Each core can read and execute program instructions (e.g., add, move data, branch) and the multiple cores can run multiple instructions at the same time to increase overall speed for programs amenable to parallel computing. The various cores can sometimes share one or more common caches and may implement message passing or shared-memory inter-core communication methods. Common network topologies to interconnect cores include bus, ring, two-dimensional mesh, and crossbar.
USPTO Backgrounds
USPTO Backgrounds