With the continuously shrinking of minimum designed line widths and pitches of integrated circuits, when a critical dimension of exposed lines approaches a theoretical limitation of the resolution of an exposure system, the image formed on a substrate may be seriously distorted, and quality of patterns formed by a lithography process may be significantly reduced. In order to minimize an optical proximity effect (OPE), resolution enhanced techniques (RETs) are developed by semiconductor industries. Amongst of RETs, a double patterning technique (DPT) attracts intensive attentions, it is considered as a practical way to bridge the gap between an immersion lithography and an extreme ultraviolet (EUV) lithography.
The existing method for forming small pitch patterns having alternatively aligned lines and spaces is often a self-aligned double patterning (SADP) technique. The SADP technique for forming small pitch patterns, illustrated in FIGS. 1-5, may include: forming a target material layer 20 (may refer to a to-be-etched layer) on a semiconductor substrate 10, as shown in FIG. 1; forming a sacrificial material layer on the target material layer 20 (not shown), and patterning the sacrificial layer 30, as shown in FIG. 2; forming a sidewall layer on surface of the sacrificial layer 30 and the exposed portion of the target material layer 20, and forming sidewalls 40 by anisotropically etching the sidewall layer, as shown in FIG. 3. A width of the sidewalls 40 may be a line width of later-formed small pitch patterns, the width of the interspace of sidewalls 40 may be a space of the later-formed small pitch patterns. Further, the SADP technique for forming small pitch patterns includes removing the sacrificial layer 30, as show in FIG. 4, and forming small pitch patterns 21 by etching the target material layer 20 using the sidewalls 40 as a mask, as shown in FIG. 5.
Although, the existing SADP technique may form repeating patterns with small line widths and spaces on a semiconductor substrate, if large scale patterns are needed to be formed on other areas of the semiconductor substrate, the small patterns and the large patterns may need to be formed separately, the fabrication process may be complex. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.
USPTO Backgrounds
USPTO Backgrounds