1. Field of the Invention
The present invention generally relates to electronic circuits, specifically, programmable logic units such as application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs), and more particularly to an improved method of overcoming design flaws in such programmable logic circuits, using software work-arounds in place of the defective portions of the circuits, but only for those input vectors affected by the fault.
2. Description of the Related Art
Modern electronic circuits use many different types of logic components or processing units to carry out numerous functions. In the early years of the semiconducting industry, these components were integrated circuits (ICs) with narrowly limited functionalities. Early small-scale integration ICs contained a few logic gates (AND gates, OR gates, NAND gates, NOR gates, XOR gates, etc.) amounting to a few dozen transistors. These gates are combined in Boolean fashion to implement particular logic circuits. Medium-scale integration increased the range of integrated logic available to counters and similar logic functions, and large-scale integration packed even larger logic functions, such as the first microprocessors, into a single chip. The current era of very large-scale integration (VLSI) offers complex processing and control capabilities with well over a million transistors on a single piece of silicon.
While many digital logic ICs became standard components which could be used to construct a variety of different microelectronic systems, there was a clear desire to provide more customized or tailor-made ICs for the electronics industry. As CMOS process technology has improved, and transistors continue to get smaller, it has become easier for engineers to design larger ICs that may be adapted to a customer's specific needs; these types of ICs are referred to as application-specific integrated circuits (ASICs).
An ASIC, like a conventional integrated circuit, includes an IC package (typically having a pin-grid array, or PGA), with the silicon chip (die) mounted in a cavity under a sealed lid. The physical size of a silicon die varies from a few millimeters on a side to over one inch on a side, but the size of an ASIC is often measured instead by the number of logic gates or transistors that the IC contains. Very large ASICs typically have hundreds of thousands of gates.
ASICs are used for a wide variety of applications, such as children's electronic toys, telecommunications, and data processing. ASICs are also known as customer-specific integrated circuits (CSICs). Some ASICs which are specific to a particular application, but are sold to many different system vendors similar to a standard component, are commonly referred to as application-specific standard part (ASSPs). ASICs can be built using customized circuits at every level, which is the most time-consuming and complicated approach, or be built using gate arrays, standard cells, or programmable logic devices. In a fully-customized ASIC, the designer uses no pretested and precharacterized cells for the design, and all layers of the chip (including the “mask” layers) are designed to unique specifications. In programmable ASICs, all of the logic cells are predesigned and none of the mask layers are customized.
These programmable ASICs include a plurality of logic elements and associated interconnect resources that are easily programmed by the end-user to implement user-defined logic operations. They can be programmed using a personal computer (PC) or similar workstation, with appropriate software and a device programmer. Therefore, unlike fully-customized ASICs that require a protracted layout procedure and an expensive fabrication process to implement a user's logic operation, a programmable ASIC may be utilized to implement the logic operation in a relatively quick and inexpensive manner.
There are generally two types of programmable ASICs: the programmable logic device (PLD), and the field-programmable gate array (FPGA). Gate arrays are made up of base cells that contain a varying number of transistors and resistors according to the vendor's specifications. Using a cell library (of gates, registers, etc.) and a macro library (for more complex functions), the customer designs the chip, and the vendor's software generates the masks that connect the transistors. An FPGA is usually larger and more complex than a PLD.
A PLD may also be programmed at the customer's site. PLDs use fusible links which are blown in order to open a circuit line, or “antifuse” technology which allows the circuit lines to be fused together. PLD techniques include programmable logic arrays (PLAs) and programmable array logic (PAL), which provide different configurations of AND and OR gates. Unlike gate arrays, which require the final masking fabrication process, PLDs are easily programmable in the field. Although memory devices generally are not considered a PLD, since they generally have no logic functions, some programmable storage chips such as programmable read-only memory (PROM) may be considered a PLD if it contains program code rather than just data.
It is very common in the ASIC/FPGA design process that only a pseudo-comprehensive test is performed for a given hardware design. The pseudo-comprehensive test basically uses a set of test vectors that provide the best coverage for the functional testing of the circuit under test. Normally, to test an n-bit input circuit, 2n test vector combinations are required; however, if the n bits are divided into two groups of m bits and (n−m) bits, then it requires only 2n−m+2 m<2n test vectors to test all the functionality. This scheme, however, cannot guarantee 100% coverage. In reality, when the ASIC is in the field, it may encounter some new inputs that are never tested in the factory. The new inputs may or may not cause the circuit to malfunction depending on how well the circuit was designed.
If a design flaw exists, there are generally two approaches to correcting the problem, hardware or software. A common hardware approach to providing fault tolerance in FPGAs is to relocate the logic portion assigned to a defective configurable logic block (CLB) into a spare or other unused CLB, and to reroute signals from the defective CLB to the spare/unused CLB. One problem with this approach is that a user typically does not know which CLB of a particular FPGA will be defective, and usually generates configuration data intended for a defect-free device. If the user then attempts to program an FPGA containing a defective CLB, the programmed FPGA will not perform as intended. Therefore, the user must either discard the FPGA, or the user must repeat the place-and-route process with a modified device description indicating the location of the defective CLB. Because each target FPGA may have a defective CLB in a different location, this approach potentially requires different configuration data for every device implementing the user's logic operation. This approach puts a heavy burden on the user who must potentially repeat the place-and-route operation for each FPGA and supply many PROM configurations.
Other hardware approaches also implement redundant circuitry in the FPGA, which is generally undesirable as it requires blocks of the circuit to be reserved and possibly go unused throughout the life of the FPGA. Since it is not easy to fix an ASIC/FPGA at the hardware level, software work-arounds are called for as an alternative until the new chip is re-designed. When the hardware fails to perform its functionality, software can be used to perform the same task, and this software is referred to as a software work-around. The software work-arounds can be keyed to a static table of faulty vectors.
When a software work-around is employed to account for a new bug, the system performance usually deteriorates at least three orders in magnitude (103) because of the gap between hardware and software speeds. The software work-around can never provide the same level of performance as the initial architecture embedded in the ASIC. At the system software level, instructions are typically executed on a scale of microseconds. At the hardware (sub-micron) level, instructions are performed on a scale of nanoseconds. This difference can bottleneck instruction throughput and have an immense (negative) impact on the overall performance of the ASIC.
This performance latency is exacerbated by the fact that, oftentimes, it is really not necessary to execute the software work-around. ASICs tend to use regularly-shaped, standard cells or blocks to simply construction and design. When a hardware block is faulty, the fault sometimes affects only a small range of input vectors (i.e., input data) of the block. Nevertheless, if the block is faulty, then all vectors to that block will be rerouted for software processing. The system will accordingly have to wait on the software work-around for all input vectors, even though some of those vectors may not be bad. It would, therefore, be desirable to devise an improved method of utilizing software work-arounds in an ASIC or FPGA, which would ensure appropriate handling of bad vectors while still retaining the benefit of the speed of the original hardware design for at least some input vectors of the faulty block. It would be further advantageous if the method allowed new faulty vectors to be dynamically discovered and the software work-around mechanism appropriately updated.
USPTO Backgrounds
USPTO Backgrounds