Various circuits have been developed, as drivers or buffers, for use in driving high voltage devices. For instance, such drivers or buffers can be formed of low-voltage electronic circuitry, to drive high-voltage power devices, such as power metal oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistor devices (IGBTs), gate controlled thyristors, and the like.
The low-voltage circuitry can be coupled to apply appropriate voltages to the gate or control terminal of the power device to turn on or turn off the power device. When the power device is an N-channel metal oxide semiconductor field effect transistor (NMOSFET, also referred to as an NFET or NMOS device), the device is turned on by applying a high voltage to the gate of the power switch and turned off by applying a low voltage to the gate. In contrast, if the power device is a P-channel metal oxide semiconductor field effect transistor (PMOSFET, also referred to as a PFET or PMOS device), the device is turned on by applying a low voltage to the gate of the power switch and turned off by applying a high voltage to the gate.
As an example, FIG. 1 depicts an example of a prior art high-voltage driver 1 that can be utilized to drive an output power switch device. The driver 1 is connected to a high voltage switch device, represented as a high voltage PMOS device 2. The driver 1 includes a first NMOS device 3 that is coupled to a first differential input pin, indicated at VINB. A second NMOS device 4 is coupled to a second differential input pin, indicated at VIN (e.g., VINB= VIN relative to electrical ground). The first NMOS device 3 has its drain coupled to a PMOS device 5 of a corresponding latch device that includes another PMOS device 6. In the prior art example of FIG. 1, the NMOS device 3 is coupled with the PMOS device 5 through a cascode NMOS device 7 and a PMOS device 8. Similarly, the other NMOS device 4 is coupled to the drain of the PMOS device 6 through cascoded PMOS devices 9 and 10.
The sources of each of the PMOS devices is coupled to a supply voltage 11. The biasing devices 7, 8, 9 and 10 generally operate to mitigate the voltage across the low power NMOS device drive devices 3 and 4. In operation, when the voltage VINB goes high, the node 12 is pulled low through the biasing devices 7 and 8 and the input driver NMOS device 3. The gate of the PMOS device 6, which is a flow, activates the PMOS device 6 so that the voltage at the gate of the PMOS device 2 is pulled high to the voltage provided by the supply 11. As a result, the PMOS device 2 is off such that the output at the drain VOUT—A is low. This is facilitated by the concurrent operation associated with the input VIN provided to the gate of NMOS device 4. Additionally, when VINB is low and VIN is high, similar operation occurs to pull the gate of the PMOS device 2 low such that VOUT—A is high according to the voltage provided by the supply in the activation of the PMOS device 2.
During operation when the input VINB goes high the node 12 between the PMOS DEVICE 5 and the PMOS device 8 (e.g., corresponding to the drain of PMOS device 5 operates as a high impedance node. Consequently, the output PMOS device 2 may not close properly while the voltage from the supply 11 (e.g., at the source of the PMOS device 2) is changing, such as corresponding to a glitch condition. When voltage at the source of output PMOS device 2 changes in such a manner, there tends to be leakage across the PMOS device 2. This leakage can result in cross regulation, such as when multiple power devices are driving respective loads from the same supply 11. The high impedance at the node 12 thus reduces performance of the driver for a variety of applications.
USPTO Backgrounds
USPTO Backgrounds