1. Field of the Invention
The present invention relates to a semiconductor device having ferroelectric capacitors in a memory cell.
2. Description of the Prior Art
There is known a ferroelectric non-volatile memory called a FeRAM (Ferroelectric Random Access Memory), for example, as a non-volatile memory capable of storing information even if a power source is turned off.
The ferroelectric non-volatile memory has ferroelectric capacitors where the relation between a polarization charge and an applied voltage is in hysteresis characteristics, and has a structure that it stores data of “1” or “0” by using polarization and inversion thereof in the ferroelectric capacitor. Such a ferroelectric non-volatile memory can be operated in high-speed and low power consumption, and its future development is expected.
Various types are suggested as a storage method of the ferroelectric non-volatile memory, and there exist a 1T1C type that stores 1-bit by using one each of transistor and capacitor and a 2T2C type that stores 1-bit by using two each of transistor and capacitor. In the 1T1C type, the number of elements is made smaller to reduce a cell area comparing to the 2T2C type. Further, the following patent document 1 describes a structure that a control circuit switches the 1T1C type and the 2T2C type and the cell area is regurated by the 2T2C type.
The ferroelectric non-volatile memory of 1T1C type, as described in the following patent document 2, requires a ferroelectric capacitor for reference (hereinafter, referred to as reference capacitor) to output a reference value for reading out data in order to determine the data of “0” or “1”, other than ferroelectric capacitors for memory (hereinafter, referred to as memory capacitor).
Next, the basics of the 1C1T type memory cell will be described based on FIGS. 1 and 2.
In FIG. 1, one ends of first and second bit lines 101a, 101b are connected to a column decoder 102 and the other ends are connected to a sense amplifier 103. Further, in a memory cell region, a plurality of word lines 104a for memory and plate lines 105a for memory are alternately formed in a direction orthogonal to the first and second bit lines 101a, 101b. The word lines for memory cell 104a are connected to a row decoder 106, and the plate lines 105a for memory cell are connected to a plate driver 107.
A memory capacitor 109a is connected between the first bit line 101a and each plate line 105a for memory via source/drains of a first n-channel MOS transistor 108a. Further, a word line 104a for memory cell is connected to the gate electrode of the first n-channel MOS transistor 108a. 
Furthermore, a plate line 105b for reference is connected to the plate driver 107, and a word line 104b for reference is connected to the row decoder 106. Then, a reference capacitor 109b is connected between the plate line 105b for reference and a second bit line 101b via source/drains of a second n-channel MOS transistor 108b. The gate electrode of the second n-channel MOS transistor 108b is connected to the word line 104b for reference.
In such a ferroelectric non-volatile memory, the column decoder 102 applies selected voltage to the first and second bit lines 101a, 101b, the row decoder 106 applies selected voltage to the first and second word lines 104a, 104b, and the plate driver 107 applies selected voltage to the plate line 105a for memory cell and the plate line 105b for reference.
Then, when reading out data, the sense amplifier 103 compares the potential variation of the first bit line 101a and the potential variation of the second bit line 101b, and data is detected according to a size of the difference between the two potential variations.
Next, a readout operation of data stored in the ferroelectric non-volatile memory will be described. Herein, data “0” is always stored in the reference capacitor 109b in a state other than writing and reading-out of data, and the polarization charge of the reference capacitor 109b is +Q2 at point C of a hysteresis line I shown in FIG. 2.
In a state where data “1” is written in the memory capacitor 109a, the polarization charge of the reference capacitor 109b is −Q1 at point A of a hysteresis line II shown in FIG. 2. Further, in a state where data “0” is written in the memory capacitor 109a, the polarization charge of the reference capacitor 109b is +Q1 at point B of the hysteresis line II shown in FIG. 2.
Then, in the case of reading out the data of the memory capacitor 109a, the voltage of the first and second word lines 104a, 104b and the first and second plate lines 105a, 105b are made to vary in the timing shown in FIG. 3, and the voltage of the first and second bit lines 101a, 101b also vary accordingly.
First, after a signal voltage that the row decoder 106 applies to the first and second word lines 104a, 104b has risen from 0 to Vcc, a signal voltage that the plate diver 107 applies to the first and second plate lines 105a, 105b rises from 0 to Vcc. Note that 0 and Vcc are ground voltage and a power source voltage, respectively, and their units are in volt. Thus, voltage V1 is applied to the memory capacitor 109a and its polarization state moves along a hysteresis loop II shown in FIG. 2 to finally reach point D and the polarization charge becomes +Q01. Note that the voltage V1 applied to the memory capacitor 109a is lower than Vcc due to voltage drop.
Herein, the polarization direction of the memory capacitor 109a is inverted when the data of the memory capacitor 109a is “1”. In contrast, the polarization direction of the memory capacitor 109a is not inverted when the data is “0”. At the same time, the polarization state of the reference capacitor 109b moves along a hysteresis loop I shown in FIG. 2 to finally vary from point C to point E and the polarization charge becomes Q02, where the polarization direction is not inverted.
Therefore, in the memory capacitor 109a, the transfer quantity of the polarization charge is α=+Q01−(−Q1) when data “1” is written in the memory capacitor 109a, and the transfer quantity of the polarization charge is β=+Q01−(Q1) when data “0” is written.
On the other hand, the transfer quantity of the polarization charge is γ=+Q02−Q2 in the reference capacitor 109b. 
The potential of the bit lines 101a, 101b increases according to the transfer quantities α, β, γ of the polarization charge, and the sense amplifier 103 amplifies the increased quantity. Then, the amplifier compares the charge variation quantities of the first bit line 101a and the second bit line 101b based on the transfer quantities α, β, γ of the polarization charge, and reads out either “1” or “0” stored in the memory capacitor 109a. Specifically, when the variation value of the potential of the first bit line 101a is larger than the variation value of the potential of the second bit line 101b (α>β), the amplifier holds as a fact that “1” is stored in the memory capacitor 109a. On the other hand, when the variation value of the first bit line is smaller (γ>β), the amplifier holds as a fact that “0” is stored in the memory capacitor 109a. 
Consequently, in order to accurately read out the memory capacitor 109a, the transfer quantity γ of the polarization charge of the reference capacitor 109b shown in FIG. 2 needs to be set to a size between the inversion transfer quantity a and the non-inversion transfer quantity β of the polarization charge.
(Patent Document 1)
    Japanese Patent Laid-open No.Hei9-120700 publication (paragraph no.0011 to 0016)(Patent Document 2)    Japanese Patent Laid-open No.Hei8-321186 publication (paragraph no.0057 to 0063, FIG. 9)
Meanwhile, it is often the case that data such as an identification number for each chip is written in the ferroelectric non-volatile memory by customer's request before heat treatment such as resin capsulation and solder junction (hereinafter, referred to as mounting/IR heat treatment).
However, the polarization charge quantity Q2 at point C of the hysteresis loop of the reference capacitor 109b readily depolarizes widely at the temperature of 200° to 250° C.
In the depolarized reference capacitor 109b, a residual polarization charge quantity varies to point C′ on a polarization charge quantity axis of FIG. 2, and the transfer quantity of the polarization charge during data readout increases to γ′ (γ′>α>β). As a result, data readout of the memory capacitor 109a based on the residual polarization quantity of the reference capacitor 109b cannot be performed.
Although the residual polarization quantity varied by the heat of the reference capacitor 109b returns to point C when the temperature is brought back to an original one and rewrite is performed, writing prior to heat treatment is meaningless.
Note that the memory capacitor 109a could also be depolarized by heat, but its depolarization quantity is not as large as that of the reference capacitor 109b because many memory capacitors 109a are connected to the bit line 101a. 
USPTO Backgrounds
USPTO Backgrounds