1. Field of the Disclosure
Generally, the present disclosure relates to sophisticated integrated circuits, and, more particularly, to methods of forming conductive contacts on a semiconductor device with embedded memory, and a novel device structure.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit. However, commensurate with the on-going shrinkage of feature sizes, certain size-related problems arise that may at least partially offset the advantages that may be obtained by simple size reduction alone. In general, decreasing the size of, for instance, circuit elements such as MOS transistors and the like, may lead to superior performance characteristics due to a decreased channel length of the transistor element, thereby resulting in higher drive current capabilities and enhanced switching speeds. Upon decreasing channel length, however, the pitch between adjacent transistors likewise decreases, thereby limiting the size of the conductive contact elements—e.g., those elements that provide electrical connection to the transistor, such as contact vias and the like—that may fit within the available real estate. Accordingly, the electrical resistance of conductive contact elements becomes a significant issue in the overall transistor design, since the cross-sectional area of these elements is similarly decreased. Moreover, the cross-sectional area of the contact vias, together with the characteristics of the materials they comprise, may have a significant influence on the effective electrical resistance and overall performance of these circuit elements.
Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than 3) in such devices. Copper metallization systems exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using tungsten for the conductive lines and vias. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants. However, the use of such low-k dielectric material can be problematic as they tend to be less resistant to metal migration as compared to some other dielectric materials.
FIG. 1 is a simplified and schematic cross-sectional view of an illustrative semiconductor device 100, i.e., a device that includes an illustrative eDRAM (embedded dynamic random access memory) device, for discussion purposes. As depicted therein, the device is formed in and above a substrate 102 and it generally includes a logic area 104, where various logic devices are formed, and a memory array 106, where various memory elements are formed. The logic area 104 and the memory array 106 are separated by an isolation structure, such as an illustrative trench isolation structure 108. The memory array 106 includes, among other things, electrical contacts 105L in the logic area 104, electrical contacts 105M in the memory array 106, and a plurality of schematically depicted capacitors 110 (e.g., single or double sided capacitors) that are electrically coupled to a plate contact 111. The capacitors 110 are formed in a layer 112 of a non-low-k dielectric material (a material having a dielectric constant greater than 3), e.g., silicon dioxide, that is formed above the surface of the substrate 102. As is common, electrical connection to the logic area 104 of the device is made by an extended length contact 114. In the embodiment depicted in FIG. 1, the capacitors 110 in the memory array 106 are formed prior to forming the extended length contact 114.
An etch stop layer 116 is formed above the layer 112 and copper-based metallization components, e.g., metal lines 118 and vias 120, are formed to provide electrical connection to the logic area 104 and the memory array 106. The copper-based metallization components are formed in a dielectric material layer 122 that is typically comprised of a low-k material to enhance the performance of the copper-based metallization components. Typically, the extended length contact 114 is comprised of a conductive material such as tungsten. The aspect ratio of the extended length contact 114 is typically very high and may be on the order of 15-20. Such high aspect ratio openings cannot be readily filled with copper. Moreover, given the difficulty in filling high aspect ratio openings with any material, the aspect ratio of the opening for the extended length contact 114 tends to limit the height of the capacitors 110 in the memory array 106.
One problem that has arisen with the modern devices as device dimensions continue to shrink, is that it is very difficult to fit contact vias in and among the various other structures of the device such as the bit lines and word lines in the memory array 106. All other things being equal, device designers would prefer to have spacing between the bit lines and word lines be as small as possible to shrink the overall size of the memory cell. However, as noted above, this continual reduction in cell size tends to make contact integration schemes very difficult and complex.
There are several other undesirable aspects of the illustrative device 100 depicted in FIG. 1. First, the use of the non-copper extended length contact 114 may reduce the operating efficiency of the device 100 as compared to how the device 100 would operate if copper could be used for the extended length contact 114. Additionally, the use of the higher k dielectric material in the layer 112, which tends to be helpful as it relates to the performance of the capacitors 110, tends to be detrimental as to the signal-to-noise ratio of the device 110.
Some efforts in the past have been made to alleviate the problem of the extended length contact 114 in the logic area 104. For example, bit lines in the memory array 106 have been made at the same time as the so-called metal-1 structures in the logic array 104. Unfortunately, this approach tends to require relatively large spacing between the bit lines which tends to increase the overall cell size.
The present disclosure relates to methods and devices for avoiding or at least reducing the effects of one or more of the problems identified above.
USPTO Backgrounds
USPTO Backgrounds