A grounded gate NMOS transistor 10 shown in FIG. 1 is commonly used as a power supply electrostatic discharge (ESD) clamp. NMOS transistor 10 comprises a gate 20, a source 30, and a drain 40. Gate 20 and source 30 are coupled together and connected to ground, Vss. Drain 40 is normally connected to a power supply voltage, Vcc. This device provides ESD protection by switching to the low-impedance “snapback” regime when a large enough voltage appears between Vcc and Vss to cause the drain junction to break down.
The NMOS device is usually implemented as a multi-finger transistor. FIG. 2 shows a layout style used with a self-aligned silicide (salicide) process to provide acceptable ESD performance. The layout of FIG. 2 comprises a gate 120, source diffusions 130, source leads 135, drain diffusions 140, and drain leads 145. Following known practice, the source and drain diffusions 130, 140 are clad in a metal silicide (not shown) to reduce the contact resistance. See, e.g., A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, pp. 300–304 (Wiley, 2d ed. 2002). The source leads 135 are connected to the source diffusions by contacts 137; and the drain leads 145 are connected to the drain diffusions 140 by contacts 147. A guard ring 160 surrounds the NMOS transistor and is connected to ground, Vss, by leads 165 and contacts 167.
In the example of FIG. 2, gate 120 comprises four polysilicon fingers, but in general the number of fingers may be varied to meet the total transistor width required to achieve the ESD goals. For a grounded gate NMOS ESD power clamp, the gate fingers are connected to Vss directly or through a resistor. The NMOS layout uses a silicide block mask to produce an unsilicided diffusion region between the source/drain contacts and the gate. The unsilicided region has higher resistance than the silicide and acts as a ballast resistance to produce uniform current flow through all legs of the transistor. A large spacing between the source/drain contacts 137, 147 and gate 120 is required to achieve a large enough resistance to provide acceptable ESD performance. This large spacing, however, leads to a large layout area for this structure. Without the ballast resistance, the current during an ESD event tends to flow through only one or a small number of fingers leading to low failure voltage See, A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, pp. 96, 283. (Wiley, 2d ed. 2002). The ballast resistance can also be implemented using a back-end ballast approach as described in K. G. Verhaege and C. C. Russ, “Wafer Cost Reduction Through Design of High Performance Fully Silicided ESD Devices,” in Proc. EOS/ESD Symp., pp. 18–28 (2000) which leads to a more area efficient layout.
A known alternative to the grounded gate NMOS device which avoids the drain junction breakdown and snapback mode of operation is shown in FIG. 3. In this alternative, circuit 300 comprises an NMOS transistor 310 having a gate 320, a source 330 and a drain 340, a timing circuit 370 comprising a capacitor 372 and a resistor 374 connected in series at a node 376 and one or more series connected inverters 380 connected between node 376 and gate 320. Timing circuit 370 and inverters 380 constitute a trigger circuit for NMOS transistor 310. The number of inverters 380 and the position of capacitor 372 and resistor 374 are chosen so that the voltage at the output of the inverters causes transistor 310 to be off during normal operation. Thus, where transistor 310 is an NMOS transistor and the number of inverters is odd as shown in FIG. 3, source 330 and the other end of capacitor 372 are connected to ground, Vss, and drain 340 and the other end of the resistor 374 are connected to Vcc. For an even number of inverters 380, the positions of capacitor 372 and resistor 374 are exchanged so that the capacitor is connected to Vcc and the resistor to ground. See, R. Merrill and E. Issaq, “ESD Design Methodology,” in Proc. EOS/ESD Symp., pp. 233–277 (1993); A. Amerasekera and D. Duvvury, ESD in Silicon Integrated Circuits, p. 178 (Wiley, 2d ed. 2002).
The NMOS transistor 310 is wide enough to handle the ESD current in the normal mode of operation with Vd=Vg. Gate 320 is held at 0V during normal operation, and is driven to Vcc when a fast ramp is detected on Vcc. The NMOS transistor does not need to use any special layout since it is operating in the normal mode. However, the width of the gate needs to be much larger than the width for a grounded gate NMOS clamp to allow the transistor to operate in the normal mode. For example, W/L=8000/0.8 for a 0.8 um technology.
The problems with the grounded gate NMOS ESD power clamp such as that shown in FIGS. 1 and 2 are:                a) The large space between the source and drain contacts and the gate results in a large structure area for the silicide block layout approach.        b) It is difficult to guarantee that the ESD power clamp will turn on before other devices connected between Vcc and Vss are damaged.        c) The above problem is exacerbated when the capacitance between Vcc and Vss is small. This leads to a very fast ramp rate of the voltage between Vcc and Vss during an ESD event.        
The problems with the non-breakdown alternative shown in FIG. 3 are:                a) The width of the NMOS device must be very large to keep the transistor away from the snapback region.        b) The trigger circuit must be tuned to work for a relatively narrow range of ESD voltage ramp rates on the Vcc bus. Since the ESD voltage ramp rate is dependent on the total capacitance between Vcc and Vss, it may not be possible to guarantee that the structure will work for any possible capacitance.        c) For a large enough capacitance between Vcc and Vss, the ramp rate of the voltage on Vcc during an ESD event may be the same or slower than the ramp rate when the circuit is being powered up during normal operation. In this case, it is impossible for the trigger circuit shown in FIG. 3 to distinguish between a normal power-up ramp and an ESD ramp which could increase to a large enough voltage to damage devices between Vcc and Vss without the ESD clamp ever turning on.        
USPTO Backgrounds
USPTO Backgrounds