In the manufacture and assembly of electronic devices, two high-density interconnection techniques—wire bond and flip chip—are commonly used to mount and electrically connect semiconductor dies (or “chips”) on interconnection substrates. The wire bond technique presents wire bond pads (typically formed from aluminum (“Al”)) on the substrate surface. The flip chip technique presents solder pads (typically formed as solder balls) on the substrate surface.
Flip chip interconnections provide the shortest electrical connecting paths, and therefore the highest electrical performance and speed. Flip chip interconnections also accommodate the greatest number of chips and chip connections within a given space because the flip chip technique can present area arrays at any location, including the center area of the die. In contrast, the wire bond technique is a perimeter method only, and is therefore more limited.
Flip chip is therefore increasingly the interconnect method of choice for high performance semiconductor devices. However, wire bonds have the important ability to “program” the wiring locations and eliminate expensive manufacturing tooling. The wire bond connection method has also been known and used for a much longer time and is much more popular. Wire bond is therefore expected to continue to be a principle interconnection method.
Input/output (“I/O”) pads for flip chips can be configured as peripheral arrays, area arrays, or both, and are given a final finish of solder-wettable metal because solder bumps are subsequently formed or connected to the I/O pads. While techniques have been tried for soldering directly to the Al pads of the underlying integrated circuit, it is well known and accepted that Al is a difficult and undesirable material for soldering. A conventional solution has therefore been to apply a finish of a different metal, or several metals, to the Al pads prior to providing the solder bumps (i.e., prior to “bumping”). Since this additional metal finish ends up under the solder bumps, it is referred to as under-bump metallization (“UBM”).
A typical UBM metal stack consists of metallic adhesion, barrier and wetting layers. One such structure that meets these requirements is a composite of layers of titanium (“Ti”), nickel-vanadium (“NiV”), and Cu. Ti is deposited first to adhere to the underlying Al pads, and typically is deposited on and adheres as well to the exposed passivation surface of the substrate outside the Al pad contact areas. Ti is known to adhere well to various materials such as Al, polyimide, benzocyclobutene (“BCB”), silicon nitride (“SixNx”), and silicon oxide (“SiOx”).
Next, NiV is deposited onto the Ti layer to barrier the diffusion of Cu into the Ti. Cu is then deposited last, onto the NiV layer.
Once the UBM metal layers have been formed, the portions thereof outside the UBM contact areas must be selectively removed in order to define the desired contact patterns. Two known removal methods have been used in forming UBM pads on wafers that are also to have Al wire-bonding pads. One method is the lift-off technique; the other is the etch-back process.
The lift-off technique involves using a shadow mask prior to formation of the UBM layers. The mask is typically a photo resist, which is an organic material. One process for depositing the UBM metals is sputtering, and, due to the organic photo resist, the lift-off technique requires rigorously controlling the sputtering temperature during deposition of the UBM metals. Unfortunately, some sputtering tools do not have sufficient temperature control capability for sputtering the relatively thick UBM metal layers. In addition, the lift-off method is often not cost effective. For example, as compared with the etch-back process, more metals are required for sputtering onto the substrate because of the shadow effect of the mask.
The etch-back process uses an etching mask following formation of the UBM layers, so no such sputtering temperature controls are required. The UBM stacks are then defined by wet etching or dry etching the deposited UBM metals that are exposed (unprotected) by the mask.
However, the etch-back process has certain limitations as well. One such limitation is selectivity. In integrated wire bond and flip chip designs, the Al pads need to be exposed for wire bonding. It is therefore important to have an etchant that selects for the UBM metals but does not select for Al. In the case of UBM structures formed of Ti/NiV/Cu, the wet etching of the Ti/NiV/Cu layers is not a problem with respect to the UBM layers, but it is a problem with respect to exposed Al wire-bonding pads due to possible poor selectivity, particularly during the Ti etching phase.
Dry etching of Ti has better selectivity over Al. However, dry etching of Ti contaminates the process chamber quickly and attacks the polyimide surface of the passivation layer. As a consequence, if the sputtering tool is not capable of supporting the lift-off technique, the wet etching of the Ti is usually the only reasonable option.
When a Cu layer is present, a typical Ti etching solution used in the semiconductor industry is a mixture of hydrofluoric acid (“HF”) and de-ionized (“DI”) water. However, Al is an amphoteric metal that can be dissolved in both acid and base. Consequently, common Ti etchants such as this typically have poor selectivity over Al, typically over 1:10 (Ti:Al). During the etching of the Ti, the Al wire-bonding pads can therefore be seriously attacked, to the extent that they become disconnected from their circuits in the die.
Another problem with respect to such wet etching with HF is that the presence of Cu and NiV in the etching process causes a residue of Ti to be left on the polyimide surface. This residue shows up only after a follow-up plasma treatment of the surface.
Still another problem with respect to wet etching is endpoint detection for the etching process. In the conventional wet etching process of Ti, at the end of the etching of the thin and shining Ti layer, the layer disappears suddenly with a lot of bubbles. This makes it hard to detect the endpoint of the entire process because the sudden disappearance of the Ti layer does not mean that the Ti on the underlying passivation layer has been cleared or removed.
Thus, a need still remains to integrate both wire bond and flip chip methods and techniques together on chips and/or their substrates. A need also remains for an effective Ti etchant for such integrated wire bond and flip chip designs. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
USPTO Backgrounds
USPTO Backgrounds