Exemplary embodiments of the present invention relate to a data input circuit.
As the integration density of semiconductor memory devices increases many efforts have been made to increase the operating speed of semiconductor memory devices. To increase the operating speed of semiconductor memory devices, synchronous memory devices have been introduced which can operate in synchronization with a clock supplied from the outside of a memory chip.
An early synchronous memory device is a single data rate (SDR) synchronous memory device which inputs/outputs data in synchronization with a rising edge of an external clock.
However, the SDR synchronous memory device could not sufficiently meet high-speed requirements of systems. In this regard, a double data rate (DDR) synchronous memory device has been introduced which processes data on both rising edge and falling edge of each clock cycle.
Accordingly, without increasing a frequency of a clock, the DDR synchronous memory device can implement at least two times the bandwidth of the conventional SDR synchronous memory device. Hence, the DDR synchronous memory device can better implement high-speed operations.
Meanwhile, the DDR synchronous memory device uses a multi-bit prefetch method which internally processes multi-bits at a time. The multi-bit prefetch method refers to a method which aligns successive input data in parallel in synchronization with a data strobe signal and stores multi-bit data, which are aligned by a write command inputted in synchronization with an external clock signal, in a memory cell array at a time.
FIG. 1 is a timing diagram illustrating a conventional multi-bit prefetch method of a data input circuit.
When a write operation is started, internal data IDATA are aligned in synchronization with a rising data strobe signal DQS_R and a falling data strobe signal DQS_F. That is, the internal data IDATA are latched in synchronization with the rising data strobe signal DQS_R and the falling data strobe signal DQS_F, and outputted as first to fourth aligned data ALGND1 to ALGND4 in synchronization with the last pulse of the falling data strobe signal DQS_F. The first to fourth aligned data ALGND1 to ALGND4 are transferred to a write driver (not shown) in synchronization with a data input clock DIN_CLK.
When the input of the internal data IDATA is completed, the data strobe signal DQS is in a precharge state during a postamble period. Meanwhile, as indicated by X1, ringing may occur in the data strobe signal DQS during the postamble. When ringing occurs in the data strobe signal DQS, ringing may also occur in the rising data strobe signal DQS_R and the falling data strobe signal DQS_F as indicated by X2. This is because the rising data strobe signal DQS_F is generated in synchronization with the rising edge of the data strobe signal DQS, and the falling data strobe signal DQS_F is generated in synchronization with the falling edge of the data strobe signal DQS.
Ringing occurring in the rising data strobe signal DQS_R and the falling data strobe signal DQS_F may latch the internal data IDATA when the internal data IDATA are not valid. Hence, the first to fourth aligned data ALGND1 to ALGND4 which are validly latched may be overwritten with invalid data, causing an error in the write operation.
USPTO Backgrounds
USPTO Backgrounds