1. Field of the Invention
The present invention relates to the field of data transfer on a high-speed data channel and, more particularly, to a grounding technique to remove jitter on the data channel.
2. Background of the Related Art
High-speed data channels are known in the art for use in the transfer of data between components or circuits resident on the channel. Typically, a data channel employs a particular bus architecture with data transfer protocol defined by the architecture. The channel architecture may also have certain physical requirements to ensure that the channel operates within the required design specifications. Further, the design specifications become more stringent as the rate of the data transfer increases (increase in the bandwidth) and meeting the design specification is imperative for proper operation of devices resident on the data channel.
High-speed data channels can be designed for the transfer of data between various circuitry on a single component (such as a semiconductor chip) or between two or more components. In the first instance, the data channel, the data sending circuitry and the data receiving circuitry are fabricated on the same substrate. In the later instance, the data channel is an interface residing outside of the chip. For example, to transfer data between a processor (or controller) and a separate memory not residing on-chip with the processor, a printed circuit (PC) board is utilized. In computer parlance, this PC board is often called the "mother board" when the central processing unit (CPU) is resident thereon or a "video card" when a graphics controller is resident thereon.
One well-known high-speed data channel architecture in use is the Rambus.upsilon. data channel (or Rambus channel). The Rambus channel is a high-speed, byte-wide (9 bits), synchronous, chip-to-chip interconnect designed to achieve 600 Mega bytes per second (MB/sec) and greater data transfer rates between components on the channel. One specific Rambus channel, referred to as the Direct Rambus.TM. channel, is specified to transfer data at 1.6 Giga bytes per second (GB/sec) between components on the channel. In order to operate on the channel, the various components operating on the Rambus channel must interface with the channel and meet the stringent requirements imposed on these components, which are referred to as Rambus components.
In a typical layout, the required power, ground and signal lines are fabricated on a PC board under strict requirements of the Rambus channel layout specifications. The various chips are then placed at designated locations on the board according to the design specifications. The components have the necessary interface circuitry for coupling onto the channel so that the components qualify as a Rambus component. For example, dynamic random-access-memories (DRAMs) meeting the Rambus specification requirements are referred to as Rambus DRAMs or RDRAMs. The RDRAMs are capable of achieving the high-speed data transfer to and from a processor (or controller) also coupled onto the channel.
Although the Rambus channel is capable of achieving high-speed data transfer between the Rambus components on the channel, jitter has been noticed to exist on the signal lines of the data channel. Upon first inspection, the signal jitter appears to be produced or induced when components, particularly processors, are placed on the channel. This is a significant problem for a system manufacturer who may purchase the DRAM, processor and the PC board from different vendors. Each meets the Rambus channel design requirements, but when assembled together, jitter is present on the signal lines of the channel. At the higher transfer rates, the jitter is more pronounced and can contribute to bit transfer errors.
The present invention identifies a source for this jitter and describes a technique for reducing or removing the jitter from the high-speed data transfer channel, such as the Rambus channel.
USPTO Backgrounds
USPTO Backgrounds