The invention relates generally to an amplifier. More particularly, the invention relates to an adjustable offset differential amplifier.
There are many uses for differential amplifiers. For example, differential amplifiers are commonly used within operational amplifiers, which are prevalent in electronics. Differential amplifiers can also be used to sense a logical state of memory cells within an array of memory cells.
Offset errors of differential amplifiers can limit performance of the differential amplifier. For example, differential amplifiers can be used to sense the resistance of a resistive memory cell. Offset errors of the differential amplifiers can hinder the reliability of the sensing of the resistive state of the resistive memory cells.
FIG. 1 shows a typical differential amplifier 100 that includes an offset error. The differential amplifier 100 can include a first input transistor 110, a second input transistor 120, a first output transistor 130 and a second output transistor 140.
An output signal VO of the differential amplifier 100 is generally linearly related to a difference between a first input V+ and a second input Vxe2x88x92. The output signal VO generally includes an offset error VOFF. The output signal can be represented by VO=A (V+xe2x88x92Vxe2x88x92)+VOFF where A is the gain of the differential amplifier 100.
Offset errors of differential amplifiers can be caused by physical design, or processing variations of the differential amplifiers. Circuit device thresholds, mismatches of device sizes, and circuit device operating conditions are all possible sources of offset errors. Physical size variations and process variations inherent in integrated circuit manufacturing processing are sources of offset errors. Processing errors are a major source of offset error in CMOS operations amplifiers that include differential amplifiers.
A technique that has been used to minimize offset errors includes manipulating transistor sizing and physical circuit element layouts. Another technique includes the use of a switched capacitor circuit. Both of these technique require special manufacturing processing steps.
It is desirable to have an apparatus and method for reducing offset error associated with a differential amplifier. It is desirable that the apparatus and method provide an adjustment of the offset errors that is linear, and reduce the offset error with a positive or negative correction. It is desirable that the apparatus and method be robust, temperature insensitive and be simple to manufacture.
The invention includes an apparatus and method for reducing offset error associated with a differential amplifier. The differential amplifier of the invention is adaptable for use within a sense amplifier of MRAM.
A first embodiment of the invention includes an adjustable offset differential amplifier. The adjustable offset differential amplifier includes a first differential transistor receiving a first differential input, and a second differential transistor receiving a second differential input. A differential amplifier output includes a signal having an amplitude proportional to a difference between the first differential input and the second differential input. The first differential transistor includes a plurality of sub first differential transistors. Each sub first differential transistor includes an adjustable back gate bias. Control circuitry can be connected to the adjustable back gate bias of each of the sub first differential transistors for reducing offset errors of the differential amplifier output.
Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.
USPTO Backgrounds
USPTO Backgrounds