An ordinary plating jig has a holding member that holds a substrate, such as a semiconductor wafer, in such a manner that an outer peripheral surface and a back surface of the semiconductor wafer are sealed, and a front surface (plating surface) thereof is exposed, and the plating surface is plated by immersing the holding member in a plating solution along with the substrate.
However, an electrolytic plating method using the ordinary plating jig has a problem that only one surface of a semiconductor wafer may be plated by one plating process, and thus the operation time is necessarily doubled for plating both the surfaces of the semiconductor wafer, which may adversely affect the in-plane uniformity of the plating thickness of the semiconductor wafer.
Under the circumstances, PTL 1 describes a plating jig having a substrate holding mechanism that holds a substrate to be plated in such a manner that the entire region of the edge portion of the substrate to be plated is sealed against a plating solution, and simultaneously the prescribed regions surrounded by the seal on both surfaces of the substrate to be plated are exposed to a plating solution. According to the use of the substrate plating jig, the prescribed regions surrounded by the seal on both the surfaces of the substrate to be plated are in contact with a plating solution, and a metal plating film may be formed simultaneously on the prescribed regions surrounded by the seal on both the surfaces of the substrate to be plated, which may solve the aforementioned problem.
In the plating jig described in PTL 1, however, the holding member itself has a certain thickness since the guide pins for positioning the substrate and the like are partially embedded therein, which may adversely affect the uniformity of plating. Furthermore, the plating jig includes a large number of members, which may increase the cost and may make the operation for replacing the seal complicated.
PTL 1: Japanese Patent No. 4,764,899
USPTO Backgrounds
USPTO Backgrounds