The technology of producing semiconductor devices has been continually pressured to increase effective device densities in order to remain cost competitive. As a result, Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) technologies have entered the sub-micron realm of structural dimension and are approaching physical limits in the nanometer feature size range. In the foreseeable future, absolute atomic physical limits will be reached in the conventional two-dimensional approach to semiconductor device design.
A two-dimensional design capacitor includes a planar capacitor (see FIG. 1). In the planar capacitor 10, the lower plate of the capacitor is formed from the n+ silicon substrate extension 12 of storage node junction 14 of field-effect transistor (FET) 15. The upper capacitor plate (or field plate) 16 is formed from a layer of conductively-doped polycrystalline silicon. Node extension 12 is electrically insulated from upper plate 16 by a dielectric layer 18.
Planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level. However, as device densities have increased, the desirable size of capacitors has grown smaller and smaller while the desirable capacitance has increased. The difficult goal of a DRAM designer is therefore to increase, or at least maintain, cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Several methods for providing adequate cell capacitance in the face of shrinking cell size are in use. Many of these efforts are aimed at creating complex three-dimensional capacitors. Such three-dimensional capacitors include trench capacitors and stacked capacitors.
Trench capacitors 19 (see FIG. 2) are employed to provide greater plate area, and therefore greater capacitance. The lower plate 20 may be formed from the n+ doped silicon substrate or it may be formed from a polysilicon layer which lines a trench cut in the n+ doped silicon substrate. The upper plate 22 is formed from a layer of conductively-doped polycrystalline silicon. Lower plate 20 and upper plate 22 are electrically insulated with a dielectric layer 24.
Another three-dimensional technique is the stacking of capacitor plates between dielectric layers on the DRAM cell surface. FIG. 3 is a graphic representation of a typical DRAM cell having a stacked capacitor 26. The lower plate 28 is formed from an n-type polycrystalline silicon layer which is in contact with the silicon substrate 30 in the region of the FET storage node junction, while the upper plate 32 is formed from a conductively-doped polycrystalline silicon layer. The two layers are separated by a dielectric layer 34. Lower plate 28 and upper plate 32 are both stacked on top of FET 36 and word line 38, resulting in a high-profile cell which requires more stringent process control for the connection of bit line 40 to access-node junction 42.
Despite the availability of these three-dimensional capacitor structures, attempts have been made to even further increase the surface area of the capacitors, thereby increasing the capacitance. One such approach is disclosed in U.S. Pat. No. 5,068,199, issued Nov. 26, 1991, of Gurtej S. Sandhu entitled "Method for Anodizing a Polysilicon Layer Lower Capacitor Plate of a DRAM to Increase Capacitance" and U.S. Pat. No. 5,138,411, issued Aug. 11, 1992 of the same inventor entitled "Anodized Polysilicon Layer Lower Capacitor Plate of a DRAM to Increase Capacitance". This patent discloses the anodization of a deposited silicon layer to form porous silicon. The deposited and anodized layer of porous silicon forms the first plate of a capacitor, which due to its porous nature has a greater surface area for capacitance. One or more of the Sandhu patents disclose a single layer of silicon nitride as the suitable thin layer dielectric for use in DRAMs where capacitative layers are not smooth (i.e. porous silicon) as well as the use of polycrystalline silicon lined trench designs. This severely limits the applicability of the structure and method disclosed in Sandhu since multi-layer dielectrics such as oxide/nitride, nitride/oxide, and oxide/nitride/oxide dielectrics offer significant advantages over single layer silicon nitride in many applications.
In Watanabe et al., A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMS, Symposium on VLSI Technology, pg. 17, May 17, 1993 the use of porous polycrystalline silicon as a substrate is taught. However, a need continues to exist for additional designs of capacitor structures with high surface area and high capacitance, without increasing the size of the capacitor structure.
USPTO Backgrounds
USPTO Backgrounds