1. Field of the Invention
The present invention relates to a semiconductor memory and, particularly, to a single chip semiconductor memory having a voltage drop circuit for stepping an externally supplied source voltage down to a source voltage for an internal circuit of the memory.
2. Description of the Prior Art
It has been known that a single chip semiconductor memory having large memory capacity includes a voltage drop circuit for stepping an externally supplied source voltage down to a voltage to be used as a source voltage for an internal circuit of the memory. Such voltage drop circuit should have a construction capable of keeping an increase of power consumption thereby minimum. One of schemes for realizing such requirement is disclosed in Japanese Patent JPA 2-195596.
A semiconductor memory disclosed therein is equipped with a voltage drop circuit including a pair of parallel connected driver circuits which have a common output terminal and have different current supply capabilities. One of the driver circuits, that is, the so-called stand-by driver circuit, is operative in both stand-by and active modes of the memory. However, since the stand-by driver circuit is enough to supply only current flowing through a whole internal circuit in stand-by mode of the memory (referred to as "stand-by internal circuit current", hereinafter), its current supply capability and hence its power consumption is small. On the other hand, the other driver circuit, that is, the so-called active driver circuit, is operative in the active mode of memory and has to supply maximum current of the internal circuit in that mode. Therefore, its current supply capability and hence power consumption is larger correspondingly. The active driver circuit is inoperative in the stand-by mode, so that power consumption of the whole memory is reduced, allowing high integration density and large memory capacity.
However, when the above memory is constructed with CMOS's, the reduced power consumption causes read/write speed to be lowered. This problem tends to occur when a signal input stage of the memory is constructed with a CMOS inverter. As well known, such CMOS inverter consumes power in only a transient period of an input signal and, therefore, its power consumption is very small. However, when the input signal is a TTL level signal from a TTL, a large current flows through the CMOS inverter even when the signal is a DC signal. Further, when the signal is a MOS level signal, current proportional to a frequency of on-off switching thereof flows therethrough.
Therefore, when the input signal to the semiconductor memory is the TTL level signal or when, although the input signal is a MOS level signal, it repeats on-off switching as in the case of an input signal to a memory device which includes a plurality of identical memories connected in parallel to each other in order to increase its memory capacity and which is, in stand-by mode, a large current flows in the signal input stage thereof and the stand-by internal circuit current substantially increases even if the memory device is in stand-by mode. For example, for an SRAM of 4 M bits size, the stand-by internal circuit current which is usually in the order of several tens .mu.A could become several tens mA.
Since, however, the current supply capability of the stand-by driver circuit of the memory disclosed in the aforementioned prior art is limited as mentioned, such substantial increase of the stand-by internal circuit current makes an output voltage of the stand-by driver circuit, that is, an internal power source voltage of the memory chip, lower substantially. As a result, there may be failure of memory content of memory cells and/or failure of read/write speed due to delay of recovery of the internal power source voltage when the operation mode is switched from stand-by mode to active mode. In order to avoid the above mentioned failures without limiting selectivity of circuit to which the memory chip is to be connected, it might be possible to preliminarily design current supply capability of the stand-by driver circuit large enough to accomodate a possible increase of current in the signal input stage thereof. In such case, however, power consumption of the stand-by driver circuit itself will be substantially increased.
Another approach for avoiding the above mentioned failures might be to provide the so-called power-cut function in the input stage of the internal circuit. That is, an operation of the input stage is inhibited in synchronism with a start control signal of the memory such as an RAS signal of a DRAM or a CS (chip select) signal of an SRAM to cut off a signal input to thereby restrict i of the stand-by internal circuit current. The power-cut function, however, must be stopped in a period in which the memory mode is shifted from stand-by mode to active mode. Therefore, the read/write operation of the memory is substantially delayed in such period.
USPTO Backgrounds
USPTO Backgrounds