1. Technical Field
This description generally relates to the field of electronic packaging, and, in particular, to mechanical components of electronic packages.
2. Description of the Related Art
Issues of mechanical and electrical reliability are of growing interest in ball bonded wafer-level packages, especially as the size of wafer-level packages increases. Larger package sizes increase the likelihood of mechanical failures, particularly at or near solder joints, from either externally applied mechanical stress or developed stress due to thermal expansion. Mechanical failures often lead to electrical failures.
One common mechanical failure mode in wafer-level packages is passivation or redistribution layer delamination. FIG. 1 shows an example of a delamination failure, exhibited by a delamination crack 10 in a passivation layer 12. The delamination crack 10 in FIG. 1 developed as a result of a series of controlled drops conducted as part of a drop test failure analysis. The test was performed according to a mechanical strength testing protocol prescribed for packages used in portable communication devices. The test included a series of drops by a sufficient number of samples to determine a failure rate. FIG. 1 shows that the delamination crack 10 enters the passivation layer 12 at a point 14 next to a solder joint 16 and then passes through the passivation layer 12 above a solder bond pad 18.
Another common failure mode in wafer-level packages is a crack in a silicon die 20 of the package. FIG. 2 shows a silicon die crack 22 that passes around the solder joint 16 by propagating through the silicon die 20. The silicon die crack 22 appears as a horizontal line passing through the silicon die 20 above the solder bond pad 18. In this failure, the bond pad 18 detaches from the silicon die 20 and remains bonded to an attached solder ball 24.
Yet another common failure mode in wafer-level packages is a crack in the solder ball 24. FIG. 3 shows a solder bond crack 26 that passes around the solder joint 16 by propagating through the solder ball 24 parallel with the solder joint 16. This failure typically occurs at a point 28 where the solder ball 24 meets the solder bond pad 18, because this is the narrowest point of the solder ball 24.
Techniques have been developed in the packaging field to attempt to reduce these failures by relieving the stress that must be carried by the bond between the solder ball 24 and its bond pad 18. One technique is the application of a polymer flux 30 to the solder ball 24 at the point where the solder ball meets the silicon die 20 or a redistribution layer if one is used. As shown in FIG. 4, the polymer flux 30 supports the solder ball 24 close to the bond pad 18 at the solder joint 16. The flux 30 carries a portion of the stress that would formerly have been carried entirely by the solder joint 16. The polymer flux 30 is applied at the same time that the solder ball 24 is applied to the bond pad 18, and therefore there involves no extra process step. A disadvantage of this technique is the difficulty in maintaining consistent thickness of the polymer flux 30. Since package reliability is subject to the polymer flux thickness, inconsistent thickness control gives rise to undesirable variations in reliability.
Another technique in the prior art that attempts to improve mechanical and electrical reliability is the front side protect technique. With the front side protect technique, a polymer material 32 is applied to a face of an electronic package 34 after the solder balls 24 have been placed on the bond pads 18. As shown in FIG. 5, the polymer material 32 couples the solder balls 24 and the package 34 in the same way as the polymer flux technique in FIG. 4. One problem with the front side protect technique is that because the polymer material 32 is applied after the solder balls 24 are placed, voids 33, 35 can form in the polymer material at the point where the solder ball 24 and the bond pad 18 meet. The size and location of these voids 33, 35 cannot be easily controlled or predicted. A void 33, 35 at this point severely diminishes the strengthening effect of the front side protect technique. The front side protect technique was used in the example of FIG. 3, yet a solder bond failure occurred anyway.
A third technique in the art is underfill, shown in FIGS. 6A and 6B. As shown in FIG. 6A, with the underfill technique a fluid polymer underfill 36 is dispensed into a space between an electronic package 34 and a printed circuit (PC) board 40, in and around the solder balls 24 that mount the electronic package 34 to the PC board 40, and then cured. As shown in FIG. 6B, once cured the underfill 36 mechanically couples the electronic package 34 to the PC board 40. One disadvantage of this technique is that it requires careful matching of the coefficients of thermal expansion of the electronic package 34 and the PC board 40. A second disadvantage is that component rework is made more difficult. If the electronic package 34 needs to be removed from the board for any reason, this is made more difficult by the underfill 36, which can lead to destruction of the package 34 during removal. Even if successful, the underfill 36 left behind on the PC board 40 must still be removed before a new electronic package 34 can be reconnected to the PC board 40.
USPTO Backgrounds
USPTO Backgrounds