Memory array circuits are used in numerous different devices including processors, controllers, memory components, and other integrated circuit chips (chips). Unfortunately, even when they are not being used, for example, when they are in so-called “sleep modes,” they can waste a considerable quantity of power due to leakage currents in their constituent transistors. With MOS transistors, for example, even when the transistors are turned off, so-called sub-threshold leakage occurs between the drain and the source and so-called gate leakage occurs between the gate and source/drain. While such leakage may not be significant for an individual transistor, overall leakage for an array of cells can quickly add up given the numerous transistors used in many array circuits. This is problematic, especially considering the prevalence of portable devices such as laptop computers, cell phones, and personal device assistants (“PDA”s) where reduced power consumption is always an important design consideration.
FIG. 1 illustrates a portion 100 of a MOS memory array with a known solution for reducing current leakage when the memory array is disabled, e.g., during a standby mode. Circuit portion 100 includes a word-line driver circuit 102, a row of bit cells 104 (BIT CELL 0 through BIT CELL N), a ground elevation transistor M109, and an operational ground transistor M110. Driver circuit 102 comprises a word-line inverter amplifier formed from transistors M107 and M108 connected as a conventional PMOS/NMOS inverter with an input at the commonly connected gates and an output at the commonly connected drains. The input is coupled to a word-line activation signal (WL#), while the output is coupled to a word-line node (WL).
A circuit for BIT CELL 0 is depicted and is representative of the other bit cells 104. It is formed from MOS transistors M101 through M107 connected, as depicted, in a conventional bit cell configuration with complementary bit lines, BL and BL#, at the drains of transistors M104 and M105, respectively. Each bit line functions as both an input and an output. Access to the bit lines is controlled by the word-line node (WL), which is connected to the gates of the bit line transistors M204, M205. The bit cell transistors are powered by a supply voltage (Vcc) and a virtual ground through a virtual ground node (VSSV). The driver circuit 102 is coupled to the row of bit cells 104 through the word line node (WL), which activates the row of bit cells 104 when the word-line inverter M107/M108 outputs a High at the word-line node in response to a Low at the word-line activation signal (WL#). Conversely, a Low voltage is output at the word-line node (WL) to deactivate the row of bit cells 104 when the word-line activation signal (WL#) is High.
Both the ground elevation transistor M109 and operational ground transistor M110 are coupled between ground and a virtual ground node (VSSV) for the row of bit cells 104. With its gate connected to a supply voltage (Vcc) the ground elevation transistor M109 is always turned on. Its size is chosen such that the potential of VSSV is nominally between 150 mV to 350 mV above the ground potential. A memory array standby signal (STANDBY#) is applied at the gate of operational ground transistor M110, which is large relative to the ground elevation transistor M109. When the array is enabled to perform an access (read or write), the STANDBY# signal is negated (High), and the large operational ground transistor M110 turns on, which pulls the virtual ground node (VSSV) sufficiently near to the ground potential for the row of bit cells 104 to operate when the word-line is active (High). Pulling the VSSV node near to ground during an array access provides higher read current and assures bit-cell stability.
On the other hand, when the array is disabled (placed in standby mode), the STANDBY# signal is asserted (Low) to turn M110 off and allow the VSSV node to return to its nominal, leakage reduction level (the value of which is dictated by transistor M109). When the array is in standby mode, the elevated virtual ground potential on VSSV reduces many of the leakage currents associated with the bit cells 104. Specifically, leakage is reduced on the four paths through M104 and M102 (BL to VSSV), M105 and M106 (BL# to VSSV), M101 and M102 (Vcc to VSSV), and through m103 and m106 (Vcc to VSSV). (Note that when in standby, typically, the WL node is held Low, and the BL and BL# nodes are held High.)
Unfortunately, however, this leakage reduction solution does not reduce gate leakage from the paths through M104 and M108 (BL to ground through M108) and M105 and M108 (BL# to ground through M108), and sub-threshold leakage through the path through M107 and M108 (Vcc to ground). Accordingly, different embodiments discussed herein redress some or all of these not addressed current leakage paths.
USPTO Backgrounds
USPTO Backgrounds