The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (random access memory) requiring a refresh.
An example of how a conventional dynamic RAM is configured is shown in FIG. 1. In the figure, the dynamic RAM is partially illustrated, with a pair of bit lines BLj and BLj (j=1, 2, 3, . . .) and their peripheral circuitry. Each of memory cells MC1, MC2, . . . is made up of a capacitor Cs and a transfer gate (MOS FET) Q. A charged state of the capacitor Cs represents data "1", while a discharged state of it, data "0". To select memory cells MCi (i=1, 2, 3, . . .), the transfer gates Q of the memory cells MC1, MC2, . . . are selectively controlled in conduction by potentials of the word lines WL1, WL2, . . . , respectively. To select a specific memory cell MCij, the word lines WL1, WL2, . . . and the bit line pair BLj and BLj are driven. The data is read out from the selected memory cell MCij onto the bit line pair BLj and BLj. The data read out is amplified by a sense amplifier 11. The sense amplifier 11 is controlled by a sense amplifier enable signal SE. Dummy cells DC1 and DC2 are provided for the bit line pair BLj and BLj in a one-to-one correspondence manner. These dummy cells DC1 and DC2 are selected by the word lines DWL1 and DWL2, respectively. To read out the data from the memory cells MC3 and MC4 connected to the bit line BLj, the dummy cell DC2 is selected. The capacitances of the capacitors CsD1and CsD2 of the dummy cells DC1 and DC2 are respectively selected to be half the capacitance of the capacitors Cs of the memory cells MC1, MC2, . . . The data stored in memory cells MC1 and MC2 are respectively read out lines DL and DL and each item of data is represented by a potential or the bit line pain BLJ and by, which is amplified by the sense amplifier. The transfer gates Q1 and Q2 are controlled in conduction by the output signal DCj of a column decoder (not shown). The data read out of the memory cell MCij onto the data line pair DL and DL are output as read out data Dout through an input/output circuit 12. The write data Din is written into the memory cell MCij through the input/output circuit 12 in in reverse order in which it was read out. The bit line pair BLj and BLj are inevitably accompanied by stray capacitances Ca and Cb, respectively.
The charge stored in the memory cells MC1, MC2, . . . , as data, leaks and decreases with time. To cope with this stored charge decrease problem, it is necessary to read out the data before it completely disappears, and to write the same data into the memory cells, again. This operation is called a refresh. The refresh is essential to the dynamic RAM. In a dynamic RAM of 256 Kilo bits, all of the memory cells are refreshed every 4 mS. The refresh restrains the normal memory operation speed of the dynamic RAM. For example, as shown in FIG. 2, the refresh Rf is required every fixed period. During this period Rf, the normal memory operation Na is impossible. During the refreshing period of the memory cell MC1, for example, the potentials on the bit line pair BLj and BLj correspond in magnitude to the data stored in the memory cell MC1. Under this condition, it is impossible to read out the data from other memory cells connected to the bit line pair BLj and BLj. Thus, during the refreshing period, any attempt to gain access to these other memory cells connected to the same bit line pair BLj and BLj is rejected. For this reason, to gain access to the memory cells, the user must wait till the refreshing operation terminates. This makes the access time long and it difficult to speed up the memory operation.
The refresh operation and the normal memory operation, i.e. the read and the write operations, will be described referring to a timing chart shown in FIG. 3. At time t0, the first cycle of the operation of the dynamic RAM starts when an address signal Add changes or a chip enable signal is applied to the RAM. At time t1, any one of the word lines WL1, WL2, . . . (in this example, the word line WL1) is selected by the output signal of a row decoder (not shown). Upon this selection, the word line WL1 becomes "H" in logical level, and a memory cell MC1 is selected. The data is read out from the memory cell MC1 onto the bit line BLj connected to this memory cell MC1. At this time the word line DWL1 is "H", and a signal as a reference is read out of the dummy cell DC1 to the bit line BLj. Then, the potentials on the bit line pair BLj and BLj start to change. The sense amplifier enable signal SE becomes "H" in logical level (time t2), and the sense amplifier 11 is operated. Then, these potentials are differentially amplified. One of the potentials is "H", and the other is "L" in level. At this time, the word line WL1 is "H". Therefore, the transfer gate Q of the memory cell MC1 is in an on state. Accordingly, the memory cell MC1 is refreshed by the output signal of the sense amplifier 11.
In a read out mode of the RAM, the bit line pair BLj and BLj are set to "L" or "H" level by the output signal of the sense amplifier 11. Under this condition, if this column is selected by the output signal CDj of the column decoder, the transfer gates Q1 and Q2 are turned on. As they are turned on, these transfer gates allow the potentials on the data lines DL and DL to be applied to the input/output circuit 12 (time t3). At time t4, an output signal Dout, which is waveshaped by the input/output circuit 12, is obtained.
As described above, the dynamic RAM requires a smaller number of circuit elements than the static RAM. However, the former has a disadvantage that it is difficult to increase the memory speed. Further, users of the dynamic RAM must inevitably find the optimum timing for the refresh operation. This work is troublesome for the users.
USPTO Backgrounds
USPTO Backgrounds