1. Field of the Invention
Embodiments of the invention relate to nonvolatile semiconductor memory devices and related methods of operation.
2. Discussion of Related Art
Generally, read and write (programming/erase) operations for memory cells in a nonvolatile semiconductor memory device are carried out by controlling bit line voltages corresponding to selected memory cells. In order to properly drive bit lines voltages during a read or programming operation, contemporary nonvolatile semiconductor memory devices provide one or more page buffers to temporarily store the data to be written into or read from the memory cells.
FIG. 1 is a diagram illustrating a conventional nonvolatile semiconductor memory device, and FIG. 2 is a diagram illustrating a typical column gate YG and corresponding page buffer PBP in the memory device of FIG. 1. The conventional semiconductor memory device comprises a memory cell array 10 comprising a plurality of memory cells, connected to a plurality of “n” page buffers PBP. Each page buffer PBP is connected to a global data line GDL through a column gate YG.
Each page buffer PBP comprises a sense latch 150, precharge circuit 140, a bit line (BL) shielding block 120 and a BL bias circuit 110. In the conventional page buffer PBP, data to be written to a selected memory cell is loaded and latched in sense latch 150. Data stored in sense latch 150 is thus provided to bit line BLe or BLo through BL shielding block 120 and BL bias circuit 110. Thereafter, a programming operation may be performed relative to the selected memory cell. In similar fashion, data to be read from a selected memory cell is temporarily stored in sense latch 150. Data thus stored in sense latch 150 may be transferred to the global data line GDL in response to a column gate signal (not shown).
USPTO Backgrounds
USPTO Backgrounds