As semiconductor devices scale to smaller dimensions, metal interconnects that form part of device circuitry are also scaling to smaller dimensions. In order to maintain the resistance-capacitance (RC) delay at acceptable levels it may be useful to reduce the materials resistance in a metal interconnect. However, conventional metal interconnects such as copper interconnects are formed using a dual Damascene process in which copper is deposited into patterned features where interconnect lines are to be formed. This may limit the grain size of the copper material, which may increase resistivity due to grain boundary scattering, among other phenomena. This smaller grains size may in turn raise the RC delay and hence limit the speed of the circuits.
In principle, larger-grain metal materials such as copper may be formed if a metal is deposited as a blanket layer. However, if metal is first deposited as a blanket layer, formation of interconnect wiring entails etching of the metal layer after deposition to pattern the metal layer. It is with respect to these and other considerations that the present improvements have been needed.
USPTO Backgrounds
USPTO Backgrounds