1. Field of the Invention
The present invention relates to cascoded level shifters and in particular to the protection of components of such cascoded level shifters.
2. Description of the Prior Art
It is known to provide level shifters which transform a signal in one voltage domain into an output signal in another voltage domain. For example, in the SOC (system-on-chip) context, whilst on-chip components may operate in a lower voltage domain, it is often desirable for those components to be able to pass signals off-chip, where such signals may be required to signal to devices operating in a higher voltage domain. This may be due to a given protocol to which the signals should adhere.
Whilst techniques are known for providing such functionality, difficulties arise with the trend for on-chip components becoming ever smaller. With state of the art CMOS technologies, both core and I/O (input-output) device power supplies have moved to lower voltages in order to reach the contemporary speed and power consumption levels required. In parallel, transistor dimensions and oxide thicknesses have also decreased.
For example, in 45 nm technologies, the “standard” external power is now 1.8V (where it was 3.3V or 2.5V). To be able to reach the high frequencies demanded of these 1.8V devices, the oxide thickness has decreased to around 28 to 32 Å (where it was previously around 50 Å).
However, in order to be compatible with older devices and some existing standard protocols, it is desirable for level shifter devices to be able to operate at a higher voltage than their nominal voltage (e.g. a level shifter operating at 1.8V nominal voltage being able to provide signals for a 3.3V voltage domain).
Such an arrangement can be problematic, due to the potential for components in the 1.8V voltage domain being exposed to excessive voltage differences, potentially overstressing those components. This overstress can lead to reduced component lifetimes due to such phenomena as oxide breakdown and hot carrier injection (HCI).
In particular, in the example of such level shifter devices which interface between two voltage domains, problems can arise during switching events (i.e. when the input signal transitions, thus causing the output signal to transition) when transient stress on components can easily arise. Experience has shown that these problems are particularly likely to arise in the cascoded devices in such level shifters.
Furthermore, in the context of these ever-smaller technology scales, it is typically a key requirement that power consumption should be kept as low as possible, meaning that it is highly desirable for the DC power consumption of such devices to be kept as low as possible.
FIG. 1 schematically illustrates a prior art level shifter 100 comprising PMOS driver switches 105 and 110, each cascoded with a PMOS cascode switch 115 and 120 respectively. Level shifter 100 further comprises NMOS driver switches 125 and 130, each cascoded with an NMOS cascode switch 135 and 140 respectively. The level shifter operates with reference to two voltage supplies, namely DVDD (3.3V) and DVDD2 (1.8V).
PMOS driver switches 105 and 110 are cross coupled, the gate of PMOS driver switch 105 being coupled to node B and the gate of PMOS driver switch 110 being coupled to node A.
PMOS cascode switches 115 and 120 have their respective gates connected together and tied to a reference voltage of 1.8V (DVDD2). Similarly NMOS cascode switches 125 and 140 have their respective gates connected together and tied to a reference voltage of 1.8V (DVDD2).
The input signal (IN) to the level shifter 100 is connected to the gate of NMOS driver switch 130, whilst the inverted input signal (NIN) is connected to the gate of NMOS driver switch 125. The high range output signal NOUTHIGH is generated at node B, whilst the low range output signal NOUTLOW is generated at node C.
Whilst this level shifter performs adequately during DC conditions, during transitions of the input/output signal there exists the risk of the cascoded devices being overstressed, as explained in the following.
In the example where input signal IN is at 0V before the transition, NOUTLOW is at 1.8V and the midpoint node MID between the upper and lower halves of the level shifter is at 3.3V. When a transition starts (in this case where input signal IN switches from low to high) NOUTLOW is pulled down very quickly by the switching of NMOS driver switch 130, but NMOS cascode switch 140 will remain off until its ground-source voltage (VGS) is above its threshold (>1 Vt). This then means that the MID node won't fall as quickly as NOUTLOW.
In consequence in the early stage of the transition, the drain-source voltage (VDS) of NMOS cascode switch 140 given by VMID-VNOUTLOW can become rather high, stressing this switch and leading to a reduced lifetime due to the degrading phenomena mentioned above.
A similar problem can occur on the PMOS side for the opposite transition. When input signal IN is at 1.8V before the transition, NOUTHIGH is at 1.8V and the node MID is at 0V. When a transition starts (in this case where input signal IN switches from high to low) NOUTHIGH is pulled up very quickly by the switching of PMOS driver switch 110, but PMOS cascode switch 120 will remain off until its ground-source voltage (VGS) is above its threshold (>1 Vt). This then means that the MID node won't rise as quickly as NOUTHIGH.
In consequence in the early stage of the transition, the drain-source voltage (VDS) of PMOS cascode switch 120 given by VNOUTHIGH-VMID can become rather high, stressing this switch and also leading to a reduced lifetime due to the degrading phenomena mentioned above.
Accordingly, it would be desirable to provide an improved technique which enabled cascoded level shifters to provide a power-efficient interface between voltage domains, without the components of those level shifters that are designed to operate at lower nominal voltages being stressed by exposure to excessive voltage differences resulting from the interface to a higher voltage domain.
USPTO Backgrounds
USPTO Backgrounds