An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor-forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
Complementary NMOS and PMOS field effect transistors are commonly called CMOS. There is a continual effort to decrease the size of CMOS devices so as to increase the speed of integrated circuitry formed from the devices. As the size of the NMOS and PMOS field effect transistors is decreased, undesired hot-carrier effects can become prevalent. Such hot-carrier effects can seriously degrade the performance characteristics of MOSFET (metal-oxide-semiconductor-field-effect-transistor) devices.
Since small circuitry is desired, several methods have been developed to avoid hot-carrier effects in MOSFET devices. Among these methods are the creation of graded junctions in NMOS or PMOS devices. Graded junctions are formed by creating a lightly doped buffer region between the heavily doped drain and the channel, outside of the channel. This produces a MOSFET device which has a graded or lightly doped extension. The graded junction reduces the maximum electric field near the drain by making the pn junction less abrupt. The reduction in the electric field reduces the hot-carrier effects in the MOSFET device.
A method for producing graded junctions in PMOS devices involves placing spacers adjacent a transistor gate and over a light dose of boron or BF.sub.2 which has been previously implanted within the substrate operatively adjacent the gate. The method then involves implanting a heavy dose of boron or BF.sub.2 within the substrate operatively adjacent the spacers and offset from the gate. A similar method can be used to produce graded junctions in NMOS devices if arsenic is used as a dopant in place of boron. An alternative method for producing graded junctions in NMOS devices involves adding phosphorus to arsenic-doped source and drain regions and driving the faster-diffusing phosphorus laterally ahead of the slower-diffusing arsenic with a temperature diffusion step.
A challenge in CMOS fabrication is to synchronize the fabrication of the paired NMOS and PMOS devices so that the desired construction of both types of devices results after all fabrication. When CMOS processes involve the formation of NMOS devices prior to formation of PMOS devices, the NMOS devices are generally subjected to high temperature processing while the PMOS devices are formed. This can lead to excess and undesired diffusion of n-type dopants in the NMOS devices. The problem is exaggerated when phosphorus is used to form graded junctions in the NMOS devices because phosphorus tends to diffuse quite rapidly.
Similarly, when CMOS processes involve the formation of PMOS devices prior to formation of NMOS devices, the PMOS devices are generally subjected to high temperature processing while the NMOS devices are formed. This can lead to excess and undesired diffusion of p-type dopants in the PMOS devices.
It is therefore desirable to develop CMOS processing methods which synchronize the steps of formation of the NMOS devices and PMOS devices such that graded junctions are formed in the NMOS or PMOS devices without over-diffusion of the graded junction dopant during subsequent processing steps.
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