1. Field of the Invention
The present invention relates to a solid-state imaging device provided with an element isolation portion formed of a STI (Shallow Trench Isolation) that is a grooved portion of a semiconductor substrate and a method for manufacturing the same and relates to an interline transfer CCD image sensor.
2. Related Background Art
In recent years, attention has been drawn to a solid-state imaging device provided with an amplification-type MOS transistor. In this solid-state imaging device, for each pixel, a signal detected by a photodiode is amplified by a MOS transistor, and the device has a feature of high sensitivity.
FIG. 6 is a circuit diagram showing a configuration of a conventional solid-state imaging device 90. The solid-state imaging device 90 includes a plurality of pixel cells 99 arranged in a matrix form on a semiconductor substrate 10. Each of the pixel cells 99 includes a photodiode 93 that converts incident light into a signal charge and stores the signal charge. In each of the pixel cells 99, a transfer transistor 94 for reading out the signal charge stored in the photodiode 93 is provided.
Each of the pixel cells 99 includes an amplify transistor 12. The amplify transistor 12 amplifies the signal charge read out by the transfer transistor 94. In each of the pixel cells 99, a reset transistor 11 is provided. The reset transistor 11 resets the signal charge read out by the transfer transistor 94.
The solid-state imaging device 90 includes a vertical driving circuit 15. A plurality of reset transistor control lines 111 are connected to the vertical driving circuit 15. The reset transistor control lines 111 are arranged parallel with each other at predetermined intervals and along a horizontal direction so as to be connected to the reset transistors 11 that are respectively provided in the pixel cells 99 arranged along the horizontal direction. A plurality of vertical select transistor control lines 121 further are connected to the vertical driving circuit 15. The vertical select transistor control lines 121 are arranged parallel with each other at predetermined intervals and along the horizontal direction so as to be connected to vertical select transistors that are provided respectively in the pixel cells 99 arranged along the horizontal direction. The vertical select transistor control lines 121 determine a row from which a signal is to be read out.
A source of each vertical select transistor is connected to a vertical signal line 61. A load transistor group 27 is connected to one end of each vertical signal line 61. The other end of each vertical signal line 61 is connected to a row signal storing portion 28. The row signal storing portion 28 includes a switching transistor for capturing signals from one row. A horizontal driving circuit 16 is connected to the row signal storing portion 28.
FIG. 7 is a timing chart for explaining an operation of the conventional solid-state imaging device 90.
When a row selection pulse 101-1 is applied so as to make a level of a vertical select transistor control line 121 high, the vertical select transistors in the selected row turn ON, so that the amplify transistors 12 in the selected row and the load transistor group 27 form a source follower circuit.
While the row selection pulse 101-1 is at a high level, a reset pulse 102-1 for making a reset transistor control line 111 at a high level is applied so as to reset a potential of a floating diffusion layer to which a gate of each of the amplify transistors 12 is connected. Next, while the row selection pulse 101-1 is at the high level, a transfer pulse 103-1 is applied so as to make a level of transfer transistor control lines high, which allows a signal charge stored in each of the photodiodes 93 to be transferred to the floating diffusion layer.
At this time, each of the amplify transistors 12 connected to the floating diffusion layer has a gate voltage equal to the potential of the floating diffusion layer, which allows a voltage that is substantially equal to this gate voltage to appear across the vertical signal line 61. Then, a signal based on the signal charge stored in the photodiode 93 is transferred to the row signal storing portion 28.
Next, the horizontal driving circuit 16 sequentially generates column selection pulses 106-1-1, 106-1-2, . . . so as to extract the signals that have been transferred to the row signal storing portion 28 as an output signal 107-1 corresponding to those obtained from one row.
FIG. 8 is a plan view for explaining a configuration of the photodiode 93 and the transfer transistor 94 that are provided in the conventional solid-state imaging device 90. FIG. 9 is a cross-sectional view taken along a line AA shown in FIG. 8.
The photodiode 93 is a buried-type pnp photodiode that includes a surface shield layer 85 formed at a surface of a semiconductor substrate 10 and a storage photodiode layer 86 formed below the surface shield layer 85. The surface shield layer 85 has a conductivity type opposite to that of the semiconductor substrate 10 and the storage photodiode layer 86 has the same conductivity type as that of the semiconductor substrate 10. The storage photodiode layer 86 is formed at a position of about 1 μm in depth.
The transfer transistor 94 is formed adjacent to the photodiode 93 and includes a gate electrode 53 formed on the semiconductor substrate 10 and a source 87 and a drain 88 formed on each side of the gate electrode 53.
In recent years, the microfabrication of transistors has rapidly progressed. Following this, depths of the source 87 and the drain 88 have been rapidly made shallower, which are currently about 0.1 μm.
Between the photodiode 93 and the transfer transistor 94, an element isolation portion 2 formed of a STI (Shallow Trench Isolation), which is a grooved portion of the semiconductor substrate 10 is formed so that the photodiode 93 and the transfer transistor 94 are isolated from each other.
An element isolation portion 2A is formed so that the photodiode 93 is isolated from another photodiode 93 contained in a pixel cell 99 adjacent to the pixel cell 99 containing the photodiode 93.
The element isolation portion 2 and the element isolation portion 2A are formed at up to a depth of about 300 nm. As the microfabrication of transistors proceeds, the element isolation portion 2 and the element isolation portion 2A are increasingly made shallower. This is because as the microfabrication proceeds, the width of the element isolation portion becomes narrower rapidly, and if the element isolation portion is grooved deeply, its aspect ratio becomes large, which makes it impossible to fill an oxidation film in that portion.
In this way, the storage photodiode layer 86 of the photodiode 93 is formed at a position deeper than the element isolation portion 2 and the element isolation portion 2A.
FIG. 10 is a cross-sectional view along the line AA shown in FIG. 8 for explaining configurations of a photodiode and a MOS transistor that are provided in another conventional solid-state imaging device. The same reference numerals are assigned to the elements having the same configurations as those of the elements described with reference to FIG. 9, and therefore detailed explanations for these elements will be omitted.
A p-type well 202 is formed on an n-type semiconductor substrate 201. A depth of an interface between the n-type semiconductor substrate 201 and the p-type well 202 is set at about 2.8 μm. A density of the n-type semiconductor substrate 201 is set at about 2×1014 cm−3 and a density of the p-type well 202 is set at about 1×1015 cm−3.
A charge stored in the photodiode 93 is discharged directly to the semiconductor substrate 201 as indicated by an arrow 203. This well structure can prevent a charge occurring at a deeper portion of the substrate also from reaching to the photodiode 93 and to the transfer transistor 94.
In the above-described configuration shown in FIG. 9, however, when the photodiode 93 converts incident light into a signal charge so as to let the storage photodiode layer 86 store the signal change, the signal charge stored in the storage photodiode layer 86 flows beyond the element isolation portion 2 and into the source 87 of the transfer transistor 94 as indicated by an arrow 81. As a result, there is a problem that a saturation charge capacity of the photodiode 93 decreases.
In addition, the signal charge stored in the storage photodiode layer 86 flows beyond the element isolation portion 2A and into the adjacent photodiode 93 as indicated by an arrow 82. As a result, there is a problem of a phenomenon called color mixture, which degrades the reproducibility of colors by the imaging device.
Furthermore, when a signal charge 79 that occurs at a deeper portion of the semiconductor substrate 10 due to the incident light enters into the adjacent photodiode 93 as indicated by an arrow 83 or enters into the source 87 of the adjacent transistor 94 as indicated by an arrow 84, the color mixture or the deterioration of sensitivity would occur.
Also with the configuration shown in FIG. 10, there occur inevitable problems of a deterioration of the saturation charge capacity of the photodiode, the color mixture and the deterioration of sensitivity.
A divide 204 is formed at a position of about 1.8 μm in depth that is around the midpoint between the lower end of the p-type well 202 and the lower end of the storage photodiode layer 86. Although a charge occurring at a position shallower than the divide 204 arrives at the photodiode 93, a charge occurring at a position deeper than the divide 204 does not arrive at the photodiode 93, which degrades the sensitivity.
Note here that the divide 204 represents a virtual border line between an electron flowing on a surface side due to thermal diffusion in terms of probabilities and an electron flowing through a deep portion of the substrate.
The following describes more details of the above-stated discharge to the semiconductor substrate 201. When a charge is discharged from the photodiode 93 to the semiconductor substrate 201, a depletion layer that extends from a side of the photodiode 93 toward the semiconductor substrate 201 through the p-type well 202 and a depletion layer that extends from the n-type semiconductor substrate 201 toward the photodiode 93 through the p-type well 202 contact with each other at the divide 204.
In this case, a charge overflowing the saturated photodiode 93 passes through the depletion layer to which an electric field is applied, and therefore the charge is discharged along the electric field to the n-type semiconductor substrate 201 without moving randomly. This is the same operation as in a well-known interline transfer type vertical overflow drain structure in which each pixel cell unit has a photodiode and a vertical CCD. Such a discharge method is called a junction FET mode.
USPTO Backgrounds
USPTO Backgrounds