Voltage regulators are known that can convert from input voltages above, below, or equal to controlled output voltages, respectively performing buck mode regulation, boost mode regulation, or buck-boost mode regulation. Regulator architecture typically is provided for power supplies for automotive applications, lap-top computers, telecom equipment and distributed power systems. A known “four-switch” buck-boost converter is described in an October 2001 datasheet for the LTC3440 “Micro-power Synchronous Buck-Boost DC/DC Converter” integrated circuit manufactured by Linear Technology Corporation. Two of the four switches are connected to the input side of an inductor, the other switches connected to the output side. In accordance with the level of voltage output to be controlled and the level of voltage input, the regulator has the capability of assuming a plurality of operation states in which the switches variously are sequentially activated or deactivated, to connect the inductor to the input, the output, and/or a common potential.
The aforementioned copending Flatness et al. application 11/052,480 describes a four switch regulator that operates at a constant clock frequency, the switches controlled in a peak current mode in boost operation and a valley current mode in buck operation. A single current sensing element provides input to a control circuit, the input indicative of current in the regulator inductor. The switches are controlled in response to this input to configure connection of the inductor to regulate output voltage. The sensing element dissipates current only during a portion of the control cycle, thereby conserving power.
The switching regulator is exemplified in the schematic block diagram of FIG. 1. An input voltage from a power source is applied to input terminal Vin. A preset output voltage is regulated at the Vout terminal. Connected in series between the input and output terminals are a first switch 22, inductor 24, and a second switch 27. Switches 22 and 27 preferably are MOSFETs, although any controlled switching device may be utilized.
An input capacitor 28 is connected between the input terminal and the common potential. An output capacitor 30 is connected between the output terminal and the common potential. Switch 33 and switch 34 are connected across inductor 24 and joined at node 36. Current sense resistor 38 is connected between node 36 and the common potential. Voltage divider resistors 40 and 42 are connected in series between the output terminal and the common potential.
Control circuit 44 has a first input connected to the junction between resistors 40 and 42, thereby to receive an output feedback voltage at resistor 42. The voltage at resistor 42 is proportional to the output voltage. A second input to control circuit 44 receives the voltage across resistor 38, which represents sensed inductor current. In response to these inputs, the control circuit 44 outputs signals for activation and deactivation of switches 22, 27, 33 and 34 for the various modes of operation. Switches 22 and 33 are controlled to be in reciprocal conductive states with respect to each other and switches 27 and 34 are controlled to be in reciprocal conductive states with respect to each other.
FIG. 2 is a block diagram of the control circuit 44 of FIG. 1. Buck logic circuit 46 outputs signals to switch drivers 48 and 49 that apply driving signals, respectively, to switches 22 and 33. Boost logic circuit 50 outputs signals to switch drivers 52 and 53 that apply driving signals, respectively, to switches 34 and 27. An output of buck comparator 54 is connected to an input of buck logic circuit 46 and an input of boost logic 50. An output of boost comparator 56 is connected to an input of buck logic circuit 46 and an input of boost logic 50.
Error amplifier 58 outputs a signal corresponding to the difference between the output feedback voltage, taken at the junction between resistors 40 and 42, and a reference voltage. This difference signal is applied as an input to buck comparator 54 and boost comparator 56. A buck compensation ramp signal and a boost compensation ramp signal are applied, respectively, to an input of the buck comparator 54 and the boost comparator 56. A compensation circuit 60 is shown connected to the error amplifier output. The compensation circuits may comprise a well-known resistive capacitive arrangement for this purpose, as described, for example, in an article entitled Modelling, Analysis and Compensation of the Current-Mode Converter, published in the 1997 edition of Applications Handbook. The compensation signal and difference signal are superimposed and compared by the comparators with the sensed current signal SNS+ SNS−, taken across current sense resistor 38 and applied as additional inputs to the comparators.
In buck mode operation, the output voltage is regulated to a preset level that is lower than the input voltage. To maintain the preset output voltage, current is applied by the regulator to the output capacitor COUT at a rate that is controlled in dependence upon sensed conditions. Buck logic circuit 46 outputs signals for turning on and off switches 22 and 33 in response to the output of buck comparator 54, while boost logic circuit 50 maintains switch 34 off. Boost comparator 56 is disabled at this time. Buck mode operation is implemented with clocked constant frequency switching control. During each cycle, the inductor is first connected between the common potential and the output terminal and thereafter connected between the input terminal and output terminal.
In boost mode operation, the output voltage is regulated to a preset level that is higher than the input voltage. Switch 22 is ideally maintained in an on state throughout the boost mode operation by buck logic circuit 46. Switch 33 is maintained in an off state throughout the boost mode operation. Buck comparator 54 is disabled throughout boost mode operation. Boost logic circuit 50 outputs signals for turning on and off switches 34 and 27 in response to the output of boost comparator 56. During each cycle, the inductor is first connected between the input terminal and common potential and thereafter connected between the input terminal and output terminal.
In each of the buck and boost operating modes, when inductor 24 is connected between the input and output terminals in each cycle, the current sense resistor 38 is disconnected from the inductor by switches 33 and 34 in their off states. During this time, there is no sensed inductor current signal input to the control circuit 44. If a short circuit condition at the output were to occur, abnormal current surges can result.
FIG. 3 is a waveform diagram that illustrates current surge when an output short circuit occurs during buck mode operation. Waveform IL represents current in inductor 24. Waveform VOUT, which depicts the voltage at the output terminal, indicates that an output short circuit condition occurs after the third clock pulse C3. Prior to the third clock pulse, normal controlled buck mode operation takes place. At the onset of clock pulses C1 and C2, inductor 24 is connected between the common potential and the output terminal via switches 33 and 27. Current is sensed by resistor 38. At times t1 and t2, inductor current has fallen to the valley threshold and control circuit 44 outputs signals to reconnect inductor 24 between the input terminal and the output terminal via switches 22 and 27 for the remainder of each clock cycle. As the valley threshold is reached relatively late in each cycle, the inductor is connected to the input terminal for a relatively small portion of the cycle.
Shortly after clock C3, at t3, a short circuit output condition occurs. As switches 33 and 27 are conductive at this time, very low voltage is applied across inductor 24. The charge stored in the inductor decreases at a significantly faster rate than during normal conditions. The valley threshold is reached early in the cycle, at t4. Control circuit 44 then outputs control signals to connect inductor 24 between the input and output terminals via switches 22 and 27. These switch states remain into the next clock pulse, C4. As switch 22 has been turned on much earlier in the cycle than normal, the inductor current has surged to a very high value.
FIG. 4 is a waveform diagram that illustrates current surge when an output short circuit occurs during boost mode operation. Waveform IL represents current in inductor 24. Waveform VOUT, which depicts the voltage at the output terminal, indicates that an output short circuit condition occurs after the third clock pulse C3. Prior to the third clock pulse, normal controlled boost mode operation takes place. At the onset of clock pulses C1 and C2, inductor 24 is connected between the input terminal and the common potential via switches 22 and 34. Current is sensed by resistor 38. At times t1 and t2, inductor current has risen to the peak threshold and control circuit 44 outputs signals to reconnect inductor 24 between the input terminal and the output terminal via switches 22 and 27 for the remainder of each clock cycle. As the voltage at the output is higher than the voltage at the input, current decreases. The peak threshold is reached relatively early in each cycle, the inductor current increasing for a relatively small portion of the cycle.
Shortly after clock C3, at t3, a short circuit output condition occurs. Switches 22 and 34 are conductive at this time and inductor current is sensed. At t4, the peak threshold is reached and control circuit 44 then outputs control signals to connect inductor 24 between the input and output terminals via switches 22 and 27. However, as a short circuit condition exists at the output and the voltage at the output now is much lower than the voltage at the input, current through inductor 24 continues to increase to a very high level. At clock C4, inductor 24 is reconnected between the input terminal and the common potential and current continues to increase.
A need thus exists for protection of the regulator in both constant frequency valley current buck mode operation and constant frequency peak current boost mode operation.
The possibility of a large inductor current spike when the regulator is operating in a low duty cycle buck mode is an additional concern. FIG. 5 is a waveform diagram that illustrates such problem when the control circuit does not respond during a cycle due, for example, to occurrence of a noise signal. Waveform IL represents current in inductor 24. Normal buck mode operation occurs during the first cycle, starting at C1. The current valley threshold is sensed at t1, and the inductor is connected between the input and output terminals for the remainder of the cycle. As the voltage at the output is significantly less than the voltage at the input, the time during which the inductor is connected to the input terminal is a small portion of the clock cycle (i.e., low duty cycle operation).
During the second cycle, beginning at clock C2, the control circuit has failed to reconnect the inductor between the input and output terminals and current continued to decrease for the whole cycle. In the cycle beginning at clock C3, the valley threshold is sensed early in the cycle at t2. Switches are then activated by the control circuit 44 to connect inductor 24 between the input and output terminals for the remainder of the cycle. Inductor current then increases without control to an abnormally high level.
The need thus exists for on-time limitation protection to prevent inductor current spike during a soft start or other fault conditions, such as soft short, in buck mode operation.
USPTO Backgrounds
USPTO Backgrounds