Communication between integrated circuit systems inevitably results in the generation of timing errors and voltage errors that occur in the inter-chip transmitted signals. The common source of such errors is inter-symbol interference (ISI), which is caused by limitations in the channel bandwidth. To accomplish high-speed inter-chip communication, the effect of ISI should be minimized.
Decision feedback equalizer (DFE) input buffers are employed in contemporary systems to mitigate the harmful effects of ISI. However, conventional DFE input buffers cannot efficiently compensate for timing and voltage errors caused by ISI, since the equalization coefficients in such buffers are fixed.
FIG. 1 is a waveform diagram illustrating the effects of timing errors and voltage errors caused by ISI. Waveforms A and B represent input signals as received by a receiver circuit. Signal B represents the normal input signal, that is, an input signal that is received without ISI error. Signal A represents an erroneous input signal that has experienced ISI. It can be seen that the erroneous input signal A experiences a timing error TE in the form of a timing delay, and a voltage error VE in the form of a reduced input voltage. Both the timing error TE and the voltage error VE are introduced as a result of ISI during the inter-circuit transfer of the signals.
FIG. 2 is a block diagram of a conventional DFE input buffer 11. In the conventional embodiment, an equalizer 10 amplifies the difference between an input signal IN including an ISI component, and an odd oversampled output signal OD multiplied by an equalizing coefficient α to compensate for the ISI component. As a result, an even amplified output signal ed is generated. In other words, the even amplified output signal ed=IN−(α*OD), where α*OD represents the ISI component, and the ISI component is thus reduced in the even amplified output signal ed.
At the same time, the equalizer 10 amplifies the sum between the input signal IN or INB (where “xB” represents throughout the present specification an inverted signal of signal “x”) including the ISI component, and an even oversampled output signal EDB or ED multiplied by the equalizing coefficient α to compensate for the ISI component. As a result, an odd amplified output signal od is generated. In other words, the odd amplified output signal od=IN−(α*ED), where α*ED represents the ISI component, and the ISI component is thus reduced in the odd amplified output signal od. The equalizer 10 thus includes a circuit that generates the even amplified output signals ed or edB and a circuit that generates the odd amplified output signals od or odB. An equalization circuit for generating the even output signals ed/edB is described below with reference to FIG. 3. An equalization circuit for generating the odd amplified output signals od/odB is similar in construct to the circuit of FIG. 3.
An oversampler 12 sequentially samples the even amplified output signal ed in response to each of sampling clock signals c0 and c90 and sequentially generates even oversampled output signals ED and ED90. Also, the oversampler 12 sequentially samples the odd amplified output signal od in response to each of sampling clock signals c90 and c180 and sequentially generates first and second odd oversampled output signals OD90 and OD.
Sampling clock signals c0 and c90 have a phase difference of 90 degrees. A phase detector 14 determines the phase difference between the even oversampled output signals ED and ED90 and determines the phase difference between the odd oversampled output signals OD and OD90, and, in response, activates an up control signal up or a down control signal dn, which, in turn, are transferred to a counter 16. The phase difference is representative of the phase relationship between the data clock of the received data and the sampling clock used by the oversampler 12 to sample the incoming data.
The counter 16 increases a count output signal cout, for example comprising a plurality of digital bits, when the up control signal up is active. The counter 16 decreases the count output signal cout, when the down control signal dn is active.
The timing controller 18 adjusts activation timing, or phase, of the sampling clock signals (c0, c90, c180, c270), in response to the count output signal cout. For example, if the value of the count output signal cout is increased to a value that is higher than a previous value, for example 00 . . . 01→00 . . . 10, the activation timing of each of the sampling clock signals (c0, c90, c180, c270) is adjusted such that it is activated at a later time than before. However, if the value of the count output signal cout is decreased to a lower value, the activation timing of each of the sampling clock signals (c0, c90, c180, c270) is adjusted such that it is activated at an earlier time than before. In this manner, the activation timing of the sampling clock signals (c0, c90, c180, c270) is adjusted by the timing controller 18 in order to compensate for a centering error that may exist between the input signal IN and the sampling clock signals (c0, c90, 180, c270) in the oversampler 12.
A clock generator 20 generates several reference clock signals (c1, c2, cn) in response to an input clock signal CLK. The reference clock signals (c1, c2, cn) have respectively different phases, from which the sampling clock signals (c0, c90, c180, c270) are generated.
FIG. 3 is a schematic diagram of the equalizer 10 component of the conventional DFE input buffer of FIG. 2. In the equalizer 10, the value of the received input signal IN is amplified to compensate for voltage error in the input signal IN. To accomplish this, a conventional equalizer has a fixed equalizing coefficient α having a value that is predetermined. In the equalizer circuit of FIG. 3, load transistors P1 and P2 operate as a load resistance and could be replaced by resistors. Differential transistors N1 and N2 receive the IN and INB signals respectively. Differential transistors N3 and N4 receive the ODB and OD signals respectively. Current source transistors N5 and N6 draw the respective currents I1 and I2 flowing through the first and second differential units. The value of the fixed equalizing coefficient α is determined as a function of the relative sizes of the channel widths of transistors N5 and N6, which are fixed. In the circuit, voltage value Vb represents a bias voltage that is constant in value. Since the value of the equalizing coefficient α is fixed, the equalizer circuit 10 operates in a constant condition, irrespective of whether timing error TE or voltage error VE exists in the input signal IN. For this reason, the conventional equalizer circuit is incapable of accurately compensating for timing errors or voltage errors in the input signal over a range of operating conditions.
USPTO Backgrounds
USPTO Backgrounds