1. Field of the Invention
The present invention relates to a pipelined analog-to-digital converter, and especially focuses on calibration for the pipelined analog-to-digital converter.
2. Description of Related Art
High-speed analog-to-digital converters (ADCs) are widely used in wire and wireless data communications, disk drive, instrumentation and imaging. There are quite a few architectures which could be used to implement high-speed ADCs. Pipelined architectures for ADCs are known to use less power than the other architectures for ADCs, but at the expense of conversion latency. In pipelined ADCs, power consumption can be optimized by an appreciate selection of bits per stage capacitor scaling down the pipelined ADCs. Also, pipelined ADCs are successfully implemented in CMOS technology using switched capacitor technique, which makes them easy to integrate.
FIG. 1 shows a block diagram of a conventional pipelined ADC. The pipelined ADC 100 includes k low-resolution stages (or to be known as sub ADC) 110, delay elements 120 synchronizing the stage outputs, and digital corrections 130. Each stage 110 has a resolution of Bi+ri bits, of which Bi represents the effective stage resolution and ri represents the redundancy for a comparator offset correction algorithm. Each stage 110 digitizes the residue of the previous stage 110, so accordingly, the digital output B1 of the first stage 110 contains the most significant bits while the output Bk of the last stage 110 contains the least significant bits. The stages 110 operate concurrently; that is, at any time, the first stage 110 operates on the most recent sample while all other stages 110 operate on residues from previous samples.
In order to provide a stable DC input for high-speed sampling rate, traditionally, most converters, including pipelined ADCs, make use of a dedicated front-end sample and hold amplifier (SHA) circuit. Unfortunately, the dedicated front-end SHA circuit consumes half of the total power consumption as well as occupies a large amount of die area. However, if the dedicated front-end SHA circuit is removed, the input voltage sampled by different stage 110 will be differently, this difference is called aperture error. Various ways have been proposed to remove or reduce aperture error.
USPTO Backgrounds
USPTO Backgrounds