Recently the semiconductor device having the semiconductor chip mounted thereon has shown the tendency to have a thin structure. Patent documents such as Japanese Patent No. 3598060 and Japanese Unexamined Patent Application Publication No. 2005-101580 disclose a module with a built-in semiconductor device having a wiring on at least one surface of an insulator substrate as a related art example 1. Referring to FIG. 1 as a sectional view of the semiconductor device according to the related art example 1, a first semiconductor chip 16 is mounted onto a first wiring layer 14 using a die adhesive material 15. The first semiconductor chip 16 is electrically coupled with the first wiring layer 14 via a bonding wire 18. The first semiconductor chip 16 and the bonding wire 18 are sealed with a resin portion 35. The resin portion 35 is embedded in a resin portion 32 so as to be integrated therewith. The resin portion 32 is provided with the first wiring layer 14 and a second wiring layer 24 at opposite surfaces, respectively. A through electrode 34 pierces the resin portion 32 to connect the first and the second wiring layers 14 and 24.
In the related art example 1, as the resin portion 35 for sealing the first semiconductor chip 16 is embedded in the resin portion 32, it is difficult to reduce the thickness of the resin portion 32. As the first and the second wiring layers 14 and 24 are exposed, a short-circuit is likely to occur between those wiring layers. The insulator films may be applied to the surfaces of both the first and the second wiring layers 14 and 24 for suppressing the aforementioned short-circuit. However, this results in an increase in the thickness of the semiconductor device.
USPTO Backgrounds
USPTO Backgrounds