The invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a circuit for a true and complement signal generator. More specifically, it relates to a circuit for a true and complement signal generator using an AND logic circuit using three MOSFET transistors.
High performance arithmetic operations have been widely implemented using pass-transistor based circuits known for low power usage and high performance. One type of pass-transistor based circuit employs only NMOS transistors. However, NMOS transistors suffer from signal degradation due to a threshold voltage drop across the source and drain of the transistor when passing a HIGH signal.
In a CMOS silicon-on-insulator (SOI) implementation, threshold voltage drop is minimized and performance is maximized due to the absence of a reverse body effect. Not only is the SOI implementation of an NMOS transistor body rarely reverse-biased, it tends to be forward-biased with respect to the source. Fluctuating biasing conditions and switching patterns cause a fluctuation in the forward bias of the body-to-source junction of the NMOS transistor, causing large variations in hysteretic delay.
To overcome the drawbacks associated with NMOS only pass-transistor circuits of both bulk CMOS and SOI CMOS implementations, transmission gates using both NMOS and PMOS transistors are used. VLSI circuits formed of NAND, NOR and INVERTER basic building block circuits using transmission gates are implemented using static or dynamic CMOS. Static CMOS circuits are generally more widely used due to their superior rail-to-rail voltage swing, robust behavior and high noise immunity.
However, static CMOS circuits require one NMOS and one PMOS transistor for every input signal. Furthermore, static CMOS gates are inverting by nature. This results in a large count of transistors for each basic circuit, large delays and high power consumption, as will be described with reference to FIGS. 1A and 1B.
FIG. 1A shows a logic representation of a two input AND operation 10. The truth table for the two input AND operation 10 is shown in FIG. 3B. In static CMOS logic, the two input AND operation 10 is implemented using a two input NAND gate 12 and a first inverter gate 14. The output C of the NAND gate 12 is A NAND B. The first inverter gate 14 outputs NOT C which is equal to A AND B. FIG. 1B shows the static CMOS logic circuit 20 for the two input AND operation 10 implementing a conventional NAND circuit 21 and a conventional inverter circuit 23. The static CMOS logic circuit 20 requires six transistors including three NMOS transistors 22, 24, 26 and three PMOS transistors 28, 30, 32. A typical delay associated with circuit 20 is 41 ps.
The basic logic AND circuit 20 are used as building blocks in applications such as a prior art True and Complement Signal Generator. With reference to FIG. 2A, a typical prior art logic representation 200 of a True and Complement Signal Generator is shown. The inputs to the True and Complement Signal Generator are a CLK signal and signal A, and the outputs are a true signal T and a complement signal C. A NAND gate 12 and an inverter gate 14 are provided together to perform an AND operation for producing each of the output signals T and C. Additional inverter gates 114 are provided for buffering the input signals CLK and A. The logic equations for the T and C signals are as follows:
T=xcx9cAxc2x7xcx9cCLKxe2x80x83xe2x80x83(1)
C=Axc2x7xcx9cCLKxe2x80x83xe2x80x83(2)
With reference to FIG. 2B, a transistor representation of a typical prior art True And Complement Signal Generator circuit 220 is shown. A logic AND circuit 20, including a conventional NAND circuit 21 and a conventional inverter circuit 23, is provided for implementing each of the AND logic operations for producing the output signals T and C. Several conventional inverter circuits 23 are provided for implementing the inverting functions shown in FIG. 2A. The total number of transistors in the circuit 220 is 22 including 11 NMOS transistors and 11 PMOS transistors. The CLK signal input passes through a series of two inverter gate circuits 23 and one NAND gate circuit 21 for generating each of the T and C signals. The A signal input passes through a series of four inverter gate circuits 23 and one NAND gate circuit 21 for generating signal T, and a series of five inverter gate circuits 23 and one NAND gate circuit 21 for generating signal C. A delay is generated as the input signals pass through each of the inverter gate circuits 23 and the NAND gate circuits 21.
An aspect of the present invention is to provide a basic logic circuits for the AND logic operation in which the number of transistors for the circuit is reduced for minimizing the size, power consumption and associated delays of the circuit, thereby maximizing efficiency.
It is another aspect of the present invention to provide a basic logic circuit for the AND logic operation in which the number of transistors that a signal passes through in series is minimized for minimizing associated delays.
Finally, it is an aspect of the present invention to provide a True And Complement Signal Generator circuit implementing the basic AND logic circuit having a reduced number of transistors and reduced associated delays for minimizing the size, power consumption and associated delays of the True And Complement Signal Generator circuit.
Accordingly, in one embodiment of the present invention, a MOSFET logic circuit having three transistors is presented for performing a logic AND operation, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of the at least two input signals is output form the circuit.
In another embodiment of the present invention, a MOSFET true and complement signal generating logic circuit is presented for receiving first and second input signals and outputting a true signal and a complement signal indicative of the first input signal to the true and complement signal generating logic circuit, the true and complement signal generator circuit including at least one MOSFET inverter logic circuit, and first and second AND logic circuits, wherein each of the first and second AND logic circuits includes three transistors.
USPTO Backgrounds
USPTO Backgrounds