1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits which use power gating so as to reduce power consumption of the integrated circuit.
2. Description of the Prior Art
Power gating is a known and effective technique for mitigating leakage power over long idle periods in integrated circuit designs. Functional state may be restored through a reset or otherwise after power up. A disadvantage that limits the usefulness of such power gating is that powering up after the power gating can have a large energy cost. There are a number of reasons for this large energy cost including the large power grid capacitance that must be slowly recharged, gated logic suffering crowbar currents until the virtual rail voltages reach approximately the transistor threshold voltages, and that logic values will be re-evaluated on power up drawing more dynamic power than after a functional mode clock event as switching activity is normally reduced by design during functional mode clocking.
USPTO Backgrounds
USPTO Backgrounds