1. Field of the Invention
The invention relates to a method and apparatus for controlling a dual-slope integrator circuit, more particularly to a method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect.
2. Description of the Related Art
Conventional dual-slope integrators are widely used in linear systems, such as analog-to-digital conversion, time interval measurement, etc. Referring to FIG. 1, a conventional dual-slope integrator 1 is shown to include an operational amplifier 10. As shown in FIG. 2, in operation, the dual-slope integrator 1 generally requires a settling time (TS) before reaching a linear operating region (TL) during which a stable output can be obtained from the operational amplifier 10. As such, as shown in FIG. 3, in a time interval measuring device 11, a control circuit 12 is used in controlling the dual-slope integrator 1 to eliminate the settling time effect. In this configuration, a digital clock signal and an analog input test signal must be inputted to the control circuit 12 for synchronization. However, the high-frequency digital clock signal can interfere with the analog input test signal and cannot be easily synchronized with the latter. In U.S. Pat. No. 6,137,749, there is disclosed a control circuit constructed from a finite state machine so as to solve the aforesaid synchronization problem between the digital clock signal and the analog input test signal. However, the control circuit proposed in the aforesaid patent is not only large and complicated, but also does not address the problems associated with the settling time of the dual-slope integrator and interference between the digital clock signal and the analog input test signal.
USPTO Backgrounds
USPTO Backgrounds