1. Field of the Invention
This invention relates to microprocessors employing register files and, more particularly, to arbitration of register file ports.
2. Description of the Related Art
In the course of executing a software program on a conventional microprocessor, instructions and data are retrieved from a system memory to be used in the execution of individual microprocessor instructions or operations. However, system memory bandwidth is generally insufficient to directly provide instructions and data to a microprocessor at the rate at which it can consume them. To improve execution performance, modern microprocessors integrate a register file into the microprocessor core. Register files typically provide a plurality of addressable locations that can be quickly decoded by the microprocessor's control logic; such locations serve as rapidly accessible storage from which to retrieve operands for the execution of operations and to which to store operation results. Register files provide operands to functional units by accessing specific locations through a plurality of read ports. Results are written to specific locations through a plurality of write ports. Typically, any given register file location can be read from any given read port and written by any given write port.
To further improve microprocessor performance, the number of operations that can be performed simultaneously may be increased by including a plurality of functional units that may execute operations in parallel. Such superscalar microprocessors may include multiple integer and floating point functional units including, for example, arithmetic logic units, address generation units, branch processing units, multipliers and dividers.
Increasing the number of functional units in a microprocessor implementation directly increases the number of operations that can be simultaneously performed. However, realizing maximum functional unit utilization requires the register file to provide sufficient read and write ports to simultaneously provide each functional unit with operands and to store execution results.
Accordingly, as the number of functional units in a microprocessor implementation increases, the number of register file read and write ports that supply operands may necessarily increase. However, increasing the number of read and write ports greatly increases the complexity of designing and implementing the register file. Each additional read or write port requires additional control logic to decode and select which location to access via that port. Further, each such additional port requires a separate wire bus connected to each register file location, if access symmetry (i.e., any location being readable or writeable by any port) is to be maintained. Depending on the manufacturing process used to manufacture the microprocessor, additional wiring may require a larger physical register file layout, resulting in slower register file performance due to electrical factors such as increased capacitive loading and signal transit time.
The performance costs of adding read or write ports may ultimately outweigh the performance benefits of increasing parallelism through adding functional units. Not providing sufficient read and write ports to simultaneously supply all functional units also limits performance. Thus, it may be desirable to have a processor design including an optimized number of register file read and write ports in a given implementation.
USPTO Backgrounds
USPTO Backgrounds