Strained Si has been adopted as a promising option to improve complementary metal oxide semiconductor (CMOS)-based transistor device performance. For example, strained silicon on insulator (SSOI) technology is a promising way to increase electron mobility in CMOS technologies such as, for example, FinFET, trigate, ultrathin body SOI and nanowires. However, current methods to fabricate SSOI wafers are very expensive. For example, the most common approach is to grow a strained Si layer on a relaxed SiGe buffer layer, which is grown epitaxially on a “donor” Si substrate and then transfer the strained Si layer to a handle wafer by a bonding, smartcut, and etch back process. However, since the SiGe buffer layer needs to be very thick this method is very expensive.
More specifically, Si is deposited on a layer of relaxed SiGe to produce a Si layer that is under tensile strain. Strained Si on SiGe has also been used in conjunction with silicon-on-insulator (SOI) to combine the benefits of both technologies. The intervening SiGe layer, however, causes complications in processes such as, for example, enhanced N-type dopant diffusion, Si/SiGe intermixing, shallow trench isolation (STI) process complications, and possible negative effects on silicide formation.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.
USPTO Backgrounds
USPTO Backgrounds