1. Field of the Invention
The present invention relates to a switch control circuit, a ΔΣ modulation circuit, and a ΔΣ modulation analog to digital (AD) converter.
2. Description of the Related Art
An AD converter using a ΔΣ modulation circuit (see, e.g., Japanese Patent Application Laid-Open Publication No. 2002-141802) is known as an AD converter used in audio equipments, etc. The ΔΣ modulation circuit used in such a AD converter is realized by an integrator that integrates and outputs an input analog signal, a quantizer that outputs a digital signal converted from the integrated analog signal, etc.
The integrator can be constituted by combining a switched capacitor and an operational amplifier. FIG. 9 shows a configuration example of an integrator using a switched capacitor and an operational amplifier. An integrator 100 includes an operational amplifier 110, an integration capacitor 111, and a switched capacitor including switches SW11 to SW14 and a capacitor 112.
One electrode of the integration capacitor 111 is electrically connected to an output terminal of the operational amplifier 110 and the other electrode is electrically connected to an inverting input terminal of the operational amplifier 110. An intermediate voltage Vdd/2 is applied to a noninverting input terminal of the operational amplifier 110. The switched capacitor including the switches SW11 to SW14 and the capacitor 112 is electrically connected to an inverting input terminal of the operational amplifier 110.
While the switches SW12, SW13 are turned on and the switches SW11, SW14 are turned off in such an integrator 100, the capacitor 112 accumulates electric charge corresponding to a difference between an input voltage Vin and the intermediate voltage Vdd/2 (a sampling process). When the switches SW12, SW13 are turned off and the switches SW11, SW14 are turned on, the electric charge accumulated in the capacitor 112 flows into the integration capacitor 111 and the capacitor 111 accumulates the electric charge (an integration process). When the sampling process and the integration process are performed repeatedly, the output voltage Vout of the operation amplifier 110 is a voltage acquired by integrating the input voltage Vin.
By the way, since the ΔΣ modulation circuit must perform the sampling process and the integration process highly accurately to increase resolution, the on/off timing of the switches SW12, SW13 may be shifted or the on/off timing of the switches SW12, SW14 may be shifted (see, e.g., Japanese Patent Application Laid-Open Publication No. 1990-84255). FIG. 10 shows a typical configuration example of a switch control circuit that generates a four-phase clock controlling the on/off of switches SW11 to SW14. A switch control circuit 120 includes NOR circuits 130 to 132 and inverter circuits 133 to 138.
To the NOR circuit 130, a standby signal STB is input through the inverter circuit 133 and a main clock CLK is input. The standby signal is H-level at the time of operation. Therefore, at the time of operation, the NOR circuit 130 outputs a signal that is the inverted main clock CLK.
The signal output from the NOR circuit 130 is input to the NOR circuit 131 and is input to the NOR circuit 132 through the inverter circuit 134. An even number of the inverter circuits 135 is disposed at a subsequent stage of the NOR circuit 132, and the output thereof is a clock signal CK1 controlling the on/off of the switch SW11. An even number of the inverter circuits 136 is disposed at a subsequent stage thereof, and the output thereof is a clock signal CK4 controlling the on/off of the switch SW14. The output of the inverter circuit 136 is input to the NOR circuit 131.
Similarly, the inverter circuits 137 of the same number as the inverter circuits 135 are disposed at a subsequent stage of the NOR circuit 131, and the output thereof is a clock signal CK2 controlling the on/off of the switch SW12. The inverter circuits 138 of the same number as the inverter circuits 136 are disposed at a subsequent stage thereof, and the output thereof is a clock signal CK3 controlling the on/off of the switch SW13. The output of the inverter circuit 138 is input to the NOR circuit 132.
In this example, when the clock signals CK1 to CK4 are H-level, the switches SW11 to SW14 are turned on, respectively.
FIG. 11 is a timing chart of the operation of the switch control circuit 120. It is assumed that the main clock CLK is changed from L-level to H-level at time t1. One input of the NOR circuit 131 becomes L-level and One input of the NOR circuit 132 becomes H-level. Therefore, the output of the NOR circuit 132 becomes L-level; the clock signal CK1 becomes L-level at time t2; and the clock signal CK4 becomes L-level at time t3. When clock signal CK4 becomes L-level, the output of the NOR circuit 131 becomes H-level; the clock signal CK2 becomes H-level at time t4; the clock signal CK3 becomes H-level at time t5.
It is assumed that the main clock changes from H-level to L-level at time t6. One input of the NOR circuit 131 becomes H-level and One input of the NOR circuit 132 becomes L-level. Therefore, the output of the NOR circuit 131 becomes L-level; the clock signal CK2 becomes L-level at time t7; and the clock signal CK3 becomes L-level at time t8. When clock signal CK3 becomes L-level, the output of the NOR circuit 132 becomes H-level; the clock signal CK1 becomes H-level at time t9; the clock signal CK4 becomes H-level at time t10.
In this way, the highly accurate sampling process and integration process are performed by turning on/off the switches SW11 to SW14 with the four-phase clock signals generated by the switch control circuit 120.
As described above, when the switches SW12, SW13 are turned on and the switches SW11, SW14 are turned off, the capacitor 112 accumulates electric charge, and when the switches SW12, SW13 are turned off and the switches SW11, SW14 are turned on, the electric charge flows into the capacitor 111. Since the noninverting input terminal and inverting input terminal of the operational amplifier 110 are imaginary-shorted, the voltage of the inverting input terminal becomes equal to the intermediate voltage Vdd/2 applied to the noninverting input terminal in theory. Therefore, the whole electric charge accumulated in the capacitor 112 flows into the capacitor 111 when the switches SW12, SW13 are turned off and the switches SW11, SW14 are turned on.
However, actually, since the operational amplifier 110 has an offset, the voltage of the inverting input terminal becomes a voltage higher or lower than the intermediate voltage Vdd/2 applied to the noninverting input terminal by the offset α. Therefore, if the switches SW11, SW14 are turned on, in the electric charge accumulated in the capacitor 12, electric charge corresponding to the offset α does not flow into the capacitor 111 and stays in the capacitor 112.
If the electric charge stays in the capacitor 112, the accuracy of the integration of the input voltage Vin is reduced in the integrator 100. When such a integrator 100 is used, the modulation accuracy of the ΔΣ modulation circuit is reduced and a distortion rate is deteriorated in the ΔΣ modulation AD converter.
FIG. 12 shows theoretical distortion rate characteristics corresponding to amplitude of an analog signal (the input signal Vin) input to the ΔΣ modulation AD converter. The distortion rate (THD+N) has a lower value in the upper portion of FIG. 12. As shown in FIG. 12, in theory, the distortion rate is minimized at amplitude (−1 to −3 dBFS) slightly lower than the full scale (0 dBFS), which is the maximum amplitude that can input.
FIG. 13 shows actual distortion rate characteristics corresponding to amplitude of the analog signal input to the ΔΣ modulation AD converter. As shown in FIG. 13, when the distortion rate is minimized in the actual distortion rate characteristics, the input amplitude is lower than the theoretical amplitude and the distortion rate has a value higher than the theoretical distortion value. That is, since the electric charge stays in the capacitor 112 constituting the integrator used in the ΔΣ modulation AD converter, the distortion rate is deteriorated as shown in FIG. 13.
USPTO Backgrounds
USPTO Backgrounds