Exemplary embodiments relate generally to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device including conductive patterns and a method of manufacturing the same.
To highly integrate semiconductor devices, the line widths in a pattern and the spacing widths between patterns are reduced in order to form more patterns in a limited area. The photolithography process has many limitations in forming patterns due to its limited resolution for further reducing the line widths of a pattern and the spacing widths between patterns.
In order to form fine patterns with a fine width greater than the resolution limit of the photolithography process, double patterning technology is used where the fine patterns are formed by overlapping the patterns, and where spacer patterning technology is used for forming the fine patterns.
A semiconductor device includes a plurality of metal lines and a plurality of contact pads coupled to the metal lines. Accordingly, there is a need for a layout scheme for efficiently arranging the plurality of metal lines and the plurality of contact pads in a narrow area.
USPTO Backgrounds
USPTO Backgrounds