Conventional comparators generally determine which of two inputs is the greater or the lesser of the two. An example of such a comparator is a sense amplifier typically used in applications such as dynamic random access memory (DRAM) cells. FIG. 1 shows a schematic diagram of a conventional sense amplifier 10 implemented using metal-oxide-semiconductor (MOS) field effect transistors. When the clock signal CK applied to sense amplifier 10 is at a logic low level, transistors MP1 and MN1 are off while transistor MPA is enabled. This equalizes the voltages at nodes A and B. At this time, a voltage difference can be introduced between A and B, since the resistance of MPA is very high. For example, the voltage at node A can be set higher than the voltage at node B by appropriate application of signal voltages to corresponding inputs IN.sub.A and IN.sub.B, respectively. The clock signal CK is then permitted to go to a logic high level, such that transistors MP1 and MN1 are turned on, and transistor MPA is turned off. This activates the random access memory (RAM) cell made up of transistors MP2, MP3, MN2 and MN3. Since the voltage at node A was set to be higher than the voltage at node B, positive feedback through the cell transistors will cause node A to approach the supply voltage V.sub.DD, while node B will approach the supply voltage V.sub.ss, which may be ground potential. As a result, the initial difference established between the voltages at nodes A and B, which may have been on the order of several millivolts, can be amplified significantly.
Unfortunately, using conventional two-input comparators configured as shown in FIG. 1 to determine, for example, which of three inputs is greater or lesser than the others, generally requires comparisons of each pair of inputs and then further comparisons of the previous comparison results. Multi-input comparators configured in this manner can also exhibit excessive computation time and signal delay, in that each stage of comparison generally requires a separate cycle of the clock signal. Furthermore, such arrangements can require an unduly large amount of circuit area, and consume an excessive amount of power. A need therefore exists for an improved multi-input comparator which is more computationally efficient, requires less circuit area, and consumes less power than conventional multi-input comparators.
USPTO Backgrounds
USPTO Backgrounds