1. Field of the Invention
This invention relates to a data interface that receives a plurality of data signals from a parallel bus, and accurately samples each and every one of the data signals having dissimilar transition times between transitions of a clock signal. As such, the data interface is adapted to adjust a timing relationship between a clock signal and the plurality of data signals with a relative amount of phase delay imparted to the clock signal. The data interface may be included within a synchronous device or, more particularly, within a communications system or network to receive and/or transmit the plurality of data signals over a parallel data bus.
2. Description of the Related Art
The following descriptions and examples are given as background only.
A synchronous device is a device in which data may be transferred from one edge-sensitive element to another in response to an active transition of a clock signal. Similarly, a synchronous system may be defined as a system in which data is transferred from one synchronous device (e.g., a transmitter) to another synchronous device (e.g., a receiver) in response to a clock transition. In some cases, data may be transferred in a single direction from transmitter to receiver over an internal or external bus. In other cases, however, data transfer may be bi-directional. In such a case, a first synchronous device may be referred to as a host, while a second synchronous device may be referred to as a transceiver. In any case, the clock signal may be transferred along with the data signal from transmitting to receiving portions of the synchronous system.
In order to successfully implement a synchronous system, it is beneficial to properly align the clock signal to the data being sampled at the input latches of the receiving portion of the system. Such alignment often entails ensuring the data transition occurs at the proper moment between the edges or active transitions of the clock signal. Synchronous systems, therefore, rely on data transitioning and remaining stable from a time at least a “setup time” before a clock transition until at least a “hold time” after the clock transition. For example, FIG. 1 illustrates a data signal that is stable for a setup time, tsu, before the active edge of the clock signal. In addition, FIG. 1 illustrates the data signal remaining stable for a hold time, th, after the active edge of the clock signal. In some cases, circuit elements of the receiving portion may be coupled to receive the data signal after it is sampled at the clock transition. These circuit elements may rely on the sampled data transitioning at least an amount of time, ta+, after a clock transition as illustrated in FIG. 2. Such an amount of time may represent the length of time in which circuit elements of the receiving portion wait to receive the sampled data signal after receiving the sample clock transition. In some cases, the amount of time is comparable to the propagation delay through output latches of the data interface within the receiving portion. Thus, the amount of time, ta+, maybe generally referred to as “clock to output Q time” or positive “access time.”
Most synchronous systems have stringent setup, hold, and access timing requirements, which are typically specified by a manufacturer of the system. In addition, the margin of time in which a clock transition can sample a data signal between data setup and hold times generally decreases as the clock transition frequency increases (i.e., as operation speed increases). As such, high-speed synchronous systems usually cannot afford significant skewing of the clock signal relative to data signal transitions. In general, clock skew may be described as a variation in the arrival times between two signals, which are specified to occur at the same time. Because clock signals are used to drive many of the components within synchronous systems, any variation in the arrival of a clock transition may significantly impact system performance and/or reliability.
In some cases, clock skew significantly affects the timing margins of synchronous systems, such as setup, hold, and access time margins, by decreasing the predictability of the arrival of a clock transition. For example, edge-sensitive flip-flops may be used to sample incoming data signals. In such an example, a flip-flop may successfully latch a data signal if the data signal is stable during critical setup and hold periods on either side of the clock transition. In some cases, however, clock skew may shift the clock transition sufficiently in time to cause a bit error to occur when the data is sampled. A bit error, as described herein, is a sampling error that occurs when a clock transition incorrectly samples a data signal. In other words, a logic value of a data signal output from a latch may not equal a logic value of the data signal input to the latch.
In addition, clock skew may reduce the cycle time within which information can be passed from one device to the next. As system speeds increase, clock skew may become an increasingly large portion of the total cycle time. When cycle times were 50 ns, for example, clock skew could occupy as much as 20% of the cycle time without degrading system performance. In high-speed systems having cycle times approaching 15 ns or less, however, only 10% of the timing budget may be allocated to clock skew. If clock skew exceeds such an allocated amount, the system will most likely perform unreliably.
Although numerous techniques are used in an effort to minimize clock skew, most techniques cannot in all conditions ensure a data signal transition occurs at the critical moment between clock signal edges. In some cases, an external component may be added to the clock path in an effort to minimize clock skew. In such a case, the external component may add a fixed amount of time delay to the clock path in an attempt to align the clock transition within the data timing margins of the receiving synchronous device.
FIG. 3 illustrates external component 5, which may include, for example, one or more buffers, a programmable logic device (PLD), or an application specific integrated circuit (ASIC). In one example, a matrix of buffers may include a plurality of parallel lines, each of which include a different number of buffers. In this manner, each of the plurality of parallel lines is adapted to impart a different amount of delay at its output. As such, the matrix of buffers may be used (in conjunction with a line selecting device, such as a multiplexer) to add a slightly variable amount of delay to the clock path. The selection of delay amounts, however, is undesirably fixed by the circuit design and cannot be changed by the user. In another example, a programmable logic device (PLD) generally includes combinational and/or sequential logic, which can be defined by the user and programmed into the device. As such, a PLD may be programmed to provide a variable amount of delay to the clock path. A PLD, however, generally exhibits low operating speeds, such as operating speeds of 150 MHz or below. As such, a PLD may not be fast enough to accommodate high-speed synchronous systems having operating speeds substantially greater than 150 MHz. An application specific integrated circuit (ASIC), on the other hand, may provide a variable amount of delay to the clock path at possibly higher operating speeds than a PLD. ASICs, however, are typically very expensive and their performance is often highly sensitive to any impedance mismatches at the inputs and outputs of the device. In addition, adding any external component tends to undesirably increase the financial cost, power, and area consumed by the synchronous system.
Alternatively, FIG. 4 illustrates an internal data interface 10, which may be included within a synchronous system. Internal data interface 10 may use a phase-locked loop (PLL) or delay-locked loop (DLL) device to add a substantially consistent amount of delay to the clock path. Generally, a PLL is a closed-loop device that uses a voltage-controlled oscillator (VCO) to obtain accurate phase and frequency alignment between a feedback clock signal and a reference clock signal. A DLL device, on the other hand, differs from a PLL device in that it generally uses a delay line instead of a VCO to obtain accurate phase alignment between the feedback clock signal and the reference clock signal.
In some cases, a PLL or DLL device (reference numeral 12) may be used to add a substantially consistent amount of delay to the clock path, which adjusts the active edge of the clock signal before clocking input latch 14 of data interface 10. As such, PLL/DLL device 12 may be used to reduce clock skew by adjusting the timing of the clock signal to occur within the data setup and hold time requirements of a transmitting portion of the synchronous system. Buffer device 16 may be included within the clock path to account for the propagation delay added to the data path by latch 14. In addition, another PLL or DLL device (reference numeral 22) may be used to add another amount of delay to the clock path, which adjusts the active edge of the clock signal after clocking output latch 20 of data interface 10. In this manner, PLL/DLL device 22 may be used to reduce clock skew by adjusting the timing of the clock signal to occur after at least a data access time requirement of a receiving portion of the synchronous system. Similar to buffer device 16, buffer device 18 may be included within the clock path to account for propagation delays, which may be added to the data path by circuit elements arranged between input latch 14 and output latch 20.
One disadvantage of internal data interface 10, however, is that the amount of delay imparted to the clock path is undesirably fixed by the circuit design. As stated above, the margin of time in which a clock transition can sample a data transition between data setup and hold times decreases proportionally as the frequency of the clock transition increases. In this manner, a fixed delay may fall further outside of such a timing margin as the frequency of the clock transition increases. Thus, a delay error tolerance of data interface 10 may decrease as operating speeds increase.
In addition, though internal data interface 10 provides a substantially consistent amount of clock path delay, it does not guarantee that the timing along the data path is correct. In a synchronous system, for example, which utilizes a parallel data bus (i.e., a plurality of parallel data paths) to transfer data between transmitting and receiving portions, interference between individual paths of the parallel data bus may introduce an unpredictable amount of delay to one or more of the individual paths. As such, even though internal data interface 10 may reduce the affects of clock skew, interference within the parallel data bus may skew the data signals separate from one another thereby causing one or more of the data signals to be sampled incorrectly.
Therefore, it would be beneficial to provide an improved data interface for a synchronous system. Such an improved data interface would preferably reduce the affects of data path interference in addition to reducing the affects of clock skew. Furthermore, the improved data interface would operate at high or low operating speeds without compromising data integrity. Moreover, the improved data interface would consume substantially less power and area, and cost less than conventional solutions.
USPTO Backgrounds
USPTO Backgrounds