The power consumption of modern electronic equipment has become a critical issue due to the increased popularity of mobile products and the focus on miniaturization. For example, cellular phones are fast becoming a necessity for the everyday consumer, with the size and battery life of such phones being major issues in the purchasing decision. These modern hardware devices contain a significant amount of CMOS semiconductor circuitry. Power consumption in a CMOS circuit is most commonly attributed to at least the following factors: (1) short circuits; (2) leakage; (3) functional switching; and/or (4) hazard pulses. As is well known, power dissipation due to short circuits is often negligible and power consumption due to leakage is significantly smaller than that of functional switching or hazard pulses. Thus, the major contributors in CMOS circuit power dissipation are functional switching and hazard pulses. In particular, it has been reported that hazard pulses consume approximately 20-40% of the total power in digital circuits (see, for example, A. Bellaouar et al., Low-Power Digital VLSI Design: Circuits and Systems, Kluwer Academic Publishers, p. 493, Boston, 1995.)
Hazard pulses occur due to the fact that before signals of a digital circuit reach their steady state, the transistor gates making up the circuit incur multiple signal transitions as a function of signals arriving at the gate by paths of varying delays. These transitions generate the hazard pulses in a gate. These extra transitions and the generated hazard pulses of the gates increase the power dissipation of the digital circuit. One known technique for eliminating hazard pulses is to balance the delays of multipath signals serving as input to a gate. The balancing is accomplished either by using a tree-like logic structure or by inserting delay buffers within particular "fast" paths of the circuit (see, Ballaouar, supra.). However, the balancing technique is sensitive to delay tolerances and may, in some cases, actually incur additional power dissipation due to the use of additional delay buffering.
Another known technique for addressing hazard pulses is so called retiming. Retiming employs a flip-flop repositioning scheme within a circuit such that particular flip-flops are moved to circuit nodes having high hazard occurrences. However, one drawback of this approach is that in many instances the number of nodes having potential hazard pulses is much larger than the number of flip-flops available for repositioning (see, for example, J. M. Rabaey et al., Low Power Design Methodologies, Kluwer Academic Publishers, pp. 148-149, Boston, 1996.) In addition to the retiming technique there is known the so called self-timing technique in which a combinational element of a circuit will not compute a result until all inputs have stabilized. This technique, however, requires the addition of other circuitry to the overall circuit design thereby increasing the complexity of the circuit.
Finally, in S. H. Unger, Asynchronous Sequential Switching Circuits, Wiley-Interscience, pp. 153-163, New York, 1969, a technique for adding inertial delays to the output of a combinational logic circuit is described which eliminates hazard pulses in asynchronous circuits. Significantly, however, this approach may leave hazard pulses on many internal signals of the asynchronous circuit and does not address the issue of power dissipation within the circuit.
Therefore, a need exists for a hazard pulse suppression technique which does not require additional circuitry, effectively handles a potentially large number of hazard pulses within digital circuits, and which contributes to an overall reduction in power dissipation of a circuit.
USPTO Backgrounds
USPTO Backgrounds