The invention relates to reducing timing variance of signals from an electronic device.
Electronic devices generate signal outputs that are typically triggered off a triggering event, e.g., an edge of a clock. Several factors can affect the time delay between the triggering event and the generation of the desired output. Such factors include temperature, voltage, and manufacturing process variations. Signal drivers generally operate faster at higher voltages and lower temperatures, and are generally slower at lower voltages and higher temperatures. Variations in the manufacturing process of these electronic devices, such as shifts in threshold voltages of transistors and other process conditions, can also affect the switching speeds of the transistors. Such variations in voltages, temperatures, and process can result in large variances in the device output behavior.
For example, in clocked integrated circuit (IC) devices such as microprocessors, microcontrollers, and synchronous memories, one signal timing parameter is Tco (clock to output valid), which specifies the delay from the leading edge of a clock to when the output buffers of the clocked device switch. The Tco parameter is specified in terms of Tco_min and Tco_max, with Tco_min specifying the fastest time from clock to output valid and Tco_max indicating the slowest time from clock to output valid.
The variance in the delay time is caused by 1) the difference in flight time through circuitry in the IC device from the triggering event to the output between fast and slow conditions because circuitry tends to respond quicker in fast conditions; and 2) the difference in driver strength between fast and slow conditions (the driver output slew rate is smaller under fast conditions).
USPTO Backgrounds
USPTO Backgrounds