1. Field of the Invention
The present invention in general relates to semiconductor integrated circuit technology. More particularly, the present invention relates to a silicon-controlled rectifier integral with an output buffer.
2. Description of the Prior Art
Electrostatic discharge, ESD hereinafter, is a common phenomenon that occurs during the handling of semiconductor integrated circuit, IC hereinafter, devices. Electrostatic charges may accumulate and cause potentially destructive effects on an IC device. ESD stressing typically can occur during a testing phase of IC fabrication, during installation of the IC onto a circuit board, as well as during use of equipment into which the IC has been installed. Damage to a single IC due to poor ESD protection in an electronic device can partially or sometimes completely disrupt its operation.
There are several ESD stress models based on the reproduction of typical discharge pulses to which the IC may be exposed during manufacturing or handling. Three standards models, known as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) have been proposed. The human-body model is set forth in U.S. Military Standard MIL-STD-883, Method 3015.6. The military standard models the electrostatic stress produced on an IC device when a human carrying electrostatic charges touches the lead pins of the IC device. The machine model is set forth in Industry Standard EIAJ-IC-121, which describes the electrostatic stress produced on an IC device when a machine carrying electric charges contacts the lead pins of the IC device. The charged device model describes the ESD current generated when an IC already carrying electric charges is grounded while being handled.
Referring to FIG. 1, a conventional output buffer is schematically illustrated. The conventional output buffer, which comprises an NMOS transistor Mn and a PMOS transistor Mp, is arranged between an output pad 1 and an internal circuit 2. The NMOS transistor Mn and PMOS transistor Mp are configured with their gates coupled to the internal circuit 2, whose drains are coupled together to the output pad 1. In addition, the NMOS transistor Mn is provided with its source connected to V.sub.SS node, and the PMOS transistor Mp is provided with its source connected to V.sub.DD node. When ESD stress occurs to the output pad 1, either a N.sup.+ /P junction between the drain and bulk of the NMOS transistor Mn or a P.sup.+ /N junction between the drain and bulk of the PMOS transistor Mp enters breakdown to bypass the ESD stress, thereby preventing the internal circuit 2 from ESD damage.
However, with the trend toward submicron scale IC fabrication in view, CMOS ICs have become more vulnerable to ESD damage due to advanced processes, such as use of a lightly-doped drain ("LDD") structure and clad silicide diffusions. Under these circumstances, additional fabrication steps are required in order to sustain ESD immunity. Moreover, a spacing of at least 5 .mu.m between each contact region and polysilicon gate is required so as to uniformly conduct an ESD discharge current and thus prevent the dissipated heat from excessive concentration. Such a concern gives rise to an increase in layout area.
Therefore, modifications to the conventional output buffer presented in FIG. 1 have been proposed and schematically illustrated in FIGS. 2 and 3.
Referring to FIG. 2, a silicon-controlled rectifier 3 is added to the output buffer, positioned between the output pad 1 and a V.sub.SS node. Preferably, the silicon-controlled rectifier 3 can be a MLSCR (modified lateral silicon-controlled rectifier) disclosed in C. Duvvury and A. Ameraskera, "ESD: A PERVASIVE CONCERN FOR IC TECHNOLOGIES," Proceedings IEEE, 1993, pp. 690-702, or a LVTSCR (low-voltage triggering silicon-controlled rectifier) disclosed in U.S. Pat. No. 5,465,189. When an ESD pulse positive to the V.sub.SS node occurs to the output pad 1, the silicon-controlled rectifier 3 conducts a current to provide a discharge path. Furthermore, a resistor R is connected between the output pad 1 and the drain of the NMOS transistor Mn to make the serial resistance thereof greater than that of the discharge path provided by the silicon-controlled rectifier 3, thereby insuring the discharge current is kept away from the output buffer.
Further referring to FIG. 2, the silicon-controlled rectifier is configured with its anode 31 and cathode 32 connected to the output pad 1 and the V.sub.SS node, respectively. The silicon-controlled rectifier 3 comprises a PNP bipolar junction transistor Qp, an NPN bipolar junction transistor Qn, and two load resistors Rp and Rn. The PNP transistor Qp has its emitter as the anode 31 of silicon-controlled rectifier 3. Moreover, the PNP transistor Qp is configured with its base tied to the collector of the NPN transistor Qn to be an anode gate 33, and with its collector tied to the base of the NPN transistor Qn to be a cathode gate 34. However, the NPN transistor Qn is provided with its emitter to be the cathode 32 of the silicon-controlled rectifier 3. The load resistor Rn is connected between the anode 31 and the anode gate 33 while the load resistor Rp is connected between the cathode 32 and the cathode gate 34.
Referring to FIG. 3, a silicon-controlled rectifier 3 is added to the output buffer, but positioned between the output pad 1 and a V.sub.DD node. Preferably, the silicon-controlled rectifier 3 can be a MLSCR (modified lateral silicon-controlled rectifier) disclosed in C. Duvvury and A. Ameraskera, "ESD: A PERVASIVE CONCERN FOR IC TECHNOLOGIES," Proceedings IEEE, 1993, pp. 690-702, or a LVTSCR (low-voltage triggering silicon-controlled rectifier) disclosed in U.S. Pat. No. 5,465,189. When an ESD pulse negative to the V.sub.DD node occurs to the output pad 1, the silicon-controlled rectifier 3 conducts a current to provide a discharge path. Furthermore, a resistor R is connected between the output pad 1 and the drain of the PMOS transistor Mp to make the serial resistance thereof greater than that of the discharge path provided by the silicon-controlled rectifier 3, thereby insuring the discharge current is kept away from the output buffer.
Further referring to FIG. 3, the silicon-controlled rectifier is configured with its anode 31 and cathode 32 connected to the V.sub.DD node and the output pad 1, respectively. The silicon-controlled rectifier 3 comprises a PNP bipolar junction transistor Qp, an NPN bipolar junction transistor Qn, and two load resistors Rp and Rn. The PNP transistor Qp has its emitter as the anode 31 of silicon-controlled rectifier 3. Moreover, the PNP transistor Qp is configured with its base tied to the collector of the NPN transistor Qn to be an anode gate 33, and with its collector tied to the base of the NPN transistor Qn to be a cathode gate 34. However, the NPN transistor Qn is provided with its emitter as the cathode 32 of silicon-controlled rectifier 3. The load resistor Rn is connected between the anode 31 and the anode gate 33 while the load resistor Rp is connected between the cathode 32 and the cathode gate 34.
However, the addition of the resistor R restrains the entire integrated circuit to a lower operation speed. Furthermore, the arrangement of the silicon-controlled rectifier 3 and the resistor R means that a great deal of layout area is required, and is thus disadvantageous to the miniaturization of the integrated circuit. In addition, the NMOS transistor Mn, the PMOS transistor Mp, and the silicon-controlled rectifier 3 are connected in parallel with reference to the output pad 1. Accordingly, the spacing between each contact region and polysilicon gate must be kept wide enough to prevent the NMOS transistor Mn and the PMOS transistor Mp from experiencing an ESD stressing effect.
USPTO Backgrounds
USPTO Backgrounds