The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. Such advances have increased the complexity and challenges of processing and manufacturing of ICs.
In IC manufacturing, spacers are formed on the sidewalls of gate stacks. Spacers are needed to isolate the gate stacks from neighboring silicide regions. However, spacers make the spaces between gate stacks become narrower. As technology advances, the distance (or space) between gate stacks become smaller and the aspect ratios of such space become higher. The small distance and high aspect ratio of the space between neighboring gate stacks degrade the quality of silicide formed between the neighboring gate stacks, which results in high resistivity and poor contact yield.
Based on the problems described above, there is a need for processes that would increase the distance between adjacent gate stacks to improve silicide quality and to improve contact yield.
USPTO Backgrounds
USPTO Backgrounds