Conventional flash memory systems, otherwise known as flash electrically erasable programmable read only memories (EEPROMs), typically comprise a two-dimensional array of floating gate memory transistors, or "cells", formed on a semiconductor substrate. It includes several strings, known as NAND strings, of floating gate memory transistors, each transistor coupled to the next transistor in the string by coupling the source of one device to the drain of the next device to form bit lines. A plurality of word lines, perpendicular to the NAND strings, each connect to the control gate of one memory cell of each NAND string.
Initially, the cells are erased so as to have a certain threshold voltage, such as -2 volts. To program a cell, the selected cell is charged to a higher threshold voltage by applying a high voltage for a predetermined period of time, such as about 18 volts for about 100 .mu.s to about 250 .mu.s, to the word line of the selected cell, while the threshold voltage of the remaining ("unselected") cells remains unchanged.
A problem arises when it is desired to program one selected cell on a word line without programming other cells on the same word line. When a voltage is applied to a word line, that voltage is applied not only to the selected cell but also to the cells along the same word line which are unselected for programming. An unselected cell on the word line, especially a cell adjacent to the selected cell, may become inadvertently programmed. The unintentional programming of an unselected cell in a selected word line is referred to as "program disturb".
Several techniques in combination are typically employed to prevent program disturb. In a method known as "self-boosting", the unselected bit lines are electrically isolated and a pass voltage, such as about 10 volts, is applied to the unselected word lines during programming. The unselected word lines capacitively couple to the unselected bit lines, causing a voltage, such as about 8 volts, to exist on the unselected bit lines, which tends to reduce program disturb. Disadvantageously, if the boosted voltage leaks from the unselected bit lines to the selected bit line (which has no voltage applied to it) during programming, disturb may occur in unselected cells on the selected bit line. This condition, which limits the amount of pass voltage which can be safely applied, hence limiting the effectiveness of the self-boosting technique, is referred to as pass disturb. The leakage path from the unselected bit lines to the selected bit line can be shut off if a negative bias is put on the substrate (also called the p-well). However, applying this charge to the p-well significantly lengthens the time required for programming, and requires additional circuitry and a corresponding increase in the size of the memory system.
Yet another conventional technique for reducing disturb is to isolate adjacent bit lines with a dopant such as boron. However, there is a limit to the amount of dopant which can be implanted into the substrate without causing undesirable electrical effects. Furthermore, this technique is problematic given the current demands for miniaturization and increased circuit density, which necessitate moving the bit lines closer together, leaving less room for such implantation.
Another method used to reduce program disturb is to place a positive bias on the selected bit line. However, this also lengthens the time required for programming, and necessitates an increase in the programming voltage to compensate for the positive bias.
There exists a need for a method of programming a NAND flash memory system with minimal program disturb which does not cause pass disturb or increase the size and complexity of the memory system.
USPTO Backgrounds
USPTO Backgrounds