1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the present invention relates to a non-planar split-gate-type nonvolatile semiconductor memory device and a method of manufacturing the same.
2. Description of the Related Art
In recent years, electrically erasable and programmable read only memory (EEPROM) or flash memory devices have become strongly relied upon. A flash memory, widely used nowadays, can be electrically erased and programmed, and retains data even if the supply of power is interrupted.
In a nonvolatile semiconductor memory device, memory cells are connected to a bit line parallel to each other. If the threshold voltage of a memory cell transistor becomes lower than a voltage (normally, 0 V) applied to a control gate of a non-selection memory cell, current flows between a source region and a drain region irrespective of whether a selection memory cell is turned on or off. As a result, all the memory cells are read as if they are continuously in a turn-on state. For this reason, it is necessary to strictly control the threshold voltage in the nonvolatile memory device, which is very difficult. Also, high-speed programming of memory cells necessitates generation of sufficient channel hot carriers, and high-speed erasing thereof requires generation of sufficient Fowler-Nordheim (F-N) tunneling currents. To generate sufficient channel hot carriers or sufficient F-N tunneling currents, a high voltage is indispensable.
To solve these problems, split-gate-type nonvolatile semiconductor memory devices (e.g., as disclosed in U.S. Pat. No. 5,045,488) have been proposed. In these conventional split-gate-type nonvolatile semiconductor memory devices, a channel region formed by a floating gate and another channel region formed by a control gate are connected in series on the same plane.
Also, with the increased integration density of semiconductor memory devices, various structures and manufacturing processes of semiconductor devices (e.g., as disclosed in U.S. Pat. No. 6,329,685) have been proposed to minimize alignment errors between components such as sources, drains, control gates, and floating gates.
Meanwhile, in recent field effect transistor (FET) techniques, devices are scaled down, thereby achieving high efficiency and thus improving the operating speed. As the channel length of an FET has been scaled down on the level of 100 nm or less, it is very difficult to sufficiently reduce the gate length of the FET by scaling. However, the conventional split-gate-type nonvolatile memory device has a planar channel structure. In this planar FET, the gate length can be scaled along with the scaling of a transistor. However, while the distance between a source region and a drain region decreases, it is difficult to sufficiently scale a tunneling oxide layer.
Thus, adverse coupling occurs between channel regions and the source region or the drain region. This lowers the controllability of a gate for turning on and off a semiconductor device, and leads to a short channel effect (SCE) and drain induced barrier lowering. Therefore, in the conventional planar nonvolatile semiconductor memory devices, the SCE cannot be properly controlled by scaling.
A split-gate-type flash memory device has a floating gate which is separated from a control gate and electrically isolated from the outside. Data storage is enabled by using a variation of current level in memory cells through injection of electrons into the floating gate (i.e., programming) and emission of the electrons from the floating gate (i.e., erasing). The injection of electrons into the floating gate is performed using channel hot electron injection (CHEI), whereas the emission of electrons from the floating gate is performed by F-N tunneling mechanism using an insulating layer between the floating gate and a control gate. Nowadays, attempts are being made to increase the erasing efficiency by forming tips at edge portions of the floating gate, adjacent to the control gate. However, in the conventional nonvolatile semiconductor memory devices, the number of corners of the floating gate where the tips can be formed is too low to improve the erasing efficiency.
USPTO Backgrounds
USPTO Backgrounds