As technology in the computer industry advances, the speed at which information is processed and accessed is increased. Certain instructions only require internal action by the processor, the processor speed controls the speed of a computer system in these situations. However, other instructions initiated by the processor require external transactions which are paced by the speed at which peripheral devices interact with the processor. Thus, optimization can be obtained by processing the transactions prior to presenting the transaction on the bus interface which requires a peripheral device to process the transactions. However, a difficulty can occur with data coherence. If data to a particular location is continuously updated and read, then the transactions to and from this location must be processed in the order in which the processor generated the transactions. Thus, when dealing with cache memory, a write request to a specific location in cache memory must be completed prior to a later request to read from that same location in memory. And conversely, a read request to a specific location in cache memory must be completed prior to a later request to write to the same location in memory.
The prior art includes at least two schemes. One scheme allows for complete in-order processing of transactions. An in-order implementation requires that a processor's read or write transactions be performed in the order in which the processor requests each transaction. This process ensures read/write coherence, but does nothing to optimize the bus utilization.
Another prior art scheme allows for out of order processing of transactions such that the read and write transactions to the cache memory can be prioritized to optimize the bus utilization. If a read transaction collides with a resident write transaction, the read data is forwarded from the write queue entry. This allows a read transaction to be performed without dependence upon the completion of a write transaction. However, this requires an undesirable increase in hardware and complexity on the processor chip or chip set.
Any advancement in the ability to optimize bus utilization while maintaining read/write coherence would be beneficial. Therefore, it is an objective in this invention to provide an increased bus utilization while maintaining read/write coherence.
USPTO Backgrounds
USPTO Backgrounds