1. Field of the Invention
The present invention relates to a method of disposing an anti-reflective coating (ARC), such as a dielectric anti-reflective coating (DARC), on a semiconductor device structure. Particularly, the present invention relates to a process for reducing the occurrence of particles or roughness on an exposed surface of an ARC or a DARC. More particularly, the present invention relates to a process which reduces the incidence of in-film particles and interfacial irregularities between an ARC or DARC layer and an adjacent, overlying silicon nitride layer.
2. Background of Related Art
Photolithography processes that have been conventionally employed in the manufacture of semiconductor devices typically include disposing a photoresist material over a layer of a semiconductor device structure, such as a wafer or bulk semiconductor material, that is to be patterned, positioning a diffraction grating over the layer of photoresist material, positioning a mask or reticle between the diffraction grating and the layer of photoresist material, and directing electromagnetic radiation, or "light," of some wavelength through openings in the diffraction grating and the mask or reticle in order to "expose" and fix portions of the photoresist beneath the diffraction grating and thereby define an etch mask from the photoresist. Many materials, such as polysilicon, aluminum and metal silicides, that are employed to fabricate structures of semiconductor devices are, however, highly light reflective.
The reflection of light by an underlying layer of material distorts the mask image that is defined from the layer of photoresist material, thereby distorting the structures that are to be defined through the mask image. Exemplary types of photomask distortion that may occur include exposure variations in the thickness of the layer of the photoresist material, which degrade the resolution of the structure to be patterned through the mask and are typically referred to as "standing waves;" pattern dimension variations, or "multiple interferences," caused by variations in the thickness of the layer of photoresist material, which deteriorate the dimensional precision of the structure; and "halation," which is caused by variations in the underlying layer, such as unevenness thereof, which cause light to be reflected into portions of the layer of photoresist material that were intended to be shielded, thereby exposing these portions of the photoresist material layer to light. The magnitude of each of these distortions of the layer of photoresist material depends on the intensity of the light reflected from the underlying layer. As the intensity of reflected light is reduced, the magnitude of standing waves, multiple interferences and halation are also reduced.
Due to the ever-decreasing geometries of state-of-the-art very large scale integration (VLSI) and ultra large scale integration (ULSI) semiconductor devices, and because of the relatively small dimensional tolerances and high dimensional resolution that are desired of the various structures of such devices, techniques have been developed to reduce the intensity of light that is reflected by the layer of material to be patterned.
One type of anti-reflective technique includes the deposition of a film of photo absorptive material, such as an anti-reflective coating (ARC) or a dielectric anti-reflective coating (DARC), over a layer of material to be patterned by etching prior to disposing a photoresist material over the semiconductor device structure. As portions of the layer of photoresist material are exposed to light, the light passes therethrough and some of the light is absorbed by the ARC or DARC film, thereby reducing the intensity of light that is reflected back into the photoresist, and decreasing the incidence and magnitude of standing waves, multiple interferences, halation, or other distortions of the resultant mask.
An exemplary ARC is a polymer film that may be disposed on the substrate layer by spin-on techniques. Other anti-reflective materials, such as the silicon-rich silicon nitride DARC disclosed in U.S. Pat. No. 5,378,659, which issued to Roman et al. on Jan. 3, 1995; and U.S. Pat. No. 5,539,249, which issued to Roman et al. on Jul. 23, 1996; and the silicon, oxygen and nitrogen DARC materials disclosed in U.S. Pat. No. 5,698,352, which issued to Ogawa et al. on Dec. 16, 1997, may be deposited by known processes, such as chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD).
The plasmas that are employed to fabricate layers of materials on semiconductor device structures may cause particulate contamination of PECVD process chambers. These contaminant particles may be subsequently disposed upon the surfaces of the exposed layers of a semiconductor device structure that is being processed within the process chamber.
Some PECVD-fabricated DARC films, however, typically have surface roughness features or particles of a size of less than about 120 nanometers (nm) dimension on the surfaces thereof. These rough surfaces or particles may act as "seeds" for the growth of larger particles when silicon nitride is subsequently disposed on the DARC film. Thus, when silicon nitride films or structures are subsequently fabricated over PECVD-fabricated DARC films which include silicon, oxygen and nitrogen, seed particles or surface roughness features on the DARC film are known to enhance increased growth of silicon nitride thereover during fabrication of a silicon nitride layer on the DARC film, which may create non-uniformities or particles of about 120-150 nm dimension in the silicon nitride layer, which are referred to as "in-film" particles, at an incidence of about 40,000 or more per eight inch semiconductor wafer. Such in-film particles are undesirable because they may cause structural deformities or other problems in semiconductor device structures of ever-decreasing dimensions.
After such a DARC film has been deposited on a semiconductor device structure and prior to removal of the semiconductor device structure and insertion of one or more subsequent semiconductor device structures into the process chamber, the process chamber is cleaned, which typically includes purging the chamber with an inert gas, such as helium. An undesirable number of particles or surface roughness features which may act as seeds for in-film particles of about 120-150 nm dimension may, however, remain present on DARC films that are fabricated in a chamber cleaned with such a helium purge.
Alternatively, semiconductor wafers or other semiconductor device structures may be heated prior to DARC film fabrication thereon in order to reduce the occurrence of particles or surface roughness of less than about 120 nm. Such preheating, however, is undesirable in that the wafer throughput is limited, thereby raising production costs, as more chambers are required to achieve the same level of throughput that may be achieved without such preheating.
U.S. Pat. No. 5,637,190 (the "'190 patent"), which issued to Liao on Jun 10, 1997; and U.S. Pat. No. 5,700,741 (the "'741 patent"), which issued to Liao on Dec. 23, 1997, disclose exemplary processes for removing contaminants from a reaction chamber by a plasma-assisted purge. The '741 patent discloses a plasma purge process which includes performing a plasma-assisted process on one or more layers of a semiconductor device structure and employing a radio frequency plasma to polarize and dilute any contaminants that remain in the process chamber while the semiconductor device structure remains in the process chamber, thereby decreasing the likelihood that any contaminant particles will contaminate the semiconductor device structure. The purging radio frequency plasma is generated at a lower power than the previously-employed process plasma in order to polarize any contaminants in the process chamber. The pressure within the process chamber is increased during the purge to dilute any contaminants that remain in the process chamber. The purge gas includes an oxidizing purge gas component, and may also include a non-oxidizing component. Subsequently, the plasma purge may be repeated, but at a lower radio frequency power and an increased process chamber pressure.
The '190 patent discloses a similar process that employs a plasma including both oxidizing and non-oxidizing components. The plasma of the '190 patent, however, chemically and physically etches any contaminants remaining in the process chamber, as well as polarizing and diluting the contaminants. The plasma power and process chamber pressure requirements of the '190 patent are similar to those of the '741 patent.
Although the '190 and '741 patents discuss processes which decrease the amount of contamination in a process chamber following fabrication or definition of silicon oxide layers of a semiconductor device, neither of them disclose use of the purge process to reduce surface roughness or particles on the surface of DARC films that include silicon, oxygen and nitrogen or the formation of in-film particles in a silicon nitride overlayer. Moreover, the processes disclosed in those patents employ oxidizing purge gases, which may not be useful for reducing or eliminating the occurrence of particles or a rough surface on a DARC film that includes silicon, oxygen and nitrogen. Neither the '190 patent nor the '741 patent addresses the removal of contaminants from a process chamber after a deposition operation, removal of the coated semiconductor device structure or other structures and prior to disposing another semiconductor device structure in the process chamber or to fabricating a DARC film thereon by PECVD techniques to reduce or eliminate the incidence of particles or an unduly rough surface on the DARC film.
Thus, a plasma purge process which employs a substantially inert gas is needed to reduce or eliminate the incidence of particles or magnitude of surface roughness features on the surface of PECVD-fabricated DARC films that include silicon, oxygen and nitrogen. A plasma purge process is also needed which may be employed prior to disposing a semiconductor device structure into a PECVD process chamber for processing.
USPTO Backgrounds
USPTO Backgrounds