1. Field of the Invention
The present invention generally relates to integrated circuit (IC) devices and, more particularly, to trimming circuits used to adjust the levels of voltages generated internally to such devices.
2. Description of the Related Art
Integrated circuit (IC) devices often operate using various internally generated voltages in an effort to reduce sensitivity to fluctuating external voltage supplies. Each internally generated voltage may also be used to perform different functions required by the IC. Internal voltage generating circuits used in such devices often include trimming circuits to adjust the internally generated voltages, for example, to compensate for variations introduced by the manufacturing process.
The trimming circuits are adjusted to bring internally generated voltages as close as possible to a target voltage during a testing procedure. Each trimming circuit may be adjusted, for example, via a set of one or more switches that may be open or closed to increase or decrease the level of the generated voltage. Typically, appropriate settings for each trim circuit are selected by a testing device (a tester) while the IC is still on a wafer and before the device has been packaged. Because each IC on the wafer may differ from each other IC, the tester may have to individually select trim settings for each IC. As a result, selecting the proper trim settings for each device may be a time-consuming process.
Another difficulty in testing each IC is establishing a connection between the tester and each IC. In order to establish the connection, the tester may use a probe card to physically connect to a number of ICs on the wafer. Due to the number of ICs on each wafer, each time a connection between the tester and wafer is established (called a touch-down), only a limited number of the ICs may be tested (and have their trim settings adjusted) at a time. Accordingly, multiple touch-downs for each wafer may be required in order to adjust all of the trim settings for each IC. The number of touch-downs necessary for an entire wafer further increases the amount of time necessary to establish trim settings for an entire wafer.
Once the appropriate trim settings for each IC have been established, each trim setting may then be saved by the tester. In order to save each trim setting, the tester may burn the settings to one or more fuses on each IC. Because the trim settings for each IC may differ, the fuses for each IC must be burned independently. In some cases, the tester may burn laser fuses to store the trim setting. In other cases, the tester may burn electronic fuses (e-fuses) to store the trim setting or the setting may be stored in some other form of non-volatile memory. In either case, independently burning the fuses for each IC on the wafer (which may require multiple touch-downs) is also a time-consuming procedure. Such excessive time requirements for performing device testing substantially reduce production efficiencies and throughput.
After the appropriate trim settings for each IC have been selected and saved, the IC may be separated from the wafer and packaged. During packaging, the IC may be connected to a package substrate and to connection pads on the substrate which route IC connections to external pins on the package. Such packaging and connections may cause heating of the IC and change the electrical characteristics of the IC and connections to the IC. Thus, trim settings, if any, selected while the IC was still on the wafer and before the IC was packaged may no longer be appropriate (i.e. the internally generated voltages may have changed) due to changes in the IC which occur during packaging.
Accordingly, what is needed are improved methods for adjusting trim settings for internally generated voltages of an integrated circuit device. There is a need to reduce or minimize the number of touchdowns on device pads required to complete testing of the devices on the wafer. Additionally, there is a need to improve efficiencies in testing time. Furthermore, there is a need for adjusting trim settings of an IC after the IC has been packaged.
USPTO Backgrounds
USPTO Backgrounds