1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a multilayer semiconductor device in which wiring metal films and via plugs electrically connecting the metal films are formed or contact plugs electrically connecting electrodes of various elements with the metal films.
2. Description of the Related Art
As semiconductor devices such as LSIs have been increased in integration, density and processing rate in recent years, it is a tendency that various elements and metal wirings are laminated one over another perpendicularly to a semiconductor substrate to form a multilayer structure. In such multilayer semiconductor devices, in order to make individual elements such as transistors and diodes in a lower layer operative, it is necessary to connect electrodes of the individual elements with metal wirings in an upper layer. For this purpose, holes called contact holes are formed in an interlayer insulation film which electrically insulates the individual layers from one another, and metal material is filled in the via holes to form metal pins called contact plugs, via which electrodes of various elements and the metal wirings of the lower upper layer are mutually connected.
Further, in the multilayer semiconductor devices, it is necessary to connect the metal wirings of the lower layer with those of the upper layer. For this purpose, holes called via holes are formed in an interlayer insulation film, and metal material is filled in the via holes to form metal pins called via plugs, via which the metal wirings of the lower layer and those of the upper layer are mutually connected.
Recently the increase of semiconductor device in integration, density and operating speed is reaching the stage of reducing the size of the contact holes and via holes. In the meantime, however, the thickness of the interlayer insulation film tends to increase due to the complexity of structure of a capacitor section to be formed on the semiconductor substrate and the flattening of the interlayer insulation film as by chemical and mechanical polishing (CMP). As a result, the aspect ratio indicating the ratio of the diameter (horizontal size) of the contact holes and of the via holes and the depth (vertical size) of the contact hole and of the via holes would be only around 2 in case of a DRAM whose memory capacity is 4 Mbit but it would be 4 or more in case of a DRAM whose memory capacity is 256 Mbit. This increase in aspect ratio necessitates to form contact plugs or via plugs by filling good step coverage in contact holes or via holes.
To meet this requirement, R. Fiordalice et al. presented a method entitled "A low temperature CVD Al plug and interconnect process for 0.25 .mu.m metallization technologies" in 1996 Symposium on VLSI Technology Digest of Technical Papers, p. 42, 1996.
This method will now be described with reference to FIGS. 3(a) through 3(c) of the accompanying drawings of the present specification.
Firstly, an interlayer insulation film 2 as of silicon oxide (SiO.sub.2) is formed on a semiconductor substrate 1 as of silicon (Si), whereupon contact holes 3 are opened as shown in FIG. 3(a), through steps of applying a resist, exposing, etching and peeling the resist. No element is illustrated either on the surface or inside the semiconductor substrate 1 for clarity in FIGS. 3(a) through 3(b); actually, however, various elements such as transistors are formed over which the interlayer insulation film 2 is formed.
Then a barrier metal film (not shown) as of titanium (Ti) is formed by physical vapor deposition (PVD) such as by sputtering, whereupon an aluminum film (hereinafter called the PVD-Al film) 4 is formed also by PVD as shown in FIG. 3(b). The barrier metal film is a foundation film for improving the tightness between the PVD-AL film 4 and the interlayer insulation film 2 and for preventing the connection from being broken due to mutual diffusion caused by reaction of raw material gas, which is used in chemical vapor deposition (CVD), with the semiconductor substrate 1 to form below-described contact plugs 6.
Then assuming that an aluminum film (hereinafter called the CVD-Al film) 5 is formed over the entire surface of the PVD-Al film 4 by CVD, as shown in FIG. 3(c), while it is kept in vacuum in the apparatus, the CVD-Al film 5 epitaxially grows on the PVD-Al film 4 to fill aluminum in the contact holes 3 to form the contact plugs 6.
In the above-mentioned conventional method, while the PVD-AL film 4 is formed, it deposits at the openings 3a of the contact holes 3 so as to reduce the size of the contact holes 3 as shown in FIG. 3(b). This phenomenon is called "overhanging", and such patterned portion of the PVD-AL film 4 is called an overhang 4a.
Since this overhang 4a exists, the openings 3a of the contact holes 3 are closed by the CVD-AL film 5 as shown in FIG. 3(c) before aluminum has been completely filled in the contact holes 3 while the CVD-Al film 5 is formed, so that voids 7 occur in the contact holes 3.
This occurrence of the voids 7 reduces the cross-sectional area of the contact plugs 6 and increases the current density of current to flow in the contact plugs 6, which would cause heat generation electromigration either resulting in wire breakage. Electromigration is a phenomenon in which metal atoms move along the flow of electrons in the wiring; breakage of the wiring occurs at its local portion where metal atoms have disappeared as they have moved, and shortcircuiting of the wiring occurs where metal atoms have been deposited adjacent to another wiring.
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