1. Technical Field
The present invention relates to a plasma processing apparatus for processing an object to be treated, in particular a semiconductor wafer or a substrate for liquid crystal, a semiconductor manufacturing apparatus such as a high-density plasma (HDP) CVD apparatus, and an electrostatic chucking unit used for the corresponding semiconductor manufacturing apparatus.
2. Related Arts
Generally, a plasma etching apparatus, plasma CVD apparatus, ion implantation apparatus, sputtering apparatus, etc., are available as a plasma processing apparatus used for manufacturing semiconductor devices, liquid crystal display devices, etc. A high-density plasma (HDP)-CVD apparatus, which carries out CVD (chemical vapor deposition) by generating high-concentration plasma, of these plasma processing apparatuses is used for forming an interlayer insulation film, trench embedding film, or passivation film in a semiconductor apparatus.
Conventionally, this type of HDP-CVD apparatus is provided with a vacuum chamber into which a processing gas can be introduced and from which the inner gas can be discharged, and an RF coil disposed so as to surround the vacuum chamber. By driving the RF coil by an RF power source, high-density plasma is generated in the vacuum chamber. There may be cases where an electrostatic chucking unit (ESC) that electrostatically supports and fixes a semiconductor wafer, etc., which is an object to be treated, is disposed in the vacuum chamber of the HDP-CVD apparatus.
In Japanese Unexamined Patent Publication No. Hei-10-242244 (1st prior art), an HDP-CVD apparatus equipped with an electrostatic chucking unit (ESC) is disclosed. The HDP-CVD apparatus disclosed in the first prior art has a unipolar electrostatic chuck unit for attracting a semiconductor wafer or other substrate onto a surface of the dielectric film coated on the chuck unit by means of electrostatic attraction of an inductive charge. Where the electrostatic chuck unit is used, it is possible to dispose and treat two wafer sheets thereon. In detail, the electrostatic chuck unit disclosed in the first prior art is provided with a cylindrical chuck body formed of a dielectric and a dielectric layer formed on two circular regions of the chuck body opposed to each other. Also, at the same time, a water-cooling channel for cooling the chuck body itself and a helium channel for cooling the wafer are provided in the chuck body. Further, the chuck body is connected to a bias RF source by a power source line, and bias RF voltage is applied to the chuck body through the power source line, where charge plasma is generated in a processing area, and a wafer is electrostatically attracted onto and fixed on the chuck surface with electrostatic attraction of an inductive charge based on the charge plasma.
On the other hand, in the specification of Japanese Unexamined Patent Publication No. 2003-160138 (2nd prior art), an HDP-CVD apparatus is shown, which has an electrostatic chuck unit in the vacuum chamber thereof. The electrostatic chuck unit shown in the second prior art is provided with an ESC (electrostatic chuck structure) stage, an RF introducing rod, connected to the stage and the bias RF power source, which supplies bias RF from the bias RF power source to the ESC stage, and a bias RF wiring, extending from the RF introducting rod, which is connected to the ESC stage. In addition, where plasma processing is carried out by generating high-power and high-density plasma using the electrostatic chuck of the second prior art, it has been pointed out that unfavorable damage occurs in a substrate to be plasma-treated, for example, a semiconductor wafer, and as a result, product yield is remarkably lowered.
Herein, a detailed description is given with the HDP-CVD apparatus shown in the second prior art with reference to drawings. Referring to FIG. 1 and FIG. 2, the HDP-CVD apparatus shown therein is a processing portion of a cluster type vacuum processing apparatus. The processing portion has a vacuum chamber 10, and the vacuum chamber 10 has a ceramic dome 11 with an opening at its top and a channel body (lower chamber) 12 connected to the dome 11. The dome 11 and the channel body 12 define the interior space of the vacuum chamber 10.
A top coil 15 is disposed on the top of the dome 11. On the other hand, a side RF coil 16 is disposed sideways of the dome 11. Further, a side nozzle 18 for jetting a gas to the side of the dome 11 is provided inside the dome 11. With such a construction, plasma generating space is provided at the upper part of the dome 11, and processing space is provided at the lower part of the dome 11.
As illustrated, a ceramic plate (herein, A1N plate) 26, a heater plate 28 and a cooling plate 30 are laminated in this order and provided on the top coil 15 secured at the top portion of the dome 11. Also, a nozzle 32 is provided so as to protrude inside the dome 11 at the middle part of the top portion of the dome 11, and the nozzle 32 is connected to the top 02 line and top silane line, which extend through an opening formed between the cooling plate 30, heater plate 28 and ceramic plate 26. Also, the dome 11 and the entire members incidental thereto are enclosed by a lid cover 35. Further, the top coil 15 and side coil 16 are connected to the RF power source 36, and a source RF voltage is applied from the RF power source 36 to these coils 15 and 16.
On the other hand, a turbo pump 22 for exhausting air from the vacuum chamber 10 is connected to the bottom of the channel body (lower chamber) 12 via a slot valve 20 and a gate valve 21. In addition, a slit valve 24 and a remote plasma generator (applicator) 27 are provided at the side portion of the channel body 12.
Furthermore, a cathode body 40 for supporting and fixing an object to be processed (herein, a semiconductor wafer) is disposed in the processing space defined by the channel body 12 so as to be opposed to the top nozzle 32, and an electrostatic chuck unit 44 is installed in the processing space between the cathode body 40 and the side nozzle 18.
The electrostatic chuck unit 44 illustrated is electrically connected to the bias RF power source 42 secured outside the vacuum chamber 10, and a bias RF voltage of 13.56 kHz is supplied from the bias RF power source 42 to the electrostatic chuck unit 44 via a power supply shaft, that is, the RF introduction rod 46.
Herein, the electrostatic chuck unit 44 includes a supporting member 441 formed by a dielectric for supporting a substrate such as a semiconductor wafer and a conductive member 442 formed by a conductive material such as aluminum, and the conductive member 442 is connected to the RF introduction rod 46 via a wiring member 443. A combination of the electrostatic chuck unit 44, wiring member 443 and RF introduction rod 46 is herein called as an “electrostatic chuck member.”
In the HDP-CVD apparatus thus constructed, when a bias RF voltage is supplied from the bias RF power source 42, charge plasma is generated, and the semiconductor wafer is electrostatically attracted on the upper surface of the electrostatic chuck by electrostatic attraction based on an inductive charge by the charge plasma and is fixed thereat.
Here, with reference to FIG. 2, a further detailed description is given of a construction of the electrostatic chuck unit 44 that composes the cathode body 40 used for a prior art plasma processing apparatus. FIG. 2 shows a connection between the electrostatic chuck unit 44 and the RF introduction rod 46 when the electrostatic chuck unit 44 is observed from the rear side of the cathode body 40. As illustrated, the RF introduction rod 46 is connected, at one point, to the conductive member 442 of the electrostatic chuck unit 44 by the wiring member 443.
However, the first prior art discloses only an electrostatic chuck unit having two electrostatic chucking surfaces and capable of processing two wafer sheets. It does not disclose any connection position, etc., between the electrostatic chuck unit and a power source line. Therefore, in the first prior art, no consideration is taken of distortion of an electromagnetic field based on an application position of the electrostatic chuck unit, to which a bias RF voltage is applied from the bias RF source, and influences thereof.
On the other hand, it has been pointed out, in the second prior art, that the electric field in the vacuum chamber is locally increased due to overlapping of the electric field based on the source RF output portion and the electric field generated in the application position of the bias RF in the ESC stage, whereby plasma is biased, and plasma damage is produced at a partial area of silicon wafer. Taking the same into consideration, the second prior art discloses that it is possible to mitigate plasma damage in wafer by determining the application position of the bias RF in the ESC stage at a position apart from the electric field based on the source RF output portion (that is, a position as far from the RF introduction rod as possible).
However, the second prior art only points out alternation of the positions of the source RF output portion and the bias RF application point. The second prior art does not disclose any means for making uniform the electric field inside the ESC stage.
Further, according to experiments made by the present inventor, as in the second prior art, it is made clear that only alteration of the connection position of the bias RF wiring connected to the RF introduction rod is insufficient to make distribution of the electric field in the vacuum chamber uniform.
Next, it is confirmed that, where, using a HDP-CVD apparatus shown in FIG. 1 and FIG. 2, a MOS transistor is produced on a semiconductor wafer incorporated in the electrostatic chuck unit 44, plasma damage is intensively generated at the connection part between the wiring member 443 for introducing bias RF and the electrostatic chuck unit 44, and in the vicinity thereof.
To make this clear, a description is given of the results of experiments in the case where a prior art plasma processing apparatus was used. First, a method for evaluating gate breakdown voltage using an antenna ratio has been known as a technology for evaluating plasma damage in a CVD apparatus. Herein, the antenna ratio expresses the ratio (SH/SG) of the area (SG) of a gate electrode of a MOS transistor formed as a device and the area (SH) of wiring connected to the gate electrode. Since the larger the antenna ratio becomes, the wider the area exposed to plasma becomes, deterioration of the gate breakdown voltage becomes remarkable. In addition, in a case of a device having a fixed antenna ratio, the higher the intensity of plasma is, the greater the deterioration of the gate breakdown voltage of the device becomes.
Using such an evaluation method, the gate breakdown voltage of the MOS transistor in a semiconductor wafer manufactured by a prior art HDP-CVD apparatus shown in FIG. 1 and FIG. 2 was evaluated, and the results shown in FIG. 3 were obtained. FIG. 3 shows the positions of the chips in the wafer which are subjected to plasma damage. For example, ▪ shows the chip which is subjected to plasma damage and whose breakdown voltage is 5 kV or low. In FIG. 3, the number of chips of ▪ is 17. Also, the number of chips whose breakdown voltage is 6.2 kV or low and larger than 6 is 36, for example.
As shown in FIG. 3, it has been found that, even in a case where the antenna ratio is comparatively small, for example, antenna ratio=5K, a number of chips which are subjected to plasma damage were produced, and the number of chips which are subjected to plasma damage was increased as the antenna ratio becomes larger and larger for 20K, 45K and 125K. Also, it is found that, where the connection position of the RF introduction rod 46 shown in FIG. 2 is taken into consideration, chips in which plasma damage occurred were unevenly generated at the connection position side by the wiring member 443 between the electrostatic chuck unit 44 and RF introduction rod 46. It can be presumed that this situation occurred due to strain in the electric field generated when closing the bias RF power source 42.
USPTO Backgrounds
USPTO Backgrounds