1. Field of the Invention
The present invention relates generally to data processing systems and more particularly to an apparatus and method for overcoming the deleterious effects of clock skewing in a synchronous data processing system employing a plurality of integrated circuits.
2. Description of the Related Art
Virtually every circuit designed in modern electronic systems involves some kind of data transfer between multiple integrated circuit (IC) chips, often located on separate printing circuit boards. For digital systems, the data is typically transferred at the transitions of a clock signal from a register or flip flop in a sending IC to a similar device on a receiving IC. For error free transmissions, the clock signals appearing at each register should operate in-phase.
A particular problem which is caused by propagation time variations in a synchronous data processing system occurs in connection with the propagation of a clocked signal in a system having a multiple number of IC's. For example, propagation time variations (clock skewing) of an input clocked signal can produce significant skewing of clocked data signal when such a clocked data signal is applied to different IC's of the system relative to the systems clock reference signal. As system cycle time decreases relative to the time associated with clock skew, the clock skew can become an non-insignificant portion of the cycle time which may require a system to increase the overall cycle time to compensate for the clock skew overhead. However, in today's high performance systems (either computers or other systems designed using digital service), increasing the system cycle time can have a significant deleterious effect on system speed.
A principle cause of clock signal skew in a data processing system is effected by signal propagation time variations which result from the employment of multiple IC's in a system, wherein each IC causes different signal delays due to differing manufacturing process tolerances relative to one another. This is a particularly sensitive problem in the case of clock distribution circuitry.
One solution to this skew problem is to improve chip fabrication processes so as to make chips more uniform so that tolerances from chip-to-chip are smaller. However, the increased cost that would be involved makes this solution economically impractical.
Hence, there exists a need to reduce clock skew in a data processing system which results from the deleterious effects of propagation time variations inherent in an integrated circuit.
USPTO Backgrounds
USPTO Backgrounds