I. Field of the Invention
The invention relates in general to an embedded system and, in particular, to an embedded controller integrated with a chipset controller for accessing flash memory devices.
II. Background of the Invention
Conventionally, as shown in FIG. 1, a system 10 includes a chipset 101, an embedded controller 103, a first set of memory devices 105, and a second set of memory devices 107. The chipset 101 accesses the first set of memory devices 105 and the embedded controller 103 accesses the second set of memory devices 107, respectively. Typically, both the first set of memory devices 105 and the second set of memory devices 107 are flash memory devices. A flash memory device can be in a particular size, such as 1 MB, 2 MB, 4 MB, or 8 MB bits. For example, the chipset 101 requires a 5 MB memory and the embedded controller 103 requires a 3 MB memory. In order to satisfy the requirements, the first set of memory 105 can be an 8 MB flash memory device or a combination of a 1 MB and a 4 MB flash memory devices; and the second set of memory 107 can be a 4 MB flash memory device or a combination of a 1 MB and a 2 MB memory device. As a consequence, although the chipset 101 and the embedded controller 103 require only 8 MB size of flash memory in total, there are more than 8 MB size of flash memory are actually used, which is costly and takes a bigger space to accommodate the flash memory devices.
In another example, the price of a flash memory device is not actually proportional to its capacity; and it tends to bear a higher price for a single large-size flash memory device compared with an equivalent capacity of several small-size flash memory devices.
Therefore, what is need is a solution to flexibly choose a combination of flash memory devices to reduce the overall cost of the flash memory devices or increase the overall utilization of the flash memory devices.
USPTO Backgrounds
USPTO Backgrounds