In a conventional DRAM, redundant cells are provided in order to improve manufacturing yield, therefore, even when a defect occurs in a part of normal memory cells, by relieving and replacing the defective cells with redundant cells, the device can be made non-defective. The replacement with redundant cells is performed by programming such as cutting the fuses according to the addresses with a write/read fault during a preliminary test in the wafer state. First, a typical example of an array configuration of a DRAM with the function of replacing a defective cell with a redundant cell is explained with reference to FIG. 1. FIG. 1 shows an overall array configuration of an embodiment where the present invention is applied, however, this will be explained first for the understanding of the invention technology.
In reference to FIG. 1, memory plates 7 are composed of a memory cell group N7, which is a group of normal cells, and an R memory cell group R7, which is a group of column redundancy cells, and provided plurally, arranged in a matrix form of row number 0 through M and column number 0 through N. The memory plates 7 and word line drivers (sub-word line drivers) SWD 12 are provided alternately in the column direction.
Sense amplifiers 6 are composed of SAN 6, which are sense amplifiers controlling the memory cell group N7, and SAR 6, which are sense amplifiers for the column redundant cells, controlling the R memory cell group R7.
The memory plates 7 and sense amplifiers 6 are provided alternately in the row direction. A sense amplifier sandwiched by the memory plates 7, for example the sense amplifier 6, which is sandwiched by the memory plates 7 on row number 0 and row number 1 in FIG. 1, controls both of the memory plates, the one on row number 0 (on the left side in FIG. 1) and one on row number 1 (on the right side in the drawing).
Such a sense amplifier configuration that controls the memory plates on both left and right sides is called shared sense amplifier.
Further, X decoders XDEC 14 are provided below the array configuration in FIG. 1, and Y decoders YDEC 13 are provided on the left side of the array configuration. The YDEC 13 comprises a YDEC N13 that outputs multiple row selecting signal lines YSW 0, YSW 1, etc. controlling a sense amplifier N 6 for the normal cells, and a RYDEC R13 that outputs a row selecting signal line RYSW controlling a sense amplifier R6 for the column redundancy cells.
In FIG. 1, only the row selecting signal lines YSW0, YSW1, etc and the RYSW on row number 0 are shown, however, these are similarly provided in row numbers 1 through N as well. Also, in the array configuration example shown in FIG. 1, only a column redundancy architecture that performs the replacement in the column direction is shown, however, a row redundancy architecture that performs the replacement in the row direction is also provided in a conventional configuration.
FIG. 6 is a drawing showing an example of a conventional circuit configuration of the shared sense amplifiers sandwiched by 2 memory plates 7 out of the sense amplifiers 6 shown in FIG. 1.
In reference to FIG. 6, to the left of a shared sense amplifier 60 (which corresponds to 6 in FIG. 1), a memory cell group N7L, a group of normal cells, and an R memory cell group R7L, a group of column redundancy cells, are provided and to the right, a memory cell group N7R, a group of normal cells, and an R memory cell group R7R, a group of column redundancy cells, are provided.
In the memory cell group N7L, multiple bit lines such as a pair of bit lines BL0LT and BL0LN, and another pair of bit lines BL1LT and BL1LN are provided, and multiple memory cells 8 are connected to each bit line. The memory cell group N7R, memory cell group R7L, and R7R have the same configuration.
The memory cell 8 is comprised of a cell capacitor and cell transistor formed with NMOS transistors. One side electrode of the cell capacitor is connected to a capacitor plate to which a voltage VP is supplied, and the other side electrode of the cell capacitor is connected to one of electrodes of the cell transistor. Furthermore, the other electrode of the cell transistor is connected to a bit line and the gate is connected to a word line.
A sense amplifier circuit 60 comprises equalizer circuits 1L and 1R on its left and right, shared switches 2L and 2R, an NMOS sense circuit 3, a PMOS sense circuit 4, and an IO switch 5, and controls the two bit line pairs, the bit line pair BL0LT and BL0LN on the left and the bit line pair BL0RT and BL0RN on the right. Sense amplifier circuits 61, 62, 63, . . . and R60, R61 have the same circuit configuration.
The equalizer circuit 1L comprises three NMOS transistors: an NMOS transistor whose electrode (either the source or drain electrode) is connected to the bit line BL0LT and other electrode (either the source or drain electrode) is connected to the bit line BL0LN, an NMOS transistor whose electrode is connected to the bit lineBL0LT and other electrode is connected to a bit line precharge power supply VHB, and an NMOS transistor whose electrode is connected to the bit line BL0LN and other electrode is connected to the a bit line precharge power supply VHB, and, to the gates of these three NMOS transistors, a control signal EQL is connected in common. When the control signal EQL is brought to a high level, the NMOS transistors of the equalizer circuit 1L are turned on and the bit lines BL0LT and BL0LN are precharged to the precharge power supply VHB. Like the equalizer circuit 1L, the equalizer circuit 1R comprises three NMOS transistors and a control signal EQR is connected in common to the gates of the three NMOS transistors.
The shared switch 2L comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the bit line BL0LT and other electrode is connected to a sense amplifier circuit node SL0T, and an NMOS transistor whose electrode is connected to the bit line BL0LN and other electrode is connected to a sense amplifier circuit node SL0N, and a control signal SHL is connected in common to the gates of these two NMOS transistors. A shared switch 2R on the right has the same circuit configuration and a control signal SHR is connected in common to the gates of its two NMOS transistors. When each of the control signals SHL and SHR is brought to a high level, each of the shared switches 2L and 2R is turned on, the bit line pair BL0LT and BL0LN on the left and the bit line pair BL0RT and BL0RN on the right become electrically connected to the sense circuits (the NMOS sense circuit 3 and PMOS sense circuit 4).
The NMOS sense circuit 3 comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T, other electrode is connected to a sense signal SAN and gate is connected to the sense amplifier circuit node SL0N, and an NMOS transistor whose electrode is connected to the SL0N, other electrode is connected to the SAN and gate is connected to the SL0T.
The PMOS sense circuit 4 comprises two PMOS transistors: an PMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T, other electrode is connected to a sense signal SAP and gate is connected to the sense amplifier circuit node SL0N, and an PMOS transistor whose electrode is connected to the node SL0N, other electrode is connected to the SAP and gate is connected to the SL0T.
The IO switch 5 comprises two NMOS transistors: an NMOS transistor whose electrode is connected to the SL0T, other electrode is connected to one of multiple IO lines and gate is connected to the row selecting signal line YSW0, and an NMOS transistor whose electrode is connected to the SL0N, other electrode is connected to another line of the multiple IO lines and gate is connected to the row selecting signal line YSW0.
In the configuration shown in FIG. 6, one row selecting signal line controls two sense amplifier circuits. In other words, the row selecting signal line YSW0 is inputted into the sense amplifier circuit 60 and a sense amplifier circuit 61, and into the gates of 4 NMOS transistors within the IO switch circuit. In this case, four IO lines are provided, and the other electrodes of the four NMOS transistors, which constitute the IO switch circuit and have the common row selecting signal line connected to its gates, are connected to separate IO lines.
With this example of a circuit configuration, when the row selecting signal line YSW0 is activated according to the address inputted externally, two sense amplifier circuits, the sense amplifier circuit 60 and sense amplifier circuit 61, can be written or read simultaneously.
As another example, there is a case where one row selecting signal line is inputted into one sense amplifier circuit. In this case, two IO lines are provided and by activating one row selecting signal line, the write or read operation of one sense amplifier circuit will start.
As a further example, there is a case where one row selecting signal line is inputted into four sense amplifier circuits, and in this case, eight IO lines are provided, and by activating one row selecting signal line, four sense amplifier circuits can be written or read simultaneously.
When a write/read fault occurs in a cell within the memory cell group N7L, which is a normal cell group on the left of the sense amplifier shown in FIG. 6, it is replaced with a redundant cell. For example, if a write/read fault occurs in a memory cell connected to the bit line BL0LN, a memory cell group 10 connected to 2 pairs of bit lines BL0LT, BL0LN and BL1LT, BL1LN, a total of four bit lines, is replaced with the column redundancy cell group R7L as a set.
In other words, a memory cell group controlled commonly by the row selecting signal line YSW0 and within the memory cell group N7L is replaced as a set. It is because of the necessity to replace sense amplifier circuits, which is written or read by one selecting signal line, as a set.
In the case where one row selecting signal line is inputted into one sense amplifier circuit, a pair of bit lines is replaced as a set.
Furthermore, in the case where one row selecting signal line is inputted into four sense amplifier circuits, eight bit lines are replaced as a set.
Furthermore, only one row selecting signal line RYSW for the column redundancy cells is shown in FIGS. 1 and 6, however, there is a case where multiple row selecting signal lines for the column redundancy cells are provided so that multiple faults can be relieved.
The shared sense amplifier shown in FIG. 6 is constituted such that the memory cell group 10, which corresponds to the row selecting signal line YSW0, is replaced by the column redundancy cells R7L of the row selecting signal line RYSW on the left side, and a memory cell group 11, which corresponds to the row selecting signal line YSW1, is replaced by the column redundancy cells R7R on the right side. In other words, this is a method in which a memory plate on one side of the shared sense amplifier and one on the other side are divided into different column replacement segments. In the present description, “column replacement segment” is a unit of memory cell group with the same group to replace in the column redundancy.
With a small layout area of column redundancy cells, the can be improved by having separate column replacement segments rather than having a common column replacement segment for the both sides of the shared sense amplifier.
In FIG. 1, let's assume that there are L number of the row selecting signal lines RYSW for the column redundancy cells on column number 0. If the left and right sides of all shared sense amplifiers have one common column replacement segment, the big region covered by M+1 number of memory cell groups, which corresponds to column number 0 and row numbers 0 through M, becomes one column replacement segment. In this case, up to L number of faults within this big region of column replacement segment can be relieved, however, if L+1 number of faults occur, it cannot be relieved.
In order to relieve L+1 number of faults, L+1 number of the row selecting signal lines RYSW for the column redundancy cells of column number 0 are needed, and as a result, the layout area of the column redundancy cells will increase.
On the other hand, in the case where the left and right sides of all shared sense amplifiers have separate column replacement segments, each memory cell group N7 on column number 0, but a different row number, becomes a small separate column replacement segment. In this case, up to L number of faults within the each small column replacement segment can be relieved.
Therefore, if the same amount of faults occur in each of the column replacement segments, a maximum of L×(M+1) number of faults can be relieved within the big region covered by M+1 number of memory cell groups that correspond to column number 0 and row numbers 0 through M.
As described above, with the same amount of the row selecting signal lines for the column redundancy cells, the smaller the column replacement segment, the more faults can be relieved.
Further, when trying to relieve the same fault density, the smaller the column replacement segment, the fewer row selecting signal lines for the column redundancy cells is needed, and as a result, a small layout area of the column redundancy cells can be achieved.
Also, not all shared sense amplifiers have memory cell groups on the both sides assigned to different column replacement segments. In general, a configuration where several memory cell groups are assigned to one column replacement segment is commonly used.
For example, in FIG. 1, the two memory cell groups on column number 0 and row numbers 0 and 1 are assigned to one column replacement segment, and the memory cell groups on row numbers 2 and 3 are assigned to one column replacement segment. This means every two memory cell groups are assigned to one column replacement segment. This is because of the following problem: The smaller column replacement segment results in more sets of the column replacement. It means more fuses for programming are needed, and as a result, the layout area of the fuses increases.
In FIG. 6, the PMOS sense circuit 4 is provided in an N-well region. All the circuits shown in FIG. 6, except for the PMOS sense circuit 4, are provided in a P-well region. On the borderline between the N-well and P-well, an wasted region with a width of several um (micrometers) called “well isolation area” where no transistor can be provided occurs. Therefore, in order to decrease the layout area, all the N-well regions of the PMOS sense circuits 4 within the sense amplifier circuits 60, 61, 62, 63, . . . , and R60 and R61 are connected, and the N-well regions are provided zonally in the vertical direction of the drawing.
FIG. 7 is a timing chart showing an example of the general operation of the shared sense amplifier shown in FIG. 6. As power-supply voltages, a boost level VPP, an array voltage VAR, the bit line precharge power supply VHB, and a reference voltage GND are supplied. The level of the VHB is set to the level of ½×VAR level. Further, the level of a capacitor plate voltage VP supplied in FIG. 6 is generally the same fixed level as the VHB.
Also, in the example shown in FIG. 7, the level of the word line during the equalizing period is at the GND potential, however, with recent DRAM's, there are cases where a power supply VKK with a negative potential, lower than the GND potential, is provided, and the level of the word line during the equalizing period is set to the VKK. Further, in a conventional DRAM, a negative potential VBB, lower than the GND potential, is supplied as the potential of the P-well shown in FIG. 6.
During the equalizing period before timing T1, the control signals EQL and EQR is set to the VPP level (the EQR is shown in the drawing). Because of this, the equalizer circuits 1L and 1R are turned on, a short circuit between the pairs of the bit line pair BL0LT, BL0LN and bit line pair BL0RT, BL0RN occurs (an equalizing operation is performed), and the bit line precharge power supply VHB is supplied. The control signals SHL and SHR are set to the VPP level, and the shared switch circuits 2L and 2R are turned on. Because of this, the sense amplifier circuit nodes SL0T, SL0N etc. are set to the VHB level, the same level as the bit line pair BL0LT, BL0LN and bit line pair BL0RT, BL0RN.
Let's assume that the word line within the memory cell group N7L on the left of FIG. 6 is activated at the timing of T1. In this case, the control signal SHR is set to the GND level, and the sense amplifier circuit nodes SL0T and SL0N, and the bit lines BL0RT and BL0RN are disconnected respectively. Also, the control signal EQL is set to the GND level, the equalizer circuit 1L is turned off, and the equalizing operation of the bit line pair BL0LT, BL0LN is stopped.
The control signal EQR is always kept at the VPP level during the period shown in FIG. 7, and it continues to supply the VHB level to the bit line pairs BL0RT, BL0RN, etc. The control signal SHL (not shown in the drawing) is also always kept at the VPP level during the period shown in FIG. 7, and it keeps the bit lines BL0RT and BL0RN, and the sense amplifier circuit nodes SL0T and SL0N connected electrically.
Next, the electric charge of the cell capacitor of the memory cells 8 connected to a word line, which has been elevated to the VPP level and within the memory cell group N7L, is outputted to the bit line BL0LT or BL0LN. In the example shown in FIG. 7, a high level is outputted to the bit line BL0LT, and this output is transferred to the sense amplifier circuit nodes SL0T and SL0N through the shared switch circuit 2L, and there is a slight difference potential between the SL0T and SL0N. After this, a sense operation is performed, setting the sense signal SAN at the GND level and the sense signal SAP at the VAR level.
During the sense operation, each one of the two transistors of the NMOS sense circuit 3 and PMOS sense circuit 4 corresponds to the slight difference potential between the SL0T and SL0N, and is turned on to amplify this difference potential. The SL0T is sensed at the VAR level and the SL0N at the GND level.
Since the NMOS sense circuit 3 and PMOS sense circuit 4 are designed such that they amplify the slight difference potential normally when the levels of the SL0T and SL0N are close to the VHB level, they cannot amplify normally when the levels of the SL0T and SL0N are not close to the VHB for some reason.
Furthermore, the levels of the nodes SL0T and SL0N within the sense amplifier circuits are transferred to the bit lines BL0LT and BL0LN respectively through the shared switch circuit 2L, and the bit lines BL0LT is set to the VAR level and the BL0LN at the GND level.
Furthermore, although not shown in the drawing, if the level of the row selecting signal line YSW0 is increased from the GND to the VAR level when in the state described above, an IO switch circuit 5 is turned on, and the IO line and the sense amplifier circuit nodes SL0T and SL0N are electrically connected. Because of this, the sense amplifier circuit can be written or read through the IO line, and a write/read operation is performed on the memory cells 8 connected to a selected word line.
The equalizing operation is performed as follows: first, the word line is set to the GND level. Then, by setting the control signal EQL at the VPP level at the timing of T2, the equalizer circuit 1L is turned on and the bit line pair BL0LT, BL0LN is equalized to the VHB level.
During this equalizing operation, even if the bit line precharge power supply VHB hardly supplies any level, the bit line pair BL0LT, BL0LN can be equalized to the VHB level. While being active, the BL0LT is at the VAR level and the BL0LN at the GND level, and the BL0LT and BL0LN have nearly the same wiring capacitance. Therefore, during the equalizing operation, they can be set to the level of ½×the VAR level, i.e., the VHB level by a charge reallocation of each bit line.
Also, the control signal SHR is set to the VPP level around the timing of T2, and the shared switch circuit 2L, 2R is turned on. By doing this, the nodes SL0T and SL0N within the sense amplifier circuit are connected to the bit line BL0LT, BL0LN, and BL0RT, BL0RN respectively through the shared switch circuit 2L and 2R, and as a result, they are set to the VHB level. Since the wiring capacities of the sense amplifier circuit nodes SL0T and SL0N are small, the nodes SL0T and SL0N follow the potential change of the bit lines BL0LT, BL0LN, and BL0RT at a high speed, and reach the VHB level even if the on-resistance of the shared switch circuits 2L and 2R is high.
The period between the timing of T1, when the control signal EQL is set to the GND level, and the timing of T2, when it is set to the VPP level, is an active period, and the period during which the control signal EQL is set to the VPP level is an equalizing period. Further, a case where all the sense amplifiers within the DRAM are in the equalizing period is called “standby.”
In the recent DRAM specifications, there has been the stronger demand for an increase in speed by shortening the equalizing period. Therefore, after the control signals EQL and SHR reaches the VPP level, it is preferred that the bit lines BL0LT and BL0LN, and the sense amplifier circuit nodes SL0T and SL0N reach the VHB level sooner than later.
In the circuit configuration shown in FIG. 6, for the purpose of decreasing the layout area of the sense amplifier circuit, it is possible to have a circuit configuration where there is only one equalizer circuit, instead of having the two equalizer circuits (1L and 1R), connected to the sense amplifier circuit nodes SL0T and SL0N.
FIG. 8 is a drawing showing a circuit configuration of such a shared sense amplifier. Only the part controlled by the row selecting signal line YSW0 is extracted from the configuration shown in FIG. 6, and shown in FIG. 8.
The difference between the configurations shown in FIGS. 6 and 8 is the fact that the equalizer circuits 1L and 1R in FIG. 6 are omitted in FIG. 8 and an equalizer circuit 1 is provided instead.
The equalizer circuit 1 comprises an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T and other electrode is connected to the SL0N, an NMOS transistor whose electrode is connected to the sense amplifier circuit node SL0T and other electrode is connected to the VHB, and an NMOS transistor whose electrode is connected to the VHB and other electrode is connected to the sense amplifier circuit node SL0N, and a control signal EQ is connected to the gates of these three NMOS transistors.
The operation of the configuration in FIG. 8 is the same as the one in FIG. 7 except for the fact that the control signal EQL is replaced by the control signal EQ. The equalizing operation is performed when the control signal EQ reaches the VPP level at the timing of T2 and the equalizer circuit 1 is turned on. At that time, the short circuit between the bit lines BL0LT and BL0LN occurs through the shared switch circuit 2L and the equalizer circuit 1. The wiring capacities of the bit lines BL0LT, BL0LN, etc. are several times the amount of the wiring capacities of the sense amplifier circuit nodes SL0T, SL0N, etc. Therefore, the on-resistance of the shared switch circuit 2L needs to be low enough in order to have the bit line pairs BL0LT, BL0LN equalized at a high speed and reach the VHB level.
In other words, the transistor size of the shared switch circuit needs to be enlarged. As a result, in order to deal with the demand for speeding up the equalizing period, the layout area of the configuration shown in FIG. 8 ends up bigger than the one of the configuration shown in FIG. 6.
Further, in the configuration shown in FIG. 8, since the shared switch circuit 2R is turned off during the active period, the bit lines BL0RT, BL0RN, etc. are floated. Depending on the specifications of the DRAM, there are cases where the active period becomes very long. If a fault where a minute leakage current flows in the bit lines BL0RT or BL0RN occurs at this time, the level will greatly deviate from the VHB and the bit line will have a write/read fault. Therefore, with the configuration shown in FIG. 8, the manufacturing yield will be reduced compared to the circuit configuration shown in FIG. 6.
Because of the problem described above, the equalizer circuits of the recent DRAM's should be provided discretely for the bit line pairs on the left and right sides of the shared sense amplifier as in the example shown in FIG. 6.
In the configuration of a conventional DRAM shown in FIG. 6, if a short-circuit defect between a bit line and word line occurs, it will result in a write/read fault. For example, if a short-circuit defect 15 between the bit line BL0LT and the word line occurs in FIG. 6, memory cells connected to the bit line pair BL0LN, BL0LT will have a write/read fault.
When this fault occurs, the memory cell group 10 will be replaced by the column redundancy memory cell group R7L and made non-defective in terms of write/read operation.
However, even after the replacement, since the VHB level is supplied to the bit line BL0LT and the GND level (or the VKK level) is supplied to the word line during the equalizing period, a leakage current will flow and the standby current will increase.
Further, the resistance value of the short-circuit defect can be anywhere from a low resistance of several ohms to high resistance of more than several hundreds mOhms. According to our estimate, when a short-circuit defect between a bit line and word line has a low resistance of several ohms, a leakage current at a short-circuit defect area will be approximately 200 μA (microampere).
Since the standby current specification of a conventional DRAM is as small as several mA (milliampere), just by having 10 short-circuit defects with a low resistance between a bit line and word line, it becomes a leakage current fault, resulting in a manufacturing yield reduction.
Therefore, means for reducing leakage current even when a short-circuit defect occurs between a bit line and word line is desired, and several methods have been proposed.
As means for reducing the leakage current caused by a short-circuit defect between a bit line and word line, a method of providing a current-limiting element between a equalizer circuit and bit line precharge power supply VHB is published in Patent Document 1.
FIG. 9 is a drawing showing the configuration of the shared sense amplifier circuit described in Patent Document 1. In FIG. 9, only the part controlled by the row selecting signal line YSW0 is extracted from FIG. 6. The difference between FIG. 6 and FIG. 9 is the fact that the current-limiting elements 9 are provided between the equalizer circuits 1L and 1R and the VHBs in FIG. 9.
Furthermore, as concrete circuit configuration examples, the configurations shown in FIG. 10A, FIG. 10B, FIG. 10C, and FIG. 10D are published in Patent Document 1.
In the circuit configuration shown in FIG. 10A, an NMOS transistor is used as a current-limiting element 9, and one electrode of the NMOS transistor is connected to the VHB, and the other electrode is connected to a node A. Further, its gate is connected to a constant voltage level V1, and the voltage of the V1 is set to a level with which an appropriate current can be flowed. Also, the node A is supplied to the equalizer circuit 1L.
In the circuit configuration shown in FIG. 10B, a PMOS transistor is used as a current-limiting element 9. A gate voltage V1 of the PMOS transistor is set to a level with which a proper current can be flowed.
In the circuit configuration shown in FIG. 10C, a depression-type NMOS transistor is used as a current-limiting element 9. The gate of the depression-type NMOS transistor is connected to the node A. The threshold voltage of the depression-type NMOS transistor is set to a value with which a proper current can be flowed by adjusting the impurity doping level.
In the circuit configuration shown in FIG. 10D, a register is used as a current-limiting element 9. The resistance value of the register is set to a value with which a proper current can be flowed.
Furthermore, in Patent Document 2 and Non-Patent Document 1, a configuration where one current-limiting element is shared by multiple equalizer circuits controlling multiple bit line pairs, which are to be replaced by a column redundancy memory cell group simultaneously as a set is published. By doing so, the number of the current-limiting elements can be reduced and the increase in layout area can be restrained.
FIG. 11 is a drawing showing the circuit configuration of a shared sense amplifier based on such a principle published in Non-Patent Document 1 as FIG. 8.
The differences between FIGS. 11 and 6 are the facts that one current limiting element 9 is provided for two equalizer circuits 1L respectively connected to the bit line pair BL0LT, BL0LN and bit line pair BL1LT, BL1LN, which are to be replaced by a column redundancy memory cell group as a set, one electrode of the current-limiting element 9 is connected to the bit line precharge power supply VHB while the other electrode is connected to a node A0L, and the node A0L is supplied to the two equalizer circuit 1L.
Similarly, one current-limiting element 9 is shared by two equalizer circuits 1R connected to 2 bit line pairs, which are to be replaced by a column redundancy memory cell group as another set. The same goes for the areas controlled by the column redundancy row selecting signal line RYSW. In the example of Non-Patent Document 1, a depression-type NMOS transistor is used as a current-limiting element 9, however, it is possible to use it as a different type of current-limiting element.
FIG. 12A shows the means for reducing the leakage current caused by a short-circuit defect between a bit line and word line, published in Patent Document 2, and the drawing shows only the part on column number 0 extracted from the DRAM array configuration shown in FIG. 1. Furthermore, FIG. 12B is an example of a circuit configuration where this method is applied to a shared sense amplifier circuit, and only the part controlled by the row selecting signal line YSW0 is extracted from FIG. 6.
What is different about FIG. 12A from FIG. 1 is the fact that signal lines A0, A1, . . . RA are wired so that each of them is parallel to each of row selecting signal lines YSW0, YSW1, . . . RYSW, each of the signal lines A0, A1, . . . RA is connected to each of the sense amplifier 6, and the signal lines A0, A1, . . . RA and the bit line precharge power supply VHB are connected through each fuse. As a current-limiting element 9, a fuse is used.
What is different about FIG. 12B from FIG. 6 is the fact that, instead of the VHB, the signal line A0 is connected to the four equalizer circuits within the sense amplifier circuits 60 and 61 controlled by the row selecting signal line YSW0.
In the configuration published in Patent Document 2 shown FIGS. 12A and 12B, when the short-circuit defect 15 between the bit line and word line occurs, the row selecting signal line YSW0, which has become faulty, is replaced by the column redundancy row selecting signal line RYSW and the fuse of the corresponding signal line A0 is cut off so that the leakage current is shut off.
[Patent Document 1]
Japanese Patent Kokai Publication No. 8-263983 (Claim 9, FIG. 3, FIG. 4, FIG. 5)
[Patent Document 2]
Japanese Patent Kokai Publication No. 7-334987 (Paragraph [0035], [0036], FIG. 1, FIG. 2, FIG. 3)
[Non-Patent Document 1]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 4, APRIL 1996, P558˜P566, Fault-Tolerant Designs for 256 Mb DRAM, Toshiaki Kirihata, et al., Publication Date: NO. 4, April 1996, P563, FIG. 8
The entire disclosure of these documents are incorporated herein by reference thereto.
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