A silicon oxide film has stability on processes and excellent insulation characteristic and is used as a gate insulating or dielectric film of a MOSFET. The thinner structure of the gate dielectric film is progressing with the miniaturization of a semiconductor device in recent years. It becomes necessary from the viewpoint of the scaling law in the semiconductor device that the gate length is equal to or less than 100 nm and that the thickness of the silicon oxide film as the gate dielectric film is equal to or less than 1.5 nm. However, in such a thinner dielectric film, tunnel current flowing through the insulating film in application of a gate bias can not be ignored to source/drain current. As a result, it becomes a big problem in superior performance and low power consumption in the MOSFET.
For this reason, the studies and developments are carried forward to decrease an effective thickness of the gate dielectric film and to suppress the tunnel current into a permissible value in system design. In one method, by adding nitrogen into the silicon oxide film, the dielectric constant is increased compared with a pure silicon oxide film. In this way, the film thickness of the gate dielectric film is decreased effectively (electrically) without decreasing the film thickness physically. However, there is a limit in this method in that the high dielectric constant is achieved by adding the nitrogen to the silicon oxide film. Also it is reported that the carrier mobility decreases due to electrical defects at the interface.
Moreover, for technique in the next generation that the miniaturization of the device further progresses, it is tried to use a thin film of metal oxides having a relative dielectric constant equal to or more than 10 or a silicate thin film of composite material of the above material and silicon as the gate dielectric film in place of the silicon oxide film. As such high relative dielectric constant material, Al2O3, ZrO2, and HfO2 oxide of the rare earth element such as Y2O3, and oxide of the lanthanoid system rare earth element such as La2O3 are studied as candidacy materials. This is on the basis of that the thicker gate dielectric film can be achieved to prevent the tunnel current while keeping the inversion capacitance in accordance with the scaling law, even though the gate length is made small, if these high relative dielectric constant films are used. It should be noted that when it is supposed that the gate dielectric film is a silicon oxide film regardless of the kind of material of the gate insulator, the film thickness of the insulating film calculated from the gate capacitance is called an equivalent oxide thickness (EOT). That is, when the relative dielectric constants of the dielectric film and the silicon oxide film are ∈h and ∈o respectively, and the thickness of the dielectric film is dh, the equivalent oxide thickness de is obtained from the following equation.de=dh(∈o/∈h)It shows that a thick insulating film can be equivalent to a thin silicon oxide film if the material has a dielectric constant ∈h large compared with ∈o. For example, it is supposed that an insulating film with a large relative dielectric constant of ∈h=39 is used because the relative dielectric constant ∈o of the silicon oxide film is about 3.9. In this case, even if the dielectric film has the physical thickness of 15 nm, the equivalent oxide thickness is 1.5 nm so that it is possible to decrease the tunnel current sharply.
On the other hand, in case of development of the semiconductor memory, severe conditions are imposed on the structure of a capacitance element to hold data as electric charge from the viewpoint of the reduction of the memory cell area. The technique to hold a sufficient amount of electric charge is required to a smaller cell area. In order to meet these requests, a technique is developed to increase the dielectric constant of the dielectric film of the capacitance element in addition to a technique to increase an element area by forming a minute unevenness structure to the capacitance element.
As described above, in the development of the next generation MOSFET, it is considered to adopt high dielectric constant material as the gate insulator, and the above-mentioned metal oxide film and the silicate film are expected as the high dielectric constant film. As characteristics of these two candidate material films, the metal oxide film generally has a high dielectric constant and can reduce the equivalent oxide thickness dramatically.
However, these high dielectric constant films crystallize (take the polycrystalline state) in a relatively low temperature region. Therefore, it is pointed out that the boundaries among the crystals (the crystal grain boundaries) are generated to cause the degradation of the insulation characteristic in these grain boundaries and the non-uniformity of the film thickness through crystallization. For this reason, a technical problem on application is in the securing of thermal stability as the gate dielectric film.
On the other hand, the dielectric constant of silicate material as ternary system material of metal oxide and silicon is lower than the metal oxide material but higher than the silicon oxide film. Also, the above-mentioned metal oxide material is easy to crystallize, whereas silicate material keeps an amorphous state in a high temperature range, and is not accompanied by the thermal change of the structure (characteristic). Therefore, the silicate material has predominance like the conventional silicon oxide film. Moreover, a film composition can be set in a wide range. It is reported that the dielectric constant increases by adding the metal element of % order to the silicon oxide film.
Also, in the application to the device for the high dielectric constant film, the electrical interface characteristics with the silicon substrate and the gate electrode material are important. Generally, the electrical interface characteristics between the metal oxide film and the silicon substrate are poor compared with those of the silicon oxide film and the silicon substrate and an interface defect density between the metal oxide and the silicon substrate is equal to or more than that of the silicon oxide film and the silicon substrate by one order. As the means of improving the electrical interface characteristics, the effectiveness of the metal silicate is pointed out.
In this way, attention is focused on the metal silicate material as the influential candidate material of the high dielectric constant gate dielectric film in the following generation. However, in application to the MOSFET, the following problems exist.
First, the electrical interface characteristics between the silicon substrate and the gate electrode material needs to be more improved. For this purpose, it could be considered that a silicon composition in the metal silicate is increased to approximate to the interface structure of the silicon oxide film. On the other hand, it is known that the crystallization temperature of the metal silicate decreases as the metal composition becomes high. Therefore, in order to achieve an excellent thermal stability, it is necessary to increase the silicon composition. However, the dielectric constant decreases with the increase of the silicon composition in the silicate. Thus, the high dielectric constant of a gate dielectric film and the thermal stability have a trade-off relation each other. That is, the metal silicate material has various excellent characteristics but is in the trade-off relation with setting of the film composition, as described above. Therefore, the proposal of an optimal metal silicate material or the gate dielectric film structure in case of device application is demanded.
In addition to the above-mentioned pointing-out, another problem of the high dielectric constant gate insulating film is a band gap of insulator material. Generally, there is a negative correlation between the dielectric constant and the band gap of the high dielectric constant material, and the high dielectric constant material has a narrow band gap. Therefore, when the valence band offset and the conduction band offset are small at the interface with the silicon substrate, carriers are thermally excited on the side of the silicon substrate or a gate electrode and more electric current flows through the gate dielectric film.
The above technical problems of the gate dielectric film in the case of the application to MOSFET are essentially same with respect to the dielectric film of a capacitor cell, although the device generation is different. The proposal of an insulating film structure with a high dielectric constant and thermal stability are demanded and excellent electrical interface characteristics are also demanded.
In conjunction with the above description, a high dielectric constant film and a manufacturing method for the same are disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 5-275646). In this reference, the high dielectric constant film consists of the oxide of Ta and Hf as high dielectric constant materials and has a composition in the range that the mole ratio of elements is shown in the following equation.0.01≦Hf/(Ta+Hf)≦0.4A substrate is located in a vacuum chamber, source gases are introduced into the vacuum chamber, and energy is applied from outside to excite the source gases. Thus, the high dielectric constant film is vapor-deposited on the substrate. Ta source gas, Hf source gas, and oxygen containing gas are used, and a composition is controlled such that the mole ratios of elements of the high dielectric constant film are in the following range.0.01≦Hf/(Ta+Hf)≦0.4
Also, a ferroelectric capacitor is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-294432). In this conventional example, the ferroelectric capacitor has the structure in which a ferroelectric film is put between a semiconductor substrate and an electrode. A reaction and/or diffusion barrier film are provided between the semiconductor substrate and the ferroelectric film or between the ferroelectric film and the electrode. The barrier film is formed of fluoride of at least one alkaline earth metal element selected from the group consisting of calcium, strontium and barium.
Also, a high dielectric constant silicate gate dielectric is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-135774). In this conventional example, a method of manufacturing an electric field effect device on an integrated circuit includes a step of providing a single crystal silicon substrate, a step of forming a metal silicate dielectric layer on the substrate and a step of forming a conductive gate on the metal silicate dielectric layer. When the metal silicate dielectric layer is formed, the substrate is cleaned such that pure Si is exposed on the substrate and a first metal film is deposited on the Si surface. The silicide film of first metal is formed on the substrate by annealing the substrate in an inactive environment, and a metal silicate dielectric layer is formed by oxidizing the silicide layer of the first metal. Or, when the metal silicate dielectric layer is formed, first metal and silicon are deposited on the substrate in an oxidant environment to form a layer oxidized partially at least, and then an annealing is carried out in the oxidant environment. Or, when the metal silicate dielectric layer is formed, the substrate is cleaned such that the pure Si is exposed on the substrate and a metal silicate having oxygen vacancies is deposited on the Si surface, and then an annealing is carried out to the metal silicate in the oxygen environment to form a high-quality metal silicate dielectric layer.
Also, in this conventional example, a field effect device is composed of a single crystal silicon semiconductor channel region, and a metal silicate gate dielectric layer formed on the channel area. The metal silicate is selected from the group consisting of zirconium silicate, barium silicate, cerium silicate, zinc silicate, thorium silicate, bismuth silicate, hafnium silicate, tantalum silicate and those combinations. A conductive gate is provided to cover the gate dielectric layer.
Also, insulator material is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-186523). In this reference, the insulator has crystal material which contains Ti and in which an atomic concentration ratio Bi/Ti in Bi2SiO5 is equal to or more than 3. The insulator film is formed by heating and vaporizing raw materials which consist of a metal compound containing Bi and a metal compound containing Ti, and by supplying these vaporized gases onto a Si substrate which is kept to a predetermined temperature, at the same time under predetermined pressures with an inactive carrier gas and an oxygen gas.
Also, a method of forming a semiconductor device and a dielectric film is disclosed in Japanese Laid Open Patent Application (JP-P 2000-323591). In this conventional example, a single crystal silicon layer is epitaxially grown on a silicon substrate. Bi, Si and oxygen are diffused to form a bismuth silicate film by introducing an oxygen gas and a gas obtained by vaporizing alt-tri-bismuth into a reaction chamber, and by keeping the substrate at a high temperature. Moreover, a BIT film as a ferroelectric substance film is formed on the bismuth silicate film. After that, after a polysilicon film is deposited on the substrate, the polysilicon film, the BIT film and the bismuth silicate film are patterned in order. Thus, a gate electrode, a storage section and a buffer layer are formed. Deterioration of the characteristic of MFISFET caused by the erosion of a channel region can be prevented and the structure near the boundary between the buffer layer and the storage section becomes good.
USPTO Backgrounds
USPTO Backgrounds