When the circuit of a traditional display panel is designed, a periphery wire termed as a shorting bar is usually arranged circumferentially around the panel outside of a display area, with gate lines guided to the periphery wire according to whether they are odd-numbered or even-numbered, respectively. That is, odd-numbered gate lines on the panel are all connected to one another outside the display area, and the even-numbered gate lines on the panel are all connected to one another outside the display area also. With such a design, different electric signals can be applied to the odd-numbered and even-numbered gate lines respectively to detect whether a short circuit or an open circuit exists in the display panel during a detection step in the TFT manufacturing procedure. Moreover, different data signals can be additionally used to detect other types of undesirable conditions. The shorting bar can be disconnected or removed after the detection, and will not affect normal display of a final product.
In order to eliminate the phenomenon of color shift occurring in a vertical alignment liquid crystal display panel viewed at a large viewing angle, a pixel can be designed via a charge sharing manner. FIG. 1 schematically shows the structure of a circuit of a charge sharing array substrate having the shorting bar in the prior art. As indicated in FIG. 1, a signal applied to a charge gate line located in an (N+2)th row is used to control activation and deactivation of a share gate line located in an Nth row. Where a short circuit occurs between a charge gate line and the share gate line that are located in the Nth row, because the share gate line located in the Nth row and the charge gate line located in the subsequent (N+2)th row are connected to each other, and the charge gate lines that are located in the Nth row and the (N+2)th row are both odd-numbered or both even-numbered in sequence, the above detection method of guiding the odd-numbered and even-numbered rows respectively to the shorting bar cannot be used to detect the short circuit defect during the TFT procedure. This can lead to use of cell lighting or even final product testing, which would cause unsatisfactory horizontal gate lines and reduce yield rates.
As shown in FIG. 2, an array substrate provided with three detecting circuits in a shorting bar area is further provided in the prior art. Detecting circuits G1, G2, and G3 are respectively connected to three successive rows of charge gate lines that are located in the display area, and detecting signals are successively provided to the three detecting circuits. This solution can be used to detect a short circuit defect possibly existing between a charge gate line and a share gate line that are located in one and a same row, whereby a more complicated detection mode has to be performed through a longer time period. Particularly, in mass production, because various procedures have become gradually stable, such a circuit defect will have a rather low probability of occurring. Consequently, if this solution is still to be used, the efficiency of detection would be low and the production capacity would be affected.
USPTO Backgrounds
USPTO Backgrounds