1. Field of the Invention
The present invention relates to a video RAM, and more particularly to a video RAM which can be freely selected during a manufacturing process of the chip to operate as a half SAM device or as a full SAM device.
2. Background of Related Art
Recently, with the rapid spread in the use of portable computers such as note book computers, video RAMS are being more widely used. Video RAMS are a dual port memory and therefore have both the function of a dynamic RAM (random access memory) and the function of a SAM (serial access memory), both functions operating asynchronously. Generally, the SAM has a very high data transfer rate. The dynamic RAM port is typically connected to a CPU of a computer system and the SAM port is typically connected to an external system such as a CRT (cathode ray tube) and/or a video camera, and as such has wide applications for various systems. In order to perform a variety of operational functions increasingly required by video RAMS, a higher data storage capacity is required. This necessitates an increase in the density of the video RAM.
According to the conventional data transfer method, a video RAM device either contains a full SAM or a half SAM. For instance, the video RAM identified as .mu.PD48244S and manufactured by NEC Co. employs the full SAM, while the video RAM TMS55160 manufactured by Texas Instrument Company employs the half SAM. Furthermore, according to the type of SAM, a controller for controlling the SAM is also classified into a full SAM controller for controlling the full SAM or a half SAM controller for controlling the half SAM. The specific structures of the conventional full SAM and half SAM are briefly mentioned hereinbelow. In the following description, the column size of the RAM is 512, and the length of the RAM cell addressed can be various conventional lengths, i.e. 1 bit, 8 bits or 16 bits. Furthermore, the column size of the full SAM is 512, and of the half SAM is 256. However, the description is aptly suitable for all sizes of memory. Furthermore, the RAM column address bit lines (or internal address bit lines) are represented as Ai (where i=0, 1, 2, . . . 8) and the SAM column address bit lines (or serial address bit lines) are represented as SSi (where i=0, 1, 2, . . . 8).
FIG. 1 is a schematic block diagram showing a structure of a conventional video RAM device having RAM 300 and a full SAM 302. In this structure, the full SAM is divided into two parts in response to an column address bit line A8. The leading 256 bits from 0 to 255 correspond to a lower SAM and the following 256 bits from 256 to 511 correspond to an upper SAM, and are individually addressable by an internal counter according to a combination of column address bit lines A0-A7. The lower and upper parts of the full SAM are alternatively selected in dependence upon the column address bit line A8. Thus, data in the lower and upper parts of the RAM can be respectively transferred to the lower and upper parts of the full SAM. Commonly, a data transfer operation from the RAM to the SAM is performed primarily by a read transfer operation and thereafter by a split read transfer operation. During the split read transfer operation, data stored in the lower part of the full SAM is output to an external device such as a CRT and data stored in the upper RAM is transferred to the upper part of the full SAM. For example, in accordance with the RAM address bit line A8, during an initial read transfer operation, either the lower part of the full SAM or the upper part of the full SAM is selected to which data is to be transferred to in the following split read transfer operation. If a serial address bit line SS8 of a logic low level or "0" level is generated from an internal counter (not shown) during the read transfer operation and thereafter the split read transfer operation is performed, the data stored in the lower part of the full SAM is output to the external devices and the data stored in the upper RAM is transferred to the upper part of the full SAM. In the meantime, if the serial address bit line SS8 is generated at a logic high level or "1" level by the internal counter, the data stored in the upper part of the full SAM is output to the external devices and the data stored in the lower RAM is transferred to the lower part of the full SAM during the split read transfer operation. Consequently, in the full SAM device since the number of data bits in the RAM is the same as the number of data bits of the SAM, the data stored in the full SAM device is transferred all at once during the data transfer operation. Such a full SAM is disclosed in a paper "A 256K Dual Port Memory" of ISSCC (published in 1985) .
FIG. 2 is a schematic block diagram showing a structure of a conventional video RAM device having RAM 300 and a half SAM 304. In this structure, the RAM associated with the half SAM is divided into two blocks B1 and B2, each block B1, B2 being equal in memory size to the SAM unlike the RAM of FIG. 1 which had two blocks which were each the size of only half of the full SAM. The respective blocks B1, B2 are divided again into upper and lower parts. Consequently, the RAM associated with the half SAM device is divided into four smaller blocks. In addition, the half SAM is divided into two parts in accordance with the address bit lines A0 to A6. The leading 128 bit addresses from 0 to 127 correspond to the lower part of the half SAM and the succeeding 128 bits from 128 to 255 correspond to the upper part of the half SAM. In summary, the RAM is divided into two blocks B1 and B2 according to the address bit line A8 and the respective blocks B1, B2 are divided again, according to the address bit line A7, into upper and lower parts for the transfer operation of the half SAM. At an initial read transfer operation, RAM address bit lines A7 and A8 select a given block in the RAM of which data is to be transferred to the lower or upper part of the half SAM in next cycle of the split read transfer operation. Address bit line A8 selects the block B1, B2 and address bit line A7 selects the upper or lower part of the respective block B1, B2. If the block B1 is selected by the RAM address bit line A8 being at a low logic level and when serial address bit line SS7 is at a low logic level by the internal counter, the data stored in block B1 of the RAM is transferred to the lower part of the half SAM. However, if the serial address bit line SS7 is at a high logic level, the data stored in block B1 of the RAM is transferred to the upper part of the half SAM. Similarly, if the block B2 is selected according to the RAM address bit line A8 at a high logic level and the serial address bit line SS7 is at a high logic level by the internal counter, the data stored in block B2 of the RAM is transferred to the upper part of the half SAM. In the next cycle, if the serial address bit line SS7 is at a low logic level, the data stored in block B2 of the RAM is transferred to the lower part of the half SAM. It is noted from the above description that in the full SAM device the RAM address bit line A8 is a "don't care" for addressing purposes and that the RAM address bit line A7 is used as an address input. On the contrary, however, in the half SAM device the RAM address bit line A8 is used as an address input and the RAM address bit line A7 is a "don't care" for addressing purposes.
Additionally, as described above, the conventional half SAM controller is not compatible with the full SAM device and conversely the conventional full SAM controller is not compatible with the half SAM device. Thus, a conventional half SAM device cannot be used together with a full SAM device in a same system comprising video RAM. Accordingly, there is a problem in that the video RAM must exclusively employ full SAM devices or half SAM devices, but not a combination of full SAM and half SAM devices. Thus, a manufacturer must design separate video RAM devices, one type having a full SAM and another type having a half SAM, since the addressing methods thereof are different from each other. The difference in conventional designs between video RAM devices employing full and half SAM's raises costs, design time and time required for manufacturing products using video RAM devices.
USPTO Backgrounds
USPTO Backgrounds