The present invention relates to a single-chip microcomputer to which a dynamic random access memory (called dynamic RAM or DRAM) may be connected directly.
Past publications about microcomputers to which a DRAM may be directly connected include Japanese Patent Laid-Open No. SHO/61-127056 (which corresponds to U.S. Pat. No. 4,792,891, issued on Dec. 20, 1988, assigned to Hitachi, Ltd.). The microcomputer disclosed in the above publication has a refresh address counter, a control signal generating circuit and a register. The refresh address counter generates refresh addresses. The control signal generating circuit generates strobe signals such as RAS* (row address strobe signal) and CAS* (column address strobe signal). The register is used to specify either a dynamic RAM or a static RAM is to be accessed. The address output format is varied depending on the content of the register. Thus not only the static RAM but also the dynamic RAM may be accessed and the dynamic RAM may be refreshed. The register is designed to specify the range of addresses in the dynamic RAM to be used and the memory capacity thereof, i.e., the number of bits constituting the address signals. Such settings make it possible to change to a certain extent the memory capacity of each DRAM to be used and the number of DRAM's that may be configured in a system. (In the description that follows, an asterisk attached to a signal name (e.g., RAS*, CAS*) indicates that the signal is an inverted signal.)
USPTO Backgrounds
USPTO Backgrounds