1. Field of the Invention
The present invention relates to a continuous-time sigma-delta modulator, and more particularly, to a sigma-delta modulator using low-jitter pulses.
2. Discussion of Related Art
A sigma-delta modulator may be composed of a discrete-time system or a continuous-time system.
The discrete-time system uses switched capacitor techniques by which signals are stored and transferred through capacitors. For example, an integrator and a digital-to-analog converter (DAC) are configured such that an input signal and a fed-back DAC signal are stored as charge in a capacitor in a sampling phase of a clock, and the sampled charge is transferred to an integrating capacitor in an integration phase.
The continuous-time system operates without an input signal sampling process. In the continuous-time system, a DAC transfers an analog current signal to an integrator in response to a clock signal.
Due to fewer requirements for design of an amplifier of the integrator than in the discrete-time system, a continuous-time system enables a sigma-delta modulator to operate at high speed under low power. Also, since the integrator does not perform sampling, the sigma-delta modulator basically has an anti-aliasing filtering function. Further, since an input terminal is coupled to a resistive element or a gate of a transistor, it is easy to design a preceding circuit block of the sigma-delta modulator when forming a system with the sigma-delta modulator.
However, the continuous-time sigma-delta modulator has a weak signal-to-noise ratio (SNR) that is highly dependent on jitter in a clock signal applied to its internal DAC.
If a pulse width of a clock signal applied to the DAC is irregular due to jitter, it has the same effect as adding noise to the DAC signal. That is, noise is further generated as shown by the dotted line from the frequency response of the sigma-delta modulator. Accordingly, signal-to-noise ratio (SNR) performance of the sigma-delta modulator is deteriorated.
USPTO Backgrounds
USPTO Backgrounds