1. Field
Exemplary embodiments of the present invention relate to a memory device, and more particularly, to a technology for measuring resistance of a memory cell in the memory device.
2. Description of the Related Art
Generally, a fuse may be programmed in the wafer stage of a memory chip because data are sorted out depending on whether the fuse is cut or not by a laser. The fuse mounted in the package stage of the memory chip may not be programmed.
To more easily program the fuse of the memory chip, an e-fuse is used, which stores a data by using a transistor and changing resistance between a gate and a drain/source of the transistor.
FIG. 1 illustrates an e-fuse formed of a transistor and operating as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse is formed of a transistor T, and a power supply voltage is applied to a gate G of the transistor T while a ground voltage is applied to a drain/source D/S thereof.
When a power supply voltage having such a level that the transistor T may bear is applied to the gate G, the e-fuse operates as a capacitor C. Therefore, no current flows between the gate G and the drain/source D/S. When a high power supply voltage having such a voltage level that the transistor T may not bear is applied to the gate G, a gate oxide of the transistor T is destroyed to cause the coupling between the gate G and the drain/source D/S and the e-fuse operates as a resistor R. Therefore, current flows between the gate G and the drain/source D/S. According to this phenomenon, a data of an e-fuse is recognized based on the resistance value between the gate G and the drain/source D/S of the e-fuse. Here, the data of the e-fuse may be recognized by 1) enlarging the size of the transistor T without additionally performing a sensing operation, or by 2) using an amplifier and sensing the current flowing through the transistor T instead of increasing the size of the transistor T. The two methods, however, have a dimensional restriction because the large size of the transistor T is to be designed or an amplifier for amplifying a data is to be added to each e-fuse.
U.S. Pat. No. 7,269,047 discloses a method for decreasing the area occupied by an e-fuse by forming an e-fuse array.
FIG. 2 is a block view illustrating a conventional memory device formed of an e-fuse array.
Referring to FIG. 2, the memory device includes a cell array including a plurality of memory cells 201, 202, 203 and 204, a row control circuit 210, a voltage supplier 220, and a column control circuit 230.
The memory cells 201, 202, 203 and 204 include memory units M1, M2, M3 and M4 and switch units S1, S2, S3 and S4, respectively. Each of the memory units M1, M2, M3 and M4 is an e-fuse that has characteristics of a resistor or a capacitor depending on whether the e-fuse is ruptured or not. In other words, the memory units M1, M2, M3 and M4 may be regarded as resistive memory devices for storing data based on their resistance values. The switch units S1, S2, S3 and S4 electrically connect the memory units M1, M2, M3 and M4 with column lines BL0 and BL1 under the control of row lines WLR0 and WLR1.
The row control circuit 210 includes a row decoder 211 and a plurality of voltage transformers VT 212 and 213. The row decoder 211 activates a signal of a selected row line, among the row lines WLR0 and WLR1, into a logic high level by decoding an address ADD to turn on a switch unit of the corresponding row. The voltage transformers VT 212 and 213 supply program/read lines WLP0 and WLP1 with a voltage of a logic low level when receiving deactivated signals through the row lines WLR0 and WLR1. When receiving activated signals through the row lines WLR0 and WLR1, the voltage transformers VT 212 and 213 transfer a voltage P/R BIAS, which is received from the voltage supplier 220, to the program/read lines WLP0 and WLP1.
The voltage supplier 220 supplies a high voltage that may destroy the gate oxide of the e-fuses M1, M2, M3 and M4 to the voltage transformers VT 212 and 213 during a program operation, which is a rupture operation of a fuse. The high voltage is generated by pumping a power supply voltage. During a read operation, the voltage supplier 220 supplies a voltage appropriate for the read operation, which is usually a power supply voltage, to the voltage transformers VT 212 and 213.
The column control circuit 230 includes a column decoder 231, a current limiter 232, and a sense amplifier 233. The column decoder 231 electrically connects a selected column line among column lines BL0 and BL1 with the current limiter 232 by decoding the address ADD. The current limiter 232 is formed of a transistor that is controlled based on a bias voltage. The current flows from the selected column line among the column lines BL0 and BL1 to a ground voltage terminal. The sense amplifier 233 senses a data by comparing a voltage of an upper node of the current limiter 232 with a reference voltage VREF. When a memory cell selected by the row decoder 211 and the column decoder 231 is ruptured, current flows through the current limiter 232. Therefore, the sense amplifier 233 generates an output data OUTPUT in a logic high level. When the selected memory cell is not ruptured, no current flows through the current limiter 232. Therefore, the sense amplifier 233 generates an output data OUTPUT in a logic low level.
In a memory device including an e-fuse array, a data is recognized based on the resistance value of a memory cell. Therefore, when the resistance value of a memory cell that is ruptured or not ruptured may be accurately measured, reliability of the memory device may be improved considerably. However, since memory cells are arranged in the form of an array and there are many peripheral circuits, it is difficult to accurately measure the resistance value of a memory cell.
USPTO Backgrounds
USPTO Backgrounds