(1) Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which is arranged to perform a refresh operation for holding data stored therein.
(2) Description of the Related Art
For memory devices provided in portable appliances such as cellular phones, conventionally, SRAMs have been mainly used. Today, however, the increase of a necessary memory capacity results in requiring a large-capacity memory like a DRAM for such portable appliances. The shortcoming involved in the use of such a large-capacity memory is a life of a cell used in a portable appliance.
Though the SRAM hardly consumes electric power for holding data, the DRAM is required to periodically perform a refresh operation for holding data. It means that the DRAM consumes a certain amount of electric power even when it stays on standby. That is, even when the portable appliance is not used, the DRAM consumes electric power for holding data, which leads to consuming up the power stored in a backup cell.
In order to solve this shortcoming, it is just necessary to reduce the times of the refresh operation on standby, for reducing the power consumption. For example, the data holding time of the DRAM is characterized to be longer as the temperature becomes lower. Hence, when the ambient temperature is lower than a specific reference temperature, the interval between the refresh operation is set to be longer, for reducing the times of the refresh operation.
FIG. 12 shows relation between a data holding time and a temperature. In FIG. 12, a waveform W11 denotes the temperature dependency of the data holding time of a DRAM cell, while a waveform W12 denotes an interval between the refresh operation of the DRAM cell. The time on the axis of ordinance is denoted on a log scale. As indicated by the waveform W11, the DRAM cell has a longer data holding time as the temperature becomes lower. Hence, as indicated by the waveform W12, when the temperature of the chip is lower than a predetermined reference temperature Tth, the interval between the refresh operation is set to be longer, while when the temperature of the chip is higher than the reference temperature Tth, the interval between the refresh operation is set to be shorter. This setting makes it possible to reduce the power consumption.
FIG. 13 is a block diagram showing a control circuit for controlling the interval between the refresh operation shown in FIG. 12. As shown in FIG. 13, the control circuit includes a reference level circuit 101, a temperature detector 102, a frequency division controller 103, a ring oscillator 104, and a frequency divider 105.
The reference level circuit 101 operates to output a constant reference voltage that does not depend upon the variations of a temperature and a power supply. The temperature detector 102 operates to compare the reference voltage supplied from the reference level circuit 101 with a voltage changing in dependency on the temperature and then output the compared result to the frequency division controller 103. That is, the temperature detector 103 determines if the temperature of the chip (that is, the DRAM cell) is higher or lower than the reference temperature. The frequency division controller 103 controls a frequency dividing ratio of the frequency divider 105 according to the determined result sent from the temperature detector 102. For example, when the temperature detector 102 determines that the temperature of the chip is lower than the reference temperature, the frequency division controller 103 controls the frequency divider so that the frequency dividing ratio may be larger. When the temperature detector 102 determines that the temperature of the chip is higher than the reference temperature, the frequency division controller 103 controls the frequency divider 105 so that the frequency dividing ratio may be smaller.
The ring oscillator 104 is composed of inverters 104a to 104e. The oscillating signal generated by the inverters 104a to 104e is outputted to the frequency divider 105 through the inverter 104f. The frequency divider 105 is composed of flip-flops 105a to 105e. The frequency divider 105 counts based on the oscillating signal sent from the ring oscillator 104 and outputs a refresh request signal when the count reaches a predetermined value. The frequency divider 105 may change its frequency dividing ratio under the control of the frequency division controller 103. The refresh request signal is outputted to the refresh circuit. In response to the signal, the refresh circuit operates to refresh the data stored in the DRAM cell.
FIG. 14 is a circuit diagram showing the reference level circuit shown in FIG. 13. As shown in FIG. 14, the reference level circuit 101 divides the voltage VRFV that does not depend upon the variations of the temperature and the power supply through the use of resistors R101 and R102 and then outputs the resulting reference voltage vref.
FIG. 15 is a circuit diagram showing the temperature detector shown in FIG. 13. As shown in FIG. 15, the temperature detector 102 is composed of inverters 111, 112, PMOS transistors M101 to M105, NMOS transistors M106 to M108, a resistor R111, and a diode D101.
When a temperature detection enable signal detenz is at the H (High) level, the temperature detector 102 operates to compare the reference voltage vref with a monitor voltage vmoni at a contact point between the diode D101 and the resistor R111 and to output the compared result as the temperature detection signal detectz through the inverter 112. The threshold value of the diode D101 changes in dependency upon the temperature and the monitor voltage vmoni is lower as the temperature is higher.
When the monitor voltage vmoni is higher than the reference voltage vref, that is, the temperature of the chip is lower than the reference temperature, the temperature detector 102 outputs the temperature detection signal detectz at the H level. When the monitor voltage vmoni is lower than the reference voltage vref, that is, the temperature of the chip is higher than the reference temperature, the temperature detector 102 outputs the temperature detection signal detectz at the L (Low) level. The temperature detection signal detectz is outputted to the frequency divider 105. Then, the frequency divider 105 changes the frequency dividing ratio in dependency upon the state of this temperature detection signal detectz.
FIG. 16 is an explanatory view showing the operation of the temperature detector shown in FIG. 15. In FIG. 16A shows relation between the reference voltage vref and the monitor voltage vmoni. FIG. 16B shows the voltage of the output (the drain of a transistor M106) of a differential amplifier composed of transistors M103, M104 and M106 to M108. FIG. 16C shows the voltage of the temperature detection signal detectz.
As shown in FIG. 16A, when the monitor voltage vmoni is higher than the reference voltage vref, the differential amplifier outputs the signal at the L state as shown in FIG. 16B. This signal is inverted by the inverter 112 so that the signal may be changed into the temperature detection signal detectz at the H level as shown in FIG. 16C. Further, as shown in FIG. 16A, when the monitor voltage vmoni is lower than the reference voltage vref, the differential amplifier outputs the signal at the H level as shown in FIG. 16B. This signal is inverted by the inverter 112 so that this signal may be changed into the temperature detection signal detectz at the L level as shown in FIG. 16C.
Further, there has been proposed a semiconductor device provided with a temperature detection function of optimizing the operating state according to the predetermined detection temperature. (see Japanese Unexamined Patent Publication No. 2003-132678.) Further, there has been proposed a temperature detection circuit arranged to calibrate a variety in manufacture, optimize the refresh interval according to the operating temperature, and reduce the power consumption. (see Japanese Unexamined Patent Publication No. 2000-55742.)
As shown in FIG. 12, however, only one reference temperature is provided for changing the interval between the refresh operation. Hence, those circuits involve a shortcoming that a large interval takes place between the data holding time of the DRAM cell and the refresh interval and thus the efficiency of lowering the power consumption is made lower.
USPTO Backgrounds
USPTO Backgrounds