The present invention relates to a nonvolatile semiconductor memory device that stores data using floating gate transistors. More specifically, the present invention pertains to a nonvolatile semiconductor memory capable of performing a stable data writing operation.
An electrically erasable programmable ROM (EEPROM) has a plurality of memory cells, with each memory cell including an electrically erasable transistor. Each memory cell transistor has, for example, a split gate type double gate structure including a floating gate and a control gate. In writing data to double gate structured memory cell transistor, hot electrons that have been produced in the drain region are accelerated and put into the floating gate. In reading data, a difference between an operation characteristic of the memory cell transistor when a charge is accumulated in the floating gate and that when a charge is not accumulated is detected.
FIG. 1 is a schematic diagram of a nonvolatile semiconductor memory device 100 having a memory cell block 10, in which split gate type memory cell transistors 11 are arranged four rows by four columns.
Word lines 12 are arranged along the memory cell transistors 11 in each row and are commonly connected to the control gates of the memory cell transistors 11 in the same row. Row selection signals LS1 to LS4 are sent to the word lines 12 from a row decoder (row selection circuit) 110, and the memory cell transistors 11 in a selected row are activated in response to the signals LS1 to LS4.
Bit lines 13 are arranged along the memory cell transistors 11 in each column and are commonly connected to the drains of the memory cell transistors 11 in the same column. Source lines 14 are arranged between and in parallel with the word lines 12 and are commonly connected to the sources of the memory cell transistors 11 in the adjacent rows. Each source line 14 is connected to a common source line 140. A write potential Vws for writing data and a first read potential Vrs for reading data are selectively supplied to each memory cell transistor 11 through the common source line 140 and the source lines 14.
A plurality of first selection transistors 15 are respectively connected to each bit line 13 and selectively connect one of the bit lines 13 to a data line 16, in response to column selection signals CS1 to CS4 from a column decoder 130 applied to the gate of the selection transistor 15.
A write circuit 120 is connected to the data line 16 and supplies a potential Vmb corresponding to write data to one of the memory cell transistors 11. The data line 16 is also connected to a sense amplifier (not shown) and supplies a potential VBL to the sense amplifier when reading.
A plurality of second selection transistors 17 are respectively connected between each bit line 13 and a power supply line 18 and connect the non-selected bit lines 13 to the power supply line 18 in response to inverted signals *CS1 to *CS4 of column selection signals CS1 to CS4 applied to the gates thereof, when writing. A predetermined potential Vb0 for preventing a write current from flowing to each non-selected memory cell transistor 11 is supplied to each non-selected bit line 13 through the power supply line 18. The second selection transistors 17 connect the bit lines 13 to the power supply line 18 in response to a read control signal RC applied to the second selection transistor gate, when reading. A second read potential Vrb (&gt;Vrs) is supplied to all of the bit lines 13 by way of the power supply line 18.
The row selection signals LS1 to LS4 are generated by the row decoder 110, based on row address information and select one of the word lines 12 (simultaneously activate each memory cell transistor 11 in the selected row). The column selection signals CS1 to CS4 are generated by a column decoder (column selection circuit) 130 based on column address information and selectively turn on one of the first selection transistors 15 (activate the memory cell transistors 11 in a specific column). One of the memory cell transistors 11 that was selected according to the row address information and the column address information is connected to the data line 16 through a bit line 13.
When writing data into a memory cell transistor 11, a potential Vmb corresponding to write data is applied to the data line 16, with one word line 12 selected, while applying a predetermined write potential Vws to the source lines 14. For example, a potential of 2V is applied to a selected word line 12, and a potential Vwb of 1V is applied to the data line 16 when the write data is `1`, and a potential Vwb of 5V is applied to the data line 16 when the write data is `0`. This enables a write current to flow to the selected memory cell transistor 11 only when the write data is `1`. This is because the memory cell transistor 11 is turned on when a potential of the word line 12 (control gate) is higher than a potential of the bit line 13 (drain) by the threshold, and a write current flows from the source line 14 to the bit line 13. Since a potential Vb0 of 5V (the same potential as the potential Vwb that is applied to the data line 16 when write data is `0`) is applied to the non-selected bit lines 13 by way of the power supply line 18, a write current does not flow in the non-selected memory cell transistors 11.
When reading data from the memory cell transistor 11, a read potential Vrb (for example, 5V) is applied to the bit line 13 through the data line 16, and a read potential Vrs (for example, 0V) is applied to the source line 14. The change of potential of the bit line 13 generated when the word line 12 is selected is read by the sense amplifier through the data line 16.
In the write operation of the split gate type memory cell transistor 11, it is necessary to set high a potential difference between the source and drain to accelerate the hot electrons generated in the drain of the memory cell transistor 11 to the source. Accordingly, for example, the potential Vwb of 0V is applied to the bit line 13, and the write potential Vws that is 10V or higher (for example, 14V) to the source line 14.
As mentioned above, since 0V is applied to the data line 16 when write data is `1`, a write current flows in the selected memory cell transistor 11. In this case, the potential of the source line 14 decreases and no excessive electric field is applied to the non-selected memory cell transistor 11. When the write data is `0`, 5V is applied to the data line 16, and a write current does not flow in the selected memory cell transistor 11. In this case, the potential of the source line 14 does not decrease and the write potential Vws may affect all of the memory cell transistors 11. That is, when the word line 12 is selected under this circumstance, a write current flows in the non-selected memory cell transistors 11. Especially, when continuously writing data in the memory cell transistors 11 in the same row, the write current repeatedly flows in each memory cell transistor 11 in the same row, thus causing a write error.
FIG. 2 is a schematic circuit diagram of a nonvolatile semiconductor memory device 200 including a memory cell block 10A. The memory cell block 10A is similar to the cell block 10 (FIG. 1), but does not include the first and second selection transistors 15, 17. Each bit line 13 is connected to a write circuit 220. When writing, the write circuit 220 supplies potentials Vwb1 to Vwb4 corresponding to a write data to the memory cell transistors 11 in each row through each bit line 13, respectively. The bit line 13 is also connected to a sense amplifier (not shown). When reading, the sense amplifier receives a potential VBL through each bit line 13. The potential VBL is generated by supplying a read potential Vrb to each memory cell transistor 11.
In the nonvolatile memory device 200, for example, when data `1` is written in the memory cell transistors 11 in all of the columns, all of the potentials Vwb1 to Vwb4 are set to 0V. Then, a write current flows in the memory cell transistors 11 in all of the columns, and the potential Vws of the source line 14 decreases by the amount of all of the write currents. The decrease of the source potential destabilizes the potential of the source line 14. The fluctuation of the write potential Vws varies write operation and causes a write error as a result.
The present invention provides a nonvolatile semiconductor memory device capable of performing a stable data writing operation.
USPTO Backgrounds
USPTO Backgrounds