For a semiconductor integrated circuit that outputs a digital signal in synchronization with a clock signal of 10 MHz or higher frequency, an output interface circuit is typically arranged for reliable high speed operation. For example, for a digital signal in synchronization with a 26 MHz clock signal, it is required that a rising edge time (hereinafter to be referred to as tr) and a falling edge time (hereinafter to be referred to as tf) of the digital signal be about 2 to 6 nanoseconds (ns). A low limit is set for tr and tf to prevent noise generation.
Consequently, in the design of the output interface circuit, circuit constants of structural parts are adjusted to obtain the desired tr, tf. However, due to variations in power supply voltage and variation in temperature, tr and tf vary, so that such adjustment is not easily accomplished.
An output potential of a band gap reference circuit (hereinafter to be referred to as a BGR circuit) which is free from the influence of the variation in the power supply voltage and the variation in the temperature can be taken as a reference potential, and tr and tf adjusted. However, the BGR circuit does not have good responsiveness, so that for an integrated circuit with a low power supply voltage or one that is required to conduct high-speed data output immediately after power is turned on, the response speed of the BGR circuit cannot catch up with the timing of output data.
USPTO Backgrounds
USPTO Backgrounds