As the level of integration of integrated circuits increases so there may also be a corresponding decrease in the size of components included in the integrated circuits. Some of the factors which contribute to the size of an integrated circuit include the memory cell size, the number of control circuits and the number of pads in the integrated circuit. In particular, the pads included in the integrated circuits may be divided into two groups: bonding pads and test pads. Bonding pads may be used to provide input and output to the integrated circuit in normal operation. Tests pads may provide test functions for the integrated circuit during the fabrication process. For example, the test signals may be applied to the corresponding test pads to initiate a test function in the integrated circuit. After the integrated circuit is fabricated, however, the test pads may not be used.
FIG. 1 is an enlarged schematic diagram that illustrates arrangements of memory cells, control circuits and outer pads in integrated circuit memory devices according to the prior art. According to FIG. 1, as the size of the memory cells 14 and the circuits 16 shown in the top half of FIG. 1 are decreased, the overall size of the integrated circuit region 12 may be decreased as shown in the lower half of FIG. 1. However, the pads 20 may be formed such that further reductions may not be easily achieved. For example, it may be difficult to reduce the pitch between adjacent pads 20 to less than about 20 .mu.m. Consequently, the pads 20 located on opposite sides of the integrated circuit region 12 may not fit into the integrated circuit region 12.
FIG. 2 is an enlarged schematic diagram that illustrates arrangement of memory cells, control circuits, and inner pads in integrated circuit memory devices according to the prior art. According to the upper half of FIG. 2, as the sizes of the memory cells 14 and the control circuits 16 are reduced as shown in the lower half of FIG. 2, the inner pads 20 may not fit on the integrated circuit 12 and may therefore limit the size reduction of the integrated circuit 12. The pads 20 therefore may limit the size reduction of the integrated circuit region 12. Moreover, limitations in the reduction of the integrated circuit region 12 may limit further reductions in the size of the integrated circuit package 10.
In view of the above, there continues to exist a need to further improve integrated circuit wafers and reduce the size of integrated circuit regions and integrated circuit packages.
USPTO Backgrounds
USPTO Backgrounds