1. Technical Field
The present invention relates to a timing generator for generating a timing signal based on a given reference clock and to a test apparatus having the timing generator. More specifically, the invention relates to a timing generator whose calorific value is stabilized.
2. Related Art
Operating speed of electronic devices such as LSI is improving lately. With that, it has become necessary to generate a high precision clock in a test apparatus and the like for testing such electronic devices. Conventionally, in order to generate a clock having a desirable pattern, there has been known a circuit having a logic gate that passes desirable pulses among pulses of a reference clock and a delaying circuit for modulating phases of the respective pulses.
However, such circuit causes a problem that a number of pulses and pattern of pulses passing through the delaying circuit vary corresponding to the pattern of the pulses selected by the logical gate and that a calorific value in the delaying circuit varies as a result. Due to that, a value of delay in the delaying circuit fluctuates, causing jitter in the clock to be generated. Such jitter is not permissible in the high precision LSI and the like.
Then, as a circuit that is capable of solving the above-mentioned problem, there has been known a circuit further including a dummy delaying circuit.
This circuit keeps a total calorific value in those delaying circuits constant regardless of the pattern of the clock to be generated by inputting pulses not inputted to the delaying circuit for generating the clock among pulses of the given reference clock to the dummy delaying circuit.
The applicant of the invention is presently unaware of existence of any related patent document or the like, so that their description will be omitted here.
However, because the conventional circuit needs to be provided with the dummy delaying circuit which is identical with the delaying circuit for generating the clock in order to keep the calorific value constant as described above, a size of the circuit increases. Still more, while it is necessary to provide the delaying circuit for generating the clock in the vicinity of the dummy delaying circuit to keep the temperature of the delaying circuit for generating the clock constant, there is also a problem that a signal in the dummy delaying circuit interferes with a signal in the delaying circuit for generating the clock, causing jitter in the clock to be generated. For example, phase of the pulses passing through the delaying circuit for generating the clock becomes almost identical with phase of the pulses passing through the dummy delaying circuit and causes interference depending on setting of the value of delay in the delaying circuit for generating the clock.
Accordingly, it is an object of the invention to provide a timing generator and a test apparatus capable of solving the above-mentioned problems. This object may be achieved through the combination of features described in independent claims of the invention. Dependent claims thereof specify preferable embodiments of the invention.
USPTO Backgrounds
USPTO Backgrounds