Semiconductor devices having rapid operation speeds as well as high capacitances are desirable. In order to meet these demands, semiconductor devices are being developed to improve the degree of integration, reliability and response speeds thereof. In particular, as semiconductor devices are highly integrated, a design rule of these semiconductor devices may be reduced.
Thus, an isolation layer or a metal wiring in the semiconductor device may be formed to have a fine (thin) line width. However, photolithography processes used to fabricate these layers/wirings may have resolution limits. Accordingly, it may not be easy to form the isolation layer or the metal wiring having a line width below the resolution limit of the photolithography process.
USPTO Backgrounds
USPTO Backgrounds