1. Field of Invention
The present invention relates generally to memory devices, and more particularly to an extended translation look-aside buffer (eTLB) for improving performance and reducing power consumption of a memory structure, and methods of memory management using the same.
2. Description of Related Art
In general, a translation look-aside buffer (TLB) is used to reduce virtual address translation time. A TLB is a table in the processor's memory that contains information about the pages in memory the processor has accessed recently. The table cross-references a program's virtual addresses with the corresponding absolute addresses in physical memory that the program has most recently used. A TLB enables faster computing because it caches the virtual to physical address translations locally. A TLB may be implemented in a number of ways. For example, a TLB may be enabled in a fully associative content addressable memory (CAM) structure. A CAM is a type of storage device which includes comparison logic with each bit of storage. A data value may be broadcast to all words of storage and then compared with the values there. Words matching a data value may be flagged in some way. Subsequent operations can then work on flagged words, e.g. read them out one at a time or write to certain bit positions in all of them. Fully associative structures can therefore store the data in any location within the CAM structure. Comparison logic, however, requires comparison circuitry, which occupies physical space—physical space which, in other structures may be utilized to provide more memory. As such, CAM structures may not be as densely configured as other memory structures. Further, because of the comparison circuitry, CAM structures have relatively high power requirements.
In other examples, a TLB may be enabled in a set associative memory (SAM) structure, such as a random access memory (RAM) structure. SAM structures organize caches so that each block of memory maps to a small number of sets or indexes. Each set may then include a number of ways. A data value may return an index whereupon comparison circuitry determines whether a match exists over the number of ways. As such, only a fraction of comparison circuitry is required to search the structure. Thus, SAM structures provide higher densities of memory per unit area as compared with CAM structures. Further, because of reduced comparison circuitry, SAM structures have lower power requirements as compared with CAM structures.
As may be appreciated, both of the memory structures described above may provide specific advantages in a processing system. In general, however, designers must typically choose between memory structures when developing a system under an existing architecture. For example, the Microprocessor without Interlocked Pipeline Stages (MIPS) architecture, which is well-known in the art, specifies a fully associative TLB based translation mechanism. The mechanism utilizes the EntryHi, EntryLo1, EntryLo0 and Index architectural registers to perform functions such as reading, writing and probing the TLB. These mechanisms and functions assume that the TLB is a fully associative structure (i.e. a CAM structure) that is in compliance with the requirements of the MIPS architecture. Therefore, increasing the size of the TLB necessitates the addition of more fully associative CAM structures. An increase in CAM structures, in turn, requires a commensurate increase in space and power to accommodate the additional CAM structures. Currently, the MIPS architecture cannot utilize a more space and power efficient SAM structure.
It may therefore be desirable to provide a system which includes an extended TLB (eTLB) that utilizes both CAM structures and SAM structures so that the relative advantages of both structures may be realized. The invention is particularly useful in systems that utilize existing registers and mechanism as specified by the MIPS architecture.
Therefore, systems and methods for utilizing an extended translation look-aside buffer having a hybrid memory structure are provided herein.
USPTO Backgrounds
USPTO Backgrounds