Prior to bonding an electronic device, such as a semiconductor integrated circuit chip, into its final position in a package, for example, in a multichip module (comprising several chips), it is often desirable for economic reasons to test the chip electrically and discard it in case the test indicates that the chip suffers from an undesirable defect. In this way, further time and materials are not wasted in conjunction with processing and handling defective chips, such as packaging them.
In one approach of prior art, such testing is performed by testing each semiconductor integrated circuit chip at the semiconductor wafer level--that is, by testing all the integrated circuit chips before they have been diced from the wafer into stand-alone individual chips. Each chip has input-output terminals or pads ("chip I/O pads") located on a major surface of the chip. Typically, these I/O pads are metallic and have surfaces, typically approximately 0.10 mm.times.0.10 mm, typically comprising aluminum. The pads are typically spaced apart by approximately 0.10 min. Each of the I/O pads can be devoted to receiving input signals or delivering output signals (or devoted to both), or devoted to receiving power or ground.
In order to test a specific chip at the wafer level, the wafer and a testing circuit board are aligned, as by means of a step-and-repeat procedure. The testing circuit board has a set of probe wires, each typically made of tungsten or of beryllium copper. During testing, the probe wires are brought into good electrical contact with some or all of the chip I/O pads, including power and ground pads. Signals from probe circuitry are delivered through some of the probe wires to some of the chip I/O pads, while power and ground (voltages) are delivered to the chip power and ground pads. The resulting signal output voltages that are developed at other of the chip I/O pads are then detected by the probe circuitry via other of the probe wires. The time duration of each test for each chip is typically of the order of only a second ("fast testing"). The circuit board together with the probe circuitry are thereafter reused for testing other chips on the same wafer, as well as for other chips on other wafers.
A problem with the foregoing fast testing procedure is that the testing signal frequency is limited to undesirably low values owing to the inductance of the probe wires and the capacitance of the testing circuit board. Therefore, high signal frequency testing--i.e., testing with signal frequencies as high as those to be handled by the packaged chip during subsequent normal operation, typically about 50 to 100 MHz or more--is not feasible at the wafer level but must await not only dicing of the wafer into chips but also proper packaging of the chips--that is, assembling each chip in a package. Each such package has a fan-out of the chip I/O pads into I/O pins that have surfaces of approximately 0.4 mm.times.0.4 mm and that are spaced apart by approximately 2.5 mm. In this way, each thus packaged chip can be tested by plugging the package's I/O pins into a testing circuit receptacle that has electrical contacts which are aligned with the packaged chip pins, these contacts having wires connected to testing circuitry. However, such testing is costly in that it thus requires prior packaging of each chip: if a chip is fatally defective and thus is to be discarded, the packaging expenditure was wasted on such a chip. Therefore, it would be desirable to have a method of high signal frequency, fast testing of integrated circuit chips (or other electrical devices for that matter, such as laser chips) before they are packaged.
USPTO Backgrounds
USPTO Backgrounds