This invention relates to a drive circuit for a latching relay which keeps an existing condition even when an input or control signal is cut off.
It has been well-known that this kind of latching relay does not require a continued current to its coil for keeping the relay in its working condition.
Such latching relays have been proposed, for example, in Japanese Utility Model Publication No. 48702/1977 and Federal Republic German Patent No. 1279777.
These known circuits are so constructed that a condenser and a latching relay are connected in series to a supply voltage of 100 to 200 V, and via a switch a unidirectional current flows into the latching relay to be actuated. The condenser, after a given time period, is charged to cut off the current, and thereafter the latching relay is kept mechanically in the existing working condition. Upon turning off the switch, the condenser discharges so that the discharge current flows in the latching relay as an inverse current through a switching circuit of semiconductor, such as transistor, thereby inverting the working condition of the relay.
These drive circuits are disadvantageous in that larger capacity condensers are needed which are inapplicable for an integrated circuit, and that the small-sized latching relay cannot house such large-sized condensers.
Japanese Patent No. 80231/1980 has proposed a solution how to overcome the above disadvantage.
This solution employs no condenser but a combination of transistors, which, similarly to the former prior arts, connects a drive circuit of transistors and a latching relay in series to the supply voltage of 100-200 V.
The Japanese patent, however, is not applicable and developable to computers, and so is the case of course with the aforementioned Japanese utility model and the German patent. According to the Japanese patent, the latching relay is changed over at high speed by output bits of a central processing unit (CPU) and connected to a programmable logic controller (PLC).
The CPU changes over the relay, for example, at high speed of 100 .mu.sec by eight output bits. On the contrary, a time period necessary for changing over the latching relay, i.e., a time period for flowing a current in coils of the relay, is 100 msec, which considerably differs from the above mentioned speed.
Therefore, in the Japanese patent No. 80231/1980, the latching relay cannot follow such high speed change-over and no circuit is provided for compensating it.
USPTO Backgrounds
USPTO Backgrounds