1. Field of the Invention
This invention relates to a method for fabricating a trenched DMOS transistor using six masking steps, resulting in a transistor having narrow trenches, shallow diffusions, and formed using relatively few process steps.
2. Description Of The Prior Art
DMOS transistors are well known as a type of MOSFET (metal on semiconductor field effect transistor) using diffusions to form the transistor regions, with a typical application being as a power transistor. Such devices enjoy widespread use in such applications as automobile electrical systems, power supplies, and power management applications.
Many different processes have been used for the fabrication of power MOSFET devices over the years; these are generally deep diffusion processes. It is also well known to form such transistors having a trench in the substrate, the trench being lined with a thin oxide layer and filled with a conductive polysilicon to form the transistor gate structure.
Prior art trenched DMOS transistors have the shortcoming that typically it takes a fairly large number (such as eight or nine) fabrication masking steps to define the various transistor regions, including the tubs in which the active transistor regions are formed, the body region of the transistor, the source region of the transistor, the body contact regions, each of which are separate diffusions, and the termination structures, i.e. field plates and field rings. Additional masking steps are used to define the oxide layers and polysilicon portions of the transistor. Each additional masking step requires a mask alignment and thus results in the possibility of alignment error, undesirably reducing yield. Additionally, the many process steps which include temperature cycles tend to result in unwanted diffusion of certain of the implanted ions, thus undesirably altering the lateral extent and/or depth of various of the diffused regions.
Thus there is a need for transistor fabrication processes using relatively few masks.
It is also desirable in fabrication of such a device to eliminate the polysilicon ("poly") stringer problem. Polysilicon stringers are typically formed when a layer of polycrystalline silicon ("polysilicon") is deposited over for instance an oxide layer which includes a step structure. Subsequent etching down of the polysilicon layer results in a portion of the polysilicon remaining adjacent to the step, since the polysilicon layer is thickest at that point. This "stringer" portion causes significant performance problems in the resulting transistor.
USPTO Backgrounds
USPTO Backgrounds