Pipeline computers bear the name by reason of some similarity to petroleum pipelines that pass different products in sequence through interconnected sections. Before one petroleum product clears a pipeline, several others may have been introduced. By analogy, in pipeline computers, a series of stages perform distinct steps on sequences of passing data.
To consider an exemplary sequence in a pipeline computer: an initial stage fetches instructions, a second stage decodes the instructions, a third stage locates operands and so on. For continuity in existing systems, the final stage in the pipeline may update a program counter to provide the address of the next instruction in a current sequence.
Normally, the first stage of a pipeline computer operates with a program counter value that is several cycles ahead of the counter value produced by the last stage. In one typical operation, the future value of the program counter is estimated for the initial stage on the basis of successive increments. A branch operation commanded by a branch instruction breaks the pipeline normally requiring the program counter to split from an existing sequence. Thus, interaction between the first and last stages of a pipeline computer is effected when a branch command alters the program counter nonsequentially. That is to say, during as many cycles as there are stages in the pipeline, no instructions can be issued. The process is thus blocked with a resulting loss of time. Also, branch operations may involve further complications and loss of time in view of conditions that remain undetermined when a conditional branch instruction reaches the last stage of the pipeline.
With regard to the present system, the delayed branch affords a way to prevent the usual loss of time attendant pipeline breaks and to enable use of what is already in the pipeline. It significantly improves the performance of branch instructions, the occurrence of which are very common (typically more than fourteen percent). Time losses, traditionally attendant pipeline breaks, are avoided by accommodating effective programming of the system.
In general, the present invention involves a system (apparatus and process) involving variable delay branch operation which accommodates programming of both conditional and unconditional branch operations as for use in a pipeline computer to avoid the loss of time.
As programmed instructions are provided for execution, the system implements steps to accommodate a branch command, followed by a split command to indicate the time for the jump. In the disclosed embodiment, the split command comprises a bit in an instruction to command the execution of a branch. That is, a jump is not executed immediately after a branch command but rather is delayed by a variable number of program instructions pending a split command in the form of a split bit. The variable number is under the control of the programmer, enabling considerable flexibility and time saving. However, as disclosed herein, the delay must be at least one cycle. The branch command does not indicate the imposed delay, but rather the system affords flexibility. If no delay is desired, the branch command can be followed by a no-operation instruction containing a split bit.
When a control instruction specifies a conditional branch, the results of subsequent processing are tested until the condition codes are ready and a split bit occurs (in either order). If the condition is not met, the system does not jump but rather resumes execution of the current sequence in the program counter.
In summary, following a branch command, the system affords a variable delay during which branch or target instructions are fetched enabling a prompt jump as on the occurrence of a split bit. By setting up the sequence of target instructions for a branch command, accommodating variable delay and accommodating conditional branches, the system of the present invention enables a substantial saving of time and flexibility in the operation of a pipeline computer. As explained in detail below, the saving of time results because with a branch, the currently operating units continue to function while the target instructions are fetched and loaded. Also, in the case of a conditional branch, condition codes are developed concurrently with useful operation. Of course, the effectiveness of the system is somewhat dependent on the extent of its utilization by an instant operating program.
USPTO Backgrounds
USPTO Backgrounds