1. Field of the Invention
The present invention relates to an image processing system.
2. Description of the Prior Art
A conventional image magnification factor processing system as shown in FIG. 1 is known (Japanese Laid-Open No. 56-137771) which allows magnification factor processing by changing the frequency of clock signals for transferring image data. In this system, the clock signals are interlaced at a predetermined rate so as to change the frequency thereof. A photoelectric image sensor 1 photoelectrically converts light reflected from or transmitted through an original for recording. A binarizing circuit 2 converts an electrical signal or an image signal from the image sensor 1 into an electrical binary signal V. A latch circuit 3 latches the binary signal V. A clock interlace circuit 4 interlaces at a predetermined rate fundamental clock signals .phi..sub.1 supplied from a clock generator (not shown). An interlaced signal W from the clock interlace circuit 4 is supplied to the latch circuit 3 and to a memory circuit 5 for controlling input/output of the image in/from the memory circuit 5.
In an image magnification factor processing system having the configuration described above, the clock generator (not shown) constantly supplies the fundamental clock signals .phi..sub.1 to the clock interlace circuit 4 and clock signals .phi..sub.2 of a different frequency to the binarizing circuit 2.
When an image is to be enlarged, as shown in the timing chart shown in FIG. 2, signals a, c and e of an image signal LV controlled by the interlaced signal W are written at different addresses of the memory circuit 5. These signals are read out (as an image signal MV) by an address counter 6 in accordance with clock signals of a predetermined frequency. When an image is to be reduced in size, the number of clocks to be eliminated from the fundamental clock signals .phi..sub.1 by the clock interlace circuit 4 is increased to write a certain proportion of the binary signal V in the memory circuit 5. In this manner, the binary signal V is controlled by the interlaced signal W and its frequency is changed. Since the clock interlace circuit 4 is used, if the phase relationship between the fundamental clock signals .phi..sub.1 and the clock signals .phi..sub.2 for forming the binary signal V is kept constant, the phase relationship between the interlaced signal W and the binary signal V is also kept constant. Therefore, the write operation into the memory circiuit 5 is stabilized.
However, although the copying size or magnification factor of an image and the clock interlace circuit 4 hold a close relationship, a means for realizing the magnification factor at a precision in units of 1% has not yet been established. For example, when a magnification factor of 95% is to be realized with a TTL 6-bit binary counter for the clock interlace circuit 4, the clock rate must be set such that a frequency fW of the interlaced signal W satisfies fW=0.95.times.f.phi..sub.2, i.e., fW=(0.95/2)f.phi..sub.1 provided that the frequency f.phi..sub.2 of the clock signal .phi..sub.2 and the frequency f.phi..sub.1 of the fundamental clock signal .phi..sub.1 hold the relation f.phi..sub.2 =(1/2)f.phi..sub.1. Therefore, when the binary counter as described above is used, a preset count M satisfying 0.95/2=M/64 must be preset as a binary number. From the above relation, M is calculated to be 30.4 in decimal notation. However, since this value cannot be represented as a binary number, M=31 or M=30 is preset. When M is preset to be 31, the actual magnification factor is 96.8%. When M is preset to be 30, the actual magnification factor is preset to be 93.7%. Thus, these magnification factors have errors of +1.8% and -1.3%, respectively, from the target magnification factor.
USPTO Backgrounds
USPTO Backgrounds