1. Field of the Invention
The present invention relates to a logic designing system for designing digital logic devices, and in particular, to a method for generating data of a logic circuit suitable for automatically comparing and modifying logic expressed with the higher and lower hierarchic data for a design change of a hierarchic logic designing.
2. Description of the Prior Art
In production of integrated semiconductor circuits as well as printed circuits, there is required a process for determining combinations of circuit elements and placement thereof to provide such circuits with respective desired functions. After the process is completed, various masks are created by use of data generated in this process. The data items are generated in a data system having two hierarchic data levels: One is a higher hierarchic level assigned to data represented by a group of function blocks of boolean expressions for logical functions of an integrated semiconductor circuit, the other is a lower hierarchic level assigned to data created in association with the higher hierarchic data and which represents combinations of circuit elements. The correspondences between the higher and lower hierarchic data items must be obtained in order to check whether or not the data at the higher hierarchic level has been properly developed with respect to the lower level data items and to modify the corresponding lower hierarchic data items when higher level items are changed, for example, because of a design change or because a logic is modified based on a result obtained from a check on the amount of signal delay due to lower level data items.
For the data modification, the information about the data correspondences between the higher and lower hierarchic data items is not necessary if all the data items at higher hierarchic level are converted again into the lower level data items; however, the lower hierarchic data items converted from the higher level data items are in general assigned with layout information such as part names, mounting placement information, and pin numbers. Consequently, when all data items at the higher hierarchic level are converted again, the layout information must be also assigned in addition. It is therefore desirable to partially convert only the modified data items.
Conventionally, since the notation varies between the higher and lower hierarchic data items, the signal names are assigned by use of the different assigning systems. In order to establish the correspondences between the higher and lower level data items, a correspondence table representing the correspondences between the signal names thereof is manually generated.
However, a considerable human power is required to create the correspondence table and there exist problems to be solved that the operation for obtaining a correspondence between functional blocks from the correspondence table is not an easy job and that the table must be generated again if a signal name is modified.
USPTO Backgrounds
USPTO Backgrounds