1. Field of the Invention
The present invention relates to a thin-film transistor, an active matrix circuit board or active matrix panel, and a manufacturing method thereof. More particularly, the present invention relates to a technology improving the electrical characteristics of the thin-film transistor.
2. Description of the Related Art
Thin-film transistors (hereafter "TFT") which use a polycrystalline silicon are used as pixel transistors in liquid crystal display panels and other active matrix circuit boards. Of the available liquid crystal display panels, active matrix circuit boards with integrated drive circuits (integrated peripheral circuits) which are formed using TFTs in the area peripheral to the pixel area are used in, for example, relatively small liquid crystal display panels for viewfinders and projectors because it is difficult to make electrical connections to narrow pitch terminals by using conventional assembly technology. As a result, drive circuit TFTs and pixel TFTs must both be formed on the same active matrix circuit board.
Of these TFTs, a low OFF current is required in the TFT of the pixel area so that the charge written through the pixel electrodes can be maintained. Polycrystalline silicon TFTs, however, may use an offset gate structure wherein a source-drain region is provided at a position separated from the edge of the gate electrodes due to a high OFF current.
In addition, a lightly doped region (LDD region) may be provided at the edge of the drain region in order to reduce the electrical field strength therein.
The following manufacturing method is conventionally used to manufacture thin-film transistors with such a structure.
FIGS. 40A-40B depict the formation of an n-channel type TFT 1200a in the drive circuit area, p-channel type TFT 1200b in the drive circuit area, and n-channel type TFT 1200c in the pixel area from left to right facing the figure. First, second, and third silicon films 1201, 1202, 1203 are first formed on the surface side of substrate 1201. The surface sides of the first, second, and third silicon films 1201, 1202, 1203 are then covered by gate insulation film 1211.
After that, a conductive film which can comprise the gate electrode is formed on the surface side of the gate insulation film 1211. This conductive film, in turn, is etched using resist layer 1213 for a mask and results in formation of gate electrode 1212.
Next, as indicated by arrow 1214, impurity ions representing donors are implanted and source-drain area 1207 is formed. Gate electrode 1212 is over-etched with resist 1213 as the mask, and gate electrode 1212 is narrowed as shown in FIG. 40B. As a result, the length of gate electrode 1212 is shorter than the length of the region(channel region) in first, second, and third silicon films 1202, 1202, 1203 in which impurity ions are not implanted, and the offset gate structure is formed.
Next, as shown in FIG. 40C, impurity ions representing acceptors are implanted (arrow 1221) to second silicon film 1202 with first and third silicon films 1201, 1203 covered by resist 1215. As a result, source-drain region 1209 is formed. In this case, since the donor impurity was previously implanted to second silicon film 1202, the dose of acceptor impurity is much higher than the concentration of donor impurity implanted in the second film.
Note that when TFTs 1200a and 1200c are formed with an LDD structure, resist 1215 is removed after implanting acceptor and donor impurity at their appropriate respective doses. IN the TFT having the offset or LDD structure thus formed, the OFF current can be sufficiently lowered because the electrical field strength at the drain edge can be reduced.
The following problems exist with the conventional manufacturing method thus described, however.
First, even though TFT electrical characteristics vary with the gate length, this method sets the gate length by over-etching the gate electrode, and it is therefore difficult to control the gate length. For example, when a gate electrode composed of polycrystalline silicon is plasma etched, it is possible to determine the end of the etching cycle because the plasma emission strength changes at the etching endpoint in the normal etching mode, but it is difficult to reliably control etching as a whole because plasma emission strength not change in over-etching mode. In addition, it is also difficult to control over-etching when over-etching is controlled by the etching time because the etching speed varies slightly with the operating conditions, etc., of the etching equipment. As a result, the ON current characteristic and other electrical characteristics of TFT manufactured with conventional methods inevitably vary due to variations in gate length and offset length. Variations of this type are fatal defects in drive circuit TFT formed by the same process.
Due to over-etching, it is also difficult to decrease TFT size. More specifically, the active matrix circuit board must be designed with a large pattern dimension to accommodate variations in gate electrode over-etching, and designs with such large margins result in large waste in the active matrix circuit board design. Therefore, conventional manufacturing methods are not suited to high resolution liquid crystal display panels, and are an obstruction to reducing the basic pattern dimension of the active matrix circuit board from 5 .mu.m to 2 .mu.m or 3 .mu.m, or even smaller dimensions.
Second, high temperature processing exceeding 600.degree. C. is required to activate the impurity ions that are implanted within LDD structures. With such high temperature processing, however, it is not possible to use low-cost glass substrates. As a result, conventional manufacturing methods also interfere with increasing display panel screen size and reducing display panel cost. Furthermore, conventional ion implantation technologies are not well suited to processing large circuit boards because of the small ion beam size.
Technologies for implanting the generated ions without mass separation have been studied with the objective of solving these problems. For example, a method for using a mixture of an impurity gas diluted with hydrogen as the doping gas and implanting the ions generated from this mixture without mass separation has been studied, and the impurity has been activated at a relatively low temperature of about 300.degree. C. However, this method cannot activate a small amount of impurities implanted to a silicon film where the impurity concentration is 1.times.10.sup.19 /cm.sup.3 or less, and it is still impossible to manufacture an LDD TFT at relatively low temperatures.
USPTO Backgrounds
USPTO Backgrounds