The present invention relates to the field of equalization in high-speed receiving units, particularly to a continuous-time linear equalization in the analog regime. Furthermore, the present invention relates to a continuous-time linear equalizer suitable for the implementation in integrated circuitry, particularly in CMOS technology.
Data transceiving systems for high-speed communication are subject to signal distortion of the transmitted signal. Various measures are applied to reconstruct the transmitted data from the received analog signal. In receiving units, a number of equalizers are commonly provided to compensate for losses and signal distortion substantially caused by propagating the data signal via the transmission channel.
One known measure concerns an equalization of the received analog signal in the continuous time regime, i.e., before sampling and digitization and before the final digital processing of information is performed, by means of a continuous-time linear equalizer. The received analog signal to be processed by the continuous-time linear equalizer corresponds to a continuous voltage or current signal which is transmitted across the physical transmission channel according to a digital modulation format, e.g., to non-return-to-zero binary level signaling or to a pulse amplitude modulation with four signaling levels (PAM-4). It is the general purpose of a continuous-time linear equalization to compensate for the losses of high-frequency components of the transmitted analog signal which are caused by attenuation and dispersion of the signal propagating along the transmission channel.
Document US 2012/0201289 A1 discloses an exemplary continuous-time linear equalizer with three stages, wherein each stage consists of a differential pair with an NMOS active inductor load.
Document US 2013/0114663 A1 discloses a continuous-time linear equalizer circuit including a differential amplifier with two NMOS transistors, wherein the sources of the NMOS transistors are connected via a source resistor and a source capacitor. The source capacitor may be configured as a variable capacitor and the source resistor as a variable resistor to enable the adjustment of frequency and gain characteristics of the circuit for equalization purposes.
Document U.S. Pat. No. 8,537,886 B1 discloses an equalization structure with offset cancellation and bypass functions. In particular, an equalization architecture is disclosed that includes a continuous-time linear equalizer and a decision feedback equalizer each provided with offset cancellation that enables the equalizer to be used at high data rates.
Document US 2013/0188965 A1 discloses a continuous-time linear equalizer for an optical transceiver. The continuous-time linear equalizer implements a tunable high-pass function and attenuates the noise.
Document U.S. Pat. No. 8,335,249 B1 discloses an equalizer circuitry with three stages in series. Each stage includes a peaking inductor circuitry. Furthermore, the equalizer circuitry may include controllable, variable, static, DC mode offset voltage compensation and/or dynamic, continuous mode offset voltage compensation circuitry for respectively reducing a DC voltage offset and/or time-varying a continuous mode voltage offset between an output of the third equalizer stage and the utilization circuitry to which said output is applied. The first equalizer stage may be configured to have controllable variable impedance.
Document U.S. Pat. No. 8,274,326 B2 discloses a continuous-time linear equalizer with differential amplifiers, differential high-pass filters and current mirrors. The continuous-time linear equalizer may amplify the difference between two signals of a differential input signal using the differential amplifiers and other circuitry coupled thereto. In this manner, the continuous-time linear equalizer may actively compensate for channel losses that would otherwise occur at higher frequencies. Moreover, the equalizer may provide an amplifier gain factor that enables an equalization of the frequency response of a communication channel over any frequency range.
Document US 2008/0101450 A1 discloses a continuous-time linear equalizer with a differential amplifier stage followed by a stage with PMOS transistors, drains of which are coupled to the supply power and sources of which are coupled via a resistive element to the gate of the respective transistor. Furthermore, current sources are applied and may be controlled to provide offset correction in order to move a center of the data eye to a desired voltage.
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