To provide consumers with increasing functionality at lowest possible cost the electronics industry is driving towards products which are smarter, faster and smaller. This evolution is being promoted by advances in semiconductor materials and fabrication technology, such as multilayer IC (integrated circuits), submicron IC features and large scale integration. Packaging and interconnect technologies play a key supporting role in the evolution. Materials for packaging and interconnect technologies must support high yield fabrication, high density packaging, fast signal propagation and compatibility with surface mount and direct attach of components. To meet these requirements reinforcements with lower in-plane CTE (coefficient of expansion), greater dimensional stability, lower dielectric constant and smooth surfaces are needed.
CTE is an important property for the printed wiring board (PWB) substrate especially in the surface mount and direct attach chip applications. CTE mismatch between the chip (or chip carrier) and the board pose reliability problems due to potential solder joint cracking during thermal cycling. Various techniques were developed to insure some reliability of the solder joints, e.g., "J" leads, gull wing leads, leaded chip carriers and leadless chip carriers. However, the high (13-18 ppm/.degree. C) in-plane CTE of the standard epoxy/E-glass or polyimide/E-glass still resulted in some solder joint failures. In order for components to successfully survive environmental testing, in-plane CTE's of 8-10 ppm/.degree. C are necessary.
The successful production of multilayer PWBs also requires layer-to-layer pad registration and registration of through holes to pads. During fabrication of PWBs, laminate materials experience a number of thermal excursions, including bake cycles at 120.degree.-150.degree. C. and short exposures to temperatures as high as 280.degree. C. In general, these thermal exposures cause dimensional change in the laminate materials.
Normally, and especially in the case of p-aramid fibers, the fiber CTE is much lower than the resin CTE. It is possible to make low CTE laminates using very low resin contents (&lt;40 wt. %), where the fiber properties dominate the composite properties. However, this laminate would have low peel strength, voids, etc. and would not meet all the property requirements for a reliable PWB, and is not a practical route to make PWBs.
USPTO Backgrounds
USPTO Backgrounds