The present invention is generally in the field of semiconductor fabrication. More particularly, the present invention is in the field of fabrication of memory arrays.
Non-volatile memory arrays are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory arrays include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) arrays. EEPROM devices differ from other non-volatile memory arrays in that they can be electrically programmed and erased. Flash memory arrays are similar to EEPROM arrays in that memory cells can be programmed and erased electrically. However, flash memory arrays enable the erasing of all memory cells in the memory array using a single current pulse.
Product development efforts in flash memory arrays have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times, reducing cell dimensions, and increasing drive current. By reducing cell dimensions, flash memory arrays can achieve increased speed and reduced power consumption. As the flash memory cell is reduced in size, the flash memory cell""s channel width is also reduced in size, which reduces the size of the flash memory array. By way of background, in a floating gate flash memory array, channel width can be defined as the distance between adjacent isolation regions, such as shallow trench isolation (STI) regions. The drive current, which refers to the current that flows between drain and source regions of the flash memory array, can be increased by the increasing the channel width. However, in a conventional flash memory array, an increase in channel width causes an undesirably increase in the size of the flash memory array.
Thus, there is a need in the art for a flash memory array, such as a floating gate flash memory array, having increased drive current, where the increased drive current is achieved without increasing the size of the flash memory array.
The present invention is directed to structure for increasing drive current in a memory array and related method. The present invention addresses and resolves the need in the art for a flash memory array, such as a floating gate flash memory array, having increased drive current, where the increased drive current is achieved without increasing the size of the flash memory array.
According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array may be, for example, a floating gate flash memory array. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom.
According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer, where the channel region extends along the trench sidewalls and trench bottom, where the channel region has an effective channel width, and where the effective channel width increases as a height of the trench sidewalls increases. The increase in the effective channel width causes an increase in the drive current in the memory array. The memory array might further comprise a floating gate layer situated over the tunnel oxide layer, where the floating gate layer is situated in the trench. The memory array might further comprise an ONO stack situated over the floating gate layer. The memory array might further comprise a word line situated over the ONO stack.
According to one embodiment, the invention is a method for achieving the above-described memory array. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.
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