1. Field of the Invention:
This invention relates generally to integrated circuit structures, and specifically to (1) oxide isolated integrated injection logic circuits utilizing a PNP and an NPN transistor wherein a lessened resistance between the collector of the PNP transistor and the base of active NPN transistor is desired, to (2) oxide isolated integrated injection logic circuits utilizing a PNP and an NPN transistor wherein a PNP V.sub.BE larger than the NPN V.sub.BE is desired, and to (3) oxide isolated integrated circuits utilizing double diffused lateral transistor structures.
2. Description of the Prior Art:
Circuits and structures utilizing integrated injection logic, sometimes abbreviated I.sup.2 L or referred to as merged transistor logic, are well known in the integrated circuit arts. Such logic circuits or structures reduce a logic gate to a pair of merged complementary transistors in which a lateral PNP transistor is typically used as a current source for the base of an inverted NPN transistor. The NPN transistor, with a buried N type region as an emitter, will frequently have multiple collectors which may be used to drive other logic elements in a given circuit. I.sup.2 L circuits possess the inherent advantage of being compact because a logic gate is reduced to a single semiconductor device. Further, I.sup.2 L circuits can operate at very low voltages and can be simply fabricated utilizing relatively few masking operations.
Integrated injection logic circuit structures and the techniques by which they may be fabricated have been the subject of many papers and patents. See, for example, H. H. Berger and S. K. Weidman, "Merged Transistor Logic (MTL) --A Low-Cost Bipolar Logic Concept", K. Hart and A. Slob, "Integrated Injection Logic: A New Approach to LSI", both in Journal of Solid-State Circuits, Vol. SC-7, 1972, at pp. 340-346 and pp. 346-351, respectively; H. H. Berger and S. K. Wiedman, "The Bipolar LSI Breakthrough, Part I, and Part II, Electronics, Sept. 4, 1975, pp. 89-95 and Oct. 2, 1975, pp. 99-103; and U.S. Patent application Ser. No. 578,060, entitled "Combined Method for Fabricating Oxide-Isolated Vertical Bipolar Transistors and Complimentary Oxide-Isolated Lateral Bipolar Transistors and the Resulting Structures", assigned to Fairchild Camera and Instrument Corporation. A multiple collector structure for bipolar transistors is desribed in U.S. Patent application Ser. No. 657,439 entitled "Graduated Multiple Collector Structure for Inverted Vertical Bipolar Transistors" of Crippen, Hingarh and Verhofstadt and assigned to Fairchild Camera and Instrument Corporation.
One method of forming oxide isolated semiconductor structures is described in U.S. Pat. No. 3,648,125, entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure", by D. L. Peltzer, and assigned to Fairchild.
An oxide isolated double diffused lateral transistor structure, and an oxide isolated integrated injection logic structure appear as FIGS. 2 and 5A respectively, in U.S. Pat. No. 3,873,989, entitled "Double-Diffused Lateral Transistor Structure" issued Mar. 25 1975, to R. D. Schinella and M. P. Anthony and assigned to Fairchild.
Prior art structures, for example, as depicted in FIGS. 2 and 5A of U.S. Pat. No. 3,873,989, required undesirably large amounts of wafer surface for their fabrication. In one embodiment, the typically silicon nitride layer 56 of U.S. Pat. No. 3,873,989 was five to six microns wide (as measured from edge 57 to edge 95 in FIG. 2). This width was required to insure that during manufacture the P+ collector contact would not diffuse through the epitaxial layer and relatively narrow PNP transistor base to contact the P+ emitter thereby shorting the transistor.
The relatively wide silicon nitride layer of prior art structures results in a relatively wide region of P- epitaxial silicon being disposed between the base and the collector contact of the PNP transistor. In I.sup.2 L structures with double diffused PNP transistors all but the relatively narrow N type base region was P type epitaxial material, and because of its resistivity, the P type material caused an undesirably large voltage drop between the collector of the PNP transistor and the base of the NPN transistor. Because this voltage drop is caused by the impurity concentration of the epitaxial layer, the resistance across which the voltage drop occurs will be referred to herein as the epitaxial resistance, and the equivalent resistor in a schematic diagram as the epitaxial resistor.
Existing I.sup.2 L circuits function adequately at lower operating currents, but at higher currents the resistance of the epitaxial resistor typically on the order of one to two thousand ohms, significantly reduces the flow of current from the emitter of the PNP transistor to the base of the NPN transistor thereby slowing the operating speed and decreasing the gain of the I.sup.2 L circuit. In some prior art devices only about 50% of the current flowing through the PNP emitter reached the NPN base. Because the voltage drop becomes more severe at increasing operating currents and for multiple collector embodiments of the NPN transistor, large arrays of I.sup.2 L circuit elements are difficult to fabricate, and even when successfully fabricated, operate at undesirably slow speeds.
USPTO Backgrounds
USPTO Backgrounds