The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a complementary MOS integrated circuit with wells and a method of manufacturing the same.
As integrated circuits are miniaturized more and more, memories such as DRAM memories introduce a vertical structure more often than a conventional planar structure. Capacitors of a trench structure are therefore used in such DRAM memories. Various problems are encountered, however, in the manufacture of memories with trench capacitors. One problem is that the well is made deep in order to suppress leakage between trenches of shallow wells.
A conventional method of forming a twin well in a complementary CMOS integrated circuit (hereinafter simply called CMOS IC) will be described with reference to FIGS. 4A to 4F.
A p-type silicon substrate 1 having impurity condition of 1.times.10.sup.15 to 5.times.10.sup.15 cm.sup.-3 is subjected to thermal oxidation under an oxygen atmosphere to form a first oxide film 2 having a thickness of 1000 angstroms (FIG. 4A).
A photoresist 3, deposited on the first oxide film 2, is selectively patterned so as to remain on the region where an n-type well is to be formed in order to form a p-type well. By using this photoresist 3 as a mask, boron ions are injected. In this case, a first damage layer 4 is formed by inactive borons (FIG. 4B).
Next, in order to form an alignment mark to be used at the succeeding photoetching process, the oxide film 2 on the p-well region is removed using ammonium fluoride liquid (NH.sub.4 F) and using the photoresist 3 as a mask. Thereafter, the photoresist 3 is removed (FIG. 4C).
In order to form the alignment mark for the photoetching process, a p-type well 6 is formed through thermal diffusion of boron ions under oxidation atmosphere. In this case, an oxide film 5 is formed at the same time on the p-type well so that a step or a level difference between oxide films is formed on the surface of the silicon substrate 1, of which the step is used as the alignment mark (FIG. 4D).
Next, a photoresist 7 is selectively patterned on the p-type well region. By using the patterned photoresist 7 as a mask, phosphorus ions are injected. In this case, a second damage layer 8 is formed by inactive phosphorus ions (FIG. 4E).
Next, after removing the photoresist 7, thermal diffusion is carried our for the purpose of activation of impurities and obtaining a desired diffusion depth, to thereby form an n-type well 9 and thus a twin well (FIG. 4F). Thereafter, a trench capacitor is formed on the semiconductor substrate by using suitable conventional manufacturing methods.
In the above conventional technique, thermal diffusion under an oxygen atmosphere for the exposed p-type well region on the silicon substrate 1, for example, at step shown in FIG. 4C, may cause Oxidation-induced stacking Faults (OSF). OSFs occur more often in a p-type boron ion injection region than in an n-type phosphorus ion injection region, and increase in proportion with the ion injection dosage. In addition, in forming trench capacitors in DRAM memories, as described previously, it is necessary to form a deep p-type well region in order to suppress leakage between trenches. In order to form a deep p-type well, it is necessary to increase the boron ion injection dose and form at first a p-type well, so that OSFs are likely to occur.
Furthermore, a process of patterning a photoresist is required to be carried out twice in forming a twin well, thereby posing an increased number of manufacturing processes.
USPTO Backgrounds
USPTO Backgrounds