(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making closely spaced electrical connections to the self-aligned source/drain contacts on field effect transistors, where the spacings between electrical connections extend beyond the photolithographic resolution limit.
(2) Description of the Prior Art
In the past few years, advances in the high resolution photolithography and directional plasma etching in semiconductor process technologies have dramatically decreased the device feature size and increased the circuit density resulting in high device performance on integrated circuit chips. The device most used for Ultra Large Scale Integration (ULSI) is the Field Effect Transistor (FET), typically using a silicon gate electrode and having self-aligned source/drain contact areas. The popular choice of FETs is because of their very small size, high packing density, low power consumption, high yields, and low cost.
The conventional FETs are typically fabricated by patterning polysilicon gate electrodes over a thin gate oxide on a single crystal semiconductor substrate. The gate electrode structure on sub-micrometer channel length FETs is itself used as an implant barrier mask to form self-aligned lightly doped source/drain areas, often referred to as the LDD areas, in the substrate adjacent to the sides of the gate electrode. Sidewall insulating spacers formed next serve to mask the LDD areas, and the source/drain contact areas are then formed by ion implantation. The spacings between the source junction and drain junction adjacent to, and on each side of the gate electrode are therefore quite close.
The advances in high resolution photolithographic techniques and directional (anisotropic) plasma etching have reduced the minimum feature sizes, such as the width of the FET gate electrode (not to be confused with the FET channel width) over and along the FET channel length to well below a micrometer (um). For example, FETs are currently used in the industry having channel lengths that are less than a half micrometer (0.5 um) in length, and are expected to be about 0.25 um by the year 1998. If further increases in circuit density and device performance are to continue, then device minimum feature sizes, and more specifically the FET channel length, must be reduced to sub-half-micrometer dimensions (that is, to less than 0.5 um). This requires improved photoresist and exposure tools that improve the photolithographic resolution or, alternatively, process methods that extend the resolution of the current photoresist systems.
Because of this downscaling and the further reduction in the FET channel length, it becomes increasingly difficult to form the electrical connections to the self-aligned source/drain areas on each side of the FET gate electrode. These electrical contacts are usually formed by patterning a conductively doped polysilicon layer or polycide (polysilicon/silicide) layer that extend over the source/drain contacts, but are electrically separated from each other. Unfortunately, because of the photolithographic resolution and limitations in aligning the photoresist mask for patterning the polysilicon layer, misalignment can result in silicon trenches being etched in the substrate adjacent to the gate electrodes. These unwanted trenches degrade or destroy the field effect transistor devices. This misalignment can also result in these unwanted trenches being formed in the silicon substrate adjacent to the narrow field oxide regions that separate the individual device areas of the FETs.
Therefore, there is still a strong need in the semiconductor industry for making electrical connections to the self-aligned source/drain contacts on FETs, while avoiding the occurrence of misaligned photoresist masking, for etching the polysilicon layer that make the electrical contacts to the FET source/drain areas.
USPTO Backgrounds
USPTO Backgrounds