1. Field of the Invention
The present invention relates to a memory device having a semiconductor memory unit, a host device connecting with the memory device, and a method for adjusting a sampling clock of the host device and, in particular, to the memory device connecting to a host device configured to adjust a sampling clock.
2. Description of the Related Art
Memory devices including a semiconductor memory unit, for example memory cards that include a non-volatile semiconductor memory unit have been developed in recent years and are widely used as external storage devices for information apparatuses such as digital cameras, which are host devices to which the memory cards are connected. So-called embedded memory systems in which a memory device is incorporated into a host device also have found wide applications.
In a memory system consisting of a memory device and a host device, the host device and the memory device send and receive a clock signal to and from each other through a clock line, a command signal and a response signal through a command line, and a data signal and a status signal through a data line.
When the host device reads data from the memory device, the host device sends a clock signal to the memory device through the clock line, the memory device outputs the data in synchronization with the clock signal provided from the host device, and then the host device takes the data signal in synchronization with the clock signal.
There is a demand for higher data transfer rates between host and memory devices, that is, higher write speeds and the readout speeds. However, as the transfer rate increases, that is, as the frequency of a clock signal increases, the effect of the read delay time between the output of the clock signal from the host device and the input of data to the host device becomes more noticeable. Consequently, it becomes difficult for the host device, which is in synchronization with the clock signal it sent, to take data in an accurate timing.
Therefore, for example Japanese Patent Application Laid-Open Publication No. 2008-90556 discloses a memory card that is accessed by a host apparatus in which a clock input circuit receives a first clock signal from the host apparatus through a clock line, a data input-output circuit receives a second clock signal from the host apparatus through a data line in a write timing adjustment mode and sends a third clock signal in a read timing adjustment mode.
USPTO Backgrounds
USPTO Backgrounds