Microprocessor systems have until recently been interconnected via multi-drop data buses. The processors, memory controllers, input-output controllers (which may generally be termed “agents”) would be able to exchange data over a common data bus structure. However, as data transmission rates become higher, limitations in the multi-drop data buses are becoming a problem. The electrical loadings and reflections in a multi-drop data bus system may limit the data transmission speed. In order to address these and other issues, newer systems are examining individual, dedicated point-to-point data interfaces between the agents of a system.
There will still exist variances among agents attempting to exchange data via the point-to-point interfaces. Source impedances, path impedances, and termination impedances may all vary due to process variations and other influences. Data skew among the various parallel data lines, and between the clock and data lines, may become more of a problem at higher data rates. For this reason, during an initialization process the two agents at the opposite ends of the point-to-point interface may exchange special data messages to support the initialization process. After the initialization process, it may still be possible for there to be changes in the data skew, requiring periodic retraining of the skew compensation circuits. Such retraining may interfere with the flow-control mechanism, which in one embodiment may include a link-layer protocol, which ensures error-free data transmission.
USPTO Backgrounds
USPTO Backgrounds