1. Field of the Invention
The present invention relates to a semiconductor memory circuit, and specifically to a semiconductor memory circuit having shift redundancy circuits used for substituting a redundancy memory cell for a defective memory cell.
2. Description of the Related Art
Recently, remarkable developmen ts have been made in a semiconductor memory circuit as a result of an improved technique of forming fine semiconductor elements, and an accessing speed of writing and reading data has been increased.
However, if the access speed is accelerated as described above, especially in the case of a synchronous semiconductor memory circuit, in the conventional redundancy circuit of a redundancy memory cell substituting type, selecting speeds of the redundancy memory cell and a normal memory cell become different from each other when the redundancy memory cell is substituted for the n ormal memory cell. Therefore, there is a tendency to use a shift redundancy circuit which does not generate a difference in selecting speed of the redundancy and normal memory cells.
FIG. 1 is a block diagram showing a conventional semiconductor memory circuit of the redundancy memory cell substituting type having the shift redundancy circuits.
Memory cell arrays MC11 to MC18 and a redundancy memory cell array MCR1 are connected to corresponding sense amplifier/write buffers SA11 to SA18 and SAR1 through corresponding column decoders YS11 to YS18 and YSR1 when the column decoders are selected.
An input/output signal line WA11 connected to the sense amplifier/write buffer SA11 and an input/output signal line WA12 connec ted to the sense amplifier/write buffer SA12 are connected to input terminals of a shift redundancy circuit SF11.
Similarly, input/output signal lines WA12 to WA18 and WAR1 respectively connected to the sense amplifier/write buffers SA12 to SA18 and SAR1 are connected to input terminals of shift redundancy circuits SF12 to SF18. Switch signal lines FS11 to FS18 to which fuse elements FA11 to FA18 on an output line of a program circuit PR11 are connected are connected to the shift redundancy circuits SF11 to SF18, and the switch signal lines FS11 to FS18 are connected to a control terminal.
In the program circuit PR11, a fuse element FAP1 and a resistance element R11 are connected to each other in series between a power supply potential VCC and a ground potential GND. A potential of a node between the fuse element FAP1 and the resistance element R11 is output to the fuse elements FA11 to FA18 through inverters INV13 and INV14.
A structure and an operation of the shift redundancy circuit will be described below. FIG. 2 is a circuit diagram showing the shift redundancy circuit.
The shift redundancy circuit is provided with a switch signal line FS to which a switch signal for the shift redundancy circuit is transmitted. An inverter INV5 and gates of an N-channel MOS transistor MN1 and a P-channel MOS transistor MP2 are connected to the switch signal line FS. The shift redundancy circuit is further provided with a P-channel MOS transistor MP1 having a source and a drain respectively connected to a source and a drain of the N-channel MOS transistor MN1 and an N-channel MOS transistor MN2 having a source and a drain connected to a source and a drain of the P-channel MOS transistor MP2. A gate of the P-channel MOS transistor MP1 is connected to a gate of the N-channel MOS transistor MN2 at a node, and the inverter INV5 is connected between the node and the switch signal line FS. Thus, the N-channel MOS transistor MN1 and the P-channel MOS transistor MP1 constitute a transfer-gate switch circuit TF1, and the N-channel MOS transistor MN2 and the P-channel MOS transistor MP2 constitute a transfer-gate switch circuit TF2.
Furthermore, an input/output signal line Wai is connected to one of the nodes connecting the sources and drains in the two MOS transistors of the switch circuit TF1, and an input/output signal line Wbi is connected to one of the nodes connecting the sources and drains of the two MOS transistors in the switch circuit TF2. A signal line Wci is connected to the other nodes of the switch circuits TF1 and TF2.
The switch signal line FS corresponds to the switch signal lines FS11 to FS18 in FIG. 1, and the input/output signal lines Wai and Wbi correspond to the input/output signal lines WA11 to WA18 and WAR1 in FIG. 1. The signal line Wci corresponds to signal lines OA11 to OA18 in FIG. 1.
The shift redundancy circuit formed in the above manner operates so that the switch circuit TF2 is turned off when the switch circuit TF1 is turned on, and the switch circuit TF2 is turned on when the switch circuit TF1 is turned off.
When the signal line FS is at a VCC level, for example, the switch circuit TF1 is turned on and the switch circuit TF2 is turned off. Then, a level of the signal line Wai is transmitted to the input/output signal line Wci.
When the signal line FS is at a GND level, on the other hand, the switch circuit TF1 is turned off and the switch circuit TF2 is turned on. Then, a level of the signal line Wbi is transmitted to the input/output signal line Wci.
An operation of the conventional semiconductor memory circuit in a case in which a defective memory cell array does not exist and the redundancy memory cell array is not substituted for a defective memory cell array by the shift redundancy circuit will be described below. In this case, a signal at a VCC level is output from the program circuit PR11 and the VCC level is transmitted to all of the signal lines FS11 to FS18. Then, a level of the input/output signal line WA11 is output to the signal line OA11 connected to the shift redundancy circuit SF11. Similarly, levels of the input/output signal lines WA12 to WA18 are respectively output to the input/output signal lines OA12 to OA18.
Next, a case in which a defective memory cell array exists for which the redundancy memory cell array is substituted will be described, supposing that the memory cell array MC15 is defective. In this case, the fuse element FAP1 in the program circuit PR11 and the fuse element FA15 are cut. As a result, a signal at a GND level is output from the program circuit PR11, and the GND level is transmitted to the switch signal lines FS15 to FS 18. Then, a level of the input/output signal line WA16 is output to the signal line OA15, a level of the input/output signal line WA17 is output to the signal line OA16, a level of the input/output line WA18 is output to the signal line OA17, and a level of the input/output signal line WAR1 is output to the signal line OA18.
On the other hand, the VCC level is transmitted to the switch signal lines FS11 to FS14, even in a state in which the fuse element FA15 is cut. Consequently, output levels of the signal lines OA11 to OA14 equal the levels of the input/output signal lines WA11 to WA14, respectively.
A level of the input/output signal line WA15 corresponding to the defective memory cell array MC15 is interrupted by the shift redundancy circuits SF14 and SF15, and is not output to any of the signal lines OA14 and OA15.
In the system of substituting the redundancy memory cell using the shift redundancy circuits SF11 to SF18 as described above, a difference is not generated between speeds of selecting the redundancy memory cell and the normal memory cell. Therefore, the redundancy memory cell substituting system is used more frequently for a high-speed semiconductor memory circuit and a synchronous semiconductor memory circuit, as compared to a normal redundancy system in which a difference exists in speeds of selecting the redundancy memory cell and the normal memory cell.
However, when the shift redundancy circuits are used, whether or not the redundancy memory cell is substituted, the signal levels are transmitted to the shift redundancy circuits SF11 to SF18 by the input/output signal lines WA11 to WA18 and WAR1, as described above. As a result, because the column decoder and the sense amplifier/write buffer corresponding to the defective memory cell array keep on operating, an operating current is increased as compared with that in a normal semiconductor memory circuit.
Therefore, a semiconductor memory circuit, which is provided with killer signal generating circuits for inactivating the column decoder and the sense amplifier/write buffer connected to the defective memory cell array, is necessary.
Such a killer signal generating circuit will be described below. FIG. 3 is a circuit diagram showing the killer signal generating circuit.
In the killer signal generating circuit, a fuse element FAR and a resistance element R12 connected to each other in series are provided between a power supply potential VCC and a ground potential GND. An inverter INV15 to which another inverter INV16 is connected in series is connected to a node between the fuse element FAR and the resistance element R12. A signal line RK1 is connected to the inverter INV16.
In the killer signal generating circuit formed in the above manner, in a case in which the redundancy memory cell array is not substituted, the fuse element FAR is not cut, and the VCC level is transmitted to the signal line RK1 through the inverters INV15 and INV16. In a case in which the redundancy memory cell array is substituted, on the other hand, the fuse element FAR is cut, and the GND level is transmitted to the signal line RK1.
FIG. 4 is a block diagram showing a conventional redundancy memory cell substituting semiconductor memory circuit having killer signal generating circuits and shift redundancy circuits. In the prior art shown in FIG. 4 (the second prior art), components similar to those in the prior art shown in FIG. 1 (the first prior art) are provided with similar reference numerals to omit detailed descriptions.
The second prior art is provided with killer signal generating circuits KR1 to KR8 and KRR for outputting killer signals EB1 to EB8 and EBR to column decoders YS11 to YS18 and YSR1 and sense amplifier/write buffers SA11 to SA18 and SAR1, respectively.
If a redundancy memory cell is not substituted, a fuse element in the killer signal generating circuit KRR is cut. As a result, the killer signal EBR acquires the GND level, and the column decoder YSR1 and the sense amplifier/write buffer SAR1 are inactivated.
On the other hand, fuse elements in the killer signal generating circuits KR1 to KR8 are not cut. For this reason, the killer signals EB1 to EB8 acquire the VCC level, and the column decoders YS11 to YS18 and the sense amplifier/write buffers SA11 to SA18 are not inactivated.
Next, a case in which a redundancy memory cell is substituted will be described. In a case in which a memory cell array MC15 is defective, for example, the fuse element in the killer signal generating circuit KR5 is cut. As a result, because the killer signal EB5 acquires the GND level, the column decoder YS15 and the sense amplifier/write buffer SA15 are inactivated.
In this manner, in the second prior art, the killer signal generating circuits KR1 to KR8 and KRR are necessary to completely inactivate one of the column decoders YS11 to YS18 and YSR1, and one of the sense amplifier/write buffers SA11 to SA18 and SAR1 based on whether or not the defective memory cell array exists. The technique of forming a finer semiconductor memory circuit has been improved recently, as described above, and transistors constituting an internal circuit has been made finer, but fuse elements are scarcely made finer. Therefore, according to the second prior art which includes large number of fuse elements in the killer signal generating circuits KR1 to KR8 and KRR, the size of a chip increases.
In other words, in the second prior art in which the operating current can be decreased, the fuse elements in the killer signal generating circuits can not be disposed in a layer below the signal lines and the like, but require exclusive spaces. In a case in which the size of the chip is approximately 25 mm.sup.2, the size of the chip increases by about 10%.
In a case in which diffusion is conducted in a wafer of a 6-inch size, for example, if the killer signal generating circuit is not provided, a number of available pellets is 600 in a chip of 25 mm.sup.2, while the number of available pellets decreases by 60 per a wafer and becomes 540 in a chip of about 27.5 mm.sup.2, if the killer signal generating circuits are provided.
As described above, in the first prior art in which the shift redundancy circuits are used for substituting the redundancy memory cell, the operating current increases considerably, because all the column decoder and sense amplifier/write buffer circuits having the circuits which are not used operate.
The second prior art having the killer signal generating circuits for decreasing the operating current, on the other hand, suffers from a problem of an increased size of the chip.
USPTO Backgrounds
USPTO Backgrounds