DRAM is provided with memory cells, each of which comprises a data storage capacitor and a data transfer transistor. For storing data into the memory cell, a voltage corresponding to a logic value (“1” or “0”) of the storage data is applied to the data storage capacitor to store a charge according to this voltage. In this data storage capacitor, a variety of current leak path is present, which causes that the charge accumulated in the data storage capacitor is gradually decreased over times, resulting in a deterioration of the data stored in the memory cell. For this reason, DRAM performs a cyclic or periodic refresh operation for refreshing the data of the memory cells.
There is a variety of refresh methods, for example, a CAS before RAS for supplying, from outside, a necessary signal for refresh and an auto-refresh for refreshing in accordance with an address internally generated upon receiving an externally supplied trigger, and further a self-refresh for automatically refreshing inside. The semiconductor memory device utilizing the above-described self-refresh method integrates a timer circuit for generating a clock signal with a constant cycle, so that the lock signal generated by this timer circuit is counted to obtain a refresh timing without any external control.
A structure of the timer circuit in accordance with the prior art and a method of setting a cycle of the clock signal to be generated by this timer circuit will, hereinafter, be described.
FIG. 1 shows a circuit configuration of the conventional timer circuit. The conventional timer circuit comprises a current mirror circuit, a resistance RR acting as a load to a primary side of this current mirror circuit, a ring oscillator acting as another load to a secondary side of the current mirror circuit and a buffer circuit.
The primary side load resistance RR acting as the load to the primary side of the current mirror circuit is connected at its one terminal to a power supplied from outside. As this primary side load resistance RR, an interconnection material, for example, polysilicon may be used.
The current mirror circuit comprises three n-channel MOS transistors N1˜N3 and two p-channel MOS transistors P1 and P2. The current mirror circuit controls a secondary current based on a primary current which flows through the above-described primary side load resistance RR. An input side of the ring oscillator is connected to a secondary side of the current mirror circuit, so that the ring oscillator acts as a load to the secondary side of the current mirror circuit. The ring oscillator comprises three inverters I1˜I3 which are connected in ring-shape. Delay-purpose capacitors C1˜C3 are respectively connected to output ports of the inverters I1˜I3. An input port of the buffer circuit B is connected to an output port of the inverter I3, so that the buffer circuit B receives an input of an oscillation signal outputted from the inverter I3, and outputs a clock signal CLK. In the below-description, a cycle of the clock signal CLK is so called to as “timer cycle”.
Sources of the n-channel MOS transistors N1˜N3 forming the above-described current mirror circuit are commonly grounded. Gates of these n-channel MOS transistors N1˜N3 are connected to a drain of the n-channel MOS transistor N1. The drain of the n-channel MOS transistor N1 is connected to another end of the primary side load resistance RR. A drain of the n-channel MOS transistor N3 is connected to each of ground nodes of the inverters I1˜I3. Transconductances gm1 and gm2 of the n-channel MOS transistors N1 and N2 are equal to each other. A transconductance gm3 of the n-channel MOS transistor N3 is set at such an appropriate value as providing a ground potential to the inverters I1˜I3. In accordance with the conventional circuit configuration, the transconductance gm3 of the n-channel MOS transistor N3 is larger by integer number times than that of the n-channel MOS transistor N1. The n-channel MOS transistors N1 and N3 constitute the current mirror circuit with the primary side load resistance RR which acts as the load to the primary side thereof for supplying the ground potential to the inverters I1˜I3.
Sources of the p-channel MOS transistors P1 and P2 are commonly connected to the power. Gates of the p-channel MOS transistors P1 and P2 are connected to a drain of the p-channel MOS transistor P1. A drain of the p-channel MOS transistor P2 is connected to respective power nodes of the inverters I1˜I3. A drain of the p-channel MOS transistor P1 is connected to a drain of the above-described n-channel MOS transistor N2. A transconductance gm5 of the p-channel MOS transistor P2 is set at such an appropriate value as providing a ground potential to the inverters I1˜I3. A transconductance gm4 of the p-channel MOS transistor P1 is larger by integer number times than that of the p-channel MOS transistor P2. The p-channel MOS transistors P1 and P2 constitute the current mirror circuit with the above-described n-channel MOS transistor N2 which acts as the load to the primary side thereof for supplying the ground potential to the inverters I1˜I3.
Subsequently, an operation of the conventional timer circuit will be described.
If a power voltage externally supplied is constant, then a current flowing through the resistance RR is definitely decided depending upon both a resistance value of this resistance RR and the transconductance gm1 of the n-channel MOS transistor N1. This current flowing through the resistance RR also flows through the n-channel MOS transistor N1. Gates of the n-channel MOS transistors N1˜N3 are commonly applied with a voltage which appears at a connection point between the resistance RR and the drain of the n-channel MOS transistor N1. Therefore, ratios of the currents respectively flowing through those n-channel MOS transistors N1˜N3 are defined depending upon those transconductances gm. In this example, a current flowing through the n-channel MOS transistor N2 is almost equal to a current flowing through the n-channel MOS transistor N1. A current flowing through the n-channel MOS transistor N3 is larger by an integer time than a current flowing through the n-channel MOS transistor N1.
A current flowing through the p-channel MOS transistor P1 is equal to a current flowing through the n-channel MOS transistor N2 and thus is equal to a current flowing through the resistance RR. The transconductance gm5 of the p-channel MOS transistor P2 is larger by an integer time than that of the p-channel MOS transistor P1. For this reason, the current flowing through the p-channel MOS transistor P2 is larger by an integer time than the current flowing through the p-channel MOS transistor P1, and thus is larger by an integer time than the current flowing through the resistance RR.
As described above, in this timer circuit, a power current supplied to the inverters I1˜I2 is controlled by the resistance value of the resistance RR.
A method of setting the timer cycle (the cycle of the clock signal) will subsequently be described by taking an example of using this timer circuit as a timer for refreshing DRAM.
FIG. 2 shows a temperature dependency of the timer cycle of the conventional timer circuit. A horizontal axis represents a temperature T(° C.), while a vertical axis represents a variation ΔF(%) of the timer cycle. The timer cycle variation ΔF(%) shows a tendency of a gentle and linear increase upon temperature increase. In a temperature range of −30° C. to 90° C., the increase of the timer cycle variation ΔF(%) tends to be generally gentle. Such characteristic is due to a temperature-characteristic of the resistance RR. In general, in case of DRAM utilizing a specification providing a refresh cycle from outside, a flat characteristic of the timer circuit providing the refresh timing is preferable as shown in FIG. 2. This is generally caused by the fact that a cycle of a signal given from outside for refresh operation does not accord to the temperature characteristic of the semiconductor memory device.
If the power voltage (VDD) is high, then a voltage at a memory node of the memory cell is high, which causes an increase in leakage of current, whereby a data hold characteristic of the memory cell tends to show a flat characteristic. If the data hold characteristic of the memory cell has the flat characteristic with reference to the power voltage, then it is preferable that the timer circuit has a flat characteristic as shown in FIG. 2.
For designing a semiconductor memory device integrating a timer circuit for refresh, the timer cycle is so set that, in consideration of a power voltage variation and a temperature variation, the refresh operation is ensured under a most strict condition in view of voltage and temperature. Namely, as shown in FIG. 2, as the temperature is high and the voltage is high, the timer cycle is long and the refresh operation condition is strict. Thus, it is necessary to ensure the refresh operation under such the strict operation condition. For this reason, the timer cycle is set to obtain a necessary time interval for refresh under operation conditions (worst conditions) that the temperature is highest and the power voltage is also highest.
The semiconductor memory device integrating the timer circuit in accordance with the above-described prior art tends to show an increase of the timer cycle upon temperature increase. If the timer cycle is so set as to ensure the refresh operation under the worst condition (high temperature), then under other conditions than the worst conditions, for example, the typical conditions, the timer cycle is shorter than that under the worst conditions.
In general, the data hold characteristic of the memory cell tends to be deteriorated as temperature is high, for which reason it is necessary that the time interval for refresh operations is shorter by temperature increase. As the temperature is low, the time interval for refresh operations may be long. If the timer cycle is set to adjust to the worst conditions, then at a lower temperature than the high temperature of the worst condition, for example, at an ordinary or low temperature, the timer cycle is shorter than that under the worst condition, whereby the refresh operations will be made at an excess frequency, and such excess refresh operation causes an unnecessary current comsumption.
USPTO Backgrounds
USPTO Backgrounds