Reference to background documents refers to the “List of References” provided below.
Fast response to load transients and other disturbances as well as tight output voltage regulation are among the most important requirements in modern low-power dc-dc switch-mode power supplies (SMPS)[1], processing power that may range from a fraction of watt to several hundreds of watts. Few of many advantages of the fast transient response are listed here. In cost-sensitive point-of-load (POL) applications and portable systems, improvements in the load transient response usually result in a substantial reduction of the size and weight of the costly power stage filter components [2], for example the filter inductor and output capacitor. In distributed power systems (DPS) for personal computers and telecom, the faster control also reduces voltage and current stress on downstream converters providing more reliable operation of the supplied equipment.
Even though numerous fast transient response methods have been developed [3]-[22], in most commercial low-power SMPS, predominantly analog voltage mode pulse-width modulation (PWM) or current-program mode regulators with limited bandwidth of the voltage loop [23], [24] are used. Among the main reasons for this are the elements of the system of operation at a constant switching frequency minimizing noise problems, tight output voltage regulation, and simple cost-effective practical implementation [1].
Fast transient response methods based on various modifications of voltage-mode hysteretic control [4], [5], including those with variable hysteretic band [25] for achieving constant switching frequency, have proven to be viable for some applications. Still, in the targeted systems their use is often limited. There are several reasons for this limited use such as, for example, the voltage mode hysteretic control cannot directly be applied for boost converters [25], while in buck topologies it can compromise voltage regulation. This is because the SMPS behaves as a second-order system and a delay between the switching action and actual increase/decrease of the output voltage always exists. As a solution, current mode hysteretic controllers have been proposed [6].
Current mode hysteretic controllers can eliminate the previously mentioned problems but their practical realization is challenging. Similar to switching surface [7]-[10] and trajectory path [22]-[23] methods, these controllers often require measurement of the output capacitor current and/or a costly high gain-bandwidth current amplifying circuit. Since the complexity of these systems significantly exceeds that of a complete conventional PWM controller [1], they have not been widely adopted in high-frequency low-power SMPS.
In [11] and [22] it has been shown that for a given converter topology an optimal-time transient response can be obtained through a single on/off action of the power switches, where the on and off times are calculated based on the output capacitor charge balance [5], [7]-[9], [11]-[16]. This fast voltage recovery mechanism has been verified through simulations and through analog implementation capable of operating for a single predefined load change. No attempt has been made to create a practical system capable of operating over a wide operating range. This may be due to the requirement for a relatively complex calculation to achieve an optimal switching sequence, including on and off transistor times, which cannot be easily realized with analog hardware.
A more practical implementation, achieving optimal response for a wide range of voltage reference changes and a fast but still sub-optimal response for the load variations, has also been suggested [12]. It combines linear and nonlinear control utilizing both analog and digital circuits. The digital hardware ensures optimal response time for the voltage reference changes. In this case, the optimal switching sequences for different references are pre-calculated and stored in look-up tables. During load transients that are usually unknown the presented controller applies constant-frequency analog hysteretic control, relying on the indirect output capacitor current measurements.
A fully-digital optimal-time controller shown in [13]-[16] is well suited for converters processing larger power than the systems targeted in this invention. By using superior flexibility and computational power of a digital processor, the proposed current-program mode implementation performs on-line calculations of the switching sequence resulting in the optimal response for various loads. In this solution the fast transient response comes at the price of fairly complex controller hardware. The practical realization of this solution can be costly. It requires a fairly powerful processor, a high-gain bandwidth current sensing/amplifying circuit and three high-sampling rate analog-to-digital converters (ADC). Hence, in emerging digital controllers for low-power SMPS, digital equivalents of analog voltage mode PWM controllers [26] are still preferred and implemented over other solutions as hardware simplicity is one of the key user requirements.
In recent years digital PWM controllers for low-power SMPS have appeared as an alternative to analog systems. They offer advanced features, such as auto-tuning [27]-[29], multi-mode operation, fault-tolerant operation, design flexibility, and design portability. However, due to the sampling effect and inherent delays of digital systems, at the very best, the digital PWM controllers have dynamic characteristics slower than their analog counterparts. The slower response of the digital systems results in significantly larger and more expensive power stage components, which in most cases completely nullify all of the abovementioned advantages of digital control.
In light of the foregoing, what is needed is a digital controller with load transient response approaching physical limitations of a given power stage that is suitable for low-power SMPS. It should be realized with fairly simple components, allowing full utilization of the advantages of digital implementation without introducing a significant hardware overhead. Such a digital controller should further be able to eliminate the delay-related problems of digital systems.
In the present invention we present a solution for this problem, relying upon the use of a simple continuous-time digital signal processor (CT-DSP) [30]-[33], which executes an algorithm for the optimal-time output voltage recovery. The algorithm applied may rely on the capacitor charge balance principle [5], [7]-[9], [11], [13] and utilize detection of the peak/valley point of the output voltage deviation to eliminate the need for a costly current sensing/amplifying circuit [34].
USPTO Backgrounds
USPTO Backgrounds