1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and method thereof, and more particularly to a level shifter and method thereof.
2. Description of the Related Art
A semiconductor integrated circuit may include a main function circuit block and an interface circuit block for interfacing with external circuits. The integrated circuit block may include logic blocks operating at different supply voltages. For example, certain logic blocks may use a lower supply voltage (e.g., less than 1.2V) while other logic blocks (e.g., analog logic blocks) of the semiconductor interface circuit may use a higher supply voltage (e.g., between 2.5V and 3.3V).
Logic blocks operating at different supply voltages may include a level shifter for interfacing with other logic blocks. The level shifter may occupy a given amount of surface area on a chip and may consume a given amount of power. In a semiconductor integrated circuit with a higher integration level, the level shifter may limit an amount of gate length scaling which may thereby limit a reduction to a chip size and/or power consumption of the semiconductor integrated circuit.
FIG. 1 illustrates a circuit diagram of a conventional level shifter 100. Referring to FIG. 1, the conventional level shifter 100 may include a level shift portion 1 and a signal selection portion 2. The level shift portion 1 may include inverters 11 and 12 and a level shifter flip-flop 13. The level shifter flip-flop 13 may receive and latch an input signal A and an inverted input signal from the inverter 12. The output of the level shifter flip-flop 13 may be inverted by transistors MP24 and MN25 to output an output signal Y. The output signal Y of the level shifter 100 may have a first voltage level (e.g., a higher voltage level) which may be higher than a second voltage level (e.g., a lower voltage level) of the input signal A. A supply voltage VDD2 may correspond to the first voltage level of the output signal Y. The supply voltage VDD2 may be at a higher voltage level than a supply voltage VDD1.
The conventional level shifter 100 may include a latch circuit and a number of additional transistors to adjust a voltage level of the input signal A at a higher frequency (e.g., several gigahertz). The conventional level shifter 100 may also adjust a voltage level of the input signal A at a lower frequency (e.g., less than several hundred megahertz).
USPTO Backgrounds
USPTO Backgrounds