The known non-volatile semiconductor devices include electrically erasable and programmable read-only memory (EEPROM), for example. A memory cell of an EEPROM usually has a MISFET structure comprising a stacked gate in which a charge storage layer and a control gate are stacked on a semiconductor substrate.
In an EEPROM, an approach of making a resistance element and a MOS transistor forming peripheral circuits configured to control the operation to have the same configuration as that of a memory cell is sometimes adopted (Jpn. Pat. Appln. KOKAI Publication No. 2010-073812, for example). In a resistance element, for example, a conductive layer that is to be a charge storage layer of the memory cell is used as a resistance region (FG poly), and two stacked gate structures arranged so as to interpose the resistance region are used as an electrode portion.
USPTO Backgrounds
USPTO Backgrounds