1. Field of the Invention
The present invention relates to the general field of computers and digital design, and more particularly, to an apparatus and method for synchronizing signals travelling between a plurality of clock domains in a larger digital system.
2. Art Background
A larger digital system frequently employs a plurality of digital subsystems. When these digital subsystems operate in conjunction with the same clock in synchronous fashion, synchronization of signals travelling between these digital subsystems is not necessary. However, if these digital subystems operate in conjunction with different clocks, signals travelling between these digital subsystems must be synchronized.
Assume, for example, that the larger digital system consists of two digital subsystems, each operating in conjunction with a different clock. Signals travelling from the first digital subsystem operating with a first clock (the first clock domain) to the second digital subsystem operating with a second clock (the second clock domain) must be synchronized with the second clock. Similarly, signals travelling in the opposite direction, from the second clock domain to the first clock domain must be synchronized with the first clock. Without such synchronization, metastability problems produce invalid logic results, and the larger digital system fails as a result.
Mestastability arises when the signal input to a flip-flop in a particular clock domain does not meet that flip-flop's set-up or hold time requirements. In essence, in order for a flip-flop in a first clock domain to function properly, its input signal must be stable for a certain period of time before the flip-flop is clocked (set-up-time), and remain stable for a certain period of time after the flip-flop is clocked (hold time). A signal from a second clock domain which is not synchronized with the clock of the first clock domain, may not necessarily meet these requirements. As a result, such an input signal can place the flip-flop in a "metastable state" wherein its output is momentarily somewhere between logic 0 and logic 1. Although, the flip-flop eventually settles to a proper logic level after a finite period of time, a period of time termed "the resolution time," during the time the flip-flop is in the metastable state, it produces unpredictable logic results, results which can cause system failure.
Accordingly, a synchronizer circuit must confront and resolve the problem of metastability. In the design of such a synchronizer circuit, a number of other factors are of considerable importance. In particular, the performance of a synchronizer can be assessed by at least three measures. The first measure, termed the mean time between failures (MTBF), indicates how often, on the average, the overall system fails due to synchronizer failure. Ideally, a synchronizer has a very large MTBF, for example 10,000 years, indicating that the overall system fails due to synchronizer failure once every 10,000 years. A second measure, termed the maximum synchronization time (TMS) indicates the maximum number of clock cycles needed to complete the synchronization process. Ideally, this number is small, reflecting a minor delay caused by the synchronizer. A third measure, the maximum transfer rate (MTR) indicates how often, in clock cycles, a signal can be sent through the synchronizer. This number is ideally one, allowing an input signal to be synchronized every cycle.
Prior art synchronizers typically consisted of a number of master/slave flip-flops coupled in series. These prior art designs provided adequate synchronization under certain, limited circumstances. These circumstances included: the use of low clock frequencies, the tolerance of frequent system failures, or the tolerance of appreciable delays introduced by the synchronizer. As a general rule, prior art synchronizers necessarily sacrificed speed in order to obtain a good MTBF value. Thus, in order to prevent frequent system failure, prior art synchronizers introduced substantial synchronization delays.
With recent advances in computers and digital design, speed and performance have been placed at a premium. In computer systems and digital designs demanding high speed and performance, prior art synchronizers prove to be inadequate. As will be described, the present invention provides for a high speed and high performance synchronizer apparatus and method. The present invention provides for optimal synchronization of signals, while introducing minimal synchronizer delay.
USPTO Backgrounds
USPTO Backgrounds