1. Field of the Invention
This invention relates generally to a method of fabricating semiconductor memory cells having stacked capacitors, and more particularly to a method of fabricating stacked capacitor DRAM devices having concave structures.
2. Background of the Invention
A DRAM (Dynamic Random Access Memory) cell is a semiconductor memory device typically comprising one access transistor and one capacitor, in which one bit of data is stored in a cell by using an electric charge. One terminal of the capacitor is connected to the source of the access transistor. Another terminal of the capacitor is connected to a reference voltage. The transistor gate electrode is connected to external connection lines, e.g., bit lines or word lines.
Advances in computer applications have increased the demand for higher capacity memory chips. Decreasing the size of the memory cells allows more memory cells to be packed into an integrated circuit. A capacitor comprises of a lower conducting plate, a dielectric layer, and an upper conducting plate. The capacitance is proportional to the surface area of the conducting plates and the dielectric layer. As the area of the memory cell is decreased, the capacitance of the capacitors tends to decrease also, lowering the performance of the memory cells.
In order to increase the density of memory cells, stacked capacitors have been proposed. Stacked capacitors are made by partially stacking the storage capacitor on top of the access transistor and on top of the bit/word line, thereby effectively reducing the area used for each memory cell. Methods for further increasing the capacitance of the stacked capacitor include increasing the surface area of the capacitor plates and increasing the dielectric constant of the capacitor insulating layer.
Various methods have been proposed to increase the surface area of the electrodes of the capacitors. Because of the small size of the capacitors, it is difficult to use lithography methods to form small corrugations due to light diffraction effects. One method that has been proposed is to use ring shaped, or bathtub shaped capacitors, utilizing the side walls of the ring shape structure to increase the surface area of the capacitor plates. FIG. 1 is a cross sectional view of a stacked capacitor DRAM cell. The capacitor has a ring shape, or bathtub shape, structure with rising side walls. The side walls increase the surface area of the dielectric layer, thereby increasing the capacitor capacitance. These capacitors are fabricated using complex procedures, including a plurality of deposition, patterning, and etch-back processes. As the dimensions of the DRAM devices are further decreased, however, even this ring shaped configuration can not provide sufficient capacitance.
Recently, a method of using focused ion beam (FIB) lithography on ladder silicone spin-on glass (LS-SOG) has been proposed. The LS-SOG acts as a positive photoresist of FIB, which is patterned by exposure to ion radiation, and etched back by buffered hydrofluoric acid (BHF). (Reference: K. Suzuki, et al., JPn., J. Appl. Phys., vol. 35, P.6517, 1996). The ion-irradiated part of the LS-SOG is etched away by BHF, and a "U-shaped" cross section structure is formed in the unirradiated region due to the special property intrinsic to the LS-SOG. The smallest dimension available by the focused ion beam lithography is about 0.1 micron.
USPTO Backgrounds
USPTO Backgrounds