1. Field of the Invention
The invention relates to a method for forming semiconductor layout patterns, semiconductor layout patterns and a semiconductor structure, and more particularly, to a method for forming semiconductor layout patterns, semiconductor layout patterns and a semiconductor structure having improved process window.
2. Description of the Prior Art
Increasingly complex electronic systems require increasingly denser active devices such as transistors. Accordingly, memory cells, such as SRAM cells can get smaller by shrinking the transistor. However, it is becoming more and more difficult to further reduce the size of transistors to continue shrinking.
In conventional semiconductor processing, diffusions are typically formed in a semiconductor substrate and then gate electrodes are aligned and patterned relative to the diffusions. Please refer to FIG. 1A, which shows expected layout patterns for a semiconductor device 100. As shown in FIG. 1A, a diffusion pattern 102, which will become part of transistors is provided, and a gate pattern 104 is subsequently provided corresponding to the diffusion pattern 102. The gate pattern 104 includes an expected gate width W and an expected channel length L. It is noteworthy that a portion of gate pattern 104 must extend past the diffusion pattern 102 for a minimum distance so that the transistor can function. The region of the gate pattern 104 extending beyond the diffusion pattern 102 is referred to as the poly end cap 106.
Please refer to FIG. 1B, which shows a top-down view of the semiconductor device 100 after transferring the layout patterns to a substrate or and a layer. It is found that the transferred gate pattern 104 always suffers end shortening arising from optical effect and obtains a gate width W′ shorter than the expected gate width W. Consequently, the device is adversely impacted by the gate width loss issue. Another consideration for the poly end cap 106 is the lithography capabilities in defining the lines and shapes near the poly ends: It is found that the poly end cap 106 is rounded as shown in FIG. 1B, instead of squared. The shortened and rounded poly end cap 106 results a channel length L′ shorter than the expected channel length L, and consequently the device is adversely impacted by the channel length loss issue.
As semiconductor scaling continues, shortcomings of the conventional patterning due to optical effect as mentioned above limits the overall reliability and yield to semiconductor device. Therefore a method for forming semiconductor layout patterns having improved process window and thus the semiconductor device obtains improved reliability and yield are always in need.
USPTO Backgrounds
USPTO Backgrounds