1. Technical Field
The present invention relates to the field of generation of random numbers, and more particularly, to generation of true random numbers.
2. Discussion of the Related Art
The methods of generating random numbers can grossly be divided into two main categories: Pseudo random number generating and true random number generating. The first method produce numbers which statistically behave as random numbers but are completely deterministic, unless the pseudo number engine is being seeded by a true random number engine. The latter method, in most cases relies on physically random process as the source of entropy, like physically random noises in any electrical circuit (e.g., shot noise and thermal noise).
In various technical fields, there is a need to generate true random numbers, enhancing an existing system's hardware to generate such number without changing or adding hardware to the system, and generating such numbers inside (completely internal) an Integrated Circuit (IC), for example inside a silicon chip without dependencies on controlled external conditions. This is needed in order to prevent external security attacks.
The need to generate a true random number (or encryption key) is rising with the security needs current electronic systems are required to support. Many of the security algorithms require starting from a true random number or key which will change every time the electronic system is turned on, and between different systems of the same type. A pseudo-random number is not sufficient for this purpose since upon given initial conditions (seed) the pseudo-random number generator will generate the exact same sequence of numbers every time. Since this need can be a new requirement from an existing product that was not designed to support this requirement, the product provider is facing the problem of manufacturing a new IC, which is very costly, which now contain a dedicated random number generator circuit in order to meet the new requirement.
Several methods of generating a true random numbers are known in the art. One such example is the ring oscillator. The ring oscillator is a chain of inverters which generates an internal clock. Since the process varies this clock will have a different frequency between chips. The design then uses this clock to feed a counter which counts a certain amount of constant time which is large enough to generate differences in counting that are caused by process variation, voltage and temperature and on-die-variation. The counter value is then being read as the random number. This value will vary from chip to chip.
FIG. 1 illustrates a dedicated circuit using an n-bit Latch register 10, according to the existing art. The n-bit register 10 is made of Latches which are not circuit biased, in other words, their n-type section and p-type section are more or less the of same resistance and have more or less the same conductance (mobility of electrons and holes are more or less the same). Due to the intentional de-biasing the Latches, quasi-static state is achieved in the latch bit cell and the n-bit register in power up will stabilize on a random value. Another method of generating this random number based on quasi-static (meta-stability) is by using a cross-coupled NOR cells.
FIG. 2 illustrates yet another exemplary circuit 20 using mux trees made of mux units 22-27, according to the existing art. Using two mux trees in which depending on the select signal will go through a crossed path or a straight one and propagate the signal from the source such as a clock 21. This tree should be designed and laid out across the chip (die) to take into account also the on-die process variation. The latch 30 will output 1 if top path is faster, else 0.
USPTO Backgrounds
USPTO Backgrounds