1. Field
The present application relates to apparatus and methods for setting wakeup times of a communication device that has been put to sleep, and more particularly to minimizing particular settings of wakeup times during a sleep mode cycle by dynamically estimating the settling time of a frequency synthesizer.
2. Background
In certain wireless devices, such as portable wireless devices, it is desirable to utilize battery energy very efficiently in order to provide long service between recharges. In particular wireless devices that operate using burst transmissions, such as in some modes of the code division multiple access (CDMA) and orthogonal frequency division multiplexed (OFDM) systems, given the burst nature of such systems, circuitry can be turned on for a short period of time when the device is actively receiving or transmitting, (i.e., during burst transmission periods) and at least some of the energy consuming circuitry turned off during sleep cycle (i.e., during an idle period). It is desirable to minimize the time that such devices are turned on, including trying to minimize the warm-up time of some components after they are turned on following a sleep period.
It is known that some components, in particular, have disproportionately long wakeup times. One such device is a frequency synthesizer, which may include a phase locked loop (PLL) and other similar devices. The settling or “lock on” time, during which the frequency synthesizer locks on the specified frequency, can take up to several milliseconds. This lock on time is difficult to estimate accurately in advance, because it varies with changing environmental conditions, such as temperature, interference, noise, etc. Notwithstanding, the lock on time needs to be predicted in advance in order for the device to wake up at a precisely specified time coincident with the beginning of a transmission burst. In order to ensure that the frequency synthesizer is locked on prior to receiving a transmission burst, it is known to set a time with an excessive safety margin (e.g., a worst case scenario) within the device's wakeup time-line to account for the somewhat uncertain settling time. Typically, the worst case scenario settling time is set containing the excessive safety margin, which is hard-coded either in software or hardware and used repetitively during consecutive wakeup cycles. By defaulting to the worst case scenario, wakeup times may not be optimized.
USPTO Backgrounds
USPTO Backgrounds