The present invention is related to data processing systems, and more particularly to systems and methods for retimed virtual data processing.
Existing data processing systems receive a series of data that includes various imbedded synchronization and timing information. The series of data is sampled using a sampling clock. The synchronization and timing information is provided to a timing loop that operates to correct the phase and frequency of the sampling clock. FIG. 1 shows an exemplary timing recovery circuit 100 including a phase detector 110 that receives a data processing output 105 and a data processing input 107. Data processing output 105 is the output received from a data processing circuit, and data processing input 107 is the input to the data processing circuit from which data processing output 105 is derived. Phase detector 110 provides a phase error based on a comparison of data processing output 105 and data processing input 107. The phase error is filtered using a loop filter 120, and the filtered phase error is interpolated using an interpolator 130 that is fed by a time based generator 140 to yield an updated sampling clock 109. Updated sampling clock 109 is used to sample the received series of data. Such loops exhibit latency from when the input data is received until the updated sampling clock is available for sampling future received data.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for timing recovery in a data processing system.
USPTO Backgrounds
USPTO Backgrounds