1. Field
The disclosed technology generally relates to a semiconductor device, and particularly to a gate-all-around (GAA) semiconductor device, and more particularly to a gate-all-around (GAA) nanostructure semiconductor device. The disclosed technology also relates to methods of manufacturing the same.
2. Description of the Related Technology
High mobility materials such as III-V semiconductor materials have drawn attention for utilization in scaling complementary metal-oxide-semiconductor (CMOS) technology at advanced technology nodes, e.g., technology nodes at 10 nm and beyond. In order to meet various technological specifications at these advanced technology nodes, e.g., specifications associated with short channel effects (SCE) such as sub-threshold slope and drain-induced barrier lowering, various multi-gate transistor structures have been proposed, e.g., tri-gate quantum well structures and gate-all-around/nanowire (GAA/NW) structures.
III-V GAA devices fabricated by growing blanket layers on an entire III-V wafer (typically 2″ or 4″ substrates) have been reported, as for example disclosed in “First experimental demonstration of gate-all-around III-V MOSFETs by top-down approach”, by Gu et al. as published in IEEE IEDM 2011 pp. 769-772. In this example, after growing, the blanket heterostructure layers are patterned and a sacrificial buffer layer is removed by means of a wet etch to release the nanowire.
However, integrating these structures at the very large scale integration (VLSI) level, e.g., on 300 mm or larger wafers, poses a considerable technical challenge. Moreover, to be economically competitive, the III-V materials should be monolithically integrated with Si, in order to minimize cost by utilizing as much of the existing Si-based semiconductor processing techniques as possible. The use of Si as a substrate would also enable the integration of several functional blocks on the same platform, such as for example logic, high-frequency, and I/O circuitry.
USPTO Backgrounds
USPTO Backgrounds