The formation of active areas and isolation regions on semiconductor substrates is well known. Active areas are those regions of the semiconductor substrate on and/or in which semiconductor devices are formed. The isolation regions are insulation regions of the semiconductor substrate between the active areas.
Two well-known techniques for forming the isolation regions on a substrate are LOCOS and STI. Both techniques involve a photolithography process with a single masking step in which photo resist is formed over the substrate and selectively exposed to light using a photo mask, whereby only selective portions of the photo resist are removed (e.g. those portions exposed to light through the mask for the case of positive photolithography). Insulation material is formed on and/or in the substrate in those selective portions where the photo resist had been removed. See for example, U.S. Pat. No. 7,315,056, which is incorporated herein by reference for all purposes.
FIG. 1 illustrates the top plan view of a semiconductor substrate 10 in which isolation regions 12 of insulation material are formed. The areas between the isolation regions 12 are the active areas 14. The configuration of FIG. 1 can be used, for example, in the formation of an array of memory devices such as flash memory cells.
FIG. 2 illustrates a photo mask 16 suitable for forming the active areas and isolation regions of FIG. 1. The mask includes opaque regions 16a (to block light) and transparent or open regions 16b (through which light will pass). The shape and dimensions of the light passing through and focused onto the substrate dictate the shape and dimensions of the active areas and isolation regions on the substrate 10.
Due to diffraction and/or process effects, the shape of the active areas and isolations regions formed on the substrate do not match exactly the shape of the opaque and transparent regions of the mask. Therefore, it is known to implement Optical Proximity Correction (OPC), whereby the shape of the mask is altered to compensate for such errors. OPC is used to compensate for distortions in line widths as well as rounded corners, which otherwise could adversely affect the electrical properties of the device(s) being fabricated. OPC involves moving edges or adding extra polygons to the pattern written on the photo mask. FIG. 3 is an example of an OPC corrected mask 18, where the dimensions and shape of the opaque and transparent regions 18a/18b are altered to more accurately fabricate the pattern of FIG. 1.
However, even with OPC, there can still be intolerable variations in active corner rounding and in critical dimensions of the pattern due to photo patterning conditions (i.e. variations in photo lithography equipment, exposure energy, development time, etc.). FIG. 4 illustrates the types of variations in the fabrication of the isolation regions 12 even with the implementation of OPC, where the ends 20 of the isolation regions 12 vary from region to region and wafer to wafer. OPC and CD optimization becomes more difficult as devices continue to shrink in size. Because the separation distance between the isolation regions 12 is an important critical dimension of the resulting devices, there is a need to better control the formation of the active areas and isolation regions.
USPTO Backgrounds
USPTO Backgrounds