1. Field of the Invention
This invention relates to cache flash upon emergency of a cache system which has a cache memory and a dual system having a redundancy structure including a 0-subsystem and a 1-subsystem.
2. Description of the Related Art
A communications system or a like system has a dual structure including a 0-subsystem and a 1-subsystem in order to secure the reliability of services. Each of the 0- and 1-subsystems includes a microprocessor (MPU), a cache memory control section, a cache memory, a main memory, a system control section, and an interface (INF) section. The MPU and the cache memory control section are interconnected by an MPU bus. The cache memory control section, main memory, system control section and INF section are interconnected by an extension MPU bus. The main memories of the 0- and 1-subsystems are interconnected by a memory confounding line. The system control sections of the 0- and 1-subsystems are interconnected by a system confounding line. A cache memory is popularly used as a technique for augmentation of the processing performance and is used to send necessary data rapidly to an MPU. Generally, the difference between the working speed of an MPU and the working speed of a main memory is considerably great, and in the case of MPU working speed  greater than  greater than main memory working speed, in order to absorb the great working speed difference to allow high speed operation, a storage device of a small capacity called cache memory is D interposed between the main memory and the MPU so that data requested by the MPU may be sent back at a high speed from the cache memory.
When the MPU tries to read data at the A address from the main memory, it issues a read command to the MPU bus. The cache memory control section receives the read command and checks whether or not contents of the A address are registered in the cache memory. If the contents are registered (cache hit), then the cache memory control section reads the data at the A address from the cache memory and sends the data back to the MPU. If the contents of the A address are not registered (cache mishit), then the cache memory control section issues a data read command for reading an amount of data including data at the A address from the main memory to the extension MPU bus. The main memory receives the data read command and sends back the data of the pertaining area of the memory. The cache memory control section receives all of the data sent back thereto and returns only the data at the A address from within the received data to the MPU and besides writes all of the received data into the cache memory. It is assumed that the MPU issues a write command to write the data into the B address. The cache memory control section receives the write command and checks whether or not contents at the B address are registered in the cache memory. If the contents are registered, then the cache memory control section rewrites the pertaining data with the data from the cache memory without issuing a read command to the main memory.
In this manner, processing contents are different depending upon whether data requested by the MPU is registered (upon cache hit) or not registered (upon cache mishit), and augmentation in processing performance is achieved by the difference in processing contents. Further, although depending upon the controlling method for the cache memory, from the point of view of high speed execution, as a method of updating of data registered once in the cache memory into the main memory, a flashback method wherein the MPU issues a flashback command to perform the updating, a store-in method wherein data is written only into the flash memory and, when the block becomes an object of replacement, the data is written into the main memory and some other methods are available. In a dual system, services are provided usually such that one subsystem is in a processing state (ACT state) while the other system is in a standby state (SBY state). If a serious trouble or the like occurs while services are provided in this state, then an ACT/SBY changing operation is performed to place the old ACT subsystem into a stopping or SBY state and place the old SBY system into an ACT state in order to continue the operation without stopping the services.
It is assumed that usually the system is operating while the 0-subsystem acts as the ACT system and the 1-subsystem acts as the SBY system. The MPU of the 0-subsystem reads out a processing program from the main memory, and control of individual functioning blocks and writing processing of a result of operation into the main memory are performed in accordance with the contents of the processing program. The contents of data written in the main memory of the ACT system are normally reflected on the main memory of the SBY system over the memory confounding line so that contents of the main memories are normally held commonly between the ACT system and the SBY system. However, when the MPU writes data on data registered in the cache memory, writing of the data back into the main memory is not performed unless flash back processing is performed. Accordingly, when such data exists, the data of the ACT system and the SBY system do not coincide with each other. Therefore, in such a dual system as described above, when a serious trouble occurs and consequently it is tried to perform an ACT/SBY changing operation, the following processing is executed.
(1) When timeout of a watch dog timer (WDT) of the system control section occurs, an ACT/SBY changing trigger is detected.
(2) The system control section notifies the MPU of interruption over an interrupt notification line.
(3) The MPU starts an emergency control operation program.
(4) Flashback processing of the cache memory and collection of logs of other trouble information are performed based on the emergency control operation program.
(5) ACT/SBY changing processing is performed so that, for example, the 1-subsystem becomes the ACT system and continues services.
As data of the cache memory is flashed back in this manner, contents of the flash memory are written into the main memory, and the data is transferred to the 1-subsystem over the memory confounding line. Consequently, the contents of the main memory of the 1-subsystem become common to the contents of the main memory of the 0-subsystem, which allows continuing of services.
However, the ACT/SBY changing operation cannot sometimes be performed normally. This is, for example, a case wherein a troubled functioning block from among blocks connected to the MPU bus or the extension MPU bus locks the bus and keeps the bus locked. Here, to lock the bus signifies a condition that the bus has been placed into and remains in a used state and is not released indefinitely. Where the MPU bus is locked, the emergency control operation program cannot transmit a command for instruction of flashback to the cache memory control section. On the other hand, where the extension MPU bus is locked, the cache memory control section cannot perform flashback into the main memory. In such instances, processing of the emergency control operation program cannot be performed, and flashback processing of the cache memory is disabled and services cannot be continued any more. As a trend in recent years, a system including a cache memory having an increased capacity is constructed as a result of further augmentation of the request processing capacity, increase of the performance of memory devices, reduction in cost of high speed devices and so forth. Consequently, the fact that contents of a cache memory cannot be taken over upon ACT/SBY changing operation or the like has an influence upon continuity of services as much.
Accordingly, it is an object of the present invention to provide a cache system wherein contents of a cache memory are written back into a main memory with certainty upon emergency.
It is another object of the present invention to provide a dual system which prevents, upon ACT/SBY changing, interruption of services arising from missing of stored contents of a cache memory caused by a trouble.
In accordance with an aspect of the present invention, there is provided a cache system, comprising a first bus, a second bus, a main memory having a memory section for storing data, the main memory being operable to write data inputted from the first bus into the memory section and output data read from the memory section to the first bus, a cache memory, instruction means for outputting to the second bus a command for instruction to write back data of the cache memory into the main memory, and a cache memory control section including a directory section for storing information regarding an address of the main memory of data stored in the cache memory and a reset terminal to which a first reset signal is inputted such that, when the first reset signal is asserted, at least an element of the cache memory control section which takes part in control of the first bus except the directory section is reset, the cache memory control section performing reading and writing of data between the main memory and the cache memory over the first bus, the cache memory control section performing write back processing of the data of the cache memory into the main memory in accordance with the command inputted over the second bus.
In accordance with another aspect of the present invention, there is provided a cache system, comprising a first bus, a second bus, a third bus, a main memory having a memory section for storing data, the main memory being operable to write data inputted from the first bus into the memory section and output data read from the memory section to the first bus, a cache memory, instruction means for outputting to the second bus a command for instruction to write back data of the cache memory into the main memory, a cache memory control section for performing reading and writing of data between the main memory and the cache memory over the first bus and performing write back processing of the data of the cache memory into the main memory in accordance with the command inputted over the second bus, an interface section for interfacing between the first bus and the third bus, and an isolate section interposed between an output side of the interface section and the first bus for isolating the output side of the interface section and the first bus from each other when a control signal inputted to a control terminal becomes valid.
In accordance with a further aspect of the present invention, there is provided a cache system, comprising a first bus, a second bus, a signal line different from the first bus, a main memory having a memory section for storing data, the main memory being operable to write data inputted from the first bus into the memory section, output data read from the memory section to the first bus, and receive data and an address from the signal line and write the data and the address into the memory section, a cache memory, instruction means for outputting to the second bus a command for instruction to write back data of the cache memory into the main memory, and a cache memory control section for performing reading and writing of data between the main memory and the cache memory over the first bus and outputting data and an address of the cache memory to the signal line in accordance with the command inputted over the second bus thereby to perform write back processing into the main memory.
The above and other objects, features and advantages of the present invention and the manner of realizing them will become more apparent, and the invention itself will best be understood, from a study of the following description and appended claims with reference to the attached drawings showing some preferred embodiments of the invention.
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