This invention relates to a semiconductor nonvolatile memory cell of floating-gate type suitable for use in flash EEPROMs (electrically erasable programmable read only memories).
In conventional flash EEPROMs, floating-gate type transistors are used as nonvolatile memory cells. A floating gate type transistor has two gate electrodes in an overlapping arrangement. The first gate electrode is "floating" on a dielectric film formed on a principal surface of a semiconductor substrate. The second gate electrode, called a control gate electrode, lies above the floating gate electrode, and there is an inter-gate dielectric film between the two gate electrodes.
In this memory cell, writing of information charge is accomplished by injecting hot electrons which appear in the channel region of the transistor into the floating gate electrode through the dielectric film on the substrate surface. Erasing of the information charge is accomplished by ejecting electrons from the floating gate electrode into the source region or the channel region of the transistor. Information stored in the memory cell becomes logical "1" by writing and changes to logical "0" by erasing. Because of the difference of the erasing mechanism from the writing mechanism, the erasing voltage needs to be considerably higher than the writing voltage. In conventional memory cells for EEPROMs the erasing voltage is about 12 V, which is more than two times higher than the writing voltage. Meanwhile, the endurance of the conventional memory cells is at the level of 10.sup.5 write/erase cycles.
With an increase in the memory capacity of flash memories, there are strong demands for improved memory cells to enhance the endurance to more than 10.sup.6 write/erase cycles and to lower writing and erasing voltages and particularly lower the erasing voltage below 5 V.
In view of such demands, there is a proposal of a modification of a floating-gate type memory cell as shown, for example, in JP 59-58868 A. In the modified memory cell the floating gate electrode is overlaid with a multilayer dielectric film including a silicon nitride layer, and, in addition to a control gate electrode, another gate electrode (called an injection-erase gate electrode) is formed on the multilayer dielectric film so as to overlap only an end area of the floating gate electrode. In this memory cell, writing is accomplished by injecting electrons from the injection-erase gate electrode into the floating gate electrode, and erasing is accomplished by returning electrons from the floating gate electrode into the injection-erase gate electrode. That is, in both writing and erasing operations electrons pass through the multilayer dielectric film between the floating gate and the injection-erase gate.
The multilayer dielectric film between the floating gate and the injection-erase gate is made high in durability to flows of electrons with a view to enhancing the endurance of the memory cell. However, for the following reasons it is difficult to actually enhance the endurance to more than 10.sup.6 write/erase cycles. Since the floating gate electrode is formed of polysilicon, the gate electrode surface is microscopically rugged. Therefore, concentration of electric field is liable to occur in very narrow areas, and in such areas deterioration of the dielectric film is inevitably promoted.
In the proposed memory cell the erasing voltage becomes equivalent to the writing voltage, and the writing and erasing voltage can be lowered by forming the control gate electrode and the injection-erase gate electrode such that the overlapping area of the control gate electrode and the floating gate electrode is very larger than the overlapping area of the injection-erase gate electrode and the floating gate electrode (the reason will be explained hereinafter). That is, the control gate electrode needs to cover a large area. This is unfavorable for a desired reduction in the memory cell size. By the proposed modification it is difficult to satisfy both the demand for lowering of operating voltage and the demand for reduction in the memory cell size.
USPTO Backgrounds
USPTO Backgrounds