This invention relates to a semiconductor chip mounting apparatus and a method of mounting a semiconductor chip, particularly to the semiconductor chip mounting apparatus and the method thereof for use in mounting a semiconductor chip on a substrate.
In mounting a semiconductor chip, such as a bear chip on a substrate, some mounting methods are generally used. In one of the mounting methods, for example, metal projections formed on electrodes of the bear chip are connected to electrodes of a substrate by solder, or the like. In another one of the mounting methods, gold projections are formed on electrodes of a bear chip so as to be thermally crimped to gold-plated electrodes of a substrate at a high temperature.
In the mounting methods, both the bear chip and the substrate are heated up to a high temperature during mounting process and thereafter naturally cooled down to an ordinary temperature. However, a great stress is imposed on a connected portion during the cooling process due to a difference between coefficient of thermal expansion of the bear chip and that of the substrate. When the substrate is made of an organic material such as glass epoxy resin, and the like, the difference of the coefficient of thermal expansion becomes serious. Accordingly, the great stress is imposed on the connected portion during the cooling process, since a shrinkage ratio of the substrate is larger than that of the bear chip. As a result, the connected portion is easily destroyed.
It is desired that the stress is reduced to obtain a reliable connected portion. Then, some proposals have been made to reduce the stress conventionally. A proposal is exemplified, as a first prior art, in unexamined Japanese Patent Publication No. Sho 63-237426, namely, 237426/1988. In the first prior art, it is attempted that a difference of amounts of thermal expansion between a semiconductor chip, such as a flip chip IC(Integrated Circuit) and a substrate is reduced by using expansion and shrinkage of resin at a comparatively low temperature for connecting the flip chip IC and the substrate. Thereby, the resin has already been fastened when the mounting process is finished to start a next cooling process. As a result, a thermal stress on a connected portion due to the difference of coefficient of thermal expansion is dispersed to prevent the connected portion from being destroyed.
However, as the connection is achieved only by a shrinkage of the resin, it becomes difficult to obtain reliability such as a temperature cycle resistant characteristic, or the like. In addition, boids are inevitably generated in the resin when the flip chip IC and the substrate are rapidly heated up to a high temperature. For preventing the boids from being generated, it therefore takes a long time to heat the flip chip IC and the substrate up to a high temperature. In view of a time to heat them up to a high temperature as well as a time to fasten the resin, the mounting method disclosed as the first prior art takes a time several times longer than the above-mentioned generally used mounting methods. As a result, a productivity per production facility unit is not so good in the first prior art.
On the other hand, another proposals are exemplified, as a second prior art, in unexamined Japanese Patent Publications No. Hei 2-14536, namely, 14536/1990, No. Hei 7-7042, namely, 7042/1995, or No. Hei 5-326585, namely, 326585/1993. In each second prior art, it is attempted that a difference of amounts of thermal expansion between a semiconductor chip and a substrate is reduced by a design of a structure of the semiconductor chip or a design of a structure of mounting the semiconductor chip on the substrate. However, members of the semiconductor chip and the substrate becomes very expensive in the second prior art. Furthermore, the second prior art cannot completely resolve the aforesaid problem of the thermal stress on the connected portion. Namely, the thermal stress is imposed, more or less on the connected portion, since a difference of amounts of thermal expansion between the semiconductor chip and the substrate cannot be substantially eliminated.
USPTO Backgrounds
USPTO Backgrounds