1. Field of the Invention
The present invention relates to a semiconductor device. Particularly, the invention relates to a semiconductor device having a structure that interrupts electric connections of power and ground lines to logic circuits or the like in a standby mode, and is pertinent to a semiconductor device that can reduce power consumption in the standby mode.
2. Description of the Background Art
In recent years, degrees of integration as well as performance of semiconductor devices have been developing, and application ranges thereof have been increasing. With these situations, it has been technically required to reduce power consumption of semiconductor devices and semiconductor chip bodies. More specifically, it is required to increase a battery operation time of an internal battery in a data information device that includes a telephone, an electronic notebook and a small personal computer in an integrated fashion. In information processing devices of high performance, it is required to reduce sizes of a cooling device and a power supply device. Since effective use of energy resources has been socially demanded for protecting the global environment, the reduction in power consumption of the semiconductor devices as well as the improvement of the performance have been important constituent techniques for high value addition to the semiconductor devices.
As an example of such techniques, there has been a semiconductor device using multiple kinds of thresholds, i.e., a multi-threshold CMOS which will be referred to as an “MTCMOS” hereinafter. The MTCMOS circuit is formed of a logic circuit group and transistors of high threshold voltages, and can prevent increase in power consumption of the logic circuit group formed of CMOSs when the logic circuit group is on standby. In connection with this, Japanese Patent Laying-Open Nos. 09-064715, 09-321600 and 2000-059200 have disclosed various manners that can reduce the power consumption in the standby mode.
More specifically, a logic circuit group includes one or a plurality of logic gate(s), each of which is formed of a P-channel MOS transistor having a threshold voltage of a small absolute value and an N-channel MOS transistor having a low threshold voltage of the small absolute value.
FIG. 38 shows a conventional MTCMOS circuit.
Referring to FIG. 38, a logic circuit group L1 includes a P-channel MOS transistor P2 of a low threshold voltage and an N-channel MOS transistor Q1 of a low threshold voltage, which are connected between a pseudo power supply line VA on a high potential side and a pseudo ground line VB on a low potential side.
Pseudo power supply line VA is connected via a P-channel MOS transistor P1 having a high threshold to a power supply voltage Vcc provided from a power supply line VL. Pseudo ground line VB is connected via an N-channel MOS transistor Q2 having a high threshold to a ground voltage GND provided from a ground line GL. Transistor P1 receives on its gate a control signal /Sleep, and transistor Q2 receives on its gate an inverted signal of control signal /Sleep provided via an inverter IV.
Inverter IV is formed of P- and N-channel MOS transistors PT1 and NT1 connected between power supply voltage Vcc and ground voltage GND. A connection node N1 between transistors PT1 and NT1 is electrically coupled to a gate of transistor Q2. This MTCMOS circuit operates as follows. In an active mode, control signal /Sleep is set to an “L” level, and transistors P1 and Q2 are turned on so that pseudo power supply line VA and pseudo ground line VB are electrically coupled to power supply voltage Vcc and ground voltage GND, respectively.
Thereby, pseudo power supply line VA and pseudo ground line VB are supplied with the required voltages via low-resistance paths, respectively, and thereby can perform predetermined circuit operations.
In the standby mode, control signal /Sleep is set to an “H” level so that transistors P1 and Q2 are turned off.
Therefore, power supply voltage Vcc and pseudo power supply line VA are electrically isolated. Likewise, ground voltage GND and pseudo ground line VB are electrically isolated.
Thereby, transistors P1 and Q2 significantly reduce a leak current in the whole circuit.
In general, a lower threshold voltage of a transistor lowers a leak current preventing capability. Thus, the power consumption increases in transistors P2 and Q1. Therefore, this circuit structure reducing the leak currents in transistors P1 and Q2 can reduce the power consumption in the standby mode. More specifically, even when logic circuit group L1 uses, e.g., transistors of a low threshold voltage, the leak current in the transistors of the logic circuit group can be suppressed so that the power consumption of the whole circuit can be reduced.
During the standby period of the above circuit structure, pseudo power supply line VA and pseudo ground line VB are electrically isolated from power supply Vcc and ground voltage GND provided from power supply line and ground line, respectively, and are set to a high-impedance state. Therefore, small amounts of currents continuously leak to pseudo power supply line VA and pseudo ground line VB via the transistors forming logic circuit group L1 with the passage of time. The leak current occurs because logic circuit group L1 is formed of the transistors of low threshold voltages as described above, and the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other.
When logic circuit group L1 is formed of a sequential circuit or the like such as a register circuit, a latch circuit or a flip-flop circuit that can store a logical state, and a standby period is long, a potential difference that can hold the logic state may not ensured between pseudo power supply line VA and pseudo ground line VB. Thus, stored information may be lost. Consequently, the semiconductor device cannot be restored to the original state even when it enters an active mode after the standby period. In logic circuits or the like other than the circuit that is required to store the logic state, such a state may be allowed that the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other.
Referring to FIG. 39, another MTCMOS circuit in the prior art will now be described.
The MTCMOS circuit in FIG. 39 differs from the structure in FIG. 38 in that a transistor P3 is additionally arranged in parallel with transistor Q2 and between a node N0 and ground voltage GND. Other structures are substantially the same, and description thereof is not repeated.
Referring to FIG. 40, description will now be given on the case where the potential level of pseudo ground line VB in FIGS. 38 and 39 rises with time.
Referring to FIG. 40, the leak current on the side of power supply voltage Vcc supplied via logic circuit group L1 raises the potential level of pseudo ground line VB in the structure of FIG. 38 with time as illustrated by dotted line in FIG. 40. A balanced state is attained when the leak current on the side of power supply voltage Vcc is balanced with the leak current passing through the transistor. In this case, the potentials of pseudo power supply line VA and pseudo ground line VB become closer to each other as already described.
In the structure of FIG. 39, transistor P3 is supplied on its gate with a control signal SV (at the “L” level) in the standby mode. Thereby, the potential of pseudo ground line VB rises to a potential level near the threshold voltage of transistor P3 so that transistor P3 starts to be turned on, and the current starts to flow from pseudo ground line VB via transistor P3. Thus, when the potential of node N0 rises to the threshold voltage of transistor P3, transistor P3 is fully turned on. If the potential is lower than it, the degree of the turn-on of transistor P3 is small.
Therefore, as illustrated in solid line in FIG. 40, the potential of node N0 attains the balanced state when it attains a level keeping the balance between the quantity of the current passing to pseudo ground line VB through logic circuit group L1 and the quantity of the current passing to ground voltage GND through transistor P3. This balanced potential depends on the threshold voltage of transistor P3, a transistor width and others. Thus, the potential level of pseudo ground line VB can be adjusted owing to provision of transistor P3. This structure is disclosed by Suhwan Kim, Stephen V. Kosonocky, Daniel R, Knebel, and Kevin Stawiasz, “Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode,” Proceedings of the 2004 International Symposium on Low Power Electronics and Design, pp. 20-25, 2004.
However, even in either of the case where transistor P3 in FIG. 39 is employed to adjust the potential level, and the case where transistor P3 is not employed, the charging current that flows immediately after the start of the standby mode until a balanced state and thus a certain predetermined balanced potential are attained is pulling from power supply voltage Vcc by the leak current flowing through logic circuit group L1.
Therefore, when the power consumption can be reduced during the above period, the power consumption can be further reduced.
USPTO Backgrounds
USPTO Backgrounds