1. Field of the Invention
The present invention generally relates to the field of electronic design automation (EDA), and more specifically, to a shifting of scan patterns for testing a digital circuit.
2. Description of the Related Art
One method of testing semiconductor devices for defects is done by applying test patterns to primary inputs of the device and comparing values of the device's primary outputs against expected values.
FIG. 1 is a block diagram of a generalized digital semiconductor device 111. Device 111 includes combinational logic blocks 11, 12, 15, 16, 19 and 110, and several flip-flops 13, 14, 17 and 18. Functional inputs such as 112 and functional outputs such as 117 provide an interface to the external world. Flip-flops 13, 14, 17 and 18 are all synchronized to sample values at their inputs on an edge of an input clock 113. Those skilled in the art will appreciate that device 111 is a greatly simplified representation of a digital integrated circuit, since there are many more combinational logic blocks, flops, clock inputs, functional inputs and functional outputs in a typical digital integrated circuit. Nevertheless, the representation of device 111 in FIG. 1 is adequate for the understanding of how the testing of an integrated circuit, or portions thereof, can be performed.
The testing of device 111 using only functional inputs is difficult. For example, a defect causing faulty operation of combinational logic block 11 cannot be directly observed at the output of device 111. A faulty value must first be captured in flip-flop 13. Then, the faulty value held in flip-flop 13 must cause a faulty output from combinational block 15, which would be captured in flip-flop 17. Then, the faulty value held in flip-flop 17 must cause a faulty output from combinational block 19, which can be observed on functional outputs 117.
A pattern exercising only functional inputs and outputs must not only be able to propagate a defective value through many stages of combinational logic and flops, but must also be able to pinpoint the location of the defect based on the sampled value on the functional outputs. A reason for the difficulty in using only functional inputs and outputs for test is that there is no easy way to control the inputs to the internal combinational blocks, or to observe the outputs of the combinational blocks. Scan architectures are used to make the process of testing semiconductor devices easier by reusing the internal flops of the device as virtual inputs and outputs to the combinational logic blocks (see U.S. Pat. No. 3,806,891, “Logic Circuit for Scan-In/Scan-Out”; and U.S. Pat. No. 4,493,077, “Scan Testable Integrated Circuit”). Scan architectures allow direct control of the output values of flip-flops through a device's inputs. The outputs of the flip-flops thus act as virtual inputs directly controlling the input to the combinational blocks. Scan architectures also allow the values on the inputs of the flip-flops to be easily observed from the device's outputs. In this way, the flip-flops act as virtual outputs capturing the output of the combinational blocks.
In scan architectures, a path known as a scan chain is created by reusing the functional registers present in the device. In FIG. 1, device 111 has one such scan chain that reuses flip-flops 13, 14, 17 and 18. The scan chain is accessed through a scan input 116. The output of the scan chain is sampled at a scan output 119. Scan output 119 is directly driven by flip-flop 18, which is the last flip-flop in the scan chain. Internal to device 111, connections such as a connection 120 connect the output of one flip-flop to the next, to form a scan chain of flip-flops from scan input 116 to scan output 119.
Scan chains have two modes: scan shift mode and normal mode. A separate input control signal, namely a scan-enable 114, controls which mode the scan chain is in.
In scan shift mode, the registers in the scan chain form a serial shift chain where the output of each register is the input of the next register in the scan chain. The application of a clock pulse to the scan chain in scan-shift mode will result in the shift of values by one place towards the end of the scan chain. For example, in scan shift mode, flip-flop 13 will capture the value on scan input 116 when the clock 113 is pulsed. At the same time, flip-flop 14 will capture the previous output of flip-flop 13, and so on, until the end of the scan chain.
In normal mode, the input of each register is the output of the functional combinational logic. The application of a clock pulse to the registers of the scan chain will result in the registers capturing the output value of the functional combinational logic at their input. For example, in normal mode, flip-flop 13 will capture the output of combinational logic block 11 via a connection 121.
In the prior art described above, the number of scan inputs is equal to the number of scan outputs. Modified scan architectures exist in which the number of scan chains internal to the device is greater than the number of primary inputs or outputs used for the purpose of scan-in and scan-out. The connection of the primary inputs and outputs to the internal scan chains is through an expander and compressor, respectively. The expander and compressor circuits may be of a combinational or sequential nature. Some examples of such architectures are the so-called Illinois scan architecture (see I. Hamzaoglu and J. Patel, “Reducing test application time for full scan embedded cores”, IEEE International Symposium on Fault Tolerant Computing, pp. 260-267, 1999; and U.S. Pat. No. 6,708,305 “Deterministic random LBIST”). Regardless of the variation of scan architecture used, the scan chains have two modes of operation: scan shift mode and normal mode.
FIG. 2 is a timing diagram of an application of a test pattern. Test patterns utilize the two modes of scan chain operation to test the device. A clock has a period 201 that is constant in shift mode, and the inverse of period 201 is referred to as the scan shift frequency. In what is referred to as a load operation, in scan shift mode, input test values 202 and 203 are shifted into the scan chain via the scan input. The response of the functional combinational logic to the input values shifted into the scan chain is captured by clocking the registers of the scan chain, in normal mode, for one cycle. This operation is referred to as capture or scan capture. The response thus captured in the scan chain is shifted out in scan shift mode as data 204 and 205, and compared against expected values at the scan output. This operation is usually referred to as the unload operation.
A test pattern that performs a single load, capture and unload operation is referred to as a scan pattern. A load or unload operation can be described in terms of two independent variables. The first variable is the scan shift period, i.e., period 201. The second variable is the scan input data, i.e., input test values 202 and 203 and the corresponding expected data 204 and 205.
A scan pattern applied at one shift frequency is just as effective at any other shift frequency, given that the scan input and expected output data set is the same. The effectiveness of a pattern is measured by its ability to detect defects in the functional logic blocks. The defects are detected only by the capture operation when the response of the functional logic to known stimulus is captured and subsequently compared. The load and unload operations do not operate upon the data, but merely transfer data in and out of the device. Therefore, the stimulus data held in the registers prior to capture, and the response captured in the registers during capture, are the same regardless of the shift frequency used to load these registers or unload the response. It is thus possible to vary the scan shift period or scan shift frequency and yet maintain the effectiveness of the scan pattern.
One scan pattern is usually insufficient to test the device in its entirety. A set of scan patterns are created such that each scan pattern tests only a portion of the device but, when all scan patterns are applied to the device, the device is fully tested. Such an approach is detailed in U.S. Pat. No. 4,534,028, “Random Testing Using Scan Path Technique”. Since the manual creation of scan pattern sets is both tedious and error-prone, automated test pattern generation (ATPG) tools are used to create the scan pattern set. Test pattern generators will generate input scan patterns and expected output values based on a simulation of a fault-free software model of the device (see U.S. Pat. No. 4,601,032, “Test-Generation System for Digital Circuits”). ATPG tools generate patterns to detect many manner of faults that might be present in the device (see “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Michael Bushnell and Vishwani Agrawal, Kluwer Academic Publishers, ISBN 0792379918, 2002, pp. 60-69). While the capture operation and scan pattern data content may vary with change in fault models, the timing of the load and unload operations are retained unchanged.
Since data is shifted by one place for every clock pulse in scan shift mode, load and unload operations require as many clock cycles as the length of the scan chain in order to fully load the input values into the chain or fully unload the response values out of the chain. Scan capture, however, is usually restricted to a single clock cycle. Since the length of the scan chains is usually much greater than one, the time required for load and unload operations dominate the test time associated with the application of a scan pattern. To save time spent in loading and unloading, the load of one scan pattern is overlapped with the unload operation of another scan pattern to form what is referred to as a load-unload operation. Thus, an ordered scan pattern set is created where the unload of a pattern is overlapped with the load of the next pattern, all the way from the load of the first scan pattern to the unload of last scan pattern.
FIG. 3 is a timing diagram that shows the overlap of load and unload for consecutive scan patterns. The load-unload operations operate at a constant scan shift period 301. The shift in of a load vector 302 is overlapped with the shift out of the previous pattern's unload vector 304, and the shift in of a load vector 303 is overlapped with the shift out of an unload vector 305. By comparing FIG. 2 and FIG. 3, it can be seen that load vector 302 and unload vector 305 form one scan pattern. Even with load-unload operations, the time spent in scan capture is insignificant in comparison to the time spent in the load-unload operation.
During both operation and test, semiconductor devices consume electrical power. This is referred to as power dissipation. Power dissipation on a device consists of two components: static power and dynamic power (see “Low-Power Digital VLSI Design: Circuits and Systems”, Bellaouar, A. (Abdellatif); Springer, ISBN 0792395875, 1995, pp 129-138). The frequency of operation is the frequency of the clock input of the device, and switching activity is a measure of the rate at which logic on the device changes state. Static power dissipation is power dissipation when logic on the device is not switching. Dynamic power dissipation is power dissipated when logic on the device switches. Static power dissipation is independent of frequency of operation. Dynamic power dissipation is proportional to both switching activity and frequency of operation.
Power dissipation beyond the rated capacity of the device is characterized by high die temperatures and excessive average and/or instantaneous supply currents. High temperatures can cause thermal damage to the device. Drawing excessive current can lower on-die voltages, referred to as IR drop, leading to failure of operation. Usually, the designers of the device attempt to ensure that both the heat dissipation capacity and the power network on the device prevent high die temperatures or low on-die voltages during normal functional operation. This is done by estimating the power dissipation incurred during functional operation, using power estimation tools (see U.S. Pat. No. 5,696,694, “Method and Apparatus for Estimating Internal Power Consumption of an Electronic Circuit Represented as Netlist”; and U.S. Pat. No. 5,668,732, “Method for Estimating Power Consumption of a Cyclic Sequential Electronic Circuit”) and designing the device to operate safely at that power.
In scan shift mode, all registers in the design and the functional combinational logic connected to the output of these registers are active. The shift of values through the registers of the scan chain during the load-unload operations can cause switching of the registers as well as the logic the registers drive. The load-unload operation could lead to switching activity much higher than switching activity during functional operation. Since most of the time of a test is spent in load-unload operations, there is a potential for very high, sustained switching activity during scan test. If scan test is performed at high frequencies, the high switching activity will cause power dissipation above the limit for which the device was designed. Thus, scan patterns are applied at low frequencies in order to limit the dynamic power dissipation during scan test, to be lower than or equal to the average power dissipation that occurs during normal device operation (see K. M. Butler et. al, “Minimizing power consumption in scan testing: pattern generation and DFT techniques”, in Proc. International Test Conf. (ITC'04), pp. 355-364, 2004).
Lower power dissipation during scan testing will allow faster application of scan patterns and, therefore, result in a reduction in test time and test cost. The power dissipation for a scan pattern is dependent on the data values in the scan pattern set, the logical and physical structure of the design, and the frequency at which the scan pattern set is applied. Prior art methods that modify the data content of a scan pattern that are applied to reduce power dissipation during scan test include power-constrained test scheduling (see R. M. Chou, Kewal K. Saluja and Vishwani D. Agarwal, “Scheduling tests for VLSI systems under power constraints”, IEEE Trans. VLSI, Vol. 5, Issue 2, pp. 175-185, 1997), and pattern optimization (see S. Wang and S. K. Gupta, “ATPG for heat dissipation minimization during scan testing,” in Proc. ACM/IEEE Design Automation Conf., 1997, pp. 614-619). An example of prior art methods that modify the logical and/or the physical structure of a design is scan chain reordering (see S. Ghosh, S. Basu, and N. A. Touba, “Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering,” in Proc. IEEE Annual Symp. on VLSI, 2003, pp. 246-249).
A method has been proposed that varies scan shift frequency to meet thermal constraints (Tafaj, E.; Rosinger, P.; Al-Hashimi, B. M.; Chakrabarty, K., “Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling”, Proc. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Vol. 0, pp. 544-551). In such a method, the shift frequency is optimized such that the temperature of the device does not exceed a given constraint. The method of the thermal-safe shift frequency scaling seeks to optimize the temperature of the die citing the damaging effects of excessive die temperature on the device.
Power dissipation can be used as a constraint to limit die temperature as there exists a linear relationship between power dissipation and die temperature, (K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-aware microarchitecture”, International Symposium on Computer Architecture (ISCA), pages 2-13, 2003). Power dissipation is a first-order effect of device operation while die temperature is a second-order effect as a result of power dissipation. Power dissipation calculations form the first step of thermal simulations. Therefore, thermal calculations for a given die and scan patterns set require more calculations than the estimation of power dissipation.
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