This U.S. nonprovisional application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2001-75689 filed Dec. 1, 2001, the contents of which are incorporated by reference.
1. Field of the Invention
The present invention generally relates to a method of fabricating a capacitor of a semiconductor device. In particular, the present invention relates to a method of fabricating a metal-insulator-metal (MIM) capacitor having an upper and lower electrode formed of metal.
2. Description of the Related Art
As the integration density of semiconductor devices increases, it becomes difficult to obtain a sufficient cell capacitance in limited areas of semiconductor devices, such as DRAMs. Several methods of increasing cell capacitance in a limited area have been suggested, including a method of making a dielectric layer into a thin film, a method of using a material having a high dielectric constant as the dielectric layer, and a method of increasing the effective area of an electrode by making a cylinder-type electrode, a fin-type electrode, or by growing hemispherical grains (HSGS) on the surface of the electrode. However, if the dielectric layer is an existing oxide/nitride/oxide (ONO) layer, it is very difficult to obtain the cell capacitance required for the operation of Gigabit semiconductor devices. As a result, a study using dielectric materials (e.g., metal oxides such as Ta2O5 and TaON, which has a dielectric constant up to several hundred times greater than the ONO layer) and high dielectric materials (e.g., (Ba, Sr)TiO3(BST), SrTiO3, BaTiO3, (Pb, Zr)TiO3(PZT), and (Pb, La, Zr)TiO3(PZT)) is currently in progress.
Unfortunately, polysilicon electrodes react with these dielectric layers, which deteriorates the electrical characteristics of the capacitor. To solve this problem, a low dielectric layer such as a SiON layer can be added to inhibit the reaction between the polysilicon electrode and the dielectric layer. However, adding such a SiON layer increases the actual thickness of the dielectric layer. Therefore, there is a limit in how much the capacitance can be increased by using a SiON layer and high dielectric materials together.
Accordingly, it is preferable to fabricate a metal-insulator-metal (MIM) capacitor having a dielectric layer formed of a high dielectric material and an upper and lower electrode formed of metal, which does not react with the dielectric layer. Preferably, the metal electrode is formed of a Pt-based noble metal, an oxide of the Pt-based noble metal, or a conductive oxide. Due to the difference between the inherent work functions of the metal electrode and the dielectric layer, a leakage current barrier layer is formed on the interface between the metal electrode and the dielectric layer. As a result, leakage current is controlled. Therefore, even though a low dielectric layer to inhibit the reaction between the electrode and the dielectric layer is not coated, stable leakage current characteristics can be obtained. Also, capacitance can be increased by thinning the dielectric layer.
Currently, in order to fabricate a MIM capacitor having a lower electrode with a concave or cylindrical structure, a node-separation step must be performed as described below with reference to FIGS. 1-3.
Referring first to FIG. 1, a dielectric layer pattern 20 defining a plurality of holes 15 is formed on a lower layer 10. The entire surface of the resultant structure is coated with a conductive layer 25 for a lower electrode. The holes 15 are then filled with an oxide layer that has excellent gap-filling characteristics to form a capping layer 30 to prevent the conductive layer 25 on the inner walls of the holes 15 from being etched in a subsequent process.
Referring now to FIG. 2, the capping layer 30 and the conductive layer 25 are sequentially removed by etch-back or chemical mechanical polishing (CMP) until the upper surface of the dielectric layer pattern 20 is exposed. As depicted in FIG. 2, the conductive layer 25 for a lower electrode on the dielectric layer pattern 20 is completely removed, i.e., the conductive layer 25 is node-separated. As a result, lower electrodes 25a, which are separated from each other, are formed and capping layers 30a remain in the holes 15.
As shown in FIG. 3, the remaining capping layers 30a are removed. Because the capping layers 30a are mainly formed of an oxide, the capping layers 30a are removed by wet etching. However, wet etching has no etching selectivity between the capping layers 30a and the dielectric layer pattern 20. Consequently, the dielectric layer pattern 20 is removed at the same time that the capping layers 30a are removed. As a result, the edges of the lower electrodes 25a protrude above the dielectric layer pattern 20a. 
In the situation where a capacitor having a cylindrical structure is desired, the entire dielectric layer pattern 20 is removed. When the capacitor has a cylindrical structure, the protrusion of the edges of the lower electrodes 25a is not a problem. On the other hand, if the edges of the lower electrodes 25a protrude in a capacitor having a concave structure, the leakage current characteristic may be deteriorated.
Furthermore, if node-separation is performed by the current method as described above, additional steps of 1) of forming the capping layer 30 formed of a material having excellent gap-filling characteristics and 2) removing the capping layers 30a remaining in the holes 15 after node-separation are needed. Therefore, the current process of fabricating a capacitor is both complicated and time consuming. Moreover, the production cost is high in node-separation according to chemical mechanical polishing.
It is therefore desirable to provide a method of fabricating a semiconductor material that overcomes the disadvantages of the known prior art.
The present invention provides a method of fabricating a metal-insulator-metal (MIM) capacitor by a simple fabricating process having a low production cost.
In an exemplary embodiment of the method of the present invention, insulating layer patterns defining a plurality of holes are formed on a semiconductor substrate. A conductive layer for the lower electrodes is formed on the entire surface of the resultant structure to a thickness that does not completely fill the holes. Capacitor lower electrodes which are separated from each other are formed by etching back portions of the conductive layer on the upper surfaces of the insulating layer patterns. No additional layer for filling the holes is necessary in exemplary embodiments of the present invention. A dielectric layer and an upper electrode are formed on the lower electrodes.
In the method according to an exemplary embodiment of the present invention, to node-separate the conductive layer by etching back portions of the conductive layer on the upper surface of the insulating layer patterns without the additional step of adding an additional layer such as a capping layer as is common in the prior art, it is preferable to use plasma containing at least one gas that is capable of selectively chemically etching portions of the conductive layer on the upper surfaces of the insulating layer. For example, when the conductive layer is a Ru layer, portions of the Ru layer on the upper surfaces of the insulating layer patterns are etched back using plasma containing oxygen. In an exemplary embodiment of the present invention, it is preferred that the pressure of the plasma is maintained at 10-100 mTorr to maximize the chemical etch. In an exemplary embodiment of the present invention, it is also preferable that plasma distribution is controlled so that only portions of the conductive layer on the upper surfaces of the insulating layer patterns are removed.
In addition, bias may be applied to the semiconductor substrate during the etch-back of the portions of the conductive layer on the upper surfaces of the insulating layer patterns. In an exemplary embodiment of the present invention, the power of the bias is maintained at 10-200 W. Etch by-products occurring during the etch-back of the conductive layer are attracted to the semiconductor substrate due to the bias applied to the semiconductor substrate and are deposited on portions of the conductive layer located on the inner walls of the holes. The deposited etch by-products protect the conductive layer on the inner walls of the holes and reduce the likelihood the conductive layer will be etched back. As a result, the portions of the conductive layer on the inner walls of the holes are not removed. Portions of the conductive layer outside the holes, i.e., on upper surfaces of insulating layer patterns, are removed without having to add an additional layer such as an existing capping layer as in the prior art methods. As a result, lower electrodes are formed.
After the lower electrodes are formed by applying the bias to the semiconductor substrate, the etch by-products may be removed by a thermal treatment in a reducing gas atmosphere. Preferably, the reducing gas is argon, nitrogen, hydrogen, or a combination thereof. Alternatively, the etch by-products may be removed by thermal treatment in a vacuum atmosphere.
Because the step of forming/removing an additional layer such as a capping layer is omitted, the fabrication process of the present invention in exemplary embodiments is simplified and the production cost is lowered. Additionally, unlike the prior art methods which results in a protrusion of the edges of the lower electrodes which often occurs when the capping layer is removed, leakage current can be reduced due to the lack of protrusion of the edges of the lower electrodes above an insulating layer.
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