As the integrated circuits (ICs) continue to become smaller in size, and the circuitry on ICs continue to increase, the density of bonds and the number of bonds continue to increase. A ball grid array (BGA) is an advanced integrated circuit package comprising a substrate having contacts on the bottom for soldering the integrated circuit package to a circuit board. A wire bond BGA comprises a die having contact pads which are bonded to a contact pads on the surface of the substrate by way of wire bonds. In contrast, a flip chip BGA comprises a die having contact pads which are directly bonded to the substrate using solder bumps. Unlike in a wire bond BGA, the die having solder bumps is flipped over and placed face down in a flip chip BGA, with the solder bumps connecting directly to corresponding contact pads on the top surface of the substrate. The contact pads on the bottom of the substrate of either type of package are ultimately soldered to a circuit board.
Flip chip packages are particularly useful with devices requiring a large number of pins, such as programmable logic devices (PLDs). A PLD is an integrated circuit designed to be programmed by users so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources. These CLBs, IOBs, and programmable routing resources are customized by loading a configuration bitstream, typically from off-chip memory, into configuration memory cells of the FPGA.
However, as both the density of the circuitry and the amount of circuitry for a given integrated circuit continues to increase, the noise associated with circuitry continues to increase. This unwanted noise is a particular problem in programmable logic devices because of the switching of digital circuits and high density of interconnect lines. In order for the circuit to operate properly, it is important to effectively control noise generated internally from digital switching. One way to control such noise is through the use of decoupling capacitors. As shown for example in the conventional integrated circuit package 102 of FIG. 1 having an integrated circuit die 104 (and the cross-sectional view of FIG. 2 taken at lines 2-2), the decoupling capacitors 106 and 108 are positioned on the substrate on the sides of the integrated circuit die 104, which has dimensions w2 and l2. Although the decoupling capacitors are shown on two sides of the integrated circuit die, the decoupling capacitors may be positioned on any number of sides, including all four sides, therefore affecting the overall size of the integrated circuit package by affecting both dimension W1 and L1.
The goal of decoupling is to provide a low impedance path between the point in the supply system where a logic element on the integrated circuit draws the current needed to operate and its local ground contact, forming the return path for current to the power supply. Placing a capacitor in close proximity to the power and ground contacts on the integrated circuit takes RF energy generated by rapid changes of current demand on the power supply during switching, and then channels it to the ground return path. The use of decoupling capacitors prevents power line channeled noise from subverting normal circuit operation. Because uncontrolled power supply noise has many effects, such as intermodulation and crosstalk, it is important to reduce noise whenever possible in digital circuits.
However, decoupling capacitors themselves may cause undesirable affects in the circuit. Decoupling capacitors are typically placed on periphery of the substrate, typically as close to the integrated circuit die as possible. In an integrated circuit package, a flip chip with solder bumps 201 having a height h1 is positioned on a substrate 202 which is coupled to a lid 204. The inside of the lid extends a height h2 from the substrate, resulting in an overall height of h3 for the integrated circuit package. As can also be seen in the bottom plan view of the integrated circuit die of FIG. 3, the solder bumps 201 are evenly positioned over the entire area of the die. The proximity of the capacitors from the integrated circuit die 104 is constrained by the die size and the underfill 206. The conducting metal lines in the substrate connect the capacitors and the power/ground pins of the chip. The inductance of these metal lines is directly proportional to the length of the conductive path. As can be seen in FIG. 2, the conductor 208 from a power or ground contact 210 of the die to the decoupling capacitor 106 may be particularly long. Even when the power or ground contact on the die is on the end of the die, the line may be relatively long, as shown by conductor 212 connecting contact 214 to the decoupling capacitor 108. Accordingly, the benefits of placing capacitors on the substrate to minimize the simultaneous switching noise (SSO) between the power/ground planes is overshadowed by the inductance of the conductive path between the capacitor and the integrated circuit die.
USPTO Backgrounds
USPTO Backgrounds