Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit of chip area occupied.
Traditionally, capacitors integrated into memory cells have been patterned after the parallel plate capacitor. A layer of dielectric is deposited between the deposition of two conductive layers and the layers are patterned, either sequentially during deposition or all at once. The patterned dielectric layer becomes the capacitor dielectric while the patterned conductive layers become the top and bottom plates or electrodes of the resultant capacitor structure. The amount of charge stored on the capacitor is proportional to the capacitance, C=.di-elect cons..di-elect cons..sub.0 A/d, where .di-elect cons. is the dielectric constant of the capacitor dielectric, .di-elect cons..sub.0 is the vacuum permittivity, A is the electrode area and d is the spacing between electrodes.
Several techniques have recently been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include increasing the effective surface area (A) of the electrodes by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three dimensional shapes to which the conductive electrodes and interlayer dielectric conform.
FIG. 1 illustrates one commonly used method of increasing cell capacitance through further increasing the surface area of the capacitor electrodes, by providing a roughened or texturized electrode surface. Roughened polycrystalline silicon (polysilicon, or simply poly) in the form of hemispherical grained silicon (HSG silicon or HSG polysilicon), for example, has been implemented for a bottom (or storage) electrode 10 of the capacitor, contacting an active area 12 of a silicon substrate 14. A thin dielectric 16 and a top (or reference) electrode layer 18 are then added conformally over the rough surface of the bottom electrode, taking on similar roughness. The electrode area A, from the capacitance formula above, is thus effectively increased, increasing the capacitance of the memory cell.
As a bottom electrode for a capacitor, however, the roughened polysilicon should be doped for conductivity sufficient to allow the bottom plate 10 to hold the requisite amount of charge. Unfortunately, rough polysilicon deposition techniques, such as HSG vacuum annealing are most effective at lower doping levels. Further doping the silicon of the bottom plate 10 tends to result in diffusion of the dopants through the silicon bottom electrode 10 to the underlying active area 12. For example, phosphorus from solid source P.sub.2 O.sub.5, a commonly employed dopant, diffuses easily through silicon during high temperature anneal steps. Downwardly diffused dopants interfere with junction operation by changing the dopant profile of the active area and the transistor characteristics. Although implanted dopants, such as arsenic ions, diffuse less easily, they fail to dope vertical surfaces, are more expensive, and at any rate do not entirely eliminate the diffusion problem.
An additional problem with the structure of FIG. 1 stems from the presence of exposed crystalline triple points at the surface of the polysilicon bottom plate 10. A triple point occurs at the point at which three individual crystals join. Such heavy stress locations tend to cause cracking in the overlying dielectric layer, resulting in another source of leakage paths. To avoid the problem of cracking, a thicker dielectric layer should be deposited, but this lowers the capacitance of the cell by effectively increasing the electrode spacing d of the capacitance formula set forth above.
Prior art methods to increase cell capacity also include the use of new dielectric materials characterized by effectively higher dielectric constants (.di-elect cons.), such as barium strontium titanate (BST), lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and various other ferro-electric materials. However, these materials are expensive and technical difficulties have been encountered in incorporating them into current integrated circuits with conventional fabrication techniques.
For example, chemical vapor deposition (CVD) of PZT and BST is often accompanied by oxidation of polysilicon electrodes. These new dielectric materials themselves demonstrate chemical and physical instability under a variety of conditions common in current integrated circuit processing. For example, high temperature processes and plasma processes are known to degrade certain high-.di-elect cons. and ferro-electric materials. Very few techniques are therefore available for etching these materials without breaking down the dielectric layer and causing shorts. The problems with these materials have thus far prevented their use in large scale, commercial production of integrated circuits such as DRAMs or SRAMs. Furthermore, even when adequate solutions are developed to allow incorporation of high-dielectric materials, it will still be desirable to further enhance capacitance through use of roughened layers and consequent increased electrode surface area.
Therefore, a need exists for a process for incorporating conventional capacitor materials (such as polysilicon and Si.sub.3 N.sub.4) into future generation integrated circuits, while at the same time providing adequate capacitance and avoiding the problems associated with doping the bottom plate.
USPTO Backgrounds
USPTO Backgrounds