The present invention relates to fabrication processes for ferroelectric devices which include one or more ferrocapacitors, and to ferroelectric devices produced by the fabrication processes.
It is known to produce ferroelectric devices such as FeRAM devices and high k DRAM devices including ferroelectric capacitors produced by depositing the following layers onto a substructure (frequently including a barrier film); a bottom electrode layer, a ferroelectric layer, and a top electrode layer. Hardmask elements, typically formed Tetraethyl Orthosilicate (TEOS), are deposited over the top electrode layer, and used to etch the structure so as to remove portions of the bottom electrode layer, ferroelectric layer, and top electrode layer which are not under the hardmask elements. The etching separates the top electrode layer into top electrodes, the bottom electrode layer into bottom electrodes, and the ferroelectric layer into ferroelectric elements sandwiched by respective pairs of top electrodes and bottom electrodes.
It is known to perform this etching process using a two stage etching process, using first hardmask elements to etch the top electrodes in a first stage, and second hardmask elements to etch the bottom electrode in a second stage.
The second stage of such a process is illustrated in FIGS. 1(a) to 1(e). As shown in FIG. 1(a), following the first stage of etching a structure is formed having an (un-etched) bottom electrode layer 1 covering a substructure 6 (generally comprising a barrier layer and a plug extending downwardly for electrically connecting the bottom electrode to other elements of the device).
Over the bottom electrode layer 1 is a ferroelectric layer 3 and a top electrode layer 5. The top electrode layer 5 and ferroelectric layer 3 have already been etched, using first hard mask elements 7 and an etching process, such as reactive ion etching (RIE).
The process for forming the second hard mask elements used for etching the bottom electrode 1 begins by depositing a TEOS layer 4, and covering portions of it with resist 8 by a lithographic process. Then, as shown in FIG. 1(b), the TEOS layer 4 is etched, leaving the portions under the resist 8 protected. The portions are the second hard mask elements 9. Then, as shown in FIG. 1(c), the resist 8 is removed (a process referred to as xe2x80x9cashingxe2x80x9d). The process shown in FIGS. 1(a) to 1(c) is referred to as xe2x80x9chard mask openingxe2x80x9d (i.e. the formation of the second hard mask elements 9). The second hard mask elements 9 have an initial taper angle marked as xcex1. The second hard mask elements 9 are wider than the first hard mask elements 7, so that there is a fringe 11 at the outer areas of the second hard mask elements 9 where they directly contact the bottom electrode 1.
The second hard mask elements 9 are then used to etch the bottom electrode 1 by a second etching process, such as a RIE process (this is called xe2x80x9cbottom electrode RIE etchingxe2x80x9d). According to the value of xcex1, the resultant structure may be as shown in either of FIG. 1(d) or FIG. 1(e). Initially, as shown in FIG. 1(c), the second hard mask elements 9 have well-defined corners 15, but during the second etching process, they become rounded.
One of the advantages of using a two stage process to fabricate the ferrocapacitor is that one can adjust the width of the fringe 11. Also, the angle of the sides of the remaining portions of the bottom electrode 1 can be selected. This can be seen from FIGS. 1(d) and 1(e). If the taper angle xcex1 of the second hard mask element 9 is almost 90xc2x0, it leads to a taper angle xcex2 of the sides of the bottom electrode which is almost 90xc2x0 as shown in FIG. 1(d). If the taper angle xcex1 of the second hard mask element 9 is lower, it leads to a taper angle xcex2 of the sides of the bottom electrode 1 which is also lower. In the case of high taper angle xcex1 the fringe 11 is wider, which leads to less damage to the bottom electrode 1, because of the protection given to it by the second hard mask element 9.
Looking more closely at the FIG. 1(d) however, it can be seen that in the case that the taper angle of the second hard mask elements 9 is high there is a thick residue 13 deposited on the sides of the second hard mask elements 9 and the bottom electrode 1. This is because residues accumulate easily on such a hard mask. These residues can cause problems in later stages of the device fabrication process, such as the oxidation of the plug.
Note that variations of the process shown in FIGS. 1(a) to 1(e) are known, in which there are multiple ferroelectric capacitors under each of the second hard mask elements 9. Two such capacitor elements 10, 12 are shown in FIG. 1(f), each having the structure of the elements 3, 5, 7 of FIG. 1(a). When the hard mask opening is performed, followed by etching of the bottom electrode 1, this leads to the structure shown in FIG. 1(g).
The present invention aims to address the problems above.
In general terms, the present invention proposes that the second stage of the two stage etching process should be performed including a process to round the shape of the second hard mark elements before the bottom electrode etching. When the etching of the bottom electrode beings, the second hard mask elements may have a taper angle xcex1 in the range 75xc2x0 to 87xc2x0.
Since the taper angle is relatively high, a capacitor can be formed with relatively little damage. However, we have found that due to the rounding process, the formation of residues is dramatically reduced. This is since residues are hardly formed on the upper part of the sides of the second hard mask elements.
The rounding process is referred to here as an etch back process.
In this method, the resist which was used to form the second hard mask elements may be wholly removed, or at least reduced in thickness (e.g. during the etching process itself) to the extent that it is no longer able to fully protect the second hard mask elements, and further RIE etching is performed on the second hard mask elements prior to the bottom electrode etching step.
The taper angle xcex1 can be controlled (reduced to a desired angle) during the etching of the second hard mask layer, such as by controlling the flow rate of O2 and chamber pressure. Alternatively, it can be controlled by a process step which is separate from the etching step (e.g. performed after the hard mask elements have been rounded and before the bottom electrode etching) using a low bias CF4 etching step to adjust the taper angle after the ashing step, such as from almost 90xc2x0 to a selected value.
USPTO Backgrounds
USPTO Backgrounds