Combinatorial processing enables rapid evaluation of semiconductor processing operations. The systems supporting the combinatorial processing are flexible to accommodate the demands for running the different processes either in parallel, serial or some combination of the two.
Some exemplary semiconductor processing operations includes operations for adding (depositions) and removing layers (etch), defining features, preparing layers (e.g., cleans), doping, etc. Similar processing techniques apply to the manufacture of integrated circuit (IC) semiconductor devices, flat panel displays, optoelectronics devices, data storage devices, magneto electronic devices, magneto optic devices, packaged devices, and the like. As feature sizes continue to shrink, improvements, whether in materials, unit processes, or process sequences, are continually being sought for the deposition processes. However, semiconductor companies conduct R&D on full wafer processing through the use of split lots, as the deposition systems are designed to support this processing scheme. This approach has resulted in ever escalating R&D costs and the inability to conduct extensive experimentation in a timely and cost effective manner. Combinatorial processing as applied to semiconductor manufacturing operations enables multiple experiments to be performed on a single substrate.
An improved technique for accommodating gathering of additional data for multiple process variations on a single substrate is provided to enhance the evaluation of the viability of different materials, unit processes, or process sequences.
USPTO Backgrounds
USPTO Backgrounds