<stg><name>karastuba_mul_templa.3</name>


<trans_list>

<trans id="185" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="186" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="190" from="2" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="188" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="189" from="4" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="191" from="5" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="195" from="5" to="8">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="193" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="194" from="7" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="196" from="8" to="9">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="200" from="8" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="198" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="199" from="10" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="201" from="11" to="12">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="202" from="11" to="14">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="204" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="205" from="13" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="207" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="229" from="15" to="20">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="230" from="15" to="16">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="225" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="227" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="228" from="19" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="215" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="236" from="21" to="26">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="237" from="21" to="22">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="22" to="23">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="233" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="234" from="24" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="235" from="25" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="223" from="26" to="27">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="28" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="4" bw="64" op_0_bw="64">
<![CDATA[
:0  %lhs0_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V"/></StgValue>
</operation>

<operation id="29" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="64" op_0_bw="64">
<![CDATA[
:1  %lhs1_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V"/></StgValue>
</operation>

<operation id="30" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="64" op_0_bw="64">
<![CDATA[
:2  %rhs0_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V"/></StgValue>
</operation>

<operation id="31" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="64" op_0_bw="64">
<![CDATA[
:3  %rhs1_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V"/></StgValue>
</operation>

<operation id="32" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="64">
<![CDATA[
:4  %lhs0_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="33" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="64" op_0_bw="64">
<![CDATA[
:5  %lhs1_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="34" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="64" op_0_bw="64">
<![CDATA[
:6  %rhs0_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="35" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="64" op_0_bw="64">
<![CDATA[
:7  %rhs1_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="36" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64">
<![CDATA[
:8  %z0_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V"/></StgValue>
</operation>

<operation id="37" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64">
<![CDATA[
:9  %z2_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V"/></StgValue>
</operation>

<operation id="38" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="64" op_0_bw="64">
<![CDATA[
:10  %cross_mul_digits_dat = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat"/></StgValue>
</operation>

<operation id="39" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="64" op_0_bw="64">
<![CDATA[
:11  %add2_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V"/></StgValue>
</operation>

<operation id="40" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="64" op_0_bw="64">
<![CDATA[
:12  %z1_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="z1_digits_data_V"/></StgValue>
</operation>

<operation id="41" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="0" op_0_bw="0">
<![CDATA[
:13  br label %1

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="42" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0  %i_0 = phi i6 [ 0, %0 ], [ %i, %2 ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="43" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %icmp_ln255 = icmp eq i6 %i_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln255"/></StgValue>
</operation>

<operation id="44" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="45" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %i = add i6 %i_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="46" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln255, label %.preheader270.preheader, label %2

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>

<operation id="47" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="64" op_0_bw="6">
<![CDATA[
:0  %zext_ln255 = zext i6 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln255"/></StgValue>
</operation>

<operation id="48" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %lhs_digits_data_V_ad = getelementptr [64 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="49" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="27" bw="64" op_0_bw="6">
<![CDATA[
:2  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>

<operation id="50" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="0" op_0_bw="0">
<![CDATA[
.preheader270.preheader:0  br label %.preheader270

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="51" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="64" op_0_bw="6">
<![CDATA[
:2  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="52" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %lhs0_tmp_digits_data_3 = getelementptr [32 x i64]* %lhs0_tmp_digits_data, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data_3"/></StgValue>
</operation>

<operation id="53" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:4  store i64 %lhs_digits_data_V_lo, i64* %lhs0_tmp_digits_data_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln255"/></StgValue>
</operation>

<operation id="54" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %lhs0_digits_data_V_a = getelementptr [32 x i64]* %lhs0_digits_data_V, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="55" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:6  store i64 %lhs_digits_data_V_lo, i64* %lhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln255"/></StgValue>
</operation>

<operation id="56" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %1

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="57" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader270:0  %i1_0 = phi i6 [ %i_16, %3 ], [ 0, %.preheader270.preheader ]

]]></Node>
<StgValue><ssdm name="i1_0"/></StgValue>
</operation>

<operation id="58" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader270:1  %icmp_ln256 = icmp eq i6 %i1_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln256"/></StgValue>
</operation>

<operation id="59" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader270:2  %empty_38 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_38"/></StgValue>
</operation>

<operation id="60" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader270:3  %i_16 = add i6 %i1_0, 1

]]></Node>
<StgValue><ssdm name="i_16"/></StgValue>
</operation>

<operation id="61" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader270:4  br i1 %icmp_ln256, label %.preheader269.preheader, label %3

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>

<operation id="62" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %xor_ln256 = xor i6 %i1_0, -32

]]></Node>
<StgValue><ssdm name="xor_ln256"/></StgValue>
</operation>

<operation id="63" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="64" op_0_bw="6">
<![CDATA[
:2  %zext_ln256_1 = zext i6 %xor_ln256 to i64

]]></Node>
<StgValue><ssdm name="zext_ln256_1"/></StgValue>
</operation>

<operation id="64" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %lhs_digits_data_V_ad_5 = getelementptr [64 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln256_1

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad_5"/></StgValue>
</operation>

<operation id="65" st_id="5" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="64" op_0_bw="6">
<![CDATA[
:4  %lhs_digits_data_V_lo_5 = load i64* %lhs_digits_data_V_ad_5, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_5"/></StgValue>
</operation>

<operation id="66" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="0" op_0_bw="0">
<![CDATA[
.preheader269.preheader:0  br label %.preheader269

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="67" st_id="6" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="64" op_0_bw="6">
<![CDATA[
:4  %lhs_digits_data_V_lo_5 = load i64* %lhs_digits_data_V_ad_5, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_5"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="68" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="64" op_0_bw="6">
<![CDATA[
:0  %zext_ln256 = zext i6 %i1_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln256"/></StgValue>
</operation>

<operation id="69" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %lhs1_tmp_digits_data_3 = getelementptr [32 x i64]* %lhs1_tmp_digits_data, i64 0, i64 %zext_ln256

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data_3"/></StgValue>
</operation>

<operation id="70" st_id="7" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:6  store i64 %lhs_digits_data_V_lo_5, i64* %lhs1_tmp_digits_data_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln256"/></StgValue>
</operation>

<operation id="71" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:7  %lhs1_digits_data_V_a = getelementptr [32 x i64]* %lhs1_digits_data_V, i64 0, i64 %zext_ln256

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="72" st_id="7" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:8  store i64 %lhs_digits_data_V_lo_5, i64* %lhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln256"/></StgValue>
</operation>

<operation id="73" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %.preheader270

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="74" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader269:0  %i2_0 = phi i6 [ %i_17, %4 ], [ 0, %.preheader269.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="75" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="56" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader269:1  %icmp_ln257 = icmp eq i6 %i2_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln257"/></StgValue>
</operation>

<operation id="76" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="57" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader269:2  %empty_39 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_39"/></StgValue>
</operation>

<operation id="77" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="58" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader269:3  %i_17 = add i6 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i_17"/></StgValue>
</operation>

<operation id="78" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader269:4  br i1 %icmp_ln257, label %.preheader268.preheader, label %4

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>

<operation id="79" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="64" op_0_bw="6">
<![CDATA[
:0  %zext_ln257 = zext i6 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln257"/></StgValue>
</operation>

<operation id="80" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %rhs_digits_data_V_ad = getelementptr [64 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="81" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="64" op_0_bw="6">
<![CDATA[
:2  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>

<operation id="82" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="0" op_0_bw="0">
<![CDATA[
.preheader268.preheader:0  br label %.preheader268

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="83" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="63" bw="64" op_0_bw="6">
<![CDATA[
:2  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="84" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="64" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %rhs0_tmp_digits_data_3 = getelementptr [32 x i64]* %rhs0_tmp_digits_data, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data_3"/></StgValue>
</operation>

<operation id="85" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="65" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:4  store i64 %rhs_digits_data_V_lo, i64* %rhs0_tmp_digits_data_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln257"/></StgValue>
</operation>

<operation id="86" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="66" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %rhs0_digits_data_V_a = getelementptr [32 x i64]* %rhs0_digits_data_V, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="87" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="67" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:6  store i64 %rhs_digits_data_V_lo, i64* %rhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln257"/></StgValue>
</operation>

<operation id="88" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %.preheader269

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="89" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader268:0  %i3_0 = phi i6 [ %i_18, %5 ], [ 0, %.preheader268.preheader ]

]]></Node>
<StgValue><ssdm name="i3_0"/></StgValue>
</operation>

<operation id="90" st_id="11" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="73" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader268:1  %icmp_ln258 = icmp eq i6 %i3_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln258"/></StgValue>
</operation>

<operation id="91" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader268:2  %empty_40 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_40"/></StgValue>
</operation>

<operation id="92" st_id="11" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="75" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader268:3  %i_18 = add i6 %i3_0, 1

]]></Node>
<StgValue><ssdm name="i_18"/></StgValue>
</operation>

<operation id="93" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader268:4  br i1 %icmp_ln258, label %._crit_edge, label %5

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>

<operation id="94" st_id="11" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %xor_ln258 = xor i6 %i3_0, -32

]]></Node>
<StgValue><ssdm name="xor_ln258"/></StgValue>
</operation>

<operation id="95" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="64" op_0_bw="6">
<![CDATA[
:2  %zext_ln258_1 = zext i6 %xor_ln258 to i64

]]></Node>
<StgValue><ssdm name="zext_ln258_1"/></StgValue>
</operation>

<operation id="96" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %rhs_digits_data_V_ad_5 = getelementptr [64 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln258_1

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad_5"/></StgValue>
</operation>

<operation id="97" st_id="11" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="64" op_0_bw="6">
<![CDATA[
:4  %rhs_digits_data_V_lo_5 = load i64* %rhs_digits_data_V_ad_5, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_5"/></StgValue>
</operation>

<operation id="98" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:0  %z0_tmp_bits = call fastcc i4 @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs0_digits_data_V, i2 0, [32 x i64]* %rhs0_digits_data_V, [64 x i64]* %z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="z0_tmp_bits"/></StgValue>
</operation>

<operation id="99" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:1  %z2_tmp_bits = call fastcc i4 @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs1_digits_data_V, i2 0, [32 x i64]* %rhs1_digits_data_V, [64 x i64]* %z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="z2_tmp_bits"/></StgValue>
</operation>

<operation id="100" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="4" op_0_bw="4" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:2  %cross_mul_tmp_bits = call fastcc i4 @karastuba_mul_templa([32 x i64]* %lhs0_tmp_digits_data, [32 x i64]* %lhs1_tmp_digits_data, [32 x i64]* %rhs0_tmp_digits_data, [32 x i64]* %rhs1_tmp_digits_data, [64 x i64]* %cross_mul_digits_dat)

]]></Node>
<StgValue><ssdm name="cross_mul_tmp_bits"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="101" st_id="12" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="64" op_0_bw="6">
<![CDATA[
:4  %rhs_digits_data_V_lo_5 = load i64* %rhs_digits_data_V_ad_5, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_5"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="102" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="64" op_0_bw="6">
<![CDATA[
:0  %zext_ln258 = zext i6 %i3_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln258"/></StgValue>
</operation>

<operation id="103" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="83" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %rhs1_tmp_digits_data_3 = getelementptr [32 x i64]* %rhs1_tmp_digits_data, i64 0, i64 %zext_ln258

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data_3"/></StgValue>
</operation>

<operation id="104" st_id="13" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="84" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:6  store i64 %rhs_digits_data_V_lo_5, i64* %rhs1_tmp_digits_data_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln258"/></StgValue>
</operation>

<operation id="105" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="85" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:7  %rhs1_digits_data_V_a = getelementptr [32 x i64]* %rhs1_digits_data_V, i64 0, i64 %zext_ln258

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="106" st_id="13" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="86" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
:8  store i64 %rhs_digits_data_V_lo_5, i64* %rhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln258"/></StgValue>
</operation>

<operation id="107" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="87" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %.preheader268

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="108" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="89" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:0  %z0_tmp_bits = call fastcc i4 @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs0_digits_data_V, i2 0, [32 x i64]* %rhs0_digits_data_V, [64 x i64]* %z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="z0_tmp_bits"/></StgValue>
</operation>

<operation id="109" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:1  %z2_tmp_bits = call fastcc i4 @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs1_digits_data_V, i2 0, [32 x i64]* %rhs1_digits_data_V, [64 x i64]* %z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="z2_tmp_bits"/></StgValue>
</operation>

<operation id="110" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="91" bw="4" op_0_bw="4" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
._crit_edge:2  %cross_mul_tmp_bits = call fastcc i4 @karastuba_mul_templa([32 x i64]* %lhs0_tmp_digits_data, [32 x i64]* %lhs1_tmp_digits_data, [32 x i64]* %rhs0_tmp_digits_data, [32 x i64]* %rhs1_tmp_digits_data, [64 x i64]* %cross_mul_digits_dat)

]]></Node>
<StgValue><ssdm name="cross_mul_tmp_bits"/></StgValue>
</operation>

<operation id="111" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="92" bw="5" op_0_bw="4">
<![CDATA[
._crit_edge:3  %zext_ln266 = zext i4 %cross_mul_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln266"/></StgValue>
</operation>

<operation id="112" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="93" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge:4  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="113" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="95" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader.i:0  %p_088_0_i = phi i2 [ %trunc_ln, %hls_label_24 ], [ 0, %._crit_edge ]

]]></Node>
<StgValue><ssdm name="p_088_0_i"/></StgValue>
</operation>

<operation id="114" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader.i:1  %i_0_i = phi i7 [ %i_19, %hls_label_24 ], [ 0, %._crit_edge ]

]]></Node>
<StgValue><ssdm name="i_0_i"/></StgValue>
</operation>

<operation id="115" st_id="15" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="97" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i:2  %icmp_ln53 = icmp eq i7 %i_0_i, -64

]]></Node>
<StgValue><ssdm name="icmp_ln53"/></StgValue>
</operation>

<operation id="116" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="98" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i:3  %empty_41 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="117" st_id="15" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="99" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i:4  %i_19 = add i7 %i_0_i, 1

]]></Node>
<StgValue><ssdm name="i_19"/></StgValue>
</operation>

<operation id="118" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="100" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i:5  br i1 %icmp_ln53, label %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit", label %hls_label_24

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>

<operation id="119" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="64" op_0_bw="7">
<![CDATA[
hls_label_24:3  %zext_ln58 = zext i7 %i_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln58"/></StgValue>
</operation>

<operation id="120" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_24:4  %z0_digits_data_V_add = getelementptr [64 x i64]* %z0_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_add"/></StgValue>
</operation>

<operation id="121" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="64" op_0_bw="6">
<![CDATA[
hls_label_24:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="122" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_24:7  %z2_digits_data_V_add = getelementptr [64 x i64]* %z2_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_add"/></StgValue>
</operation>

<operation id="123" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="64" op_0_bw="6">
<![CDATA[
hls_label_24:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="124" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="64" op_0_bw="6">
<![CDATA[
hls_label_24:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="125" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="64" op_0_bw="6">
<![CDATA[
hls_label_24:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="126" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="65" op_0_bw="64">
<![CDATA[
hls_label_24:6  %zext_ln209 = zext i64 %z0_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln209"/></StgValue>
</operation>

<operation id="127" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="65" op_0_bw="64">
<![CDATA[
hls_label_24:9  %zext_ln700 = zext i64 %z2_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln700"/></StgValue>
</operation>

<operation id="128" st_id="17" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_24:11  %add_ln700 = add i65 %zext_ln209, %zext_ln700

]]></Node>
<StgValue><ssdm name="add_ln700"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="129" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="66" op_0_bw="2">
<![CDATA[
hls_label_24:0  %zext_ln53 = zext i2 %p_088_0_i to i66

]]></Node>
<StgValue><ssdm name="zext_ln53"/></StgValue>
</operation>

<operation id="130" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="64" op_0_bw="2">
<![CDATA[
hls_label_24:10  %zext_ln700_24 = zext i2 %p_088_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_24"/></StgValue>
</operation>

<operation id="131" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="66" op_0_bw="65">
<![CDATA[
hls_label_24:12  %zext_ln700_25 = zext i65 %add_ln700 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_25"/></StgValue>
</operation>

<operation id="132" st_id="18" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_24:13  %tmp_V = add i66 %zext_ln700_25, %zext_ln53

]]></Node>
<StgValue><ssdm name="tmp_V"/></StgValue>
</operation>

<operation id="133" st_id="18" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_24:14  %add_ln209_13 = add i64 %z2_digits_data_V_loa, %zext_ln700_24

]]></Node>
<StgValue><ssdm name="add_ln209_13"/></StgValue>
</operation>

<operation id="134" st_id="18" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_24:15  %add_ln209 = add i64 %add_ln209_13, %z0_digits_data_V_loa

]]></Node>
<StgValue><ssdm name="add_ln209"/></StgValue>
</operation>

<operation id="135" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_24:18  %trunc_ln = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="136" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_24:1  %tmp_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str17)

]]></Node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="137" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_24:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln55"/></StgValue>
</operation>

<operation id="138" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_24:16  %add2_digits_data_V_a = getelementptr [64 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a"/></StgValue>
</operation>

<operation id="139" st_id="19" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_24:17  store i64 %add_ln209, i64* %add2_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln60"/></StgValue>
</operation>

<operation id="140" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="121" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_24:19  %empty_42 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str17, i32 %tmp_i)

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>

<operation id="141" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="0" op_0_bw="0">
<![CDATA[
hls_label_24:20  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="142" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="124" bw="6" op_0_bw="2">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:0  %zext_ln63 = zext i2 %p_088_0_i to i6

]]></Node>
<StgValue><ssdm name="zext_ln63"/></StgValue>
</operation>

<operation id="143" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="5" op_0_bw="4">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:1  %zext_ln63_1 = zext i4 %z0_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln63_1"/></StgValue>
</operation>

<operation id="144" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="126" bw="5" op_0_bw="4">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:2  %zext_ln63_2 = zext i4 %z2_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln63_2"/></StgValue>
</operation>

<operation id="145" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:3  %add_ln63 = add i5 %zext_ln63_2, %zext_ln63_1

]]></Node>
<StgValue><ssdm name="add_ln63"/></StgValue>
</operation>

<operation id="146" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="6" op_0_bw="5">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:4  %zext_ln63_8 = zext i5 %add_ln63 to i6

]]></Node>
<StgValue><ssdm name="zext_ln63_8"/></StgValue>
</operation>

<operation id="147" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="129" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:5  %add2_tmp_bits = add i6 %zext_ln63, %zext_ln63_8

]]></Node>
<StgValue><ssdm name="add2_tmp_bits"/></StgValue>
</operation>

<operation id="148" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="130" bw="7" op_0_bw="6">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:6  %zext_ln63_9 = zext i6 %add2_tmp_bits to i7

]]></Node>
<StgValue><ssdm name="zext_ln63_9"/></StgValue>
</operation>

<operation id="149" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="131" bw="0" op_0_bw="0">
<![CDATA[
add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:7  br label %.preheader.i2

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="150" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="133" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
<![CDATA[
.preheader.i2:0  %op2_assign = phi i1 [ %tmp, %hls_label_25 ], [ false, %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="op2_assign"/></StgValue>
</operation>

<operation id="151" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="134" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader.i2:1  %i_0_i1 = phi i7 [ %i_20, %hls_label_25 ], [ 0, %"add_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="i_0_i1"/></StgValue>
</operation>

<operation id="152" st_id="21" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="135" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i2:2  %exitcond_i = icmp eq i7 %i_0_i1, -64

]]></Node>
<StgValue><ssdm name="exitcond_i"/></StgValue>
</operation>

<operation id="153" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="136" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i2:3  %empty_43 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_43"/></StgValue>
</operation>

<operation id="154" st_id="21" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="137" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
.preheader.i2:4  %i_20 = add i7 %i_0_i1, 1

]]></Node>
<StgValue><ssdm name="i_20"/></StgValue>
</operation>

<operation id="155" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="138" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i2:5  br i1 %exitcond_i, label %"sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit", label %hls_label_25

]]></Node>
<StgValue><ssdm name="br_ln77"/></StgValue>
</operation>

<operation id="156" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="142" bw="64" op_0_bw="7">
<![CDATA[
hls_label_25:2  %zext_ln80 = zext i7 %i_0_i1 to i64

]]></Node>
<StgValue><ssdm name="zext_ln80"/></StgValue>
</operation>

<operation id="157" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="143" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_25:3  %cross_mul_digits_dat_5 = getelementptr [64 x i64]* %cross_mul_digits_dat, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_5"/></StgValue>
</operation>

<operation id="158" st_id="21" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="144" bw="64" op_0_bw="6">
<![CDATA[
hls_label_25:4  %cross_mul_digits_dat_6 = load i64* %cross_mul_digits_dat_5, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_6"/></StgValue>
</operation>

<operation id="159" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="146" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_25:6  %add2_digits_data_V_a_3 = getelementptr [64 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a_3"/></StgValue>
</operation>

<operation id="160" st_id="21" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="64" op_0_bw="6">
<![CDATA[
hls_label_25:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_3, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="161" st_id="22" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="144" bw="64" op_0_bw="6">
<![CDATA[
hls_label_25:4  %cross_mul_digits_dat_6 = load i64* %cross_mul_digits_dat_5, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_6"/></StgValue>
</operation>

<operation id="162" st_id="22" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="64" op_0_bw="6">
<![CDATA[
hls_label_25:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_3, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="163" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="145" bw="65" op_0_bw="64">
<![CDATA[
hls_label_25:5  %zext_ln180 = zext i64 %cross_mul_digits_dat_6 to i65

]]></Node>
<StgValue><ssdm name="zext_ln180"/></StgValue>
</operation>

<operation id="164" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="65" op_0_bw="64">
<![CDATA[
hls_label_25:8  %zext_ln701 = zext i64 %add2_digits_data_V_l to i65

]]></Node>
<StgValue><ssdm name="zext_ln701"/></StgValue>
</operation>

<operation id="165" st_id="23" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="149" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_25:9  %tmp_V_10 = sub i65 %zext_ln180, %zext_ln701

]]></Node>
<StgValue><ssdm name="tmp_V_10"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="166" st_id="24" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="150" bw="65" op_0_bw="1" op_1_bw="65" op_2_bw="65">
<![CDATA[
hls_label_25:10  %select_ln701 = select i1 %op2_assign, i65 -1, i65 0

]]></Node>
<StgValue><ssdm name="select_ln701"/></StgValue>
</operation>

<operation id="167" st_id="24" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="1" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_25:11  %select_ln701_3 = select i1 %op2_assign, i64 -1, i64 0

]]></Node>
<StgValue><ssdm name="select_ln701_3"/></StgValue>
</operation>

<operation id="168" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="64" op_0_bw="65">
<![CDATA[
hls_label_25:12  %trunc_ln701 = trunc i65 %tmp_V_10 to i64

]]></Node>
<StgValue><ssdm name="trunc_ln701"/></StgValue>
</operation>

<operation id="169" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_25:13  %tmp_V_11 = add i65 %select_ln701, %tmp_V_10

]]></Node>
<StgValue><ssdm name="tmp_V_11"/></StgValue>
</operation>

<operation id="170" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="1" op_0_bw="1" op_1_bw="65" op_2_bw="32">
<![CDATA[
hls_label_25:14  %tmp = call i1 @_ssdm_op_BitSelect.i1.i65.i32(i65 %tmp_V_11, i32 64)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="171" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_25:15  %add_ln700_15 = add i64 %trunc_ln701, %select_ln701_3

]]></Node>
<StgValue><ssdm name="add_ln700_15"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="172" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_25:0  %tmp_i3 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str16)

]]></Node>
<StgValue><ssdm name="tmp_i3"/></StgValue>
</operation>

<operation id="173" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="141" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_25:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln79"/></StgValue>
</operation>

<operation id="174" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="156" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_25:16  %z1_digits_data_V_add = getelementptr [64 x i64]* %z1_digits_data_V, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="z1_digits_data_V_add"/></StgValue>
</operation>

<operation id="175" st_id="25" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_25:17  store i64 %add_ln700_15, i64* %z1_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln88"/></StgValue>
</operation>

<operation id="176" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_25:18  %empty_44 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str16, i32 %tmp_i3)

]]></Node>
<StgValue><ssdm name="empty_44"/></StgValue>
</operation>

<operation id="177" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="0" op_0_bw="0">
<![CDATA[
hls_label_25:19  br label %.preheader.i2

]]></Node>
<StgValue><ssdm name="br_ln77"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="178" st_id="26" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="161" bw="5" op_0_bw="1" op_1_bw="5" op_2_bw="5">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:0  %empty_45 = select i1 %op2_assign, i5 -1, i5 0

]]></Node>
<StgValue><ssdm name="empty_45"/></StgValue>
</operation>

<operation id="179" st_id="26" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="162" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:1  %add_ln95 = add i5 %empty_45, %zext_ln266

]]></Node>
<StgValue><ssdm name="add_ln95"/></StgValue>
</operation>

<operation id="180" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="163" bw="7" op_0_bw="5">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:2  %sext_ln95 = sext i5 %add_ln95 to i7

]]></Node>
<StgValue><ssdm name="sext_ln95"/></StgValue>
</operation>

<operation id="181" st_id="26" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="164" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:3  %z1_tmp_bits = sub i7 %sext_ln95, %zext_ln63_9

]]></Node>
<StgValue><ssdm name="z1_tmp_bits"/></StgValue>
</operation>

<operation id="182" st_id="26" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="165" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="7" op_3_bw="64" op_4_bw="64" op_5_bw="64" op_6_bw="4" op_7_bw="4">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:4  call fastcc void @CAT_I_I_I_O([64 x i64]* %z0_digits_data_V, i7 %z1_tmp_bits, [64 x i64]* %z1_digits_data_V, [64 x i64]* %z2_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln275"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="183" st_id="27" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="165" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="7" op_3_bw="64" op_4_bw="64" op_5_bw="64" op_6_bw="4" op_7_bw="4">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:4  call fastcc void @CAT_I_I_I_O([64 x i64]* %z0_digits_data_V, i7 %z1_tmp_bits, [64 x i64]* %z1_digits_data_V, [64 x i64]* %z2_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln275"/></StgValue>
</operation>

<operation id="184" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="166" bw="0">
<![CDATA[
sub_I_O<Bignum<64, 64>, Bignum<64, 64> >.exit:5  ret void

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
