<stg><name>karastuba_mul</name>


<trans_list>

<trans id="69" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="85" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="86" from="2" to="2">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="72" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="89" from="4" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="90" from="4" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="88" from="5" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="77" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="78" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="94" from="8" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="95" from="8" to="9">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="92" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="93" from="10" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="3" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
:0  call void (...)* @_ssdm_op_SpecBitsMap(i64* %hs_input_V), !map !160

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="4" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecBitsMap(i64* %res_output_V), !map !166

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecTopModule([14 x i8]* @karastuba_mul_str) nounwind

]]></Node>
<StgValue><ssdm name="spectopmodule_ln0"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="64" op_0_bw="64">
<![CDATA[
:3  %lhs_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="64" op_0_bw="64">
<![CDATA[
:4  %rhs_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="64">
<![CDATA[
:5  %res_digits_data_V = alloca [128 x i64], align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
:6  call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specinterface_ln317"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
:7  call void (...)* @_ssdm_op_SpecInterface(i64* %hs_input_V, [5 x i8]* @p_str2, i32 1, i32 1, [5 x i8]* @p_str3, i32 0, i32 1024, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln318"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
:8  call void (...)* @_ssdm_op_SpecInterface(i64* %res_output_V, [5 x i8]* @p_str2, i32 1, i32 1, [5 x i8]* @p_str3, i32 0, i32 1024, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln319"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %1

]]></Node>
<StgValue><ssdm name="br_ln326"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="22" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:0  %i_0 = phi i7 [ 0, %0 ], [ %i, %hls_label_0 ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="23" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
:1  %icmp_ln326 = icmp eq i7 %i_0, -64

]]></Node>
<StgValue><ssdm name="icmp_ln326"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="25" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
:3  %i = add i7 %i_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln326, label %.preheader.preheader, label %hls_label_0

]]></Node>
<StgValue><ssdm name="br_ln326"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_0:0  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str4)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_0:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln328"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="22" bw="64" op_0_bw="7">
<![CDATA[
hls_label_0:2  %zext_ln329 = zext i7 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln329"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_0:3  %hs_input_V_read = call i64 @_ssdm_op_Read.axis.volatile.i64P(i64* %hs_input_V)

]]></Node>
<StgValue><ssdm name="hs_input_V_read"/></StgValue>
</operation>

<operation id="31" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="24" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_0:4  %lhs_digits_data_V_ad = getelementptr [64 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln329

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="32" st_id="2" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_0:5  store i64 %hs_input_V_read, i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="store_ln329"/></StgValue>
</operation>

<operation id="33" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_0:6  %empty_55 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str4, i32 %tmp)

]]></Node>
<StgValue><ssdm name="empty_55"/></StgValue>
</operation>

<operation id="34" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln326" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="0">
<![CDATA[
hls_label_0:7  br label %1

]]></Node>
<StgValue><ssdm name="br_ln326"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="35" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="0">
<![CDATA[
.preheader.preheader:0  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln331"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="36" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="8" op_0_bw="8" op_1_bw="0" op_2_bw="8" op_3_bw="0">
<![CDATA[
.preheader:0  %i1_0 = phi i8 [ %i_24, %hls_label_1 ], [ 64, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="i1_0"/></StgValue>
</operation>

<operation id="37" st_id="4" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.preheader:1  %icmp_ln331 = icmp eq i8 %i1_0, -128

]]></Node>
<StgValue><ssdm name="icmp_ln331"/></StgValue>
</operation>

<operation id="38" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:2  %empty_56 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="39" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:3  br i1 %icmp_ln331, label %2, label %hls_label_1

]]></Node>
<StgValue><ssdm name="br_ln331"/></StgValue>
</operation>

<operation id="40" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
hls_label_1:2  %add_ln334 = add i8 %i1_0, -64

]]></Node>
<StgValue><ssdm name="add_ln334"/></StgValue>
</operation>

<operation id="41" st_id="4" stage="1" lat="1">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_1:4  %hs_input_V_read_1 = call i64 @_ssdm_op_Read.axis.volatile.i64P(i64* %hs_input_V)

]]></Node>
<StgValue><ssdm name="hs_input_V_read_1"/></StgValue>
</operation>

<operation id="42" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
hls_label_1:8  %i_24 = add i8 %i1_0, 1

]]></Node>
<StgValue><ssdm name="i_24"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="43" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_1:0  %tmp_5 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str5)

]]></Node>
<StgValue><ssdm name="tmp_5"/></StgValue>
</operation>

<operation id="44" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_1:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln333"/></StgValue>
</operation>

<operation id="45" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="39" bw="64" op_0_bw="8">
<![CDATA[
hls_label_1:3  %zext_ln334 = zext i8 %add_ln334 to i64

]]></Node>
<StgValue><ssdm name="zext_ln334"/></StgValue>
</operation>

<operation id="46" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_1:5  %rhs_digits_data_V_ad = getelementptr [64 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln334

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="47" st_id="5" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_1:6  store i64 %hs_input_V_read_1, i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="store_ln334"/></StgValue>
</operation>

<operation id="48" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_1:7  %empty_57 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str5, i32 %tmp_5)

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>

<operation id="49" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln331" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="0" op_0_bw="0">
<![CDATA[
hls_label_1:9  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln331"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="50" st_id="6" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:0  call fastcc void @karastuba_mul_templa.3([64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln338"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="51" st_id="7" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:0  call fastcc void @karastuba_mul_templa.3([64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln338"/></StgValue>
</operation>

<operation id="52" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln340"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="53" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="8" op_0_bw="8" op_1_bw="0" op_2_bw="8" op_3_bw="0">
<![CDATA[
:0  %i2_0 = phi i8 [ 0, %2 ], [ %i_25, %hls_label_2 ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="54" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
:1  %icmp_ln340 = icmp eq i8 %i2_0, -128

]]></Node>
<StgValue><ssdm name="icmp_ln340"/></StgValue>
</operation>

<operation id="55" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_58 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 128, i64 128, i64 128)

]]></Node>
<StgValue><ssdm name="empty_58"/></StgValue>
</operation>

<operation id="56" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
:3  %i_25 = add i8 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i_25"/></StgValue>
</operation>

<operation id="57" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln340, label %4, label %hls_label_2

]]></Node>
<StgValue><ssdm name="br_ln340"/></StgValue>
</operation>

<operation id="58" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="64" op_0_bw="8">
<![CDATA[
hls_label_2:2  %zext_ln343 = zext i8 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln343"/></StgValue>
</operation>

<operation id="59" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="7" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_2:3  %res_digits_data_V_ad = getelementptr [128 x i64]* %res_digits_data_V, i64 0, i64 %zext_ln343

]]></Node>
<StgValue><ssdm name="res_digits_data_V_ad"/></StgValue>
</operation>

<operation id="60" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="64" op_0_bw="7">
<![CDATA[
hls_label_2:4  %res_digits_data_V_lo = load i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="61" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="64" op_0_bw="7">
<![CDATA[
hls_label_2:4  %res_digits_data_V_lo = load i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo"/></StgValue>
</operation>

<operation id="62" st_id="9" stage="2" lat="2">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_2:5  call void @_ssdm_op_Write.axis.volatile.i64P(i64* %res_output_V, i64 %res_digits_data_V_lo)

]]></Node>
<StgValue><ssdm name="write_ln343"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="63" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_2:0  %tmp_6 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str6)

]]></Node>
<StgValue><ssdm name="tmp_6"/></StgValue>
</operation>

<operation id="64" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_2:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln342"/></StgValue>
</operation>

<operation id="65" st_id="10" stage="1" lat="2">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_2:5  call void @_ssdm_op_Write.axis.volatile.i64P(i64* %res_output_V, i64 %res_digits_data_V_lo)

]]></Node>
<StgValue><ssdm name="write_ln343"/></StgValue>
</operation>

<operation id="66" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_2:6  %empty_59 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str6, i32 %tmp_6)

]]></Node>
<StgValue><ssdm name="empty_59"/></StgValue>
</operation>

<operation id="67" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln340" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="0" op_0_bw="0">
<![CDATA[
hls_label_2:7  br label %3

]]></Node>
<StgValue><ssdm name="br_ln340"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="68" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="65" bw="0">
<![CDATA[
:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln346"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
