<stg><name>karastuba_mul_templa.4</name>


<trans_list>

<trans id="280" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="281" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="285" from="2" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="283" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="284" from="4" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="286" from="5" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="290" from="5" to="8">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="288" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="289" from="7" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="291" from="8" to="9">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="295" from="8" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="293" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="294" from="10" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="296" from="11" to="12">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="297" from="11" to="14">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="299" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="300" from="13" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="302" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="343" from="15" to="20">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="344" from="15" to="16">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="339" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="340" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="341" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="342" from="19" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="310" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="350" from="21" to="26">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="351" from="21" to="22">
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="346" from="22" to="23">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="347" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="348" from="24" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="349" from="25" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="318" from="26" to="27">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="319" from="27" to="33">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln278" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="320" from="27" to="28">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln278" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="357" from="28" to="33">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="358" from="28" to="29">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="353" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="354" from="30" to="31">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="355" from="31" to="32">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="356" from="32" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="328" from="33" to="40">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln292" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="329" from="33" to="34">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln292" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="364" from="34" to="39">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="365" from="34" to="35">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="360" from="35" to="36">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="361" from="36" to="37">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="362" from="37" to="38">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="363" from="38" to="34">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="337" from="39" to="40">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="41" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
:0  %rhs_tmp_bits_read_2 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %rhs_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="rhs_tmp_bits_read_2"/></StgValue>
</operation>

<operation id="42" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
:1  %lhs_tmp_bits_read_2 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %lhs_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="lhs_tmp_bits_read_2"/></StgValue>
</operation>

<operation id="43" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="64">
<![CDATA[
:2  %lhs0_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V"/></StgValue>
</operation>

<operation id="44" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="64" op_0_bw="64">
<![CDATA[
:3  %lhs1_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V"/></StgValue>
</operation>

<operation id="45" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="64" op_0_bw="64">
<![CDATA[
:4  %rhs0_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V"/></StgValue>
</operation>

<operation id="46" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="64" op_0_bw="64">
<![CDATA[
:5  %rhs1_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V"/></StgValue>
</operation>

<operation id="47" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64">
<![CDATA[
:6  %lhs0_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="48" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64">
<![CDATA[
:7  %lhs1_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="49" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="64" op_0_bw="64">
<![CDATA[
:8  %rhs0_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="50" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="64" op_0_bw="64">
<![CDATA[
:9  %rhs1_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="51" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="64" op_0_bw="64">
<![CDATA[
:10  %z0_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V"/></StgValue>
</operation>

<operation id="52" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="64" op_0_bw="64">
<![CDATA[
:11  %z2_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V"/></StgValue>
</operation>

<operation id="53" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="64" op_0_bw="64">
<![CDATA[
:12  %cross_mul_digits_dat = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat"/></StgValue>
</operation>

<operation id="54" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="64" op_0_bw="64">
<![CDATA[
:13  %add2_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V"/></StgValue>
</operation>

<operation id="55" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="64" op_0_bw="64">
<![CDATA[
:14  %z1_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="z1_digits_data_V"/></StgValue>
</operation>

<operation id="56" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="0">
<![CDATA[
:15  br label %1

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="57" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
:0  %i_0 = phi i5 [ 0, %0 ], [ %i, %2 ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="58" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
:1  %icmp_ln255 = icmp eq i5 %i_0, -16

]]></Node>
<StgValue><ssdm name="icmp_ln255"/></StgValue>
</operation>

<operation id="59" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="60" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:3  %i = add i5 %i_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="61" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln255, label %.preheader270.preheader, label %2

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>

<operation id="62" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="64" op_0_bw="5">
<![CDATA[
:0  %zext_ln255 = zext i5 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln255"/></StgValue>
</operation>

<operation id="63" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %lhs_digits_data_V_ad = getelementptr [32 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="64" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="64" op_0_bw="5">
<![CDATA[
:2  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>

<operation id="65" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln255" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="0">
<![CDATA[
.preheader270.preheader:0  br label %.preheader270

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="66" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="64" op_0_bw="5">
<![CDATA[
:2  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="67" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %lhs0_tmp_digits_data_2 = getelementptr [16 x i64]* %lhs0_tmp_digits_data, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data_2"/></StgValue>
</operation>

<operation id="68" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:4  store i64 %lhs_digits_data_V_lo, i64* %lhs0_tmp_digits_data_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln255"/></StgValue>
</operation>

<operation id="69" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %lhs0_digits_data_V_a = getelementptr [16 x i64]* %lhs0_digits_data_V, i64 0, i64 %zext_ln255

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="70" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:6  store i64 %lhs_digits_data_V_lo, i64* %lhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln255"/></StgValue>
</operation>

<operation id="71" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %1

]]></Node>
<StgValue><ssdm name="br_ln255"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="72" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader270:0  %i1_0 = phi i5 [ %i_9, %3 ], [ 0, %.preheader270.preheader ]

]]></Node>
<StgValue><ssdm name="i1_0"/></StgValue>
</operation>

<operation id="73" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader270:1  %icmp_ln256 = icmp eq i5 %i1_0, -16

]]></Node>
<StgValue><ssdm name="icmp_ln256"/></StgValue>
</operation>

<operation id="74" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader270:2  %empty_26 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_26"/></StgValue>
</operation>

<operation id="75" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader270:3  %i_9 = add i5 %i1_0, 1

]]></Node>
<StgValue><ssdm name="i_9"/></StgValue>
</operation>

<operation id="76" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader270:4  br i1 %icmp_ln256, label %.preheader269.preheader, label %3

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>

<operation id="77" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:1  %xor_ln256 = xor i5 %i1_0, -16

]]></Node>
<StgValue><ssdm name="xor_ln256"/></StgValue>
</operation>

<operation id="78" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="64" op_0_bw="5">
<![CDATA[
:2  %zext_ln256_2 = zext i5 %xor_ln256 to i64

]]></Node>
<StgValue><ssdm name="zext_ln256_2"/></StgValue>
</operation>

<operation id="79" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %lhs_digits_data_V_ad_3 = getelementptr [32 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln256_2

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad_3"/></StgValue>
</operation>

<operation id="80" st_id="5" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="64" op_0_bw="5">
<![CDATA[
:4  %lhs_digits_data_V_lo_3 = load i64* %lhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_3"/></StgValue>
</operation>

<operation id="81" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln256" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="0" op_0_bw="0">
<![CDATA[
.preheader269.preheader:0  br label %.preheader269

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="82" st_id="6" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="64" op_0_bw="5">
<![CDATA[
:4  %lhs_digits_data_V_lo_3 = load i64* %lhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="83" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="64" op_0_bw="5">
<![CDATA[
:0  %zext_ln256 = zext i5 %i1_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln256"/></StgValue>
</operation>

<operation id="84" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %lhs1_tmp_digits_data_2 = getelementptr [16 x i64]* %lhs1_tmp_digits_data, i64 0, i64 %zext_ln256

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data_2"/></StgValue>
</operation>

<operation id="85" st_id="7" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:6  store i64 %lhs_digits_data_V_lo_3, i64* %lhs1_tmp_digits_data_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln256"/></StgValue>
</operation>

<operation id="86" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:7  %lhs1_digits_data_V_a = getelementptr [16 x i64]* %lhs1_digits_data_V, i64 0, i64 %zext_ln256

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="87" st_id="7" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:8  store i64 %lhs_digits_data_V_lo_3, i64* %lhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln256"/></StgValue>
</operation>

<operation id="88" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %.preheader270

]]></Node>
<StgValue><ssdm name="br_ln256"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="89" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="59" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader269:0  %i2_0 = phi i5 [ %i_10, %4 ], [ 0, %.preheader269.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="90" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="60" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader269:1  %icmp_ln257 = icmp eq i5 %i2_0, -16

]]></Node>
<StgValue><ssdm name="icmp_ln257"/></StgValue>
</operation>

<operation id="91" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader269:2  %empty_27 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_27"/></StgValue>
</operation>

<operation id="92" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="62" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader269:3  %i_10 = add i5 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i_10"/></StgValue>
</operation>

<operation id="93" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="63" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader269:4  br i1 %icmp_ln257, label %.preheader268.preheader, label %4

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>

<operation id="94" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="64" op_0_bw="5">
<![CDATA[
:0  %zext_ln257 = zext i5 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln257"/></StgValue>
</operation>

<operation id="95" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:1  %rhs_digits_data_V_ad = getelementptr [32 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="96" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="64" op_0_bw="5">
<![CDATA[
:2  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>

<operation id="97" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln257" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="0" op_0_bw="0">
<![CDATA[
.preheader268.preheader:0  br label %.preheader268

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="98" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="67" bw="64" op_0_bw="5">
<![CDATA[
:2  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="99" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %rhs0_tmp_digits_data_2 = getelementptr [16 x i64]* %rhs0_tmp_digits_data, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data_2"/></StgValue>
</operation>

<operation id="100" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="69" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:4  store i64 %rhs_digits_data_V_lo, i64* %rhs0_tmp_digits_data_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln257"/></StgValue>
</operation>

<operation id="101" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %rhs0_digits_data_V_a = getelementptr [16 x i64]* %rhs0_digits_data_V, i64 0, i64 %zext_ln257

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="102" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="71" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:6  store i64 %rhs_digits_data_V_lo, i64* %rhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln257"/></StgValue>
</operation>

<operation id="103" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %.preheader269

]]></Node>
<StgValue><ssdm name="br_ln257"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="104" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader268:0  %i3_0 = phi i5 [ %i_11, %5 ], [ 0, %.preheader268.preheader ]

]]></Node>
<StgValue><ssdm name="i3_0"/></StgValue>
</operation>

<operation id="105" st_id="11" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="77" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader268:1  %icmp_ln258 = icmp eq i5 %i3_0, -16

]]></Node>
<StgValue><ssdm name="icmp_ln258"/></StgValue>
</operation>

<operation id="106" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader268:2  %empty_28 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_28"/></StgValue>
</operation>

<operation id="107" st_id="11" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader268:3  %i_11 = add i5 %i3_0, 1

]]></Node>
<StgValue><ssdm name="i_11"/></StgValue>
</operation>

<operation id="108" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader268:4  br i1 %icmp_ln258, label %6, label %5

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>

<operation id="109" st_id="11" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:1  %xor_ln258 = xor i5 %i3_0, -16

]]></Node>
<StgValue><ssdm name="xor_ln258"/></StgValue>
</operation>

<operation id="110" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="64" op_0_bw="5">
<![CDATA[
:2  %zext_ln258_2 = zext i5 %xor_ln258 to i64

]]></Node>
<StgValue><ssdm name="zext_ln258_2"/></StgValue>
</operation>

<operation id="111" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:3  %rhs_digits_data_V_ad_3 = getelementptr [32 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln258_2

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad_3"/></StgValue>
</operation>

<operation id="112" st_id="11" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="5">
<![CDATA[
:4  %rhs_digits_data_V_lo_3 = load i64* %rhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_3"/></StgValue>
</operation>

<operation id="113" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
:0  %z0_tmp_bits = call fastcc i4 @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs0_digits_data_V, i2 0, [16 x i64]* %rhs0_digits_data_V, [32 x i64]* %z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="z0_tmp_bits"/></StgValue>
</operation>

<operation id="114" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
:1  %z2_tmp_bits = call fastcc i4 @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs1_digits_data_V, i2 0, [16 x i64]* %rhs1_digits_data_V, [32 x i64]* %z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="z2_tmp_bits"/></StgValue>
</operation>

<operation id="115" st_id="11" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln258" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="4" op_0_bw="4" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
:2  %cross_mul_tmp_bits = call fastcc i4 @karastuba_mul_templa.1([16 x i64]* %lhs0_tmp_digits_data, [16 x i64]* %lhs1_tmp_digits_data, [16 x i64]* %rhs0_tmp_digits_data, [16 x i64]* %rhs1_tmp_digits_data, [32 x i64]* %cross_mul_digits_dat)

]]></Node>
<StgValue><ssdm name="cross_mul_tmp_bits"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="116" st_id="12" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="5">
<![CDATA[
:4  %rhs_digits_data_V_lo_3 = load i64* %rhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="117" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="64" op_0_bw="5">
<![CDATA[
:0  %zext_ln258 = zext i5 %i3_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln258"/></StgValue>
</operation>

<operation id="118" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="87" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:5  %rhs1_tmp_digits_data_2 = getelementptr [16 x i64]* %rhs1_tmp_digits_data, i64 0, i64 %zext_ln258

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data_2"/></StgValue>
</operation>

<operation id="119" st_id="13" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:6  store i64 %rhs_digits_data_V_lo_3, i64* %rhs1_tmp_digits_data_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln258"/></StgValue>
</operation>

<operation id="120" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="89" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:7  %rhs1_digits_data_V_a = getelementptr [16 x i64]* %rhs1_digits_data_V, i64 0, i64 %zext_ln258

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="121" st_id="13" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:8  store i64 %rhs_digits_data_V_lo_3, i64* %rhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln258"/></StgValue>
</operation>

<operation id="122" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="91" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %.preheader268

]]></Node>
<StgValue><ssdm name="br_ln258"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="123" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="93" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
:0  %z0_tmp_bits = call fastcc i4 @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs0_digits_data_V, i2 0, [16 x i64]* %rhs0_digits_data_V, [32 x i64]* %z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="z0_tmp_bits"/></StgValue>
</operation>

<operation id="124" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="94" bw="4" op_0_bw="4" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="64">
<![CDATA[
:1  %z2_tmp_bits = call fastcc i4 @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs1_digits_data_V, i2 0, [16 x i64]* %rhs1_digits_data_V, [32 x i64]* %z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="z2_tmp_bits"/></StgValue>
</operation>

<operation id="125" st_id="14" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="95" bw="4" op_0_bw="4" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="64">
<![CDATA[
:2  %cross_mul_tmp_bits = call fastcc i4 @karastuba_mul_templa.1([16 x i64]* %lhs0_tmp_digits_data, [16 x i64]* %lhs1_tmp_digits_data, [16 x i64]* %rhs0_tmp_digits_data, [16 x i64]* %rhs1_tmp_digits_data, [32 x i64]* %cross_mul_digits_dat)

]]></Node>
<StgValue><ssdm name="cross_mul_tmp_bits"/></StgValue>
</operation>

<operation id="126" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="5" op_0_bw="4">
<![CDATA[
:3  %zext_ln266 = zext i4 %cross_mul_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln266"/></StgValue>
</operation>

<operation id="127" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="97" bw="0" op_0_bw="0">
<![CDATA[
:4  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="128" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="99" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader.i:0  %p_088_0_i = phi i2 [ %trunc_ln, %hls_label_20 ], [ 0, %6 ]

]]></Node>
<StgValue><ssdm name="p_088_0_i"/></StgValue>
</operation>

<operation id="129" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="100" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader.i:1  %i_0_i = phi i6 [ %i_12, %hls_label_20 ], [ 0, %6 ]

]]></Node>
<StgValue><ssdm name="i_0_i"/></StgValue>
</operation>

<operation id="130" st_id="15" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="101" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader.i:2  %icmp_ln53 = icmp eq i6 %i_0_i, -32

]]></Node>
<StgValue><ssdm name="icmp_ln53"/></StgValue>
</operation>

<operation id="131" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i:3  %empty_29 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_29"/></StgValue>
</operation>

<operation id="132" st_id="15" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="103" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader.i:4  %i_12 = add i6 %i_0_i, 1

]]></Node>
<StgValue><ssdm name="i_12"/></StgValue>
</operation>

<operation id="133" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="104" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i:5  br i1 %icmp_ln53, label %"add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit", label %hls_label_20

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>

<operation id="134" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="64" op_0_bw="6">
<![CDATA[
hls_label_20:3  %zext_ln58 = zext i6 %i_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln58"/></StgValue>
</operation>

<operation id="135" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_20:4  %z0_digits_data_V_add = getelementptr [32 x i64]* %z0_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_add"/></StgValue>
</operation>

<operation id="136" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="64" op_0_bw="5">
<![CDATA[
hls_label_20:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="137" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_20:7  %z2_digits_data_V_add = getelementptr [32 x i64]* %z2_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_add"/></StgValue>
</operation>

<operation id="138" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="64" op_0_bw="5">
<![CDATA[
hls_label_20:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="139" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="64" op_0_bw="5">
<![CDATA[
hls_label_20:5  %z0_digits_data_V_loa = load i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_loa"/></StgValue>
</operation>

<operation id="140" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="64" op_0_bw="5">
<![CDATA[
hls_label_20:8  %z2_digits_data_V_loa = load i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_loa"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="141" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="65" op_0_bw="64">
<![CDATA[
hls_label_20:6  %zext_ln209 = zext i64 %z0_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln209"/></StgValue>
</operation>

<operation id="142" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="65" op_0_bw="64">
<![CDATA[
hls_label_20:9  %zext_ln700 = zext i64 %z2_digits_data_V_loa to i65

]]></Node>
<StgValue><ssdm name="zext_ln700"/></StgValue>
</operation>

<operation id="143" st_id="17" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_20:11  %add_ln700 = add i65 %zext_ln209, %zext_ln700

]]></Node>
<StgValue><ssdm name="add_ln700"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="144" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="66" op_0_bw="2">
<![CDATA[
hls_label_20:0  %zext_ln53 = zext i2 %p_088_0_i to i66

]]></Node>
<StgValue><ssdm name="zext_ln53"/></StgValue>
</operation>

<operation id="145" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="64" op_0_bw="2">
<![CDATA[
hls_label_20:10  %zext_ln700_17 = zext i2 %p_088_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_17"/></StgValue>
</operation>

<operation id="146" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="66" op_0_bw="65">
<![CDATA[
hls_label_20:12  %zext_ln700_18 = zext i65 %add_ln700 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_18"/></StgValue>
</operation>

<operation id="147" st_id="18" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_20:13  %tmp_V_6 = add i66 %zext_ln700_18, %zext_ln53

]]></Node>
<StgValue><ssdm name="tmp_V_6"/></StgValue>
</operation>

<operation id="148" st_id="18" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_20:14  %add_ln209_10 = add i64 %z2_digits_data_V_loa, %zext_ln700_17

]]></Node>
<StgValue><ssdm name="add_ln209_10"/></StgValue>
</operation>

<operation id="149" st_id="18" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="121" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_20:15  %add_ln209_5 = add i64 %add_ln209_10, %z0_digits_data_V_loa

]]></Node>
<StgValue><ssdm name="add_ln209_5"/></StgValue>
</operation>

<operation id="150" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="124" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_20:18  %trunc_ln = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V_6, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="151" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_20:1  %tmp_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str18)

]]></Node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="152" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_20:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln55"/></StgValue>
</operation>

<operation id="153" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_20:16  %add2_digits_data_V_a = getelementptr [32 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln58

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a"/></StgValue>
</operation>

<operation id="154" st_id="19" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="123" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_20:17  store i64 %add_ln209_5, i64* %add2_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln60"/></StgValue>
</operation>

<operation id="155" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="125" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_20:19  %empty_30 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str18, i32 %tmp_i)

]]></Node>
<StgValue><ssdm name="empty_30"/></StgValue>
</operation>

<operation id="156" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln53" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="126" bw="0" op_0_bw="0">
<![CDATA[
hls_label_20:20  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln53"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="157" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="6" op_0_bw="2">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:0  %zext_ln63 = zext i2 %p_088_0_i to i6

]]></Node>
<StgValue><ssdm name="zext_ln63"/></StgValue>
</operation>

<operation id="158" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="129" bw="5" op_0_bw="4">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:1  %zext_ln63_4 = zext i4 %z0_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln63_4"/></StgValue>
</operation>

<operation id="159" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="130" bw="5" op_0_bw="4">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:2  %zext_ln63_5 = zext i4 %z2_tmp_bits to i5

]]></Node>
<StgValue><ssdm name="zext_ln63_5"/></StgValue>
</operation>

<operation id="160" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="131" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:3  %add_ln63 = add i5 %zext_ln63_5, %zext_ln63_4

]]></Node>
<StgValue><ssdm name="add_ln63"/></StgValue>
</operation>

<operation id="161" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="132" bw="6" op_0_bw="5">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:4  %zext_ln63_6 = zext i5 %add_ln63 to i6

]]></Node>
<StgValue><ssdm name="zext_ln63_6"/></StgValue>
</operation>

<operation id="162" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="133" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:5  %add2_tmp_bits = add i6 %zext_ln63, %zext_ln63_6

]]></Node>
<StgValue><ssdm name="add2_tmp_bits"/></StgValue>
</operation>

<operation id="163" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="134" bw="7" op_0_bw="6">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:6  %zext_ln63_7 = zext i6 %add2_tmp_bits to i7

]]></Node>
<StgValue><ssdm name="zext_ln63_7"/></StgValue>
</operation>

<operation id="164" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="135" bw="0" op_0_bw="0">
<![CDATA[
add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:7  br label %.preheader.i2

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="165" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="137" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
<![CDATA[
.preheader.i2:0  %op2_assign = phi i1 [ %tmp_2, %hls_label_21 ], [ false, %"add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="op2_assign"/></StgValue>
</operation>

<operation id="166" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="138" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader.i2:1  %i_0_i1 = phi i6 [ %i_13, %hls_label_21 ], [ 0, %"add_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit" ]

]]></Node>
<StgValue><ssdm name="i_0_i1"/></StgValue>
</operation>

<operation id="167" st_id="21" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="139" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader.i2:2  %exitcond_i = icmp eq i6 %i_0_i1, -32

]]></Node>
<StgValue><ssdm name="exitcond_i"/></StgValue>
</operation>

<operation id="168" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="140" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i2:3  %empty_31 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_31"/></StgValue>
</operation>

<operation id="169" st_id="21" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="141" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader.i2:4  %i_13 = add i6 %i_0_i1, 1

]]></Node>
<StgValue><ssdm name="i_13"/></StgValue>
</operation>

<operation id="170" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="142" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i2:5  br i1 %exitcond_i, label %"sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit", label %hls_label_21

]]></Node>
<StgValue><ssdm name="br_ln77"/></StgValue>
</operation>

<operation id="171" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="146" bw="64" op_0_bw="6">
<![CDATA[
hls_label_21:2  %zext_ln80 = zext i6 %i_0_i1 to i64

]]></Node>
<StgValue><ssdm name="zext_ln80"/></StgValue>
</operation>

<operation id="172" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_21:3  %cross_mul_digits_dat_3 = getelementptr [32 x i64]* %cross_mul_digits_dat, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_3"/></StgValue>
</operation>

<operation id="173" st_id="21" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="64" op_0_bw="5">
<![CDATA[
hls_label_21:4  %cross_mul_digits_dat_4 = load i64* %cross_mul_digits_dat_3, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_4"/></StgValue>
</operation>

<operation id="174" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="150" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_21:6  %add2_digits_data_V_a_2 = getelementptr [32 x i64]* %add2_digits_data_V, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_a_2"/></StgValue>
</operation>

<operation id="175" st_id="21" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="5">
<![CDATA[
hls_label_21:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_2, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="176" st_id="22" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="64" op_0_bw="5">
<![CDATA[
hls_label_21:4  %cross_mul_digits_dat_4 = load i64* %cross_mul_digits_dat_3, align 8

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_4"/></StgValue>
</operation>

<operation id="177" st_id="22" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="5">
<![CDATA[
hls_label_21:7  %add2_digits_data_V_l = load i64* %add2_digits_data_V_a_2, align 8

]]></Node>
<StgValue><ssdm name="add2_digits_data_V_l"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="178" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="149" bw="65" op_0_bw="64">
<![CDATA[
hls_label_21:5  %zext_ln180 = zext i64 %cross_mul_digits_dat_4 to i65

]]></Node>
<StgValue><ssdm name="zext_ln180"/></StgValue>
</operation>

<operation id="179" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="65" op_0_bw="64">
<![CDATA[
hls_label_21:8  %zext_ln701 = zext i64 %add2_digits_data_V_l to i65

]]></Node>
<StgValue><ssdm name="zext_ln701"/></StgValue>
</operation>

<operation id="180" st_id="23" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_21:9  %tmp_V_7 = sub i65 %zext_ln180, %zext_ln701

]]></Node>
<StgValue><ssdm name="tmp_V_7"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="181" st_id="24" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="65" op_0_bw="1" op_1_bw="65" op_2_bw="65">
<![CDATA[
hls_label_21:10  %select_ln701 = select i1 %op2_assign, i65 -1, i65 0

]]></Node>
<StgValue><ssdm name="select_ln701"/></StgValue>
</operation>

<operation id="182" st_id="24" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="64" op_0_bw="1" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_21:11  %select_ln701_2 = select i1 %op2_assign, i64 -1, i64 0

]]></Node>
<StgValue><ssdm name="select_ln701_2"/></StgValue>
</operation>

<operation id="183" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="156" bw="64" op_0_bw="65">
<![CDATA[
hls_label_21:12  %trunc_ln701 = trunc i65 %tmp_V_7 to i64

]]></Node>
<StgValue><ssdm name="trunc_ln701"/></StgValue>
</operation>

<operation id="184" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_21:13  %tmp_V_8 = add i65 %select_ln701, %tmp_V_7

]]></Node>
<StgValue><ssdm name="tmp_V_8"/></StgValue>
</operation>

<operation id="185" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="1" op_0_bw="1" op_1_bw="65" op_2_bw="32">
<![CDATA[
hls_label_21:14  %tmp_2 = call i1 @_ssdm_op_BitSelect.i1.i65.i32(i65 %tmp_V_8, i32 64)

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>

<operation id="186" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_21:15  %add_ln700_13 = add i64 %trunc_ln701, %select_ln701_2

]]></Node>
<StgValue><ssdm name="add_ln700_13"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="187" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="144" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_21:0  %tmp_i3 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str23)

]]></Node>
<StgValue><ssdm name="tmp_i3"/></StgValue>
</operation>

<operation id="188" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="145" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_21:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln79"/></StgValue>
</operation>

<operation id="189" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_21:16  %z1_digits_data_V_add = getelementptr [32 x i64]* %z1_digits_data_V, i64 0, i64 %zext_ln80

]]></Node>
<StgValue><ssdm name="z1_digits_data_V_add"/></StgValue>
</operation>

<operation id="190" st_id="25" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="161" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_21:17  store i64 %add_ln700_13, i64* %z1_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln88"/></StgValue>
</operation>

<operation id="191" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="162" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_21:18  %empty_32 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str23, i32 %tmp_i3)

]]></Node>
<StgValue><ssdm name="empty_32"/></StgValue>
</operation>

<operation id="192" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="exitcond_i" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="163" bw="0" op_0_bw="0">
<![CDATA[
hls_label_21:19  br label %.preheader.i2

]]></Node>
<StgValue><ssdm name="br_ln77"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="193" st_id="26" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="165" bw="5" op_0_bw="1" op_1_bw="5" op_2_bw="5">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:0  %empty_33 = select i1 %op2_assign, i5 -1, i5 0

]]></Node>
<StgValue><ssdm name="empty_33"/></StgValue>
</operation>

<operation id="194" st_id="26" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="166" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:1  %add_ln95 = add i5 %empty_33, %zext_ln266

]]></Node>
<StgValue><ssdm name="add_ln95"/></StgValue>
</operation>

<operation id="195" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="167" bw="7" op_0_bw="5">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:2  %sext_ln95 = sext i5 %add_ln95 to i7

]]></Node>
<StgValue><ssdm name="sext_ln95"/></StgValue>
</operation>

<operation id="196" st_id="26" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="168" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:3  %z1_tmp_bits = sub i7 %sext_ln95, %zext_ln63_7

]]></Node>
<StgValue><ssdm name="z1_tmp_bits"/></StgValue>
</operation>

<operation id="197" st_id="26" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="169" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="7" op_3_bw="64" op_4_bw="64" op_5_bw="64" op_6_bw="4" op_7_bw="4">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:4  call fastcc void @CAT_I_I_I_O.1([32 x i64]* %z0_digits_data_V, i7 %z1_tmp_bits, [32 x i64]* %z1_digits_data_V, [32 x i64]* %z2_digits_data_V, [64 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln275"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="198" st_id="27" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="169" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="7" op_3_bw="64" op_4_bw="64" op_5_bw="64" op_6_bw="4" op_7_bw="4">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:4  call fastcc void @CAT_I_I_I_O.1([32 x i64]* %z0_digits_data_V, i7 %z1_tmp_bits, [32 x i64]* %z1_digits_data_V, [32 x i64]* %z2_digits_data_V, [64 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln275"/></StgValue>
</operation>

<operation id="199" st_id="27" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="170" bw="1" op_0_bw="2" op_1_bw="2">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:5  %icmp_ln278 = icmp eq i2 %rhs_tmp_bits_read_2, 0

]]></Node>
<StgValue><ssdm name="icmp_ln278"/></StgValue>
</operation>

<operation id="200" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="171" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit:6  br i1 %icmp_ln278, label %._crit_edge, label %.preheader267.preheader

]]></Node>
<StgValue><ssdm name="br_ln278"/></StgValue>
</operation>

<operation id="201" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln278" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="173" bw="0" op_0_bw="0">
<![CDATA[
.preheader267.preheader:0  br label %.preheader267

]]></Node>
<StgValue><ssdm name="br_ln282"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="202" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="175" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader267:0  %p_084_0 = phi i2 [ %trunc_ln858_6, %hls_label_8 ], [ 0, %.preheader267.preheader ]

]]></Node>
<StgValue><ssdm name="p_084_0"/></StgValue>
</operation>

<operation id="203" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="176" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader267:1  %i4_0 = phi i6 [ %i_14, %hls_label_8 ], [ 0, %.preheader267.preheader ]

]]></Node>
<StgValue><ssdm name="i4_0"/></StgValue>
</operation>

<operation id="204" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="177" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader267:2  %j_0 = phi i7 [ %j, %hls_label_8 ], [ 32, %.preheader267.preheader ]

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="205" st_id="28" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="178" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader267:3  %icmp_ln282 = icmp eq i6 %i4_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln282"/></StgValue>
</operation>

<operation id="206" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="179" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader267:4  %empty_34 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_34"/></StgValue>
</operation>

<operation id="207" st_id="28" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="180" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader267:5  %i_14 = add i6 %i4_0, 1

]]></Node>
<StgValue><ssdm name="i_14"/></StgValue>
</operation>

<operation id="208" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="181" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader267:6  br i1 %icmp_ln282, label %._crit_edge.loopexit, label %hls_label_8

]]></Node>
<StgValue><ssdm name="br_ln282"/></StgValue>
</operation>

<operation id="209" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="186" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:3  %zext_ln285 = zext i6 %i4_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln285"/></StgValue>
</operation>

<operation id="210" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="187" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:4  %lhs_digits_data_V_ad_4 = getelementptr [32 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln285

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad_4"/></StgValue>
</operation>

<operation id="211" st_id="28" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="188" bw="64" op_0_bw="5">
<![CDATA[
hls_label_8:5  %lhs_digits_data_V_lo_4 = load i64* %lhs_digits_data_V_ad_4, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_4"/></StgValue>
</operation>

<operation id="212" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="64" op_0_bw="7">
<![CDATA[
hls_label_8:7  %zext_ln286 = zext i7 %j_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln286"/></StgValue>
</operation>

<operation id="213" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="191" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:8  %res_digits_data_V_ad = getelementptr [64 x i64]* %res_digits_data_V, i64 0, i64 %zext_ln286

]]></Node>
<StgValue><ssdm name="res_digits_data_V_ad"/></StgValue>
</operation>

<operation id="214" st_id="28" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="192" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:9  %res_digits_data_V_lo = load i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo"/></StgValue>
</operation>

<operation id="215" st_id="28" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="203" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
hls_label_8:20  %j = add i7 %j_0, 1

]]></Node>
<StgValue><ssdm name="j"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="216" st_id="29" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="188" bw="64" op_0_bw="5">
<![CDATA[
hls_label_8:5  %lhs_digits_data_V_lo_4 = load i64* %lhs_digits_data_V_ad_4, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_4"/></StgValue>
</operation>

<operation id="217" st_id="29" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="192" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:9  %res_digits_data_V_lo = load i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="218" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="65" op_0_bw="64">
<![CDATA[
hls_label_8:6  %zext_ln286_1 = zext i64 %lhs_digits_data_V_lo_4 to i65

]]></Node>
<StgValue><ssdm name="zext_ln286_1"/></StgValue>
</operation>

<operation id="219" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="193" bw="65" op_0_bw="64">
<![CDATA[
hls_label_8:10  %zext_ln700_19 = zext i64 %res_digits_data_V_lo to i65

]]></Node>
<StgValue><ssdm name="zext_ln700_19"/></StgValue>
</operation>

<operation id="220" st_id="30" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_8:12  %add_ln700_14 = add i65 %zext_ln286_1, %zext_ln700_19

]]></Node>
<StgValue><ssdm name="add_ln700_14"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="221" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="66" op_0_bw="2">
<![CDATA[
hls_label_8:0  %zext_ln282 = zext i2 %p_084_0 to i66

]]></Node>
<StgValue><ssdm name="zext_ln282"/></StgValue>
</operation>

<operation id="222" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="194" bw="64" op_0_bw="2">
<![CDATA[
hls_label_8:11  %zext_ln700_20 = zext i2 %p_084_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_20"/></StgValue>
</operation>

<operation id="223" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="66" op_0_bw="65">
<![CDATA[
hls_label_8:13  %zext_ln700_21 = zext i65 %add_ln700_14 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_21"/></StgValue>
</operation>

<operation id="224" st_id="31" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="197" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_8:14  %tmp_V = add i66 %zext_ln700_21, %zext_ln282

]]></Node>
<StgValue><ssdm name="tmp_V"/></StgValue>
</operation>

<operation id="225" st_id="31" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="198" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_8:15  %add_ln209_11 = add i64 %res_digits_data_V_lo, %zext_ln700_20

]]></Node>
<StgValue><ssdm name="add_ln209_11"/></StgValue>
</operation>

<operation id="226" st_id="31" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="199" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_8:16  %add_ln209 = add i64 %add_ln209_11, %lhs_digits_data_V_lo_4

]]></Node>
<StgValue><ssdm name="add_ln209"/></StgValue>
</operation>

<operation id="227" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="201" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_8:18  %trunc_ln858_6 = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln858_6"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">

<operation id="228" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_8:1  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str19)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="229" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="185" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_8:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln284"/></StgValue>
</operation>

<operation id="230" st_id="32" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="200" bw="0" op_0_bw="64" op_1_bw="6" op_2_bw="64">
<![CDATA[
hls_label_8:17  store i64 %add_ln209, i64* %res_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="store_ln287"/></StgValue>
</operation>

<operation id="231" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="202" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_8:19  %empty_35 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str19, i32 %tmp)

]]></Node>
<StgValue><ssdm name="empty_35"/></StgValue>
</operation>

<operation id="232" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln282" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="204" bw="0" op_0_bw="0">
<![CDATA[
hls_label_8:21  br label %.preheader267

]]></Node>
<StgValue><ssdm name="br_ln282"/></StgValue>
</operation>
</state>

<state id="33" st_id="33">

<operation id="233" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln278" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="206" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit:0  br label %._crit_edge

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>

<operation id="234" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="208" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
._crit_edge:0  %res_tmp_bits_0 = phi i2 [ 0, %"sub_I_O<Bignum<32, 64>, Bignum<32, 64> >.exit" ], [ %p_084_0, %._crit_edge.loopexit ]

]]></Node>
<StgValue><ssdm name="res_tmp_bits_0"/></StgValue>
</operation>

<operation id="235" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="209" bw="3" op_0_bw="2">
<![CDATA[
._crit_edge:1  %zext_ln292 = zext i2 %res_tmp_bits_0 to i3

]]></Node>
<StgValue><ssdm name="zext_ln292"/></StgValue>
</operation>

<operation id="236" st_id="33" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="210" bw="1" op_0_bw="2" op_1_bw="2">
<![CDATA[
._crit_edge:2  %icmp_ln292 = icmp eq i2 %lhs_tmp_bits_read_2, 0

]]></Node>
<StgValue><ssdm name="icmp_ln292"/></StgValue>
</operation>

<operation id="237" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="211" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge:3  br i1 %icmp_ln292, label %._crit_edge271, label %.preheader.preheader

]]></Node>
<StgValue><ssdm name="br_ln292"/></StgValue>
</operation>

<operation id="238" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln292" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="213" bw="0" op_0_bw="0">
<![CDATA[
.preheader.preheader:0  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln296"/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="239" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="215" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.preheader:0  %p_0160_0 = phi i2 [ %trunc_ln858_7, %hls_label_9 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="p_0160_0"/></StgValue>
</operation>

<operation id="240" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="216" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader:1  %i7_0 = phi i6 [ %i_15, %hls_label_9 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="i7_0"/></StgValue>
</operation>

<operation id="241" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="217" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
.preheader:2  %j8_0 = phi i7 [ %j_5, %hls_label_9 ], [ 32, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="j8_0"/></StgValue>
</operation>

<operation id="242" st_id="34" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="218" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:3  %icmp_ln296 = icmp eq i6 %i7_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln296"/></StgValue>
</operation>

<operation id="243" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="219" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:4  %empty_36 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_36"/></StgValue>
</operation>

<operation id="244" st_id="34" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="220" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:5  %i_15 = add i6 %i7_0, 1

]]></Node>
<StgValue><ssdm name="i_15"/></StgValue>
</operation>

<operation id="245" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="221" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:6  br i1 %icmp_ln296, label %7, label %hls_label_9

]]></Node>
<StgValue><ssdm name="br_ln296"/></StgValue>
</operation>

<operation id="246" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="226" bw="64" op_0_bw="6">
<![CDATA[
hls_label_9:3  %zext_ln299 = zext i6 %i7_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln299"/></StgValue>
</operation>

<operation id="247" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="227" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_9:4  %rhs_digits_data_V_ad_4 = getelementptr [32 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln299

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad_4"/></StgValue>
</operation>

<operation id="248" st_id="34" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="228" bw="64" op_0_bw="5">
<![CDATA[
hls_label_9:5  %rhs_digits_data_V_lo_4 = load i64* %rhs_digits_data_V_ad_4, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_4"/></StgValue>
</operation>

<operation id="249" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="64" op_0_bw="7">
<![CDATA[
hls_label_9:7  %zext_ln300 = zext i7 %j8_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln300"/></StgValue>
</operation>

<operation id="250" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="231" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_9:8  %res_digits_data_V_ad_2 = getelementptr [64 x i64]* %res_digits_data_V, i64 0, i64 %zext_ln300

]]></Node>
<StgValue><ssdm name="res_digits_data_V_ad_2"/></StgValue>
</operation>

<operation id="251" st_id="34" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="232" bw="64" op_0_bw="6">
<![CDATA[
hls_label_9:9  %res_digits_data_V_lo_2 = load i64* %res_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo_2"/></StgValue>
</operation>

<operation id="252" st_id="34" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="243" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
hls_label_9:20  %j_5 = add i7 %j8_0, 1

]]></Node>
<StgValue><ssdm name="j_5"/></StgValue>
</operation>
</state>

<state id="35" st_id="35">

<operation id="253" st_id="35" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="228" bw="64" op_0_bw="5">
<![CDATA[
hls_label_9:5  %rhs_digits_data_V_lo_4 = load i64* %rhs_digits_data_V_ad_4, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_4"/></StgValue>
</operation>

<operation id="254" st_id="35" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="232" bw="64" op_0_bw="6">
<![CDATA[
hls_label_9:9  %res_digits_data_V_lo_2 = load i64* %res_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V_lo_2"/></StgValue>
</operation>
</state>

<state id="36" st_id="36">

<operation id="255" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="65" op_0_bw="64">
<![CDATA[
hls_label_9:6  %zext_ln300_1 = zext i64 %rhs_digits_data_V_lo_4 to i65

]]></Node>
<StgValue><ssdm name="zext_ln300_1"/></StgValue>
</operation>

<operation id="256" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="233" bw="65" op_0_bw="64">
<![CDATA[
hls_label_9:10  %zext_ln700_22 = zext i64 %res_digits_data_V_lo_2 to i65

]]></Node>
<StgValue><ssdm name="zext_ln700_22"/></StgValue>
</operation>

<operation id="257" st_id="36" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="235" bw="65" op_0_bw="65" op_1_bw="65">
<![CDATA[
hls_label_9:12  %add_ln700_16 = add i65 %zext_ln300_1, %zext_ln700_22

]]></Node>
<StgValue><ssdm name="add_ln700_16"/></StgValue>
</operation>
</state>

<state id="37" st_id="37">

<operation id="258" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="223" bw="66" op_0_bw="2">
<![CDATA[
hls_label_9:0  %zext_ln296 = zext i2 %p_0160_0 to i66

]]></Node>
<StgValue><ssdm name="zext_ln296"/></StgValue>
</operation>

<operation id="259" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="234" bw="64" op_0_bw="2">
<![CDATA[
hls_label_9:11  %zext_ln700_23 = zext i2 %p_0160_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln700_23"/></StgValue>
</operation>

<operation id="260" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="66" op_0_bw="65">
<![CDATA[
hls_label_9:13  %zext_ln700_24 = zext i65 %add_ln700_16 to i66

]]></Node>
<StgValue><ssdm name="zext_ln700_24"/></StgValue>
</operation>

<operation id="261" st_id="37" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="237" bw="66" op_0_bw="66" op_1_bw="66">
<![CDATA[
hls_label_9:14  %tmp_V_9 = add i66 %zext_ln700_24, %zext_ln296

]]></Node>
<StgValue><ssdm name="tmp_V_9"/></StgValue>
</operation>

<operation id="262" st_id="37" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="238" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_9:15  %add_ln209_12 = add i64 %res_digits_data_V_lo_2, %zext_ln700_23

]]></Node>
<StgValue><ssdm name="add_ln209_12"/></StgValue>
</operation>

<operation id="263" st_id="37" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="239" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
hls_label_9:16  %add_ln209_4 = add i64 %add_ln209_12, %rhs_digits_data_V_lo_4

]]></Node>
<StgValue><ssdm name="add_ln209_4"/></StgValue>
</operation>

<operation id="264" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="2" op_0_bw="2" op_1_bw="66" op_2_bw="32" op_3_bw="32">
<![CDATA[
hls_label_9:18  %trunc_ln858_7 = call i2 @_ssdm_op_PartSelect.i2.i66.i32.i32(i66 %tmp_V_9, i32 64, i32 65)

]]></Node>
<StgValue><ssdm name="trunc_ln858_7"/></StgValue>
</operation>
</state>

<state id="38" st_id="38">

<operation id="265" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="224" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_9:1  %tmp_3 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str20)

]]></Node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="266" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="225" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_9:2  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln298"/></StgValue>
</operation>

<operation id="267" st_id="38" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="240" bw="0" op_0_bw="64" op_1_bw="6" op_2_bw="64">
<![CDATA[
hls_label_9:17  store i64 %add_ln209_4, i64* %res_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln301"/></StgValue>
</operation>

<operation id="268" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_9:19  %empty_37 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str20, i32 %tmp_3)

]]></Node>
<StgValue><ssdm name="empty_37"/></StgValue>
</operation>

<operation id="269" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln296" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="244" bw="0" op_0_bw="0">
<![CDATA[
hls_label_9:21  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln296"/></StgValue>
</operation>
</state>

<state id="39" st_id="39">

<operation id="270" st_id="39" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="246" bw="3" op_0_bw="2">
<![CDATA[
:0  %zext_ln304 = zext i2 %p_0160_0 to i3

]]></Node>
<StgValue><ssdm name="zext_ln304"/></StgValue>
</operation>

<operation id="271" st_id="39" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="247" bw="3" op_0_bw="3" op_1_bw="3">
<![CDATA[
:1  %add_ln304 = add i3 %zext_ln292, %zext_ln304

]]></Node>
<StgValue><ssdm name="add_ln304"/></StgValue>
</operation>

<operation id="272" st_id="39" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="248" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %._crit_edge271

]]></Node>
<StgValue><ssdm name="br_ln305"/></StgValue>
</operation>
</state>

<state id="40" st_id="40">

<operation id="273" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="250" bw="3" op_0_bw="3" op_1_bw="0" op_2_bw="3" op_3_bw="0">
<![CDATA[
._crit_edge271:0  %res_tmp_bits_1 = phi i3 [ %zext_ln292, %._crit_edge ], [ %add_ln304, %7 ]

]]></Node>
<StgValue><ssdm name="res_tmp_bits_1"/></StgValue>
</operation>

<operation id="274" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="251" bw="4" op_0_bw="3">
<![CDATA[
._crit_edge271:1  %zext_ln306 = zext i3 %res_tmp_bits_1 to i4

]]></Node>
<StgValue><ssdm name="zext_ln306"/></StgValue>
</operation>

<operation id="275" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="252" bw="4" op_0_bw="2">
<![CDATA[
._crit_edge271:2  %zext_ln306_3 = zext i2 %rhs_tmp_bits_read_2 to i4

]]></Node>
<StgValue><ssdm name="zext_ln306_3"/></StgValue>
</operation>

<operation id="276" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="253" bw="4" op_0_bw="2">
<![CDATA[
._crit_edge271:3  %zext_ln306_4 = zext i2 %lhs_tmp_bits_read_2 to i4

]]></Node>
<StgValue><ssdm name="zext_ln306_4"/></StgValue>
</operation>

<operation id="277" st_id="40" stage="1" lat="1">
<core>Mul</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="254" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
._crit_edge271:4  %mul_ln306 = mul i4 %zext_ln306_3, %zext_ln306_4

]]></Node>
<StgValue><ssdm name="mul_ln306"/></StgValue>
</operation>

<operation id="278" st_id="40" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="255" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
._crit_edge271:5  %add_ln306 = add i4 %zext_ln306, %mul_ln306

]]></Node>
<StgValue><ssdm name="add_ln306"/></StgValue>
</operation>

<operation id="279" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="256" bw="0" op_0_bw="4">
<![CDATA[
._crit_edge271:6  ret i4 %add_ln306

]]></Node>
<StgValue><ssdm name="ret_ln308"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
