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<item  id="141" filename="multest.cc" linenumber="149" name="zext_ln700_7" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_7_fu_595_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="142" filename="multest.cc" linenumber="150" name="add_ln700_4" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln700_4_fu_585_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="143" filename="multest.cc" linenumber="150" name="zext_ln700_8" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln700_8_fu_599_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="144" filename="multest.cc" linenumber="150" name="tmp_V_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="tmp_V_1_fu_602_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="145" filename="multest.cc" linenumber="151" name="add_ln209_5" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_5_fu_608_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="146" filename="multest.cc" linenumber="151" name="add_ln209_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln209_3_fu_614_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="152" name="trunc_ln858_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="trunc_ln858_2_reg_857" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="150" filename="multest.cc" linenumber="146" name="j_3" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="j_3_fu_566_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="153" filename="multest.cc" linenumber="154" name="zext_ln154" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln154_fu_630_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="154" filename="multest.cc" linenumber="154" name="add_ln154" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln154_fu_634_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="158" filename="multest.cc" linenumber="156" name="zext_ln156" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="zext_ln156_fu_639_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="159" filename="multest.cc" linenumber="156" name="zext_ln156_1" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln156_fu_649_p00" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="160" filename="multest.cc" linenumber="156" name="zext_ln156_2" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln156_fu_649_p10" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="161" filename="multest.cc" linenumber="156" name="mul_ln156" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="mul_ln156_fu_649_p2" latency="0" BRAM="-1" DSP="0" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="162" filename="multest.cc" linenumber="156" name="add_ln156" contextFuncName="mul_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="mul_I_O" rtlName="add_ln156_fu_655_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="232" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;16, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="233" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;16, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="icmp_ln53_fu_192_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="53" name="i" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="i_fu_198_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln53_fu_224_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln58_fu_204_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln209_fu_210_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_fu_214_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="58" name="zext_ln700_19" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_19_fu_228_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln700_fu_218_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="zext_ln700_20" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_20_fu_232_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="59" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="tmp_V_fu_235_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="60" name="add_ln209_12" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln209_12_fu_241_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="60" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add0_digits_data_V_d0" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="p_088_0_i_reg_134" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="53" name="icmp_ln53_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="icmp_ln53_1_fu_262_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="53" name="i_21" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="i_21_fu_268_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="53" name="zext_ln53_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln53_1_fu_294_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="58" name="zext_ln58_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln58_1_fu_274_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="59" name="zext_ln209_1" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln209_1_fu_280_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="58" name="zext_ln700_21" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_21_fu_284_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="58" name="zext_ln700_22" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_22_fu_298_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="add_ln700_13" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln700_13_fu_288_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="zext_ln700_23" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="zext_ln700_23_fu_302_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="59" name="tmp_V_12" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="tmp_V_12_fu_305_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="60" name="add_ln209_13" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add_ln209_13_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="60" name="add_ln209_4" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="add1_digits_data_V_d0" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="61" name="trunc_ln858_5" contextFuncName="add_I_O&lt;Bignum&lt;8, 64&gt;, Bignum&lt;8, 64&gt; &gt;" moduleName="karastuba_mul_templa.2" rtlName="p_088_0_i1_reg_157" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="219" name="res_tmp_bits_write_a" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_templa.2" rtlName="grp_mul_I_O_fu_180" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="162" name="sext_ln162" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="sext_ln162_fu_251_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="167" name="icmp_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln167_fu_255_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="167" name="zext_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln167_fu_261_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="167" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_fu_266_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="169" name="icmp_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln169_fu_272_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="169" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_fu_278_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="169" name="zext_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln169_fu_284_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="174" name="icmp_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln174_fu_289_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="174" name="i_26" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_26_fu_295_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="174" name="zext_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln174_fu_330_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="179" name="zext_ln179" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln179_fu_301_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="180" name="zext_ln180_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln180_1_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln180_fu_306_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="179" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_fu_320_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="179" name="zext_ln700_26" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_26_fu_334_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="add_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln700_fu_324_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="180" name="zext_ln700_27" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_27_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="180" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_fu_341_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="181" name="add_ln209_14" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_14_fu_347_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="181" name="add_ln209_10" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_10_fu_353_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="182" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="trunc_ln_reg_547" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="183" name="j_6" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_6_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="185" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln1468_fu_368_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="185" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln209_fu_372_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="185" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_fu_375_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="185" name="zext_ln209_3" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln209_3_fu_381_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="185" name="add_ln209_3" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_3_fu_384_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="82" filename="multest.cc" linenumber="190" name="icmp_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="icmp_ln190_fu_390_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="190" name="i_27" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="i_27_fu_396_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="190" name="zext_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln190_fu_431_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="90" filename="multest.cc" linenumber="195" name="zext_ln195" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln195_fu_402_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="196" name="zext_ln196_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln196_1_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="94" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln196_fu_407_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="195" name="zext_ln700_28" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_28_fu_421_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="195" name="zext_ln700_29" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_29_fu_435_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="add_ln700_26" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln700_26_fu_425_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="196" name="zext_ln700_30" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="zext_ln700_30_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="196" name="tmp_V_15" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="tmp_V_15_fu_442_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="197" name="add_ln209_15" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_15_fu_448_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="197" name="add_ln209_11" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="add_ln209_11_fu_454_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="198" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="trunc_ln858_s_reg_608" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="199" name="j_7" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="CAT_I_I_I_O.2" rtlName="j_7_fu_412_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="253" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="253" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="253" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="253" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="253" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="253" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="253" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="253" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="261" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="263" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="270" name="add2_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="272" name="z1_digits_data_V" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="255" name="icmp_ln255" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="icmp_ln255_fu_630_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="255" name="i" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="i_fu_636_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="255" name="zext_ln255" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln255_fu_642_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="256" name="icmp_ln256" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="icmp_ln256_fu_647_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="256" name="i_2" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="i_2_fu_653_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="256" name="zext_ln256" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln256_fu_670_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="47" filename="multest.cc" linenumber="256" name="xor_ln256" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="xor_ln256_fu_659_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="5" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="256" name="zext_ln256_1" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln256_1_fu_665_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="257" name="icmp_ln257" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="icmp_ln257_fu_676_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="257" name="i_3" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="i_3_fu_682_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="257" name="zext_ln257" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln257_fu_688_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="258" name="icmp_ln258" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="icmp_ln258_fu_693_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="258" name="i_4" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="i_4_fu_699_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="82" filename="multest.cc" linenumber="258" name="zext_ln258" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln258_fu_716_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="83" filename="multest.cc" linenumber="258" name="xor_ln258" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="xor_ln258_fu_705_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="5" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="258" name="zext_ln258_1" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln258_1_fu_711_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="219" name="res_tmp_bits_write_a" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="grp_mul_I_O_fu_594" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="94" filename="multest.cc" linenumber="219" name="res_tmp_bits_write_a_1" contextFuncName="karastuba_mul_template&lt;8, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="grp_mul_I_O_fu_605" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="95" filename="multest.cc" linenumber="266" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="grp_karastuba_mul_templa_2_fu_585" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="266" name="zext_ln266" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln266_fu_722_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="icmp_ln53_fu_726_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="53" name="i_5" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="i_5_fu_732_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln53_fu_756_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="109" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln58_fu_738_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="112" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln209_fu_744_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="115" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln700_fu_747_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="58" name="zext_ln700_9" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln700_9_fu_760_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln700_fu_750_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="59" name="zext_ln700_10" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln700_10_fu_764_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="119" filename="multest.cc" linenumber="59" name="tmp_V_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="tmp_V_2_fu_767_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="60" name="add_ln209_7" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln209_7_fu_773_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="121" filename="multest.cc" linenumber="60" name="add_ln209_6" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln209_6_fu_778_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="124" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="trunc_ln_reg_1254" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="128" filename="multest.cc" linenumber="63" name="zext_ln63" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln63_fu_793_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
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<item  id="235" filename="multest.cc" linenumber="300" name="add_ln700_10" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln700_10_fu_1042_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="236" filename="multest.cc" linenumber="300" name="zext_ln700_16" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln700_16_fu_1056_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="237" filename="multest.cc" linenumber="300" name="tmp_V_5" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="tmp_V_5_fu_1059_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="238" filename="multest.cc" linenumber="301" name="add_ln209_9" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln209_9_fu_1065_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="239" filename="multest.cc" linenumber="301" name="add_ln209_5" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln209_5_fu_1071_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="241" filename="multest.cc" linenumber="302" name="trunc_ln858_9" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="trunc_ln858_9_reg_1420" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="243" filename="multest.cc" linenumber="296" name="j_4" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="j_4_fu_1029_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="246" filename="multest.cc" linenumber="304" name="zext_ln304" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln304_fu_1086_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="247" filename="multest.cc" linenumber="304" name="add_ln304" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln304_fu_1090_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="251" filename="multest.cc" linenumber="306" name="zext_ln306" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="zext_ln306_fu_1095_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="252" filename="multest.cc" linenumber="306" name="zext_ln306_1" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="mul_ln306_fu_1105_p00" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="253" filename="multest.cc" linenumber="306" name="zext_ln306_2" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="mul_ln306_fu_1105_p10" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="254" filename="multest.cc" linenumber="306" name="mul_ln306" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="mul_ln306_fu_1105_p2" latency="0" BRAM="-1" DSP="0" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="255" filename="multest.cc" linenumber="306" name="add_ln306" contextFuncName="karastuba_mul_template&lt;16, 64&gt;" moduleName="karastuba_mul_templa.5" rtlName="add_ln306_fu_1111_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="232" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="233" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="icmp_ln53_fu_192_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="53" name="i" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="i_fu_198_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln53_fu_222_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln58_fu_204_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln209_fu_210_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_fu_213_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="58" name="zext_ln700_14" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_14_fu_226_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln700_fu_216_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="zext_ln700_15" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_15_fu_230_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="59" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="tmp_V_fu_233_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="60" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_fu_239_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="60" name="add_ln209_9" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_9_fu_244_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="trunc_ln_reg_372" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="53" name="icmp_ln53_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="icmp_ln53_2_fu_259_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="53" name="i_22" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="i_22_fu_265_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="53" name="zext_ln53_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln53_2_fu_289_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="58" name="zext_ln58_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln58_2_fu_271_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="59" name="zext_ln209_2" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln209_2_fu_277_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="58" name="zext_ln700_16" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_16_fu_280_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="58" name="zext_ln700_17" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_17_fu_293_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="add_ln700_10" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln700_10_fu_283_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="zext_ln700_18" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="zext_ln700_18_fu_297_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="59" name="tmp_V_13" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="tmp_V_13_fu_300_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="60" name="add_ln209_10" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_10_fu_306_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="60" name="add_ln209_11" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="add_ln209_11_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="61" name="trunc_ln858_4" contextFuncName="add_I_O&lt;Bignum&lt;16, 64&gt;, Bignum&lt;16, 64&gt; &gt;" moduleName="karastuba_mul_templa.1" rtlName="trunc_ln858_4_reg_423" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="240" name="cross_mul_tmp_bits_w" contextFuncName="karastuba_mul_template_z1&lt;32, 64&gt;" moduleName="karastuba_mul_templa.1" rtlName="grp_karastuba_mul_templa_5_fu_180" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="162" name="sext_ln162" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="sext_ln162_fu_251_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="167" name="icmp_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln167_fu_255_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="167" name="zext_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln167_fu_261_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="167" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_fu_266_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="169" name="icmp_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln169_fu_272_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="169" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_fu_278_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="169" name="zext_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln169_fu_284_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="174" name="icmp_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln174_fu_289_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="174" name="i_28" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_28_fu_295_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="174" name="zext_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln174_fu_330_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="179" name="zext_ln179" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln179_fu_301_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="180" name="zext_ln180_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln180_2_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln180_fu_306_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="179" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_fu_320_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="179" name="zext_ln700_31" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_31_fu_334_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="add_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln700_fu_324_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="180" name="zext_ln700_32" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_32_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="180" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_fu_341_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="181" name="add_ln209_16" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_16_fu_347_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="181" name="add_ln209_8" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_8_fu_353_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="182" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="trunc_ln_reg_547" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="183" name="j_8" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_8_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="185" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln1468_fu_368_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="185" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln209_fu_372_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="185" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_fu_375_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="185" name="zext_ln209_4" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln209_4_fu_381_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="185" name="add_ln209_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_2_fu_384_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="82" filename="multest.cc" linenumber="190" name="icmp_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="icmp_ln190_fu_390_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="190" name="i_29" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="i_29_fu_396_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="190" name="zext_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln190_fu_431_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="90" filename="multest.cc" linenumber="195" name="zext_ln195" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln195_fu_402_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="196" name="zext_ln196_2" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln196_2_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="94" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln196_fu_407_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="195" name="zext_ln700_33" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_33_fu_421_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="195" name="zext_ln700_34" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_34_fu_435_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="add_ln700_29" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln700_29_fu_425_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="196" name="zext_ln700_35" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="zext_ln700_35_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="196" name="tmp_V_16" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="tmp_V_16_fu_442_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="197" name="add_ln209_17" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_17_fu_448_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="197" name="add_ln209_9" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="add_ln209_9_fu_454_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="198" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="trunc_ln858_s_reg_608" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="199" name="j_9" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="CAT_I_I_I_O.1" rtlName="j_9_fu_412_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="253" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="253" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="253" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="253" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="253" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="253" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="253" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="253" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="261" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="263" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="19" filename="multest.cc" linenumber="270" name="add2_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="272" name="z1_digits_data_V" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="255" name="icmp_ln255" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="icmp_ln255_fu_638_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="255" name="i" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="i_fu_644_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="255" name="zext_ln255" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln255_fu_650_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="256" name="icmp_ln256" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="icmp_ln256_fu_655_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="256" name="i_9" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="i_9_fu_661_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="256" name="zext_ln256" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln256_fu_678_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="47" filename="multest.cc" linenumber="256" name="xor_ln256" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="xor_ln256_fu_667_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="6" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="256" name="zext_ln256_2" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln256_2_fu_673_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="257" name="icmp_ln257" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="icmp_ln257_fu_684_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="257" name="i_10" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="i_10_fu_690_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="257" name="zext_ln257" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln257_fu_696_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="77" filename="multest.cc" linenumber="258" name="icmp_ln258" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="icmp_ln258_fu_701_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="258" name="i_11" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="i_11_fu_707_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="82" filename="multest.cc" linenumber="258" name="zext_ln258" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln258_fu_724_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="83" filename="multest.cc" linenumber="258" name="xor_ln258" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="xor_ln258_fu_713_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="6" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="258" name="zext_ln258_2" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln258_2_fu_719_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="262" name="z0_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="grp_karastuba_mul_templa_5_fu_586" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="94" filename="multest.cc" linenumber="264" name="z2_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="grp_karastuba_mul_templa_5_fu_597" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="95" filename="multest.cc" linenumber="266" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="grp_karastuba_mul_templa_1_fu_577" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="96" filename="multest.cc" linenumber="266" name="zext_ln266" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln266_fu_730_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="icmp_ln53_fu_734_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="53" name="i_12" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="i_12_fu_740_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln53_fu_764_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="109" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln58_fu_746_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="112" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln209_fu_752_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="115" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln700_fu_755_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="58" name="zext_ln700_17" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln700_17_fu_768_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln700_fu_758_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="118" filename="multest.cc" linenumber="59" name="zext_ln700_18" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln700_18_fu_772_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="119" filename="multest.cc" linenumber="59" name="tmp_V_6" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="tmp_V_6_fu_775_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="60" name="add_ln209_10" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln209_10_fu_781_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="121" filename="multest.cc" linenumber="60" name="add_ln209_5" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln209_5_fu_786_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="124" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="trunc_ln_reg_1266" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="128" filename="multest.cc" linenumber="63" name="zext_ln63" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln63_fu_801_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="129" filename="multest.cc" linenumber="63" name="zext_ln63_4" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln63_4_fu_805_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="130" filename="multest.cc" linenumber="63" name="zext_ln63_5" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln63_5_fu_808_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="131" filename="multest.cc" linenumber="63" name="add_ln63" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln63_fu_811_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="132" filename="multest.cc" linenumber="63" name="zext_ln63_6" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln63_6_fu_817_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="133" filename="multest.cc" linenumber="63" name="add2_tmp_bits" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa.4" rtlName="add2_tmp_bits_fu_821_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
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<item  id="243" filename="multest.cc" linenumber="296" name="j_5" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="j_5_fu_1039_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="246" filename="multest.cc" linenumber="304" name="zext_ln304" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln304_fu_1098_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="247" filename="multest.cc" linenumber="304" name="add_ln304" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln304_fu_1102_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="251" filename="multest.cc" linenumber="306" name="zext_ln306" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="zext_ln306_fu_1107_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="252" filename="multest.cc" linenumber="306" name="zext_ln306_3" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="mul_ln306_fu_1117_p00" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="253" filename="multest.cc" linenumber="306" name="zext_ln306_4" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="mul_ln306_fu_1117_p10" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="254" filename="multest.cc" linenumber="306" name="mul_ln306" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="mul_ln306_fu_1117_p2" latency="0" BRAM="-1" DSP="0" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="255" filename="multest.cc" linenumber="306" name="add_ln306" contextFuncName="karastuba_mul_template&lt;32, 64&gt;" moduleName="karastuba_mul_templa.4" rtlName="add_ln306_fu_1123_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="12" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="232" name="add0_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="add0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="233" name="add1_digits_data_V" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="add1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="icmp_ln53_fu_192_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="14" filename="multest.cc" linenumber="53" name="i" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="i_fu_198_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="17" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln53_fu_222_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln58_fu_204_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="23" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln209_fu_210_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_fu_213_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="27" filename="multest.cc" linenumber="58" name="zext_ln700_9" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_9_fu_226_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="28" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln700_fu_216_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="59" name="zext_ln700_10" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_10_fu_230_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="30" filename="multest.cc" linenumber="59" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="tmp_V_fu_233_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="31" filename="multest.cc" linenumber="60" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_fu_239_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="32" filename="multest.cc" linenumber="60" name="add_ln209_6" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_6_fu_244_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="35" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="trunc_ln_reg_372" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="53" name="icmp_ln53_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="icmp_ln53_1_fu_259_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="45" filename="multest.cc" linenumber="53" name="i_23" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="i_23_fu_265_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="48" filename="multest.cc" linenumber="53" name="zext_ln53_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln53_1_fu_289_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="51" filename="multest.cc" linenumber="58" name="zext_ln58_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln58_1_fu_271_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="54" filename="multest.cc" linenumber="59" name="zext_ln209_1" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln209_1_fu_277_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="58" name="zext_ln700_11" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_11_fu_280_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="58" name="zext_ln700_12" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_12_fu_293_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="59" name="add_ln700_7" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln700_7_fu_283_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="59" name="zext_ln700_13" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="zext_ln700_13_fu_297_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="59" name="tmp_V_14" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="tmp_V_14_fu_300_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="60" name="add_ln209_7" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_7_fu_306_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="63" filename="multest.cc" linenumber="60" name="add_ln209_8" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="add_ln209_8_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="66" filename="multest.cc" linenumber="61" name="trunc_ln858_3" contextFuncName="add_I_O&lt;Bignum&lt;32, 64&gt;, Bignum&lt;32, 64&gt; &gt;" moduleName="karastuba_mul_templa" rtlName="trunc_ln858_3_reg_423" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="70" filename="multest.cc" linenumber="240" name="cross_mul_tmp_bits_w" contextFuncName="karastuba_mul_template_z1&lt;64, 64&gt;" moduleName="karastuba_mul_templa" rtlName="grp_karastuba_mul_templa_4_fu_180" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="162" name="sext_ln162" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="sext_ln162_fu_251_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="167" name="icmp_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln167_fu_255_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="167" name="zext_ln167" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln167_fu_261_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="18" filename="multest.cc" linenumber="167" name="j" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_fu_266_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="24" filename="multest.cc" linenumber="169" name="icmp_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln169_fu_272_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="26" filename="multest.cc" linenumber="169" name="i" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_fu_278_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="29" filename="multest.cc" linenumber="169" name="zext_ln169" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln169_fu_284_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="41" filename="multest.cc" linenumber="174" name="icmp_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln174_fu_289_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="174" name="i_30" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_30_fu_295_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="46" filename="multest.cc" linenumber="174" name="zext_ln174" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln174_fu_330_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="49" filename="multest.cc" linenumber="179" name="zext_ln179" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln179_fu_301_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="52" filename="multest.cc" linenumber="180" name="zext_ln180_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln180_1_fu_317_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="53" filename="multest.cc" linenumber="180" name="zext_ln180" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln180_fu_306_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="179" name="zext_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_fu_320_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="57" filename="multest.cc" linenumber="179" name="zext_ln700_36" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_36_fu_334_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="180" name="add_ln700" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln700_fu_324_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="59" filename="multest.cc" linenumber="180" name="zext_ln700_37" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_37_fu_338_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="60" filename="multest.cc" linenumber="180" name="tmp_V" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_fu_341_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="181" name="add_ln209_18" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_18_fu_347_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="62" filename="multest.cc" linenumber="181" name="add_ln209_6" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_6_fu_353_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="64" filename="multest.cc" linenumber="182" name="trunc_ln" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="trunc_ln_reg_547" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="65" filename="multest.cc" linenumber="183" name="j_10" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_10_fu_311_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="71" filename="multest.cc" linenumber="185" name="zext_ln1468" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln1468_fu_368_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="72" filename="multest.cc" linenumber="185" name="zext_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln209_fu_372_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="185" name="add_ln209" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_fu_375_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="40" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="74" filename="multest.cc" linenumber="185" name="zext_ln209_4" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln209_4_fu_381_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="185" name="add_ln209_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_1_fu_384_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="71" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="82" filename="multest.cc" linenumber="190" name="icmp_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="icmp_ln190_fu_390_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="84" filename="multest.cc" linenumber="190" name="i_31" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="i_31_fu_396_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="87" filename="multest.cc" linenumber="190" name="zext_ln190" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln190_fu_431_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="90" filename="multest.cc" linenumber="195" name="zext_ln195" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln195_fu_402_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="93" filename="multest.cc" linenumber="196" name="zext_ln196_1" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln196_1_fu_418_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="94" filename="multest.cc" linenumber="196" name="zext_ln196" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln196_fu_407_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="195" name="zext_ln700_38" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_38_fu_421_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="98" filename="multest.cc" linenumber="195" name="zext_ln700_39" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_39_fu_435_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="196" name="add_ln700_30" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln700_30_fu_425_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="100" filename="multest.cc" linenumber="196" name="zext_ln700_40" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="zext_ln700_40_fu_439_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="101" filename="multest.cc" linenumber="196" name="tmp_V_17" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="tmp_V_17_fu_442_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="197" name="add_ln209_19" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_19_fu_448_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="103" filename="multest.cc" linenumber="197" name="add_ln209_7" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="add_ln209_7_fu_454_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="198" name="trunc_ln858_s" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="trunc_ln858_s_reg_608" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="106" filename="multest.cc" linenumber="199" name="j_11" contextFuncName="CAT_I_I_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt;, Bignum&lt;128, 64&gt; &gt;" moduleName="CAT_I_I_I_O" rtlName="j_11_fu_412_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="4" filename="multest.cc" linenumber="253" name="lhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="lhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="5" filename="multest.cc" linenumber="253" name="lhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="lhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="6" filename="multest.cc" linenumber="253" name="rhs0_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="rhs0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="7" filename="multest.cc" linenumber="253" name="rhs1_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="rhs1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="8" filename="multest.cc" linenumber="253" name="lhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="lhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="9" filename="multest.cc" linenumber="253" name="lhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="lhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="10" filename="multest.cc" linenumber="253" name="rhs0_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="rhs0_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="11" filename="multest.cc" linenumber="253" name="rhs1_tmp_digits_data" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="rhs1_tmp_digits_data_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="12" filename="multest.cc" linenumber="261" name="z0_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z0_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="13" filename="multest.cc" linenumber="263" name="z2_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="15" filename="multest.cc" linenumber="270" name="add2_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="add2_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="16" filename="multest.cc" linenumber="272" name="z1_digits_data_V" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="z1_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="20" filename="multest.cc" linenumber="255" name="icmp_ln255" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="icmp_ln255_fu_480_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="22" filename="multest.cc" linenumber="255" name="i" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="i_fu_486_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="25" filename="multest.cc" linenumber="255" name="zext_ln255" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln255_fu_492_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="37" filename="multest.cc" linenumber="256" name="icmp_ln256" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="icmp_ln256_fu_497_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="39" filename="multest.cc" linenumber="256" name="i_16" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="i_16_fu_503_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="42" filename="multest.cc" linenumber="256" name="zext_ln256" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln256_fu_520_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="43" filename="multest.cc" linenumber="256" name="xor_ln256" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="xor_ln256_fu_509_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="44" filename="multest.cc" linenumber="256" name="zext_ln256_1" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln256_1_fu_515_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="56" filename="multest.cc" linenumber="257" name="icmp_ln257" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="icmp_ln257_fu_526_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="58" filename="multest.cc" linenumber="257" name="i_17" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="i_17_fu_532_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="61" filename="multest.cc" linenumber="257" name="zext_ln257" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln257_fu_538_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="73" filename="multest.cc" linenumber="258" name="icmp_ln258" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="icmp_ln258_fu_543_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="75" filename="multest.cc" linenumber="258" name="i_18" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="i_18_fu_549_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="78" filename="multest.cc" linenumber="258" name="zext_ln258" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln258_fu_566_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="79" filename="multest.cc" linenumber="258" name="xor_ln258" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="xor_ln258_fu_555_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="7" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="80" filename="multest.cc" linenumber="258" name="zext_ln258_1" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln258_1_fu_561_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="89" filename="multest.cc" linenumber="262" name="z0_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="grp_karastuba_mul_templa_4_fu_432" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="90" filename="multest.cc" linenumber="264" name="z2_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="grp_karastuba_mul_templa_4_fu_443" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="91" filename="multest.cc" linenumber="266" name="cross_mul_tmp_bits" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="grp_karastuba_mul_templa_fu_423" latency="1" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="92" filename="multest.cc" linenumber="266" name="zext_ln266" contextFuncName="karastuba_mul_template&lt;64, 64&gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln266_fu_572_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="97" filename="multest.cc" linenumber="53" name="icmp_ln53" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="icmp_ln53_fu_576_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="99" filename="multest.cc" linenumber="53" name="i_19" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="i_19_fu_582_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="102" filename="multest.cc" linenumber="53" name="zext_ln53" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln53_fu_606_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="105" filename="multest.cc" linenumber="58" name="zext_ln58" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln58_fu_588_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="108" filename="multest.cc" linenumber="59" name="zext_ln209" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln209_fu_594_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="111" filename="multest.cc" linenumber="58" name="zext_ln700" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln700_fu_597_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="112" filename="multest.cc" linenumber="58" name="zext_ln700_24" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln700_24_fu_610_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="113" filename="multest.cc" linenumber="59" name="add_ln700" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="add_ln700_fu_600_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="72" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="114" filename="multest.cc" linenumber="59" name="zext_ln700_25" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln700_25_fu_614_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="115" filename="multest.cc" linenumber="59" name="tmp_V" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="tmp_V_fu_617_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="73" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="116" filename="multest.cc" linenumber="60" name="add_ln209_13" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="add_ln209_13_fu_623_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="117" filename="multest.cc" linenumber="60" name="add_ln209" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="add_ln209_fu_628_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="64" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="120" filename="multest.cc" linenumber="61" name="trunc_ln" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="trunc_ln_reg_889" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="124" filename="multest.cc" linenumber="63" name="zext_ln63" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln63_fu_643_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="125" filename="multest.cc" linenumber="63" name="zext_ln63_1" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln63_1_fu_647_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="126" filename="multest.cc" linenumber="63" name="zext_ln63_2" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln63_2_fu_650_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="127" filename="multest.cc" linenumber="63" name="add_ln63" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="add_ln63_fu_653_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="128" filename="multest.cc" linenumber="63" name="zext_ln63_8" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln63_8_fu_659_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="129" filename="multest.cc" linenumber="63" name="add2_tmp_bits" contextFuncName="add_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="add2_tmp_bits_fu_663_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
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<item  id="137" filename="multest.cc" linenumber="77" name="i_20" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="i_20_fu_679_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="15" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
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<item  id="145" filename="multest.cc" linenumber="80" name="zext_ln180" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln180_fu_691_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
<item  id="148" filename="multest.cc" linenumber="81" name="zext_ln701" contextFuncName="sub_I_O&lt;Bignum&lt;64, 64&gt;, Bignum&lt;64, 64&gt; &gt;" moduleName="karastuba_mul_templa.3" rtlName="zext_ln701_fu_694_p1" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"&gt;&lt;\/item&gt;
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<item  id="6" filename="multest.cc" linenumber="321" name="lhs_digits_data_V" contextFuncName="karastuba_mul" moduleName="karastuba_mul" rtlName="lhs_digits_data_V_U" latency="0" BRAM="-1" DSP="-1" FF="-1" LUT="-1" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"><\/item>
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<item  id="15" filename="multest.cc" linenumber="326" name="icmp_ln326" contextFuncName="karastuba_mul" moduleName="karastuba_mul" rtlName="icmp_ln326_fu_175_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="11" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"><\/item>
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<item  id="32" filename="multest.cc" linenumber="331" name="icmp_ln331" contextFuncName="karastuba_mul" moduleName="karastuba_mul" rtlName="icmp_ln331_fu_192_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"><\/item>
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<item  id="51" filename="multest.cc" linenumber="340" name="icmp_ln340" contextFuncName="karastuba_mul" moduleName="karastuba_mul" rtlName="icmp_ln340_fu_214_p2" latency="0" BRAM="-1" DSP="-1" FF="0" LUT="13" fileDirectory="/home/tingyuan/Dropbox/High-Performance-Karatsuba-Multiplier-HLS-FPGA/HLS_Implementation"><\/item>
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