read_verilog ../dynamic_shift_registers_1.v
hierarchy -top dynamic_shift_register_1
proc
flatten
#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'.
#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dynamic_shift_register_1 # Constrain all select calls below inside the top module
#Vivado synthesizes 1 BUFG, 3 SRLC32E.
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:SRLC32E
select -assert-none t:BUFG t:SRLC32E %% t:* %D
