<stg><name>karastuba_mul_MUL_st</name>


<trans_list>

<trans id="194" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="241" from="2" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="242" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="239" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="240" from="4" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="200" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="246" from="6" to="9">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="247" from="6" to="7">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="244" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="245" from="8" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="206" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="251" from="10" to="13">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="252" from="10" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="249" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="250" from="12" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="212" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="256" from="14" to="17">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="257" from="14" to="15">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="254" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="255" from="16" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="218" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="219" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="220" from="19" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="261" from="20" to="23">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="262" from="20" to="21">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="259" from="21" to="22">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="260" from="22" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="266" from="24" to="27">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="267" from="24" to="25">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="264" from="25" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="265" from="26" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="271" from="28" to="31">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="272" from="28" to="29">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="269" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="270" from="30" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="32" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="64">
<![CDATA[
:0  %lhs0_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V"/></StgValue>
</operation>

<operation id="33" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="64" op_0_bw="64">
<![CDATA[
:1  %lhs1_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V"/></StgValue>
</operation>

<operation id="34" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="64" op_0_bw="64">
<![CDATA[
:2  %rhs0_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V"/></StgValue>
</operation>

<operation id="35" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="64" op_0_bw="64">
<![CDATA[
:3  %rhs1_digits_data_V = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V"/></StgValue>
</operation>

<operation id="36" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64">
<![CDATA[
:4  %lhs0_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="37" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64">
<![CDATA[
:5  %lhs1_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="38" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="64" op_0_bw="64">
<![CDATA[
:6  %rhs0_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="39" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="64" op_0_bw="64">
<![CDATA[
:7  %rhs1_tmp_digits_data = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="40" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="64">
<![CDATA[
:8  %p_z0_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_z0_tmp_bits"/></StgValue>
</operation>

<operation id="41" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="64" op_0_bw="64">
<![CDATA[
:9  %p_z0_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V"/></StgValue>
</operation>

<operation id="42" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="64">
<![CDATA[
:10  %p_z2_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_z2_tmp_bits"/></StgValue>
</operation>

<operation id="43" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="64" op_0_bw="64">
<![CDATA[
:11  %p_z2_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V"/></StgValue>
</operation>

<operation id="44" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="64">
<![CDATA[
:12  %p_cross_mul_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_cross_mul_tmp_bits"/></StgValue>
</operation>

<operation id="45" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="64" op_0_bw="64">
<![CDATA[
:13  %p_cross_mul_digits_da = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da"/></StgValue>
</operation>

<operation id="46" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="0" op_0_bw="0">
<![CDATA[
:14  br label %1

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="47" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0  %i_0 = phi i6 [ 0, %0 ], [ %i, %hls_label_5 ]

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="48" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %icmp_ln262 = icmp eq i6 %i_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln262"/></StgValue>
</operation>

<operation id="49" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="50" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %i = add i6 %i_0, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="51" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln262, label %.preheader30.preheader, label %hls_label_5

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>

<operation id="52" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="32" bw="64" op_0_bw="6">
<![CDATA[
hls_label_5:2  %zext_ln265 = zext i6 %i_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln265"/></StgValue>
</operation>

<operation id="53" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="33" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_5:3  %lhs_digits_data_V_ad = getelementptr [64 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="54" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="64" op_0_bw="6">
<![CDATA[
hls_label_5:4  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="55" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="64" op_0_bw="6">
<![CDATA[
hls_label_5:4  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="56" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_5:0  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str18)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="57" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_5:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln264"/></StgValue>
</operation>

<operation id="58" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="35" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_5:5  %inter_lhs_digits_dat = getelementptr [64 x i64]* %inter_lhs_digits_data_V, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="inter_lhs_digits_dat"/></StgValue>
</operation>

<operation id="59" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_5:6  store i64 %lhs_digits_data_V_lo, i64* %inter_lhs_digits_dat, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="60" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_5:7  %lhs0_tmp_digits_data_6 = getelementptr [32 x i64]* %lhs0_tmp_digits_data, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data_6"/></StgValue>
</operation>

<operation id="61" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_5:8  store i64 %lhs_digits_data_V_lo, i64* %lhs0_tmp_digits_data_6, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="62" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="39" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_5:9  %lhs0_digits_data_V_a = getelementptr [32 x i64]* %lhs0_digits_data_V, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="63" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_5:10  store i64 %lhs_digits_data_V_lo, i64* %lhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="64" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_5:11  %empty_53 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str18, i32 %tmp)

]]></Node>
<StgValue><ssdm name="empty_53"/></StgValue>
</operation>

<operation id="65" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="0">
<![CDATA[
hls_label_5:12  br label %1

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="66" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="0">
<![CDATA[
.preheader30.preheader:0  br label %.preheader30

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="67" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader30:0  %i1_0 = phi i6 [ %i_17, %hls_label_6 ], [ 0, %.preheader30.preheader ]

]]></Node>
<StgValue><ssdm name="i1_0"/></StgValue>
</operation>

<operation id="68" st_id="6" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader30:1  %icmp_ln267 = icmp eq i6 %i1_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln267"/></StgValue>
</operation>

<operation id="69" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader30:2  %empty_54 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_54"/></StgValue>
</operation>

<operation id="70" st_id="6" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader30:3  %i_17 = add i6 %i1_0, 1

]]></Node>
<StgValue><ssdm name="i_17"/></StgValue>
</operation>

<operation id="71" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader30:4  br i1 %icmp_ln267, label %.preheader29.preheader, label %hls_label_6

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>

<operation id="72" st_id="6" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
hls_label_6:3  %xor_ln270 = xor i6 %i1_0, -32

]]></Node>
<StgValue><ssdm name="xor_ln270"/></StgValue>
</operation>

<operation id="73" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="64" op_0_bw="6">
<![CDATA[
hls_label_6:4  %zext_ln270_1 = zext i6 %xor_ln270 to i64

]]></Node>
<StgValue><ssdm name="zext_ln270_1"/></StgValue>
</operation>

<operation id="74" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_6:5  %lhs_digits_data_V_ad_3 = getelementptr [64 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln270_1

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad_3"/></StgValue>
</operation>

<operation id="75" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="64" op_0_bw="6">
<![CDATA[
hls_label_6:6  %lhs_digits_data_V_lo_3 = load i64* %lhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="76" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="64" op_0_bw="6">
<![CDATA[
hls_label_6:6  %lhs_digits_data_V_lo_3 = load i64* %lhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="77" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_6:0  %tmp_3 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str19)

]]></Node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="78" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_6:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln269"/></StgValue>
</operation>

<operation id="79" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="64" op_0_bw="6">
<![CDATA[
hls_label_6:2  %zext_ln270 = zext i6 %i1_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln270"/></StgValue>
</operation>

<operation id="80" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_6:7  %inter_lhs_digits_dat_5 = getelementptr [64 x i64]* %inter_lhs_digits_data_V, i64 0, i64 %zext_ln270_1

]]></Node>
<StgValue><ssdm name="inter_lhs_digits_dat_5"/></StgValue>
</operation>

<operation id="81" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_6:8  store i64 %lhs_digits_data_V_lo_3, i64* %inter_lhs_digits_dat_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="82" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_6:9  %lhs1_tmp_digits_data_6 = getelementptr [32 x i64]* %lhs1_tmp_digits_data, i64 0, i64 %zext_ln270

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data_6"/></StgValue>
</operation>

<operation id="83" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_6:10  store i64 %lhs_digits_data_V_lo_3, i64* %lhs1_tmp_digits_data_6, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="84" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_6:11  %lhs1_digits_data_V_a = getelementptr [32 x i64]* %lhs1_digits_data_V, i64 0, i64 %zext_ln270

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="85" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_6:12  store i64 %lhs_digits_data_V_lo_3, i64* %lhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="86" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_6:13  %empty_55 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str19, i32 %tmp_3)

]]></Node>
<StgValue><ssdm name="empty_55"/></StgValue>
</operation>

<operation id="87" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="0" op_0_bw="0">
<![CDATA[
hls_label_6:14  br label %.preheader30

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="88" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="0" op_0_bw="0">
<![CDATA[
.preheader29.preheader:0  br label %.preheader29

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="89" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader29:0  %i2_0 = phi i6 [ %i_18, %hls_label_7 ], [ 0, %.preheader29.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0"/></StgValue>
</operation>

<operation id="90" st_id="10" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="71" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader29:1  %icmp_ln272 = icmp eq i6 %i2_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln272"/></StgValue>
</operation>

<operation id="91" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader29:2  %empty_56 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="92" st_id="10" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="73" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader29:3  %i_18 = add i6 %i2_0, 1

]]></Node>
<StgValue><ssdm name="i_18"/></StgValue>
</operation>

<operation id="93" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader29:4  br i1 %icmp_ln272, label %.preheader.preheader, label %hls_label_7

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>

<operation id="94" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="64" op_0_bw="6">
<![CDATA[
hls_label_7:2  %zext_ln275 = zext i6 %i2_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln275"/></StgValue>
</operation>

<operation id="95" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_7:3  %rhs_digits_data_V_ad = getelementptr [64 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="96" st_id="10" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="64" op_0_bw="6">
<![CDATA[
hls_label_7:4  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="97" st_id="11" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="64" op_0_bw="6">
<![CDATA[
hls_label_7:4  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="98" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_7:0  %tmp_4 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str20)

]]></Node>
<StgValue><ssdm name="tmp_4"/></StgValue>
</operation>

<operation id="99" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_7:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln274"/></StgValue>
</operation>

<operation id="100" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_7:5  %inter_rhs_digits_dat = getelementptr [64 x i64]* %inter_rhs_digits_data_V, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="inter_rhs_digits_dat"/></StgValue>
</operation>

<operation id="101" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_7:6  store i64 %rhs_digits_data_V_lo, i64* %inter_rhs_digits_dat, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="102" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_7:7  %rhs0_tmp_digits_data_6 = getelementptr [32 x i64]* %rhs0_tmp_digits_data, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data_6"/></StgValue>
</operation>

<operation id="103" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_7:8  store i64 %rhs_digits_data_V_lo, i64* %rhs0_tmp_digits_data_6, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="104" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_7:9  %rhs0_digits_data_V_a = getelementptr [32 x i64]* %rhs0_digits_data_V, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="105" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_7:10  store i64 %rhs_digits_data_V_lo, i64* %rhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="106" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_7:11  %empty_57 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str20, i32 %tmp_4)

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>

<operation id="107" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="0">
<![CDATA[
hls_label_7:12  br label %.preheader29

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="108" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="0" op_0_bw="0">
<![CDATA[
.preheader.preheader:0  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="109" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="92" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
.preheader:0  %i3_0 = phi i6 [ %i_19, %hls_label_8 ], [ 0, %.preheader.preheader ]

]]></Node>
<StgValue><ssdm name="i3_0"/></StgValue>
</operation>

<operation id="110" st_id="14" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="93" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:1  %icmp_ln277 = icmp eq i6 %i3_0, -32

]]></Node>
<StgValue><ssdm name="icmp_ln277"/></StgValue>
</operation>

<operation id="111" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="94" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:2  %empty_58 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_58"/></StgValue>
</operation>

<operation id="112" st_id="14" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="95" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.preheader:3  %i_19 = add i6 %i3_0, 1

]]></Node>
<StgValue><ssdm name="i_19"/></StgValue>
</operation>

<operation id="113" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:4  br i1 %icmp_ln277, label %2, label %hls_label_8

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>

<operation id="114" st_id="14" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
hls_label_8:3  %xor_ln280 = xor i6 %i3_0, -32

]]></Node>
<StgValue><ssdm name="xor_ln280"/></StgValue>
</operation>

<operation id="115" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:4  %zext_ln280_1 = zext i6 %xor_ln280 to i64

]]></Node>
<StgValue><ssdm name="zext_ln280_1"/></StgValue>
</operation>

<operation id="116" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:5  %rhs_digits_data_V_ad_3 = getelementptr [64 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln280_1

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad_3"/></StgValue>
</operation>

<operation id="117" st_id="14" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:6  %rhs_digits_data_V_lo_3 = load i64* %rhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="118" st_id="15" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:6  %rhs_digits_data_V_lo_3 = load i64* %rhs_digits_data_V_ad_3, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_3"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="119" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_8:0  %tmp_5 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str21)

]]></Node>
<StgValue><ssdm name="tmp_5"/></StgValue>
</operation>

<operation id="120" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_8:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln279"/></StgValue>
</operation>

<operation id="121" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="64" op_0_bw="6">
<![CDATA[
hls_label_8:2  %zext_ln280 = zext i6 %i3_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln280"/></StgValue>
</operation>

<operation id="122" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:7  %inter_rhs_digits_dat_5 = getelementptr [64 x i64]* %inter_rhs_digits_data_V, i64 0, i64 %zext_ln280_1

]]></Node>
<StgValue><ssdm name="inter_rhs_digits_dat_5"/></StgValue>
</operation>

<operation id="123" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_8:8  store i64 %rhs_digits_data_V_lo_3, i64* %inter_rhs_digits_dat_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="124" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:9  %rhs1_tmp_digits_data_6 = getelementptr [32 x i64]* %rhs1_tmp_digits_data, i64 0, i64 %zext_ln280

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data_6"/></StgValue>
</operation>

<operation id="125" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_8:10  store i64 %rhs_digits_data_V_lo_3, i64* %rhs1_tmp_digits_data_6, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="126" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_8:11  %rhs1_digits_data_V_a = getelementptr [32 x i64]* %rhs1_digits_data_V, i64 0, i64 %zext_ln280

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="127" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_8:12  store i64 %rhs_digits_data_V_lo_3, i64* %rhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="128" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_8:13  %empty_59 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str21, i32 %tmp_5)

]]></Node>
<StgValue><ssdm name="empty_59"/></StgValue>
</operation>

<operation id="129" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="0" op_0_bw="0">
<![CDATA[
hls_label_8:14  br label %.preheader

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="130" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="114" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  store i32 0, i32* %p_cross_mul_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>

<operation id="131" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="115" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:1  store i32 0, i32* %p_z2_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>

<operation id="132" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="116" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  store i32 0, i32* %p_z0_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="133" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="117" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:3  call fastcc void @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs0_digits_data_V, i2 0, [32 x i64]* %rhs0_digits_data_V, i32* %p_z0_tmp_bits, [64 x i64]* %p_z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln290"/></StgValue>
</operation>

<operation id="134" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:4  call fastcc void @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs1_digits_data_V, i2 0, [32 x i64]* %rhs1_digits_data_V, i32* %p_z2_tmp_bits, [64 x i64]* %p_z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln291"/></StgValue>
</operation>

<operation id="135" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="119" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:5  call fastcc void @karastuba_mul_templa([32 x i64]* %lhs0_tmp_digits_data, [32 x i64]* %lhs1_tmp_digits_data, [32 x i64]* %rhs0_tmp_digits_data, [32 x i64]* %rhs1_tmp_digits_data, i32* %p_cross_mul_tmp_bits, [64 x i64]* %p_cross_mul_digits_da)

]]></Node>
<StgValue><ssdm name="call_ln292"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="136" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="117" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:3  call fastcc void @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs0_digits_data_V, i2 0, [32 x i64]* %rhs0_digits_data_V, i32* %p_z0_tmp_bits, [64 x i64]* %p_z0_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln290"/></StgValue>
</operation>

<operation id="137" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:4  call fastcc void @karastuba_mul_templa.4(i2 0, [32 x i64]* %lhs1_digits_data_V, i2 0, [32 x i64]* %rhs1_digits_data_V, i32* %p_z2_tmp_bits, [64 x i64]* %p_z2_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln291"/></StgValue>
</operation>

<operation id="138" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="119" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:5  call fastcc void @karastuba_mul_templa([32 x i64]* %lhs0_tmp_digits_data, [32 x i64]* %lhs1_tmp_digits_data, [32 x i64]* %rhs0_tmp_digits_data, [32 x i64]* %rhs1_tmp_digits_data, i32* %p_cross_mul_tmp_bits, [64 x i64]* %p_cross_mul_digits_da)

]]></Node>
<StgValue><ssdm name="call_ln292"/></StgValue>
</operation>

<operation id="139" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="120" bw="0" op_0_bw="0">
<![CDATA[
:6  br label %3

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="140" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="122" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:0  %i4_0 = phi i7 [ 0, %2 ], [ %i_20, %hls_label_9 ]

]]></Node>
<StgValue><ssdm name="i4_0"/></StgValue>
</operation>

<operation id="141" st_id="20" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="123" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
:1  %icmp_ln294 = icmp eq i7 %i4_0, -64

]]></Node>
<StgValue><ssdm name="icmp_ln294"/></StgValue>
</operation>

<operation id="142" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="124" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_60 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_60"/></StgValue>
</operation>

<operation id="143" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
:3  %i_20 = add i7 %i4_0, 1

]]></Node>
<StgValue><ssdm name="i_20"/></StgValue>
</operation>

<operation id="144" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="126" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln294, label %4, label %hls_label_9

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>

<operation id="145" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="130" bw="64" op_0_bw="7">
<![CDATA[
hls_label_9:2  %zext_ln297 = zext i7 %i4_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln297"/></StgValue>
</operation>

<operation id="146" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="131" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_9:3  %p_z0_digits_data_V_ad = getelementptr [64 x i64]* %p_z0_digits_data_V, i64 0, i64 %zext_ln297

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_ad"/></StgValue>
</operation>

<operation id="147" st_id="20" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="132" bw="64" op_0_bw="6">
<![CDATA[
hls_label_9:4  %p_z0_digits_data_V_lo = load i64* %p_z0_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="148" st_id="21" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="132" bw="64" op_0_bw="6">
<![CDATA[
hls_label_9:4  %p_z0_digits_data_V_lo = load i64* %p_z0_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="149" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="128" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_9:0  %tmp_6 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str22)

]]></Node>
<StgValue><ssdm name="tmp_6"/></StgValue>
</operation>

<operation id="150" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="129" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_9:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln296"/></StgValue>
</operation>

<operation id="151" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="133" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_9:5  %z0_digits_data_V_add = getelementptr [64 x i64]* %z0_digits_data_V, i64 0, i64 %zext_ln297

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_add"/></StgValue>
</operation>

<operation id="152" st_id="22" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="134" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_9:6  store i64 %p_z0_digits_data_V_lo, i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln297"/></StgValue>
</operation>

<operation id="153" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="135" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_9:7  %empty_61 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str22, i32 %tmp_6)

]]></Node>
<StgValue><ssdm name="empty_61"/></StgValue>
</operation>

<operation id="154" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="136" bw="0" op_0_bw="0">
<![CDATA[
hls_label_9:8  br label %3

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="155" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="138" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  %p_z0_tmp_bits_load = load i32* %p_z0_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_z0_tmp_bits_load"/></StgValue>
</operation>

<operation id="156" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="139" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %5

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="157" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="141" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:0  %i5_0 = phi i7 [ 0, %4 ], [ %i_21, %hls_label_10 ]

]]></Node>
<StgValue><ssdm name="i5_0"/></StgValue>
</operation>

<operation id="158" st_id="24" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="142" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
:1  %icmp_ln300 = icmp eq i7 %i5_0, -64

]]></Node>
<StgValue><ssdm name="icmp_ln300"/></StgValue>
</operation>

<operation id="159" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="143" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_62 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_62"/></StgValue>
</operation>

<operation id="160" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="144" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
:3  %i_21 = add i7 %i5_0, 1

]]></Node>
<StgValue><ssdm name="i_21"/></StgValue>
</operation>

<operation id="161" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="145" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln300, label %6, label %hls_label_10

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>

<operation id="162" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="149" bw="64" op_0_bw="7">
<![CDATA[
hls_label_10:2  %zext_ln303 = zext i7 %i5_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln303"/></StgValue>
</operation>

<operation id="163" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="150" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_10:3  %p_z2_digits_data_V_ad = getelementptr [64 x i64]* %p_z2_digits_data_V, i64 0, i64 %zext_ln303

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_ad"/></StgValue>
</operation>

<operation id="164" st_id="24" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="6">
<![CDATA[
hls_label_10:4  %p_z2_digits_data_V_lo = load i64* %p_z2_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="165" st_id="25" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="6">
<![CDATA[
hls_label_10:4  %p_z2_digits_data_V_lo = load i64* %p_z2_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="166" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_10:0  %tmp_7 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str23)

]]></Node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>

<operation id="167" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_10:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln302"/></StgValue>
</operation>

<operation id="168" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_10:5  %z2_digits_data_V_add = getelementptr [64 x i64]* %z2_digits_data_V, i64 0, i64 %zext_ln303

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_add"/></StgValue>
</operation>

<operation id="169" st_id="26" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_10:6  store i64 %p_z2_digits_data_V_lo, i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln303"/></StgValue>
</operation>

<operation id="170" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_10:7  %empty_63 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str23, i32 %tmp_7)

]]></Node>
<StgValue><ssdm name="empty_63"/></StgValue>
</operation>

<operation id="171" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="0" op_0_bw="0">
<![CDATA[
hls_label_10:8  br label %5

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="172" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="157" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  %p_z2_tmp_bits_load = load i32* %p_z2_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_z2_tmp_bits_load"/></StgValue>
</operation>

<operation id="173" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="158" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %7

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="174" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="160" bw="7" op_0_bw="7" op_1_bw="0" op_2_bw="7" op_3_bw="0">
<![CDATA[
:0  %i6_0 = phi i7 [ 0, %6 ], [ %i_22, %hls_label_11 ]

]]></Node>
<StgValue><ssdm name="i6_0"/></StgValue>
</operation>

<operation id="175" st_id="28" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="161" bw="1" op_0_bw="7" op_1_bw="7">
<![CDATA[
:1  %icmp_ln306 = icmp eq i7 %i6_0, -64

]]></Node>
<StgValue><ssdm name="icmp_ln306"/></StgValue>
</operation>

<operation id="176" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="162" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_64 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 64, i64 64, i64 64)

]]></Node>
<StgValue><ssdm name="empty_64"/></StgValue>
</operation>

<operation id="177" st_id="28" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="163" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
:3  %i_22 = add i7 %i6_0, 1

]]></Node>
<StgValue><ssdm name="i_22"/></StgValue>
</operation>

<operation id="178" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="164" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln306, label %8, label %hls_label_11

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>

<operation id="179" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="168" bw="64" op_0_bw="7">
<![CDATA[
hls_label_11:2  %zext_ln309 = zext i7 %i6_0 to i64

]]></Node>
<StgValue><ssdm name="zext_ln309"/></StgValue>
</operation>

<operation id="180" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="169" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_11:3  %p_cross_mul_digits_da_5 = getelementptr [64 x i64]* %p_cross_mul_digits_da, i64 0, i64 %zext_ln309

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_5"/></StgValue>
</operation>

<operation id="181" st_id="28" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="170" bw="64" op_0_bw="6">
<![CDATA[
hls_label_11:4  %p_cross_mul_digits_da_6 = load i64* %p_cross_mul_digits_da_5, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_6"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="182" st_id="29" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="170" bw="64" op_0_bw="6">
<![CDATA[
hls_label_11:4  %p_cross_mul_digits_da_6 = load i64* %p_cross_mul_digits_da_5, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_6"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="183" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_11:0  %tmp_8 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str24)

]]></Node>
<StgValue><ssdm name="tmp_8"/></StgValue>
</operation>

<operation id="184" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="167" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_11:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln308"/></StgValue>
</operation>

<operation id="185" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="6" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_11:5  %cross_mul_digits_dat = getelementptr [64 x i64]* %cross_mul_digits_data_V, i64 0, i64 %zext_ln309

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat"/></StgValue>
</operation>

<operation id="186" st_id="30" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="0" op_0_bw="64" op_1_bw="6">
<![CDATA[
hls_label_11:6  store i64 %p_cross_mul_digits_da_6, i64* %cross_mul_digits_dat, align 8

]]></Node>
<StgValue><ssdm name="store_ln309"/></StgValue>
</operation>

<operation id="187" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="173" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_11:7  %empty_65 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str24, i32 %tmp_8)

]]></Node>
<StgValue><ssdm name="empty_65"/></StgValue>
</operation>

<operation id="188" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="174" bw="0" op_0_bw="0">
<![CDATA[
hls_label_11:8  br label %7

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="189" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="176" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  %p_cross_mul_tmp_bits_s = load i32* %p_cross_mul_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_tmp_bits_s"/></StgValue>
</operation>

<operation id="190" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="177" bw="96" op_0_bw="96" op_1_bw="32">
<![CDATA[
:1  %newret = insertvalue { i32, i32, i32 } undef, i32 %p_z0_tmp_bits_load, 0

]]></Node>
<StgValue><ssdm name="newret"/></StgValue>
</operation>

<operation id="191" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="178" bw="96" op_0_bw="96" op_1_bw="32">
<![CDATA[
:2  %newret2 = insertvalue { i32, i32, i32 } %newret, i32 %p_z2_tmp_bits_load, 1

]]></Node>
<StgValue><ssdm name="newret2"/></StgValue>
</operation>

<operation id="192" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="179" bw="96" op_0_bw="96" op_1_bw="32">
<![CDATA[
:3  %newret4 = insertvalue { i32, i32, i32 } %newret2, i32 %p_cross_mul_tmp_bits_s, 2

]]></Node>
<StgValue><ssdm name="newret4"/></StgValue>
</operation>

<operation id="193" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="180" bw="0" op_0_bw="96">
<![CDATA[
:4  ret { i32, i32, i32 } %newret4

]]></Node>
<StgValue><ssdm name="ret_ln299"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
