<stg><name>karastuba_mul</name>


<trans_list>

<trans id="26" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="27" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="28" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="29" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="30" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="31" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="32" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="9" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="64" op_0_bw="64">
<![CDATA[
codeRepl:4  %lhs_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="64">
<![CDATA[
codeRepl:5  %rhs_digits_data_V = alloca [64 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="64" op_0_bw="64">
<![CDATA[
codeRepl:6  %res_digits_data_V = alloca [128 x i64], align 8

]]></Node>
<StgValue><ssdm name="res_digits_data_V"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="12" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
codeRepl:10  call fastcc void @Loop_1_proc(i64* %hs_input_V, [64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="13" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
codeRepl:10  call fastcc void @Loop_1_proc(i64* %hs_input_V, [64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="14" st_id="4" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="0" op_5_bw="0">
<![CDATA[
codeRepl:11  call fastcc void @karastuba_mul_templa.3([64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln423"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="15" st_id="5" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="0" op_5_bw="0">
<![CDATA[
codeRepl:11  call fastcc void @karastuba_mul_templa.3([64 x i64]* %lhs_digits_data_V, [64 x i64]* %rhs_digits_data_V, [128 x i64]* %res_digits_data_V)

]]></Node>
<StgValue><ssdm name="call_ln423"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="16" st_id="6" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="0" op_4_bw="0">
<![CDATA[
codeRepl:12  call fastcc void @Loop_2_proc([128 x i64]* %res_digits_data_V, i64* %res_output_V)

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="17" st_id="7" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="0" op_4_bw="0">
<![CDATA[
codeRepl:12  call fastcc void @Loop_2_proc([128 x i64]* %res_digits_data_V, i64* %res_output_V)

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="18" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="3" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="0">
<![CDATA[
codeRepl:0  call void (...)* @_ssdm_op_SpecDataflowPipeline(i32 -1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specdataflowpipeline_ln410"/></StgValue>
</operation>

<operation id="19" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="4" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
codeRepl:1  call void (...)* @_ssdm_op_SpecBitsMap(i64* %hs_input_V), !map !180

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="20" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
codeRepl:2  call void (...)* @_ssdm_op_SpecBitsMap(i64* %res_output_V), !map !186

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="21" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
codeRepl:3  call void (...)* @_ssdm_op_SpecTopModule([14 x i8]* @karastuba_mul_str) nounwind

]]></Node>
<StgValue><ssdm name="spectopmodule_ln0"/></StgValue>
</operation>

<operation id="22" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:7  call void (...)* @_ssdm_op_SpecInterface(i32 0, [10 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str1, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specinterface_ln403"/></StgValue>
</operation>

<operation id="23" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:8  call void (...)* @_ssdm_op_SpecInterface(i64* %hs_input_V, [5 x i8]* @p_str2, i32 1, i32 1, [5 x i8]* @p_str3, i32 0, i32 1024, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln404"/></StgValue>
</operation>

<operation id="24" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:9  call void (...)* @_ssdm_op_SpecInterface(i64* %res_output_V, [5 x i8]* @p_str2, i32 1, i32 1, [5 x i8]* @p_str3, i32 0, i32 1024, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln405"/></StgValue>
</operation>

<operation id="25" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="0">
<![CDATA[
codeRepl:13  ret void

]]></Node>
<StgValue><ssdm name="ret_ln431"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
