<stg><name>karastuba_mul_MUL_st.1</name>


<trans_list>

<trans id="200" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="247" from="2" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="248" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="245" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="246" from="4" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="206" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="252" from="6" to="9">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="253" from="6" to="7">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="250" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="251" from="8" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="212" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="257" from="10" to="13">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="258" from="10" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="255" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="256" from="12" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="218" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="262" from="14" to="17">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="263" from="14" to="15">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="260" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="261" from="16" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="224" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="225" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="19" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="267" from="20" to="23">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="268" from="20" to="21">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="265" from="21" to="22">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="266" from="22" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="272" from="24" to="27">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="273" from="24" to="25">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="270" from="25" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="271" from="26" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="238" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="277" from="28" to="31">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="278" from="28" to="29">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="275" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="276" from="30" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="32" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
entry:0  %rhs_tmp_bits_read_4 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %rhs_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="rhs_tmp_bits_read_4"/></StgValue>
</operation>

<operation id="33" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="2" op_0_bw="2" op_1_bw="2">
<![CDATA[
entry:1  %lhs_tmp_bits_read_4 = call i2 @_ssdm_op_Read.ap_auto.i2(i2 %lhs_tmp_bits_read)

]]></Node>
<StgValue><ssdm name="lhs_tmp_bits_read_4"/></StgValue>
</operation>

<operation id="34" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64">
<![CDATA[
entry:2  %lhs0_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V"/></StgValue>
</operation>

<operation id="35" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64">
<![CDATA[
entry:3  %lhs1_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V"/></StgValue>
</operation>

<operation id="36" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="64" op_0_bw="64">
<![CDATA[
entry:4  %rhs0_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V"/></StgValue>
</operation>

<operation id="37" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="64" op_0_bw="64">
<![CDATA[
entry:5  %rhs1_digits_data_V = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V"/></StgValue>
</operation>

<operation id="38" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="64" op_0_bw="64">
<![CDATA[
entry:6  %lhs0_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="39" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="64" op_0_bw="64">
<![CDATA[
entry:7  %lhs1_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="40" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="64" op_0_bw="64">
<![CDATA[
entry:8  %rhs0_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data"/></StgValue>
</operation>

<operation id="41" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="64" op_0_bw="64">
<![CDATA[
entry:9  %rhs1_tmp_digits_data = alloca [16 x i64], align 8

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data"/></StgValue>
</operation>

<operation id="42" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="64">
<![CDATA[
entry:10  %p_z0_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_z0_tmp_bits"/></StgValue>
</operation>

<operation id="43" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="64" op_0_bw="64">
<![CDATA[
entry:11  %p_z0_digits_data_V_i = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_i"/></StgValue>
</operation>

<operation id="44" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="64">
<![CDATA[
entry:12  %p_z2_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_z2_tmp_bits"/></StgValue>
</operation>

<operation id="45" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64">
<![CDATA[
entry:13  %p_z2_digits_data_V_i = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_i"/></StgValue>
</operation>

<operation id="46" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="64">
<![CDATA[
entry:14  %p_cross_mul_tmp_bits = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="p_cross_mul_tmp_bits"/></StgValue>
</operation>

<operation id="47" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="64" op_0_bw="64">
<![CDATA[
entry:15  %p_cross_mul_digits_da = alloca [32 x i64], align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da"/></StgValue>
</operation>

<operation id="48" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="32" op_0_bw="2">
<![CDATA[
entry:16  %p_read1_cast_i = zext i2 %rhs_tmp_bits_read_4 to i32

]]></Node>
<StgValue><ssdm name="p_read1_cast_i"/></StgValue>
</operation>

<operation id="49" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="32" op_0_bw="2">
<![CDATA[
entry:17  %p_read_cast_i = zext i2 %lhs_tmp_bits_read_4 to i32

]]></Node>
<StgValue><ssdm name="p_read_cast_i"/></StgValue>
</operation>

<operation id="50" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="0" op_0_bw="0">
<![CDATA[
entry:18  br label %0

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="51" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
:0  %i_0_i = phi i5 [ 0, %entry ], [ %i, %hls_label_12 ]

]]></Node>
<StgValue><ssdm name="i_0_i"/></StgValue>
</operation>

<operation id="52" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
:1  %icmp_ln262 = icmp eq i5 %i_0_i, -16

]]></Node>
<StgValue><ssdm name="icmp_ln262"/></StgValue>
</operation>

<operation id="53" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="54" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:3  %i = add i5 %i_0_i, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="55" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln262, label %.preheader30.i.preheader, label %hls_label_12

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>

<operation id="56" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="64" op_0_bw="5">
<![CDATA[
hls_label_12:2  %zext_ln265 = zext i5 %i_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln265"/></StgValue>
</operation>

<operation id="57" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="39" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_12:3  %lhs_digits_data_V_ad = getelementptr [32 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="58" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="64" op_0_bw="5">
<![CDATA[
hls_label_12:4  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="59" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="64" op_0_bw="5">
<![CDATA[
hls_label_12:4  %lhs_digits_data_V_lo = load i64* %lhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="60" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_12:0  %tmp_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str32)

]]></Node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="61" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_12:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln264"/></StgValue>
</operation>

<operation id="62" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_12:5  %inter_lhs_digits_dat_3 = getelementptr [32 x i64]* %inter_lhs_digits_dat, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="inter_lhs_digits_dat_3"/></StgValue>
</operation>

<operation id="63" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_12:6  store i64 %lhs_digits_data_V_lo, i64* %inter_lhs_digits_dat_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="64" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_12:7  %lhs0_tmp_digits_data_5 = getelementptr [16 x i64]* %lhs0_tmp_digits_data, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs0_tmp_digits_data_5"/></StgValue>
</operation>

<operation id="65" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_12:8  store i64 %lhs_digits_data_V_lo, i64* %lhs0_tmp_digits_data_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="66" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_12:9  %lhs0_digits_data_V_a = getelementptr [16 x i64]* %lhs0_digits_data_V, i64 0, i64 %zext_ln265

]]></Node>
<StgValue><ssdm name="lhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="67" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_12:10  store i64 %lhs_digits_data_V_lo, i64* %lhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln265"/></StgValue>
</operation>

<operation id="68" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_12:11  %empty_39 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str32, i32 %tmp_i)

]]></Node>
<StgValue><ssdm name="empty_39"/></StgValue>
</operation>

<operation id="69" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln262" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0">
<![CDATA[
hls_label_12:12  br label %0

]]></Node>
<StgValue><ssdm name="br_ln262"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="70" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="0">
<![CDATA[
.preheader30.i.preheader:0  br label %.preheader30.i

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="71" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader30.i:0  %i1_0_i = phi i5 [ %i_11, %hls_label_13 ], [ 0, %.preheader30.i.preheader ]

]]></Node>
<StgValue><ssdm name="i1_0_i"/></StgValue>
</operation>

<operation id="72" st_id="6" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader30.i:1  %icmp_ln267 = icmp eq i5 %i1_0_i, -16

]]></Node>
<StgValue><ssdm name="icmp_ln267"/></StgValue>
</operation>

<operation id="73" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader30.i:2  %empty_40 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_40"/></StgValue>
</operation>

<operation id="74" st_id="6" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader30.i:3  %i_11 = add i5 %i1_0_i, 1

]]></Node>
<StgValue><ssdm name="i_11"/></StgValue>
</operation>

<operation id="75" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="56" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader30.i:4  br i1 %icmp_ln267, label %.preheader29.i.preheader, label %hls_label_13

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>

<operation id="76" st_id="6" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
hls_label_13:3  %xor_ln270 = xor i5 %i1_0_i, -16

]]></Node>
<StgValue><ssdm name="xor_ln270"/></StgValue>
</operation>

<operation id="77" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="64" op_0_bw="5">
<![CDATA[
hls_label_13:4  %zext_ln270_2 = zext i5 %xor_ln270 to i64

]]></Node>
<StgValue><ssdm name="zext_ln270_2"/></StgValue>
</operation>

<operation id="78" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_13:5  %lhs_digits_data_V_ad_2 = getelementptr [32 x i64]* %lhs_digits_data_V, i64 0, i64 %zext_ln270_2

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_ad_2"/></StgValue>
</operation>

<operation id="79" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="64" op_0_bw="5">
<![CDATA[
hls_label_13:6  %lhs_digits_data_V_lo_2 = load i64* %lhs_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_2"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="80" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="64" op_0_bw="5">
<![CDATA[
hls_label_13:6  %lhs_digits_data_V_lo_2 = load i64* %lhs_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="lhs_digits_data_V_lo_2"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="81" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_13:0  %tmp_9_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str33)

]]></Node>
<StgValue><ssdm name="tmp_9_i"/></StgValue>
</operation>

<operation id="82" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_13:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln269"/></StgValue>
</operation>

<operation id="83" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="64" op_0_bw="5">
<![CDATA[
hls_label_13:2  %zext_ln270 = zext i5 %i1_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln270"/></StgValue>
</operation>

<operation id="84" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_13:7  %inter_lhs_digits_dat_4 = getelementptr [32 x i64]* %inter_lhs_digits_dat, i64 0, i64 %zext_ln270_2

]]></Node>
<StgValue><ssdm name="inter_lhs_digits_dat_4"/></StgValue>
</operation>

<operation id="85" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_13:8  store i64 %lhs_digits_data_V_lo_2, i64* %inter_lhs_digits_dat_4, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="86" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_13:9  %lhs1_tmp_digits_data_5 = getelementptr [16 x i64]* %lhs1_tmp_digits_data, i64 0, i64 %zext_ln270

]]></Node>
<StgValue><ssdm name="lhs1_tmp_digits_data_5"/></StgValue>
</operation>

<operation id="87" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_13:10  store i64 %lhs_digits_data_V_lo_2, i64* %lhs1_tmp_digits_data_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="88" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_13:11  %lhs1_digits_data_V_a = getelementptr [16 x i64]* %lhs1_digits_data_V, i64 0, i64 %zext_ln270

]]></Node>
<StgValue><ssdm name="lhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="89" st_id="8" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_13:12  store i64 %lhs_digits_data_V_lo_2, i64* %lhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln270"/></StgValue>
</operation>

<operation id="90" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_13:13  %empty_41 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str33, i32 %tmp_9_i)

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="91" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln267" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="0" op_0_bw="0">
<![CDATA[
hls_label_13:14  br label %.preheader30.i

]]></Node>
<StgValue><ssdm name="br_ln267"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="92" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="0" op_0_bw="0">
<![CDATA[
.preheader29.i.preheader:0  br label %.preheader29.i

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="93" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader29.i:0  %i2_0_i = phi i5 [ %i_12, %hls_label_14 ], [ 0, %.preheader29.i.preheader ]

]]></Node>
<StgValue><ssdm name="i2_0_i"/></StgValue>
</operation>

<operation id="94" st_id="10" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="77" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader29.i:1  %icmp_ln272 = icmp eq i5 %i2_0_i, -16

]]></Node>
<StgValue><ssdm name="icmp_ln272"/></StgValue>
</operation>

<operation id="95" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader29.i:2  %empty_42 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>

<operation id="96" st_id="10" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader29.i:3  %i_12 = add i5 %i2_0_i, 1

]]></Node>
<StgValue><ssdm name="i_12"/></StgValue>
</operation>

<operation id="97" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader29.i:4  br i1 %icmp_ln272, label %.preheader.i.preheader, label %hls_label_14

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>

<operation id="98" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="64" op_0_bw="5">
<![CDATA[
hls_label_14:2  %zext_ln275 = zext i5 %i2_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln275"/></StgValue>
</operation>

<operation id="99" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_14:3  %rhs_digits_data_V_ad = getelementptr [32 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad"/></StgValue>
</operation>

<operation id="100" st_id="10" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="5">
<![CDATA[
hls_label_14:4  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="101" st_id="11" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="5">
<![CDATA[
hls_label_14:4  %rhs_digits_data_V_lo = load i64* %rhs_digits_data_V_ad, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="102" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_14:0  %tmp_i_43 = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str34)

]]></Node>
<StgValue><ssdm name="tmp_i_43"/></StgValue>
</operation>

<operation id="103" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_14:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln274"/></StgValue>
</operation>

<operation id="104" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_14:5  %inter_rhs_digits_dat_3 = getelementptr [32 x i64]* %inter_rhs_digits_dat, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="inter_rhs_digits_dat_3"/></StgValue>
</operation>

<operation id="105" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_14:6  store i64 %rhs_digits_data_V_lo, i64* %inter_rhs_digits_dat_3, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="106" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_14:7  %rhs0_tmp_digits_data_5 = getelementptr [16 x i64]* %rhs0_tmp_digits_data, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs0_tmp_digits_data_5"/></StgValue>
</operation>

<operation id="107" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_14:8  store i64 %rhs_digits_data_V_lo, i64* %rhs0_tmp_digits_data_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="108" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_14:9  %rhs0_digits_data_V_a = getelementptr [16 x i64]* %rhs0_digits_data_V, i64 0, i64 %zext_ln275

]]></Node>
<StgValue><ssdm name="rhs0_digits_data_V_a"/></StgValue>
</operation>

<operation id="109" st_id="12" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_14:10  store i64 %rhs_digits_data_V_lo, i64* %rhs0_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln275"/></StgValue>
</operation>

<operation id="110" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_14:11  %empty_44 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str34, i32 %tmp_i_43)

]]></Node>
<StgValue><ssdm name="empty_44"/></StgValue>
</operation>

<operation id="111" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln272" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="0" op_0_bw="0">
<![CDATA[
hls_label_14:12  br label %.preheader29.i

]]></Node>
<StgValue><ssdm name="br_ln272"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="112" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="0" op_0_bw="0">
<![CDATA[
.preheader.i.preheader:0  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="113" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="98" bw="5" op_0_bw="5" op_1_bw="0" op_2_bw="5" op_3_bw="0">
<![CDATA[
.preheader.i:0  %i3_0_i = phi i5 [ %i_13, %hls_label_15 ], [ 0, %.preheader.i.preheader ]

]]></Node>
<StgValue><ssdm name="i3_0_i"/></StgValue>
</operation>

<operation id="114" st_id="14" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="99" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader.i:1  %icmp_ln277 = icmp eq i5 %i3_0_i, -16

]]></Node>
<StgValue><ssdm name="icmp_ln277"/></StgValue>
</operation>

<operation id="115" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="100" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader.i:2  %empty_45 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 16, i64 16, i64 16)

]]></Node>
<StgValue><ssdm name="empty_45"/></StgValue>
</operation>

<operation id="116" st_id="14" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="101" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader.i:3  %i_13 = add i5 %i3_0_i, 1

]]></Node>
<StgValue><ssdm name="i_13"/></StgValue>
</operation>

<operation id="117" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="102" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader.i:4  br i1 %icmp_ln277, label %1, label %hls_label_15

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>

<operation id="118" st_id="14" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
hls_label_15:3  %xor_ln280 = xor i5 %i3_0_i, -16

]]></Node>
<StgValue><ssdm name="xor_ln280"/></StgValue>
</operation>

<operation id="119" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="64" op_0_bw="5">
<![CDATA[
hls_label_15:4  %zext_ln280_2 = zext i5 %xor_ln280 to i64

]]></Node>
<StgValue><ssdm name="zext_ln280_2"/></StgValue>
</operation>

<operation id="120" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_15:5  %rhs_digits_data_V_ad_2 = getelementptr [32 x i64]* %rhs_digits_data_V, i64 0, i64 %zext_ln280_2

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_ad_2"/></StgValue>
</operation>

<operation id="121" st_id="14" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="64" op_0_bw="5">
<![CDATA[
hls_label_15:6  %rhs_digits_data_V_lo_2 = load i64* %rhs_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_2"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="122" st_id="15" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="64" op_0_bw="5">
<![CDATA[
hls_label_15:6  %rhs_digits_data_V_lo_2 = load i64* %rhs_digits_data_V_ad_2, align 8

]]></Node>
<StgValue><ssdm name="rhs_digits_data_V_lo_2"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="123" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_15:0  %tmp_1_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str35)

]]></Node>
<StgValue><ssdm name="tmp_1_i"/></StgValue>
</operation>

<operation id="124" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_15:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln279"/></StgValue>
</operation>

<operation id="125" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="64" op_0_bw="5">
<![CDATA[
hls_label_15:2  %zext_ln280 = zext i5 %i3_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln280"/></StgValue>
</operation>

<operation id="126" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_15:7  %inter_rhs_digits_dat_4 = getelementptr [32 x i64]* %inter_rhs_digits_dat, i64 0, i64 %zext_ln280_2

]]></Node>
<StgValue><ssdm name="inter_rhs_digits_dat_4"/></StgValue>
</operation>

<operation id="127" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_15:8  store i64 %rhs_digits_data_V_lo_2, i64* %inter_rhs_digits_dat_4, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="128" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_15:9  %rhs1_tmp_digits_data_5 = getelementptr [16 x i64]* %rhs1_tmp_digits_data, i64 0, i64 %zext_ln280

]]></Node>
<StgValue><ssdm name="rhs1_tmp_digits_data_5"/></StgValue>
</operation>

<operation id="129" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_15:10  store i64 %rhs_digits_data_V_lo_2, i64* %rhs1_tmp_digits_data_5, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="130" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_15:11  %rhs1_digits_data_V_a = getelementptr [16 x i64]* %rhs1_digits_data_V, i64 0, i64 %zext_ln280

]]></Node>
<StgValue><ssdm name="rhs1_digits_data_V_a"/></StgValue>
</operation>

<operation id="131" st_id="16" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
hls_label_15:12  store i64 %rhs_digits_data_V_lo_2, i64* %rhs1_digits_data_V_a, align 8

]]></Node>
<StgValue><ssdm name="store_ln280"/></StgValue>
</operation>

<operation id="132" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_15:13  %empty_46 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str35, i32 %tmp_1_i)

]]></Node>
<StgValue><ssdm name="empty_46"/></StgValue>
</operation>

<operation id="133" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln277" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="0">
<![CDATA[
hls_label_15:14  br label %.preheader.i

]]></Node>
<StgValue><ssdm name="br_ln277"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="134" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="120" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  store i32 0, i32* %p_cross_mul_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>

<operation id="135" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="121" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:1  store i32 0, i32* %p_z2_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>

<operation id="136" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="122" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  store i32 0, i32* %p_z0_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="store_ln288"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="137" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="123" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:3  call fastcc void @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs0_digits_data_V, i2 0, [16 x i64]* %rhs0_digits_data_V, i32* %p_z0_tmp_bits, [32 x i64]* %p_z0_digits_data_V_i)

]]></Node>
<StgValue><ssdm name="call_ln290"/></StgValue>
</operation>

<operation id="138" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="124" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:4  call fastcc void @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs1_digits_data_V, i2 0, [16 x i64]* %rhs1_digits_data_V, i32* %p_z2_tmp_bits, [32 x i64]* %p_z2_digits_data_V_i)

]]></Node>
<StgValue><ssdm name="call_ln291"/></StgValue>
</operation>

<operation id="139" st_id="18" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:5  call fastcc void @karastuba_mul_templa.1([16 x i64]* %lhs0_tmp_digits_data, [16 x i64]* %lhs1_tmp_digits_data, [16 x i64]* %rhs0_tmp_digits_data, [16 x i64]* %rhs1_tmp_digits_data, i32* %p_cross_mul_tmp_bits, [32 x i64]* %p_cross_mul_digits_da)

]]></Node>
<StgValue><ssdm name="call_ln292"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="140" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="123" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:3  call fastcc void @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs0_digits_data_V, i2 0, [16 x i64]* %rhs0_digits_data_V, i32* %p_z0_tmp_bits, [32 x i64]* %p_z0_digits_data_V_i)

]]></Node>
<StgValue><ssdm name="call_ln290"/></StgValue>
</operation>

<operation id="141" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="124" bw="0" op_0_bw="0" op_1_bw="2" op_2_bw="64" op_3_bw="2" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:4  call fastcc void @karastuba_mul_templa.5(i2 0, [16 x i64]* %lhs1_digits_data_V, i2 0, [16 x i64]* %rhs1_digits_data_V, i32* %p_z2_tmp_bits, [32 x i64]* %p_z2_digits_data_V_i)

]]></Node>
<StgValue><ssdm name="call_ln291"/></StgValue>
</operation>

<operation id="142" st_id="19" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64" op_4_bw="64" op_5_bw="32" op_6_bw="64" op_7_bw="0">
<![CDATA[
:5  call fastcc void @karastuba_mul_templa.1([16 x i64]* %lhs0_tmp_digits_data, [16 x i64]* %lhs1_tmp_digits_data, [16 x i64]* %rhs0_tmp_digits_data, [16 x i64]* %rhs1_tmp_digits_data, i32* %p_cross_mul_tmp_bits, [32 x i64]* %p_cross_mul_digits_da)

]]></Node>
<StgValue><ssdm name="call_ln292"/></StgValue>
</operation>

<operation id="143" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="126" bw="0" op_0_bw="0">
<![CDATA[
:6  br label %2

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="144" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0  %i4_0_i = phi i6 [ 0, %1 ], [ %i_14, %hls_label_16 ]

]]></Node>
<StgValue><ssdm name="i4_0_i"/></StgValue>
</operation>

<operation id="145" st_id="20" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="129" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %icmp_ln294 = icmp eq i6 %i4_0_i, -32

]]></Node>
<StgValue><ssdm name="icmp_ln294"/></StgValue>
</operation>

<operation id="146" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="130" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_47 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_47"/></StgValue>
</operation>

<operation id="147" st_id="20" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="131" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %i_14 = add i6 %i4_0_i, 1

]]></Node>
<StgValue><ssdm name="i_14"/></StgValue>
</operation>

<operation id="148" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="132" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln294, label %3, label %hls_label_16

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>

<operation id="149" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="136" bw="64" op_0_bw="6">
<![CDATA[
hls_label_16:2  %zext_ln297 = zext i6 %i4_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln297"/></StgValue>
</operation>

<operation id="150" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="137" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_16:3  %p_z0_digits_data_V_i_s = getelementptr [32 x i64]* %p_z0_digits_data_V_i, i64 0, i64 %zext_ln297

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_i_s"/></StgValue>
</operation>

<operation id="151" st_id="20" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="138" bw="64" op_0_bw="5">
<![CDATA[
hls_label_16:4  %p_z0_digits_data_V_i_1 = load i64* %p_z0_digits_data_V_i_s, align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_i_1"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="152" st_id="21" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="138" bw="64" op_0_bw="5">
<![CDATA[
hls_label_16:4  %p_z0_digits_data_V_i_1 = load i64* %p_z0_digits_data_V_i_s, align 8

]]></Node>
<StgValue><ssdm name="p_z0_digits_data_V_i_1"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="153" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="134" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_16:0  %tmp_2_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str36)

]]></Node>
<StgValue><ssdm name="tmp_2_i"/></StgValue>
</operation>

<operation id="154" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="135" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_16:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln296"/></StgValue>
</operation>

<operation id="155" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_16:5  %z0_digits_data_V_add = getelementptr [32 x i64]* %z0_digits_data_V, i64 0, i64 %zext_ln297

]]></Node>
<StgValue><ssdm name="z0_digits_data_V_add"/></StgValue>
</operation>

<operation id="156" st_id="22" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_16:6  store i64 %p_z0_digits_data_V_i_1, i64* %z0_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln297"/></StgValue>
</operation>

<operation id="157" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="141" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_16:7  %empty_48 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str36, i32 %tmp_2_i)

]]></Node>
<StgValue><ssdm name="empty_48"/></StgValue>
</operation>

<operation id="158" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln294" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="142" bw="0" op_0_bw="0">
<![CDATA[
hls_label_16:8  br label %2

]]></Node>
<StgValue><ssdm name="br_ln294"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="159" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="144" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  %p_z0_tmp_bits_load = load i32* %p_z0_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_z0_tmp_bits_load"/></StgValue>
</operation>

<operation id="160" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="145" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %4

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="161" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="147" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0  %i5_0_i = phi i6 [ 0, %3 ], [ %i_15, %hls_label_17 ]

]]></Node>
<StgValue><ssdm name="i5_0_i"/></StgValue>
</operation>

<operation id="162" st_id="24" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="148" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %icmp_ln300 = icmp eq i6 %i5_0_i, -32

]]></Node>
<StgValue><ssdm name="icmp_ln300"/></StgValue>
</operation>

<operation id="163" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="149" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_49 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_49"/></StgValue>
</operation>

<operation id="164" st_id="24" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="150" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %i_15 = add i6 %i5_0_i, 1

]]></Node>
<StgValue><ssdm name="i_15"/></StgValue>
</operation>

<operation id="165" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="151" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln300, label %5, label %hls_label_17

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>

<operation id="166" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="64" op_0_bw="6">
<![CDATA[
hls_label_17:2  %zext_ln303 = zext i6 %i5_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln303"/></StgValue>
</operation>

<operation id="167" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="156" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_17:3  %p_z2_digits_data_V_i_s = getelementptr [32 x i64]* %p_z2_digits_data_V_i, i64 0, i64 %zext_ln303

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_i_s"/></StgValue>
</operation>

<operation id="168" st_id="24" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="64" op_0_bw="5">
<![CDATA[
hls_label_17:4  %p_z2_digits_data_V_i_1 = load i64* %p_z2_digits_data_V_i_s, align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_i_1"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="169" st_id="25" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="64" op_0_bw="5">
<![CDATA[
hls_label_17:4  %p_z2_digits_data_V_i_1 = load i64* %p_z2_digits_data_V_i_s, align 8

]]></Node>
<StgValue><ssdm name="p_z2_digits_data_V_i_1"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="170" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_17:0  %tmp_3_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str37)

]]></Node>
<StgValue><ssdm name="tmp_3_i"/></StgValue>
</operation>

<operation id="171" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_17:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln302"/></StgValue>
</operation>

<operation id="172" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_17:5  %z2_digits_data_V_add = getelementptr [32 x i64]* %z2_digits_data_V, i64 0, i64 %zext_ln303

]]></Node>
<StgValue><ssdm name="z2_digits_data_V_add"/></StgValue>
</operation>

<operation id="173" st_id="26" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_17:6  store i64 %p_z2_digits_data_V_i_1, i64* %z2_digits_data_V_add, align 8

]]></Node>
<StgValue><ssdm name="store_ln303"/></StgValue>
</operation>

<operation id="174" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_17:7  %empty_50 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str37, i32 %tmp_3_i)

]]></Node>
<StgValue><ssdm name="empty_50"/></StgValue>
</operation>

<operation id="175" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln300" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="161" bw="0" op_0_bw="0">
<![CDATA[
hls_label_17:8  br label %4

]]></Node>
<StgValue><ssdm name="br_ln300"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="176" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="163" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  %p_z2_tmp_bits_load = load i32* %p_z2_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_z2_tmp_bits_load"/></StgValue>
</operation>

<operation id="177" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="164" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %6

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="178" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="166" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0  %i6_0_i = phi i6 [ 0, %5 ], [ %i_16, %hls_label_18 ]

]]></Node>
<StgValue><ssdm name="i6_0_i"/></StgValue>
</operation>

<operation id="179" st_id="28" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="167" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1  %icmp_ln306 = icmp eq i6 %i6_0_i, -32

]]></Node>
<StgValue><ssdm name="icmp_ln306"/></StgValue>
</operation>

<operation id="180" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="168" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2  %empty_51 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 32, i64 32, i64 32)

]]></Node>
<StgValue><ssdm name="empty_51"/></StgValue>
</operation>

<operation id="181" st_id="28" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="169" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3  %i_16 = add i6 %i6_0_i, 1

]]></Node>
<StgValue><ssdm name="i_16"/></StgValue>
</operation>

<operation id="182" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="170" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %icmp_ln306, label %karastuba_mul_MUL_st.1.exit, label %hls_label_18

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>

<operation id="183" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="174" bw="64" op_0_bw="6">
<![CDATA[
hls_label_18:2  %zext_ln309 = zext i6 %i6_0_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln309"/></StgValue>
</operation>

<operation id="184" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="175" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_18:3  %p_cross_mul_digits_da_3 = getelementptr [32 x i64]* %p_cross_mul_digits_da, i64 0, i64 %zext_ln309

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_3"/></StgValue>
</operation>

<operation id="185" st_id="28" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="176" bw="64" op_0_bw="5">
<![CDATA[
hls_label_18:4  %p_cross_mul_digits_da_4 = load i64* %p_cross_mul_digits_da_3, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_4"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="186" st_id="29" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="176" bw="64" op_0_bw="5">
<![CDATA[
hls_label_18:4  %p_cross_mul_digits_da_4 = load i64* %p_cross_mul_digits_da_3, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_digits_da_4"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="187" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_18:0  %tmp_4_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([13 x i8]* @p_str38)

]]></Node>
<StgValue><ssdm name="tmp_4_i"/></StgValue>
</operation>

<operation id="188" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="173" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_18:1  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln308"/></StgValue>
</operation>

<operation id="189" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="5" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_18:5  %cross_mul_digits_dat_2 = getelementptr [32 x i64]* %cross_mul_digits_dat, i64 0, i64 %zext_ln309

]]></Node>
<StgValue><ssdm name="cross_mul_digits_dat_2"/></StgValue>
</operation>

<operation id="190" st_id="30" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="0" op_0_bw="64" op_1_bw="5">
<![CDATA[
hls_label_18:6  store i64 %p_cross_mul_digits_da_4, i64* %cross_mul_digits_dat_2, align 8

]]></Node>
<StgValue><ssdm name="store_ln309"/></StgValue>
</operation>

<operation id="191" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="179" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_18:7  %empty_52 = call i32 (...)* @_ssdm_op_SpecRegionEnd([13 x i8]* @p_str38, i32 %tmp_4_i)

]]></Node>
<StgValue><ssdm name="empty_52"/></StgValue>
</operation>

<operation id="192" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln306" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="180" bw="0" op_0_bw="0">
<![CDATA[
hls_label_18:8  br label %6

]]></Node>
<StgValue><ssdm name="br_ln306"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="193" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="182" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
karastuba_mul_MUL_st.1.exit:0  %p_cross_mul_tmp_bits_s = load i32* %p_cross_mul_tmp_bits, align 8

]]></Node>
<StgValue><ssdm name="p_cross_mul_tmp_bits_s"/></StgValue>
</operation>

<operation id="194" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="183" bw="160" op_0_bw="160" op_1_bw="32">
<![CDATA[
karastuba_mul_MUL_st.1.exit:1  %mrv_i = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %p_z0_tmp_bits_load, 0

]]></Node>
<StgValue><ssdm name="mrv_i"/></StgValue>
</operation>

<operation id="195" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="184" bw="160" op_0_bw="160" op_1_bw="32">
<![CDATA[
karastuba_mul_MUL_st.1.exit:2  %mrv_1_i = insertvalue { i32, i32, i32, i32, i32 } %mrv_i, i32 %p_z2_tmp_bits_load, 1

]]></Node>
<StgValue><ssdm name="mrv_1_i"/></StgValue>
</operation>

<operation id="196" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="185" bw="160" op_0_bw="160" op_1_bw="32">
<![CDATA[
karastuba_mul_MUL_st.1.exit:3  %mrv_2_i = insertvalue { i32, i32, i32, i32, i32 } %mrv_1_i, i32 %p_cross_mul_tmp_bits_s, 2

]]></Node>
<StgValue><ssdm name="mrv_2_i"/></StgValue>
</operation>

<operation id="197" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="186" bw="160" op_0_bw="160" op_1_bw="32">
<![CDATA[
karastuba_mul_MUL_st.1.exit:4  %mrv_3_i = insertvalue { i32, i32, i32, i32, i32 } %mrv_2_i, i32 %p_read_cast_i, 3

]]></Node>
<StgValue><ssdm name="mrv_3_i"/></StgValue>
</operation>

<operation id="198" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="187" bw="160" op_0_bw="160" op_1_bw="32">
<![CDATA[
karastuba_mul_MUL_st.1.exit:5  %mrv_4_i = insertvalue { i32, i32, i32, i32, i32 } %mrv_3_i, i32 %p_read1_cast_i, 4

]]></Node>
<StgValue><ssdm name="mrv_4_i"/></StgValue>
</operation>

<operation id="199" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="188" bw="0" op_0_bw="160">
<![CDATA[
karastuba_mul_MUL_st.1.exit:6  ret { i32, i32, i32, i32, i32 } %mrv_4_i

]]></Node>
<StgValue><ssdm name="ret_ln390"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
