<stg><name>Loop_Border_proc</name>


<trans_list>

<trans id="99" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="100" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="101" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="102" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="127" from="5" to="10">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="128" from="5" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="123" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="124" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="125" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="126" from="9" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="32" op_0_bw="32">
<![CDATA[
entry:0  %r_edge_pix = alloca i32

]]></Node>
<StgValue><ssdm name="r_edge_pix"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="32" op_0_bw="32">
<![CDATA[
entry:1  %pix_out = alloca i32

]]></Node>
<StgValue><ssdm name="pix_out"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="32" op_0_bw="32">
<![CDATA[
entry:2  %pix_out_1 = alloca i32

]]></Node>
<StgValue><ssdm name="pix_out_1"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="32" op_0_bw="64">
<![CDATA[
entry:5  %borderbuf = alloca [1910 x i32], align 16

]]></Node>
<StgValue><ssdm name="borderbuf"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:9  %width_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %width)

]]></Node>
<StgValue><ssdm name="width_read"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:10  %height_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %height)

]]></Node>
<StgValue><ssdm name="height_read"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:11  %vconv_xlim_loc_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %vconv_xlim_loc)

]]></Node>
<StgValue><ssdm name="vconv_xlim_loc_read"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="18" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="64" op_0_bw="32">
<![CDATA[
entry:15  %cast = zext i32 %height_read to i64

]]></Node>
<StgValue><ssdm name="cast"/></StgValue>
</operation>

<operation id="19" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="64" op_0_bw="32">
<![CDATA[
entry:16  %cast1 = zext i32 %width_read to i64

]]></Node>
<StgValue><ssdm name="cast1"/></StgValue>
</operation>

<operation id="20" st_id="2" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:17  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="21" st_id="3" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:17  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="22" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:3  call void (...)* @_ssdm_op_SpecInterface(i32* %dst_V, [5 x i8]* @p_str5, i32 1, i32 1, [5 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="23" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:4  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="24" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:6  call void (...)* @_ssdm_op_SpecInterface(i32* %height, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="25" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:7  call void (...)* @_ssdm_op_SpecInterface(i32* %width, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="26" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:8  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_xlim_loc, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="27" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:12  %add_ln217 = add nsw i32 %width_read, -11

]]></Node>
<StgValue><ssdm name="add_ln217"/></StgValue>
</operation>

<operation id="28" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:13  %add_ln224 = add nsw i32 %width_read, -6

]]></Node>
<StgValue><ssdm name="add_ln224"/></StgValue>
</operation>

<operation id="29" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:14  %add_ln207 = add nsw i32 %height_read, -5

]]></Node>
<StgValue><ssdm name="add_ln207"/></StgValue>
</operation>

<operation id="30" st_id="4" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:17  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>

<operation id="31" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="0" op_0_bw="0">
<![CDATA[
entry:18  br label %0

]]></Node>
<StgValue><ssdm name="br_ln203"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="32" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:0  %indvar_flatten = phi i64 [ 0, %entry ], [ %add_ln203, %hls_label_0_end ]

]]></Node>
<StgValue><ssdm name="indvar_flatten"/></StgValue>
</operation>

<operation id="33" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:1  %i6_0_i_i_i = phi i11 [ 0, %entry ], [ %select_ln203_2, %hls_label_0_end ]

]]></Node>
<StgValue><ssdm name="i6_0_i_i_i"/></StgValue>
</operation>

<operation id="34" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:2  %j_0_i_i_i = phi i11 [ 0, %entry ], [ %j, %hls_label_0_end ]

]]></Node>
<StgValue><ssdm name="j_0_i_i_i"/></StgValue>
</operation>

<operation id="35" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="32" op_0_bw="11">
<![CDATA[
:3  %zext_ln203_1 = zext i11 %i6_0_i_i_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln203_1"/></StgValue>
</operation>

<operation id="36" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
:4  %icmp_ln207 = icmp eq i11 %i6_0_i_i_i, 0

]]></Node>
<StgValue><ssdm name="icmp_ln207"/></StgValue>
</operation>

<operation id="37" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
:5  %icmp_ln207_1 = icmp ugt i11 %i6_0_i_i_i, 5

]]></Node>
<StgValue><ssdm name="icmp_ln207_1"/></StgValue>
</operation>

<operation id="38" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:6  %icmp_ln207_2 = icmp slt i32 %zext_ln203_1, %add_ln207

]]></Node>
<StgValue><ssdm name="icmp_ln207_2"/></StgValue>
</operation>

<operation id="39" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:7  %and_ln207 = and i1 %icmp_ln207_2, %icmp_ln207_1

]]></Node>
<StgValue><ssdm name="and_ln207"/></StgValue>
</operation>

<operation id="40" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:8  %or_ln207 = or i1 %icmp_ln207, %and_ln207

]]></Node>
<StgValue><ssdm name="or_ln207"/></StgValue>
</operation>

<operation id="41" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="32" op_0_bw="11">
<![CDATA[
:9  %zext_ln204 = zext i11 %j_0_i_i_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln204"/></StgValue>
</operation>

<operation id="42" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:10  %icmp_ln204 = icmp slt i32 %zext_ln204, %width_read

]]></Node>
<StgValue><ssdm name="icmp_ln204"/></StgValue>
</operation>

<operation id="43" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:11  %icmp_ln203 = icmp eq i64 %indvar_flatten, %bound

]]></Node>
<StgValue><ssdm name="icmp_ln203"/></StgValue>
</operation>

<operation id="44" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
:12  %add_ln203 = add i64 %indvar_flatten, 1

]]></Node>
<StgValue><ssdm name="add_ln203"/></StgValue>
</operation>

<operation id="45" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:13  br i1 %icmp_ln203, label %.exit, label %hls_label_0_begin

]]></Node>
<StgValue><ssdm name="br_ln203"/></StgValue>
</operation>

<operation id="46" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_begin:0  %add_ln203_1 = add i11 %i6_0_i_i_i, 1

]]></Node>
<StgValue><ssdm name="add_ln203_1"/></StgValue>
</operation>

<operation id="47" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="32" op_0_bw="11">
<![CDATA[
hls_label_0_begin:1  %zext_ln203 = zext i11 %add_ln203_1 to i32

]]></Node>
<StgValue><ssdm name="zext_ln203"/></StgValue>
</operation>

<operation id="48" st_id="5" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
hls_label_0_begin:4  %select_ln203 = select i1 %icmp_ln204, i11 %j_0_i_i_i, i11 0

]]></Node>
<StgValue><ssdm name="select_ln203"/></StgValue>
</operation>

<operation id="49" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_begin:5  %icmp_ln207_3 = icmp eq i11 %add_ln203_1, 0

]]></Node>
<StgValue><ssdm name="icmp_ln207_3"/></StgValue>
</operation>

<operation id="50" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_begin:6  %icmp_ln207_4 = icmp ugt i11 %add_ln203_1, 5

]]></Node>
<StgValue><ssdm name="icmp_ln207_4"/></StgValue>
</operation>

<operation id="51" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
hls_label_0_begin:7  %icmp_ln207_5 = icmp slt i32 %zext_ln203, %add_ln207

]]></Node>
<StgValue><ssdm name="icmp_ln207_5"/></StgValue>
</operation>

<operation id="52" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
hls_label_0_begin:8  %and_ln207_1 = and i1 %icmp_ln207_5, %icmp_ln207_4

]]></Node>
<StgValue><ssdm name="and_ln207_1"/></StgValue>
</operation>

<operation id="53" st_id="5" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
hls_label_0_begin:9  %or_ln207_1 = or i1 %icmp_ln207_3, %and_ln207_1

]]></Node>
<StgValue><ssdm name="or_ln207_1"/></StgValue>
</operation>

<operation id="54" st_id="5" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="1" op_0_bw="1" op_1_bw="1" op_2_bw="1">
<![CDATA[
hls_label_0_begin:10  %select_ln203_1 = select i1 %icmp_ln204, i1 %or_ln207, i1 %or_ln207_1

]]></Node>
<StgValue><ssdm name="select_ln203_1"/></StgValue>
</operation>

<operation id="55" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="32" op_0_bw="11">
<![CDATA[
hls_label_0_begin:11  %zext_ln203_2 = zext i11 %select_ln203 to i32

]]></Node>
<StgValue><ssdm name="zext_ln203_2"/></StgValue>
</operation>

<operation id="56" st_id="5" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
hls_label_0_begin:12  %select_ln203_2 = select i1 %icmp_ln204, i11 %i6_0_i_i_i, i11 %add_ln203_1

]]></Node>
<StgValue><ssdm name="select_ln203_2"/></StgValue>
</operation>

<operation id="57" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
hls_label_0_begin:15  br i1 %select_ln203_1, label %._crit_edge6.i.i.i, label %hls_label_0_end

]]></Node>
<StgValue><ssdm name="br_ln207"/></StgValue>
</operation>

<operation id="58" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
<literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge6.i.i.i:0  %icmp_ln210 = icmp slt i32 %zext_ln203_2, %vconv_xlim_loc_read

]]></Node>
<StgValue><ssdm name="icmp_ln210"/></StgValue>
</operation>

<operation id="59" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
<literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge6.i.i.i:1  br i1 %icmp_ln210, label %1, label %._crit_edge9.i.i.i

]]></Node>
<StgValue><ssdm name="br_ln210"/></StgValue>
</operation>

<operation id="60" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
<literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge9.i.i.i:5  %icmp_ln217 = icmp eq i32 %zext_ln203_2, %add_ln217

]]></Node>
<StgValue><ssdm name="icmp_ln217"/></StgValue>
</operation>

<operation id="61" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
hls_label_0_end:3  %icmp_ln224 = icmp slt i32 %zext_ln203_2, %add_ln224

]]></Node>
<StgValue><ssdm name="icmp_ln224"/></StgValue>
</operation>

<operation id="62" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_end:14  %j = add i11 %select_ln203, 1

]]></Node>
<StgValue><ssdm name="j"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="63" st_id="6" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %tmp = call i32 @_ssdm_op_Read.ap_fifo.volatile.i32P(i32* %vconv_V)

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="64" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  store i32 %tmp, i32* %r_edge_pix

]]></Node>
<StgValue><ssdm name="store_ln213"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="65" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="64" op_0_bw="11">
<![CDATA[
:1  %zext_ln212 = zext i11 %select_ln203 to i64

]]></Node>
<StgValue><ssdm name="zext_ln212"/></StgValue>
</operation>

<operation id="66" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
:2  %borderbuf_addr = getelementptr inbounds [1910 x i32]* %borderbuf, i64 0, i64 %zext_ln212

]]></Node>
<StgValue><ssdm name="borderbuf_addr"/></StgValue>
</operation>

<operation id="67" st_id="7" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
:3  store i32 %tmp, i32* %borderbuf_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln212"/></StgValue>
</operation>

<operation id="68" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
._crit_edge9.i.i.i:0  %l_edge_pix_2 = load i32* %r_edge_pix

]]></Node>
<StgValue><ssdm name="l_edge_pix_2"/></StgValue>
</operation>

<operation id="69" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln217" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="32" op_0_bw="32">
<![CDATA[
._crit_edge9.i.i.i:1  %pix_out_load = load i32* %pix_out

]]></Node>
<StgValue><ssdm name="pix_out_load"/></StgValue>
</operation>

<operation id="70" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="32">
<![CDATA[
._crit_edge9.i.i.i:2  %pix_out_1_load = load i32* %pix_out_1

]]></Node>
<StgValue><ssdm name="pix_out_1_load"/></StgValue>
</operation>

<operation id="71" st_id="7" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge9.i.i.i:3  %icmp_ln214 = icmp eq i11 %select_ln203, 0

]]></Node>
<StgValue><ssdm name="icmp_ln214"/></StgValue>
</operation>

<operation id="72" st_id="7" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
._crit_edge9.i.i.i:4  %select_ln214 = select i1 %icmp_ln214, i32 %l_edge_pix_2, i32 %pix_out_1_load

]]></Node>
<StgValue><ssdm name="select_ln214"/></StgValue>
</operation>

<operation id="73" st_id="7" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
._crit_edge9.i.i.i:6  %l_edge_pix = select i1 %icmp_ln217, i32 %l_edge_pix_2, i32 %pix_out_load

]]></Node>
<StgValue><ssdm name="l_edge_pix"/></StgValue>
</operation>

<operation id="74" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
._crit_edge9.i.i.i:7  store i32 %select_ln214, i32* %pix_out_1

]]></Node>
<StgValue><ssdm name="store_ln220"/></StgValue>
</operation>

<operation id="75" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
._crit_edge9.i.i.i:8  store i32 %l_edge_pix, i32* %pix_out

]]></Node>
<StgValue><ssdm name="store_ln220"/></StgValue>
</operation>

<operation id="76" st_id="7" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_end:4  %add_ln227 = add i11 %select_ln203, -5

]]></Node>
<StgValue><ssdm name="add_ln227"/></StgValue>
</operation>

<operation id="77" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="64" op_0_bw="11">
<![CDATA[
hls_label_0_end:5  %zext_ln227 = zext i11 %add_ln227 to i64

]]></Node>
<StgValue><ssdm name="zext_ln227"/></StgValue>
</operation>

<operation id="78" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
hls_label_0_end:6  %borderbuf_addr_1 = getelementptr inbounds [1910 x i32]* %borderbuf, i64 0, i64 %zext_ln227

]]></Node>
<StgValue><ssdm name="borderbuf_addr_1"/></StgValue>
</operation>

<operation id="79" st_id="7" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="32" op_0_bw="11">
<![CDATA[
hls_label_0_end:7  %pix_out_7 = load i32* %borderbuf_addr_1, align 4

]]></Node>
<StgValue><ssdm name="pix_out_7"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="80" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_0_end:0  %pix_out_4 = load i32* %pix_out

]]></Node>
<StgValue><ssdm name="pix_out_4"/></StgValue>
</operation>

<operation id="81" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_0_end:1  %pix_out_6 = load i32* %pix_out_1

]]></Node>
<StgValue><ssdm name="pix_out_6"/></StgValue>
</operation>

<operation id="82" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
hls_label_0_end:2  %icmp_ln222 = icmp ult i11 %select_ln203, 6

]]></Node>
<StgValue><ssdm name="icmp_ln222"/></StgValue>
</operation>

<operation id="83" st_id="8" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="32" op_0_bw="11">
<![CDATA[
hls_label_0_end:7  %pix_out_7 = load i32* %borderbuf_addr_1, align 4

]]></Node>
<StgValue><ssdm name="pix_out_7"/></StgValue>
</operation>

<operation id="84" st_id="8" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
hls_label_0_end:8  %xor_ln222 = xor i1 %icmp_ln222, true

]]></Node>
<StgValue><ssdm name="xor_ln222"/></StgValue>
</operation>

<operation id="85" st_id="8" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
hls_label_0_end:9  %and_ln224 = and i1 %icmp_ln224, %xor_ln222

]]></Node>
<StgValue><ssdm name="and_ln224"/></StgValue>
</operation>

<operation id="86" st_id="8" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
hls_label_0_end:10  %pix_out_8 = select i1 %and_ln224, i32 %pix_out_7, i32 %pix_out_4

]]></Node>
<StgValue><ssdm name="pix_out_8"/></StgValue>
</operation>

<operation id="87" st_id="8" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
hls_label_0_end:11  %pix_out_10 = select i1 %icmp_ln222, i32 %pix_out_6, i32 %pix_out_8

]]></Node>
<StgValue><ssdm name="pix_out_10"/></StgValue>
</operation>

<operation id="88" st_id="8" stage="2" lat="2">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
hls_label_0_end:12  call void @_ssdm_op_Write.axis.volatile.i32P(i32* %dst_V, i32 %pix_out_10)

]]></Node>
<StgValue><ssdm name="write_ln229"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="89" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
hls_label_0_begin:2  call void (...)* @_ssdm_op_SpecLoopName([9 x i8]* @Border_L_str)

]]></Node>
<StgValue><ssdm name="specloopname_ln0"/></StgValue>
</operation>

<operation id="90" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
hls_label_0_begin:3  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 2070601, i64 0)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="91" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
hls_label_0_begin:13  %tmp_18_i_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str21)

]]></Node>
<StgValue><ssdm name="tmp_18_i_i"/></StgValue>
</operation>

<operation id="92" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
hls_label_0_begin:14  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln206"/></StgValue>
</operation>

<operation id="93" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
<literal name="icmp_ln210" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="0" op_0_bw="0">
<![CDATA[
:5  br label %._crit_edge9.i.i.i

]]></Node>
<StgValue><ssdm name="br_ln213"/></StgValue>
</operation>

<operation id="94" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="select_ln203_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge9.i.i.i:9  br label %hls_label_0_end

]]></Node>
<StgValue><ssdm name="br_ln220"/></StgValue>
</operation>

<operation id="95" st_id="9" stage="1" lat="2">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
hls_label_0_end:12  call void @_ssdm_op_Write.axis.volatile.i32P(i32* %dst_V, i32 %pix_out_10)

]]></Node>
<StgValue><ssdm name="write_ln229"/></StgValue>
</operation>

<operation id="96" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
hls_label_0_end:13  %empty_19 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str21, i32 %tmp_18_i_i)

]]></Node>
<StgValue><ssdm name="empty_19"/></StgValue>
</operation>

<operation id="97" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln203" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="0" op_0_bw="0">
<![CDATA[
hls_label_0_end:15  br label %0

]]></Node>
<StgValue><ssdm name="br_ln204"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="98" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="0">
<![CDATA[
.exit:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
