<stg><name>sample_iterator_next</name>


<trans_list>

<trans id="50" from="1" to="2">
<condition id="11">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="51" from="2" to="3">
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="52" from="3" to="4">
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="53" from="4" to="5">
<condition id="14">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="54" from="5" to="6">
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="55" from="6" to="7">
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="56" from="7" to="8">
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="9" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="12" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:6  %i_sample_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %i_sample)

]]></node>
<StgValue><ssdm name="i_sample_read"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="13" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  %i_index_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %i_index)

]]></node>
<StgValue><ssdm name="i_index_read"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="15" bw="32" op_0_bw="16">
<![CDATA[
:9  %tmp_8 = zext i16 %i_index_read to i32

]]></node>
<StgValue><ssdm name="tmp_8"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="16" bw="16" op_0_bw="16" op_1_bw="32">
<![CDATA[
:10  %indices_samples_addr = getelementptr i16* %indices_samples, i32 %tmp_8

]]></node>
<StgValue><ssdm name="indices_samples_addr"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="17" bw="1" op_0_bw="1" op_1_bw="16" op_2_bw="32">
<![CDATA[
:11  %indices_samples_load_req = call i1 @_ssdm_op_ReadReq.ap_bus.i16P(i16* %indices_samples_addr, i32 1)

]]></node>
<StgValue><ssdm name="indices_samples_load_req"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="14" st_id="2" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="18" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:12  %indices_samples_addr_read = call i16 @_ssdm_op_Read.ap_bus.i16P(i16* %indices_samples_addr)

]]></node>
<StgValue><ssdm name="indices_samples_addr_read"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="15" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="19" bw="17" op_0_bw="16">
<![CDATA[
:13  %tmp_9_cast = zext i16 %indices_samples_addr_read to i17

]]></node>
<StgValue><ssdm name="tmp_9_cast"/></StgValue>
</operation>

<operation id="16" st_id="3" stage="4" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="17" op_0_bw="17" op_1_bw="17">
<![CDATA[
:14  %tmp_s = add i17 %tmp_9_cast, -1

]]></node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="17" st_id="4" stage="3" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="17" op_0_bw="17" op_1_bw="17">
<![CDATA[
:14  %tmp_s = add i17 %tmp_9_cast, -1

]]></node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="18" st_id="4" stage="4" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:17  %tmp_3 = add i16 %i_index_read, 1

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="19" st_id="4" stage="4" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:18  %tmp_2 = add i16 %i_sample_read, 1

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="20" st_id="5" stage="2" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="17" op_0_bw="17" op_1_bw="17">
<![CDATA[
:14  %tmp_s = add i17 %tmp_9_cast, -1

]]></node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="21" st_id="5" stage="3" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:17  %tmp_3 = add i16 %i_index_read, 1

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="22" st_id="5" stage="3" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:18  %tmp_2 = add i16 %i_sample_read, 1

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="23" st_id="6" stage="1" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="17" op_0_bw="17" op_1_bw="17">
<![CDATA[
:14  %tmp_s = add i17 %tmp_9_cast, -1

]]></node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="24" st_id="6" stage="2" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:17  %tmp_3 = add i16 %i_index_read, 1

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="25" st_id="6" stage="2" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:18  %tmp_2 = add i16 %i_sample_read, 1

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="26" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="14" bw="18" op_0_bw="16">
<![CDATA[
:8  %tmp_cast = zext i16 %i_sample_read to i18

]]></node>
<StgValue><ssdm name="tmp_cast"/></StgValue>
</operation>

<operation id="27" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="21" bw="18" op_0_bw="17">
<![CDATA[
:15  %tmp_cast_14 = sext i17 %tmp_s to i18

]]></node>
<StgValue><ssdm name="tmp_cast_14"/></StgValue>
</operation>

<operation id="28" st_id="7" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="22" bw="1" op_0_bw="18" op_1_bw="18">
<![CDATA[
:16  %tmp_1 = icmp slt i18 %tmp_cast, %tmp_cast_14

]]></node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="29" st_id="7" stage="1" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:17  %tmp_3 = add i16 %i_index_read, 1

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="30" st_id="7" stage="1" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:18  %tmp_2 = add i16 %i_sample_read, 1

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="31" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="6" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:0  call void (...)* @_ssdm_op_SpecIFCore(i8* %indices_stride, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="32" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="7" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecIFCore(i32* %indices_begin, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="33" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="8" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecBus(i8* %indices_stride, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="34" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecBus(i32* %indices_begin, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="35" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="10" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:4  call void (...)* @_ssdm_op_SpecIFCore(i16* %indices_samples, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="36" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="11" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:5  call void (...)* @_ssdm_op_SpecBus(i16* %indices_samples, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="37" st_id="8" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="25" bw="16" op_0_bw="1" op_1_bw="16" op_2_bw="16">
<![CDATA[
:19  %agg_result_sample_write_assign = select i1 %tmp_1, i16 %tmp_2, i16 0

]]></node>
<StgValue><ssdm name="agg_result_sample_write_assign"/></StgValue>
</operation>

<operation id="38" st_id="8" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="26" bw="16" op_0_bw="1" op_1_bw="16" op_2_bw="16">
<![CDATA[
:20  %agg_result_index_write_assign = select i1 %tmp_1, i16 %i_index_read, i16 %tmp_3

]]></node>
<StgValue><ssdm name="agg_result_index_write_assign"/></StgValue>
</operation>

<operation id="39" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="32" op_0_bw="32" op_1_bw="16">
<![CDATA[
:21  %mrv = insertvalue { i16, i16 } undef, i16 %agg_result_index_write_assign, 0

]]></node>
<StgValue><ssdm name="mrv"/></StgValue>
</operation>

<operation id="40" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="28" bw="32" op_0_bw="32" op_1_bw="16">
<![CDATA[
:22  %mrv_1 = insertvalue { i16, i16 } %mrv, i16 %agg_result_sample_write_assign, 1

]]></node>
<StgValue><ssdm name="mrv_1"/></StgValue>
</operation>

<operation id="41" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="0" op_0_bw="32">
<![CDATA[
:23  ret { i16, i16 } %mrv_1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
