<stg><name>nfa_get_finals.1</name>


<trans_list>

<trans id="19" from="1" to="2">
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="20" from="2" to="3">
<condition id="4">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="21" from="3" to="4">
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="5" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="4" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:0  %tmp_28_read = call i5 @_ssdm_op_Read.ap_auto.i5(i5 %tmp_28)

]]></node>
<StgValue><ssdm name="tmp_28_read"/></StgValue>
</operation>

<operation id="6" st_id="1" stage="2" lat="2">
<core>PLB46M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="1" op_0_bw="1" op_1_bw="64" op_2_bw="32">
<![CDATA[
:5  %nfa_finals_buckets_load_req = call i1 @_ssdm_op_ReadReq.ap_bus.i64P(i64* %nfa_finals_buckets, i32 1)

]]></node>
<StgValue><ssdm name="nfa_finals_buckets_load_req"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="7" st_id="2" stage="1" lat="2">
<core>PLB46M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="1" op_0_bw="1" op_1_bw="64" op_2_bw="32">
<![CDATA[
:5  %nfa_finals_buckets_load_req = call i1 @_ssdm_op_ReadReq.ap_bus.i64P(i64* %nfa_finals_buckets, i32 1)

]]></node>
<StgValue><ssdm name="nfa_finals_buckets_load_req"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="8" st_id="3" stage="1" lat="1">
<core>PLB46M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="10" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
:6  %nfa_finals_buckets_read = call i64 @_ssdm_op_Read.ap_bus.i64P(i64* %nfa_finals_buckets)

]]></node>
<StgValue><ssdm name="nfa_finals_buckets_read"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="9" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="5" bw="64" op_0_bw="5">
<![CDATA[
:1  %tmp_28_cast = zext i5 %tmp_28_read to i64

]]></node>
<StgValue><ssdm name="tmp_28_cast"/></StgValue>
</operation>

<operation id="10" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="6" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecIFCore(i64* %nfa_finals_buckets, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="11" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="7" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecBus(i64* %nfa_finals_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="12" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="8" bw="4" op_0_bw="64" op_1_bw="64" op_2_bw="64">
<![CDATA[
:4  %finals_buckets_addr = getelementptr [16 x i64]* %finals_buckets, i64 0, i64 %tmp_28_cast

]]></node>
<StgValue><ssdm name="finals_buckets_addr"/></StgValue>
</operation>

<operation id="13" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="11" bw="0" op_0_bw="64" op_1_bw="4">
<![CDATA[
:7  store i64 %nfa_finals_buckets_read, i64* %finals_buckets_addr, align 8

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="14" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="12" bw="0">
<![CDATA[
:8  ret void

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
