<stg><name>filter11x11_strm</name>


<trans_list>

<trans id="62" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="63" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="64" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="65" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="66" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="67" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="68" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="9" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
codeRepl:0  %height_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %height)

]]></Node>
<StgValue><ssdm name="height_read"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
codeRepl:1  %width_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %width)

]]></Node>
<StgValue><ssdm name="width_read"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:2  %vconv_xlim_loc_c65 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="vconv_xlim_loc_c65"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:3  %height_c64 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="height_c64"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:4  %vconv_xlim_loc_c = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="vconv_xlim_loc_c"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:5  %height_c63 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="height_c63"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:6  %width_c62 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="width_c62"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:7  %height_c61 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="height_c61"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:8  %height_c = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="height_c"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:9  %width_c60 = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="width_c60"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:10  %width_c = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="width_c"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:16  %hconv_V = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="hconv_V"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="32" op_0_bw="64">
<![CDATA[
codeRepl:19  %vconv_V = alloca i32, align 4

]]></Node>
<StgValue><ssdm name="vconv_V"/></StgValue>
</operation>

<operation id="22" st_id="1" stage="1" lat="1">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32">
<![CDATA[
codeRepl:33  call fastcc void @filter11x11_strm.ent(i32 %width_read, i32 %height_read, i32* %width_c, i32* %width_c60, i32* %height_c, i32* %height_c61)

]]></Node>
<StgValue><ssdm name="call_ln263"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="23" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="56" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
codeRepl:40  call fastcc void @Block__proc(i32* nocapture %width_c, i32* nocapture %height_c, i32* %width_c62, i32* %height_c63, i32* %vconv_xlim_loc_c)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="57" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
codeRepl:41  call fastcc void @Loop_HConvH_proc6(i32* nocapture %height_c61, i32* nocapture %width_c60, i32* %src_V, i32* %hconv_V)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="25" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="56" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
codeRepl:40  call fastcc void @Block__proc(i32* nocapture %width_c, i32* nocapture %height_c, i32* %width_c62, i32* %height_c63, i32* %vconv_xlim_loc_c)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>

<operation id="26" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="57" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
codeRepl:41  call fastcc void @Loop_HConvH_proc6(i32* nocapture %height_c61, i32* nocapture %width_c60, i32* %src_V, i32* %hconv_V)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="27" st_id="4" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="62" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32" op_9_bw="32" op_10_bw="32" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="32" op_16_bw="32" op_17_bw="10" op_18_bw="0" op_19_bw="0" op_20_bw="0">
<![CDATA[
codeRepl:46  call fastcc void @Loop_VConvH_proc(i32* nocapture %height_c63, i32* nocapture %vconv_xlim_loc_c, i32* %hconv_V, i32* %vconv_V, i32* %height_c64, i32* %vconv_xlim_loc_c65)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="28" st_id="5" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="62" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32" op_9_bw="32" op_10_bw="32" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="32" op_16_bw="32" op_17_bw="10" op_18_bw="0" op_19_bw="0" op_20_bw="0">
<![CDATA[
codeRepl:46  call fastcc void @Loop_VConvH_proc(i32* nocapture %height_c63, i32* nocapture %vconv_xlim_loc_c, i32* %hconv_V, i32* %vconv_V, i32* %height_c64, i32* %vconv_xlim_loc_c65)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="29" st_id="6" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="63" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
codeRepl:47  call fastcc void @Loop_Border_proc(i32* nocapture %width_c62, i32* nocapture %height_c64, i32* %dst_V, i32* nocapture %vconv_xlim_loc_c65, i32* %vconv_V)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="30" st_id="7" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="63" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
codeRepl:47  call fastcc void @Loop_Border_proc(i32* nocapture %width_c62, i32* nocapture %height_c64, i32* %dst_V, i32* nocapture %vconv_xlim_loc_c65, i32* %vconv_V)

]]></Node>
<StgValue><ssdm name="call_ln143"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="31" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="0">
<![CDATA[
codeRepl:11  call void (...)* @_ssdm_op_SpecDataflowPipeline(i32 -1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specdataflowpipeline_ln263"/></StgValue>
</operation>

<operation id="32" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
codeRepl:12  call void (...)* @_ssdm_op_SpecBitsMap(i32 %width), !map !43

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="33" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
codeRepl:13  call void (...)* @_ssdm_op_SpecBitsMap(i32 %height), !map !49

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="34" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
codeRepl:14  call void (...)* @_ssdm_op_SpecBitsMap(i32* %src_V), !map !53

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="35" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
codeRepl:15  call void (...)* @_ssdm_op_SpecBitsMap(i32* %dst_V), !map !59

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="36" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:17  %empty = call i32 (...)* @_ssdm_op_SpecChannel([8 x i8]* @hconv_OC_V_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32* %hconv_V, i32* %hconv_V)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="37" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:18  call void (...)* @_ssdm_op_SpecInterface(i32* %hconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="38" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:20  %empty_4 = call i32 (...)* @_ssdm_op_SpecChannel([8 x i8]* @vconv_OC_V_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32* %vconv_V, i32* %vconv_V)

]]></Node>
<StgValue><ssdm name="empty_4"/></StgValue>
</operation>

<operation id="39" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:21  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="40" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
codeRepl:22  call void (...)* @_ssdm_op_SpecTopModule([17 x i8]* @filter11x11_strm_str) nounwind

]]></Node>
<StgValue><ssdm name="spectopmodule_ln0"/></StgValue>
</operation>

<operation id="41" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:23  call void (...)* @_ssdm_op_SpecInterface(i32* %src_V, [5 x i8]* @p_str5, i32 1, i32 1, [5 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specinterface_ln260"/></StgValue>
</operation>

<operation id="42" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:24  call void (...)* @_ssdm_op_SpecInterface(i32* %dst_V, [5 x i8]* @p_str5, i32 1, i32 1, [5 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specinterface_ln261"/></StgValue>
</operation>

<operation id="43" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:25  %empty_5 = call i32 (...)* @_ssdm_op_SpecChannel([8 x i8]* @width_c_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %width_c, i32* %width_c)

]]></Node>
<StgValue><ssdm name="empty_5"/></StgValue>
</operation>

<operation id="44" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:26  call void (...)* @_ssdm_op_SpecInterface(i32* %width_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="45" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:27  %empty_6 = call i32 (...)* @_ssdm_op_SpecChannel([10 x i8]* @width_c60_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %width_c60, i32* %width_c60)

]]></Node>
<StgValue><ssdm name="empty_6"/></StgValue>
</operation>

<operation id="46" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:28  call void (...)* @_ssdm_op_SpecInterface(i32* %width_c60, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="47" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:29  %empty_7 = call i32 (...)* @_ssdm_op_SpecChannel([9 x i8]* @height_c_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %height_c, i32* %height_c)

]]></Node>
<StgValue><ssdm name="empty_7"/></StgValue>
</operation>

<operation id="48" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:30  call void (...)* @_ssdm_op_SpecInterface(i32* %height_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="49" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:31  %empty_8 = call i32 (...)* @_ssdm_op_SpecChannel([11 x i8]* @height_c61_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %height_c61, i32* %height_c61)

]]></Node>
<StgValue><ssdm name="empty_8"/></StgValue>
</operation>

<operation id="50" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:32  call void (...)* @_ssdm_op_SpecInterface(i32* %height_c61, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="51" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:34  %empty_9 = call i32 (...)* @_ssdm_op_SpecChannel([10 x i8]* @width_c62_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 3, i32 0, i32* %width_c62, i32* %width_c62)

]]></Node>
<StgValue><ssdm name="empty_9"/></StgValue>
</operation>

<operation id="52" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:35  call void (...)* @_ssdm_op_SpecInterface(i32* %width_c62, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="53" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:36  %empty_10 = call i32 (...)* @_ssdm_op_SpecChannel([11 x i8]* @height_c63_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %height_c63, i32* %height_c63)

]]></Node>
<StgValue><ssdm name="empty_10"/></StgValue>
</operation>

<operation id="54" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:37  call void (...)* @_ssdm_op_SpecInterface(i32* %height_c63, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="55" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:38  %empty_11 = call i32 (...)* @_ssdm_op_SpecChannel([17 x i8]* @vconv_xlim_OC_loc_c_s, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %vconv_xlim_loc_c, i32* %vconv_xlim_loc_c)

]]></Node>
<StgValue><ssdm name="empty_11"/></StgValue>
</operation>

<operation id="56" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:39  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_xlim_loc_c, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="57" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="58" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:42  %empty_12 = call i32 (...)* @_ssdm_op_SpecChannel([11 x i8]* @height_c64_str, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %height_c64, i32* %height_c64)

]]></Node>
<StgValue><ssdm name="empty_12"/></StgValue>
</operation>

<operation id="58" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:43  call void (...)* @_ssdm_op_SpecInterface(i32* %height_c64, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln143"/></StgValue>
</operation>

<operation id="59" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="60" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
codeRepl:44  %empty_13 = call i32 (...)* @_ssdm_op_SpecChannel([19 x i8]* @vconv_xlim_OC_loc_c6, i32 1, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 0, i32* %vconv_xlim_loc_c65, i32* %vconv_xlim_loc_c65)

]]></Node>
<StgValue><ssdm name="empty_13"/></StgValue>
</operation>

<operation id="60" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="61" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
codeRepl:45  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_xlim_loc_c65, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="61" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="64" bw="0">
<![CDATA[
codeRepl:48  ret void

]]></Node>
<StgValue><ssdm name="ret_ln273"/></StgValue>
</operation>
</state>
</state_list>


<ports>
<port id="70" name="width" dir="0" iftype="0">
<core>NULL</core><StgValue><ssdm name="width"/></StgValue>
</port>
<port id="71" name="height" dir="0" iftype="0">
<core>NULL</core><StgValue><ssdm name="height"/></StgValue>
</port>
<port id="72" name="src_V" dir="0" iftype="0">
<core>NULL</core><StgValue><ssdm name="src_V"/></StgValue>
</port>
<port id="73" name="dst_V" dir="1" iftype="0">
<core>NULL</core><StgValue><ssdm name="dst_V"/></StgValue>
</port>
<port id="74" name="linebuf_0" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_0"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="75" name="linebuf_1" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_1"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="76" name="linebuf_2" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_2"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="77" name="linebuf_3" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_3"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="78" name="linebuf_4" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_4"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="79" name="linebuf_5" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_5"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="80" name="linebuf_6" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_6"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="81" name="linebuf_7" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_7"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="82" name="linebuf_8" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_8"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="83" name="linebuf_9" dir="2" iftype="1">
<core>RAM</core><StgValue><ssdm name="linebuf_9"/><MemPortTyVec>2 3 </MemPortTyVec>
</StgValue>
</port>
<port id="84" name="filt11_coeff" dir="0" iftype="1">
<core>ROM_nP</core><StgValue><ssdm name="filt11_coeff"/><MemPortTyVec>1 </MemPortTyVec>
</StgValue>
</port>
</ports>


<dataflows>
<dataflow id="86" from="_ssdm_op_Read.ap_auto.i32" to="height_read" fromId="85" toId="9">
</dataflow>
<dataflow id="87" from="height" to="height_read" fromId="71" toId="9">
</dataflow>
<dataflow id="88" from="_ssdm_op_Read.ap_auto.i32" to="width_read" fromId="85" toId="10">
</dataflow>
<dataflow id="89" from="width" to="width_read" fromId="70" toId="10">
</dataflow>
<dataflow id="91" from="StgValue_90" to="vconv_xlim_loc_c65" fromId="90" toId="11">
</dataflow>
<dataflow id="92" from="StgValue_90" to="height_c64" fromId="90" toId="12">
</dataflow>
<dataflow id="93" from="StgValue_90" to="vconv_xlim_loc_c" fromId="90" toId="13">
</dataflow>
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<dataflow id="533" from="StgValue_188" to="specinterface_ln0" fromId="188" toId="60">
</dataflow>
<dataflow id="534" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
<dataflow id="535" from="StgValue_188" to="specinterface_ln0" fromId="188" toId="60">
</dataflow>
<dataflow id="536" from="StgValue_188" to="specinterface_ln0" fromId="188" toId="60">
</dataflow>
<dataflow id="537" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
<dataflow id="538" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
<dataflow id="539" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
<dataflow id="540" from="StgValue_210" to="specinterface_ln0" fromId="210" toId="60">
</dataflow>
<dataflow id="541" from="StgValue_210" to="specinterface_ln0" fromId="210" toId="60">
</dataflow>
<dataflow id="542" from="StgValue_230" to="specinterface_ln0" fromId="230" toId="60">
</dataflow>
<dataflow id="543" from="StgValue_230" to="specinterface_ln0" fromId="230" toId="60">
</dataflow>
<dataflow id="544" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
<dataflow id="545" from="p_str" to="specinterface_ln0" fromId="207" toId="60">
</dataflow>
</dataflows>


</stg>
