<stg><name>rotate_right</name>


<trans_list>

<trans id="13" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="3" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="3" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
entry:0 %n_read = read i5 @_ssdm_op_Read.ap_auto.i5, i5 %n

]]></Node>
<StgValue><ssdm name="n_read"/></StgValue>
</operation>

<operation id="4" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="6" op_0_bw="5">
<![CDATA[
entry:3 %n_cast = zext i5 %n_read

]]></Node>
<StgValue><ssdm name="n_cast"/></StgValue>
</operation>

<operation id="5" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
entry:5 %sub_ln12 = sub i6 32, i6 %n_cast

]]></Node>
<StgValue><ssdm name="sub_ln12"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="6" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="4" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:1 %x_read = read i32 @_ssdm_op_Read.ap_auto.i32, i32 %x

]]></Node>
<StgValue><ssdm name="x_read"/></StgValue>
</operation>

<operation id="7" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="32" op_0_bw="5">
<![CDATA[
entry:2 %n_cast1 = zext i5 %n_read

]]></Node>
<StgValue><ssdm name="n_cast1"/></StgValue>
</operation>

<operation id="8" st_id="2" stage="1" lat="1">
<core>Shifter</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:4 %lshr_ln12 = lshr i32 %x_read, i32 %n_cast1

]]></Node>
<StgValue><ssdm name="lshr_ln12"/></StgValue>
</operation>

<operation id="9" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="32" op_0_bw="6">
<![CDATA[
entry:6 %zext_ln12 = zext i6 %sub_ln12

]]></Node>
<StgValue><ssdm name="zext_ln12"/></StgValue>
</operation>

<operation id="10" st_id="2" stage="1" lat="1">
<core>Shifter</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:7 %shl_ln12 = shl i32 %x_read, i32 %zext_ln12

]]></Node>
<StgValue><ssdm name="shl_ln12"/></StgValue>
</operation>

<operation id="11" st_id="2" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:8 %or_ln12 = or i32 %shl_ln12, i32 %lshr_ln12

]]></Node>
<StgValue><ssdm name="or_ln12"/></StgValue>
</operation>

<operation id="12" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="32">
<![CDATA[
entry:9 %ret_ln12 = ret i32 %or_ln12

]]></Node>
<StgValue><ssdm name="ret_ln12"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
