<stg><name>nfa_accept_samples_generic_hw</name>


<trans_list>

<trans id="130" from="1" to="2">
<condition id="27">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="131" from="2" to="3">
<condition id="29">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="132" from="3" to="7">
<condition id="30">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
</and_exp><and_exp><literal name="finished_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="133" from="3" to="4">
<condition id="32">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
<literal name="finished_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="136" from="4" to="5">
<condition id="34">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="137" from="5" to="6">
<condition id="35">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="138" from="6" to="3">
<condition id="37">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="140" from="7" to="8">
<condition id="41">
<or_exp><and_exp><literal name="brmerge_demorgan" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="141" from="7" to="10">
<condition id="40">
<or_exp><and_exp><literal name="brmerge_demorgan" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="142" from="8" to="9">
<condition id="42">
<or_exp><and_exp><literal name="exitcond" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="145" from="8" to="2">
<condition id="47">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="146" from="8" to="10">
<condition id="49">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="144" from="9" to="8">
<condition id="45">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="17" bw="16" op_0_bw="64">
<![CDATA[
:0  %c = alloca i16, align 2

]]></node>
<StgValue><ssdm name="c"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="18" bw="16" op_0_bw="64">
<![CDATA[
:1  %i_index = alloca i16, align 2

]]></node>
<StgValue><ssdm name="i_index"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="19" bw="16" op_0_bw="64">
<![CDATA[
:2  %i_sample = alloca i16, align 2

]]></node>
<StgValue><ssdm name="i_sample"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="0" op_0_bw="0" op_1_bw="56">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecBitsMap(i56* %indices), !map !0

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="21" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
:4  call void (...)* @_ssdm_op_SpecBitsMap(i64* %nfa_finals_buckets), !map !12

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="22" bw="0" op_0_bw="0" op_1_bw="64">
<![CDATA[
:5  call void (...)* @_ssdm_op_SpecBitsMap(i64* %nfa_initials_buckets), !map !23

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:6  call void (...)* @_ssdm_op_SpecBitsMap(i32* %nfa_forward_buckets), !map !30

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:7  call void (...)* @_ssdm_op_SpecBitsMap([32130 x i32]* %nfa_backward_buckets), !map !37

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="25" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:8  call void (...)* @_ssdm_op_SpecBitsMap(i8* %nfa_symbols), !map !41

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="26" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:9  call void (...)* @_ssdm_op_SpecBitsMap(i8* %sample_buffer), !map !47

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:10  call void (...)* @_ssdm_op_SpecBitsMap(i32 %sample_buffer_length), !map !53

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="22" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="28" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:11  call void (...)* @_ssdm_op_SpecBitsMap(i16 %sample_length), !map !59

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="23" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:12  call void (...)* @_ssdm_op_SpecBitsMap(i16 %i_size), !map !63

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="24" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="30" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:13  call void (...)* @_ssdm_op_SpecBitsMap(i16 %begin_index), !map !67

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="25" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="31" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:14  call void (...)* @_ssdm_op_SpecBitsMap(i16 %begin_sample), !map !71

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="26" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:15  call void (...)* @_ssdm_op_SpecBitsMap(i16 %end_index), !map !75

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="27" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="33" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:16  call void (...)* @_ssdm_op_SpecBitsMap(i16 %end_sample), !map !79

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="28" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="34" bw="0" op_0_bw="0" op_1_bw="1">
<![CDATA[
:17  call void (...)* @_ssdm_op_SpecBitsMap(i1 %stop_on_first), !map !83

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="29" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="0" op_0_bw="0" op_1_bw="1">
<![CDATA[
:18  call void (...)* @_ssdm_op_SpecBitsMap(i1 %accept), !map !87

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="30" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="36" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:19  call void (...)* @_ssdm_op_SpecBitsMap(i32 0) nounwind, !map !91

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="31" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="37" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:20  call void (...)* @_ssdm_op_SpecTopModule([30 x i8]* @str) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="32" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="38" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:21  %accept_read = call i1 @_ssdm_op_Read.ap_none.i1(i1 %accept)

]]></node>
<StgValue><ssdm name="accept_read"/></StgValue>
</operation>

<operation id="33" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="39" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:22  %stop_on_first_read = call i1 @_ssdm_op_Read.ap_none.i1(i1 %stop_on_first)

]]></node>
<StgValue><ssdm name="stop_on_first_read"/></StgValue>
</operation>

<operation id="34" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:23  %end_sample_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %end_sample)

]]></node>
<StgValue><ssdm name="end_sample_read"/></StgValue>
</operation>

<operation id="35" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="41" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:24  %end_index_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %end_index)

]]></node>
<StgValue><ssdm name="end_index_read"/></StgValue>
</operation>

<operation id="36" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="42" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:25  %i_sample_1 = call i16 @_ssdm_op_Read.ap_none.i16(i16 %begin_sample)

]]></node>
<StgValue><ssdm name="i_sample_1"/></StgValue>
</operation>

<operation id="37" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="43" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:26  %i_index_1 = call i16 @_ssdm_op_Read.ap_none.i16(i16 %begin_index)

]]></node>
<StgValue><ssdm name="i_index_1"/></StgValue>
</operation>

<operation id="38" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="44" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:27  %sample_length_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %sample_length)

]]></node>
<StgValue><ssdm name="sample_length_read"/></StgValue>
</operation>

<operation id="39" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="45" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:28  %sample_buffer_length_read = call i32 @_ssdm_op_Read.ap_none.i32(i32 %sample_buffer_length)

]]></node>
<StgValue><ssdm name="sample_buffer_length_read"/></StgValue>
</operation>

<operation id="40" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="46" bw="1" op_0_bw="64">
<![CDATA[
:29  %result = alloca [16 x i1], align 16

]]></node>
<StgValue><ssdm name="result"/></StgValue>
</operation>

<operation id="41" st_id="1" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="47" bw="32" op_0_bw="64">
<![CDATA[
:30  %start_indices = alloca [16 x i32], align 16

]]></node>
<StgValue><ssdm name="start_indices"/></StgValue>
</operation>

<operation id="42" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="48" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:31  call void (...)* @_ssdm_op_SpecBus(i64* %nfa_initials_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="43" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="49" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:32  call void (...)* @_ssdm_op_SpecBus(i64* %nfa_finals_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="44" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="50" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:33  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_forward_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="45" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="51" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:34  call void (...)* @_ssdm_op_SpecWire(i8* %nfa_symbols, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="46" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="52" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:35  call void (...)* @_ssdm_op_SpecBus(i8* %sample_buffer, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="47" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="53" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:36  call void (...)* @_ssdm_op_SpecWire(i32 %sample_buffer_length, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="48" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="54" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:37  call void (...)* @_ssdm_op_SpecWire(i16 %sample_length, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="49" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="55" bw="0" op_0_bw="0" op_1_bw="56" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:38  call void (...)* @_ssdm_op_SpecBus(i56* %indices, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, i32 10, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="50" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="56" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:39  call void (...)* @_ssdm_op_SpecWire(i16 %i_size, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="51" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="57" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="8" op_9_bw="8" op_10_bw="8">
<![CDATA[
:40  call void (...)* @_ssdm_op_SpecWire(i16 %begin_index, i16 %begin_sample, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="52" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="58" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="8" op_9_bw="8" op_10_bw="8">
<![CDATA[
:41  call void (...)* @_ssdm_op_SpecWire(i16 %end_index, i16 %end_sample, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="53" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="59" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:42  call void (...)* @_ssdm_op_SpecWire(i1 %stop_on_first, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="54" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="60" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:43  call void (...)* @_ssdm_op_SpecWire(i1 %accept, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="55" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="61" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:44  call void (...)* @_ssdm_op_SpecWire(i32 0, [11 x i8]* @p_str37, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="56" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="62" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:45  call void (...)* @_ssdm_op_SpecIFCore(i64* %nfa_initials_buckets, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="57" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="63" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:46  call void (...)* @_ssdm_op_SpecIFCore(i64* %nfa_finals_buckets, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="58" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="64" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:47  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_forward_buckets, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="59" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="65" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:48  call void (...)* @_ssdm_op_SpecIFCore(i8* %nfa_symbols, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="60" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="66" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:49  call void (...)* @_ssdm_op_SpecIFCore(i8* %sample_buffer, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="61" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="67" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:50  call void (...)* @_ssdm_op_SpecIFCore(i32 %sample_buffer_length, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="62" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="68" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:51  call void (...)* @_ssdm_op_SpecIFCore(i16 %sample_length, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="63" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="69" bw="0" op_0_bw="0" op_1_bw="56" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:52  call void (...)* @_ssdm_op_SpecIFCore(i56* %indices, [1 x i8]* @p_str1129, [7 x i8]* @p_str38, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="64" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="70" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:53  call void (...)* @_ssdm_op_SpecIFCore(i16 %i_size, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="65" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="71" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:54  call void (...)* @_ssdm_op_SpecIFCore(i16 %begin_index, i16 %begin_sample, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="66" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="72" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:55  call void (...)* @_ssdm_op_SpecIFCore(i16 %end_index, i16 %end_sample, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="67" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="73" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:56  call void (...)* @_ssdm_op_SpecIFCore(i1 %stop_on_first, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="68" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="74" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:57  call void (...)* @_ssdm_op_SpecIFCore(i1 %accept, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="69" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="75" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:58  call void (...)* @_ssdm_op_SpecIFCore(i32 0, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="70" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="76" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:59  store i16 %i_sample_1, i16* %i_sample, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="71" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="77" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:60  store i16 %i_index_1, i16* %i_index, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="72" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="78" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:61  store i16 0, i16* %c, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="73" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="79" bw="0" op_0_bw="0">
<![CDATA[
:62  br label %._crit_edge

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="74" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="4">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="81" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
._crit_edge:0  %finished = phi i1 [ false, %0 ], [ %finished_2, %5 ]

]]></node>
<StgValue><ssdm name="finished"/></StgValue>
</operation>

<operation id="75" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="4">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="82" bw="32" op_0_bw="32" op_1_bw="8">
<![CDATA[
._crit_edge:1  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str41)

]]></node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="76" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="4">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="83" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
._crit_edge:2  call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 1000, i32 500, [1 x i8]* @p_str1129) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="77" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="4">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge:3  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="78" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="86" bw="5" op_0_bw="5" op_1_bw="0">
<![CDATA[
:0  %indvars_iv = phi i5 [ 0, %._crit_edge ], [ %units, %3 ]

]]></node>
<StgValue><ssdm name="indvars_iv"/></StgValue>
</operation>

<operation id="79" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="87" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
:1  %finished_1 = phi i1 [ %finished, %._crit_edge ], [ false, %3 ]

]]></node>
<StgValue><ssdm name="finished_1"/></StgValue>
</operation>

<operation id="80" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="88" bw="1" op_0_bw="1" op_1_bw="5" op_2_bw="32">
<![CDATA[
:2  %tmp_3 = call i1 @_ssdm_op_BitSelect.i1.i5.i32(i5 %indvars_iv, i32 4)

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="81" st_id="3" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="89" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
:3  %units = add i5 %indvars_iv, 1

]]></node>
<StgValue><ssdm name="units"/></StgValue>
</operation>

<operation id="82" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="5">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="90" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:4  br i1 %tmp_3, label %.loopexit, label %2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="83" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="92" bw="16" op_0_bw="16">
<![CDATA[
:0  %i_index_load = load i16* %i_index, align 2

]]></node>
<StgValue><ssdm name="i_index_load"/></StgValue>
</operation>

<operation id="84" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="93" bw="16" op_0_bw="16">
<![CDATA[
:1  %i_sample_load = load i16* %i_sample, align 2

]]></node>
<StgValue><ssdm name="i_sample_load"/></StgValue>
</operation>

<operation id="85" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="94" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecIFCore(i16 %end_index, i16 %end_sample, [1 x i8]* @p_str1129, [7 x i8]* @p_str39, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [1 x i8]* @p_str1129, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="86" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="95" bw="1" op_0_bw="16" op_1_bw="16">
<![CDATA[
:3  %tmp_i = icmp eq i16 %i_sample_load, %end_sample_read

]]></node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="87" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="96" bw="1" op_0_bw="16" op_1_bw="16">
<![CDATA[
:4  %tmp_i_16 = icmp eq i16 %i_index_load, %end_index_read

]]></node>
<StgValue><ssdm name="tmp_i_16"/></StgValue>
</operation>

<operation id="88" st_id="3" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="97" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:5  %finished_3 = and i1 %tmp_i, %tmp_i_16

]]></node>
<StgValue><ssdm name="finished_3"/></StgValue>
</operation>

<operation id="89" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="7">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="98" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6  br i1 %finished_3, label %.loopexit, label %3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="90" st_id="3" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="9">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
<literal name="finished_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="100" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="56" op_4_bw="32" op_5_bw="16">
<![CDATA[
:0  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index_load, i16 %i_sample_load, i56* %indices, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>

<operation id="91" st_id="3" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
</and_exp><and_exp><literal name="finished_3" val="1"/>
</and_exp></or_exp>
</condition>

<node id="112" bw="1" op_0_bw="1" op_1_bw="64" op_2_bw="64" op_3_bw="32" op_4_bw="8" op_5_bw="8" op_6_bw="16" op_7_bw="32" op_8_bw="1" op_9_bw="1" op_10_bw="5" op_11_bw="1">
<![CDATA[
.loopexit:1  %stop_on_first_meet = call fastcc i1 @nfa_accept_sample_multi(i64* %nfa_initials_buckets, i64* %nfa_finals_buckets, i32* %nfa_forward_buckets, i8* %nfa_symbols, i8* %sample_buffer, i16 %sample_length_read, [16 x i32]* %start_indices, i1 %stop_on_first_read, i1 %accept_read, i5 %indvars_iv, [16 x i1]* %result)

]]></node>
<StgValue><ssdm name="stop_on_first_meet"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="92" st_id="4" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="100" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="56" op_4_bw="32" op_5_bw="16">
<![CDATA[
:0  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index_load, i16 %i_sample_load, i56* %indices, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>

<operation id="93" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="101" bw="64" op_0_bw="5">
<![CDATA[
:1  %tmp_1 = zext i5 %indvars_iv to i64

]]></node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="94" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="102" bw="4" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
:2  %start_indices_addr = getelementptr inbounds [16 x i32]* %start_indices, i64 0, i64 %tmp_1

]]></node>
<StgValue><ssdm name="start_indices_addr"/></StgValue>
</operation>

<operation id="95" st_id="4" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="0" op_0_bw="32" op_1_bw="4">
<![CDATA[
:3  store i32 %offset, i32* %start_indices_addr, align 4

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="96" st_id="5" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="14">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="104" bw="32" op_0_bw="32" op_1_bw="56" op_2_bw="16" op_3_bw="16">
<![CDATA[
:4  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i56* %indices, i16 %i_index_load, i16 %i_sample_load)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="97" st_id="6" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="104" bw="32" op_0_bw="32" op_1_bw="56" op_2_bw="16" op_3_bw="16">
<![CDATA[
:4  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i56* %indices, i16 %i_index_load, i16 %i_sample_load)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>

<operation id="98" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="105" bw="16" op_0_bw="32">
<![CDATA[
:5  %i_index_2 = extractvalue { i16, i16 } %call_ret, 0

]]></node>
<StgValue><ssdm name="i_index_2"/></StgValue>
</operation>

<operation id="99" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="106" bw="16" op_0_bw="32">
<![CDATA[
:6  %i_sample_2 = extractvalue { i16, i16 } %call_ret, 1

]]></node>
<StgValue><ssdm name="i_sample_2"/></StgValue>
</operation>

<operation id="100" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="107" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  store i16 %i_sample_2, i16* %i_sample, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="101" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="108" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:8  store i16 %i_index_2, i16* %i_index, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="102" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="109" bw="0" op_0_bw="0">
<![CDATA[
:9  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="103" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="111" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
.loopexit:0  %finished_2 = phi i1 [ %finished_1, %1 ], [ %finished_3, %2 ]

]]></node>
<StgValue><ssdm name="finished_2"/></StgValue>
</operation>

<operation id="104" st_id="7" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="112" bw="1" op_0_bw="1" op_1_bw="64" op_2_bw="64" op_3_bw="32" op_4_bw="8" op_5_bw="8" op_6_bw="16" op_7_bw="32" op_8_bw="1" op_9_bw="1" op_10_bw="5" op_11_bw="1">
<![CDATA[
.loopexit:1  %stop_on_first_meet = call fastcc i1 @nfa_accept_sample_multi(i64* %nfa_initials_buckets, i64* %nfa_finals_buckets, i32* %nfa_forward_buckets, i8* %nfa_symbols, i8* %sample_buffer, i16 %sample_length_read, [16 x i32]* %start_indices, i1 %stop_on_first_read, i1 %accept_read, i5 %indvars_iv, [16 x i1]* %result)

]]></node>
<StgValue><ssdm name="stop_on_first_meet"/></StgValue>
</operation>

<operation id="105" st_id="7" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="113" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.loopexit:2  %brmerge_demorgan = and i1 %stop_on_first_meet, %stop_on_first_read

]]></node>
<StgValue><ssdm name="brmerge_demorgan"/></StgValue>
</operation>

<operation id="106" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="114" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.loopexit:3  br i1 %brmerge_demorgan, label %.loopexit8, label %.preheader

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="107" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="116" bw="5" op_0_bw="5" op_1_bw="0">
<![CDATA[
.preheader:0  %k_1 = phi i5 [ %k_2, %4 ], [ 0, %.loopexit ]

]]></node>
<StgValue><ssdm name="k_1"/></StgValue>
</operation>

<operation id="108" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="117" bw="1" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader:1  %exitcond = icmp eq i5 %k_1, %indvars_iv

]]></node>
<StgValue><ssdm name="exitcond"/></StgValue>
</operation>

<operation id="109" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="118" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader:2  call void (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 16, i64 0)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="110" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="119" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.preheader:3  %k_2 = add i5 %k_1, 1

]]></node>
<StgValue><ssdm name="k_2"/></StgValue>
</operation>

<operation id="111" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="120" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:4  br i1 %exitcond, label %5, label %4

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="112" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="19">
<or_exp><and_exp><literal name="exitcond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="123" bw="64" op_0_bw="5">
<![CDATA[
:1  %tmp_2 = zext i5 %k_1 to i64

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>

<operation id="113" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="19">
<or_exp><and_exp><literal name="exitcond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="124" bw="4" op_0_bw="1" op_1_bw="64" op_2_bw="64">
<![CDATA[
:2  %result_addr = getelementptr inbounds [16 x i1]* %result, i64 0, i64 %tmp_2

]]></node>
<StgValue><ssdm name="result_addr"/></StgValue>
</operation>

<operation id="114" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="19">
<or_exp><and_exp><literal name="exitcond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="125" bw="1" op_0_bw="4">
<![CDATA[
:3  %result_load = load i1* %result_addr, align 1

]]></node>
<StgValue><ssdm name="result_load"/></StgValue>
</operation>

<operation id="115" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp><literal name="exitcond" val="1"/>
</and_exp></or_exp>
</condition>

<node id="131" bw="32" op_0_bw="32" op_1_bw="8" op_2_bw="32">
<![CDATA[
:0  %empty = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str41, i32 %tmp)

]]></node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="116" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp><literal name="exitcond" val="1"/>
</and_exp></or_exp>
</condition>

<node id="132" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:1  br i1 %finished_2, label %6, label %._crit_edge

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="117" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="53">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="1"/>
<literal name="stop_on_first_read" val="0"/>
</and_exp></or_exp>
</condition>

<node id="134" bw="16" op_0_bw="16">
<![CDATA[
:0  %c_load_1 = load i16* %c, align 2

]]></node>
<StgValue><ssdm name="c_load_1"/></StgValue>
</operation>

<operation id="118" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="52">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="1"/>
<literal name="stop_on_first_read" val="1"/>
</and_exp></or_exp>
</condition>

<node id="135" bw="16" op_0_bw="1">
<![CDATA[
:1  %tmp_3_cast = zext i1 %stop_on_first_meet to i16

]]></node>
<StgValue><ssdm name="tmp_3_cast"/></StgValue>
</operation>

<operation id="119" st_id="8" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="23">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="1"/>
</and_exp></or_exp>
</condition>

<node id="136" bw="16" op_0_bw="1" op_1_bw="16" op_2_bw="16">
<![CDATA[
:2  %tmp_5 = select i1 %stop_on_first_read, i16 %tmp_3_cast, i16 %c_load_1

]]></node>
<StgValue><ssdm name="tmp_5"/></StgValue>
</operation>

<operation id="120" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="23">
<or_exp><and_exp><literal name="exitcond" val="1"/>
<literal name="finished_2" val="1"/>
</and_exp></or_exp>
</condition>

<node id="137" bw="0" op_0_bw="0">
<![CDATA[
:3  br label %.loopexit8

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="121" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="122" bw="16" op_0_bw="16">
<![CDATA[
:0  %c_load = load i16* %c, align 2

]]></node>
<StgValue><ssdm name="c_load"/></StgValue>
</operation>

<operation id="122" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="125" bw="1" op_0_bw="4">
<![CDATA[
:3  %result_load = load i1* %result_addr, align 1

]]></node>
<StgValue><ssdm name="result_load"/></StgValue>
</operation>

<operation id="123" st_id="9" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="126" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:4  %c_1 = add i16 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>

<operation id="124" st_id="9" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="127" bw="16" op_0_bw="1" op_1_bw="16" op_2_bw="16">
<![CDATA[
:5  %p_c_1 = select i1 %result_load, i16 %c_1, i16 %c_load

]]></node>
<StgValue><ssdm name="p_c_1"/></StgValue>
</operation>

<operation id="125" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="128" bw="0" op_0_bw="16" op_1_bw="16">
<![CDATA[
:6  store i16 %p_c_1, i16* %c, align 2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="126" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="129" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %.preheader

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="127" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="139" bw="16" op_0_bw="16" op_1_bw="0">
<![CDATA[
.loopexit8:0  %p_0 = phi i16 [ %tmp_5, %6 ], [ 1, %.loopexit ]

]]></node>
<StgValue><ssdm name="p_0"/></StgValue>
</operation>

<operation id="128" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="140" bw="32" op_0_bw="16">
<![CDATA[
.loopexit8:1  %p_0_cast = zext i16 %p_0 to i32

]]></node>
<StgValue><ssdm name="p_0_cast"/></StgValue>
</operation>

<operation id="129" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="141" bw="0" op_0_bw="32">
<![CDATA[
.loopexit8:2  ret i32 %p_0_cast

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
