<stg><name>compute_add</name>


<trans_list>

<trans id="24" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="25" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="4" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:1 %size_read = read i32 @_ssdm_op_Read.ap_fifo.i32P0A, i32 %size

]]></Node>
<StgValue><ssdm name="size_read"/></StgValue>
</operation>

<operation id="5" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:3 %write_ln61 = write void @_ssdm_op_Write.ap_fifo.i32P0A, i32 %size_c, i32 %size_read

]]></Node>
<StgValue><ssdm name="write_ln61"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="6" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="0">
<![CDATA[
entry:16 %empty = wait i32 @_ssdm_op_Wait

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="7" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
entry:17 %call_ln0 = call void @compute_add_Pipeline_execute, i32 %size_read, i32 %in1_stream, i32 %in2_stream, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="8" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:0 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %size, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @ScalarProp_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="9" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:2 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %size_c, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @ScalarProp_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="10" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:4 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="11" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:5 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="12" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:6 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="13" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:7 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in2_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="14" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:8 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in2_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="15" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:9 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in2_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="16" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:10 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %out_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="17" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:11 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %out_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="18" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:12 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %out_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="19" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:13 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %out_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="20" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:14 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in2_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="21" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:15 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="22" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
entry:17 %call_ln0 = call void @compute_add_Pipeline_execute, i32 %size_read, i32 %in1_stream, i32 %in2_stream, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln0"/></StgValue>
</operation>

<operation id="23" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="0">
<![CDATA[
entry:18 %ret_ln0 = ret

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
