<stg><name>Loop_HConvH_proc6</name>


<trans_list>

<trans id="122" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="123" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="124" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="125" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="151" from="5" to="13">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="152" from="5" to="6">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="144" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="145" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="146" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="147" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="148" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="149" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="150" from="12" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="14" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="32" op_0_bw="32">
<![CDATA[
entry:0  %hwin_1_1_i = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_1_1_i"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="32" op_0_bw="32">
<![CDATA[
entry:1  %hwin_1 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_1"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="32" op_0_bw="32">
<![CDATA[
entry:2  %hwin_2 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_2"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="32" op_0_bw="32">
<![CDATA[
entry:3  %hwin_3 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_3"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="32" op_0_bw="32">
<![CDATA[
entry:4  %hwin_4 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_4"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="32" op_0_bw="32">
<![CDATA[
entry:5  %hwin_5 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_5"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="32" op_0_bw="32">
<![CDATA[
entry:6  %hwin_6 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_6"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="32" op_0_bw="32">
<![CDATA[
entry:7  %hwin_7 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_7"/></StgValue>
</operation>

<operation id="22" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="32" op_0_bw="32">
<![CDATA[
entry:8  %hwin_8 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_8"/></StgValue>
</operation>

<operation id="23" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="32" op_0_bw="32">
<![CDATA[
entry:9  %hwin_9 = alloca i32

]]></Node>
<StgValue><ssdm name="hwin_9"/></StgValue>
</operation>

<operation id="24" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:14  %height_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %height)

]]></Node>
<StgValue><ssdm name="height_read"/></StgValue>
</operation>

<operation id="25" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:15  %width_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %width)

]]></Node>
<StgValue><ssdm name="width_read"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="64" op_0_bw="32">
<![CDATA[
entry:16  %cast = zext i32 %height_read to i64

]]></Node>
<StgValue><ssdm name="cast"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="64" op_0_bw="32">
<![CDATA[
entry:17  %cast1 = zext i32 %width_read to i64

]]></Node>
<StgValue><ssdm name="cast1"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:18  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="29" st_id="3" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:18  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="30" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:10  call void (...)* @_ssdm_op_SpecInterface(i32* %src_V, [5 x i8]* @p_str5, i32 1, i32 1, [5 x i8]* @p_str6, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1, [1 x i8]* @p_str1, i32 0, i32 0, i32 0, i32 0, [1 x i8]* @p_str1, [1 x i8]* @p_str1)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="31" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:11  call void (...)* @_ssdm_op_SpecInterface(i32* %hconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="32" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:12  call void (...)* @_ssdm_op_SpecInterface(i32* %width, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="33" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:13  call void (...)* @_ssdm_op_SpecInterface(i32* %height, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="34" st_id="4" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:18  %bound = mul i64 %cast1, %cast

]]></Node>
<StgValue><ssdm name="bound"/></StgValue>
</operation>

<operation id="35" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="0" op_0_bw="0">
<![CDATA[
entry:19  br label %0

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="36" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:0  %indvar_flatten = phi i64 [ 0, %entry ], [ %add_ln168, %HConvW_end ]

]]></Node>
<StgValue><ssdm name="indvar_flatten"/></StgValue>
</operation>

<operation id="37" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:1  %row_0_i_i = phi i11 [ 0, %entry ], [ %row, %HConvW_end ]

]]></Node>
<StgValue><ssdm name="row_0_i_i"/></StgValue>
</operation>

<operation id="38" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="32" op_0_bw="32">
<![CDATA[
:2  %hwin_1_1_i_load = load i32* %hwin_1_1_i

]]></Node>
<StgValue><ssdm name="hwin_1_1_i_load"/></StgValue>
</operation>

<operation id="39" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="32" op_0_bw="32">
<![CDATA[
:3  %hwin_1_load = load i32* %hwin_1

]]></Node>
<StgValue><ssdm name="hwin_1_load"/></StgValue>
</operation>

<operation id="40" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="32" op_0_bw="32">
<![CDATA[
:4  %hwin_2_load = load i32* %hwin_2

]]></Node>
<StgValue><ssdm name="hwin_2_load"/></StgValue>
</operation>

<operation id="41" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="32" op_0_bw="32">
<![CDATA[
:5  %hwin_3_load = load i32* %hwin_3

]]></Node>
<StgValue><ssdm name="hwin_3_load"/></StgValue>
</operation>

<operation id="42" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="32" op_0_bw="32">
<![CDATA[
:6  %hwin_4_load = load i32* %hwin_4

]]></Node>
<StgValue><ssdm name="hwin_4_load"/></StgValue>
</operation>

<operation id="43" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="32">
<![CDATA[
:7  %hwin_5_load = load i32* %hwin_5

]]></Node>
<StgValue><ssdm name="hwin_5_load"/></StgValue>
</operation>

<operation id="44" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32">
<![CDATA[
:8  %hwin_6_load = load i32* %hwin_6

]]></Node>
<StgValue><ssdm name="hwin_6_load"/></StgValue>
</operation>

<operation id="45" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="32" op_0_bw="32">
<![CDATA[
:9  %hwin_7_load = load i32* %hwin_7

]]></Node>
<StgValue><ssdm name="hwin_7_load"/></StgValue>
</operation>

<operation id="46" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32">
<![CDATA[
:10  %hwin_8_load = load i32* %hwin_8

]]></Node>
<StgValue><ssdm name="hwin_8_load"/></StgValue>
</operation>

<operation id="47" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="32" op_0_bw="32">
<![CDATA[
:11  %hwin_9_load_1 = load i32* %hwin_9

]]></Node>
<StgValue><ssdm name="hwin_9_load_1"/></StgValue>
</operation>

<operation id="48" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="32" op_0_bw="11">
<![CDATA[
:12  %zext_ln169 = zext i11 %row_0_i_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln169"/></StgValue>
</operation>

<operation id="49" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:13  %icmp_ln169 = icmp slt i32 %zext_ln169, %width_read

]]></Node>
<StgValue><ssdm name="icmp_ln169"/></StgValue>
</operation>

<operation id="50" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:14  %icmp_ln168 = icmp eq i64 %indvar_flatten, %bound

]]></Node>
<StgValue><ssdm name="icmp_ln168"/></StgValue>
</operation>

<operation id="51" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
:15  %add_ln168 = add i64 %indvar_flatten, 1

]]></Node>
<StgValue><ssdm name="add_ln168"/></StgValue>
</operation>

<operation id="52" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:16  store i32 %hwin_9_load_1, i32* %hwin_8

]]></Node>
<StgValue><ssdm name="store_ln0"/></StgValue>
</operation>

<operation id="53" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:17  store i32 %hwin_8_load, i32* %hwin_7

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="54" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:18  store i32 %hwin_7_load, i32* %hwin_6

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="55" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:19  store i32 %hwin_6_load, i32* %hwin_5

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="56" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:20  store i32 %hwin_5_load, i32* %hwin_4

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="57" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:21  store i32 %hwin_4_load, i32* %hwin_3

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="58" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:22  store i32 %hwin_3_load, i32* %hwin_2

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="59" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:23  store i32 %hwin_2_load, i32* %hwin_1

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="60" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32">
<![CDATA[
:24  store i32 %hwin_1_load, i32* %hwin_1_1_i

]]></Node>
<StgValue><ssdm name="store_ln176"/></StgValue>
</operation>

<operation id="61" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:25  br i1 %icmp_ln168, label %.exit, label %HConvW_begin

]]></Node>
<StgValue><ssdm name="br_ln168"/></StgValue>
</operation>

<operation id="62" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="32" op_0_bw="32">
<![CDATA[
HConvW_begin:0  %hwin_9_load = load i32* %hwin_9

]]></Node>
<StgValue><ssdm name="hwin_9_load"/></StgValue>
</operation>

<operation id="63" st_id="5" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
HConvW_begin:3  %select_ln169 = select i1 %icmp_ln169, i11 %row_0_i_i, i11 0

]]></Node>
<StgValue><ssdm name="select_ln169"/></StgValue>
</operation>

<operation id="64" st_id="5" stage="1" lat="1">
<core>AXI4Stream</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:7  %tmp_2 = call i32 @_ssdm_op_Read.axis.volatile.i32P(i32* %src_V)

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>

<operation id="65" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:10  %mul_ln176 = mul i32 111, %hwin_1_load

]]></Node>
<StgValue><ssdm name="mul_ln176"/></StgValue>
</operation>

<operation id="66" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:11  %mul_ln176_1 = mul i32 266, %hwin_2_load

]]></Node>
<StgValue><ssdm name="mul_ln176_1"/></StgValue>
</operation>

<operation id="67" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:13  %mul_ln176_3 = mul i32 724, %hwin_4_load

]]></Node>
<StgValue><ssdm name="mul_ln176_3"/></StgValue>
</operation>

<operation id="68" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:14  %mul_ln176_4 = mul i32 821, %hwin_5_load

]]></Node>
<StgValue><ssdm name="mul_ln176_4"/></StgValue>
</operation>

<operation id="69" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:17  %mul_ln176_7 = mul i32 266, %hwin_8_load

]]></Node>
<StgValue><ssdm name="mul_ln176_7"/></StgValue>
</operation>

<operation id="70" st_id="5" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:18  %mul_ln176_8 = mul i32 111, %hwin_9_load

]]></Node>
<StgValue><ssdm name="mul_ln176_8"/></StgValue>
</operation>

<operation id="71" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
HConvW_begin:33  %icmp_ln178 = icmp ugt i11 %select_ln169, 9

]]></Node>
<StgValue><ssdm name="icmp_ln178"/></StgValue>
</operation>

<operation id="72" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="0" op_0_bw="32" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
HConvW_begin:34  store i32 %tmp_2, i32* %hwin_9

]]></Node>
<StgValue><ssdm name="store_ln178"/></StgValue>
</operation>

<operation id="73" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
HConvW_begin:35  br i1 %icmp_ln178, label %1, label %HConvW_end

]]></Node>
<StgValue><ssdm name="br_ln178"/></StgValue>
</operation>

<operation id="74" st_id="5" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
HConvW_end:1  %row = add i11 %select_ln169, 1

]]></Node>
<StgValue><ssdm name="row"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="75" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:10  %mul_ln176 = mul i32 111, %hwin_1_load

]]></Node>
<StgValue><ssdm name="mul_ln176"/></StgValue>
</operation>

<operation id="76" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:11  %mul_ln176_1 = mul i32 266, %hwin_2_load

]]></Node>
<StgValue><ssdm name="mul_ln176_1"/></StgValue>
</operation>

<operation id="77" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:13  %mul_ln176_3 = mul i32 724, %hwin_4_load

]]></Node>
<StgValue><ssdm name="mul_ln176_3"/></StgValue>
</operation>

<operation id="78" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:14  %mul_ln176_4 = mul i32 821, %hwin_5_load

]]></Node>
<StgValue><ssdm name="mul_ln176_4"/></StgValue>
</operation>

<operation id="79" st_id="6" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:15  %mul_ln176_5 = mul i32 724, %hwin_6_load

]]></Node>
<StgValue><ssdm name="mul_ln176_5"/></StgValue>
</operation>

<operation id="80" st_id="6" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:16  %mul_ln176_6 = mul i32 498, %hwin_7_load

]]></Node>
<StgValue><ssdm name="mul_ln176_6"/></StgValue>
</operation>

<operation id="81" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:17  %mul_ln176_7 = mul i32 266, %hwin_8_load

]]></Node>
<StgValue><ssdm name="mul_ln176_7"/></StgValue>
</operation>

<operation id="82" st_id="6" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:18  %mul_ln176_8 = mul i32 111, %hwin_9_load

]]></Node>
<StgValue><ssdm name="mul_ln176_8"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="83" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:10  %mul_ln176 = mul i32 111, %hwin_1_load

]]></Node>
<StgValue><ssdm name="mul_ln176"/></StgValue>
</operation>

<operation id="84" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:11  %mul_ln176_1 = mul i32 266, %hwin_2_load

]]></Node>
<StgValue><ssdm name="mul_ln176_1"/></StgValue>
</operation>

<operation id="85" st_id="7" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:12  %mul_ln176_2 = mul i32 498, %hwin_3_load

]]></Node>
<StgValue><ssdm name="mul_ln176_2"/></StgValue>
</operation>

<operation id="86" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:13  %mul_ln176_3 = mul i32 724, %hwin_4_load

]]></Node>
<StgValue><ssdm name="mul_ln176_3"/></StgValue>
</operation>

<operation id="87" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:14  %mul_ln176_4 = mul i32 821, %hwin_5_load

]]></Node>
<StgValue><ssdm name="mul_ln176_4"/></StgValue>
</operation>

<operation id="88" st_id="7" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:15  %mul_ln176_5 = mul i32 724, %hwin_6_load

]]></Node>
<StgValue><ssdm name="mul_ln176_5"/></StgValue>
</operation>

<operation id="89" st_id="7" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:16  %mul_ln176_6 = mul i32 498, %hwin_7_load

]]></Node>
<StgValue><ssdm name="mul_ln176_6"/></StgValue>
</operation>

<operation id="90" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:17  %mul_ln176_7 = mul i32 266, %hwin_8_load

]]></Node>
<StgValue><ssdm name="mul_ln176_7"/></StgValue>
</operation>

<operation id="91" st_id="7" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:18  %mul_ln176_8 = mul i32 111, %hwin_9_load

]]></Node>
<StgValue><ssdm name="mul_ln176_8"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="92" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:8  %shl_ln176 = shl i32 %hwin_1_1_i_load, 5

]]></Node>
<StgValue><ssdm name="shl_ln176"/></StgValue>
</operation>

<operation id="93" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:9  %shl_ln176_1 = shl i32 %hwin_1_1_i_load, 2

]]></Node>
<StgValue><ssdm name="shl_ln176_1"/></StgValue>
</operation>

<operation id="94" st_id="8" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:12  %mul_ln176_2 = mul i32 498, %hwin_3_load

]]></Node>
<StgValue><ssdm name="mul_ln176_2"/></StgValue>
</operation>

<operation id="95" st_id="8" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:15  %mul_ln176_5 = mul i32 724, %hwin_6_load

]]></Node>
<StgValue><ssdm name="mul_ln176_5"/></StgValue>
</operation>

<operation id="96" st_id="8" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:16  %mul_ln176_6 = mul i32 498, %hwin_7_load

]]></Node>
<StgValue><ssdm name="mul_ln176_6"/></StgValue>
</operation>

<operation id="97" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:19  %shl_ln176_2 = shl i32 %tmp_2, 5

]]></Node>
<StgValue><ssdm name="shl_ln176_2"/></StgValue>
</operation>

<operation id="98" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:20  %shl_ln176_3 = shl i32 %tmp_2, 2

]]></Node>
<StgValue><ssdm name="shl_ln176_3"/></StgValue>
</operation>

<operation id="99" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:21  %add_ln176 = add i32 %shl_ln176_2, %shl_ln176

]]></Node>
<StgValue><ssdm name="add_ln176"/></StgValue>
</operation>

<operation id="100" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:22  %add_ln176_1 = add i32 %add_ln176, %shl_ln176_3

]]></Node>
<StgValue><ssdm name="add_ln176_1"/></StgValue>
</operation>

<operation id="101" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:23  %add_ln176_2 = add i32 %mul_ln176, %mul_ln176_1

]]></Node>
<StgValue><ssdm name="add_ln176_2"/></StgValue>
</operation>

<operation id="102" st_id="8" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:24  %add_ln176_3 = add i32 %add_ln176_2, %shl_ln176_1

]]></Node>
<StgValue><ssdm name="add_ln176_3"/></StgValue>
</operation>

<operation id="103" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:26  %add_ln176_5 = add i32 %mul_ln176_3, %mul_ln176_4

]]></Node>
<StgValue><ssdm name="add_ln176_5"/></StgValue>
</operation>

<operation id="104" st_id="8" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:29  %add_ln176_8 = add i32 %mul_ln176_7, %mul_ln176_8

]]></Node>
<StgValue><ssdm name="add_ln176_8"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="105" st_id="9" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:12  %mul_ln176_2 = mul i32 498, %hwin_3_load

]]></Node>
<StgValue><ssdm name="mul_ln176_2"/></StgValue>
</operation>

<operation id="106" st_id="9" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:28  %add_ln176_7 = add i32 %mul_ln176_5, %mul_ln176_6

]]></Node>
<StgValue><ssdm name="add_ln176_7"/></StgValue>
</operation>

<operation id="107" st_id="9" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:30  %add_ln176_9 = add i32 %add_ln176_8, %add_ln176_7

]]></Node>
<StgValue><ssdm name="add_ln176_9"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="108" st_id="10" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:27  %add_ln176_6 = add i32 %add_ln176_5, %mul_ln176_2

]]></Node>
<StgValue><ssdm name="add_ln176_6"/></StgValue>
</operation>

<operation id="109" st_id="10" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:31  %add_ln176_10 = add i32 %add_ln176_9, %add_ln176_6

]]></Node>
<StgValue><ssdm name="add_ln176_10"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="110" st_id="11" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:25  %add_ln176_4 = add i32 %add_ln176_3, %add_ln176_1

]]></Node>
<StgValue><ssdm name="add_ln176_4"/></StgValue>
</operation>

<operation id="111" st_id="11" stage="1" lat="1">
<core>TAddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
HConvW_begin:32  %tmp = add i32 %add_ln176_10, %add_ln176_4

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="112" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
HConvW_begin:1  call void (...)* @_ssdm_op_SpecLoopName([14 x i8]* @HConvH_HConvW_str)

]]></Node>
<StgValue><ssdm name="specloopname_ln0"/></StgValue>
</operation>

<operation id="113" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
HConvW_begin:2  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 2070601, i64 0)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="114" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
HConvW_begin:4  call void (...)* @_ssdm_op_SpecLoopName([7 x i8]* @p_str15) nounwind

]]></Node>
<StgValue><ssdm name="specloopname_ln169"/></StgValue>
</operation>

<operation id="115" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
HConvW_begin:5  %tmp_5_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([7 x i8]* @p_str15)

]]></Node>
<StgValue><ssdm name="tmp_5_i"/></StgValue>
</operation>

<operation id="116" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
HConvW_begin:6  call void (...)* @_ssdm_op_SpecPipeline(i32 -1, i32 1, i32 1, i32 0, [1 x i8]* @p_str1) nounwind

]]></Node>
<StgValue><ssdm name="specpipeline_ln170"/></StgValue>
</operation>

<operation id="117" st_id="12" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln178" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
:0  call void @_ssdm_op_Write.ap_fifo.volatile.i32P(i32* %hconv_V, i32 %tmp)

]]></Node>
<StgValue><ssdm name="write_ln179"/></StgValue>
</operation>

<operation id="118" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln178" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %HConvW_end

]]></Node>
<StgValue><ssdm name="br_ln179"/></StgValue>
</operation>

<operation id="119" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
HConvW_end:0  %empty_18 = call i32 (...)* @_ssdm_op_SpecRegionEnd([7 x i8]* @p_str15, i32 %tmp_5_i)

]]></Node>
<StgValue><ssdm name="empty_18"/></StgValue>
</operation>

<operation id="120" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln168" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="0" op_0_bw="0">
<![CDATA[
HConvW_end:2  br label %0

]]></Node>
<StgValue><ssdm name="br_ln169"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="121" st_id="13" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="97" bw="0">
<![CDATA[
.exit:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
