<stg><name>entry_proc</name>


<trans_list>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="2" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="3" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:0 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %out_r_c, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @ScalarProp_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="3" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="4" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:1 %out_r_read = read i64 @_ssdm_op_Read.ap_auto.i64, i64 %out_r

]]></Node>
<StgValue><ssdm name="out_r_read"/></StgValue>
</operation>

<operation id="4" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64">
<![CDATA[
entry:2 %write_ln0 = write void @_ssdm_op_Write.ap_fifo.i64P0A, i64 %out_r_c, i64 %out_r_read

]]></Node>
<StgValue><ssdm name="write_ln0"/></StgValue>
</operation>

<operation id="5" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="0">
<![CDATA[
entry:3 %ret_ln0 = ret

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
