<stg><name>filter11x11_strm.ent</name>


<trans_list>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="2" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:0  call void (...)* @_ssdm_op_SpecInterface(i32* %width_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="3" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:1  %height_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %height)

]]></Node>
<StgValue><ssdm name="height_read"/></StgValue>
</operation>

<operation id="4" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:2  %width_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %width)

]]></Node>
<StgValue><ssdm name="width_read"/></StgValue>
</operation>

<operation id="5" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:3  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %width_out, i32 %width_read)

]]></Node>
<StgValue><ssdm name="write_ln263"/></StgValue>
</operation>

<operation id="6" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:4  call void (...)* @_ssdm_op_SpecInterface(i32* %width_out1, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="7" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:5  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %width_out1, i32 %width_read)

]]></Node>
<StgValue><ssdm name="write_ln263"/></StgValue>
</operation>

<operation id="8" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:6  call void (...)* @_ssdm_op_SpecInterface(i32* %height_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="9" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:7  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %height_out, i32 %height_read)

]]></Node>
<StgValue><ssdm name="write_ln263"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:8  call void (...)* @_ssdm_op_SpecInterface(i32* %height_out2, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:9  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %height_out2, i32 %height_read)

]]></Node>
<StgValue><ssdm name="write_ln263"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="0">
<![CDATA[
entry:10  ret void

]]></Node>
<StgValue><ssdm name="ret_ln263"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
