<stg><name>applySingleKernel</name>


<trans_list>

<trans id="2157" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2158" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2159" from="2" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2161" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2162" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2163" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2897" from="6" to="61">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2898" from="6" to="7">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2843" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2844" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2845" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2846" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2847" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2848" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2849" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2850" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2851" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2852" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2853" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2854" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2855" from="19" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2856" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2857" from="21" to="22">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2858" from="22" to="23">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2859" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2860" from="24" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2861" from="25" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2862" from="26" to="27">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2863" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2864" from="28" to="29">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2865" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2866" from="30" to="31">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2867" from="31" to="32">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2868" from="32" to="33">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2869" from="33" to="34">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2870" from="34" to="35">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2871" from="35" to="36">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2872" from="36" to="37">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2873" from="37" to="38">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2874" from="38" to="39">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2875" from="39" to="40">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2876" from="40" to="41">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2877" from="41" to="42">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2878" from="42" to="43">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2879" from="43" to="44">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2880" from="44" to="45">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2881" from="45" to="46">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2882" from="46" to="47">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2883" from="47" to="48">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2884" from="48" to="49">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2885" from="49" to="50">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2886" from="50" to="51">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2887" from="51" to="52">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2888" from="52" to="53">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2889" from="53" to="54">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2890" from="54" to="55">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2891" from="55" to="56">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2892" from="56" to="57">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2893" from="57" to="58">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2894" from="58" to="59">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2895" from="59" to="60">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2896" from="60" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2221" from="61" to="62">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2222" from="61" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2224" from="62" to="63">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2225" from="63" to="64">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2226" from="64" to="65">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2954" from="65" to="120">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2955" from="65" to="66">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2900" from="66" to="67">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2901" from="67" to="68">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2902" from="68" to="69">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2903" from="69" to="70">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2904" from="70" to="71">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2905" from="71" to="72">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2906" from="72" to="73">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2907" from="73" to="74">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2908" from="74" to="75">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2909" from="75" to="76">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2910" from="76" to="77">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2911" from="77" to="78">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2912" from="78" to="79">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2913" from="79" to="80">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2914" from="80" to="81">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2915" from="81" to="82">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2916" from="82" to="83">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2917" from="83" to="84">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2918" from="84" to="85">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2919" from="85" to="86">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2920" from="86" to="87">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2921" from="87" to="88">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2922" from="88" to="89">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2923" from="89" to="90">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2924" from="90" to="91">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2925" from="91" to="92">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2926" from="92" to="93">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2927" from="93" to="94">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2928" from="94" to="95">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2929" from="95" to="96">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2930" from="96" to="97">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2931" from="97" to="98">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2932" from="98" to="99">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2933" from="99" to="100">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2934" from="100" to="101">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2935" from="101" to="102">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2936" from="102" to="103">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2937" from="103" to="104">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2938" from="104" to="105">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2939" from="105" to="106">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2940" from="106" to="107">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2941" from="107" to="108">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2942" from="108" to="109">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2943" from="109" to="110">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2944" from="110" to="111">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2945" from="111" to="112">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2946" from="112" to="113">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2947" from="113" to="114">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2948" from="114" to="115">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2949" from="115" to="116">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2950" from="116" to="117">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2951" from="117" to="118">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2952" from="118" to="119">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2953" from="119" to="65">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2284" from="120" to="121">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2285" from="120" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2287" from="121" to="122">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2288" from="122" to="123">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2289" from="123" to="124">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3011" from="124" to="179">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3012" from="124" to="125">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2957" from="125" to="126">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2958" from="126" to="127">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2959" from="127" to="128">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2960" from="128" to="129">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2961" from="129" to="130">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2962" from="130" to="131">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2963" from="131" to="132">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2964" from="132" to="133">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2965" from="133" to="134">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2966" from="134" to="135">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2967" from="135" to="136">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2968" from="136" to="137">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2969" from="137" to="138">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2970" from="138" to="139">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2971" from="139" to="140">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2972" from="140" to="141">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2973" from="141" to="142">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2974" from="142" to="143">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2975" from="143" to="144">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2976" from="144" to="145">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2977" from="145" to="146">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2978" from="146" to="147">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2979" from="147" to="148">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2980" from="148" to="149">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2981" from="149" to="150">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2982" from="150" to="151">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2983" from="151" to="152">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2984" from="152" to="153">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2985" from="153" to="154">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2986" from="154" to="155">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2987" from="155" to="156">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2988" from="156" to="157">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2989" from="157" to="158">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2990" from="158" to="159">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2991" from="159" to="160">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2992" from="160" to="161">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2993" from="161" to="162">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2994" from="162" to="163">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2995" from="163" to="164">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2996" from="164" to="165">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2997" from="165" to="166">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2998" from="166" to="167">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2999" from="167" to="168">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3000" from="168" to="169">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3001" from="169" to="170">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3002" from="170" to="171">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3003" from="171" to="172">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3004" from="172" to="173">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3005" from="173" to="174">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3006" from="174" to="175">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3007" from="175" to="176">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3008" from="176" to="177">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3009" from="177" to="178">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3010" from="178" to="124">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2347" from="179" to="180">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2348" from="179" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2350" from="180" to="181">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2351" from="181" to="182">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2352" from="182" to="183">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3068" from="183" to="238">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3069" from="183" to="184">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3014" from="184" to="185">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3015" from="185" to="186">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3016" from="186" to="187">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3017" from="187" to="188">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3018" from="188" to="189">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3019" from="189" to="190">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3020" from="190" to="191">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3021" from="191" to="192">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3022" from="192" to="193">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3023" from="193" to="194">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3024" from="194" to="195">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3025" from="195" to="196">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3026" from="196" to="197">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3027" from="197" to="198">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3028" from="198" to="199">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3029" from="199" to="200">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3030" from="200" to="201">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3031" from="201" to="202">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3032" from="202" to="203">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3033" from="203" to="204">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3034" from="204" to="205">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3035" from="205" to="206">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3036" from="206" to="207">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3037" from="207" to="208">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3038" from="208" to="209">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3039" from="209" to="210">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3040" from="210" to="211">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3041" from="211" to="212">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3042" from="212" to="213">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3043" from="213" to="214">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3044" from="214" to="215">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3045" from="215" to="216">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3046" from="216" to="217">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3047" from="217" to="218">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3048" from="218" to="219">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3049" from="219" to="220">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3050" from="220" to="221">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3051" from="221" to="222">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3052" from="222" to="223">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3053" from="223" to="224">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3054" from="224" to="225">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3055" from="225" to="226">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3056" from="226" to="227">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3057" from="227" to="228">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3058" from="228" to="229">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3059" from="229" to="230">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3060" from="230" to="231">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3061" from="231" to="232">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3062" from="232" to="233">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3063" from="233" to="234">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3064" from="234" to="235">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3065" from="235" to="236">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3066" from="236" to="237">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3067" from="237" to="183">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2410" from="238" to="239">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_4" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2411" from="238" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_4" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2413" from="239" to="240">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2414" from="240" to="241">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2415" from="241" to="242">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3125" from="242" to="297">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3126" from="242" to="243">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3071" from="243" to="244">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3072" from="244" to="245">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3073" from="245" to="246">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3074" from="246" to="247">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3075" from="247" to="248">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3076" from="248" to="249">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3077" from="249" to="250">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3078" from="250" to="251">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3079" from="251" to="252">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3080" from="252" to="253">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3081" from="253" to="254">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3082" from="254" to="255">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3083" from="255" to="256">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3084" from="256" to="257">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3085" from="257" to="258">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3086" from="258" to="259">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3087" from="259" to="260">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3088" from="260" to="261">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3089" from="261" to="262">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3090" from="262" to="263">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3091" from="263" to="264">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3092" from="264" to="265">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3093" from="265" to="266">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3094" from="266" to="267">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3095" from="267" to="268">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3096" from="268" to="269">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3097" from="269" to="270">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3098" from="270" to="271">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3099" from="271" to="272">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3100" from="272" to="273">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3101" from="273" to="274">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3102" from="274" to="275">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3103" from="275" to="276">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3104" from="276" to="277">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3105" from="277" to="278">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3106" from="278" to="279">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3107" from="279" to="280">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3108" from="280" to="281">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3109" from="281" to="282">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3110" from="282" to="283">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3111" from="283" to="284">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3112" from="284" to="285">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3113" from="285" to="286">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3114" from="286" to="287">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3115" from="287" to="288">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3116" from="288" to="289">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3117" from="289" to="290">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3118" from="290" to="291">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3119" from="291" to="292">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3120" from="292" to="293">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3121" from="293" to="294">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3122" from="294" to="295">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3123" from="295" to="296">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3124" from="296" to="242">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2473" from="297" to="298">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_5" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2474" from="297" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_5" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2476" from="298" to="299">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2477" from="299" to="300">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2478" from="300" to="301">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3182" from="301" to="356">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3183" from="301" to="302">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3128" from="302" to="303">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3129" from="303" to="304">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3130" from="304" to="305">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3131" from="305" to="306">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3132" from="306" to="307">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3133" from="307" to="308">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3134" from="308" to="309">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3135" from="309" to="310">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3136" from="310" to="311">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3137" from="311" to="312">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3138" from="312" to="313">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3139" from="313" to="314">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3140" from="314" to="315">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3141" from="315" to="316">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3142" from="316" to="317">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3143" from="317" to="318">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3144" from="318" to="319">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3145" from="319" to="320">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3146" from="320" to="321">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3147" from="321" to="322">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3148" from="322" to="323">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3149" from="323" to="324">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3150" from="324" to="325">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3151" from="325" to="326">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3152" from="326" to="327">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3153" from="327" to="328">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3154" from="328" to="329">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3155" from="329" to="330">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3156" from="330" to="331">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3157" from="331" to="332">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3158" from="332" to="333">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3159" from="333" to="334">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3160" from="334" to="335">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3161" from="335" to="336">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3162" from="336" to="337">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3163" from="337" to="338">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3164" from="338" to="339">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3165" from="339" to="340">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3166" from="340" to="341">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3167" from="341" to="342">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3168" from="342" to="343">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3169" from="343" to="344">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3170" from="344" to="345">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3171" from="345" to="346">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3172" from="346" to="347">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3173" from="347" to="348">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3174" from="348" to="349">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3175" from="349" to="350">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3176" from="350" to="351">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3177" from="351" to="352">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3178" from="352" to="353">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3179" from="353" to="354">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3180" from="354" to="355">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3181" from="355" to="301">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2536" from="356" to="357">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_6" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2537" from="356" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_6" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2539" from="357" to="358">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2540" from="358" to="359">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2541" from="359" to="360">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3239" from="360" to="415">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3240" from="360" to="361">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3185" from="361" to="362">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3186" from="362" to="363">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3187" from="363" to="364">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3188" from="364" to="365">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3189" from="365" to="366">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3190" from="366" to="367">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3191" from="367" to="368">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3192" from="368" to="369">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3193" from="369" to="370">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3194" from="370" to="371">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3195" from="371" to="372">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3196" from="372" to="373">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3197" from="373" to="374">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3198" from="374" to="375">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3199" from="375" to="376">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3200" from="376" to="377">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3201" from="377" to="378">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3202" from="378" to="379">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3203" from="379" to="380">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3204" from="380" to="381">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3205" from="381" to="382">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3206" from="382" to="383">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3207" from="383" to="384">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3208" from="384" to="385">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3209" from="385" to="386">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3210" from="386" to="387">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3211" from="387" to="388">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3212" from="388" to="389">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3213" from="389" to="390">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3214" from="390" to="391">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3215" from="391" to="392">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3216" from="392" to="393">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3217" from="393" to="394">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3218" from="394" to="395">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3219" from="395" to="396">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3220" from="396" to="397">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3221" from="397" to="398">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3222" from="398" to="399">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3223" from="399" to="400">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3224" from="400" to="401">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3225" from="401" to="402">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3226" from="402" to="403">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3227" from="403" to="404">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3228" from="404" to="405">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3229" from="405" to="406">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3230" from="406" to="407">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3231" from="407" to="408">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3232" from="408" to="409">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3233" from="409" to="410">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3234" from="410" to="411">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3235" from="411" to="412">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3236" from="412" to="413">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3237" from="413" to="414">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3238" from="414" to="360">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2599" from="415" to="416">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_7" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2600" from="415" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_7" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2602" from="416" to="417">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2603" from="417" to="418">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2604" from="418" to="419">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3296" from="419" to="474">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3297" from="419" to="420">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3242" from="420" to="421">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3243" from="421" to="422">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3244" from="422" to="423">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3245" from="423" to="424">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3246" from="424" to="425">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3247" from="425" to="426">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3248" from="426" to="427">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3249" from="427" to="428">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3250" from="428" to="429">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3251" from="429" to="430">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3252" from="430" to="431">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3253" from="431" to="432">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3254" from="432" to="433">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3255" from="433" to="434">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3256" from="434" to="435">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3257" from="435" to="436">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3258" from="436" to="437">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3259" from="437" to="438">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3260" from="438" to="439">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3261" from="439" to="440">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3262" from="440" to="441">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3263" from="441" to="442">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3264" from="442" to="443">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3265" from="443" to="444">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3266" from="444" to="445">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3267" from="445" to="446">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3268" from="446" to="447">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3269" from="447" to="448">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3270" from="448" to="449">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3271" from="449" to="450">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3272" from="450" to="451">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3273" from="451" to="452">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3274" from="452" to="453">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3275" from="453" to="454">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3276" from="454" to="455">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3277" from="455" to="456">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3278" from="456" to="457">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3279" from="457" to="458">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3280" from="458" to="459">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3281" from="459" to="460">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3282" from="460" to="461">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3283" from="461" to="462">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3284" from="462" to="463">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3285" from="463" to="464">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3286" from="464" to="465">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3287" from="465" to="466">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3288" from="466" to="467">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3289" from="467" to="468">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3290" from="468" to="469">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3291" from="469" to="470">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3292" from="470" to="471">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3293" from="471" to="472">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3294" from="472" to="473">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3295" from="473" to="419">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2662" from="474" to="475">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_8" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2663" from="474" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_8" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2665" from="475" to="476">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2666" from="476" to="477">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2667" from="477" to="478">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3353" from="478" to="533">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3354" from="478" to="479">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3299" from="479" to="480">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3300" from="480" to="481">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3301" from="481" to="482">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3302" from="482" to="483">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3303" from="483" to="484">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3304" from="484" to="485">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3305" from="485" to="486">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3306" from="486" to="487">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3307" from="487" to="488">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3308" from="488" to="489">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3309" from="489" to="490">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3310" from="490" to="491">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3311" from="491" to="492">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3312" from="492" to="493">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3313" from="493" to="494">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3314" from="494" to="495">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3315" from="495" to="496">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3316" from="496" to="497">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3317" from="497" to="498">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3318" from="498" to="499">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3319" from="499" to="500">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3320" from="500" to="501">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3321" from="501" to="502">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3322" from="502" to="503">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3323" from="503" to="504">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3324" from="504" to="505">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3325" from="505" to="506">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3326" from="506" to="507">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3327" from="507" to="508">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3328" from="508" to="509">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3329" from="509" to="510">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3330" from="510" to="511">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3331" from="511" to="512">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3332" from="512" to="513">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3333" from="513" to="514">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3334" from="514" to="515">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3335" from="515" to="516">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3336" from="516" to="517">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3337" from="517" to="518">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3338" from="518" to="519">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3339" from="519" to="520">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3340" from="520" to="521">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3341" from="521" to="522">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3342" from="522" to="523">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3343" from="523" to="524">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3344" from="524" to="525">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3345" from="525" to="526">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3346" from="526" to="527">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3347" from="527" to="528">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3348" from="528" to="529">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3349" from="529" to="530">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3350" from="530" to="531">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3351" from="531" to="532">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3352" from="532" to="478">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2725" from="533" to="534">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_9" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2726" from="533" to="593">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_9" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="2728" from="534" to="535">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2729" from="535" to="536">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2730" from="536" to="537">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3356" from="537" to="538">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3357" from="538" to="539">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3358" from="539" to="540">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3359" from="540" to="541">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3360" from="541" to="542">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3361" from="542" to="543">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3362" from="543" to="544">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3363" from="544" to="545">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3364" from="545" to="546">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3365" from="546" to="547">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3366" from="547" to="548">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3367" from="548" to="549">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3368" from="549" to="550">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3369" from="550" to="551">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3370" from="551" to="552">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3371" from="552" to="553">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3372" from="553" to="554">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3373" from="554" to="555">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3374" from="555" to="556">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3375" from="556" to="557">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3376" from="557" to="558">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3377" from="558" to="559">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3378" from="559" to="560">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3379" from="560" to="561">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3380" from="561" to="562">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3381" from="562" to="563">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3382" from="563" to="564">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3383" from="564" to="565">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3384" from="565" to="566">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3385" from="566" to="567">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3386" from="567" to="568">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3387" from="568" to="569">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3388" from="569" to="570">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3389" from="570" to="571">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3390" from="571" to="572">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3391" from="572" to="573">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3392" from="573" to="574">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3393" from="574" to="575">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3394" from="575" to="576">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3395" from="576" to="577">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3396" from="577" to="578">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3397" from="578" to="579">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3398" from="579" to="580">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3399" from="580" to="581">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3400" from="581" to="582">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3401" from="582" to="583">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3402" from="583" to="584">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3403" from="584" to="585">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3404" from="585" to="586">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3405" from="586" to="587">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3406" from="587" to="588">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3407" from="588" to="589">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3408" from="589" to="590">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="3410" from="590" to="592">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3411" from="590" to="591">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="3409" from="591" to="537">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="2841" from="592" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="594" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.lr.ph12:0 %h_read = read i5 @_ssdm_op_Read.ap_auto.i5, i5 %h

]]></Node>
<StgValue><ssdm name="h_read"/></StgValue>
</operation>

<operation id="595" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph12:1 %w_read = read i6 @_ssdm_op_Read.ap_auto.i6, i6 %w

]]></Node>
<StgValue><ssdm name="w_read"/></StgValue>
</operation>

<operation id="596" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:2 %p_read_1 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read8

]]></Node>
<StgValue><ssdm name="p_read_1"/></StgValue>
</operation>

<operation id="597" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:3 %p_read_2 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read7

]]></Node>
<StgValue><ssdm name="p_read_2"/></StgValue>
</operation>

<operation id="598" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:4 %p_read_3 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read6

]]></Node>
<StgValue><ssdm name="p_read_3"/></StgValue>
</operation>

<operation id="599" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:5 %p_read_4 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read5

]]></Node>
<StgValue><ssdm name="p_read_4"/></StgValue>
</operation>

<operation id="600" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:6 %p_read_5 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read4

]]></Node>
<StgValue><ssdm name="p_read_5"/></StgValue>
</operation>

<operation id="601" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:7 %p_read_6 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read3

]]></Node>
<StgValue><ssdm name="p_read_6"/></StgValue>
</operation>

<operation id="602" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:8 %p_read_7 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read2

]]></Node>
<StgValue><ssdm name="p_read_7"/></StgValue>
</operation>

<operation id="603" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:9 %p_read_8 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read1

]]></Node>
<StgValue><ssdm name="p_read_8"/></StgValue>
</operation>

<operation id="604" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.lr.ph12:10 %p_read_9 = read i32 @_ssdm_op_Read.ap_auto.float, i32 %p_read

]]></Node>
<StgValue><ssdm name="p_read_9"/></StgValue>
</operation>

<operation id="605" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph12:11 %sub1 = add i6 %w_read, i6 63

]]></Node>
<StgValue><ssdm name="sub1"/></StgValue>
</operation>

<operation id="606" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="11" op_0_bw="6">
<![CDATA[
.lr.ph12:12 %zext_ln44 = zext i6 %w_read

]]></Node>
<StgValue><ssdm name="zext_ln44"/></StgValue>
</operation>

<operation id="607" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.lr.ph12:13 %add_ln44 = add i5 %h_read, i5 31

]]></Node>
<StgValue><ssdm name="add_ln44"/></StgValue>
</operation>

<operation id="608" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="64" op_0_bw="5">
<![CDATA[
.lr.ph12:14 %zext_ln44_1 = zext i5 %add_ln44

]]></Node>
<StgValue><ssdm name="zext_ln44_1"/></StgValue>
</operation>

<operation id="609" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph12:15 %add_ln44_1 = add i6 %w_read, i6 62

]]></Node>
<StgValue><ssdm name="add_ln44_1"/></StgValue>
</operation>

<operation id="610" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="32" op_0_bw="6">
<![CDATA[
.lr.ph12:16 %zext_ln44_2 = zext i6 %add_ln44_1

]]></Node>
<StgValue><ssdm name="zext_ln44_2"/></StgValue>
</operation>

<operation id="611" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph12:17 %br_ln44 = br void

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="612" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:0 %i_0 = phi i64 %add_ln44_21, void %._crit_edge.loopexit.9, i64 1, void %.lr.ph12

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="613" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %t_0 = phi i32 %add_ln44_20, void %._crit_edge.loopexit.9, i32 0, void %.lr.ph12

]]></Node>
<StgValue><ssdm name="t_0"/></StgValue>
</operation>

<operation id="614" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:2 %icmp_ln44 = icmp_slt  i64 %i_0, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44"/></StgValue>
</operation>

<operation id="615" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:3 %br_ln44 = br i1 %icmp_ln44, void %._crit_edge13.loopexit, void %.split6.0

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="616" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="11" op_0_bw="64">
<![CDATA[
.split6.0:0 %trunc_ln44 = trunc i64 %i_0

]]></Node>
<StgValue><ssdm name="trunc_ln44"/></StgValue>
</operation>

<operation id="617" st_id="2" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:3 %empty = add i11 %trunc_ln44, i11 2047

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="618" st_id="2" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:4 %empty_100 = mul i11 %empty, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_100"/></StgValue>
</operation>

<operation id="619" st_id="2" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:5 %empty_101 = mul i11 %trunc_ln44, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_101"/></StgValue>
</operation>

<operation id="620" st_id="2" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:6 %empty_102 = add i11 %trunc_ln44, i11 1

]]></Node>
<StgValue><ssdm name="empty_102"/></StgValue>
</operation>

<operation id="621" st_id="2" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:7 %empty_103 = mul i11 %empty_102, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_103"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="622" st_id="3" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:4 %empty_100 = mul i11 %empty, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_100"/></StgValue>
</operation>

<operation id="623" st_id="3" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:5 %empty_101 = mul i11 %trunc_ln44, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_101"/></StgValue>
</operation>

<operation id="624" st_id="3" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:7 %empty_103 = mul i11 %empty_102, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_103"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="625" st_id="4" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:4 %empty_100 = mul i11 %empty, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_100"/></StgValue>
</operation>

<operation id="626" st_id="4" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:5 %empty_101 = mul i11 %trunc_ln44, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_101"/></StgValue>
</operation>

<operation id="627" st_id="4" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:7 %empty_103 = mul i11 %empty_102, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_103"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="628" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split6.0:1 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_8

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="629" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="33" op_0_bw="32">
<![CDATA[
.split6.0:2 %t_0_cast = sext i32 %t_0

]]></Node>
<StgValue><ssdm name="t_0_cast"/></StgValue>
</operation>

<operation id="630" st_id="5" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:4 %empty_100 = mul i11 %empty, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_100"/></StgValue>
</operation>

<operation id="631" st_id="5" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:5 %empty_101 = mul i11 %trunc_ln44, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_101"/></StgValue>
</operation>

<operation id="632" st_id="5" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split6.0:7 %empty_103 = mul i11 %empty_102, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_103"/></StgValue>
</operation>

<operation id="633" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="0" op_0_bw="0">
<![CDATA[
.split6.0:8 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="634" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_0 = phi i33 %add_ln58, void %.split4.0, i33 %t_0_cast, void %.split6.0

]]></Node>
<StgValue><ssdm name="t_3_0"/></StgValue>
</operation>

<operation id="635" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_0 = phi i6 %add_ln47, void %.split4.0, i6 1, void %.split6.0

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="636" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="637" st_id="6" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47 = icmp_eq  i6 %j_0, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47"/></StgValue>
</operation>

<operation id="638" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_104 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_104"/></StgValue>
</operation>

<operation id="639" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47, void %.split4.0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="640" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="11" op_0_bw="6">
<![CDATA[
.split4.0:2 %j_0_cast = zext i6 %j_0

]]></Node>
<StgValue><ssdm name="j_0_cast"/></StgValue>
</operation>

<operation id="641" st_id="6" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.0:4 %empty_105 = add i6 %j_0, i6 63

]]></Node>
<StgValue><ssdm name="empty_105"/></StgValue>
</operation>

<operation id="642" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="11" op_0_bw="6">
<![CDATA[
.split4.0:5 %zext_ln8 = zext i6 %empty_105

]]></Node>
<StgValue><ssdm name="zext_ln8"/></StgValue>
</operation>

<operation id="643" st_id="6" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:6 %add_ln8 = add i11 %zext_ln8, i11 %empty_100

]]></Node>
<StgValue><ssdm name="add_ln8"/></StgValue>
</operation>

<operation id="644" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:7 %zext_ln8_40 = zext i11 %add_ln8

]]></Node>
<StgValue><ssdm name="zext_ln8_40"/></StgValue>
</operation>

<operation id="645" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:8 %arr_addr = getelementptr i32 %arr, i64 0, i64 %zext_ln8_40

]]></Node>
<StgValue><ssdm name="arr_addr"/></StgValue>
</operation>

<operation id="646" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:9 %arr_load = load i11 %arr_addr

]]></Node>
<StgValue><ssdm name="arr_load"/></StgValue>
</operation>

<operation id="647" st_id="6" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:12 %add_ln8_40 = add i11 %j_0_cast, i11 %empty_100

]]></Node>
<StgValue><ssdm name="add_ln8_40"/></StgValue>
</operation>

<operation id="648" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:13 %zext_ln8_41 = zext i11 %add_ln8_40

]]></Node>
<StgValue><ssdm name="zext_ln8_41"/></StgValue>
</operation>

<operation id="649" st_id="6" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:14 %arr_addr_40 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_41

]]></Node>
<StgValue><ssdm name="arr_addr_40"/></StgValue>
</operation>

<operation id="650" st_id="6" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:15 %arr_load_40 = load i11 %arr_addr_40

]]></Node>
<StgValue><ssdm name="arr_load_40"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="651" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:9 %arr_load = load i11 %arr_addr

]]></Node>
<StgValue><ssdm name="arr_load"/></StgValue>
</operation>

<operation id="652" st_id="7" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:10 %mul9 = fmul i32 %arr_load, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9"/></StgValue>
</operation>

<operation id="653" st_id="7" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:15 %arr_load_40 = load i11 %arr_addr_40

]]></Node>
<StgValue><ssdm name="arr_load_40"/></StgValue>
</operation>

<operation id="654" st_id="7" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:16 %mul9_0_0_1 = fmul i32 %arr_load_40, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_0_0_1"/></StgValue>
</operation>

<operation id="655" st_id="7" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:18 %add_ln8_41 = add i11 %add_ln8, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_41"/></StgValue>
</operation>

<operation id="656" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:19 %zext_ln8_42 = zext i11 %add_ln8_41

]]></Node>
<StgValue><ssdm name="zext_ln8_42"/></StgValue>
</operation>

<operation id="657" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:20 %arr_addr_41 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_42

]]></Node>
<StgValue><ssdm name="arr_addr_41"/></StgValue>
</operation>

<operation id="658" st_id="7" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:21 %arr_load_41 = load i11 %arr_addr_41

]]></Node>
<StgValue><ssdm name="arr_load_41"/></StgValue>
</operation>

<operation id="659" st_id="7" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:24 %add_ln8_42 = add i11 %zext_ln8, i11 %empty_101

]]></Node>
<StgValue><ssdm name="add_ln8_42"/></StgValue>
</operation>

<operation id="660" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:25 %zext_ln8_43 = zext i11 %add_ln8_42

]]></Node>
<StgValue><ssdm name="zext_ln8_43"/></StgValue>
</operation>

<operation id="661" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:26 %arr_addr_42 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_43

]]></Node>
<StgValue><ssdm name="arr_addr_42"/></StgValue>
</operation>

<operation id="662" st_id="7" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:27 %arr_load_42 = load i11 %arr_addr_42

]]></Node>
<StgValue><ssdm name="arr_load_42"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="663" st_id="8" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:10 %mul9 = fmul i32 %arr_load, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9"/></StgValue>
</operation>

<operation id="664" st_id="8" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:16 %mul9_0_0_1 = fmul i32 %arr_load_40, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_0_0_1"/></StgValue>
</operation>

<operation id="665" st_id="8" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:21 %arr_load_41 = load i11 %arr_addr_41

]]></Node>
<StgValue><ssdm name="arr_load_41"/></StgValue>
</operation>

<operation id="666" st_id="8" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:22 %mul9_0_0_2 = fmul i32 %arr_load_41, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_0_0_2"/></StgValue>
</operation>

<operation id="667" st_id="8" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:27 %arr_load_42 = load i11 %arr_addr_42

]]></Node>
<StgValue><ssdm name="arr_load_42"/></StgValue>
</operation>

<operation id="668" st_id="8" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:28 %mul9_0_1 = fmul i32 %arr_load_42, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_0_1"/></StgValue>
</operation>

<operation id="669" st_id="8" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:30 %add_ln8_43 = add i11 %j_0_cast, i11 %empty_101

]]></Node>
<StgValue><ssdm name="add_ln8_43"/></StgValue>
</operation>

<operation id="670" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:31 %zext_ln8_44 = zext i11 %add_ln8_43

]]></Node>
<StgValue><ssdm name="zext_ln8_44"/></StgValue>
</operation>

<operation id="671" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:32 %arr_addr_43 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_44

]]></Node>
<StgValue><ssdm name="arr_addr_43"/></StgValue>
</operation>

<operation id="672" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:33 %arr_load_43 = load i11 %arr_addr_43

]]></Node>
<StgValue><ssdm name="arr_load_43"/></StgValue>
</operation>

<operation id="673" st_id="8" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:36 %add_ln8_44 = add i11 %add_ln8_42, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_44"/></StgValue>
</operation>

<operation id="674" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:37 %zext_ln8_45 = zext i11 %add_ln8_44

]]></Node>
<StgValue><ssdm name="zext_ln8_45"/></StgValue>
</operation>

<operation id="675" st_id="8" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:38 %arr_addr_44 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_45

]]></Node>
<StgValue><ssdm name="arr_addr_44"/></StgValue>
</operation>

<operation id="676" st_id="8" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:39 %arr_load_44 = load i11 %arr_addr_44

]]></Node>
<StgValue><ssdm name="arr_load_44"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="677" st_id="9" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:10 %mul9 = fmul i32 %arr_load, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9"/></StgValue>
</operation>

<operation id="678" st_id="9" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:16 %mul9_0_0_1 = fmul i32 %arr_load_40, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_0_0_1"/></StgValue>
</operation>

<operation id="679" st_id="9" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:22 %mul9_0_0_2 = fmul i32 %arr_load_41, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_0_0_2"/></StgValue>
</operation>

<operation id="680" st_id="9" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:28 %mul9_0_1 = fmul i32 %arr_load_42, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_0_1"/></StgValue>
</operation>

<operation id="681" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:33 %arr_load_43 = load i11 %arr_addr_43

]]></Node>
<StgValue><ssdm name="arr_load_43"/></StgValue>
</operation>

<operation id="682" st_id="9" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:34 %mul9_0_1_1 = fmul i32 %arr_load_43, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_0_1_1"/></StgValue>
</operation>

<operation id="683" st_id="9" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:39 %arr_load_44 = load i11 %arr_addr_44

]]></Node>
<StgValue><ssdm name="arr_load_44"/></StgValue>
</operation>

<operation id="684" st_id="9" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:40 %mul9_0_1_2 = fmul i32 %arr_load_44, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_0_1_2"/></StgValue>
</operation>

<operation id="685" st_id="9" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:42 %add_ln8_45 = add i11 %zext_ln8, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_45"/></StgValue>
</operation>

<operation id="686" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:43 %zext_ln8_46 = zext i11 %add_ln8_45

]]></Node>
<StgValue><ssdm name="zext_ln8_46"/></StgValue>
</operation>

<operation id="687" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:44 %arr_addr_45 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_46

]]></Node>
<StgValue><ssdm name="arr_addr_45"/></StgValue>
</operation>

<operation id="688" st_id="9" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:45 %arr_load_45 = load i11 %arr_addr_45

]]></Node>
<StgValue><ssdm name="arr_load_45"/></StgValue>
</operation>

<operation id="689" st_id="9" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:48 %add_ln8_46 = add i11 %j_0_cast, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_46"/></StgValue>
</operation>

<operation id="690" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:49 %zext_ln8_47 = zext i11 %add_ln8_46

]]></Node>
<StgValue><ssdm name="zext_ln8_47"/></StgValue>
</operation>

<operation id="691" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:50 %arr_addr_46 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_47

]]></Node>
<StgValue><ssdm name="arr_addr_46"/></StgValue>
</operation>

<operation id="692" st_id="9" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:51 %arr_load_46 = load i11 %arr_addr_46

]]></Node>
<StgValue><ssdm name="arr_load_46"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="693" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.0:0 %add_ln47 = add i6 %j_0, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47"/></StgValue>
</operation>

<operation id="694" st_id="10" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:10 %mul9 = fmul i32 %arr_load, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9"/></StgValue>
</operation>

<operation id="695" st_id="10" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:16 %mul9_0_0_1 = fmul i32 %arr_load_40, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_0_0_1"/></StgValue>
</operation>

<operation id="696" st_id="10" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:22 %mul9_0_0_2 = fmul i32 %arr_load_41, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_0_0_2"/></StgValue>
</operation>

<operation id="697" st_id="10" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:28 %mul9_0_1 = fmul i32 %arr_load_42, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_0_1"/></StgValue>
</operation>

<operation id="698" st_id="10" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:34 %mul9_0_1_1 = fmul i32 %arr_load_43, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_0_1_1"/></StgValue>
</operation>

<operation id="699" st_id="10" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:40 %mul9_0_1_2 = fmul i32 %arr_load_44, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_0_1_2"/></StgValue>
</operation>

<operation id="700" st_id="10" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:45 %arr_load_45 = load i11 %arr_addr_45

]]></Node>
<StgValue><ssdm name="arr_load_45"/></StgValue>
</operation>

<operation id="701" st_id="10" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:46 %mul9_0_2 = fmul i32 %arr_load_45, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_0_2"/></StgValue>
</operation>

<operation id="702" st_id="10" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:51 %arr_load_46 = load i11 %arr_addr_46

]]></Node>
<StgValue><ssdm name="arr_load_46"/></StgValue>
</operation>

<operation id="703" st_id="10" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:52 %mul9_0_2_1 = fmul i32 %arr_load_46, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_0_2_1"/></StgValue>
</operation>

<operation id="704" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:54 %add_ln8_47 = add i11 %add_ln8_45, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_47"/></StgValue>
</operation>

<operation id="705" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="64" op_0_bw="11">
<![CDATA[
.split4.0:55 %zext_ln8_48 = zext i11 %add_ln8_47

]]></Node>
<StgValue><ssdm name="zext_ln8_48"/></StgValue>
</operation>

<operation id="706" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:56 %arr_addr_47 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_48

]]></Node>
<StgValue><ssdm name="arr_addr_47"/></StgValue>
</operation>

<operation id="707" st_id="10" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:57 %arr_load_47 = load i11 %arr_addr_47

]]></Node>
<StgValue><ssdm name="arr_load_47"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="708" st_id="11" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:11 %sum_2 = fadd i32 %mul9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>

<operation id="709" st_id="11" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:22 %mul9_0_0_2 = fmul i32 %arr_load_41, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_0_0_2"/></StgValue>
</operation>

<operation id="710" st_id="11" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:28 %mul9_0_1 = fmul i32 %arr_load_42, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_0_1"/></StgValue>
</operation>

<operation id="711" st_id="11" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:34 %mul9_0_1_1 = fmul i32 %arr_load_43, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_0_1_1"/></StgValue>
</operation>

<operation id="712" st_id="11" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:40 %mul9_0_1_2 = fmul i32 %arr_load_44, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_0_1_2"/></StgValue>
</operation>

<operation id="713" st_id="11" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:46 %mul9_0_2 = fmul i32 %arr_load_45, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_0_2"/></StgValue>
</operation>

<operation id="714" st_id="11" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:52 %mul9_0_2_1 = fmul i32 %arr_load_46, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_0_2_1"/></StgValue>
</operation>

<operation id="715" st_id="11" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="32" op_0_bw="11">
<![CDATA[
.split4.0:57 %arr_load_47 = load i11 %arr_addr_47

]]></Node>
<StgValue><ssdm name="arr_load_47"/></StgValue>
</operation>

<operation id="716" st_id="11" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:58 %mul9_0_2_2 = fmul i32 %arr_load_47, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_0_2_2"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="717" st_id="12" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:11 %sum_2 = fadd i32 %mul9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>

<operation id="718" st_id="12" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:34 %mul9_0_1_1 = fmul i32 %arr_load_43, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_0_1_1"/></StgValue>
</operation>

<operation id="719" st_id="12" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:40 %mul9_0_1_2 = fmul i32 %arr_load_44, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_0_1_2"/></StgValue>
</operation>

<operation id="720" st_id="12" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:46 %mul9_0_2 = fmul i32 %arr_load_45, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_0_2"/></StgValue>
</operation>

<operation id="721" st_id="12" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:52 %mul9_0_2_1 = fmul i32 %arr_load_46, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_0_2_1"/></StgValue>
</operation>

<operation id="722" st_id="12" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:58 %mul9_0_2_2 = fmul i32 %arr_load_47, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_0_2_2"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="723" st_id="13" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:11 %sum_2 = fadd i32 %mul9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>

<operation id="724" st_id="13" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:46 %mul9_0_2 = fmul i32 %arr_load_45, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_0_2"/></StgValue>
</operation>

<operation id="725" st_id="13" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:52 %mul9_0_2_1 = fmul i32 %arr_load_46, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_0_2_1"/></StgValue>
</operation>

<operation id="726" st_id="13" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:58 %mul9_0_2_2 = fmul i32 %arr_load_47, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_0_2_2"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="727" st_id="14" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:11 %sum_2 = fadd i32 %mul9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>

<operation id="728" st_id="14" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:58 %mul9_0_2_2 = fmul i32 %arr_load_47, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_0_2_2"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="729" st_id="15" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:11 %sum_2 = fadd i32 %mul9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="730" st_id="16" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:17 %sum_2_0_0_1 = fadd i32 %sum_2, i32 %mul9_0_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_0_1"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="731" st_id="17" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:17 %sum_2_0_0_1 = fadd i32 %sum_2, i32 %mul9_0_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_0_1"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="732" st_id="18" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:17 %sum_2_0_0_1 = fadd i32 %sum_2, i32 %mul9_0_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_0_1"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="733" st_id="19" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:17 %sum_2_0_0_1 = fadd i32 %sum_2, i32 %mul9_0_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_0_1"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="734" st_id="20" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:17 %sum_2_0_0_1 = fadd i32 %sum_2, i32 %mul9_0_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_0_1"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">
</state>

<state id="22" st_id="22">

<operation id="735" st_id="22" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:23 %sum_2_0_0_2 = fadd i32 %sum_2_0_0_1, i32 %mul9_0_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_0_2"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="736" st_id="23" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:23 %sum_2_0_0_2 = fadd i32 %sum_2_0_0_1, i32 %mul9_0_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_0_2"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="737" st_id="24" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:23 %sum_2_0_0_2 = fadd i32 %sum_2_0_0_1, i32 %mul9_0_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_0_2"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="738" st_id="25" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:23 %sum_2_0_0_2 = fadd i32 %sum_2_0_0_1, i32 %mul9_0_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_0_2"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="739" st_id="26" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:23 %sum_2_0_0_2 = fadd i32 %sum_2_0_0_1, i32 %mul9_0_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_0_2"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="740" st_id="27" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:29 %sum_2_0_1 = fadd i32 %sum_2_0_0_2, i32 %mul9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="741" st_id="28" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:29 %sum_2_0_1 = fadd i32 %sum_2_0_0_2, i32 %mul9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="742" st_id="29" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:29 %sum_2_0_1 = fadd i32 %sum_2_0_0_2, i32 %mul9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="743" st_id="30" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:29 %sum_2_0_1 = fadd i32 %sum_2_0_0_2, i32 %mul9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="744" st_id="31" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:29 %sum_2_0_1 = fadd i32 %sum_2_0_0_2, i32 %mul9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">
</state>

<state id="33" st_id="33">

<operation id="745" st_id="33" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:35 %sum_2_0_1_1 = fadd i32 %sum_2_0_1, i32 %mul9_0_1_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1_1"/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="746" st_id="34" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:35 %sum_2_0_1_1 = fadd i32 %sum_2_0_1, i32 %mul9_0_1_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1_1"/></StgValue>
</operation>
</state>

<state id="35" st_id="35">

<operation id="747" st_id="35" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:35 %sum_2_0_1_1 = fadd i32 %sum_2_0_1, i32 %mul9_0_1_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1_1"/></StgValue>
</operation>
</state>

<state id="36" st_id="36">

<operation id="748" st_id="36" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:35 %sum_2_0_1_1 = fadd i32 %sum_2_0_1, i32 %mul9_0_1_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1_1"/></StgValue>
</operation>
</state>

<state id="37" st_id="37">

<operation id="749" st_id="37" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:35 %sum_2_0_1_1 = fadd i32 %sum_2_0_1, i32 %mul9_0_1_1

]]></Node>
<StgValue><ssdm name="sum_2_0_1_1"/></StgValue>
</operation>
</state>

<state id="38" st_id="38">

<operation id="750" st_id="38" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:41 %sum_2_0_1_2 = fadd i32 %sum_2_0_1_1, i32 %mul9_0_1_2

]]></Node>
<StgValue><ssdm name="sum_2_0_1_2"/></StgValue>
</operation>
</state>

<state id="39" st_id="39">

<operation id="751" st_id="39" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:41 %sum_2_0_1_2 = fadd i32 %sum_2_0_1_1, i32 %mul9_0_1_2

]]></Node>
<StgValue><ssdm name="sum_2_0_1_2"/></StgValue>
</operation>
</state>

<state id="40" st_id="40">

<operation id="752" st_id="40" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:41 %sum_2_0_1_2 = fadd i32 %sum_2_0_1_1, i32 %mul9_0_1_2

]]></Node>
<StgValue><ssdm name="sum_2_0_1_2"/></StgValue>
</operation>
</state>

<state id="41" st_id="41">

<operation id="753" st_id="41" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:41 %sum_2_0_1_2 = fadd i32 %sum_2_0_1_1, i32 %mul9_0_1_2

]]></Node>
<StgValue><ssdm name="sum_2_0_1_2"/></StgValue>
</operation>
</state>

<state id="42" st_id="42">

<operation id="754" st_id="42" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:41 %sum_2_0_1_2 = fadd i32 %sum_2_0_1_1, i32 %mul9_0_1_2

]]></Node>
<StgValue><ssdm name="sum_2_0_1_2"/></StgValue>
</operation>
</state>

<state id="43" st_id="43">
</state>

<state id="44" st_id="44">

<operation id="755" st_id="44" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:47 %sum_2_0_2 = fadd i32 %sum_2_0_1_2, i32 %mul9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2"/></StgValue>
</operation>
</state>

<state id="45" st_id="45">

<operation id="756" st_id="45" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:47 %sum_2_0_2 = fadd i32 %sum_2_0_1_2, i32 %mul9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2"/></StgValue>
</operation>
</state>

<state id="46" st_id="46">

<operation id="757" st_id="46" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:47 %sum_2_0_2 = fadd i32 %sum_2_0_1_2, i32 %mul9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2"/></StgValue>
</operation>
</state>

<state id="47" st_id="47">

<operation id="758" st_id="47" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:47 %sum_2_0_2 = fadd i32 %sum_2_0_1_2, i32 %mul9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2"/></StgValue>
</operation>
</state>

<state id="48" st_id="48">

<operation id="759" st_id="48" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:47 %sum_2_0_2 = fadd i32 %sum_2_0_1_2, i32 %mul9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2"/></StgValue>
</operation>
</state>

<state id="49" st_id="49">

<operation id="760" st_id="49" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:53 %sum_2_0_2_1 = fadd i32 %sum_2_0_2, i32 %mul9_0_2_1

]]></Node>
<StgValue><ssdm name="sum_2_0_2_1"/></StgValue>
</operation>
</state>

<state id="50" st_id="50">

<operation id="761" st_id="50" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:53 %sum_2_0_2_1 = fadd i32 %sum_2_0_2, i32 %mul9_0_2_1

]]></Node>
<StgValue><ssdm name="sum_2_0_2_1"/></StgValue>
</operation>
</state>

<state id="51" st_id="51">

<operation id="762" st_id="51" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:53 %sum_2_0_2_1 = fadd i32 %sum_2_0_2, i32 %mul9_0_2_1

]]></Node>
<StgValue><ssdm name="sum_2_0_2_1"/></StgValue>
</operation>
</state>

<state id="52" st_id="52">

<operation id="763" st_id="52" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:53 %sum_2_0_2_1 = fadd i32 %sum_2_0_2, i32 %mul9_0_2_1

]]></Node>
<StgValue><ssdm name="sum_2_0_2_1"/></StgValue>
</operation>
</state>

<state id="53" st_id="53">

<operation id="764" st_id="53" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:53 %sum_2_0_2_1 = fadd i32 %sum_2_0_2, i32 %mul9_0_2_1

]]></Node>
<StgValue><ssdm name="sum_2_0_2_1"/></StgValue>
</operation>
</state>

<state id="54" st_id="54">
</state>

<state id="55" st_id="55">

<operation id="765" st_id="55" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:59 %sum_2_0_2_2 = fadd i32 %sum_2_0_2_1, i32 %mul9_0_2_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2_2"/></StgValue>
</operation>
</state>

<state id="56" st_id="56">

<operation id="766" st_id="56" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:59 %sum_2_0_2_2 = fadd i32 %sum_2_0_2_1, i32 %mul9_0_2_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2_2"/></StgValue>
</operation>
</state>

<state id="57" st_id="57">

<operation id="767" st_id="57" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:59 %sum_2_0_2_2 = fadd i32 %sum_2_0_2_1, i32 %mul9_0_2_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2_2"/></StgValue>
</operation>
</state>

<state id="58" st_id="58">

<operation id="768" st_id="58" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:59 %sum_2_0_2_2 = fadd i32 %sum_2_0_2_1, i32 %mul9_0_2_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2_2"/></StgValue>
</operation>
</state>

<state id="59" st_id="59">

<operation id="769" st_id="59" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.0:59 %sum_2_0_2_2 = fadd i32 %sum_2_0_2_1, i32 %mul9_0_2_2

]]></Node>
<StgValue><ssdm name="sum_2_0_2_2"/></StgValue>
</operation>
</state>

<state id="60" st_id="60">

<operation id="770" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="64" op_0_bw="33">
<![CDATA[
.split4.0:1 %t_3_0_cast = zext i33 %t_3_0

]]></Node>
<StgValue><ssdm name="t_3_0_cast"/></StgValue>
</operation>

<operation id="771" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.0:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="772" st_id="60" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.0:60 %add_ln58 = add i33 %t_3_0, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58"/></StgValue>
</operation>

<operation id="773" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.0:61 %out_addr = getelementptr i32 %out_r, i64 0, i64 %t_3_0_cast

]]></Node>
<StgValue><ssdm name="out_addr"/></StgValue>
</operation>

<operation id="774" st_id="60" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.0:62 %store_ln58 = store i32 %sum_2_0_2_2, i11 %out_addr

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="775" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="0">
<![CDATA[
.split4.0:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="61" st_id="61">

<operation id="776" st_id="61" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="120" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.0:0 %add_ln44_2 = add i32 %zext_ln44_2, i32 %t_0

]]></Node>
<StgValue><ssdm name="add_ln44_2"/></StgValue>
</operation>

<operation id="777" st_id="61" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="121" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.0:1 %add_ln44_3 = add i64 %i_0, i64 1

]]></Node>
<StgValue><ssdm name="add_ln44_3"/></StgValue>
</operation>

<operation id="778" st_id="61" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="122" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.0:2 %icmp_ln44_1 = icmp_slt  i64 %add_ln44_3, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_1"/></StgValue>
</operation>

<operation id="779" st_id="61" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="123" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.0:3 %br_ln44 = br i1 %icmp_ln44_1, void %._crit_edge13.loopexit, void %.lr.ph.1

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="780" st_id="61" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="126" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.1:1 %empty_107 = add i11 %trunc_ln44, i11 2

]]></Node>
<StgValue><ssdm name="empty_107"/></StgValue>
</operation>

<operation id="781" st_id="61" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="127" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.1:2 %empty_108 = mul i11 %empty_107, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_108"/></StgValue>
</operation>
</state>

<state id="62" st_id="62">

<operation id="782" st_id="62" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.1:2 %empty_108 = mul i11 %empty_107, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_108"/></StgValue>
</operation>
</state>

<state id="63" st_id="63">

<operation id="783" st_id="63" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.1:2 %empty_108 = mul i11 %empty_107, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_108"/></StgValue>
</operation>
</state>

<state id="64" st_id="64">

<operation id="784" st_id="64" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.1:0 %add_ln44_2_cast = sext i32 %add_ln44_2

]]></Node>
<StgValue><ssdm name="add_ln44_2_cast"/></StgValue>
</operation>

<operation id="785" st_id="64" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.1:2 %empty_108 = mul i11 %empty_107, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_108"/></StgValue>
</operation>

<operation id="786" st_id="64" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.1:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="65" st_id="65">

<operation id="787" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="130" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_1 = phi i33 %add_ln58_1, void %.split4.1, i33 %add_ln44_2_cast, void %.lr.ph.1

]]></Node>
<StgValue><ssdm name="t_3_1"/></StgValue>
</operation>

<operation id="788" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="131" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_1 = phi i6 %add_ln47_1, void %.split4.1, i6 1, void %.lr.ph.1

]]></Node>
<StgValue><ssdm name="j_1"/></StgValue>
</operation>

<operation id="789" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="132" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="790" st_id="65" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="133" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_1 = icmp_eq  i6 %j_1, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_1"/></StgValue>
</operation>

<operation id="791" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="134" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_106 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_106"/></StgValue>
</operation>

<operation id="792" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="135" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_1, void %.split4.1, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="793" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="11" op_0_bw="6">
<![CDATA[
.split4.1:2 %j_1_cast = zext i6 %j_1

]]></Node>
<StgValue><ssdm name="j_1_cast"/></StgValue>
</operation>

<operation id="794" st_id="65" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="141" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.1:4 %empty_109 = add i6 %j_1, i6 63

]]></Node>
<StgValue><ssdm name="empty_109"/></StgValue>
</operation>

<operation id="795" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="142" bw="11" op_0_bw="6">
<![CDATA[
.split4.1:5 %zext_ln8_49 = zext i6 %empty_109

]]></Node>
<StgValue><ssdm name="zext_ln8_49"/></StgValue>
</operation>

<operation id="796" st_id="65" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="143" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:6 %add_ln8_48 = add i11 %zext_ln8_49, i11 %empty_101

]]></Node>
<StgValue><ssdm name="add_ln8_48"/></StgValue>
</operation>

<operation id="797" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="144" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:7 %zext_ln8_50 = zext i11 %add_ln8_48

]]></Node>
<StgValue><ssdm name="zext_ln8_50"/></StgValue>
</operation>

<operation id="798" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="145" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:8 %arr_addr_48 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_50

]]></Node>
<StgValue><ssdm name="arr_addr_48"/></StgValue>
</operation>

<operation id="799" st_id="65" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="146" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:9 %arr_load_48 = load i11 %arr_addr_48

]]></Node>
<StgValue><ssdm name="arr_load_48"/></StgValue>
</operation>

<operation id="800" st_id="65" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="149" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:12 %add_ln8_49 = add i11 %j_1_cast, i11 %empty_101

]]></Node>
<StgValue><ssdm name="add_ln8_49"/></StgValue>
</operation>

<operation id="801" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="150" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:13 %zext_ln8_51 = zext i11 %add_ln8_49

]]></Node>
<StgValue><ssdm name="zext_ln8_51"/></StgValue>
</operation>

<operation id="802" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:14 %arr_addr_49 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_51

]]></Node>
<StgValue><ssdm name="arr_addr_49"/></StgValue>
</operation>

<operation id="803" st_id="65" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:15 %arr_load_49 = load i11 %arr_addr_49

]]></Node>
<StgValue><ssdm name="arr_load_49"/></StgValue>
</operation>
</state>

<state id="66" st_id="66">

<operation id="804" st_id="66" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="146" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:9 %arr_load_48 = load i11 %arr_addr_48

]]></Node>
<StgValue><ssdm name="arr_load_48"/></StgValue>
</operation>

<operation id="805" st_id="66" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:10 %mul9_1 = fmul i32 %arr_load_48, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_1"/></StgValue>
</operation>

<operation id="806" st_id="66" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:15 %arr_load_49 = load i11 %arr_addr_49

]]></Node>
<StgValue><ssdm name="arr_load_49"/></StgValue>
</operation>

<operation id="807" st_id="66" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:16 %mul9_1_0_1 = fmul i32 %arr_load_49, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_1_0_1"/></StgValue>
</operation>

<operation id="808" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:18 %add_ln8_50 = add i11 %add_ln8_48, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_50"/></StgValue>
</operation>

<operation id="809" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="156" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:19 %zext_ln8_52 = zext i11 %add_ln8_50

]]></Node>
<StgValue><ssdm name="zext_ln8_52"/></StgValue>
</operation>

<operation id="810" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:20 %arr_addr_50 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_52

]]></Node>
<StgValue><ssdm name="arr_addr_50"/></StgValue>
</operation>

<operation id="811" st_id="66" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:21 %arr_load_50 = load i11 %arr_addr_50

]]></Node>
<StgValue><ssdm name="arr_load_50"/></StgValue>
</operation>

<operation id="812" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="161" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:24 %add_ln8_51 = add i11 %zext_ln8_49, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_51"/></StgValue>
</operation>

<operation id="813" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="162" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:25 %zext_ln8_53 = zext i11 %add_ln8_51

]]></Node>
<StgValue><ssdm name="zext_ln8_53"/></StgValue>
</operation>

<operation id="814" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="163" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:26 %arr_addr_51 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_53

]]></Node>
<StgValue><ssdm name="arr_addr_51"/></StgValue>
</operation>

<operation id="815" st_id="66" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="164" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:27 %arr_load_51 = load i11 %arr_addr_51

]]></Node>
<StgValue><ssdm name="arr_load_51"/></StgValue>
</operation>
</state>

<state id="67" st_id="67">

<operation id="816" st_id="67" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:10 %mul9_1 = fmul i32 %arr_load_48, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_1"/></StgValue>
</operation>

<operation id="817" st_id="67" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:16 %mul9_1_0_1 = fmul i32 %arr_load_49, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_1_0_1"/></StgValue>
</operation>

<operation id="818" st_id="67" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:21 %arr_load_50 = load i11 %arr_addr_50

]]></Node>
<StgValue><ssdm name="arr_load_50"/></StgValue>
</operation>

<operation id="819" st_id="67" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:22 %mul9_1_0_2 = fmul i32 %arr_load_50, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_1_0_2"/></StgValue>
</operation>

<operation id="820" st_id="67" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="164" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:27 %arr_load_51 = load i11 %arr_addr_51

]]></Node>
<StgValue><ssdm name="arr_load_51"/></StgValue>
</operation>

<operation id="821" st_id="67" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="165" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:28 %mul9_1_1 = fmul i32 %arr_load_51, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_1_1"/></StgValue>
</operation>

<operation id="822" st_id="67" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="167" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:30 %add_ln8_52 = add i11 %j_1_cast, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_52"/></StgValue>
</operation>

<operation id="823" st_id="67" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="168" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:31 %zext_ln8_54 = zext i11 %add_ln8_52

]]></Node>
<StgValue><ssdm name="zext_ln8_54"/></StgValue>
</operation>

<operation id="824" st_id="67" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="169" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:32 %arr_addr_52 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_54

]]></Node>
<StgValue><ssdm name="arr_addr_52"/></StgValue>
</operation>

<operation id="825" st_id="67" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="170" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:33 %arr_load_52 = load i11 %arr_addr_52

]]></Node>
<StgValue><ssdm name="arr_load_52"/></StgValue>
</operation>

<operation id="826" st_id="67" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="173" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:36 %add_ln8_53 = add i11 %add_ln8_51, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_53"/></StgValue>
</operation>

<operation id="827" st_id="67" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="174" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:37 %zext_ln8_55 = zext i11 %add_ln8_53

]]></Node>
<StgValue><ssdm name="zext_ln8_55"/></StgValue>
</operation>

<operation id="828" st_id="67" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="175" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:38 %arr_addr_53 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_55

]]></Node>
<StgValue><ssdm name="arr_addr_53"/></StgValue>
</operation>

<operation id="829" st_id="67" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="176" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:39 %arr_load_53 = load i11 %arr_addr_53

]]></Node>
<StgValue><ssdm name="arr_load_53"/></StgValue>
</operation>
</state>

<state id="68" st_id="68">

<operation id="830" st_id="68" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:10 %mul9_1 = fmul i32 %arr_load_48, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_1"/></StgValue>
</operation>

<operation id="831" st_id="68" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:16 %mul9_1_0_1 = fmul i32 %arr_load_49, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_1_0_1"/></StgValue>
</operation>

<operation id="832" st_id="68" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:22 %mul9_1_0_2 = fmul i32 %arr_load_50, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_1_0_2"/></StgValue>
</operation>

<operation id="833" st_id="68" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="165" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:28 %mul9_1_1 = fmul i32 %arr_load_51, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_1_1"/></StgValue>
</operation>

<operation id="834" st_id="68" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="170" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:33 %arr_load_52 = load i11 %arr_addr_52

]]></Node>
<StgValue><ssdm name="arr_load_52"/></StgValue>
</operation>

<operation id="835" st_id="68" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:34 %mul9_1_1_1 = fmul i32 %arr_load_52, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_1_1_1"/></StgValue>
</operation>

<operation id="836" st_id="68" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="176" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:39 %arr_load_53 = load i11 %arr_addr_53

]]></Node>
<StgValue><ssdm name="arr_load_53"/></StgValue>
</operation>

<operation id="837" st_id="68" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:40 %mul9_1_1_2 = fmul i32 %arr_load_53, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_1_1_2"/></StgValue>
</operation>

<operation id="838" st_id="68" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="179" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:42 %add_ln8_54 = add i11 %zext_ln8_49, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_54"/></StgValue>
</operation>

<operation id="839" st_id="68" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="180" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:43 %zext_ln8_56 = zext i11 %add_ln8_54

]]></Node>
<StgValue><ssdm name="zext_ln8_56"/></StgValue>
</operation>

<operation id="840" st_id="68" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="181" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:44 %arr_addr_54 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_56

]]></Node>
<StgValue><ssdm name="arr_addr_54"/></StgValue>
</operation>

<operation id="841" st_id="68" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="182" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:45 %arr_load_54 = load i11 %arr_addr_54

]]></Node>
<StgValue><ssdm name="arr_load_54"/></StgValue>
</operation>

<operation id="842" st_id="68" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="185" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:48 %add_ln8_55 = add i11 %j_1_cast, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_55"/></StgValue>
</operation>

<operation id="843" st_id="68" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="186" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:49 %zext_ln8_57 = zext i11 %add_ln8_55

]]></Node>
<StgValue><ssdm name="zext_ln8_57"/></StgValue>
</operation>

<operation id="844" st_id="68" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="187" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:50 %arr_addr_55 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_57

]]></Node>
<StgValue><ssdm name="arr_addr_55"/></StgValue>
</operation>

<operation id="845" st_id="68" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="188" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:51 %arr_load_55 = load i11 %arr_addr_55

]]></Node>
<StgValue><ssdm name="arr_load_55"/></StgValue>
</operation>
</state>

<state id="69" st_id="69">

<operation id="846" st_id="69" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="137" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.1:0 %add_ln47_1 = add i6 %j_1, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_1"/></StgValue>
</operation>

<operation id="847" st_id="69" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="147" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:10 %mul9_1 = fmul i32 %arr_load_48, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_1"/></StgValue>
</operation>

<operation id="848" st_id="69" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:16 %mul9_1_0_1 = fmul i32 %arr_load_49, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_1_0_1"/></StgValue>
</operation>

<operation id="849" st_id="69" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:22 %mul9_1_0_2 = fmul i32 %arr_load_50, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_1_0_2"/></StgValue>
</operation>

<operation id="850" st_id="69" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="165" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:28 %mul9_1_1 = fmul i32 %arr_load_51, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_1_1"/></StgValue>
</operation>

<operation id="851" st_id="69" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:34 %mul9_1_1_1 = fmul i32 %arr_load_52, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_1_1_1"/></StgValue>
</operation>

<operation id="852" st_id="69" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:40 %mul9_1_1_2 = fmul i32 %arr_load_53, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_1_1_2"/></StgValue>
</operation>

<operation id="853" st_id="69" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="182" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:45 %arr_load_54 = load i11 %arr_addr_54

]]></Node>
<StgValue><ssdm name="arr_load_54"/></StgValue>
</operation>

<operation id="854" st_id="69" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:46 %mul9_1_2 = fmul i32 %arr_load_54, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_1_2"/></StgValue>
</operation>

<operation id="855" st_id="69" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="188" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:51 %arr_load_55 = load i11 %arr_addr_55

]]></Node>
<StgValue><ssdm name="arr_load_55"/></StgValue>
</operation>

<operation id="856" st_id="69" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:52 %mul9_1_2_1 = fmul i32 %arr_load_55, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_1_2_1"/></StgValue>
</operation>

<operation id="857" st_id="69" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="191" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:54 %add_ln8_56 = add i11 %add_ln8_54, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_56"/></StgValue>
</operation>

<operation id="858" st_id="69" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="192" bw="64" op_0_bw="11">
<![CDATA[
.split4.1:55 %zext_ln8_58 = zext i11 %add_ln8_56

]]></Node>
<StgValue><ssdm name="zext_ln8_58"/></StgValue>
</operation>

<operation id="859" st_id="69" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="193" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:56 %arr_addr_56 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_58

]]></Node>
<StgValue><ssdm name="arr_addr_56"/></StgValue>
</operation>

<operation id="860" st_id="69" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="194" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:57 %arr_load_56 = load i11 %arr_addr_56

]]></Node>
<StgValue><ssdm name="arr_load_56"/></StgValue>
</operation>
</state>

<state id="70" st_id="70">

<operation id="861" st_id="70" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:11 %sum_2_1 = fadd i32 %mul9_1, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_1"/></StgValue>
</operation>

<operation id="862" st_id="70" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:22 %mul9_1_0_2 = fmul i32 %arr_load_50, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_1_0_2"/></StgValue>
</operation>

<operation id="863" st_id="70" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="165" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:28 %mul9_1_1 = fmul i32 %arr_load_51, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_1_1"/></StgValue>
</operation>

<operation id="864" st_id="70" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:34 %mul9_1_1_1 = fmul i32 %arr_load_52, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_1_1_1"/></StgValue>
</operation>

<operation id="865" st_id="70" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:40 %mul9_1_1_2 = fmul i32 %arr_load_53, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_1_1_2"/></StgValue>
</operation>

<operation id="866" st_id="70" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:46 %mul9_1_2 = fmul i32 %arr_load_54, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_1_2"/></StgValue>
</operation>

<operation id="867" st_id="70" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:52 %mul9_1_2_1 = fmul i32 %arr_load_55, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_1_2_1"/></StgValue>
</operation>

<operation id="868" st_id="70" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="194" bw="32" op_0_bw="11">
<![CDATA[
.split4.1:57 %arr_load_56 = load i11 %arr_addr_56

]]></Node>
<StgValue><ssdm name="arr_load_56"/></StgValue>
</operation>

<operation id="869" st_id="70" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:58 %mul9_1_2_2 = fmul i32 %arr_load_56, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_1_2_2"/></StgValue>
</operation>
</state>

<state id="71" st_id="71">

<operation id="870" st_id="71" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:11 %sum_2_1 = fadd i32 %mul9_1, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_1"/></StgValue>
</operation>

<operation id="871" st_id="71" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:34 %mul9_1_1_1 = fmul i32 %arr_load_52, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_1_1_1"/></StgValue>
</operation>

<operation id="872" st_id="71" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:40 %mul9_1_1_2 = fmul i32 %arr_load_53, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_1_1_2"/></StgValue>
</operation>

<operation id="873" st_id="71" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:46 %mul9_1_2 = fmul i32 %arr_load_54, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_1_2"/></StgValue>
</operation>

<operation id="874" st_id="71" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:52 %mul9_1_2_1 = fmul i32 %arr_load_55, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_1_2_1"/></StgValue>
</operation>

<operation id="875" st_id="71" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:58 %mul9_1_2_2 = fmul i32 %arr_load_56, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_1_2_2"/></StgValue>
</operation>
</state>

<state id="72" st_id="72">

<operation id="876" st_id="72" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:11 %sum_2_1 = fadd i32 %mul9_1, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_1"/></StgValue>
</operation>

<operation id="877" st_id="72" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:46 %mul9_1_2 = fmul i32 %arr_load_54, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_1_2"/></StgValue>
</operation>

<operation id="878" st_id="72" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:52 %mul9_1_2_1 = fmul i32 %arr_load_55, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_1_2_1"/></StgValue>
</operation>

<operation id="879" st_id="72" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:58 %mul9_1_2_2 = fmul i32 %arr_load_56, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_1_2_2"/></StgValue>
</operation>
</state>

<state id="73" st_id="73">

<operation id="880" st_id="73" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:11 %sum_2_1 = fadd i32 %mul9_1, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_1"/></StgValue>
</operation>

<operation id="881" st_id="73" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:58 %mul9_1_2_2 = fmul i32 %arr_load_56, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_1_2_2"/></StgValue>
</operation>
</state>

<state id="74" st_id="74">

<operation id="882" st_id="74" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:11 %sum_2_1 = fadd i32 %mul9_1, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_1"/></StgValue>
</operation>
</state>

<state id="75" st_id="75">

<operation id="883" st_id="75" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:17 %sum_2_1_0_1 = fadd i32 %sum_2_1, i32 %mul9_1_0_1

]]></Node>
<StgValue><ssdm name="sum_2_1_0_1"/></StgValue>
</operation>
</state>

<state id="76" st_id="76">

<operation id="884" st_id="76" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:17 %sum_2_1_0_1 = fadd i32 %sum_2_1, i32 %mul9_1_0_1

]]></Node>
<StgValue><ssdm name="sum_2_1_0_1"/></StgValue>
</operation>
</state>

<state id="77" st_id="77">

<operation id="885" st_id="77" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:17 %sum_2_1_0_1 = fadd i32 %sum_2_1, i32 %mul9_1_0_1

]]></Node>
<StgValue><ssdm name="sum_2_1_0_1"/></StgValue>
</operation>
</state>

<state id="78" st_id="78">

<operation id="886" st_id="78" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:17 %sum_2_1_0_1 = fadd i32 %sum_2_1, i32 %mul9_1_0_1

]]></Node>
<StgValue><ssdm name="sum_2_1_0_1"/></StgValue>
</operation>
</state>

<state id="79" st_id="79">

<operation id="887" st_id="79" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:17 %sum_2_1_0_1 = fadd i32 %sum_2_1, i32 %mul9_1_0_1

]]></Node>
<StgValue><ssdm name="sum_2_1_0_1"/></StgValue>
</operation>
</state>

<state id="80" st_id="80">
</state>

<state id="81" st_id="81">

<operation id="888" st_id="81" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:23 %sum_2_1_0_2 = fadd i32 %sum_2_1_0_1, i32 %mul9_1_0_2

]]></Node>
<StgValue><ssdm name="sum_2_1_0_2"/></StgValue>
</operation>
</state>

<state id="82" st_id="82">

<operation id="889" st_id="82" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:23 %sum_2_1_0_2 = fadd i32 %sum_2_1_0_1, i32 %mul9_1_0_2

]]></Node>
<StgValue><ssdm name="sum_2_1_0_2"/></StgValue>
</operation>
</state>

<state id="83" st_id="83">

<operation id="890" st_id="83" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:23 %sum_2_1_0_2 = fadd i32 %sum_2_1_0_1, i32 %mul9_1_0_2

]]></Node>
<StgValue><ssdm name="sum_2_1_0_2"/></StgValue>
</operation>
</state>

<state id="84" st_id="84">

<operation id="891" st_id="84" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:23 %sum_2_1_0_2 = fadd i32 %sum_2_1_0_1, i32 %mul9_1_0_2

]]></Node>
<StgValue><ssdm name="sum_2_1_0_2"/></StgValue>
</operation>
</state>

<state id="85" st_id="85">

<operation id="892" st_id="85" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:23 %sum_2_1_0_2 = fadd i32 %sum_2_1_0_1, i32 %mul9_1_0_2

]]></Node>
<StgValue><ssdm name="sum_2_1_0_2"/></StgValue>
</operation>
</state>

<state id="86" st_id="86">

<operation id="893" st_id="86" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:29 %sum_2_1_1 = fadd i32 %sum_2_1_0_2, i32 %mul9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1"/></StgValue>
</operation>
</state>

<state id="87" st_id="87">

<operation id="894" st_id="87" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:29 %sum_2_1_1 = fadd i32 %sum_2_1_0_2, i32 %mul9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1"/></StgValue>
</operation>
</state>

<state id="88" st_id="88">

<operation id="895" st_id="88" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:29 %sum_2_1_1 = fadd i32 %sum_2_1_0_2, i32 %mul9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1"/></StgValue>
</operation>
</state>

<state id="89" st_id="89">

<operation id="896" st_id="89" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:29 %sum_2_1_1 = fadd i32 %sum_2_1_0_2, i32 %mul9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1"/></StgValue>
</operation>
</state>

<state id="90" st_id="90">

<operation id="897" st_id="90" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:29 %sum_2_1_1 = fadd i32 %sum_2_1_0_2, i32 %mul9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1"/></StgValue>
</operation>
</state>

<state id="91" st_id="91">
</state>

<state id="92" st_id="92">

<operation id="898" st_id="92" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:35 %sum_2_1_1_1 = fadd i32 %sum_2_1_1, i32 %mul9_1_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1_1"/></StgValue>
</operation>
</state>

<state id="93" st_id="93">

<operation id="899" st_id="93" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:35 %sum_2_1_1_1 = fadd i32 %sum_2_1_1, i32 %mul9_1_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1_1"/></StgValue>
</operation>
</state>

<state id="94" st_id="94">

<operation id="900" st_id="94" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:35 %sum_2_1_1_1 = fadd i32 %sum_2_1_1, i32 %mul9_1_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1_1"/></StgValue>
</operation>
</state>

<state id="95" st_id="95">

<operation id="901" st_id="95" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:35 %sum_2_1_1_1 = fadd i32 %sum_2_1_1, i32 %mul9_1_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1_1"/></StgValue>
</operation>
</state>

<state id="96" st_id="96">

<operation id="902" st_id="96" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:35 %sum_2_1_1_1 = fadd i32 %sum_2_1_1, i32 %mul9_1_1_1

]]></Node>
<StgValue><ssdm name="sum_2_1_1_1"/></StgValue>
</operation>
</state>

<state id="97" st_id="97">

<operation id="903" st_id="97" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:41 %sum_2_1_1_2 = fadd i32 %sum_2_1_1_1, i32 %mul9_1_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_1_2"/></StgValue>
</operation>
</state>

<state id="98" st_id="98">

<operation id="904" st_id="98" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:41 %sum_2_1_1_2 = fadd i32 %sum_2_1_1_1, i32 %mul9_1_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_1_2"/></StgValue>
</operation>
</state>

<state id="99" st_id="99">

<operation id="905" st_id="99" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:41 %sum_2_1_1_2 = fadd i32 %sum_2_1_1_1, i32 %mul9_1_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_1_2"/></StgValue>
</operation>
</state>

<state id="100" st_id="100">

<operation id="906" st_id="100" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:41 %sum_2_1_1_2 = fadd i32 %sum_2_1_1_1, i32 %mul9_1_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_1_2"/></StgValue>
</operation>
</state>

<state id="101" st_id="101">

<operation id="907" st_id="101" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:41 %sum_2_1_1_2 = fadd i32 %sum_2_1_1_1, i32 %mul9_1_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_1_2"/></StgValue>
</operation>
</state>

<state id="102" st_id="102">
</state>

<state id="103" st_id="103">

<operation id="908" st_id="103" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:47 %sum_2_1_2 = fadd i32 %sum_2_1_1_2, i32 %mul9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2"/></StgValue>
</operation>
</state>

<state id="104" st_id="104">

<operation id="909" st_id="104" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:47 %sum_2_1_2 = fadd i32 %sum_2_1_1_2, i32 %mul9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2"/></StgValue>
</operation>
</state>

<state id="105" st_id="105">

<operation id="910" st_id="105" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:47 %sum_2_1_2 = fadd i32 %sum_2_1_1_2, i32 %mul9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2"/></StgValue>
</operation>
</state>

<state id="106" st_id="106">

<operation id="911" st_id="106" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:47 %sum_2_1_2 = fadd i32 %sum_2_1_1_2, i32 %mul9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2"/></StgValue>
</operation>
</state>

<state id="107" st_id="107">

<operation id="912" st_id="107" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:47 %sum_2_1_2 = fadd i32 %sum_2_1_1_2, i32 %mul9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2"/></StgValue>
</operation>
</state>

<state id="108" st_id="108">

<operation id="913" st_id="108" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:53 %sum_2_1_2_1 = fadd i32 %sum_2_1_2, i32 %mul9_1_2_1

]]></Node>
<StgValue><ssdm name="sum_2_1_2_1"/></StgValue>
</operation>
</state>

<state id="109" st_id="109">

<operation id="914" st_id="109" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:53 %sum_2_1_2_1 = fadd i32 %sum_2_1_2, i32 %mul9_1_2_1

]]></Node>
<StgValue><ssdm name="sum_2_1_2_1"/></StgValue>
</operation>
</state>

<state id="110" st_id="110">

<operation id="915" st_id="110" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:53 %sum_2_1_2_1 = fadd i32 %sum_2_1_2, i32 %mul9_1_2_1

]]></Node>
<StgValue><ssdm name="sum_2_1_2_1"/></StgValue>
</operation>
</state>

<state id="111" st_id="111">

<operation id="916" st_id="111" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:53 %sum_2_1_2_1 = fadd i32 %sum_2_1_2, i32 %mul9_1_2_1

]]></Node>
<StgValue><ssdm name="sum_2_1_2_1"/></StgValue>
</operation>
</state>

<state id="112" st_id="112">

<operation id="917" st_id="112" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:53 %sum_2_1_2_1 = fadd i32 %sum_2_1_2, i32 %mul9_1_2_1

]]></Node>
<StgValue><ssdm name="sum_2_1_2_1"/></StgValue>
</operation>
</state>

<state id="113" st_id="113">
</state>

<state id="114" st_id="114">

<operation id="918" st_id="114" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:59 %sum_2_1_2_2 = fadd i32 %sum_2_1_2_1, i32 %mul9_1_2_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2_2"/></StgValue>
</operation>
</state>

<state id="115" st_id="115">

<operation id="919" st_id="115" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:59 %sum_2_1_2_2 = fadd i32 %sum_2_1_2_1, i32 %mul9_1_2_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2_2"/></StgValue>
</operation>
</state>

<state id="116" st_id="116">

<operation id="920" st_id="116" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:59 %sum_2_1_2_2 = fadd i32 %sum_2_1_2_1, i32 %mul9_1_2_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2_2"/></StgValue>
</operation>
</state>

<state id="117" st_id="117">

<operation id="921" st_id="117" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:59 %sum_2_1_2_2 = fadd i32 %sum_2_1_2_1, i32 %mul9_1_2_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2_2"/></StgValue>
</operation>
</state>

<state id="118" st_id="118">

<operation id="922" st_id="118" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.1:59 %sum_2_1_2_2 = fadd i32 %sum_2_1_2_1, i32 %mul9_1_2_2

]]></Node>
<StgValue><ssdm name="sum_2_1_2_2"/></StgValue>
</operation>
</state>

<state id="119" st_id="119">

<operation id="923" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="138" bw="64" op_0_bw="33">
<![CDATA[
.split4.1:1 %t_3_1_cast = zext i33 %t_3_1

]]></Node>
<StgValue><ssdm name="t_3_1_cast"/></StgValue>
</operation>

<operation id="924" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.1:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="925" st_id="119" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="197" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.1:60 %add_ln58_1 = add i33 %t_3_1, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_1"/></StgValue>
</operation>

<operation id="926" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="198" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.1:61 %out_addr_10 = getelementptr i32 %out_r, i64 0, i64 %t_3_1_cast

]]></Node>
<StgValue><ssdm name="out_addr_10"/></StgValue>
</operation>

<operation id="927" st_id="119" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="199" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.1:62 %store_ln58 = store i32 %sum_2_1_2_2, i11 %out_addr_10

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="928" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="200" bw="0" op_0_bw="0">
<![CDATA[
.split4.1:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="120" st_id="120">

<operation id="929" st_id="120" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="202" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.1:0 %add_ln44_4 = add i32 %zext_ln44_2, i32 %add_ln44_2

]]></Node>
<StgValue><ssdm name="add_ln44_4"/></StgValue>
</operation>

<operation id="930" st_id="120" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="203" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.1:1 %add_ln44_5 = add i64 %i_0, i64 2

]]></Node>
<StgValue><ssdm name="add_ln44_5"/></StgValue>
</operation>

<operation id="931" st_id="120" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="204" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.1:2 %icmp_ln44_2 = icmp_slt  i64 %add_ln44_5, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_2"/></StgValue>
</operation>

<operation id="932" st_id="120" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="205" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.1:3 %br_ln44 = br i1 %icmp_ln44_2, void %._crit_edge13.loopexit, void %.lr.ph.2

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="933" st_id="120" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_2" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="208" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.2:1 %empty_111 = add i11 %trunc_ln44, i11 3

]]></Node>
<StgValue><ssdm name="empty_111"/></StgValue>
</operation>

<operation id="934" st_id="120" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_2" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="209" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.2:2 %empty_112 = mul i11 %empty_111, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_112"/></StgValue>
</operation>
</state>

<state id="121" st_id="121">

<operation id="935" st_id="121" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="209" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.2:2 %empty_112 = mul i11 %empty_111, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_112"/></StgValue>
</operation>
</state>

<state id="122" st_id="122">

<operation id="936" st_id="122" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="209" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.2:2 %empty_112 = mul i11 %empty_111, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_112"/></StgValue>
</operation>
</state>

<state id="123" st_id="123">

<operation id="937" st_id="123" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="207" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.2:0 %add_ln44_5_cast = sext i32 %add_ln44_4

]]></Node>
<StgValue><ssdm name="add_ln44_5_cast"/></StgValue>
</operation>

<operation id="938" st_id="123" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="209" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.2:2 %empty_112 = mul i11 %empty_111, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_112"/></StgValue>
</operation>

<operation id="939" st_id="123" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="210" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.2:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="124" st_id="124">

<operation id="940" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="212" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_2 = phi i33 %add_ln58_2, void %.split4.2, i33 %add_ln44_5_cast, void %.lr.ph.2

]]></Node>
<StgValue><ssdm name="t_3_2"/></StgValue>
</operation>

<operation id="941" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="213" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_2 = phi i6 %add_ln47_2, void %.split4.2, i6 1, void %.lr.ph.2

]]></Node>
<StgValue><ssdm name="j_2"/></StgValue>
</operation>

<operation id="942" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="214" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="943" st_id="124" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="215" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_2 = icmp_eq  i6 %j_2, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_2"/></StgValue>
</operation>

<operation id="944" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="216" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_110 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_110"/></StgValue>
</operation>

<operation id="945" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="217" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_2, void %.split4.2, void %._crit_edge.loopexit.2

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="946" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="221" bw="11" op_0_bw="6">
<![CDATA[
.split4.2:2 %j_2_cast = zext i6 %j_2

]]></Node>
<StgValue><ssdm name="j_2_cast"/></StgValue>
</operation>

<operation id="947" st_id="124" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="223" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.2:4 %empty_113 = add i6 %j_2, i6 63

]]></Node>
<StgValue><ssdm name="empty_113"/></StgValue>
</operation>

<operation id="948" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="224" bw="11" op_0_bw="6">
<![CDATA[
.split4.2:5 %zext_ln8_59 = zext i6 %empty_113

]]></Node>
<StgValue><ssdm name="zext_ln8_59"/></StgValue>
</operation>

<operation id="949" st_id="124" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="225" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:6 %add_ln8_57 = add i11 %zext_ln8_59, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_57"/></StgValue>
</operation>

<operation id="950" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="226" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:7 %zext_ln8_60 = zext i11 %add_ln8_57

]]></Node>
<StgValue><ssdm name="zext_ln8_60"/></StgValue>
</operation>

<operation id="951" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="227" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:8 %arr_addr_57 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_60

]]></Node>
<StgValue><ssdm name="arr_addr_57"/></StgValue>
</operation>

<operation id="952" st_id="124" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="228" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:9 %arr_load_57 = load i11 %arr_addr_57

]]></Node>
<StgValue><ssdm name="arr_load_57"/></StgValue>
</operation>

<operation id="953" st_id="124" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="231" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:12 %add_ln8_58 = add i11 %j_2_cast, i11 %empty_103

]]></Node>
<StgValue><ssdm name="add_ln8_58"/></StgValue>
</operation>

<operation id="954" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="232" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:13 %zext_ln8_61 = zext i11 %add_ln8_58

]]></Node>
<StgValue><ssdm name="zext_ln8_61"/></StgValue>
</operation>

<operation id="955" st_id="124" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="233" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:14 %arr_addr_58 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_61

]]></Node>
<StgValue><ssdm name="arr_addr_58"/></StgValue>
</operation>

<operation id="956" st_id="124" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="234" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:15 %arr_load_58 = load i11 %arr_addr_58

]]></Node>
<StgValue><ssdm name="arr_load_58"/></StgValue>
</operation>
</state>

<state id="125" st_id="125">

<operation id="957" st_id="125" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="228" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:9 %arr_load_57 = load i11 %arr_addr_57

]]></Node>
<StgValue><ssdm name="arr_load_57"/></StgValue>
</operation>

<operation id="958" st_id="125" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:10 %mul9_2 = fmul i32 %arr_load_57, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_2"/></StgValue>
</operation>

<operation id="959" st_id="125" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="234" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:15 %arr_load_58 = load i11 %arr_addr_58

]]></Node>
<StgValue><ssdm name="arr_load_58"/></StgValue>
</operation>

<operation id="960" st_id="125" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="235" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:16 %mul9_2_0_1 = fmul i32 %arr_load_58, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_2_0_1"/></StgValue>
</operation>

<operation id="961" st_id="125" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="237" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:18 %add_ln8_59 = add i11 %add_ln8_57, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_59"/></StgValue>
</operation>

<operation id="962" st_id="125" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="238" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:19 %zext_ln8_62 = zext i11 %add_ln8_59

]]></Node>
<StgValue><ssdm name="zext_ln8_62"/></StgValue>
</operation>

<operation id="963" st_id="125" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="239" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:20 %arr_addr_59 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_62

]]></Node>
<StgValue><ssdm name="arr_addr_59"/></StgValue>
</operation>

<operation id="964" st_id="125" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="240" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:21 %arr_load_59 = load i11 %arr_addr_59

]]></Node>
<StgValue><ssdm name="arr_load_59"/></StgValue>
</operation>

<operation id="965" st_id="125" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="243" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:24 %add_ln8_60 = add i11 %zext_ln8_59, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_60"/></StgValue>
</operation>

<operation id="966" st_id="125" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="244" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:25 %zext_ln8_63 = zext i11 %add_ln8_60

]]></Node>
<StgValue><ssdm name="zext_ln8_63"/></StgValue>
</operation>

<operation id="967" st_id="125" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="245" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:26 %arr_addr_60 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_63

]]></Node>
<StgValue><ssdm name="arr_addr_60"/></StgValue>
</operation>

<operation id="968" st_id="125" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="246" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:27 %arr_load_60 = load i11 %arr_addr_60

]]></Node>
<StgValue><ssdm name="arr_load_60"/></StgValue>
</operation>
</state>

<state id="126" st_id="126">

<operation id="969" st_id="126" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:10 %mul9_2 = fmul i32 %arr_load_57, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_2"/></StgValue>
</operation>

<operation id="970" st_id="126" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="235" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:16 %mul9_2_0_1 = fmul i32 %arr_load_58, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_2_0_1"/></StgValue>
</operation>

<operation id="971" st_id="126" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="240" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:21 %arr_load_59 = load i11 %arr_addr_59

]]></Node>
<StgValue><ssdm name="arr_load_59"/></StgValue>
</operation>

<operation id="972" st_id="126" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:22 %mul9_2_0_2 = fmul i32 %arr_load_59, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_2_0_2"/></StgValue>
</operation>

<operation id="973" st_id="126" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="246" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:27 %arr_load_60 = load i11 %arr_addr_60

]]></Node>
<StgValue><ssdm name="arr_load_60"/></StgValue>
</operation>

<operation id="974" st_id="126" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="247" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:28 %mul9_2_1 = fmul i32 %arr_load_60, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_2_1"/></StgValue>
</operation>

<operation id="975" st_id="126" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="249" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:30 %add_ln8_61 = add i11 %j_2_cast, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_61"/></StgValue>
</operation>

<operation id="976" st_id="126" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="250" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:31 %zext_ln8_64 = zext i11 %add_ln8_61

]]></Node>
<StgValue><ssdm name="zext_ln8_64"/></StgValue>
</operation>

<operation id="977" st_id="126" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="251" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:32 %arr_addr_61 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_64

]]></Node>
<StgValue><ssdm name="arr_addr_61"/></StgValue>
</operation>

<operation id="978" st_id="126" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="252" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:33 %arr_load_61 = load i11 %arr_addr_61

]]></Node>
<StgValue><ssdm name="arr_load_61"/></StgValue>
</operation>

<operation id="979" st_id="126" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="255" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:36 %add_ln8_62 = add i11 %add_ln8_60, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_62"/></StgValue>
</operation>

<operation id="980" st_id="126" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="256" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:37 %zext_ln8_65 = zext i11 %add_ln8_62

]]></Node>
<StgValue><ssdm name="zext_ln8_65"/></StgValue>
</operation>

<operation id="981" st_id="126" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="257" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:38 %arr_addr_62 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_65

]]></Node>
<StgValue><ssdm name="arr_addr_62"/></StgValue>
</operation>

<operation id="982" st_id="126" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="258" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:39 %arr_load_62 = load i11 %arr_addr_62

]]></Node>
<StgValue><ssdm name="arr_load_62"/></StgValue>
</operation>
</state>

<state id="127" st_id="127">

<operation id="983" st_id="127" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:10 %mul9_2 = fmul i32 %arr_load_57, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_2"/></StgValue>
</operation>

<operation id="984" st_id="127" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="235" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:16 %mul9_2_0_1 = fmul i32 %arr_load_58, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_2_0_1"/></StgValue>
</operation>

<operation id="985" st_id="127" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:22 %mul9_2_0_2 = fmul i32 %arr_load_59, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_2_0_2"/></StgValue>
</operation>

<operation id="986" st_id="127" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="247" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:28 %mul9_2_1 = fmul i32 %arr_load_60, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_2_1"/></StgValue>
</operation>

<operation id="987" st_id="127" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="252" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:33 %arr_load_61 = load i11 %arr_addr_61

]]></Node>
<StgValue><ssdm name="arr_load_61"/></StgValue>
</operation>

<operation id="988" st_id="127" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="253" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:34 %mul9_2_1_1 = fmul i32 %arr_load_61, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_2_1_1"/></StgValue>
</operation>

<operation id="989" st_id="127" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="258" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:39 %arr_load_62 = load i11 %arr_addr_62

]]></Node>
<StgValue><ssdm name="arr_load_62"/></StgValue>
</operation>

<operation id="990" st_id="127" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="259" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:40 %mul9_2_1_2 = fmul i32 %arr_load_62, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_2_1_2"/></StgValue>
</operation>

<operation id="991" st_id="127" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="261" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:42 %add_ln8_63 = add i11 %zext_ln8_59, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_63"/></StgValue>
</operation>

<operation id="992" st_id="127" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="262" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:43 %zext_ln8_66 = zext i11 %add_ln8_63

]]></Node>
<StgValue><ssdm name="zext_ln8_66"/></StgValue>
</operation>

<operation id="993" st_id="127" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="263" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:44 %arr_addr_63 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_66

]]></Node>
<StgValue><ssdm name="arr_addr_63"/></StgValue>
</operation>

<operation id="994" st_id="127" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="264" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:45 %arr_load_63 = load i11 %arr_addr_63

]]></Node>
<StgValue><ssdm name="arr_load_63"/></StgValue>
</operation>

<operation id="995" st_id="127" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="267" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:48 %add_ln8_64 = add i11 %j_2_cast, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_64"/></StgValue>
</operation>

<operation id="996" st_id="127" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="268" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:49 %zext_ln8_67 = zext i11 %add_ln8_64

]]></Node>
<StgValue><ssdm name="zext_ln8_67"/></StgValue>
</operation>

<operation id="997" st_id="127" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="269" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:50 %arr_addr_64 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_67

]]></Node>
<StgValue><ssdm name="arr_addr_64"/></StgValue>
</operation>

<operation id="998" st_id="127" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="270" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:51 %arr_load_64 = load i11 %arr_addr_64

]]></Node>
<StgValue><ssdm name="arr_load_64"/></StgValue>
</operation>
</state>

<state id="128" st_id="128">

<operation id="999" st_id="128" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="219" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.2:0 %add_ln47_2 = add i6 %j_2, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_2"/></StgValue>
</operation>

<operation id="1000" st_id="128" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:10 %mul9_2 = fmul i32 %arr_load_57, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_2"/></StgValue>
</operation>

<operation id="1001" st_id="128" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="235" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:16 %mul9_2_0_1 = fmul i32 %arr_load_58, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_2_0_1"/></StgValue>
</operation>

<operation id="1002" st_id="128" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:22 %mul9_2_0_2 = fmul i32 %arr_load_59, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_2_0_2"/></StgValue>
</operation>

<operation id="1003" st_id="128" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="247" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:28 %mul9_2_1 = fmul i32 %arr_load_60, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_2_1"/></StgValue>
</operation>

<operation id="1004" st_id="128" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="253" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:34 %mul9_2_1_1 = fmul i32 %arr_load_61, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_2_1_1"/></StgValue>
</operation>

<operation id="1005" st_id="128" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="259" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:40 %mul9_2_1_2 = fmul i32 %arr_load_62, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_2_1_2"/></StgValue>
</operation>

<operation id="1006" st_id="128" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="264" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:45 %arr_load_63 = load i11 %arr_addr_63

]]></Node>
<StgValue><ssdm name="arr_load_63"/></StgValue>
</operation>

<operation id="1007" st_id="128" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="265" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:46 %mul9_2_2 = fmul i32 %arr_load_63, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_2_2"/></StgValue>
</operation>

<operation id="1008" st_id="128" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="270" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:51 %arr_load_64 = load i11 %arr_addr_64

]]></Node>
<StgValue><ssdm name="arr_load_64"/></StgValue>
</operation>

<operation id="1009" st_id="128" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="271" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:52 %mul9_2_2_1 = fmul i32 %arr_load_64, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_2_2_1"/></StgValue>
</operation>

<operation id="1010" st_id="128" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="273" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:54 %add_ln8_65 = add i11 %add_ln8_63, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_65"/></StgValue>
</operation>

<operation id="1011" st_id="128" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="274" bw="64" op_0_bw="11">
<![CDATA[
.split4.2:55 %zext_ln8_68 = zext i11 %add_ln8_65

]]></Node>
<StgValue><ssdm name="zext_ln8_68"/></StgValue>
</operation>

<operation id="1012" st_id="128" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="275" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:56 %arr_addr_65 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_68

]]></Node>
<StgValue><ssdm name="arr_addr_65"/></StgValue>
</operation>

<operation id="1013" st_id="128" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="276" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:57 %arr_load_65 = load i11 %arr_addr_65

]]></Node>
<StgValue><ssdm name="arr_load_65"/></StgValue>
</operation>
</state>

<state id="129" st_id="129">

<operation id="1014" st_id="129" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:11 %sum_2_2 = fadd i32 %mul9_2, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_2"/></StgValue>
</operation>

<operation id="1015" st_id="129" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:22 %mul9_2_0_2 = fmul i32 %arr_load_59, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_2_0_2"/></StgValue>
</operation>

<operation id="1016" st_id="129" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="247" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:28 %mul9_2_1 = fmul i32 %arr_load_60, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_2_1"/></StgValue>
</operation>

<operation id="1017" st_id="129" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="253" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:34 %mul9_2_1_1 = fmul i32 %arr_load_61, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_2_1_1"/></StgValue>
</operation>

<operation id="1018" st_id="129" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="259" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:40 %mul9_2_1_2 = fmul i32 %arr_load_62, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_2_1_2"/></StgValue>
</operation>

<operation id="1019" st_id="129" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="265" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:46 %mul9_2_2 = fmul i32 %arr_load_63, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_2_2"/></StgValue>
</operation>

<operation id="1020" st_id="129" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="271" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:52 %mul9_2_2_1 = fmul i32 %arr_load_64, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_2_2_1"/></StgValue>
</operation>

<operation id="1021" st_id="129" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="276" bw="32" op_0_bw="11">
<![CDATA[
.split4.2:57 %arr_load_65 = load i11 %arr_addr_65

]]></Node>
<StgValue><ssdm name="arr_load_65"/></StgValue>
</operation>

<operation id="1022" st_id="129" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="277" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:58 %mul9_2_2_2 = fmul i32 %arr_load_65, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_2_2_2"/></StgValue>
</operation>
</state>

<state id="130" st_id="130">

<operation id="1023" st_id="130" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:11 %sum_2_2 = fadd i32 %mul9_2, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_2"/></StgValue>
</operation>

<operation id="1024" st_id="130" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="253" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:34 %mul9_2_1_1 = fmul i32 %arr_load_61, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_2_1_1"/></StgValue>
</operation>

<operation id="1025" st_id="130" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="259" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:40 %mul9_2_1_2 = fmul i32 %arr_load_62, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_2_1_2"/></StgValue>
</operation>

<operation id="1026" st_id="130" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="265" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:46 %mul9_2_2 = fmul i32 %arr_load_63, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_2_2"/></StgValue>
</operation>

<operation id="1027" st_id="130" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="271" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:52 %mul9_2_2_1 = fmul i32 %arr_load_64, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_2_2_1"/></StgValue>
</operation>

<operation id="1028" st_id="130" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="277" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:58 %mul9_2_2_2 = fmul i32 %arr_load_65, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_2_2_2"/></StgValue>
</operation>
</state>

<state id="131" st_id="131">

<operation id="1029" st_id="131" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:11 %sum_2_2 = fadd i32 %mul9_2, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_2"/></StgValue>
</operation>

<operation id="1030" st_id="131" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="265" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:46 %mul9_2_2 = fmul i32 %arr_load_63, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_2_2"/></StgValue>
</operation>

<operation id="1031" st_id="131" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="271" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:52 %mul9_2_2_1 = fmul i32 %arr_load_64, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_2_2_1"/></StgValue>
</operation>

<operation id="1032" st_id="131" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="277" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:58 %mul9_2_2_2 = fmul i32 %arr_load_65, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_2_2_2"/></StgValue>
</operation>
</state>

<state id="132" st_id="132">

<operation id="1033" st_id="132" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:11 %sum_2_2 = fadd i32 %mul9_2, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_2"/></StgValue>
</operation>

<operation id="1034" st_id="132" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="277" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:58 %mul9_2_2_2 = fmul i32 %arr_load_65, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_2_2_2"/></StgValue>
</operation>
</state>

<state id="133" st_id="133">

<operation id="1035" st_id="133" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:11 %sum_2_2 = fadd i32 %mul9_2, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_2"/></StgValue>
</operation>
</state>

<state id="134" st_id="134">

<operation id="1036" st_id="134" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:17 %sum_2_2_0_1 = fadd i32 %sum_2_2, i32 %mul9_2_0_1

]]></Node>
<StgValue><ssdm name="sum_2_2_0_1"/></StgValue>
</operation>
</state>

<state id="135" st_id="135">

<operation id="1037" st_id="135" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:17 %sum_2_2_0_1 = fadd i32 %sum_2_2, i32 %mul9_2_0_1

]]></Node>
<StgValue><ssdm name="sum_2_2_0_1"/></StgValue>
</operation>
</state>

<state id="136" st_id="136">

<operation id="1038" st_id="136" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:17 %sum_2_2_0_1 = fadd i32 %sum_2_2, i32 %mul9_2_0_1

]]></Node>
<StgValue><ssdm name="sum_2_2_0_1"/></StgValue>
</operation>
</state>

<state id="137" st_id="137">

<operation id="1039" st_id="137" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:17 %sum_2_2_0_1 = fadd i32 %sum_2_2, i32 %mul9_2_0_1

]]></Node>
<StgValue><ssdm name="sum_2_2_0_1"/></StgValue>
</operation>
</state>

<state id="138" st_id="138">

<operation id="1040" st_id="138" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="236" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:17 %sum_2_2_0_1 = fadd i32 %sum_2_2, i32 %mul9_2_0_1

]]></Node>
<StgValue><ssdm name="sum_2_2_0_1"/></StgValue>
</operation>
</state>

<state id="139" st_id="139">
</state>

<state id="140" st_id="140">

<operation id="1041" st_id="140" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:23 %sum_2_2_0_2 = fadd i32 %sum_2_2_0_1, i32 %mul9_2_0_2

]]></Node>
<StgValue><ssdm name="sum_2_2_0_2"/></StgValue>
</operation>
</state>

<state id="141" st_id="141">

<operation id="1042" st_id="141" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:23 %sum_2_2_0_2 = fadd i32 %sum_2_2_0_1, i32 %mul9_2_0_2

]]></Node>
<StgValue><ssdm name="sum_2_2_0_2"/></StgValue>
</operation>
</state>

<state id="142" st_id="142">

<operation id="1043" st_id="142" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:23 %sum_2_2_0_2 = fadd i32 %sum_2_2_0_1, i32 %mul9_2_0_2

]]></Node>
<StgValue><ssdm name="sum_2_2_0_2"/></StgValue>
</operation>
</state>

<state id="143" st_id="143">

<operation id="1044" st_id="143" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:23 %sum_2_2_0_2 = fadd i32 %sum_2_2_0_1, i32 %mul9_2_0_2

]]></Node>
<StgValue><ssdm name="sum_2_2_0_2"/></StgValue>
</operation>
</state>

<state id="144" st_id="144">

<operation id="1045" st_id="144" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:23 %sum_2_2_0_2 = fadd i32 %sum_2_2_0_1, i32 %mul9_2_0_2

]]></Node>
<StgValue><ssdm name="sum_2_2_0_2"/></StgValue>
</operation>
</state>

<state id="145" st_id="145">

<operation id="1046" st_id="145" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="248" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:29 %sum_2_2_1 = fadd i32 %sum_2_2_0_2, i32 %mul9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1"/></StgValue>
</operation>
</state>

<state id="146" st_id="146">

<operation id="1047" st_id="146" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="248" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:29 %sum_2_2_1 = fadd i32 %sum_2_2_0_2, i32 %mul9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1"/></StgValue>
</operation>
</state>

<state id="147" st_id="147">

<operation id="1048" st_id="147" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="248" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:29 %sum_2_2_1 = fadd i32 %sum_2_2_0_2, i32 %mul9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1"/></StgValue>
</operation>
</state>

<state id="148" st_id="148">

<operation id="1049" st_id="148" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="248" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:29 %sum_2_2_1 = fadd i32 %sum_2_2_0_2, i32 %mul9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1"/></StgValue>
</operation>
</state>

<state id="149" st_id="149">

<operation id="1050" st_id="149" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="248" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:29 %sum_2_2_1 = fadd i32 %sum_2_2_0_2, i32 %mul9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1"/></StgValue>
</operation>
</state>

<state id="150" st_id="150">
</state>

<state id="151" st_id="151">

<operation id="1051" st_id="151" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:35 %sum_2_2_1_1 = fadd i32 %sum_2_2_1, i32 %mul9_2_1_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1_1"/></StgValue>
</operation>
</state>

<state id="152" st_id="152">

<operation id="1052" st_id="152" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:35 %sum_2_2_1_1 = fadd i32 %sum_2_2_1, i32 %mul9_2_1_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1_1"/></StgValue>
</operation>
</state>

<state id="153" st_id="153">

<operation id="1053" st_id="153" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:35 %sum_2_2_1_1 = fadd i32 %sum_2_2_1, i32 %mul9_2_1_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1_1"/></StgValue>
</operation>
</state>

<state id="154" st_id="154">

<operation id="1054" st_id="154" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:35 %sum_2_2_1_1 = fadd i32 %sum_2_2_1, i32 %mul9_2_1_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1_1"/></StgValue>
</operation>
</state>

<state id="155" st_id="155">

<operation id="1055" st_id="155" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:35 %sum_2_2_1_1 = fadd i32 %sum_2_2_1, i32 %mul9_2_1_1

]]></Node>
<StgValue><ssdm name="sum_2_2_1_1"/></StgValue>
</operation>
</state>

<state id="156" st_id="156">

<operation id="1056" st_id="156" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:41 %sum_2_2_1_2 = fadd i32 %sum_2_2_1_1, i32 %mul9_2_1_2

]]></Node>
<StgValue><ssdm name="sum_2_2_1_2"/></StgValue>
</operation>
</state>

<state id="157" st_id="157">

<operation id="1057" st_id="157" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:41 %sum_2_2_1_2 = fadd i32 %sum_2_2_1_1, i32 %mul9_2_1_2

]]></Node>
<StgValue><ssdm name="sum_2_2_1_2"/></StgValue>
</operation>
</state>

<state id="158" st_id="158">

<operation id="1058" st_id="158" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:41 %sum_2_2_1_2 = fadd i32 %sum_2_2_1_1, i32 %mul9_2_1_2

]]></Node>
<StgValue><ssdm name="sum_2_2_1_2"/></StgValue>
</operation>
</state>

<state id="159" st_id="159">

<operation id="1059" st_id="159" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:41 %sum_2_2_1_2 = fadd i32 %sum_2_2_1_1, i32 %mul9_2_1_2

]]></Node>
<StgValue><ssdm name="sum_2_2_1_2"/></StgValue>
</operation>
</state>

<state id="160" st_id="160">

<operation id="1060" st_id="160" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:41 %sum_2_2_1_2 = fadd i32 %sum_2_2_1_1, i32 %mul9_2_1_2

]]></Node>
<StgValue><ssdm name="sum_2_2_1_2"/></StgValue>
</operation>
</state>

<state id="161" st_id="161">
</state>

<state id="162" st_id="162">

<operation id="1061" st_id="162" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:47 %sum_2_2_2 = fadd i32 %sum_2_2_1_2, i32 %mul9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2"/></StgValue>
</operation>
</state>

<state id="163" st_id="163">

<operation id="1062" st_id="163" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:47 %sum_2_2_2 = fadd i32 %sum_2_2_1_2, i32 %mul9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2"/></StgValue>
</operation>
</state>

<state id="164" st_id="164">

<operation id="1063" st_id="164" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:47 %sum_2_2_2 = fadd i32 %sum_2_2_1_2, i32 %mul9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2"/></StgValue>
</operation>
</state>

<state id="165" st_id="165">

<operation id="1064" st_id="165" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:47 %sum_2_2_2 = fadd i32 %sum_2_2_1_2, i32 %mul9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2"/></StgValue>
</operation>
</state>

<state id="166" st_id="166">

<operation id="1065" st_id="166" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:47 %sum_2_2_2 = fadd i32 %sum_2_2_1_2, i32 %mul9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2"/></StgValue>
</operation>
</state>

<state id="167" st_id="167">

<operation id="1066" st_id="167" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:53 %sum_2_2_2_1 = fadd i32 %sum_2_2_2, i32 %mul9_2_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_2_1"/></StgValue>
</operation>
</state>

<state id="168" st_id="168">

<operation id="1067" st_id="168" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:53 %sum_2_2_2_1 = fadd i32 %sum_2_2_2, i32 %mul9_2_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_2_1"/></StgValue>
</operation>
</state>

<state id="169" st_id="169">

<operation id="1068" st_id="169" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:53 %sum_2_2_2_1 = fadd i32 %sum_2_2_2, i32 %mul9_2_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_2_1"/></StgValue>
</operation>
</state>

<state id="170" st_id="170">

<operation id="1069" st_id="170" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:53 %sum_2_2_2_1 = fadd i32 %sum_2_2_2, i32 %mul9_2_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_2_1"/></StgValue>
</operation>
</state>

<state id="171" st_id="171">

<operation id="1070" st_id="171" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:53 %sum_2_2_2_1 = fadd i32 %sum_2_2_2, i32 %mul9_2_2_1

]]></Node>
<StgValue><ssdm name="sum_2_2_2_1"/></StgValue>
</operation>
</state>

<state id="172" st_id="172">
</state>

<state id="173" st_id="173">

<operation id="1071" st_id="173" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:59 %sum_2_2_2_2 = fadd i32 %sum_2_2_2_1, i32 %mul9_2_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2_2"/></StgValue>
</operation>
</state>

<state id="174" st_id="174">

<operation id="1072" st_id="174" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:59 %sum_2_2_2_2 = fadd i32 %sum_2_2_2_1, i32 %mul9_2_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2_2"/></StgValue>
</operation>
</state>

<state id="175" st_id="175">

<operation id="1073" st_id="175" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:59 %sum_2_2_2_2 = fadd i32 %sum_2_2_2_1, i32 %mul9_2_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2_2"/></StgValue>
</operation>
</state>

<state id="176" st_id="176">

<operation id="1074" st_id="176" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:59 %sum_2_2_2_2 = fadd i32 %sum_2_2_2_1, i32 %mul9_2_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2_2"/></StgValue>
</operation>
</state>

<state id="177" st_id="177">

<operation id="1075" st_id="177" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.2:59 %sum_2_2_2_2 = fadd i32 %sum_2_2_2_1, i32 %mul9_2_2_2

]]></Node>
<StgValue><ssdm name="sum_2_2_2_2"/></StgValue>
</operation>
</state>

<state id="178" st_id="178">

<operation id="1076" st_id="178" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="220" bw="64" op_0_bw="33">
<![CDATA[
.split4.2:1 %t_3_2_cast = zext i33 %t_3_2

]]></Node>
<StgValue><ssdm name="t_3_2_cast"/></StgValue>
</operation>

<operation id="1077" st_id="178" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="222" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.2:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1078" st_id="178" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="279" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.2:60 %add_ln58_2 = add i33 %t_3_2, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_2"/></StgValue>
</operation>

<operation id="1079" st_id="178" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="280" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.2:61 %out_addr_11 = getelementptr i32 %out_r, i64 0, i64 %t_3_2_cast

]]></Node>
<StgValue><ssdm name="out_addr_11"/></StgValue>
</operation>

<operation id="1080" st_id="178" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="281" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.2:62 %store_ln58 = store i32 %sum_2_2_2_2, i11 %out_addr_11

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1081" st_id="178" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="282" bw="0" op_0_bw="0">
<![CDATA[
.split4.2:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="179" st_id="179">

<operation id="1082" st_id="179" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="284" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.2:0 %add_ln44_6 = add i32 %zext_ln44_2, i32 %add_ln44_4

]]></Node>
<StgValue><ssdm name="add_ln44_6"/></StgValue>
</operation>

<operation id="1083" st_id="179" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="285" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.2:1 %add_ln44_7 = add i64 %i_0, i64 3

]]></Node>
<StgValue><ssdm name="add_ln44_7"/></StgValue>
</operation>

<operation id="1084" st_id="179" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="286" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.2:2 %icmp_ln44_3 = icmp_slt  i64 %add_ln44_7, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_3"/></StgValue>
</operation>

<operation id="1085" st_id="179" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="287" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.2:3 %br_ln44 = br i1 %icmp_ln44_3, void %._crit_edge13.loopexit, void %.lr.ph.3

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1086" st_id="179" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_3" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="290" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.3:1 %empty_115 = add i11 %trunc_ln44, i11 4

]]></Node>
<StgValue><ssdm name="empty_115"/></StgValue>
</operation>

<operation id="1087" st_id="179" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_3" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="291" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.3:2 %empty_116 = mul i11 %empty_115, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_116"/></StgValue>
</operation>
</state>

<state id="180" st_id="180">

<operation id="1088" st_id="180" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="291" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.3:2 %empty_116 = mul i11 %empty_115, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_116"/></StgValue>
</operation>
</state>

<state id="181" st_id="181">

<operation id="1089" st_id="181" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="291" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.3:2 %empty_116 = mul i11 %empty_115, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_116"/></StgValue>
</operation>
</state>

<state id="182" st_id="182">

<operation id="1090" st_id="182" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="289" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.3:0 %add_ln44_8_cast = sext i32 %add_ln44_6

]]></Node>
<StgValue><ssdm name="add_ln44_8_cast"/></StgValue>
</operation>

<operation id="1091" st_id="182" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="291" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.3:2 %empty_116 = mul i11 %empty_115, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_116"/></StgValue>
</operation>

<operation id="1092" st_id="182" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="292" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.3:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="183" st_id="183">

<operation id="1093" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="294" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_3 = phi i33 %add_ln58_3, void %.split4.3, i33 %add_ln44_8_cast, void %.lr.ph.3

]]></Node>
<StgValue><ssdm name="t_3_3"/></StgValue>
</operation>

<operation id="1094" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="295" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_3 = phi i6 %add_ln47_3, void %.split4.3, i6 1, void %.lr.ph.3

]]></Node>
<StgValue><ssdm name="j_3"/></StgValue>
</operation>

<operation id="1095" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="296" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1096" st_id="183" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="297" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_3 = icmp_eq  i6 %j_3, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_3"/></StgValue>
</operation>

<operation id="1097" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="298" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_114 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_114"/></StgValue>
</operation>

<operation id="1098" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="299" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_3, void %.split4.3, void %._crit_edge.loopexit.3

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1099" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="303" bw="11" op_0_bw="6">
<![CDATA[
.split4.3:2 %j_3_cast = zext i6 %j_3

]]></Node>
<StgValue><ssdm name="j_3_cast"/></StgValue>
</operation>

<operation id="1100" st_id="183" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="305" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.3:4 %empty_117 = add i6 %j_3, i6 63

]]></Node>
<StgValue><ssdm name="empty_117"/></StgValue>
</operation>

<operation id="1101" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="306" bw="11" op_0_bw="6">
<![CDATA[
.split4.3:5 %zext_ln8_69 = zext i6 %empty_117

]]></Node>
<StgValue><ssdm name="zext_ln8_69"/></StgValue>
</operation>

<operation id="1102" st_id="183" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="307" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:6 %add_ln8_66 = add i11 %zext_ln8_69, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_66"/></StgValue>
</operation>

<operation id="1103" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="308" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:7 %zext_ln8_70 = zext i11 %add_ln8_66

]]></Node>
<StgValue><ssdm name="zext_ln8_70"/></StgValue>
</operation>

<operation id="1104" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="309" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:8 %arr_addr_66 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_70

]]></Node>
<StgValue><ssdm name="arr_addr_66"/></StgValue>
</operation>

<operation id="1105" st_id="183" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="310" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:9 %arr_load_66 = load i11 %arr_addr_66

]]></Node>
<StgValue><ssdm name="arr_load_66"/></StgValue>
</operation>

<operation id="1106" st_id="183" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="313" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:12 %add_ln8_67 = add i11 %j_3_cast, i11 %empty_108

]]></Node>
<StgValue><ssdm name="add_ln8_67"/></StgValue>
</operation>

<operation id="1107" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="314" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:13 %zext_ln8_71 = zext i11 %add_ln8_67

]]></Node>
<StgValue><ssdm name="zext_ln8_71"/></StgValue>
</operation>

<operation id="1108" st_id="183" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="315" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:14 %arr_addr_67 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_71

]]></Node>
<StgValue><ssdm name="arr_addr_67"/></StgValue>
</operation>

<operation id="1109" st_id="183" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="316" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:15 %arr_load_67 = load i11 %arr_addr_67

]]></Node>
<StgValue><ssdm name="arr_load_67"/></StgValue>
</operation>
</state>

<state id="184" st_id="184">

<operation id="1110" st_id="184" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="310" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:9 %arr_load_66 = load i11 %arr_addr_66

]]></Node>
<StgValue><ssdm name="arr_load_66"/></StgValue>
</operation>

<operation id="1111" st_id="184" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="311" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:10 %mul9_3 = fmul i32 %arr_load_66, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_3"/></StgValue>
</operation>

<operation id="1112" st_id="184" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="316" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:15 %arr_load_67 = load i11 %arr_addr_67

]]></Node>
<StgValue><ssdm name="arr_load_67"/></StgValue>
</operation>

<operation id="1113" st_id="184" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:16 %mul9_3_0_1 = fmul i32 %arr_load_67, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_3_0_1"/></StgValue>
</operation>

<operation id="1114" st_id="184" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="319" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:18 %add_ln8_68 = add i11 %add_ln8_66, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_68"/></StgValue>
</operation>

<operation id="1115" st_id="184" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="320" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:19 %zext_ln8_72 = zext i11 %add_ln8_68

]]></Node>
<StgValue><ssdm name="zext_ln8_72"/></StgValue>
</operation>

<operation id="1116" st_id="184" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="321" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:20 %arr_addr_68 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_72

]]></Node>
<StgValue><ssdm name="arr_addr_68"/></StgValue>
</operation>

<operation id="1117" st_id="184" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="322" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:21 %arr_load_68 = load i11 %arr_addr_68

]]></Node>
<StgValue><ssdm name="arr_load_68"/></StgValue>
</operation>

<operation id="1118" st_id="184" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="325" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:24 %add_ln8_69 = add i11 %zext_ln8_69, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_69"/></StgValue>
</operation>

<operation id="1119" st_id="184" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="326" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:25 %zext_ln8_73 = zext i11 %add_ln8_69

]]></Node>
<StgValue><ssdm name="zext_ln8_73"/></StgValue>
</operation>

<operation id="1120" st_id="184" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="327" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:26 %arr_addr_69 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_73

]]></Node>
<StgValue><ssdm name="arr_addr_69"/></StgValue>
</operation>

<operation id="1121" st_id="184" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="328" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:27 %arr_load_69 = load i11 %arr_addr_69

]]></Node>
<StgValue><ssdm name="arr_load_69"/></StgValue>
</operation>
</state>

<state id="185" st_id="185">

<operation id="1122" st_id="185" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="311" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:10 %mul9_3 = fmul i32 %arr_load_66, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_3"/></StgValue>
</operation>

<operation id="1123" st_id="185" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:16 %mul9_3_0_1 = fmul i32 %arr_load_67, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_3_0_1"/></StgValue>
</operation>

<operation id="1124" st_id="185" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="322" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:21 %arr_load_68 = load i11 %arr_addr_68

]]></Node>
<StgValue><ssdm name="arr_load_68"/></StgValue>
</operation>

<operation id="1125" st_id="185" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="323" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:22 %mul9_3_0_2 = fmul i32 %arr_load_68, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_3_0_2"/></StgValue>
</operation>

<operation id="1126" st_id="185" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="328" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:27 %arr_load_69 = load i11 %arr_addr_69

]]></Node>
<StgValue><ssdm name="arr_load_69"/></StgValue>
</operation>

<operation id="1127" st_id="185" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:28 %mul9_3_1 = fmul i32 %arr_load_69, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_3_1"/></StgValue>
</operation>

<operation id="1128" st_id="185" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="331" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:30 %add_ln8_70 = add i11 %j_3_cast, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_70"/></StgValue>
</operation>

<operation id="1129" st_id="185" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="332" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:31 %zext_ln8_74 = zext i11 %add_ln8_70

]]></Node>
<StgValue><ssdm name="zext_ln8_74"/></StgValue>
</operation>

<operation id="1130" st_id="185" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="333" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:32 %arr_addr_70 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_74

]]></Node>
<StgValue><ssdm name="arr_addr_70"/></StgValue>
</operation>

<operation id="1131" st_id="185" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="334" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:33 %arr_load_70 = load i11 %arr_addr_70

]]></Node>
<StgValue><ssdm name="arr_load_70"/></StgValue>
</operation>

<operation id="1132" st_id="185" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="337" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:36 %add_ln8_71 = add i11 %add_ln8_69, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_71"/></StgValue>
</operation>

<operation id="1133" st_id="185" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="338" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:37 %zext_ln8_75 = zext i11 %add_ln8_71

]]></Node>
<StgValue><ssdm name="zext_ln8_75"/></StgValue>
</operation>

<operation id="1134" st_id="185" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="339" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:38 %arr_addr_71 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_75

]]></Node>
<StgValue><ssdm name="arr_addr_71"/></StgValue>
</operation>

<operation id="1135" st_id="185" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="340" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:39 %arr_load_71 = load i11 %arr_addr_71

]]></Node>
<StgValue><ssdm name="arr_load_71"/></StgValue>
</operation>
</state>

<state id="186" st_id="186">

<operation id="1136" st_id="186" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="311" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:10 %mul9_3 = fmul i32 %arr_load_66, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_3"/></StgValue>
</operation>

<operation id="1137" st_id="186" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:16 %mul9_3_0_1 = fmul i32 %arr_load_67, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_3_0_1"/></StgValue>
</operation>

<operation id="1138" st_id="186" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="323" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:22 %mul9_3_0_2 = fmul i32 %arr_load_68, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_3_0_2"/></StgValue>
</operation>

<operation id="1139" st_id="186" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:28 %mul9_3_1 = fmul i32 %arr_load_69, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_3_1"/></StgValue>
</operation>

<operation id="1140" st_id="186" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="334" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:33 %arr_load_70 = load i11 %arr_addr_70

]]></Node>
<StgValue><ssdm name="arr_load_70"/></StgValue>
</operation>

<operation id="1141" st_id="186" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="335" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:34 %mul9_3_1_1 = fmul i32 %arr_load_70, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_3_1_1"/></StgValue>
</operation>

<operation id="1142" st_id="186" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="340" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:39 %arr_load_71 = load i11 %arr_addr_71

]]></Node>
<StgValue><ssdm name="arr_load_71"/></StgValue>
</operation>

<operation id="1143" st_id="186" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="341" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:40 %mul9_3_1_2 = fmul i32 %arr_load_71, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_3_1_2"/></StgValue>
</operation>

<operation id="1144" st_id="186" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="343" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:42 %add_ln8_72 = add i11 %zext_ln8_69, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_72"/></StgValue>
</operation>

<operation id="1145" st_id="186" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="344" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:43 %zext_ln8_76 = zext i11 %add_ln8_72

]]></Node>
<StgValue><ssdm name="zext_ln8_76"/></StgValue>
</operation>

<operation id="1146" st_id="186" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="345" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:44 %arr_addr_72 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_76

]]></Node>
<StgValue><ssdm name="arr_addr_72"/></StgValue>
</operation>

<operation id="1147" st_id="186" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="346" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:45 %arr_load_72 = load i11 %arr_addr_72

]]></Node>
<StgValue><ssdm name="arr_load_72"/></StgValue>
</operation>

<operation id="1148" st_id="186" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="349" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:48 %add_ln8_73 = add i11 %j_3_cast, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_73"/></StgValue>
</operation>

<operation id="1149" st_id="186" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="350" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:49 %zext_ln8_77 = zext i11 %add_ln8_73

]]></Node>
<StgValue><ssdm name="zext_ln8_77"/></StgValue>
</operation>

<operation id="1150" st_id="186" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="351" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:50 %arr_addr_73 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_77

]]></Node>
<StgValue><ssdm name="arr_addr_73"/></StgValue>
</operation>

<operation id="1151" st_id="186" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="352" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:51 %arr_load_73 = load i11 %arr_addr_73

]]></Node>
<StgValue><ssdm name="arr_load_73"/></StgValue>
</operation>
</state>

<state id="187" st_id="187">

<operation id="1152" st_id="187" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="301" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.3:0 %add_ln47_3 = add i6 %j_3, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_3"/></StgValue>
</operation>

<operation id="1153" st_id="187" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="311" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:10 %mul9_3 = fmul i32 %arr_load_66, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_3"/></StgValue>
</operation>

<operation id="1154" st_id="187" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:16 %mul9_3_0_1 = fmul i32 %arr_load_67, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_3_0_1"/></StgValue>
</operation>

<operation id="1155" st_id="187" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="323" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:22 %mul9_3_0_2 = fmul i32 %arr_load_68, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_3_0_2"/></StgValue>
</operation>

<operation id="1156" st_id="187" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:28 %mul9_3_1 = fmul i32 %arr_load_69, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_3_1"/></StgValue>
</operation>

<operation id="1157" st_id="187" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="335" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:34 %mul9_3_1_1 = fmul i32 %arr_load_70, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_3_1_1"/></StgValue>
</operation>

<operation id="1158" st_id="187" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="341" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:40 %mul9_3_1_2 = fmul i32 %arr_load_71, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_3_1_2"/></StgValue>
</operation>

<operation id="1159" st_id="187" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="346" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:45 %arr_load_72 = load i11 %arr_addr_72

]]></Node>
<StgValue><ssdm name="arr_load_72"/></StgValue>
</operation>

<operation id="1160" st_id="187" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="347" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:46 %mul9_3_2 = fmul i32 %arr_load_72, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_3_2"/></StgValue>
</operation>

<operation id="1161" st_id="187" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="352" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:51 %arr_load_73 = load i11 %arr_addr_73

]]></Node>
<StgValue><ssdm name="arr_load_73"/></StgValue>
</operation>

<operation id="1162" st_id="187" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="353" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:52 %mul9_3_2_1 = fmul i32 %arr_load_73, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_3_2_1"/></StgValue>
</operation>

<operation id="1163" st_id="187" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="355" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:54 %add_ln8_74 = add i11 %add_ln8_72, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_74"/></StgValue>
</operation>

<operation id="1164" st_id="187" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="356" bw="64" op_0_bw="11">
<![CDATA[
.split4.3:55 %zext_ln8_78 = zext i11 %add_ln8_74

]]></Node>
<StgValue><ssdm name="zext_ln8_78"/></StgValue>
</operation>

<operation id="1165" st_id="187" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="357" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:56 %arr_addr_74 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_78

]]></Node>
<StgValue><ssdm name="arr_addr_74"/></StgValue>
</operation>

<operation id="1166" st_id="187" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="358" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:57 %arr_load_74 = load i11 %arr_addr_74

]]></Node>
<StgValue><ssdm name="arr_load_74"/></StgValue>
</operation>
</state>

<state id="188" st_id="188">

<operation id="1167" st_id="188" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:11 %sum_2_3 = fadd i32 %mul9_3, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_3"/></StgValue>
</operation>

<operation id="1168" st_id="188" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="323" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:22 %mul9_3_0_2 = fmul i32 %arr_load_68, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_3_0_2"/></StgValue>
</operation>

<operation id="1169" st_id="188" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:28 %mul9_3_1 = fmul i32 %arr_load_69, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_3_1"/></StgValue>
</operation>

<operation id="1170" st_id="188" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="335" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:34 %mul9_3_1_1 = fmul i32 %arr_load_70, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_3_1_1"/></StgValue>
</operation>

<operation id="1171" st_id="188" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="341" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:40 %mul9_3_1_2 = fmul i32 %arr_load_71, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_3_1_2"/></StgValue>
</operation>

<operation id="1172" st_id="188" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="347" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:46 %mul9_3_2 = fmul i32 %arr_load_72, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_3_2"/></StgValue>
</operation>

<operation id="1173" st_id="188" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="353" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:52 %mul9_3_2_1 = fmul i32 %arr_load_73, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_3_2_1"/></StgValue>
</operation>

<operation id="1174" st_id="188" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="358" bw="32" op_0_bw="11">
<![CDATA[
.split4.3:57 %arr_load_74 = load i11 %arr_addr_74

]]></Node>
<StgValue><ssdm name="arr_load_74"/></StgValue>
</operation>

<operation id="1175" st_id="188" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="359" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:58 %mul9_3_2_2 = fmul i32 %arr_load_74, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_3_2_2"/></StgValue>
</operation>
</state>

<state id="189" st_id="189">

<operation id="1176" st_id="189" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:11 %sum_2_3 = fadd i32 %mul9_3, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_3"/></StgValue>
</operation>

<operation id="1177" st_id="189" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="335" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:34 %mul9_3_1_1 = fmul i32 %arr_load_70, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_3_1_1"/></StgValue>
</operation>

<operation id="1178" st_id="189" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="341" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:40 %mul9_3_1_2 = fmul i32 %arr_load_71, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_3_1_2"/></StgValue>
</operation>

<operation id="1179" st_id="189" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="347" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:46 %mul9_3_2 = fmul i32 %arr_load_72, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_3_2"/></StgValue>
</operation>

<operation id="1180" st_id="189" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="353" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:52 %mul9_3_2_1 = fmul i32 %arr_load_73, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_3_2_1"/></StgValue>
</operation>

<operation id="1181" st_id="189" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="359" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:58 %mul9_3_2_2 = fmul i32 %arr_load_74, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_3_2_2"/></StgValue>
</operation>
</state>

<state id="190" st_id="190">

<operation id="1182" st_id="190" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:11 %sum_2_3 = fadd i32 %mul9_3, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_3"/></StgValue>
</operation>

<operation id="1183" st_id="190" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="347" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:46 %mul9_3_2 = fmul i32 %arr_load_72, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_3_2"/></StgValue>
</operation>

<operation id="1184" st_id="190" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="353" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:52 %mul9_3_2_1 = fmul i32 %arr_load_73, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_3_2_1"/></StgValue>
</operation>

<operation id="1185" st_id="190" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="359" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:58 %mul9_3_2_2 = fmul i32 %arr_load_74, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_3_2_2"/></StgValue>
</operation>
</state>

<state id="191" st_id="191">

<operation id="1186" st_id="191" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:11 %sum_2_3 = fadd i32 %mul9_3, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_3"/></StgValue>
</operation>

<operation id="1187" st_id="191" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="359" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:58 %mul9_3_2_2 = fmul i32 %arr_load_74, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_3_2_2"/></StgValue>
</operation>
</state>

<state id="192" st_id="192">

<operation id="1188" st_id="192" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:11 %sum_2_3 = fadd i32 %mul9_3, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_3"/></StgValue>
</operation>
</state>

<state id="193" st_id="193">

<operation id="1189" st_id="193" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:17 %sum_2_3_0_1 = fadd i32 %sum_2_3, i32 %mul9_3_0_1

]]></Node>
<StgValue><ssdm name="sum_2_3_0_1"/></StgValue>
</operation>
</state>

<state id="194" st_id="194">

<operation id="1190" st_id="194" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:17 %sum_2_3_0_1 = fadd i32 %sum_2_3, i32 %mul9_3_0_1

]]></Node>
<StgValue><ssdm name="sum_2_3_0_1"/></StgValue>
</operation>
</state>

<state id="195" st_id="195">

<operation id="1191" st_id="195" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:17 %sum_2_3_0_1 = fadd i32 %sum_2_3, i32 %mul9_3_0_1

]]></Node>
<StgValue><ssdm name="sum_2_3_0_1"/></StgValue>
</operation>
</state>

<state id="196" st_id="196">

<operation id="1192" st_id="196" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:17 %sum_2_3_0_1 = fadd i32 %sum_2_3, i32 %mul9_3_0_1

]]></Node>
<StgValue><ssdm name="sum_2_3_0_1"/></StgValue>
</operation>
</state>

<state id="197" st_id="197">

<operation id="1193" st_id="197" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:17 %sum_2_3_0_1 = fadd i32 %sum_2_3, i32 %mul9_3_0_1

]]></Node>
<StgValue><ssdm name="sum_2_3_0_1"/></StgValue>
</operation>
</state>

<state id="198" st_id="198">
</state>

<state id="199" st_id="199">

<operation id="1194" st_id="199" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:23 %sum_2_3_0_2 = fadd i32 %sum_2_3_0_1, i32 %mul9_3_0_2

]]></Node>
<StgValue><ssdm name="sum_2_3_0_2"/></StgValue>
</operation>
</state>

<state id="200" st_id="200">

<operation id="1195" st_id="200" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:23 %sum_2_3_0_2 = fadd i32 %sum_2_3_0_1, i32 %mul9_3_0_2

]]></Node>
<StgValue><ssdm name="sum_2_3_0_2"/></StgValue>
</operation>
</state>

<state id="201" st_id="201">

<operation id="1196" st_id="201" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:23 %sum_2_3_0_2 = fadd i32 %sum_2_3_0_1, i32 %mul9_3_0_2

]]></Node>
<StgValue><ssdm name="sum_2_3_0_2"/></StgValue>
</operation>
</state>

<state id="202" st_id="202">

<operation id="1197" st_id="202" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:23 %sum_2_3_0_2 = fadd i32 %sum_2_3_0_1, i32 %mul9_3_0_2

]]></Node>
<StgValue><ssdm name="sum_2_3_0_2"/></StgValue>
</operation>
</state>

<state id="203" st_id="203">

<operation id="1198" st_id="203" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:23 %sum_2_3_0_2 = fadd i32 %sum_2_3_0_1, i32 %mul9_3_0_2

]]></Node>
<StgValue><ssdm name="sum_2_3_0_2"/></StgValue>
</operation>
</state>

<state id="204" st_id="204">

<operation id="1199" st_id="204" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:29 %sum_2_3_1 = fadd i32 %sum_2_3_0_2, i32 %mul9_3_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1"/></StgValue>
</operation>
</state>

<state id="205" st_id="205">

<operation id="1200" st_id="205" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:29 %sum_2_3_1 = fadd i32 %sum_2_3_0_2, i32 %mul9_3_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1"/></StgValue>
</operation>
</state>

<state id="206" st_id="206">

<operation id="1201" st_id="206" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:29 %sum_2_3_1 = fadd i32 %sum_2_3_0_2, i32 %mul9_3_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1"/></StgValue>
</operation>
</state>

<state id="207" st_id="207">

<operation id="1202" st_id="207" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:29 %sum_2_3_1 = fadd i32 %sum_2_3_0_2, i32 %mul9_3_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1"/></StgValue>
</operation>
</state>

<state id="208" st_id="208">

<operation id="1203" st_id="208" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:29 %sum_2_3_1 = fadd i32 %sum_2_3_0_2, i32 %mul9_3_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1"/></StgValue>
</operation>
</state>

<state id="209" st_id="209">
</state>

<state id="210" st_id="210">

<operation id="1204" st_id="210" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:35 %sum_2_3_1_1 = fadd i32 %sum_2_3_1, i32 %mul9_3_1_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1_1"/></StgValue>
</operation>
</state>

<state id="211" st_id="211">

<operation id="1205" st_id="211" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:35 %sum_2_3_1_1 = fadd i32 %sum_2_3_1, i32 %mul9_3_1_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1_1"/></StgValue>
</operation>
</state>

<state id="212" st_id="212">

<operation id="1206" st_id="212" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:35 %sum_2_3_1_1 = fadd i32 %sum_2_3_1, i32 %mul9_3_1_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1_1"/></StgValue>
</operation>
</state>

<state id="213" st_id="213">

<operation id="1207" st_id="213" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:35 %sum_2_3_1_1 = fadd i32 %sum_2_3_1, i32 %mul9_3_1_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1_1"/></StgValue>
</operation>
</state>

<state id="214" st_id="214">

<operation id="1208" st_id="214" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:35 %sum_2_3_1_1 = fadd i32 %sum_2_3_1, i32 %mul9_3_1_1

]]></Node>
<StgValue><ssdm name="sum_2_3_1_1"/></StgValue>
</operation>
</state>

<state id="215" st_id="215">

<operation id="1209" st_id="215" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:41 %sum_2_3_1_2 = fadd i32 %sum_2_3_1_1, i32 %mul9_3_1_2

]]></Node>
<StgValue><ssdm name="sum_2_3_1_2"/></StgValue>
</operation>
</state>

<state id="216" st_id="216">

<operation id="1210" st_id="216" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:41 %sum_2_3_1_2 = fadd i32 %sum_2_3_1_1, i32 %mul9_3_1_2

]]></Node>
<StgValue><ssdm name="sum_2_3_1_2"/></StgValue>
</operation>
</state>

<state id="217" st_id="217">

<operation id="1211" st_id="217" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:41 %sum_2_3_1_2 = fadd i32 %sum_2_3_1_1, i32 %mul9_3_1_2

]]></Node>
<StgValue><ssdm name="sum_2_3_1_2"/></StgValue>
</operation>
</state>

<state id="218" st_id="218">

<operation id="1212" st_id="218" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:41 %sum_2_3_1_2 = fadd i32 %sum_2_3_1_1, i32 %mul9_3_1_2

]]></Node>
<StgValue><ssdm name="sum_2_3_1_2"/></StgValue>
</operation>
</state>

<state id="219" st_id="219">

<operation id="1213" st_id="219" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:41 %sum_2_3_1_2 = fadd i32 %sum_2_3_1_1, i32 %mul9_3_1_2

]]></Node>
<StgValue><ssdm name="sum_2_3_1_2"/></StgValue>
</operation>
</state>

<state id="220" st_id="220">
</state>

<state id="221" st_id="221">

<operation id="1214" st_id="221" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="348" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:47 %sum_2_3_2 = fadd i32 %sum_2_3_1_2, i32 %mul9_3_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2"/></StgValue>
</operation>
</state>

<state id="222" st_id="222">

<operation id="1215" st_id="222" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="348" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:47 %sum_2_3_2 = fadd i32 %sum_2_3_1_2, i32 %mul9_3_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2"/></StgValue>
</operation>
</state>

<state id="223" st_id="223">

<operation id="1216" st_id="223" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="348" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:47 %sum_2_3_2 = fadd i32 %sum_2_3_1_2, i32 %mul9_3_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2"/></StgValue>
</operation>
</state>

<state id="224" st_id="224">

<operation id="1217" st_id="224" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="348" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:47 %sum_2_3_2 = fadd i32 %sum_2_3_1_2, i32 %mul9_3_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2"/></StgValue>
</operation>
</state>

<state id="225" st_id="225">

<operation id="1218" st_id="225" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="348" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:47 %sum_2_3_2 = fadd i32 %sum_2_3_1_2, i32 %mul9_3_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2"/></StgValue>
</operation>
</state>

<state id="226" st_id="226">

<operation id="1219" st_id="226" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="354" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:53 %sum_2_3_2_1 = fadd i32 %sum_2_3_2, i32 %mul9_3_2_1

]]></Node>
<StgValue><ssdm name="sum_2_3_2_1"/></StgValue>
</operation>
</state>

<state id="227" st_id="227">

<operation id="1220" st_id="227" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="354" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:53 %sum_2_3_2_1 = fadd i32 %sum_2_3_2, i32 %mul9_3_2_1

]]></Node>
<StgValue><ssdm name="sum_2_3_2_1"/></StgValue>
</operation>
</state>

<state id="228" st_id="228">

<operation id="1221" st_id="228" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="354" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:53 %sum_2_3_2_1 = fadd i32 %sum_2_3_2, i32 %mul9_3_2_1

]]></Node>
<StgValue><ssdm name="sum_2_3_2_1"/></StgValue>
</operation>
</state>

<state id="229" st_id="229">

<operation id="1222" st_id="229" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="354" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:53 %sum_2_3_2_1 = fadd i32 %sum_2_3_2, i32 %mul9_3_2_1

]]></Node>
<StgValue><ssdm name="sum_2_3_2_1"/></StgValue>
</operation>
</state>

<state id="230" st_id="230">

<operation id="1223" st_id="230" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="354" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:53 %sum_2_3_2_1 = fadd i32 %sum_2_3_2, i32 %mul9_3_2_1

]]></Node>
<StgValue><ssdm name="sum_2_3_2_1"/></StgValue>
</operation>
</state>

<state id="231" st_id="231">
</state>

<state id="232" st_id="232">

<operation id="1224" st_id="232" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:59 %sum_2_3_2_2 = fadd i32 %sum_2_3_2_1, i32 %mul9_3_2_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2_2"/></StgValue>
</operation>
</state>

<state id="233" st_id="233">

<operation id="1225" st_id="233" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:59 %sum_2_3_2_2 = fadd i32 %sum_2_3_2_1, i32 %mul9_3_2_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2_2"/></StgValue>
</operation>
</state>

<state id="234" st_id="234">

<operation id="1226" st_id="234" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:59 %sum_2_3_2_2 = fadd i32 %sum_2_3_2_1, i32 %mul9_3_2_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2_2"/></StgValue>
</operation>
</state>

<state id="235" st_id="235">

<operation id="1227" st_id="235" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:59 %sum_2_3_2_2 = fadd i32 %sum_2_3_2_1, i32 %mul9_3_2_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2_2"/></StgValue>
</operation>
</state>

<state id="236" st_id="236">

<operation id="1228" st_id="236" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.3:59 %sum_2_3_2_2 = fadd i32 %sum_2_3_2_1, i32 %mul9_3_2_2

]]></Node>
<StgValue><ssdm name="sum_2_3_2_2"/></StgValue>
</operation>
</state>

<state id="237" st_id="237">

<operation id="1229" st_id="237" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="302" bw="64" op_0_bw="33">
<![CDATA[
.split4.3:1 %t_3_3_cast = zext i33 %t_3_3

]]></Node>
<StgValue><ssdm name="t_3_3_cast"/></StgValue>
</operation>

<operation id="1230" st_id="237" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="304" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.3:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1231" st_id="237" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="361" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.3:60 %add_ln58_3 = add i33 %t_3_3, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_3"/></StgValue>
</operation>

<operation id="1232" st_id="237" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="362" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.3:61 %out_addr_12 = getelementptr i32 %out_r, i64 0, i64 %t_3_3_cast

]]></Node>
<StgValue><ssdm name="out_addr_12"/></StgValue>
</operation>

<operation id="1233" st_id="237" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="363" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.3:62 %store_ln58 = store i32 %sum_2_3_2_2, i11 %out_addr_12

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1234" st_id="237" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="364" bw="0" op_0_bw="0">
<![CDATA[
.split4.3:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="238" st_id="238">

<operation id="1235" st_id="238" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="366" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.3:0 %add_ln44_8 = add i32 %zext_ln44_2, i32 %add_ln44_6

]]></Node>
<StgValue><ssdm name="add_ln44_8"/></StgValue>
</operation>

<operation id="1236" st_id="238" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="367" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.3:1 %add_ln44_9 = add i64 %i_0, i64 4

]]></Node>
<StgValue><ssdm name="add_ln44_9"/></StgValue>
</operation>

<operation id="1237" st_id="238" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="368" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.3:2 %icmp_ln44_4 = icmp_slt  i64 %add_ln44_9, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_4"/></StgValue>
</operation>

<operation id="1238" st_id="238" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="369" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.3:3 %br_ln44 = br i1 %icmp_ln44_4, void %._crit_edge13.loopexit, void %.lr.ph.4

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1239" st_id="238" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="372" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.4:1 %empty_119 = add i11 %trunc_ln44, i11 5

]]></Node>
<StgValue><ssdm name="empty_119"/></StgValue>
</operation>

<operation id="1240" st_id="238" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="373" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.4:2 %empty_120 = mul i11 %empty_119, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_120"/></StgValue>
</operation>
</state>

<state id="239" st_id="239">

<operation id="1241" st_id="239" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="373" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.4:2 %empty_120 = mul i11 %empty_119, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_120"/></StgValue>
</operation>
</state>

<state id="240" st_id="240">

<operation id="1242" st_id="240" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="373" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.4:2 %empty_120 = mul i11 %empty_119, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_120"/></StgValue>
</operation>
</state>

<state id="241" st_id="241">

<operation id="1243" st_id="241" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="371" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.4:0 %add_ln44_11_cast = sext i32 %add_ln44_8

]]></Node>
<StgValue><ssdm name="add_ln44_11_cast"/></StgValue>
</operation>

<operation id="1244" st_id="241" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="373" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.4:2 %empty_120 = mul i11 %empty_119, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_120"/></StgValue>
</operation>

<operation id="1245" st_id="241" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="374" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.4:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="242" st_id="242">

<operation id="1246" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="376" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_4 = phi i33 %add_ln58_4, void %.split4.4, i33 %add_ln44_11_cast, void %.lr.ph.4

]]></Node>
<StgValue><ssdm name="t_3_4"/></StgValue>
</operation>

<operation id="1247" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="377" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_4 = phi i6 %add_ln47_4, void %.split4.4, i6 1, void %.lr.ph.4

]]></Node>
<StgValue><ssdm name="j_4"/></StgValue>
</operation>

<operation id="1248" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="378" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1249" st_id="242" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="379" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_4 = icmp_eq  i6 %j_4, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_4"/></StgValue>
</operation>

<operation id="1250" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="380" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_118 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_118"/></StgValue>
</operation>

<operation id="1251" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="381" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_4, void %.split4.4, void %._crit_edge.loopexit.4

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1252" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="385" bw="11" op_0_bw="6">
<![CDATA[
.split4.4:2 %j_4_cast = zext i6 %j_4

]]></Node>
<StgValue><ssdm name="j_4_cast"/></StgValue>
</operation>

<operation id="1253" st_id="242" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="387" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.4:4 %empty_121 = add i6 %j_4, i6 63

]]></Node>
<StgValue><ssdm name="empty_121"/></StgValue>
</operation>

<operation id="1254" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="388" bw="11" op_0_bw="6">
<![CDATA[
.split4.4:5 %zext_ln8_79 = zext i6 %empty_121

]]></Node>
<StgValue><ssdm name="zext_ln8_79"/></StgValue>
</operation>

<operation id="1255" st_id="242" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="389" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:6 %add_ln8_75 = add i11 %zext_ln8_79, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_75"/></StgValue>
</operation>

<operation id="1256" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="390" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:7 %zext_ln8_80 = zext i11 %add_ln8_75

]]></Node>
<StgValue><ssdm name="zext_ln8_80"/></StgValue>
</operation>

<operation id="1257" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="391" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:8 %arr_addr_75 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_80

]]></Node>
<StgValue><ssdm name="arr_addr_75"/></StgValue>
</operation>

<operation id="1258" st_id="242" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="392" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:9 %arr_load_75 = load i11 %arr_addr_75

]]></Node>
<StgValue><ssdm name="arr_load_75"/></StgValue>
</operation>

<operation id="1259" st_id="242" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="395" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:12 %add_ln8_76 = add i11 %j_4_cast, i11 %empty_112

]]></Node>
<StgValue><ssdm name="add_ln8_76"/></StgValue>
</operation>

<operation id="1260" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="396" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:13 %zext_ln8_81 = zext i11 %add_ln8_76

]]></Node>
<StgValue><ssdm name="zext_ln8_81"/></StgValue>
</operation>

<operation id="1261" st_id="242" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="397" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:14 %arr_addr_76 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_81

]]></Node>
<StgValue><ssdm name="arr_addr_76"/></StgValue>
</operation>

<operation id="1262" st_id="242" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="398" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:15 %arr_load_76 = load i11 %arr_addr_76

]]></Node>
<StgValue><ssdm name="arr_load_76"/></StgValue>
</operation>
</state>

<state id="243" st_id="243">

<operation id="1263" st_id="243" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="392" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:9 %arr_load_75 = load i11 %arr_addr_75

]]></Node>
<StgValue><ssdm name="arr_load_75"/></StgValue>
</operation>

<operation id="1264" st_id="243" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="393" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:10 %mul9_4 = fmul i32 %arr_load_75, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_4"/></StgValue>
</operation>

<operation id="1265" st_id="243" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="398" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:15 %arr_load_76 = load i11 %arr_addr_76

]]></Node>
<StgValue><ssdm name="arr_load_76"/></StgValue>
</operation>

<operation id="1266" st_id="243" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="399" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:16 %mul9_4_0_1 = fmul i32 %arr_load_76, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_4_0_1"/></StgValue>
</operation>

<operation id="1267" st_id="243" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="401" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:18 %add_ln8_77 = add i11 %add_ln8_75, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_77"/></StgValue>
</operation>

<operation id="1268" st_id="243" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="402" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:19 %zext_ln8_82 = zext i11 %add_ln8_77

]]></Node>
<StgValue><ssdm name="zext_ln8_82"/></StgValue>
</operation>

<operation id="1269" st_id="243" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="403" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:20 %arr_addr_77 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_82

]]></Node>
<StgValue><ssdm name="arr_addr_77"/></StgValue>
</operation>

<operation id="1270" st_id="243" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="404" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:21 %arr_load_77 = load i11 %arr_addr_77

]]></Node>
<StgValue><ssdm name="arr_load_77"/></StgValue>
</operation>

<operation id="1271" st_id="243" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="407" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:24 %add_ln8_78 = add i11 %zext_ln8_79, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_78"/></StgValue>
</operation>

<operation id="1272" st_id="243" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="408" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:25 %zext_ln8_83 = zext i11 %add_ln8_78

]]></Node>
<StgValue><ssdm name="zext_ln8_83"/></StgValue>
</operation>

<operation id="1273" st_id="243" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="409" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:26 %arr_addr_78 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_83

]]></Node>
<StgValue><ssdm name="arr_addr_78"/></StgValue>
</operation>

<operation id="1274" st_id="243" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="410" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:27 %arr_load_78 = load i11 %arr_addr_78

]]></Node>
<StgValue><ssdm name="arr_load_78"/></StgValue>
</operation>

<operation id="1275" st_id="243" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="425" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:42 %add_ln8_81 = add i11 %zext_ln8_79, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_81"/></StgValue>
</operation>
</state>

<state id="244" st_id="244">

<operation id="1276" st_id="244" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="393" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:10 %mul9_4 = fmul i32 %arr_load_75, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_4"/></StgValue>
</operation>

<operation id="1277" st_id="244" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="399" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:16 %mul9_4_0_1 = fmul i32 %arr_load_76, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_4_0_1"/></StgValue>
</operation>

<operation id="1278" st_id="244" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="404" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:21 %arr_load_77 = load i11 %arr_addr_77

]]></Node>
<StgValue><ssdm name="arr_load_77"/></StgValue>
</operation>

<operation id="1279" st_id="244" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="405" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:22 %mul9_4_0_2 = fmul i32 %arr_load_77, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_4_0_2"/></StgValue>
</operation>

<operation id="1280" st_id="244" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="410" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:27 %arr_load_78 = load i11 %arr_addr_78

]]></Node>
<StgValue><ssdm name="arr_load_78"/></StgValue>
</operation>

<operation id="1281" st_id="244" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="411" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:28 %mul9_4_1 = fmul i32 %arr_load_78, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_4_1"/></StgValue>
</operation>

<operation id="1282" st_id="244" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="413" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:30 %add_ln8_79 = add i11 %j_4_cast, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_79"/></StgValue>
</operation>

<operation id="1283" st_id="244" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="414" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:31 %zext_ln8_84 = zext i11 %add_ln8_79

]]></Node>
<StgValue><ssdm name="zext_ln8_84"/></StgValue>
</operation>

<operation id="1284" st_id="244" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="415" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:32 %arr_addr_79 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_84

]]></Node>
<StgValue><ssdm name="arr_addr_79"/></StgValue>
</operation>

<operation id="1285" st_id="244" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="416" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:33 %arr_load_79 = load i11 %arr_addr_79

]]></Node>
<StgValue><ssdm name="arr_load_79"/></StgValue>
</operation>

<operation id="1286" st_id="244" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="419" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:36 %add_ln8_80 = add i11 %add_ln8_78, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_80"/></StgValue>
</operation>

<operation id="1287" st_id="244" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="420" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:37 %zext_ln8_85 = zext i11 %add_ln8_80

]]></Node>
<StgValue><ssdm name="zext_ln8_85"/></StgValue>
</operation>

<operation id="1288" st_id="244" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="421" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:38 %arr_addr_80 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_85

]]></Node>
<StgValue><ssdm name="arr_addr_80"/></StgValue>
</operation>

<operation id="1289" st_id="244" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="422" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:39 %arr_load_80 = load i11 %arr_addr_80

]]></Node>
<StgValue><ssdm name="arr_load_80"/></StgValue>
</operation>

<operation id="1290" st_id="244" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="431" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:48 %add_ln8_82 = add i11 %j_4_cast, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_82"/></StgValue>
</operation>
</state>

<state id="245" st_id="245">

<operation id="1291" st_id="245" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="393" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:10 %mul9_4 = fmul i32 %arr_load_75, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_4"/></StgValue>
</operation>

<operation id="1292" st_id="245" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="399" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:16 %mul9_4_0_1 = fmul i32 %arr_load_76, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_4_0_1"/></StgValue>
</operation>

<operation id="1293" st_id="245" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="405" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:22 %mul9_4_0_2 = fmul i32 %arr_load_77, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_4_0_2"/></StgValue>
</operation>

<operation id="1294" st_id="245" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="411" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:28 %mul9_4_1 = fmul i32 %arr_load_78, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_4_1"/></StgValue>
</operation>

<operation id="1295" st_id="245" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="416" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:33 %arr_load_79 = load i11 %arr_addr_79

]]></Node>
<StgValue><ssdm name="arr_load_79"/></StgValue>
</operation>

<operation id="1296" st_id="245" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="417" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:34 %mul9_4_1_1 = fmul i32 %arr_load_79, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_4_1_1"/></StgValue>
</operation>

<operation id="1297" st_id="245" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="422" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:39 %arr_load_80 = load i11 %arr_addr_80

]]></Node>
<StgValue><ssdm name="arr_load_80"/></StgValue>
</operation>

<operation id="1298" st_id="245" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="423" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:40 %mul9_4_1_2 = fmul i32 %arr_load_80, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_4_1_2"/></StgValue>
</operation>

<operation id="1299" st_id="245" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="426" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:43 %zext_ln8_86 = zext i11 %add_ln8_81

]]></Node>
<StgValue><ssdm name="zext_ln8_86"/></StgValue>
</operation>

<operation id="1300" st_id="245" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="427" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:44 %arr_addr_81 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_86

]]></Node>
<StgValue><ssdm name="arr_addr_81"/></StgValue>
</operation>

<operation id="1301" st_id="245" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="428" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:45 %arr_load_81 = load i11 %arr_addr_81

]]></Node>
<StgValue><ssdm name="arr_load_81"/></StgValue>
</operation>

<operation id="1302" st_id="245" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="432" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:49 %zext_ln8_87 = zext i11 %add_ln8_82

]]></Node>
<StgValue><ssdm name="zext_ln8_87"/></StgValue>
</operation>

<operation id="1303" st_id="245" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="433" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:50 %arr_addr_82 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_87

]]></Node>
<StgValue><ssdm name="arr_addr_82"/></StgValue>
</operation>

<operation id="1304" st_id="245" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="434" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:51 %arr_load_82 = load i11 %arr_addr_82

]]></Node>
<StgValue><ssdm name="arr_load_82"/></StgValue>
</operation>
</state>

<state id="246" st_id="246">

<operation id="1305" st_id="246" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="383" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.4:0 %add_ln47_4 = add i6 %j_4, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_4"/></StgValue>
</operation>

<operation id="1306" st_id="246" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="393" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:10 %mul9_4 = fmul i32 %arr_load_75, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_4"/></StgValue>
</operation>

<operation id="1307" st_id="246" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="399" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:16 %mul9_4_0_1 = fmul i32 %arr_load_76, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_4_0_1"/></StgValue>
</operation>

<operation id="1308" st_id="246" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="405" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:22 %mul9_4_0_2 = fmul i32 %arr_load_77, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_4_0_2"/></StgValue>
</operation>

<operation id="1309" st_id="246" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="411" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:28 %mul9_4_1 = fmul i32 %arr_load_78, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_4_1"/></StgValue>
</operation>

<operation id="1310" st_id="246" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="417" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:34 %mul9_4_1_1 = fmul i32 %arr_load_79, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_4_1_1"/></StgValue>
</operation>

<operation id="1311" st_id="246" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="423" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:40 %mul9_4_1_2 = fmul i32 %arr_load_80, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_4_1_2"/></StgValue>
</operation>

<operation id="1312" st_id="246" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="428" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:45 %arr_load_81 = load i11 %arr_addr_81

]]></Node>
<StgValue><ssdm name="arr_load_81"/></StgValue>
</operation>

<operation id="1313" st_id="246" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="429" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:46 %mul9_4_2 = fmul i32 %arr_load_81, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_4_2"/></StgValue>
</operation>

<operation id="1314" st_id="246" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="434" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:51 %arr_load_82 = load i11 %arr_addr_82

]]></Node>
<StgValue><ssdm name="arr_load_82"/></StgValue>
</operation>

<operation id="1315" st_id="246" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="435" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:52 %mul9_4_2_1 = fmul i32 %arr_load_82, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_4_2_1"/></StgValue>
</operation>

<operation id="1316" st_id="246" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="437" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:54 %add_ln8_83 = add i11 %add_ln8_81, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_83"/></StgValue>
</operation>

<operation id="1317" st_id="246" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="438" bw="64" op_0_bw="11">
<![CDATA[
.split4.4:55 %zext_ln8_88 = zext i11 %add_ln8_83

]]></Node>
<StgValue><ssdm name="zext_ln8_88"/></StgValue>
</operation>

<operation id="1318" st_id="246" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="439" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:56 %arr_addr_83 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_88

]]></Node>
<StgValue><ssdm name="arr_addr_83"/></StgValue>
</operation>

<operation id="1319" st_id="246" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="440" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:57 %arr_load_83 = load i11 %arr_addr_83

]]></Node>
<StgValue><ssdm name="arr_load_83"/></StgValue>
</operation>
</state>

<state id="247" st_id="247">

<operation id="1320" st_id="247" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:11 %sum_2_4 = fadd i32 %mul9_4, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_4"/></StgValue>
</operation>

<operation id="1321" st_id="247" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="405" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:22 %mul9_4_0_2 = fmul i32 %arr_load_77, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_4_0_2"/></StgValue>
</operation>

<operation id="1322" st_id="247" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="411" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:28 %mul9_4_1 = fmul i32 %arr_load_78, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_4_1"/></StgValue>
</operation>

<operation id="1323" st_id="247" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="417" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:34 %mul9_4_1_1 = fmul i32 %arr_load_79, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_4_1_1"/></StgValue>
</operation>

<operation id="1324" st_id="247" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="423" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:40 %mul9_4_1_2 = fmul i32 %arr_load_80, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_4_1_2"/></StgValue>
</operation>

<operation id="1325" st_id="247" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="429" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:46 %mul9_4_2 = fmul i32 %arr_load_81, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_4_2"/></StgValue>
</operation>

<operation id="1326" st_id="247" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="435" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:52 %mul9_4_2_1 = fmul i32 %arr_load_82, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_4_2_1"/></StgValue>
</operation>

<operation id="1327" st_id="247" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="440" bw="32" op_0_bw="11">
<![CDATA[
.split4.4:57 %arr_load_83 = load i11 %arr_addr_83

]]></Node>
<StgValue><ssdm name="arr_load_83"/></StgValue>
</operation>

<operation id="1328" st_id="247" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="441" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:58 %mul9_4_2_2 = fmul i32 %arr_load_83, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_4_2_2"/></StgValue>
</operation>
</state>

<state id="248" st_id="248">

<operation id="1329" st_id="248" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:11 %sum_2_4 = fadd i32 %mul9_4, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_4"/></StgValue>
</operation>

<operation id="1330" st_id="248" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="417" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:34 %mul9_4_1_1 = fmul i32 %arr_load_79, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_4_1_1"/></StgValue>
</operation>

<operation id="1331" st_id="248" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="423" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:40 %mul9_4_1_2 = fmul i32 %arr_load_80, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_4_1_2"/></StgValue>
</operation>

<operation id="1332" st_id="248" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="429" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:46 %mul9_4_2 = fmul i32 %arr_load_81, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_4_2"/></StgValue>
</operation>

<operation id="1333" st_id="248" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="435" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:52 %mul9_4_2_1 = fmul i32 %arr_load_82, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_4_2_1"/></StgValue>
</operation>

<operation id="1334" st_id="248" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="441" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:58 %mul9_4_2_2 = fmul i32 %arr_load_83, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_4_2_2"/></StgValue>
</operation>
</state>

<state id="249" st_id="249">

<operation id="1335" st_id="249" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:11 %sum_2_4 = fadd i32 %mul9_4, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_4"/></StgValue>
</operation>

<operation id="1336" st_id="249" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="429" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:46 %mul9_4_2 = fmul i32 %arr_load_81, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_4_2"/></StgValue>
</operation>

<operation id="1337" st_id="249" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="435" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:52 %mul9_4_2_1 = fmul i32 %arr_load_82, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_4_2_1"/></StgValue>
</operation>

<operation id="1338" st_id="249" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="441" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:58 %mul9_4_2_2 = fmul i32 %arr_load_83, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_4_2_2"/></StgValue>
</operation>
</state>

<state id="250" st_id="250">

<operation id="1339" st_id="250" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:11 %sum_2_4 = fadd i32 %mul9_4, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_4"/></StgValue>
</operation>

<operation id="1340" st_id="250" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="441" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:58 %mul9_4_2_2 = fmul i32 %arr_load_83, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_4_2_2"/></StgValue>
</operation>
</state>

<state id="251" st_id="251">

<operation id="1341" st_id="251" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:11 %sum_2_4 = fadd i32 %mul9_4, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_4"/></StgValue>
</operation>
</state>

<state id="252" st_id="252">

<operation id="1342" st_id="252" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:17 %sum_2_4_0_1 = fadd i32 %sum_2_4, i32 %mul9_4_0_1

]]></Node>
<StgValue><ssdm name="sum_2_4_0_1"/></StgValue>
</operation>
</state>

<state id="253" st_id="253">

<operation id="1343" st_id="253" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:17 %sum_2_4_0_1 = fadd i32 %sum_2_4, i32 %mul9_4_0_1

]]></Node>
<StgValue><ssdm name="sum_2_4_0_1"/></StgValue>
</operation>
</state>

<state id="254" st_id="254">

<operation id="1344" st_id="254" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:17 %sum_2_4_0_1 = fadd i32 %sum_2_4, i32 %mul9_4_0_1

]]></Node>
<StgValue><ssdm name="sum_2_4_0_1"/></StgValue>
</operation>
</state>

<state id="255" st_id="255">

<operation id="1345" st_id="255" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:17 %sum_2_4_0_1 = fadd i32 %sum_2_4, i32 %mul9_4_0_1

]]></Node>
<StgValue><ssdm name="sum_2_4_0_1"/></StgValue>
</operation>
</state>

<state id="256" st_id="256">

<operation id="1346" st_id="256" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:17 %sum_2_4_0_1 = fadd i32 %sum_2_4, i32 %mul9_4_0_1

]]></Node>
<StgValue><ssdm name="sum_2_4_0_1"/></StgValue>
</operation>
</state>

<state id="257" st_id="257">
</state>

<state id="258" st_id="258">

<operation id="1347" st_id="258" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:23 %sum_2_4_0_2 = fadd i32 %sum_2_4_0_1, i32 %mul9_4_0_2

]]></Node>
<StgValue><ssdm name="sum_2_4_0_2"/></StgValue>
</operation>
</state>

<state id="259" st_id="259">

<operation id="1348" st_id="259" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:23 %sum_2_4_0_2 = fadd i32 %sum_2_4_0_1, i32 %mul9_4_0_2

]]></Node>
<StgValue><ssdm name="sum_2_4_0_2"/></StgValue>
</operation>
</state>

<state id="260" st_id="260">

<operation id="1349" st_id="260" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:23 %sum_2_4_0_2 = fadd i32 %sum_2_4_0_1, i32 %mul9_4_0_2

]]></Node>
<StgValue><ssdm name="sum_2_4_0_2"/></StgValue>
</operation>
</state>

<state id="261" st_id="261">

<operation id="1350" st_id="261" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:23 %sum_2_4_0_2 = fadd i32 %sum_2_4_0_1, i32 %mul9_4_0_2

]]></Node>
<StgValue><ssdm name="sum_2_4_0_2"/></StgValue>
</operation>
</state>

<state id="262" st_id="262">

<operation id="1351" st_id="262" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:23 %sum_2_4_0_2 = fadd i32 %sum_2_4_0_1, i32 %mul9_4_0_2

]]></Node>
<StgValue><ssdm name="sum_2_4_0_2"/></StgValue>
</operation>
</state>

<state id="263" st_id="263">

<operation id="1352" st_id="263" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:29 %sum_2_4_1 = fadd i32 %sum_2_4_0_2, i32 %mul9_4_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1"/></StgValue>
</operation>
</state>

<state id="264" st_id="264">

<operation id="1353" st_id="264" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:29 %sum_2_4_1 = fadd i32 %sum_2_4_0_2, i32 %mul9_4_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1"/></StgValue>
</operation>
</state>

<state id="265" st_id="265">

<operation id="1354" st_id="265" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:29 %sum_2_4_1 = fadd i32 %sum_2_4_0_2, i32 %mul9_4_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1"/></StgValue>
</operation>
</state>

<state id="266" st_id="266">

<operation id="1355" st_id="266" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:29 %sum_2_4_1 = fadd i32 %sum_2_4_0_2, i32 %mul9_4_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1"/></StgValue>
</operation>
</state>

<state id="267" st_id="267">

<operation id="1356" st_id="267" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:29 %sum_2_4_1 = fadd i32 %sum_2_4_0_2, i32 %mul9_4_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1"/></StgValue>
</operation>
</state>

<state id="268" st_id="268">
</state>

<state id="269" st_id="269">

<operation id="1357" st_id="269" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:35 %sum_2_4_1_1 = fadd i32 %sum_2_4_1, i32 %mul9_4_1_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1_1"/></StgValue>
</operation>
</state>

<state id="270" st_id="270">

<operation id="1358" st_id="270" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:35 %sum_2_4_1_1 = fadd i32 %sum_2_4_1, i32 %mul9_4_1_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1_1"/></StgValue>
</operation>
</state>

<state id="271" st_id="271">

<operation id="1359" st_id="271" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:35 %sum_2_4_1_1 = fadd i32 %sum_2_4_1, i32 %mul9_4_1_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1_1"/></StgValue>
</operation>
</state>

<state id="272" st_id="272">

<operation id="1360" st_id="272" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:35 %sum_2_4_1_1 = fadd i32 %sum_2_4_1, i32 %mul9_4_1_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1_1"/></StgValue>
</operation>
</state>

<state id="273" st_id="273">

<operation id="1361" st_id="273" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:35 %sum_2_4_1_1 = fadd i32 %sum_2_4_1, i32 %mul9_4_1_1

]]></Node>
<StgValue><ssdm name="sum_2_4_1_1"/></StgValue>
</operation>
</state>

<state id="274" st_id="274">

<operation id="1362" st_id="274" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:41 %sum_2_4_1_2 = fadd i32 %sum_2_4_1_1, i32 %mul9_4_1_2

]]></Node>
<StgValue><ssdm name="sum_2_4_1_2"/></StgValue>
</operation>
</state>

<state id="275" st_id="275">

<operation id="1363" st_id="275" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:41 %sum_2_4_1_2 = fadd i32 %sum_2_4_1_1, i32 %mul9_4_1_2

]]></Node>
<StgValue><ssdm name="sum_2_4_1_2"/></StgValue>
</operation>
</state>

<state id="276" st_id="276">

<operation id="1364" st_id="276" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:41 %sum_2_4_1_2 = fadd i32 %sum_2_4_1_1, i32 %mul9_4_1_2

]]></Node>
<StgValue><ssdm name="sum_2_4_1_2"/></StgValue>
</operation>
</state>

<state id="277" st_id="277">

<operation id="1365" st_id="277" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:41 %sum_2_4_1_2 = fadd i32 %sum_2_4_1_1, i32 %mul9_4_1_2

]]></Node>
<StgValue><ssdm name="sum_2_4_1_2"/></StgValue>
</operation>
</state>

<state id="278" st_id="278">

<operation id="1366" st_id="278" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:41 %sum_2_4_1_2 = fadd i32 %sum_2_4_1_1, i32 %mul9_4_1_2

]]></Node>
<StgValue><ssdm name="sum_2_4_1_2"/></StgValue>
</operation>
</state>

<state id="279" st_id="279">
</state>

<state id="280" st_id="280">

<operation id="1367" st_id="280" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:47 %sum_2_4_2 = fadd i32 %sum_2_4_1_2, i32 %mul9_4_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2"/></StgValue>
</operation>
</state>

<state id="281" st_id="281">

<operation id="1368" st_id="281" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:47 %sum_2_4_2 = fadd i32 %sum_2_4_1_2, i32 %mul9_4_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2"/></StgValue>
</operation>
</state>

<state id="282" st_id="282">

<operation id="1369" st_id="282" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:47 %sum_2_4_2 = fadd i32 %sum_2_4_1_2, i32 %mul9_4_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2"/></StgValue>
</operation>
</state>

<state id="283" st_id="283">

<operation id="1370" st_id="283" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:47 %sum_2_4_2 = fadd i32 %sum_2_4_1_2, i32 %mul9_4_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2"/></StgValue>
</operation>
</state>

<state id="284" st_id="284">

<operation id="1371" st_id="284" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:47 %sum_2_4_2 = fadd i32 %sum_2_4_1_2, i32 %mul9_4_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2"/></StgValue>
</operation>
</state>

<state id="285" st_id="285">

<operation id="1372" st_id="285" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="436" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:53 %sum_2_4_2_1 = fadd i32 %sum_2_4_2, i32 %mul9_4_2_1

]]></Node>
<StgValue><ssdm name="sum_2_4_2_1"/></StgValue>
</operation>
</state>

<state id="286" st_id="286">

<operation id="1373" st_id="286" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="436" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:53 %sum_2_4_2_1 = fadd i32 %sum_2_4_2, i32 %mul9_4_2_1

]]></Node>
<StgValue><ssdm name="sum_2_4_2_1"/></StgValue>
</operation>
</state>

<state id="287" st_id="287">

<operation id="1374" st_id="287" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="436" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:53 %sum_2_4_2_1 = fadd i32 %sum_2_4_2, i32 %mul9_4_2_1

]]></Node>
<StgValue><ssdm name="sum_2_4_2_1"/></StgValue>
</operation>
</state>

<state id="288" st_id="288">

<operation id="1375" st_id="288" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="436" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:53 %sum_2_4_2_1 = fadd i32 %sum_2_4_2, i32 %mul9_4_2_1

]]></Node>
<StgValue><ssdm name="sum_2_4_2_1"/></StgValue>
</operation>
</state>

<state id="289" st_id="289">

<operation id="1376" st_id="289" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="436" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:53 %sum_2_4_2_1 = fadd i32 %sum_2_4_2, i32 %mul9_4_2_1

]]></Node>
<StgValue><ssdm name="sum_2_4_2_1"/></StgValue>
</operation>
</state>

<state id="290" st_id="290">
</state>

<state id="291" st_id="291">

<operation id="1377" st_id="291" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="442" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:59 %sum_2_4_2_2 = fadd i32 %sum_2_4_2_1, i32 %mul9_4_2_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2_2"/></StgValue>
</operation>
</state>

<state id="292" st_id="292">

<operation id="1378" st_id="292" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="442" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:59 %sum_2_4_2_2 = fadd i32 %sum_2_4_2_1, i32 %mul9_4_2_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2_2"/></StgValue>
</operation>
</state>

<state id="293" st_id="293">

<operation id="1379" st_id="293" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="442" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:59 %sum_2_4_2_2 = fadd i32 %sum_2_4_2_1, i32 %mul9_4_2_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2_2"/></StgValue>
</operation>
</state>

<state id="294" st_id="294">

<operation id="1380" st_id="294" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="442" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:59 %sum_2_4_2_2 = fadd i32 %sum_2_4_2_1, i32 %mul9_4_2_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2_2"/></StgValue>
</operation>
</state>

<state id="295" st_id="295">

<operation id="1381" st_id="295" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="442" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.4:59 %sum_2_4_2_2 = fadd i32 %sum_2_4_2_1, i32 %mul9_4_2_2

]]></Node>
<StgValue><ssdm name="sum_2_4_2_2"/></StgValue>
</operation>
</state>

<state id="296" st_id="296">

<operation id="1382" st_id="296" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="384" bw="64" op_0_bw="33">
<![CDATA[
.split4.4:1 %t_3_4_cast = zext i33 %t_3_4

]]></Node>
<StgValue><ssdm name="t_3_4_cast"/></StgValue>
</operation>

<operation id="1383" st_id="296" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="386" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.4:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1384" st_id="296" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="443" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.4:60 %add_ln58_4 = add i33 %t_3_4, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_4"/></StgValue>
</operation>

<operation id="1385" st_id="296" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="444" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.4:61 %out_addr_13 = getelementptr i32 %out_r, i64 0, i64 %t_3_4_cast

]]></Node>
<StgValue><ssdm name="out_addr_13"/></StgValue>
</operation>

<operation id="1386" st_id="296" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="445" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.4:62 %store_ln58 = store i32 %sum_2_4_2_2, i11 %out_addr_13

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1387" st_id="296" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="446" bw="0" op_0_bw="0">
<![CDATA[
.split4.4:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="297" st_id="297">

<operation id="1388" st_id="297" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="448" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.4:0 %add_ln44_10 = add i32 %zext_ln44_2, i32 %add_ln44_8

]]></Node>
<StgValue><ssdm name="add_ln44_10"/></StgValue>
</operation>

<operation id="1389" st_id="297" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="449" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.4:1 %add_ln44_11 = add i64 %i_0, i64 5

]]></Node>
<StgValue><ssdm name="add_ln44_11"/></StgValue>
</operation>

<operation id="1390" st_id="297" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="450" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.4:2 %icmp_ln44_5 = icmp_slt  i64 %add_ln44_11, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_5"/></StgValue>
</operation>

<operation id="1391" st_id="297" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="451" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.4:3 %br_ln44 = br i1 %icmp_ln44_5, void %._crit_edge13.loopexit, void %.lr.ph.5

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1392" st_id="297" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="454" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.5:1 %empty_123 = add i11 %trunc_ln44, i11 6

]]></Node>
<StgValue><ssdm name="empty_123"/></StgValue>
</operation>

<operation id="1393" st_id="297" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="455" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.5:2 %empty_124 = mul i11 %empty_123, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_124"/></StgValue>
</operation>
</state>

<state id="298" st_id="298">

<operation id="1394" st_id="298" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="455" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.5:2 %empty_124 = mul i11 %empty_123, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_124"/></StgValue>
</operation>
</state>

<state id="299" st_id="299">

<operation id="1395" st_id="299" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="455" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.5:2 %empty_124 = mul i11 %empty_123, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_124"/></StgValue>
</operation>
</state>

<state id="300" st_id="300">

<operation id="1396" st_id="300" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="453" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.5:0 %add_ln44_14_cast = sext i32 %add_ln44_10

]]></Node>
<StgValue><ssdm name="add_ln44_14_cast"/></StgValue>
</operation>

<operation id="1397" st_id="300" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="455" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.5:2 %empty_124 = mul i11 %empty_123, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_124"/></StgValue>
</operation>

<operation id="1398" st_id="300" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="456" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.5:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="301" st_id="301">

<operation id="1399" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="458" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_5 = phi i33 %add_ln58_5, void %.split4.5, i33 %add_ln44_14_cast, void %.lr.ph.5

]]></Node>
<StgValue><ssdm name="t_3_5"/></StgValue>
</operation>

<operation id="1400" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="459" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_5 = phi i6 %add_ln47_5, void %.split4.5, i6 1, void %.lr.ph.5

]]></Node>
<StgValue><ssdm name="j_5"/></StgValue>
</operation>

<operation id="1401" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="460" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1402" st_id="301" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="461" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_5 = icmp_eq  i6 %j_5, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_5"/></StgValue>
</operation>

<operation id="1403" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="462" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_122 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_122"/></StgValue>
</operation>

<operation id="1404" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="463" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_5, void %.split4.5, void %._crit_edge.loopexit.5

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1405" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="467" bw="11" op_0_bw="6">
<![CDATA[
.split4.5:2 %j_5_cast = zext i6 %j_5

]]></Node>
<StgValue><ssdm name="j_5_cast"/></StgValue>
</operation>

<operation id="1406" st_id="301" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="469" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.5:4 %empty_125 = add i6 %j_5, i6 63

]]></Node>
<StgValue><ssdm name="empty_125"/></StgValue>
</operation>

<operation id="1407" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="470" bw="11" op_0_bw="6">
<![CDATA[
.split4.5:5 %zext_ln8_89 = zext i6 %empty_125

]]></Node>
<StgValue><ssdm name="zext_ln8_89"/></StgValue>
</operation>

<operation id="1408" st_id="301" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="471" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:6 %add_ln8_84 = add i11 %zext_ln8_89, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_84"/></StgValue>
</operation>

<operation id="1409" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="472" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:7 %zext_ln8_90 = zext i11 %add_ln8_84

]]></Node>
<StgValue><ssdm name="zext_ln8_90"/></StgValue>
</operation>

<operation id="1410" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="473" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:8 %arr_addr_84 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_90

]]></Node>
<StgValue><ssdm name="arr_addr_84"/></StgValue>
</operation>

<operation id="1411" st_id="301" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="474" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:9 %arr_load_84 = load i11 %arr_addr_84

]]></Node>
<StgValue><ssdm name="arr_load_84"/></StgValue>
</operation>

<operation id="1412" st_id="301" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="477" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:12 %add_ln8_85 = add i11 %j_5_cast, i11 %empty_116

]]></Node>
<StgValue><ssdm name="add_ln8_85"/></StgValue>
</operation>

<operation id="1413" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="478" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:13 %zext_ln8_91 = zext i11 %add_ln8_85

]]></Node>
<StgValue><ssdm name="zext_ln8_91"/></StgValue>
</operation>

<operation id="1414" st_id="301" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="479" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:14 %arr_addr_85 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_91

]]></Node>
<StgValue><ssdm name="arr_addr_85"/></StgValue>
</operation>

<operation id="1415" st_id="301" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="480" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:15 %arr_load_85 = load i11 %arr_addr_85

]]></Node>
<StgValue><ssdm name="arr_load_85"/></StgValue>
</operation>
</state>

<state id="302" st_id="302">

<operation id="1416" st_id="302" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="474" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:9 %arr_load_84 = load i11 %arr_addr_84

]]></Node>
<StgValue><ssdm name="arr_load_84"/></StgValue>
</operation>

<operation id="1417" st_id="302" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="475" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:10 %mul9_5 = fmul i32 %arr_load_84, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_5"/></StgValue>
</operation>

<operation id="1418" st_id="302" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="480" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:15 %arr_load_85 = load i11 %arr_addr_85

]]></Node>
<StgValue><ssdm name="arr_load_85"/></StgValue>
</operation>

<operation id="1419" st_id="302" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="481" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:16 %mul9_5_0_1 = fmul i32 %arr_load_85, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_5_0_1"/></StgValue>
</operation>

<operation id="1420" st_id="302" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="483" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:18 %add_ln8_86 = add i11 %add_ln8_84, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_86"/></StgValue>
</operation>

<operation id="1421" st_id="302" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="484" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:19 %zext_ln8_92 = zext i11 %add_ln8_86

]]></Node>
<StgValue><ssdm name="zext_ln8_92"/></StgValue>
</operation>

<operation id="1422" st_id="302" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="485" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:20 %arr_addr_86 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_92

]]></Node>
<StgValue><ssdm name="arr_addr_86"/></StgValue>
</operation>

<operation id="1423" st_id="302" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="486" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:21 %arr_load_86 = load i11 %arr_addr_86

]]></Node>
<StgValue><ssdm name="arr_load_86"/></StgValue>
</operation>

<operation id="1424" st_id="302" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="489" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:24 %add_ln8_87 = add i11 %zext_ln8_89, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_87"/></StgValue>
</operation>

<operation id="1425" st_id="302" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="490" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:25 %zext_ln8_93 = zext i11 %add_ln8_87

]]></Node>
<StgValue><ssdm name="zext_ln8_93"/></StgValue>
</operation>

<operation id="1426" st_id="302" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="491" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:26 %arr_addr_87 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_93

]]></Node>
<StgValue><ssdm name="arr_addr_87"/></StgValue>
</operation>

<operation id="1427" st_id="302" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="492" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:27 %arr_load_87 = load i11 %arr_addr_87

]]></Node>
<StgValue><ssdm name="arr_load_87"/></StgValue>
</operation>
</state>

<state id="303" st_id="303">

<operation id="1428" st_id="303" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="475" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:10 %mul9_5 = fmul i32 %arr_load_84, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_5"/></StgValue>
</operation>

<operation id="1429" st_id="303" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="481" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:16 %mul9_5_0_1 = fmul i32 %arr_load_85, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_5_0_1"/></StgValue>
</operation>

<operation id="1430" st_id="303" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="486" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:21 %arr_load_86 = load i11 %arr_addr_86

]]></Node>
<StgValue><ssdm name="arr_load_86"/></StgValue>
</operation>

<operation id="1431" st_id="303" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="487" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:22 %mul9_5_0_2 = fmul i32 %arr_load_86, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_5_0_2"/></StgValue>
</operation>

<operation id="1432" st_id="303" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="492" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:27 %arr_load_87 = load i11 %arr_addr_87

]]></Node>
<StgValue><ssdm name="arr_load_87"/></StgValue>
</operation>

<operation id="1433" st_id="303" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="493" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:28 %mul9_5_1 = fmul i32 %arr_load_87, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_5_1"/></StgValue>
</operation>

<operation id="1434" st_id="303" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="495" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:30 %add_ln8_88 = add i11 %j_5_cast, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_88"/></StgValue>
</operation>

<operation id="1435" st_id="303" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="496" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:31 %zext_ln8_94 = zext i11 %add_ln8_88

]]></Node>
<StgValue><ssdm name="zext_ln8_94"/></StgValue>
</operation>

<operation id="1436" st_id="303" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="497" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:32 %arr_addr_88 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_94

]]></Node>
<StgValue><ssdm name="arr_addr_88"/></StgValue>
</operation>

<operation id="1437" st_id="303" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="498" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:33 %arr_load_88 = load i11 %arr_addr_88

]]></Node>
<StgValue><ssdm name="arr_load_88"/></StgValue>
</operation>

<operation id="1438" st_id="303" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="501" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:36 %add_ln8_89 = add i11 %add_ln8_87, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_89"/></StgValue>
</operation>

<operation id="1439" st_id="303" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="502" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:37 %zext_ln8_95 = zext i11 %add_ln8_89

]]></Node>
<StgValue><ssdm name="zext_ln8_95"/></StgValue>
</operation>

<operation id="1440" st_id="303" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="503" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:38 %arr_addr_89 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_95

]]></Node>
<StgValue><ssdm name="arr_addr_89"/></StgValue>
</operation>

<operation id="1441" st_id="303" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="504" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:39 %arr_load_89 = load i11 %arr_addr_89

]]></Node>
<StgValue><ssdm name="arr_load_89"/></StgValue>
</operation>
</state>

<state id="304" st_id="304">

<operation id="1442" st_id="304" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="475" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:10 %mul9_5 = fmul i32 %arr_load_84, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_5"/></StgValue>
</operation>

<operation id="1443" st_id="304" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="481" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:16 %mul9_5_0_1 = fmul i32 %arr_load_85, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_5_0_1"/></StgValue>
</operation>

<operation id="1444" st_id="304" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="487" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:22 %mul9_5_0_2 = fmul i32 %arr_load_86, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_5_0_2"/></StgValue>
</operation>

<operation id="1445" st_id="304" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="493" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:28 %mul9_5_1 = fmul i32 %arr_load_87, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_5_1"/></StgValue>
</operation>

<operation id="1446" st_id="304" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="498" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:33 %arr_load_88 = load i11 %arr_addr_88

]]></Node>
<StgValue><ssdm name="arr_load_88"/></StgValue>
</operation>

<operation id="1447" st_id="304" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="499" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:34 %mul9_5_1_1 = fmul i32 %arr_load_88, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_5_1_1"/></StgValue>
</operation>

<operation id="1448" st_id="304" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="504" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:39 %arr_load_89 = load i11 %arr_addr_89

]]></Node>
<StgValue><ssdm name="arr_load_89"/></StgValue>
</operation>

<operation id="1449" st_id="304" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="505" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:40 %mul9_5_1_2 = fmul i32 %arr_load_89, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_5_1_2"/></StgValue>
</operation>

<operation id="1450" st_id="304" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="507" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:42 %add_ln8_90 = add i11 %zext_ln8_89, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_90"/></StgValue>
</operation>

<operation id="1451" st_id="304" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="508" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:43 %zext_ln8_96 = zext i11 %add_ln8_90

]]></Node>
<StgValue><ssdm name="zext_ln8_96"/></StgValue>
</operation>

<operation id="1452" st_id="304" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="509" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:44 %arr_addr_90 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_96

]]></Node>
<StgValue><ssdm name="arr_addr_90"/></StgValue>
</operation>

<operation id="1453" st_id="304" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="510" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:45 %arr_load_90 = load i11 %arr_addr_90

]]></Node>
<StgValue><ssdm name="arr_load_90"/></StgValue>
</operation>

<operation id="1454" st_id="304" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="513" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:48 %add_ln8_91 = add i11 %j_5_cast, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_91"/></StgValue>
</operation>

<operation id="1455" st_id="304" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="514" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:49 %zext_ln8_97 = zext i11 %add_ln8_91

]]></Node>
<StgValue><ssdm name="zext_ln8_97"/></StgValue>
</operation>

<operation id="1456" st_id="304" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="515" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:50 %arr_addr_91 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_97

]]></Node>
<StgValue><ssdm name="arr_addr_91"/></StgValue>
</operation>

<operation id="1457" st_id="304" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="516" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:51 %arr_load_91 = load i11 %arr_addr_91

]]></Node>
<StgValue><ssdm name="arr_load_91"/></StgValue>
</operation>
</state>

<state id="305" st_id="305">

<operation id="1458" st_id="305" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="465" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.5:0 %add_ln47_5 = add i6 %j_5, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_5"/></StgValue>
</operation>

<operation id="1459" st_id="305" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="475" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:10 %mul9_5 = fmul i32 %arr_load_84, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_5"/></StgValue>
</operation>

<operation id="1460" st_id="305" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="481" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:16 %mul9_5_0_1 = fmul i32 %arr_load_85, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_5_0_1"/></StgValue>
</operation>

<operation id="1461" st_id="305" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="487" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:22 %mul9_5_0_2 = fmul i32 %arr_load_86, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_5_0_2"/></StgValue>
</operation>

<operation id="1462" st_id="305" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="493" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:28 %mul9_5_1 = fmul i32 %arr_load_87, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_5_1"/></StgValue>
</operation>

<operation id="1463" st_id="305" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="499" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:34 %mul9_5_1_1 = fmul i32 %arr_load_88, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_5_1_1"/></StgValue>
</operation>

<operation id="1464" st_id="305" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="505" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:40 %mul9_5_1_2 = fmul i32 %arr_load_89, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_5_1_2"/></StgValue>
</operation>

<operation id="1465" st_id="305" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="510" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:45 %arr_load_90 = load i11 %arr_addr_90

]]></Node>
<StgValue><ssdm name="arr_load_90"/></StgValue>
</operation>

<operation id="1466" st_id="305" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="511" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:46 %mul9_5_2 = fmul i32 %arr_load_90, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_5_2"/></StgValue>
</operation>

<operation id="1467" st_id="305" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="516" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:51 %arr_load_91 = load i11 %arr_addr_91

]]></Node>
<StgValue><ssdm name="arr_load_91"/></StgValue>
</operation>

<operation id="1468" st_id="305" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:52 %mul9_5_2_1 = fmul i32 %arr_load_91, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_5_2_1"/></StgValue>
</operation>

<operation id="1469" st_id="305" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="519" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:54 %add_ln8_92 = add i11 %add_ln8_90, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_92"/></StgValue>
</operation>

<operation id="1470" st_id="305" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="520" bw="64" op_0_bw="11">
<![CDATA[
.split4.5:55 %zext_ln8_98 = zext i11 %add_ln8_92

]]></Node>
<StgValue><ssdm name="zext_ln8_98"/></StgValue>
</operation>

<operation id="1471" st_id="305" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="521" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:56 %arr_addr_92 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_98

]]></Node>
<StgValue><ssdm name="arr_addr_92"/></StgValue>
</operation>

<operation id="1472" st_id="305" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="522" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:57 %arr_load_92 = load i11 %arr_addr_92

]]></Node>
<StgValue><ssdm name="arr_load_92"/></StgValue>
</operation>
</state>

<state id="306" st_id="306">

<operation id="1473" st_id="306" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:11 %sum_2_5 = fadd i32 %mul9_5, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_5"/></StgValue>
</operation>

<operation id="1474" st_id="306" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="487" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:22 %mul9_5_0_2 = fmul i32 %arr_load_86, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_5_0_2"/></StgValue>
</operation>

<operation id="1475" st_id="306" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="493" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:28 %mul9_5_1 = fmul i32 %arr_load_87, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_5_1"/></StgValue>
</operation>

<operation id="1476" st_id="306" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="499" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:34 %mul9_5_1_1 = fmul i32 %arr_load_88, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_5_1_1"/></StgValue>
</operation>

<operation id="1477" st_id="306" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="505" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:40 %mul9_5_1_2 = fmul i32 %arr_load_89, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_5_1_2"/></StgValue>
</operation>

<operation id="1478" st_id="306" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="511" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:46 %mul9_5_2 = fmul i32 %arr_load_90, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_5_2"/></StgValue>
</operation>

<operation id="1479" st_id="306" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:52 %mul9_5_2_1 = fmul i32 %arr_load_91, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_5_2_1"/></StgValue>
</operation>

<operation id="1480" st_id="306" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="522" bw="32" op_0_bw="11">
<![CDATA[
.split4.5:57 %arr_load_92 = load i11 %arr_addr_92

]]></Node>
<StgValue><ssdm name="arr_load_92"/></StgValue>
</operation>

<operation id="1481" st_id="306" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="523" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:58 %mul9_5_2_2 = fmul i32 %arr_load_92, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_5_2_2"/></StgValue>
</operation>
</state>

<state id="307" st_id="307">

<operation id="1482" st_id="307" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:11 %sum_2_5 = fadd i32 %mul9_5, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_5"/></StgValue>
</operation>

<operation id="1483" st_id="307" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="499" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:34 %mul9_5_1_1 = fmul i32 %arr_load_88, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_5_1_1"/></StgValue>
</operation>

<operation id="1484" st_id="307" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="505" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:40 %mul9_5_1_2 = fmul i32 %arr_load_89, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_5_1_2"/></StgValue>
</operation>

<operation id="1485" st_id="307" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="511" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:46 %mul9_5_2 = fmul i32 %arr_load_90, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_5_2"/></StgValue>
</operation>

<operation id="1486" st_id="307" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:52 %mul9_5_2_1 = fmul i32 %arr_load_91, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_5_2_1"/></StgValue>
</operation>

<operation id="1487" st_id="307" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="523" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:58 %mul9_5_2_2 = fmul i32 %arr_load_92, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_5_2_2"/></StgValue>
</operation>
</state>

<state id="308" st_id="308">

<operation id="1488" st_id="308" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:11 %sum_2_5 = fadd i32 %mul9_5, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_5"/></StgValue>
</operation>

<operation id="1489" st_id="308" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="511" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:46 %mul9_5_2 = fmul i32 %arr_load_90, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_5_2"/></StgValue>
</operation>

<operation id="1490" st_id="308" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:52 %mul9_5_2_1 = fmul i32 %arr_load_91, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_5_2_1"/></StgValue>
</operation>

<operation id="1491" st_id="308" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="523" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:58 %mul9_5_2_2 = fmul i32 %arr_load_92, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_5_2_2"/></StgValue>
</operation>
</state>

<state id="309" st_id="309">

<operation id="1492" st_id="309" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:11 %sum_2_5 = fadd i32 %mul9_5, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_5"/></StgValue>
</operation>

<operation id="1493" st_id="309" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="523" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:58 %mul9_5_2_2 = fmul i32 %arr_load_92, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_5_2_2"/></StgValue>
</operation>
</state>

<state id="310" st_id="310">

<operation id="1494" st_id="310" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:11 %sum_2_5 = fadd i32 %mul9_5, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_5"/></StgValue>
</operation>
</state>

<state id="311" st_id="311">

<operation id="1495" st_id="311" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:17 %sum_2_5_0_1 = fadd i32 %sum_2_5, i32 %mul9_5_0_1

]]></Node>
<StgValue><ssdm name="sum_2_5_0_1"/></StgValue>
</operation>
</state>

<state id="312" st_id="312">

<operation id="1496" st_id="312" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:17 %sum_2_5_0_1 = fadd i32 %sum_2_5, i32 %mul9_5_0_1

]]></Node>
<StgValue><ssdm name="sum_2_5_0_1"/></StgValue>
</operation>
</state>

<state id="313" st_id="313">

<operation id="1497" st_id="313" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:17 %sum_2_5_0_1 = fadd i32 %sum_2_5, i32 %mul9_5_0_1

]]></Node>
<StgValue><ssdm name="sum_2_5_0_1"/></StgValue>
</operation>
</state>

<state id="314" st_id="314">

<operation id="1498" st_id="314" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:17 %sum_2_5_0_1 = fadd i32 %sum_2_5, i32 %mul9_5_0_1

]]></Node>
<StgValue><ssdm name="sum_2_5_0_1"/></StgValue>
</operation>
</state>

<state id="315" st_id="315">

<operation id="1499" st_id="315" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:17 %sum_2_5_0_1 = fadd i32 %sum_2_5, i32 %mul9_5_0_1

]]></Node>
<StgValue><ssdm name="sum_2_5_0_1"/></StgValue>
</operation>
</state>

<state id="316" st_id="316">
</state>

<state id="317" st_id="317">

<operation id="1500" st_id="317" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:23 %sum_2_5_0_2 = fadd i32 %sum_2_5_0_1, i32 %mul9_5_0_2

]]></Node>
<StgValue><ssdm name="sum_2_5_0_2"/></StgValue>
</operation>
</state>

<state id="318" st_id="318">

<operation id="1501" st_id="318" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:23 %sum_2_5_0_2 = fadd i32 %sum_2_5_0_1, i32 %mul9_5_0_2

]]></Node>
<StgValue><ssdm name="sum_2_5_0_2"/></StgValue>
</operation>
</state>

<state id="319" st_id="319">

<operation id="1502" st_id="319" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:23 %sum_2_5_0_2 = fadd i32 %sum_2_5_0_1, i32 %mul9_5_0_2

]]></Node>
<StgValue><ssdm name="sum_2_5_0_2"/></StgValue>
</operation>
</state>

<state id="320" st_id="320">

<operation id="1503" st_id="320" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:23 %sum_2_5_0_2 = fadd i32 %sum_2_5_0_1, i32 %mul9_5_0_2

]]></Node>
<StgValue><ssdm name="sum_2_5_0_2"/></StgValue>
</operation>
</state>

<state id="321" st_id="321">

<operation id="1504" st_id="321" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:23 %sum_2_5_0_2 = fadd i32 %sum_2_5_0_1, i32 %mul9_5_0_2

]]></Node>
<StgValue><ssdm name="sum_2_5_0_2"/></StgValue>
</operation>
</state>

<state id="322" st_id="322">

<operation id="1505" st_id="322" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:29 %sum_2_5_1 = fadd i32 %sum_2_5_0_2, i32 %mul9_5_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1"/></StgValue>
</operation>
</state>

<state id="323" st_id="323">

<operation id="1506" st_id="323" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:29 %sum_2_5_1 = fadd i32 %sum_2_5_0_2, i32 %mul9_5_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1"/></StgValue>
</operation>
</state>

<state id="324" st_id="324">

<operation id="1507" st_id="324" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:29 %sum_2_5_1 = fadd i32 %sum_2_5_0_2, i32 %mul9_5_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1"/></StgValue>
</operation>
</state>

<state id="325" st_id="325">

<operation id="1508" st_id="325" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:29 %sum_2_5_1 = fadd i32 %sum_2_5_0_2, i32 %mul9_5_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1"/></StgValue>
</operation>
</state>

<state id="326" st_id="326">

<operation id="1509" st_id="326" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:29 %sum_2_5_1 = fadd i32 %sum_2_5_0_2, i32 %mul9_5_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1"/></StgValue>
</operation>
</state>

<state id="327" st_id="327">
</state>

<state id="328" st_id="328">

<operation id="1510" st_id="328" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:35 %sum_2_5_1_1 = fadd i32 %sum_2_5_1, i32 %mul9_5_1_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1_1"/></StgValue>
</operation>
</state>

<state id="329" st_id="329">

<operation id="1511" st_id="329" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:35 %sum_2_5_1_1 = fadd i32 %sum_2_5_1, i32 %mul9_5_1_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1_1"/></StgValue>
</operation>
</state>

<state id="330" st_id="330">

<operation id="1512" st_id="330" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:35 %sum_2_5_1_1 = fadd i32 %sum_2_5_1, i32 %mul9_5_1_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1_1"/></StgValue>
</operation>
</state>

<state id="331" st_id="331">

<operation id="1513" st_id="331" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:35 %sum_2_5_1_1 = fadd i32 %sum_2_5_1, i32 %mul9_5_1_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1_1"/></StgValue>
</operation>
</state>

<state id="332" st_id="332">

<operation id="1514" st_id="332" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:35 %sum_2_5_1_1 = fadd i32 %sum_2_5_1, i32 %mul9_5_1_1

]]></Node>
<StgValue><ssdm name="sum_2_5_1_1"/></StgValue>
</operation>
</state>

<state id="333" st_id="333">

<operation id="1515" st_id="333" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:41 %sum_2_5_1_2 = fadd i32 %sum_2_5_1_1, i32 %mul9_5_1_2

]]></Node>
<StgValue><ssdm name="sum_2_5_1_2"/></StgValue>
</operation>
</state>

<state id="334" st_id="334">

<operation id="1516" st_id="334" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:41 %sum_2_5_1_2 = fadd i32 %sum_2_5_1_1, i32 %mul9_5_1_2

]]></Node>
<StgValue><ssdm name="sum_2_5_1_2"/></StgValue>
</operation>
</state>

<state id="335" st_id="335">

<operation id="1517" st_id="335" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:41 %sum_2_5_1_2 = fadd i32 %sum_2_5_1_1, i32 %mul9_5_1_2

]]></Node>
<StgValue><ssdm name="sum_2_5_1_2"/></StgValue>
</operation>
</state>

<state id="336" st_id="336">

<operation id="1518" st_id="336" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:41 %sum_2_5_1_2 = fadd i32 %sum_2_5_1_1, i32 %mul9_5_1_2

]]></Node>
<StgValue><ssdm name="sum_2_5_1_2"/></StgValue>
</operation>
</state>

<state id="337" st_id="337">

<operation id="1519" st_id="337" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:41 %sum_2_5_1_2 = fadd i32 %sum_2_5_1_1, i32 %mul9_5_1_2

]]></Node>
<StgValue><ssdm name="sum_2_5_1_2"/></StgValue>
</operation>
</state>

<state id="338" st_id="338">
</state>

<state id="339" st_id="339">

<operation id="1520" st_id="339" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:47 %sum_2_5_2 = fadd i32 %sum_2_5_1_2, i32 %mul9_5_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2"/></StgValue>
</operation>
</state>

<state id="340" st_id="340">

<operation id="1521" st_id="340" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:47 %sum_2_5_2 = fadd i32 %sum_2_5_1_2, i32 %mul9_5_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2"/></StgValue>
</operation>
</state>

<state id="341" st_id="341">

<operation id="1522" st_id="341" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:47 %sum_2_5_2 = fadd i32 %sum_2_5_1_2, i32 %mul9_5_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2"/></StgValue>
</operation>
</state>

<state id="342" st_id="342">

<operation id="1523" st_id="342" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:47 %sum_2_5_2 = fadd i32 %sum_2_5_1_2, i32 %mul9_5_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2"/></StgValue>
</operation>
</state>

<state id="343" st_id="343">

<operation id="1524" st_id="343" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:47 %sum_2_5_2 = fadd i32 %sum_2_5_1_2, i32 %mul9_5_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2"/></StgValue>
</operation>
</state>

<state id="344" st_id="344">

<operation id="1525" st_id="344" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:53 %sum_2_5_2_1 = fadd i32 %sum_2_5_2, i32 %mul9_5_2_1

]]></Node>
<StgValue><ssdm name="sum_2_5_2_1"/></StgValue>
</operation>
</state>

<state id="345" st_id="345">

<operation id="1526" st_id="345" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:53 %sum_2_5_2_1 = fadd i32 %sum_2_5_2, i32 %mul9_5_2_1

]]></Node>
<StgValue><ssdm name="sum_2_5_2_1"/></StgValue>
</operation>
</state>

<state id="346" st_id="346">

<operation id="1527" st_id="346" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:53 %sum_2_5_2_1 = fadd i32 %sum_2_5_2, i32 %mul9_5_2_1

]]></Node>
<StgValue><ssdm name="sum_2_5_2_1"/></StgValue>
</operation>
</state>

<state id="347" st_id="347">

<operation id="1528" st_id="347" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:53 %sum_2_5_2_1 = fadd i32 %sum_2_5_2, i32 %mul9_5_2_1

]]></Node>
<StgValue><ssdm name="sum_2_5_2_1"/></StgValue>
</operation>
</state>

<state id="348" st_id="348">

<operation id="1529" st_id="348" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:53 %sum_2_5_2_1 = fadd i32 %sum_2_5_2, i32 %mul9_5_2_1

]]></Node>
<StgValue><ssdm name="sum_2_5_2_1"/></StgValue>
</operation>
</state>

<state id="349" st_id="349">
</state>

<state id="350" st_id="350">

<operation id="1530" st_id="350" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:59 %sum_2_5_2_2 = fadd i32 %sum_2_5_2_1, i32 %mul9_5_2_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2_2"/></StgValue>
</operation>
</state>

<state id="351" st_id="351">

<operation id="1531" st_id="351" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:59 %sum_2_5_2_2 = fadd i32 %sum_2_5_2_1, i32 %mul9_5_2_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2_2"/></StgValue>
</operation>
</state>

<state id="352" st_id="352">

<operation id="1532" st_id="352" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:59 %sum_2_5_2_2 = fadd i32 %sum_2_5_2_1, i32 %mul9_5_2_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2_2"/></StgValue>
</operation>
</state>

<state id="353" st_id="353">

<operation id="1533" st_id="353" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:59 %sum_2_5_2_2 = fadd i32 %sum_2_5_2_1, i32 %mul9_5_2_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2_2"/></StgValue>
</operation>
</state>

<state id="354" st_id="354">

<operation id="1534" st_id="354" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.5:59 %sum_2_5_2_2 = fadd i32 %sum_2_5_2_1, i32 %mul9_5_2_2

]]></Node>
<StgValue><ssdm name="sum_2_5_2_2"/></StgValue>
</operation>
</state>

<state id="355" st_id="355">

<operation id="1535" st_id="355" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="466" bw="64" op_0_bw="33">
<![CDATA[
.split4.5:1 %t_3_5_cast = zext i33 %t_3_5

]]></Node>
<StgValue><ssdm name="t_3_5_cast"/></StgValue>
</operation>

<operation id="1536" st_id="355" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="468" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.5:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1537" st_id="355" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="525" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.5:60 %add_ln58_5 = add i33 %t_3_5, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_5"/></StgValue>
</operation>

<operation id="1538" st_id="355" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="526" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.5:61 %out_addr_14 = getelementptr i32 %out_r, i64 0, i64 %t_3_5_cast

]]></Node>
<StgValue><ssdm name="out_addr_14"/></StgValue>
</operation>

<operation id="1539" st_id="355" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="527" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.5:62 %store_ln58 = store i32 %sum_2_5_2_2, i11 %out_addr_14

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1540" st_id="355" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="528" bw="0" op_0_bw="0">
<![CDATA[
.split4.5:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="356" st_id="356">

<operation id="1541" st_id="356" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="530" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.5:0 %add_ln44_12 = add i32 %zext_ln44_2, i32 %add_ln44_10

]]></Node>
<StgValue><ssdm name="add_ln44_12"/></StgValue>
</operation>

<operation id="1542" st_id="356" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="531" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.5:1 %add_ln44_13 = add i64 %i_0, i64 6

]]></Node>
<StgValue><ssdm name="add_ln44_13"/></StgValue>
</operation>

<operation id="1543" st_id="356" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="532" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.5:2 %icmp_ln44_6 = icmp_slt  i64 %add_ln44_13, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_6"/></StgValue>
</operation>

<operation id="1544" st_id="356" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="533" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.5:3 %br_ln44 = br i1 %icmp_ln44_6, void %._crit_edge13.loopexit, void %.lr.ph.6

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1545" st_id="356" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_6" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="536" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.6:1 %empty_127 = add i11 %trunc_ln44, i11 7

]]></Node>
<StgValue><ssdm name="empty_127"/></StgValue>
</operation>

<operation id="1546" st_id="356" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_6" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="537" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.6:2 %empty_128 = mul i11 %empty_127, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_128"/></StgValue>
</operation>
</state>

<state id="357" st_id="357">

<operation id="1547" st_id="357" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="537" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.6:2 %empty_128 = mul i11 %empty_127, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_128"/></StgValue>
</operation>
</state>

<state id="358" st_id="358">

<operation id="1548" st_id="358" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="537" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.6:2 %empty_128 = mul i11 %empty_127, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_128"/></StgValue>
</operation>
</state>

<state id="359" st_id="359">

<operation id="1549" st_id="359" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="535" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.6:0 %add_ln44_17_cast = sext i32 %add_ln44_12

]]></Node>
<StgValue><ssdm name="add_ln44_17_cast"/></StgValue>
</operation>

<operation id="1550" st_id="359" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="537" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.6:2 %empty_128 = mul i11 %empty_127, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_128"/></StgValue>
</operation>

<operation id="1551" st_id="359" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="538" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.6:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="360" st_id="360">

<operation id="1552" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="540" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_6 = phi i33 %add_ln58_6, void %.split4.6, i33 %add_ln44_17_cast, void %.lr.ph.6

]]></Node>
<StgValue><ssdm name="t_3_6"/></StgValue>
</operation>

<operation id="1553" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="541" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_6 = phi i6 %add_ln47_6, void %.split4.6, i6 1, void %.lr.ph.6

]]></Node>
<StgValue><ssdm name="j_6"/></StgValue>
</operation>

<operation id="1554" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="542" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1555" st_id="360" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="543" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_6 = icmp_eq  i6 %j_6, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_6"/></StgValue>
</operation>

<operation id="1556" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="544" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_126 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_126"/></StgValue>
</operation>

<operation id="1557" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="545" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_6, void %.split4.6, void %._crit_edge.loopexit.6

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1558" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="549" bw="11" op_0_bw="6">
<![CDATA[
.split4.6:2 %j_6_cast = zext i6 %j_6

]]></Node>
<StgValue><ssdm name="j_6_cast"/></StgValue>
</operation>

<operation id="1559" st_id="360" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="551" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.6:4 %empty_129 = add i6 %j_6, i6 63

]]></Node>
<StgValue><ssdm name="empty_129"/></StgValue>
</operation>

<operation id="1560" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="552" bw="11" op_0_bw="6">
<![CDATA[
.split4.6:5 %zext_ln8_99 = zext i6 %empty_129

]]></Node>
<StgValue><ssdm name="zext_ln8_99"/></StgValue>
</operation>

<operation id="1561" st_id="360" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="553" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:6 %add_ln8_93 = add i11 %zext_ln8_99, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_93"/></StgValue>
</operation>

<operation id="1562" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="554" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:7 %zext_ln8_100 = zext i11 %add_ln8_93

]]></Node>
<StgValue><ssdm name="zext_ln8_100"/></StgValue>
</operation>

<operation id="1563" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="555" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:8 %arr_addr_93 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_100

]]></Node>
<StgValue><ssdm name="arr_addr_93"/></StgValue>
</operation>

<operation id="1564" st_id="360" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="556" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:9 %arr_load_93 = load i11 %arr_addr_93

]]></Node>
<StgValue><ssdm name="arr_load_93"/></StgValue>
</operation>

<operation id="1565" st_id="360" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="559" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:12 %add_ln8_94 = add i11 %j_6_cast, i11 %empty_120

]]></Node>
<StgValue><ssdm name="add_ln8_94"/></StgValue>
</operation>

<operation id="1566" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="560" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:13 %zext_ln8_101 = zext i11 %add_ln8_94

]]></Node>
<StgValue><ssdm name="zext_ln8_101"/></StgValue>
</operation>

<operation id="1567" st_id="360" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="561" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:14 %arr_addr_94 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_101

]]></Node>
<StgValue><ssdm name="arr_addr_94"/></StgValue>
</operation>

<operation id="1568" st_id="360" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="562" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:15 %arr_load_94 = load i11 %arr_addr_94

]]></Node>
<StgValue><ssdm name="arr_load_94"/></StgValue>
</operation>
</state>

<state id="361" st_id="361">

<operation id="1569" st_id="361" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="556" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:9 %arr_load_93 = load i11 %arr_addr_93

]]></Node>
<StgValue><ssdm name="arr_load_93"/></StgValue>
</operation>

<operation id="1570" st_id="361" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="557" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:10 %mul9_6 = fmul i32 %arr_load_93, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_6"/></StgValue>
</operation>

<operation id="1571" st_id="361" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="562" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:15 %arr_load_94 = load i11 %arr_addr_94

]]></Node>
<StgValue><ssdm name="arr_load_94"/></StgValue>
</operation>

<operation id="1572" st_id="361" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="563" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:16 %mul9_6_0_1 = fmul i32 %arr_load_94, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_6_0_1"/></StgValue>
</operation>

<operation id="1573" st_id="361" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="565" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:18 %add_ln8_95 = add i11 %add_ln8_93, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_95"/></StgValue>
</operation>

<operation id="1574" st_id="361" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="566" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:19 %zext_ln8_102 = zext i11 %add_ln8_95

]]></Node>
<StgValue><ssdm name="zext_ln8_102"/></StgValue>
</operation>

<operation id="1575" st_id="361" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="567" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:20 %arr_addr_95 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_102

]]></Node>
<StgValue><ssdm name="arr_addr_95"/></StgValue>
</operation>

<operation id="1576" st_id="361" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="568" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:21 %arr_load_95 = load i11 %arr_addr_95

]]></Node>
<StgValue><ssdm name="arr_load_95"/></StgValue>
</operation>

<operation id="1577" st_id="361" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="571" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:24 %add_ln8_96 = add i11 %zext_ln8_99, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_96"/></StgValue>
</operation>

<operation id="1578" st_id="361" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="572" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:25 %zext_ln8_103 = zext i11 %add_ln8_96

]]></Node>
<StgValue><ssdm name="zext_ln8_103"/></StgValue>
</operation>

<operation id="1579" st_id="361" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="573" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:26 %arr_addr_96 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_103

]]></Node>
<StgValue><ssdm name="arr_addr_96"/></StgValue>
</operation>

<operation id="1580" st_id="361" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="574" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:27 %arr_load_96 = load i11 %arr_addr_96

]]></Node>
<StgValue><ssdm name="arr_load_96"/></StgValue>
</operation>
</state>

<state id="362" st_id="362">

<operation id="1581" st_id="362" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="557" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:10 %mul9_6 = fmul i32 %arr_load_93, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_6"/></StgValue>
</operation>

<operation id="1582" st_id="362" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="563" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:16 %mul9_6_0_1 = fmul i32 %arr_load_94, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_6_0_1"/></StgValue>
</operation>

<operation id="1583" st_id="362" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="568" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:21 %arr_load_95 = load i11 %arr_addr_95

]]></Node>
<StgValue><ssdm name="arr_load_95"/></StgValue>
</operation>

<operation id="1584" st_id="362" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="569" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:22 %mul9_6_0_2 = fmul i32 %arr_load_95, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_6_0_2"/></StgValue>
</operation>

<operation id="1585" st_id="362" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="574" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:27 %arr_load_96 = load i11 %arr_addr_96

]]></Node>
<StgValue><ssdm name="arr_load_96"/></StgValue>
</operation>

<operation id="1586" st_id="362" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:28 %mul9_6_1 = fmul i32 %arr_load_96, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_6_1"/></StgValue>
</operation>

<operation id="1587" st_id="362" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="577" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:30 %add_ln8_97 = add i11 %j_6_cast, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_97"/></StgValue>
</operation>

<operation id="1588" st_id="362" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="578" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:31 %zext_ln8_104 = zext i11 %add_ln8_97

]]></Node>
<StgValue><ssdm name="zext_ln8_104"/></StgValue>
</operation>

<operation id="1589" st_id="362" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="579" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:32 %arr_addr_97 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_104

]]></Node>
<StgValue><ssdm name="arr_addr_97"/></StgValue>
</operation>

<operation id="1590" st_id="362" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="580" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:33 %arr_load_97 = load i11 %arr_addr_97

]]></Node>
<StgValue><ssdm name="arr_load_97"/></StgValue>
</operation>

<operation id="1591" st_id="362" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="583" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:36 %add_ln8_98 = add i11 %add_ln8_96, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_98"/></StgValue>
</operation>

<operation id="1592" st_id="362" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="584" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:37 %zext_ln8_105 = zext i11 %add_ln8_98

]]></Node>
<StgValue><ssdm name="zext_ln8_105"/></StgValue>
</operation>

<operation id="1593" st_id="362" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="585" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:38 %arr_addr_98 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_105

]]></Node>
<StgValue><ssdm name="arr_addr_98"/></StgValue>
</operation>

<operation id="1594" st_id="362" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="586" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:39 %arr_load_98 = load i11 %arr_addr_98

]]></Node>
<StgValue><ssdm name="arr_load_98"/></StgValue>
</operation>
</state>

<state id="363" st_id="363">

<operation id="1595" st_id="363" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="557" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:10 %mul9_6 = fmul i32 %arr_load_93, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_6"/></StgValue>
</operation>

<operation id="1596" st_id="363" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="563" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:16 %mul9_6_0_1 = fmul i32 %arr_load_94, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_6_0_1"/></StgValue>
</operation>

<operation id="1597" st_id="363" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="569" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:22 %mul9_6_0_2 = fmul i32 %arr_load_95, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_6_0_2"/></StgValue>
</operation>

<operation id="1598" st_id="363" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:28 %mul9_6_1 = fmul i32 %arr_load_96, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_6_1"/></StgValue>
</operation>

<operation id="1599" st_id="363" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="580" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:33 %arr_load_97 = load i11 %arr_addr_97

]]></Node>
<StgValue><ssdm name="arr_load_97"/></StgValue>
</operation>

<operation id="1600" st_id="363" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="581" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:34 %mul9_6_1_1 = fmul i32 %arr_load_97, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_6_1_1"/></StgValue>
</operation>

<operation id="1601" st_id="363" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="586" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:39 %arr_load_98 = load i11 %arr_addr_98

]]></Node>
<StgValue><ssdm name="arr_load_98"/></StgValue>
</operation>

<operation id="1602" st_id="363" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="587" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:40 %mul9_6_1_2 = fmul i32 %arr_load_98, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_6_1_2"/></StgValue>
</operation>

<operation id="1603" st_id="363" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="589" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:42 %add_ln8_99 = add i11 %zext_ln8_99, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_99"/></StgValue>
</operation>

<operation id="1604" st_id="363" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="590" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:43 %zext_ln8_106 = zext i11 %add_ln8_99

]]></Node>
<StgValue><ssdm name="zext_ln8_106"/></StgValue>
</operation>

<operation id="1605" st_id="363" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="591" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:44 %arr_addr_99 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_106

]]></Node>
<StgValue><ssdm name="arr_addr_99"/></StgValue>
</operation>

<operation id="1606" st_id="363" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="592" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:45 %arr_load_99 = load i11 %arr_addr_99

]]></Node>
<StgValue><ssdm name="arr_load_99"/></StgValue>
</operation>

<operation id="1607" st_id="363" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="595" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:48 %add_ln8_100 = add i11 %j_6_cast, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_100"/></StgValue>
</operation>

<operation id="1608" st_id="363" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="596" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:49 %zext_ln8_107 = zext i11 %add_ln8_100

]]></Node>
<StgValue><ssdm name="zext_ln8_107"/></StgValue>
</operation>

<operation id="1609" st_id="363" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="597" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:50 %arr_addr_100 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_107

]]></Node>
<StgValue><ssdm name="arr_addr_100"/></StgValue>
</operation>

<operation id="1610" st_id="363" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="598" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:51 %arr_load_100 = load i11 %arr_addr_100

]]></Node>
<StgValue><ssdm name="arr_load_100"/></StgValue>
</operation>
</state>

<state id="364" st_id="364">

<operation id="1611" st_id="364" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="547" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.6:0 %add_ln47_6 = add i6 %j_6, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_6"/></StgValue>
</operation>

<operation id="1612" st_id="364" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="557" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:10 %mul9_6 = fmul i32 %arr_load_93, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_6"/></StgValue>
</operation>

<operation id="1613" st_id="364" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="563" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:16 %mul9_6_0_1 = fmul i32 %arr_load_94, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_6_0_1"/></StgValue>
</operation>

<operation id="1614" st_id="364" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="569" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:22 %mul9_6_0_2 = fmul i32 %arr_load_95, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_6_0_2"/></StgValue>
</operation>

<operation id="1615" st_id="364" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:28 %mul9_6_1 = fmul i32 %arr_load_96, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_6_1"/></StgValue>
</operation>

<operation id="1616" st_id="364" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="581" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:34 %mul9_6_1_1 = fmul i32 %arr_load_97, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_6_1_1"/></StgValue>
</operation>

<operation id="1617" st_id="364" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="587" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:40 %mul9_6_1_2 = fmul i32 %arr_load_98, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_6_1_2"/></StgValue>
</operation>

<operation id="1618" st_id="364" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="592" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:45 %arr_load_99 = load i11 %arr_addr_99

]]></Node>
<StgValue><ssdm name="arr_load_99"/></StgValue>
</operation>

<operation id="1619" st_id="364" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:46 %mul9_6_2 = fmul i32 %arr_load_99, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_6_2"/></StgValue>
</operation>

<operation id="1620" st_id="364" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="598" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:51 %arr_load_100 = load i11 %arr_addr_100

]]></Node>
<StgValue><ssdm name="arr_load_100"/></StgValue>
</operation>

<operation id="1621" st_id="364" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="599" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:52 %mul9_6_2_1 = fmul i32 %arr_load_100, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_6_2_1"/></StgValue>
</operation>

<operation id="1622" st_id="364" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="601" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:54 %add_ln8_101 = add i11 %add_ln8_99, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_101"/></StgValue>
</operation>

<operation id="1623" st_id="364" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="602" bw="64" op_0_bw="11">
<![CDATA[
.split4.6:55 %zext_ln8_108 = zext i11 %add_ln8_101

]]></Node>
<StgValue><ssdm name="zext_ln8_108"/></StgValue>
</operation>

<operation id="1624" st_id="364" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="603" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:56 %arr_addr_101 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_108

]]></Node>
<StgValue><ssdm name="arr_addr_101"/></StgValue>
</operation>

<operation id="1625" st_id="364" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="604" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:57 %arr_load_101 = load i11 %arr_addr_101

]]></Node>
<StgValue><ssdm name="arr_load_101"/></StgValue>
</operation>
</state>

<state id="365" st_id="365">

<operation id="1626" st_id="365" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="558" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:11 %sum_2_6 = fadd i32 %mul9_6, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_6"/></StgValue>
</operation>

<operation id="1627" st_id="365" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="569" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:22 %mul9_6_0_2 = fmul i32 %arr_load_95, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_6_0_2"/></StgValue>
</operation>

<operation id="1628" st_id="365" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:28 %mul9_6_1 = fmul i32 %arr_load_96, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_6_1"/></StgValue>
</operation>

<operation id="1629" st_id="365" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="581" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:34 %mul9_6_1_1 = fmul i32 %arr_load_97, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_6_1_1"/></StgValue>
</operation>

<operation id="1630" st_id="365" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="587" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:40 %mul9_6_1_2 = fmul i32 %arr_load_98, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_6_1_2"/></StgValue>
</operation>

<operation id="1631" st_id="365" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:46 %mul9_6_2 = fmul i32 %arr_load_99, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_6_2"/></StgValue>
</operation>

<operation id="1632" st_id="365" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="599" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:52 %mul9_6_2_1 = fmul i32 %arr_load_100, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_6_2_1"/></StgValue>
</operation>

<operation id="1633" st_id="365" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="604" bw="32" op_0_bw="11">
<![CDATA[
.split4.6:57 %arr_load_101 = load i11 %arr_addr_101

]]></Node>
<StgValue><ssdm name="arr_load_101"/></StgValue>
</operation>

<operation id="1634" st_id="365" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="605" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:58 %mul9_6_2_2 = fmul i32 %arr_load_101, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_6_2_2"/></StgValue>
</operation>
</state>

<state id="366" st_id="366">

<operation id="1635" st_id="366" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="558" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:11 %sum_2_6 = fadd i32 %mul9_6, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_6"/></StgValue>
</operation>

<operation id="1636" st_id="366" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="581" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:34 %mul9_6_1_1 = fmul i32 %arr_load_97, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_6_1_1"/></StgValue>
</operation>

<operation id="1637" st_id="366" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="587" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:40 %mul9_6_1_2 = fmul i32 %arr_load_98, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_6_1_2"/></StgValue>
</operation>

<operation id="1638" st_id="366" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:46 %mul9_6_2 = fmul i32 %arr_load_99, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_6_2"/></StgValue>
</operation>

<operation id="1639" st_id="366" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="599" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:52 %mul9_6_2_1 = fmul i32 %arr_load_100, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_6_2_1"/></StgValue>
</operation>

<operation id="1640" st_id="366" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="605" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:58 %mul9_6_2_2 = fmul i32 %arr_load_101, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_6_2_2"/></StgValue>
</operation>
</state>

<state id="367" st_id="367">

<operation id="1641" st_id="367" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="558" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:11 %sum_2_6 = fadd i32 %mul9_6, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_6"/></StgValue>
</operation>

<operation id="1642" st_id="367" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:46 %mul9_6_2 = fmul i32 %arr_load_99, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_6_2"/></StgValue>
</operation>

<operation id="1643" st_id="367" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="599" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:52 %mul9_6_2_1 = fmul i32 %arr_load_100, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_6_2_1"/></StgValue>
</operation>

<operation id="1644" st_id="367" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="605" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:58 %mul9_6_2_2 = fmul i32 %arr_load_101, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_6_2_2"/></StgValue>
</operation>
</state>

<state id="368" st_id="368">

<operation id="1645" st_id="368" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="558" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:11 %sum_2_6 = fadd i32 %mul9_6, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_6"/></StgValue>
</operation>

<operation id="1646" st_id="368" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="605" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:58 %mul9_6_2_2 = fmul i32 %arr_load_101, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_6_2_2"/></StgValue>
</operation>
</state>

<state id="369" st_id="369">

<operation id="1647" st_id="369" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="558" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:11 %sum_2_6 = fadd i32 %mul9_6, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_6"/></StgValue>
</operation>
</state>

<state id="370" st_id="370">

<operation id="1648" st_id="370" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:17 %sum_2_6_0_1 = fadd i32 %sum_2_6, i32 %mul9_6_0_1

]]></Node>
<StgValue><ssdm name="sum_2_6_0_1"/></StgValue>
</operation>
</state>

<state id="371" st_id="371">

<operation id="1649" st_id="371" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:17 %sum_2_6_0_1 = fadd i32 %sum_2_6, i32 %mul9_6_0_1

]]></Node>
<StgValue><ssdm name="sum_2_6_0_1"/></StgValue>
</operation>
</state>

<state id="372" st_id="372">

<operation id="1650" st_id="372" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:17 %sum_2_6_0_1 = fadd i32 %sum_2_6, i32 %mul9_6_0_1

]]></Node>
<StgValue><ssdm name="sum_2_6_0_1"/></StgValue>
</operation>
</state>

<state id="373" st_id="373">

<operation id="1651" st_id="373" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:17 %sum_2_6_0_1 = fadd i32 %sum_2_6, i32 %mul9_6_0_1

]]></Node>
<StgValue><ssdm name="sum_2_6_0_1"/></StgValue>
</operation>
</state>

<state id="374" st_id="374">

<operation id="1652" st_id="374" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:17 %sum_2_6_0_1 = fadd i32 %sum_2_6, i32 %mul9_6_0_1

]]></Node>
<StgValue><ssdm name="sum_2_6_0_1"/></StgValue>
</operation>
</state>

<state id="375" st_id="375">
</state>

<state id="376" st_id="376">

<operation id="1653" st_id="376" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:23 %sum_2_6_0_2 = fadd i32 %sum_2_6_0_1, i32 %mul9_6_0_2

]]></Node>
<StgValue><ssdm name="sum_2_6_0_2"/></StgValue>
</operation>
</state>

<state id="377" st_id="377">

<operation id="1654" st_id="377" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:23 %sum_2_6_0_2 = fadd i32 %sum_2_6_0_1, i32 %mul9_6_0_2

]]></Node>
<StgValue><ssdm name="sum_2_6_0_2"/></StgValue>
</operation>
</state>

<state id="378" st_id="378">

<operation id="1655" st_id="378" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:23 %sum_2_6_0_2 = fadd i32 %sum_2_6_0_1, i32 %mul9_6_0_2

]]></Node>
<StgValue><ssdm name="sum_2_6_0_2"/></StgValue>
</operation>
</state>

<state id="379" st_id="379">

<operation id="1656" st_id="379" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:23 %sum_2_6_0_2 = fadd i32 %sum_2_6_0_1, i32 %mul9_6_0_2

]]></Node>
<StgValue><ssdm name="sum_2_6_0_2"/></StgValue>
</operation>
</state>

<state id="380" st_id="380">

<operation id="1657" st_id="380" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:23 %sum_2_6_0_2 = fadd i32 %sum_2_6_0_1, i32 %mul9_6_0_2

]]></Node>
<StgValue><ssdm name="sum_2_6_0_2"/></StgValue>
</operation>
</state>

<state id="381" st_id="381">

<operation id="1658" st_id="381" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:29 %sum_2_6_1 = fadd i32 %sum_2_6_0_2, i32 %mul9_6_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1"/></StgValue>
</operation>
</state>

<state id="382" st_id="382">

<operation id="1659" st_id="382" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:29 %sum_2_6_1 = fadd i32 %sum_2_6_0_2, i32 %mul9_6_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1"/></StgValue>
</operation>
</state>

<state id="383" st_id="383">

<operation id="1660" st_id="383" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:29 %sum_2_6_1 = fadd i32 %sum_2_6_0_2, i32 %mul9_6_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1"/></StgValue>
</operation>
</state>

<state id="384" st_id="384">

<operation id="1661" st_id="384" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:29 %sum_2_6_1 = fadd i32 %sum_2_6_0_2, i32 %mul9_6_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1"/></StgValue>
</operation>
</state>

<state id="385" st_id="385">

<operation id="1662" st_id="385" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:29 %sum_2_6_1 = fadd i32 %sum_2_6_0_2, i32 %mul9_6_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1"/></StgValue>
</operation>
</state>

<state id="386" st_id="386">
</state>

<state id="387" st_id="387">

<operation id="1663" st_id="387" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:35 %sum_2_6_1_1 = fadd i32 %sum_2_6_1, i32 %mul9_6_1_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1_1"/></StgValue>
</operation>
</state>

<state id="388" st_id="388">

<operation id="1664" st_id="388" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:35 %sum_2_6_1_1 = fadd i32 %sum_2_6_1, i32 %mul9_6_1_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1_1"/></StgValue>
</operation>
</state>

<state id="389" st_id="389">

<operation id="1665" st_id="389" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:35 %sum_2_6_1_1 = fadd i32 %sum_2_6_1, i32 %mul9_6_1_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1_1"/></StgValue>
</operation>
</state>

<state id="390" st_id="390">

<operation id="1666" st_id="390" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:35 %sum_2_6_1_1 = fadd i32 %sum_2_6_1, i32 %mul9_6_1_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1_1"/></StgValue>
</operation>
</state>

<state id="391" st_id="391">

<operation id="1667" st_id="391" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:35 %sum_2_6_1_1 = fadd i32 %sum_2_6_1, i32 %mul9_6_1_1

]]></Node>
<StgValue><ssdm name="sum_2_6_1_1"/></StgValue>
</operation>
</state>

<state id="392" st_id="392">

<operation id="1668" st_id="392" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:41 %sum_2_6_1_2 = fadd i32 %sum_2_6_1_1, i32 %mul9_6_1_2

]]></Node>
<StgValue><ssdm name="sum_2_6_1_2"/></StgValue>
</operation>
</state>

<state id="393" st_id="393">

<operation id="1669" st_id="393" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:41 %sum_2_6_1_2 = fadd i32 %sum_2_6_1_1, i32 %mul9_6_1_2

]]></Node>
<StgValue><ssdm name="sum_2_6_1_2"/></StgValue>
</operation>
</state>

<state id="394" st_id="394">

<operation id="1670" st_id="394" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:41 %sum_2_6_1_2 = fadd i32 %sum_2_6_1_1, i32 %mul9_6_1_2

]]></Node>
<StgValue><ssdm name="sum_2_6_1_2"/></StgValue>
</operation>
</state>

<state id="395" st_id="395">

<operation id="1671" st_id="395" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:41 %sum_2_6_1_2 = fadd i32 %sum_2_6_1_1, i32 %mul9_6_1_2

]]></Node>
<StgValue><ssdm name="sum_2_6_1_2"/></StgValue>
</operation>
</state>

<state id="396" st_id="396">

<operation id="1672" st_id="396" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:41 %sum_2_6_1_2 = fadd i32 %sum_2_6_1_1, i32 %mul9_6_1_2

]]></Node>
<StgValue><ssdm name="sum_2_6_1_2"/></StgValue>
</operation>
</state>

<state id="397" st_id="397">
</state>

<state id="398" st_id="398">

<operation id="1673" st_id="398" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:47 %sum_2_6_2 = fadd i32 %sum_2_6_1_2, i32 %mul9_6_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2"/></StgValue>
</operation>
</state>

<state id="399" st_id="399">

<operation id="1674" st_id="399" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:47 %sum_2_6_2 = fadd i32 %sum_2_6_1_2, i32 %mul9_6_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2"/></StgValue>
</operation>
</state>

<state id="400" st_id="400">

<operation id="1675" st_id="400" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:47 %sum_2_6_2 = fadd i32 %sum_2_6_1_2, i32 %mul9_6_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2"/></StgValue>
</operation>
</state>

<state id="401" st_id="401">

<operation id="1676" st_id="401" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:47 %sum_2_6_2 = fadd i32 %sum_2_6_1_2, i32 %mul9_6_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2"/></StgValue>
</operation>
</state>

<state id="402" st_id="402">

<operation id="1677" st_id="402" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:47 %sum_2_6_2 = fadd i32 %sum_2_6_1_2, i32 %mul9_6_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2"/></StgValue>
</operation>
</state>

<state id="403" st_id="403">

<operation id="1678" st_id="403" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:53 %sum_2_6_2_1 = fadd i32 %sum_2_6_2, i32 %mul9_6_2_1

]]></Node>
<StgValue><ssdm name="sum_2_6_2_1"/></StgValue>
</operation>
</state>

<state id="404" st_id="404">

<operation id="1679" st_id="404" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:53 %sum_2_6_2_1 = fadd i32 %sum_2_6_2, i32 %mul9_6_2_1

]]></Node>
<StgValue><ssdm name="sum_2_6_2_1"/></StgValue>
</operation>
</state>

<state id="405" st_id="405">

<operation id="1680" st_id="405" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:53 %sum_2_6_2_1 = fadd i32 %sum_2_6_2, i32 %mul9_6_2_1

]]></Node>
<StgValue><ssdm name="sum_2_6_2_1"/></StgValue>
</operation>
</state>

<state id="406" st_id="406">

<operation id="1681" st_id="406" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:53 %sum_2_6_2_1 = fadd i32 %sum_2_6_2, i32 %mul9_6_2_1

]]></Node>
<StgValue><ssdm name="sum_2_6_2_1"/></StgValue>
</operation>
</state>

<state id="407" st_id="407">

<operation id="1682" st_id="407" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:53 %sum_2_6_2_1 = fadd i32 %sum_2_6_2, i32 %mul9_6_2_1

]]></Node>
<StgValue><ssdm name="sum_2_6_2_1"/></StgValue>
</operation>
</state>

<state id="408" st_id="408">
</state>

<state id="409" st_id="409">

<operation id="1683" st_id="409" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:59 %sum_2_6_2_2 = fadd i32 %sum_2_6_2_1, i32 %mul9_6_2_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2_2"/></StgValue>
</operation>
</state>

<state id="410" st_id="410">

<operation id="1684" st_id="410" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:59 %sum_2_6_2_2 = fadd i32 %sum_2_6_2_1, i32 %mul9_6_2_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2_2"/></StgValue>
</operation>
</state>

<state id="411" st_id="411">

<operation id="1685" st_id="411" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:59 %sum_2_6_2_2 = fadd i32 %sum_2_6_2_1, i32 %mul9_6_2_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2_2"/></StgValue>
</operation>
</state>

<state id="412" st_id="412">

<operation id="1686" st_id="412" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:59 %sum_2_6_2_2 = fadd i32 %sum_2_6_2_1, i32 %mul9_6_2_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2_2"/></StgValue>
</operation>
</state>

<state id="413" st_id="413">

<operation id="1687" st_id="413" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.6:59 %sum_2_6_2_2 = fadd i32 %sum_2_6_2_1, i32 %mul9_6_2_2

]]></Node>
<StgValue><ssdm name="sum_2_6_2_2"/></StgValue>
</operation>
</state>

<state id="414" st_id="414">

<operation id="1688" st_id="414" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="548" bw="64" op_0_bw="33">
<![CDATA[
.split4.6:1 %t_3_6_cast = zext i33 %t_3_6

]]></Node>
<StgValue><ssdm name="t_3_6_cast"/></StgValue>
</operation>

<operation id="1689" st_id="414" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="550" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.6:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1690" st_id="414" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="607" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.6:60 %add_ln58_6 = add i33 %t_3_6, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_6"/></StgValue>
</operation>

<operation id="1691" st_id="414" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="608" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.6:61 %out_addr_15 = getelementptr i32 %out_r, i64 0, i64 %t_3_6_cast

]]></Node>
<StgValue><ssdm name="out_addr_15"/></StgValue>
</operation>

<operation id="1692" st_id="414" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="609" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.6:62 %store_ln58 = store i32 %sum_2_6_2_2, i11 %out_addr_15

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1693" st_id="414" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="610" bw="0" op_0_bw="0">
<![CDATA[
.split4.6:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="415" st_id="415">

<operation id="1694" st_id="415" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="612" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.6:0 %add_ln44_14 = add i32 %zext_ln44_2, i32 %add_ln44_12

]]></Node>
<StgValue><ssdm name="add_ln44_14"/></StgValue>
</operation>

<operation id="1695" st_id="415" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="613" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.6:1 %add_ln44_15 = add i64 %i_0, i64 7

]]></Node>
<StgValue><ssdm name="add_ln44_15"/></StgValue>
</operation>

<operation id="1696" st_id="415" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="614" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.6:2 %icmp_ln44_7 = icmp_slt  i64 %add_ln44_15, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_7"/></StgValue>
</operation>

<operation id="1697" st_id="415" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="615" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.6:3 %br_ln44 = br i1 %icmp_ln44_7, void %._crit_edge13.loopexit, void %.lr.ph.7

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1698" st_id="415" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="618" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.7:1 %empty_131 = add i11 %trunc_ln44, i11 8

]]></Node>
<StgValue><ssdm name="empty_131"/></StgValue>
</operation>

<operation id="1699" st_id="415" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="619" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.7:2 %empty_132 = mul i11 %empty_131, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_132"/></StgValue>
</operation>
</state>

<state id="416" st_id="416">

<operation id="1700" st_id="416" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="619" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.7:2 %empty_132 = mul i11 %empty_131, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_132"/></StgValue>
</operation>
</state>

<state id="417" st_id="417">

<operation id="1701" st_id="417" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="619" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.7:2 %empty_132 = mul i11 %empty_131, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_132"/></StgValue>
</operation>
</state>

<state id="418" st_id="418">

<operation id="1702" st_id="418" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="617" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.7:0 %add_ln44_20_cast = sext i32 %add_ln44_14

]]></Node>
<StgValue><ssdm name="add_ln44_20_cast"/></StgValue>
</operation>

<operation id="1703" st_id="418" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="619" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.7:2 %empty_132 = mul i11 %empty_131, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_132"/></StgValue>
</operation>

<operation id="1704" st_id="418" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="620" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.7:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="419" st_id="419">

<operation id="1705" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="622" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_7 = phi i33 %add_ln58_7, void %.split4.7, i33 %add_ln44_20_cast, void %.lr.ph.7

]]></Node>
<StgValue><ssdm name="t_3_7"/></StgValue>
</operation>

<operation id="1706" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="623" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_7 = phi i6 %add_ln47_7, void %.split4.7, i6 1, void %.lr.ph.7

]]></Node>
<StgValue><ssdm name="j_7"/></StgValue>
</operation>

<operation id="1707" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="624" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1708" st_id="419" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="625" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_7 = icmp_eq  i6 %j_7, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_7"/></StgValue>
</operation>

<operation id="1709" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="626" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_130 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_130"/></StgValue>
</operation>

<operation id="1710" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="627" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_7, void %.split4.7, void %._crit_edge.loopexit.7

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1711" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="631" bw="11" op_0_bw="6">
<![CDATA[
.split4.7:2 %j_7_cast = zext i6 %j_7

]]></Node>
<StgValue><ssdm name="j_7_cast"/></StgValue>
</operation>

<operation id="1712" st_id="419" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="633" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.7:4 %empty_133 = add i6 %j_7, i6 63

]]></Node>
<StgValue><ssdm name="empty_133"/></StgValue>
</operation>

<operation id="1713" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="634" bw="11" op_0_bw="6">
<![CDATA[
.split4.7:5 %zext_ln8_109 = zext i6 %empty_133

]]></Node>
<StgValue><ssdm name="zext_ln8_109"/></StgValue>
</operation>

<operation id="1714" st_id="419" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="635" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:6 %add_ln8_102 = add i11 %zext_ln8_109, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_102"/></StgValue>
</operation>

<operation id="1715" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="636" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:7 %zext_ln8_110 = zext i11 %add_ln8_102

]]></Node>
<StgValue><ssdm name="zext_ln8_110"/></StgValue>
</operation>

<operation id="1716" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="637" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:8 %arr_addr_102 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_110

]]></Node>
<StgValue><ssdm name="arr_addr_102"/></StgValue>
</operation>

<operation id="1717" st_id="419" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="638" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:9 %arr_load_102 = load i11 %arr_addr_102

]]></Node>
<StgValue><ssdm name="arr_load_102"/></StgValue>
</operation>

<operation id="1718" st_id="419" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="641" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:12 %add_ln8_103 = add i11 %j_7_cast, i11 %empty_124

]]></Node>
<StgValue><ssdm name="add_ln8_103"/></StgValue>
</operation>

<operation id="1719" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="642" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:13 %zext_ln8_111 = zext i11 %add_ln8_103

]]></Node>
<StgValue><ssdm name="zext_ln8_111"/></StgValue>
</operation>

<operation id="1720" st_id="419" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="643" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:14 %arr_addr_103 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_111

]]></Node>
<StgValue><ssdm name="arr_addr_103"/></StgValue>
</operation>

<operation id="1721" st_id="419" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="644" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:15 %arr_load_103 = load i11 %arr_addr_103

]]></Node>
<StgValue><ssdm name="arr_load_103"/></StgValue>
</operation>
</state>

<state id="420" st_id="420">

<operation id="1722" st_id="420" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="638" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:9 %arr_load_102 = load i11 %arr_addr_102

]]></Node>
<StgValue><ssdm name="arr_load_102"/></StgValue>
</operation>

<operation id="1723" st_id="420" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="639" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:10 %mul9_7 = fmul i32 %arr_load_102, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_7"/></StgValue>
</operation>

<operation id="1724" st_id="420" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="644" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:15 %arr_load_103 = load i11 %arr_addr_103

]]></Node>
<StgValue><ssdm name="arr_load_103"/></StgValue>
</operation>

<operation id="1725" st_id="420" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="645" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:16 %mul9_7_0_1 = fmul i32 %arr_load_103, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_7_0_1"/></StgValue>
</operation>

<operation id="1726" st_id="420" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="647" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:18 %add_ln8_104 = add i11 %add_ln8_102, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_104"/></StgValue>
</operation>

<operation id="1727" st_id="420" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="648" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:19 %zext_ln8_112 = zext i11 %add_ln8_104

]]></Node>
<StgValue><ssdm name="zext_ln8_112"/></StgValue>
</operation>

<operation id="1728" st_id="420" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="649" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:20 %arr_addr_104 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_112

]]></Node>
<StgValue><ssdm name="arr_addr_104"/></StgValue>
</operation>

<operation id="1729" st_id="420" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="650" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:21 %arr_load_104 = load i11 %arr_addr_104

]]></Node>
<StgValue><ssdm name="arr_load_104"/></StgValue>
</operation>

<operation id="1730" st_id="420" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="653" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:24 %add_ln8_105 = add i11 %zext_ln8_109, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_105"/></StgValue>
</operation>

<operation id="1731" st_id="420" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="654" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:25 %zext_ln8_113 = zext i11 %add_ln8_105

]]></Node>
<StgValue><ssdm name="zext_ln8_113"/></StgValue>
</operation>

<operation id="1732" st_id="420" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="655" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:26 %arr_addr_105 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_113

]]></Node>
<StgValue><ssdm name="arr_addr_105"/></StgValue>
</operation>

<operation id="1733" st_id="420" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="656" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:27 %arr_load_105 = load i11 %arr_addr_105

]]></Node>
<StgValue><ssdm name="arr_load_105"/></StgValue>
</operation>
</state>

<state id="421" st_id="421">

<operation id="1734" st_id="421" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="639" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:10 %mul9_7 = fmul i32 %arr_load_102, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_7"/></StgValue>
</operation>

<operation id="1735" st_id="421" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="645" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:16 %mul9_7_0_1 = fmul i32 %arr_load_103, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_7_0_1"/></StgValue>
</operation>

<operation id="1736" st_id="421" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="650" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:21 %arr_load_104 = load i11 %arr_addr_104

]]></Node>
<StgValue><ssdm name="arr_load_104"/></StgValue>
</operation>

<operation id="1737" st_id="421" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="651" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:22 %mul9_7_0_2 = fmul i32 %arr_load_104, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_7_0_2"/></StgValue>
</operation>

<operation id="1738" st_id="421" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="656" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:27 %arr_load_105 = load i11 %arr_addr_105

]]></Node>
<StgValue><ssdm name="arr_load_105"/></StgValue>
</operation>

<operation id="1739" st_id="421" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="657" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:28 %mul9_7_1 = fmul i32 %arr_load_105, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_7_1"/></StgValue>
</operation>

<operation id="1740" st_id="421" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="659" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:30 %add_ln8_106 = add i11 %j_7_cast, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_106"/></StgValue>
</operation>

<operation id="1741" st_id="421" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="660" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:31 %zext_ln8_114 = zext i11 %add_ln8_106

]]></Node>
<StgValue><ssdm name="zext_ln8_114"/></StgValue>
</operation>

<operation id="1742" st_id="421" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="661" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:32 %arr_addr_106 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_114

]]></Node>
<StgValue><ssdm name="arr_addr_106"/></StgValue>
</operation>

<operation id="1743" st_id="421" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="662" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:33 %arr_load_106 = load i11 %arr_addr_106

]]></Node>
<StgValue><ssdm name="arr_load_106"/></StgValue>
</operation>

<operation id="1744" st_id="421" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="665" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:36 %add_ln8_107 = add i11 %add_ln8_105, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_107"/></StgValue>
</operation>

<operation id="1745" st_id="421" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="666" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:37 %zext_ln8_115 = zext i11 %add_ln8_107

]]></Node>
<StgValue><ssdm name="zext_ln8_115"/></StgValue>
</operation>

<operation id="1746" st_id="421" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="667" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:38 %arr_addr_107 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_115

]]></Node>
<StgValue><ssdm name="arr_addr_107"/></StgValue>
</operation>

<operation id="1747" st_id="421" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="668" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:39 %arr_load_107 = load i11 %arr_addr_107

]]></Node>
<StgValue><ssdm name="arr_load_107"/></StgValue>
</operation>
</state>

<state id="422" st_id="422">

<operation id="1748" st_id="422" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="639" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:10 %mul9_7 = fmul i32 %arr_load_102, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_7"/></StgValue>
</operation>

<operation id="1749" st_id="422" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="645" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:16 %mul9_7_0_1 = fmul i32 %arr_load_103, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_7_0_1"/></StgValue>
</operation>

<operation id="1750" st_id="422" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="651" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:22 %mul9_7_0_2 = fmul i32 %arr_load_104, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_7_0_2"/></StgValue>
</operation>

<operation id="1751" st_id="422" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="657" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:28 %mul9_7_1 = fmul i32 %arr_load_105, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_7_1"/></StgValue>
</operation>

<operation id="1752" st_id="422" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="662" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:33 %arr_load_106 = load i11 %arr_addr_106

]]></Node>
<StgValue><ssdm name="arr_load_106"/></StgValue>
</operation>

<operation id="1753" st_id="422" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="663" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:34 %mul9_7_1_1 = fmul i32 %arr_load_106, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_7_1_1"/></StgValue>
</operation>

<operation id="1754" st_id="422" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="668" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:39 %arr_load_107 = load i11 %arr_addr_107

]]></Node>
<StgValue><ssdm name="arr_load_107"/></StgValue>
</operation>

<operation id="1755" st_id="422" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="669" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:40 %mul9_7_1_2 = fmul i32 %arr_load_107, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_7_1_2"/></StgValue>
</operation>

<operation id="1756" st_id="422" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="671" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:42 %add_ln8_108 = add i11 %zext_ln8_109, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_108"/></StgValue>
</operation>

<operation id="1757" st_id="422" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="672" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:43 %zext_ln8_116 = zext i11 %add_ln8_108

]]></Node>
<StgValue><ssdm name="zext_ln8_116"/></StgValue>
</operation>

<operation id="1758" st_id="422" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="673" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:44 %arr_addr_108 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_116

]]></Node>
<StgValue><ssdm name="arr_addr_108"/></StgValue>
</operation>

<operation id="1759" st_id="422" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="674" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:45 %arr_load_108 = load i11 %arr_addr_108

]]></Node>
<StgValue><ssdm name="arr_load_108"/></StgValue>
</operation>

<operation id="1760" st_id="422" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="677" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:48 %add_ln8_109 = add i11 %j_7_cast, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_109"/></StgValue>
</operation>

<operation id="1761" st_id="422" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="678" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:49 %zext_ln8_117 = zext i11 %add_ln8_109

]]></Node>
<StgValue><ssdm name="zext_ln8_117"/></StgValue>
</operation>

<operation id="1762" st_id="422" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="679" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:50 %arr_addr_109 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_117

]]></Node>
<StgValue><ssdm name="arr_addr_109"/></StgValue>
</operation>

<operation id="1763" st_id="422" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="680" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:51 %arr_load_109 = load i11 %arr_addr_109

]]></Node>
<StgValue><ssdm name="arr_load_109"/></StgValue>
</operation>
</state>

<state id="423" st_id="423">

<operation id="1764" st_id="423" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="629" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.7:0 %add_ln47_7 = add i6 %j_7, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_7"/></StgValue>
</operation>

<operation id="1765" st_id="423" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="639" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:10 %mul9_7 = fmul i32 %arr_load_102, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_7"/></StgValue>
</operation>

<operation id="1766" st_id="423" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="645" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:16 %mul9_7_0_1 = fmul i32 %arr_load_103, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_7_0_1"/></StgValue>
</operation>

<operation id="1767" st_id="423" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="651" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:22 %mul9_7_0_2 = fmul i32 %arr_load_104, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_7_0_2"/></StgValue>
</operation>

<operation id="1768" st_id="423" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="657" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:28 %mul9_7_1 = fmul i32 %arr_load_105, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_7_1"/></StgValue>
</operation>

<operation id="1769" st_id="423" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="663" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:34 %mul9_7_1_1 = fmul i32 %arr_load_106, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_7_1_1"/></StgValue>
</operation>

<operation id="1770" st_id="423" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="669" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:40 %mul9_7_1_2 = fmul i32 %arr_load_107, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_7_1_2"/></StgValue>
</operation>

<operation id="1771" st_id="423" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="674" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:45 %arr_load_108 = load i11 %arr_addr_108

]]></Node>
<StgValue><ssdm name="arr_load_108"/></StgValue>
</operation>

<operation id="1772" st_id="423" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="675" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:46 %mul9_7_2 = fmul i32 %arr_load_108, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_7_2"/></StgValue>
</operation>

<operation id="1773" st_id="423" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="680" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:51 %arr_load_109 = load i11 %arr_addr_109

]]></Node>
<StgValue><ssdm name="arr_load_109"/></StgValue>
</operation>

<operation id="1774" st_id="423" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:52 %mul9_7_2_1 = fmul i32 %arr_load_109, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_7_2_1"/></StgValue>
</operation>

<operation id="1775" st_id="423" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="683" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:54 %add_ln8_110 = add i11 %add_ln8_108, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_110"/></StgValue>
</operation>

<operation id="1776" st_id="423" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="684" bw="64" op_0_bw="11">
<![CDATA[
.split4.7:55 %zext_ln8_118 = zext i11 %add_ln8_110

]]></Node>
<StgValue><ssdm name="zext_ln8_118"/></StgValue>
</operation>

<operation id="1777" st_id="423" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="685" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:56 %arr_addr_110 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_118

]]></Node>
<StgValue><ssdm name="arr_addr_110"/></StgValue>
</operation>

<operation id="1778" st_id="423" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="686" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:57 %arr_load_110 = load i11 %arr_addr_110

]]></Node>
<StgValue><ssdm name="arr_load_110"/></StgValue>
</operation>
</state>

<state id="424" st_id="424">

<operation id="1779" st_id="424" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="640" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:11 %sum_2_7 = fadd i32 %mul9_7, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_7"/></StgValue>
</operation>

<operation id="1780" st_id="424" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="651" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:22 %mul9_7_0_2 = fmul i32 %arr_load_104, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_7_0_2"/></StgValue>
</operation>

<operation id="1781" st_id="424" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="657" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:28 %mul9_7_1 = fmul i32 %arr_load_105, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_7_1"/></StgValue>
</operation>

<operation id="1782" st_id="424" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="663" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:34 %mul9_7_1_1 = fmul i32 %arr_load_106, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_7_1_1"/></StgValue>
</operation>

<operation id="1783" st_id="424" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="669" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:40 %mul9_7_1_2 = fmul i32 %arr_load_107, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_7_1_2"/></StgValue>
</operation>

<operation id="1784" st_id="424" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="675" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:46 %mul9_7_2 = fmul i32 %arr_load_108, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_7_2"/></StgValue>
</operation>

<operation id="1785" st_id="424" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:52 %mul9_7_2_1 = fmul i32 %arr_load_109, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_7_2_1"/></StgValue>
</operation>

<operation id="1786" st_id="424" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="686" bw="32" op_0_bw="11">
<![CDATA[
.split4.7:57 %arr_load_110 = load i11 %arr_addr_110

]]></Node>
<StgValue><ssdm name="arr_load_110"/></StgValue>
</operation>

<operation id="1787" st_id="424" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="687" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:58 %mul9_7_2_2 = fmul i32 %arr_load_110, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_7_2_2"/></StgValue>
</operation>
</state>

<state id="425" st_id="425">

<operation id="1788" st_id="425" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="640" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:11 %sum_2_7 = fadd i32 %mul9_7, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_7"/></StgValue>
</operation>

<operation id="1789" st_id="425" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="663" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:34 %mul9_7_1_1 = fmul i32 %arr_load_106, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_7_1_1"/></StgValue>
</operation>

<operation id="1790" st_id="425" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="669" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:40 %mul9_7_1_2 = fmul i32 %arr_load_107, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_7_1_2"/></StgValue>
</operation>

<operation id="1791" st_id="425" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="675" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:46 %mul9_7_2 = fmul i32 %arr_load_108, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_7_2"/></StgValue>
</operation>

<operation id="1792" st_id="425" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:52 %mul9_7_2_1 = fmul i32 %arr_load_109, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_7_2_1"/></StgValue>
</operation>

<operation id="1793" st_id="425" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="687" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:58 %mul9_7_2_2 = fmul i32 %arr_load_110, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_7_2_2"/></StgValue>
</operation>
</state>

<state id="426" st_id="426">

<operation id="1794" st_id="426" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="640" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:11 %sum_2_7 = fadd i32 %mul9_7, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_7"/></StgValue>
</operation>

<operation id="1795" st_id="426" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="675" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:46 %mul9_7_2 = fmul i32 %arr_load_108, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_7_2"/></StgValue>
</operation>

<operation id="1796" st_id="426" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:52 %mul9_7_2_1 = fmul i32 %arr_load_109, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_7_2_1"/></StgValue>
</operation>

<operation id="1797" st_id="426" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="687" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:58 %mul9_7_2_2 = fmul i32 %arr_load_110, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_7_2_2"/></StgValue>
</operation>
</state>

<state id="427" st_id="427">

<operation id="1798" st_id="427" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="640" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:11 %sum_2_7 = fadd i32 %mul9_7, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_7"/></StgValue>
</operation>

<operation id="1799" st_id="427" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="687" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:58 %mul9_7_2_2 = fmul i32 %arr_load_110, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_7_2_2"/></StgValue>
</operation>
</state>

<state id="428" st_id="428">

<operation id="1800" st_id="428" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="640" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:11 %sum_2_7 = fadd i32 %mul9_7, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_7"/></StgValue>
</operation>
</state>

<state id="429" st_id="429">

<operation id="1801" st_id="429" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="646" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:17 %sum_2_7_0_1 = fadd i32 %sum_2_7, i32 %mul9_7_0_1

]]></Node>
<StgValue><ssdm name="sum_2_7_0_1"/></StgValue>
</operation>
</state>

<state id="430" st_id="430">

<operation id="1802" st_id="430" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="646" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:17 %sum_2_7_0_1 = fadd i32 %sum_2_7, i32 %mul9_7_0_1

]]></Node>
<StgValue><ssdm name="sum_2_7_0_1"/></StgValue>
</operation>
</state>

<state id="431" st_id="431">

<operation id="1803" st_id="431" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="646" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:17 %sum_2_7_0_1 = fadd i32 %sum_2_7, i32 %mul9_7_0_1

]]></Node>
<StgValue><ssdm name="sum_2_7_0_1"/></StgValue>
</operation>
</state>

<state id="432" st_id="432">

<operation id="1804" st_id="432" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="646" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:17 %sum_2_7_0_1 = fadd i32 %sum_2_7, i32 %mul9_7_0_1

]]></Node>
<StgValue><ssdm name="sum_2_7_0_1"/></StgValue>
</operation>
</state>

<state id="433" st_id="433">

<operation id="1805" st_id="433" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="646" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:17 %sum_2_7_0_1 = fadd i32 %sum_2_7, i32 %mul9_7_0_1

]]></Node>
<StgValue><ssdm name="sum_2_7_0_1"/></StgValue>
</operation>
</state>

<state id="434" st_id="434">
</state>

<state id="435" st_id="435">

<operation id="1806" st_id="435" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="652" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:23 %sum_2_7_0_2 = fadd i32 %sum_2_7_0_1, i32 %mul9_7_0_2

]]></Node>
<StgValue><ssdm name="sum_2_7_0_2"/></StgValue>
</operation>
</state>

<state id="436" st_id="436">

<operation id="1807" st_id="436" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="652" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:23 %sum_2_7_0_2 = fadd i32 %sum_2_7_0_1, i32 %mul9_7_0_2

]]></Node>
<StgValue><ssdm name="sum_2_7_0_2"/></StgValue>
</operation>
</state>

<state id="437" st_id="437">

<operation id="1808" st_id="437" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="652" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:23 %sum_2_7_0_2 = fadd i32 %sum_2_7_0_1, i32 %mul9_7_0_2

]]></Node>
<StgValue><ssdm name="sum_2_7_0_2"/></StgValue>
</operation>
</state>

<state id="438" st_id="438">

<operation id="1809" st_id="438" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="652" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:23 %sum_2_7_0_2 = fadd i32 %sum_2_7_0_1, i32 %mul9_7_0_2

]]></Node>
<StgValue><ssdm name="sum_2_7_0_2"/></StgValue>
</operation>
</state>

<state id="439" st_id="439">

<operation id="1810" st_id="439" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="652" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:23 %sum_2_7_0_2 = fadd i32 %sum_2_7_0_1, i32 %mul9_7_0_2

]]></Node>
<StgValue><ssdm name="sum_2_7_0_2"/></StgValue>
</operation>
</state>

<state id="440" st_id="440">

<operation id="1811" st_id="440" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:29 %sum_2_7_1 = fadd i32 %sum_2_7_0_2, i32 %mul9_7_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1"/></StgValue>
</operation>
</state>

<state id="441" st_id="441">

<operation id="1812" st_id="441" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:29 %sum_2_7_1 = fadd i32 %sum_2_7_0_2, i32 %mul9_7_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1"/></StgValue>
</operation>
</state>

<state id="442" st_id="442">

<operation id="1813" st_id="442" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:29 %sum_2_7_1 = fadd i32 %sum_2_7_0_2, i32 %mul9_7_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1"/></StgValue>
</operation>
</state>

<state id="443" st_id="443">

<operation id="1814" st_id="443" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:29 %sum_2_7_1 = fadd i32 %sum_2_7_0_2, i32 %mul9_7_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1"/></StgValue>
</operation>
</state>

<state id="444" st_id="444">

<operation id="1815" st_id="444" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:29 %sum_2_7_1 = fadd i32 %sum_2_7_0_2, i32 %mul9_7_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1"/></StgValue>
</operation>
</state>

<state id="445" st_id="445">
</state>

<state id="446" st_id="446">

<operation id="1816" st_id="446" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:35 %sum_2_7_1_1 = fadd i32 %sum_2_7_1, i32 %mul9_7_1_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1_1"/></StgValue>
</operation>
</state>

<state id="447" st_id="447">

<operation id="1817" st_id="447" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:35 %sum_2_7_1_1 = fadd i32 %sum_2_7_1, i32 %mul9_7_1_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1_1"/></StgValue>
</operation>
</state>

<state id="448" st_id="448">

<operation id="1818" st_id="448" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:35 %sum_2_7_1_1 = fadd i32 %sum_2_7_1, i32 %mul9_7_1_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1_1"/></StgValue>
</operation>
</state>

<state id="449" st_id="449">

<operation id="1819" st_id="449" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:35 %sum_2_7_1_1 = fadd i32 %sum_2_7_1, i32 %mul9_7_1_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1_1"/></StgValue>
</operation>
</state>

<state id="450" st_id="450">

<operation id="1820" st_id="450" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:35 %sum_2_7_1_1 = fadd i32 %sum_2_7_1, i32 %mul9_7_1_1

]]></Node>
<StgValue><ssdm name="sum_2_7_1_1"/></StgValue>
</operation>
</state>

<state id="451" st_id="451">

<operation id="1821" st_id="451" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:41 %sum_2_7_1_2 = fadd i32 %sum_2_7_1_1, i32 %mul9_7_1_2

]]></Node>
<StgValue><ssdm name="sum_2_7_1_2"/></StgValue>
</operation>
</state>

<state id="452" st_id="452">

<operation id="1822" st_id="452" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:41 %sum_2_7_1_2 = fadd i32 %sum_2_7_1_1, i32 %mul9_7_1_2

]]></Node>
<StgValue><ssdm name="sum_2_7_1_2"/></StgValue>
</operation>
</state>

<state id="453" st_id="453">

<operation id="1823" st_id="453" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:41 %sum_2_7_1_2 = fadd i32 %sum_2_7_1_1, i32 %mul9_7_1_2

]]></Node>
<StgValue><ssdm name="sum_2_7_1_2"/></StgValue>
</operation>
</state>

<state id="454" st_id="454">

<operation id="1824" st_id="454" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:41 %sum_2_7_1_2 = fadd i32 %sum_2_7_1_1, i32 %mul9_7_1_2

]]></Node>
<StgValue><ssdm name="sum_2_7_1_2"/></StgValue>
</operation>
</state>

<state id="455" st_id="455">

<operation id="1825" st_id="455" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:41 %sum_2_7_1_2 = fadd i32 %sum_2_7_1_1, i32 %mul9_7_1_2

]]></Node>
<StgValue><ssdm name="sum_2_7_1_2"/></StgValue>
</operation>
</state>

<state id="456" st_id="456">
</state>

<state id="457" st_id="457">

<operation id="1826" st_id="457" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:47 %sum_2_7_2 = fadd i32 %sum_2_7_1_2, i32 %mul9_7_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2"/></StgValue>
</operation>
</state>

<state id="458" st_id="458">

<operation id="1827" st_id="458" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:47 %sum_2_7_2 = fadd i32 %sum_2_7_1_2, i32 %mul9_7_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2"/></StgValue>
</operation>
</state>

<state id="459" st_id="459">

<operation id="1828" st_id="459" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:47 %sum_2_7_2 = fadd i32 %sum_2_7_1_2, i32 %mul9_7_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2"/></StgValue>
</operation>
</state>

<state id="460" st_id="460">

<operation id="1829" st_id="460" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:47 %sum_2_7_2 = fadd i32 %sum_2_7_1_2, i32 %mul9_7_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2"/></StgValue>
</operation>
</state>

<state id="461" st_id="461">

<operation id="1830" st_id="461" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:47 %sum_2_7_2 = fadd i32 %sum_2_7_1_2, i32 %mul9_7_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2"/></StgValue>
</operation>
</state>

<state id="462" st_id="462">

<operation id="1831" st_id="462" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:53 %sum_2_7_2_1 = fadd i32 %sum_2_7_2, i32 %mul9_7_2_1

]]></Node>
<StgValue><ssdm name="sum_2_7_2_1"/></StgValue>
</operation>
</state>

<state id="463" st_id="463">

<operation id="1832" st_id="463" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:53 %sum_2_7_2_1 = fadd i32 %sum_2_7_2, i32 %mul9_7_2_1

]]></Node>
<StgValue><ssdm name="sum_2_7_2_1"/></StgValue>
</operation>
</state>

<state id="464" st_id="464">

<operation id="1833" st_id="464" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:53 %sum_2_7_2_1 = fadd i32 %sum_2_7_2, i32 %mul9_7_2_1

]]></Node>
<StgValue><ssdm name="sum_2_7_2_1"/></StgValue>
</operation>
</state>

<state id="465" st_id="465">

<operation id="1834" st_id="465" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:53 %sum_2_7_2_1 = fadd i32 %sum_2_7_2, i32 %mul9_7_2_1

]]></Node>
<StgValue><ssdm name="sum_2_7_2_1"/></StgValue>
</operation>
</state>

<state id="466" st_id="466">

<operation id="1835" st_id="466" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:53 %sum_2_7_2_1 = fadd i32 %sum_2_7_2, i32 %mul9_7_2_1

]]></Node>
<StgValue><ssdm name="sum_2_7_2_1"/></StgValue>
</operation>
</state>

<state id="467" st_id="467">
</state>

<state id="468" st_id="468">

<operation id="1836" st_id="468" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:59 %sum_2_7_2_2 = fadd i32 %sum_2_7_2_1, i32 %mul9_7_2_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2_2"/></StgValue>
</operation>
</state>

<state id="469" st_id="469">

<operation id="1837" st_id="469" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:59 %sum_2_7_2_2 = fadd i32 %sum_2_7_2_1, i32 %mul9_7_2_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2_2"/></StgValue>
</operation>
</state>

<state id="470" st_id="470">

<operation id="1838" st_id="470" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:59 %sum_2_7_2_2 = fadd i32 %sum_2_7_2_1, i32 %mul9_7_2_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2_2"/></StgValue>
</operation>
</state>

<state id="471" st_id="471">

<operation id="1839" st_id="471" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:59 %sum_2_7_2_2 = fadd i32 %sum_2_7_2_1, i32 %mul9_7_2_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2_2"/></StgValue>
</operation>
</state>

<state id="472" st_id="472">

<operation id="1840" st_id="472" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.7:59 %sum_2_7_2_2 = fadd i32 %sum_2_7_2_1, i32 %mul9_7_2_2

]]></Node>
<StgValue><ssdm name="sum_2_7_2_2"/></StgValue>
</operation>
</state>

<state id="473" st_id="473">

<operation id="1841" st_id="473" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="630" bw="64" op_0_bw="33">
<![CDATA[
.split4.7:1 %t_3_7_cast = zext i33 %t_3_7

]]></Node>
<StgValue><ssdm name="t_3_7_cast"/></StgValue>
</operation>

<operation id="1842" st_id="473" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="632" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.7:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1843" st_id="473" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="689" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.7:60 %add_ln58_7 = add i33 %t_3_7, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_7"/></StgValue>
</operation>

<operation id="1844" st_id="473" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="690" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.7:61 %out_addr_16 = getelementptr i32 %out_r, i64 0, i64 %t_3_7_cast

]]></Node>
<StgValue><ssdm name="out_addr_16"/></StgValue>
</operation>

<operation id="1845" st_id="473" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="691" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.7:62 %store_ln58 = store i32 %sum_2_7_2_2, i11 %out_addr_16

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1846" st_id="473" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="692" bw="0" op_0_bw="0">
<![CDATA[
.split4.7:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="474" st_id="474">

<operation id="1847" st_id="474" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="694" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.7:0 %add_ln44_16 = add i32 %zext_ln44_2, i32 %add_ln44_14

]]></Node>
<StgValue><ssdm name="add_ln44_16"/></StgValue>
</operation>

<operation id="1848" st_id="474" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="695" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.7:1 %add_ln44_17 = add i64 %i_0, i64 8

]]></Node>
<StgValue><ssdm name="add_ln44_17"/></StgValue>
</operation>

<operation id="1849" st_id="474" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="696" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.7:2 %icmp_ln44_8 = icmp_slt  i64 %add_ln44_17, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_8"/></StgValue>
</operation>

<operation id="1850" st_id="474" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="697" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.7:3 %br_ln44 = br i1 %icmp_ln44_8, void %._crit_edge13.loopexit, void %.lr.ph.8

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="1851" st_id="474" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_8" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="700" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.8:1 %empty_135 = add i11 %trunc_ln44, i11 9

]]></Node>
<StgValue><ssdm name="empty_135"/></StgValue>
</operation>

<operation id="1852" st_id="474" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_8" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="701" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.8:2 %empty_136 = mul i11 %empty_135, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_136"/></StgValue>
</operation>
</state>

<state id="475" st_id="475">

<operation id="1853" st_id="475" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="701" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.8:2 %empty_136 = mul i11 %empty_135, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_136"/></StgValue>
</operation>
</state>

<state id="476" st_id="476">

<operation id="1854" st_id="476" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="701" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.8:2 %empty_136 = mul i11 %empty_135, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_136"/></StgValue>
</operation>
</state>

<state id="477" st_id="477">

<operation id="1855" st_id="477" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="699" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.8:0 %add_ln44_23_cast = sext i32 %add_ln44_16

]]></Node>
<StgValue><ssdm name="add_ln44_23_cast"/></StgValue>
</operation>

<operation id="1856" st_id="477" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="701" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.8:2 %empty_136 = mul i11 %empty_135, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_136"/></StgValue>
</operation>

<operation id="1857" st_id="477" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="702" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.8:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="478" st_id="478">

<operation id="1858" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="704" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_8 = phi i33 %add_ln58_8, void %.split4.8, i33 %add_ln44_23_cast, void %.lr.ph.8

]]></Node>
<StgValue><ssdm name="t_3_8"/></StgValue>
</operation>

<operation id="1859" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="705" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_8 = phi i6 %add_ln47_8, void %.split4.8, i6 1, void %.lr.ph.8

]]></Node>
<StgValue><ssdm name="j_8"/></StgValue>
</operation>

<operation id="1860" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="706" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1861" st_id="478" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="707" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_8 = icmp_eq  i6 %j_8, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_8"/></StgValue>
</operation>

<operation id="1862" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="708" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_134 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_134"/></StgValue>
</operation>

<operation id="1863" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="709" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_8, void %.split4.8, void %._crit_edge.loopexit.8

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="1864" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="713" bw="11" op_0_bw="6">
<![CDATA[
.split4.8:2 %j_8_cast = zext i6 %j_8

]]></Node>
<StgValue><ssdm name="j_8_cast"/></StgValue>
</operation>

<operation id="1865" st_id="478" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="715" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.8:4 %empty_137 = add i6 %j_8, i6 63

]]></Node>
<StgValue><ssdm name="empty_137"/></StgValue>
</operation>

<operation id="1866" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="716" bw="11" op_0_bw="6">
<![CDATA[
.split4.8:5 %zext_ln8_119 = zext i6 %empty_137

]]></Node>
<StgValue><ssdm name="zext_ln8_119"/></StgValue>
</operation>

<operation id="1867" st_id="478" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="717" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:6 %add_ln8_111 = add i11 %zext_ln8_119, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_111"/></StgValue>
</operation>

<operation id="1868" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="718" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:7 %zext_ln8_120 = zext i11 %add_ln8_111

]]></Node>
<StgValue><ssdm name="zext_ln8_120"/></StgValue>
</operation>

<operation id="1869" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="719" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:8 %arr_addr_111 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_120

]]></Node>
<StgValue><ssdm name="arr_addr_111"/></StgValue>
</operation>

<operation id="1870" st_id="478" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="720" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:9 %arr_load_111 = load i11 %arr_addr_111

]]></Node>
<StgValue><ssdm name="arr_load_111"/></StgValue>
</operation>

<operation id="1871" st_id="478" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="723" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:12 %add_ln8_112 = add i11 %j_8_cast, i11 %empty_128

]]></Node>
<StgValue><ssdm name="add_ln8_112"/></StgValue>
</operation>

<operation id="1872" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="724" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:13 %zext_ln8_121 = zext i11 %add_ln8_112

]]></Node>
<StgValue><ssdm name="zext_ln8_121"/></StgValue>
</operation>

<operation id="1873" st_id="478" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="725" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:14 %arr_addr_112 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_121

]]></Node>
<StgValue><ssdm name="arr_addr_112"/></StgValue>
</operation>

<operation id="1874" st_id="478" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="726" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:15 %arr_load_112 = load i11 %arr_addr_112

]]></Node>
<StgValue><ssdm name="arr_load_112"/></StgValue>
</operation>
</state>

<state id="479" st_id="479">

<operation id="1875" st_id="479" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="720" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:9 %arr_load_111 = load i11 %arr_addr_111

]]></Node>
<StgValue><ssdm name="arr_load_111"/></StgValue>
</operation>

<operation id="1876" st_id="479" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:10 %mul9_8 = fmul i32 %arr_load_111, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_8"/></StgValue>
</operation>

<operation id="1877" st_id="479" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="726" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:15 %arr_load_112 = load i11 %arr_addr_112

]]></Node>
<StgValue><ssdm name="arr_load_112"/></StgValue>
</operation>

<operation id="1878" st_id="479" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="727" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:16 %mul9_8_0_1 = fmul i32 %arr_load_112, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_8_0_1"/></StgValue>
</operation>

<operation id="1879" st_id="479" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="729" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:18 %add_ln8_113 = add i11 %add_ln8_111, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_113"/></StgValue>
</operation>

<operation id="1880" st_id="479" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="730" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:19 %zext_ln8_122 = zext i11 %add_ln8_113

]]></Node>
<StgValue><ssdm name="zext_ln8_122"/></StgValue>
</operation>

<operation id="1881" st_id="479" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="731" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:20 %arr_addr_113 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_122

]]></Node>
<StgValue><ssdm name="arr_addr_113"/></StgValue>
</operation>

<operation id="1882" st_id="479" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="732" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:21 %arr_load_113 = load i11 %arr_addr_113

]]></Node>
<StgValue><ssdm name="arr_load_113"/></StgValue>
</operation>

<operation id="1883" st_id="479" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="735" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:24 %add_ln8_114 = add i11 %zext_ln8_119, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_114"/></StgValue>
</operation>

<operation id="1884" st_id="479" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="736" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:25 %zext_ln8_123 = zext i11 %add_ln8_114

]]></Node>
<StgValue><ssdm name="zext_ln8_123"/></StgValue>
</operation>

<operation id="1885" st_id="479" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="737" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:26 %arr_addr_114 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_123

]]></Node>
<StgValue><ssdm name="arr_addr_114"/></StgValue>
</operation>

<operation id="1886" st_id="479" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="738" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:27 %arr_load_114 = load i11 %arr_addr_114

]]></Node>
<StgValue><ssdm name="arr_load_114"/></StgValue>
</operation>
</state>

<state id="480" st_id="480">

<operation id="1887" st_id="480" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:10 %mul9_8 = fmul i32 %arr_load_111, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_8"/></StgValue>
</operation>

<operation id="1888" st_id="480" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="727" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:16 %mul9_8_0_1 = fmul i32 %arr_load_112, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_8_0_1"/></StgValue>
</operation>

<operation id="1889" st_id="480" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="732" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:21 %arr_load_113 = load i11 %arr_addr_113

]]></Node>
<StgValue><ssdm name="arr_load_113"/></StgValue>
</operation>

<operation id="1890" st_id="480" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="733" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:22 %mul9_8_0_2 = fmul i32 %arr_load_113, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_8_0_2"/></StgValue>
</operation>

<operation id="1891" st_id="480" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="738" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:27 %arr_load_114 = load i11 %arr_addr_114

]]></Node>
<StgValue><ssdm name="arr_load_114"/></StgValue>
</operation>

<operation id="1892" st_id="480" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="739" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:28 %mul9_8_1 = fmul i32 %arr_load_114, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_8_1"/></StgValue>
</operation>

<operation id="1893" st_id="480" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="741" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:30 %add_ln8_115 = add i11 %j_8_cast, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_115"/></StgValue>
</operation>

<operation id="1894" st_id="480" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="742" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:31 %zext_ln8_124 = zext i11 %add_ln8_115

]]></Node>
<StgValue><ssdm name="zext_ln8_124"/></StgValue>
</operation>

<operation id="1895" st_id="480" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="743" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:32 %arr_addr_115 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_124

]]></Node>
<StgValue><ssdm name="arr_addr_115"/></StgValue>
</operation>

<operation id="1896" st_id="480" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="744" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:33 %arr_load_115 = load i11 %arr_addr_115

]]></Node>
<StgValue><ssdm name="arr_load_115"/></StgValue>
</operation>

<operation id="1897" st_id="480" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="747" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:36 %add_ln8_116 = add i11 %add_ln8_114, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_116"/></StgValue>
</operation>

<operation id="1898" st_id="480" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="748" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:37 %zext_ln8_125 = zext i11 %add_ln8_116

]]></Node>
<StgValue><ssdm name="zext_ln8_125"/></StgValue>
</operation>

<operation id="1899" st_id="480" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="749" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:38 %arr_addr_116 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_125

]]></Node>
<StgValue><ssdm name="arr_addr_116"/></StgValue>
</operation>

<operation id="1900" st_id="480" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="750" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:39 %arr_load_116 = load i11 %arr_addr_116

]]></Node>
<StgValue><ssdm name="arr_load_116"/></StgValue>
</operation>
</state>

<state id="481" st_id="481">

<operation id="1901" st_id="481" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:10 %mul9_8 = fmul i32 %arr_load_111, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_8"/></StgValue>
</operation>

<operation id="1902" st_id="481" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="727" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:16 %mul9_8_0_1 = fmul i32 %arr_load_112, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_8_0_1"/></StgValue>
</operation>

<operation id="1903" st_id="481" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="733" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:22 %mul9_8_0_2 = fmul i32 %arr_load_113, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_8_0_2"/></StgValue>
</operation>

<operation id="1904" st_id="481" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="739" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:28 %mul9_8_1 = fmul i32 %arr_load_114, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_8_1"/></StgValue>
</operation>

<operation id="1905" st_id="481" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="744" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:33 %arr_load_115 = load i11 %arr_addr_115

]]></Node>
<StgValue><ssdm name="arr_load_115"/></StgValue>
</operation>

<operation id="1906" st_id="481" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="745" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:34 %mul9_8_1_1 = fmul i32 %arr_load_115, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_8_1_1"/></StgValue>
</operation>

<operation id="1907" st_id="481" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="750" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:39 %arr_load_116 = load i11 %arr_addr_116

]]></Node>
<StgValue><ssdm name="arr_load_116"/></StgValue>
</operation>

<operation id="1908" st_id="481" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="751" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:40 %mul9_8_1_2 = fmul i32 %arr_load_116, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_8_1_2"/></StgValue>
</operation>

<operation id="1909" st_id="481" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="753" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:42 %add_ln8_117 = add i11 %zext_ln8_119, i11 %empty_136

]]></Node>
<StgValue><ssdm name="add_ln8_117"/></StgValue>
</operation>

<operation id="1910" st_id="481" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="754" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:43 %zext_ln8_126 = zext i11 %add_ln8_117

]]></Node>
<StgValue><ssdm name="zext_ln8_126"/></StgValue>
</operation>

<operation id="1911" st_id="481" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="755" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:44 %arr_addr_117 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_126

]]></Node>
<StgValue><ssdm name="arr_addr_117"/></StgValue>
</operation>

<operation id="1912" st_id="481" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="756" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:45 %arr_load_117 = load i11 %arr_addr_117

]]></Node>
<StgValue><ssdm name="arr_load_117"/></StgValue>
</operation>

<operation id="1913" st_id="481" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="759" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:48 %add_ln8_118 = add i11 %j_8_cast, i11 %empty_136

]]></Node>
<StgValue><ssdm name="add_ln8_118"/></StgValue>
</operation>

<operation id="1914" st_id="481" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="760" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:49 %zext_ln8_127 = zext i11 %add_ln8_118

]]></Node>
<StgValue><ssdm name="zext_ln8_127"/></StgValue>
</operation>

<operation id="1915" st_id="481" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="761" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:50 %arr_addr_118 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_127

]]></Node>
<StgValue><ssdm name="arr_addr_118"/></StgValue>
</operation>

<operation id="1916" st_id="481" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="762" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:51 %arr_load_118 = load i11 %arr_addr_118

]]></Node>
<StgValue><ssdm name="arr_load_118"/></StgValue>
</operation>
</state>

<state id="482" st_id="482">

<operation id="1917" st_id="482" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="711" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.8:0 %add_ln47_8 = add i6 %j_8, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_8"/></StgValue>
</operation>

<operation id="1918" st_id="482" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:10 %mul9_8 = fmul i32 %arr_load_111, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_8"/></StgValue>
</operation>

<operation id="1919" st_id="482" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="727" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:16 %mul9_8_0_1 = fmul i32 %arr_load_112, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_8_0_1"/></StgValue>
</operation>

<operation id="1920" st_id="482" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="733" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:22 %mul9_8_0_2 = fmul i32 %arr_load_113, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_8_0_2"/></StgValue>
</operation>

<operation id="1921" st_id="482" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="739" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:28 %mul9_8_1 = fmul i32 %arr_load_114, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_8_1"/></StgValue>
</operation>

<operation id="1922" st_id="482" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="745" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:34 %mul9_8_1_1 = fmul i32 %arr_load_115, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_8_1_1"/></StgValue>
</operation>

<operation id="1923" st_id="482" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="751" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:40 %mul9_8_1_2 = fmul i32 %arr_load_116, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_8_1_2"/></StgValue>
</operation>

<operation id="1924" st_id="482" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="756" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:45 %arr_load_117 = load i11 %arr_addr_117

]]></Node>
<StgValue><ssdm name="arr_load_117"/></StgValue>
</operation>

<operation id="1925" st_id="482" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="757" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:46 %mul9_8_2 = fmul i32 %arr_load_117, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_8_2"/></StgValue>
</operation>

<operation id="1926" st_id="482" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="762" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:51 %arr_load_118 = load i11 %arr_addr_118

]]></Node>
<StgValue><ssdm name="arr_load_118"/></StgValue>
</operation>

<operation id="1927" st_id="482" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="763" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:52 %mul9_8_2_1 = fmul i32 %arr_load_118, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_8_2_1"/></StgValue>
</operation>

<operation id="1928" st_id="482" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="765" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:54 %add_ln8_119 = add i11 %add_ln8_117, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_119"/></StgValue>
</operation>

<operation id="1929" st_id="482" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="766" bw="64" op_0_bw="11">
<![CDATA[
.split4.8:55 %zext_ln8_128 = zext i11 %add_ln8_119

]]></Node>
<StgValue><ssdm name="zext_ln8_128"/></StgValue>
</operation>

<operation id="1930" st_id="482" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="767" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:56 %arr_addr_119 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_128

]]></Node>
<StgValue><ssdm name="arr_addr_119"/></StgValue>
</operation>

<operation id="1931" st_id="482" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="768" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:57 %arr_load_119 = load i11 %arr_addr_119

]]></Node>
<StgValue><ssdm name="arr_load_119"/></StgValue>
</operation>
</state>

<state id="483" st_id="483">

<operation id="1932" st_id="483" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:11 %sum_2_8 = fadd i32 %mul9_8, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_8"/></StgValue>
</operation>

<operation id="1933" st_id="483" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="733" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:22 %mul9_8_0_2 = fmul i32 %arr_load_113, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_8_0_2"/></StgValue>
</operation>

<operation id="1934" st_id="483" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="739" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:28 %mul9_8_1 = fmul i32 %arr_load_114, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_8_1"/></StgValue>
</operation>

<operation id="1935" st_id="483" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="745" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:34 %mul9_8_1_1 = fmul i32 %arr_load_115, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_8_1_1"/></StgValue>
</operation>

<operation id="1936" st_id="483" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="751" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:40 %mul9_8_1_2 = fmul i32 %arr_load_116, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_8_1_2"/></StgValue>
</operation>

<operation id="1937" st_id="483" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="757" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:46 %mul9_8_2 = fmul i32 %arr_load_117, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_8_2"/></StgValue>
</operation>

<operation id="1938" st_id="483" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="763" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:52 %mul9_8_2_1 = fmul i32 %arr_load_118, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_8_2_1"/></StgValue>
</operation>

<operation id="1939" st_id="483" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="768" bw="32" op_0_bw="11">
<![CDATA[
.split4.8:57 %arr_load_119 = load i11 %arr_addr_119

]]></Node>
<StgValue><ssdm name="arr_load_119"/></StgValue>
</operation>

<operation id="1940" st_id="483" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="769" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:58 %mul9_8_2_2 = fmul i32 %arr_load_119, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_8_2_2"/></StgValue>
</operation>
</state>

<state id="484" st_id="484">

<operation id="1941" st_id="484" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:11 %sum_2_8 = fadd i32 %mul9_8, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_8"/></StgValue>
</operation>

<operation id="1942" st_id="484" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="745" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:34 %mul9_8_1_1 = fmul i32 %arr_load_115, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_8_1_1"/></StgValue>
</operation>

<operation id="1943" st_id="484" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="751" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:40 %mul9_8_1_2 = fmul i32 %arr_load_116, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_8_1_2"/></StgValue>
</operation>

<operation id="1944" st_id="484" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="757" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:46 %mul9_8_2 = fmul i32 %arr_load_117, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_8_2"/></StgValue>
</operation>

<operation id="1945" st_id="484" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="763" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:52 %mul9_8_2_1 = fmul i32 %arr_load_118, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_8_2_1"/></StgValue>
</operation>

<operation id="1946" st_id="484" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="769" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:58 %mul9_8_2_2 = fmul i32 %arr_load_119, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_8_2_2"/></StgValue>
</operation>
</state>

<state id="485" st_id="485">

<operation id="1947" st_id="485" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:11 %sum_2_8 = fadd i32 %mul9_8, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_8"/></StgValue>
</operation>

<operation id="1948" st_id="485" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="757" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:46 %mul9_8_2 = fmul i32 %arr_load_117, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_8_2"/></StgValue>
</operation>

<operation id="1949" st_id="485" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="763" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:52 %mul9_8_2_1 = fmul i32 %arr_load_118, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_8_2_1"/></StgValue>
</operation>

<operation id="1950" st_id="485" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="769" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:58 %mul9_8_2_2 = fmul i32 %arr_load_119, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_8_2_2"/></StgValue>
</operation>
</state>

<state id="486" st_id="486">

<operation id="1951" st_id="486" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:11 %sum_2_8 = fadd i32 %mul9_8, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_8"/></StgValue>
</operation>

<operation id="1952" st_id="486" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="769" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:58 %mul9_8_2_2 = fmul i32 %arr_load_119, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_8_2_2"/></StgValue>
</operation>
</state>

<state id="487" st_id="487">

<operation id="1953" st_id="487" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:11 %sum_2_8 = fadd i32 %mul9_8, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_8"/></StgValue>
</operation>
</state>

<state id="488" st_id="488">

<operation id="1954" st_id="488" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:17 %sum_2_8_0_1 = fadd i32 %sum_2_8, i32 %mul9_8_0_1

]]></Node>
<StgValue><ssdm name="sum_2_8_0_1"/></StgValue>
</operation>
</state>

<state id="489" st_id="489">

<operation id="1955" st_id="489" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:17 %sum_2_8_0_1 = fadd i32 %sum_2_8, i32 %mul9_8_0_1

]]></Node>
<StgValue><ssdm name="sum_2_8_0_1"/></StgValue>
</operation>
</state>

<state id="490" st_id="490">

<operation id="1956" st_id="490" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:17 %sum_2_8_0_1 = fadd i32 %sum_2_8, i32 %mul9_8_0_1

]]></Node>
<StgValue><ssdm name="sum_2_8_0_1"/></StgValue>
</operation>
</state>

<state id="491" st_id="491">

<operation id="1957" st_id="491" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:17 %sum_2_8_0_1 = fadd i32 %sum_2_8, i32 %mul9_8_0_1

]]></Node>
<StgValue><ssdm name="sum_2_8_0_1"/></StgValue>
</operation>
</state>

<state id="492" st_id="492">

<operation id="1958" st_id="492" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:17 %sum_2_8_0_1 = fadd i32 %sum_2_8, i32 %mul9_8_0_1

]]></Node>
<StgValue><ssdm name="sum_2_8_0_1"/></StgValue>
</operation>
</state>

<state id="493" st_id="493">
</state>

<state id="494" st_id="494">

<operation id="1959" st_id="494" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:23 %sum_2_8_0_2 = fadd i32 %sum_2_8_0_1, i32 %mul9_8_0_2

]]></Node>
<StgValue><ssdm name="sum_2_8_0_2"/></StgValue>
</operation>
</state>

<state id="495" st_id="495">

<operation id="1960" st_id="495" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:23 %sum_2_8_0_2 = fadd i32 %sum_2_8_0_1, i32 %mul9_8_0_2

]]></Node>
<StgValue><ssdm name="sum_2_8_0_2"/></StgValue>
</operation>
</state>

<state id="496" st_id="496">

<operation id="1961" st_id="496" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:23 %sum_2_8_0_2 = fadd i32 %sum_2_8_0_1, i32 %mul9_8_0_2

]]></Node>
<StgValue><ssdm name="sum_2_8_0_2"/></StgValue>
</operation>
</state>

<state id="497" st_id="497">

<operation id="1962" st_id="497" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:23 %sum_2_8_0_2 = fadd i32 %sum_2_8_0_1, i32 %mul9_8_0_2

]]></Node>
<StgValue><ssdm name="sum_2_8_0_2"/></StgValue>
</operation>
</state>

<state id="498" st_id="498">

<operation id="1963" st_id="498" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:23 %sum_2_8_0_2 = fadd i32 %sum_2_8_0_1, i32 %mul9_8_0_2

]]></Node>
<StgValue><ssdm name="sum_2_8_0_2"/></StgValue>
</operation>
</state>

<state id="499" st_id="499">

<operation id="1964" st_id="499" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:29 %sum_2_8_1 = fadd i32 %sum_2_8_0_2, i32 %mul9_8_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1"/></StgValue>
</operation>
</state>

<state id="500" st_id="500">

<operation id="1965" st_id="500" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:29 %sum_2_8_1 = fadd i32 %sum_2_8_0_2, i32 %mul9_8_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1"/></StgValue>
</operation>
</state>

<state id="501" st_id="501">

<operation id="1966" st_id="501" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:29 %sum_2_8_1 = fadd i32 %sum_2_8_0_2, i32 %mul9_8_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1"/></StgValue>
</operation>
</state>

<state id="502" st_id="502">

<operation id="1967" st_id="502" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:29 %sum_2_8_1 = fadd i32 %sum_2_8_0_2, i32 %mul9_8_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1"/></StgValue>
</operation>
</state>

<state id="503" st_id="503">

<operation id="1968" st_id="503" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:29 %sum_2_8_1 = fadd i32 %sum_2_8_0_2, i32 %mul9_8_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1"/></StgValue>
</operation>
</state>

<state id="504" st_id="504">
</state>

<state id="505" st_id="505">

<operation id="1969" st_id="505" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="746" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:35 %sum_2_8_1_1 = fadd i32 %sum_2_8_1, i32 %mul9_8_1_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1_1"/></StgValue>
</operation>
</state>

<state id="506" st_id="506">

<operation id="1970" st_id="506" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="746" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:35 %sum_2_8_1_1 = fadd i32 %sum_2_8_1, i32 %mul9_8_1_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1_1"/></StgValue>
</operation>
</state>

<state id="507" st_id="507">

<operation id="1971" st_id="507" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="746" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:35 %sum_2_8_1_1 = fadd i32 %sum_2_8_1, i32 %mul9_8_1_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1_1"/></StgValue>
</operation>
</state>

<state id="508" st_id="508">

<operation id="1972" st_id="508" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="746" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:35 %sum_2_8_1_1 = fadd i32 %sum_2_8_1, i32 %mul9_8_1_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1_1"/></StgValue>
</operation>
</state>

<state id="509" st_id="509">

<operation id="1973" st_id="509" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="746" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:35 %sum_2_8_1_1 = fadd i32 %sum_2_8_1, i32 %mul9_8_1_1

]]></Node>
<StgValue><ssdm name="sum_2_8_1_1"/></StgValue>
</operation>
</state>

<state id="510" st_id="510">

<operation id="1974" st_id="510" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:41 %sum_2_8_1_2 = fadd i32 %sum_2_8_1_1, i32 %mul9_8_1_2

]]></Node>
<StgValue><ssdm name="sum_2_8_1_2"/></StgValue>
</operation>
</state>

<state id="511" st_id="511">

<operation id="1975" st_id="511" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:41 %sum_2_8_1_2 = fadd i32 %sum_2_8_1_1, i32 %mul9_8_1_2

]]></Node>
<StgValue><ssdm name="sum_2_8_1_2"/></StgValue>
</operation>
</state>

<state id="512" st_id="512">

<operation id="1976" st_id="512" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:41 %sum_2_8_1_2 = fadd i32 %sum_2_8_1_1, i32 %mul9_8_1_2

]]></Node>
<StgValue><ssdm name="sum_2_8_1_2"/></StgValue>
</operation>
</state>

<state id="513" st_id="513">

<operation id="1977" st_id="513" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:41 %sum_2_8_1_2 = fadd i32 %sum_2_8_1_1, i32 %mul9_8_1_2

]]></Node>
<StgValue><ssdm name="sum_2_8_1_2"/></StgValue>
</operation>
</state>

<state id="514" st_id="514">

<operation id="1978" st_id="514" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:41 %sum_2_8_1_2 = fadd i32 %sum_2_8_1_1, i32 %mul9_8_1_2

]]></Node>
<StgValue><ssdm name="sum_2_8_1_2"/></StgValue>
</operation>
</state>

<state id="515" st_id="515">
</state>

<state id="516" st_id="516">

<operation id="1979" st_id="516" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="758" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:47 %sum_2_8_2 = fadd i32 %sum_2_8_1_2, i32 %mul9_8_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2"/></StgValue>
</operation>
</state>

<state id="517" st_id="517">

<operation id="1980" st_id="517" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="758" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:47 %sum_2_8_2 = fadd i32 %sum_2_8_1_2, i32 %mul9_8_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2"/></StgValue>
</operation>
</state>

<state id="518" st_id="518">

<operation id="1981" st_id="518" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="758" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:47 %sum_2_8_2 = fadd i32 %sum_2_8_1_2, i32 %mul9_8_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2"/></StgValue>
</operation>
</state>

<state id="519" st_id="519">

<operation id="1982" st_id="519" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="758" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:47 %sum_2_8_2 = fadd i32 %sum_2_8_1_2, i32 %mul9_8_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2"/></StgValue>
</operation>
</state>

<state id="520" st_id="520">

<operation id="1983" st_id="520" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="758" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:47 %sum_2_8_2 = fadd i32 %sum_2_8_1_2, i32 %mul9_8_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2"/></StgValue>
</operation>
</state>

<state id="521" st_id="521">

<operation id="1984" st_id="521" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:53 %sum_2_8_2_1 = fadd i32 %sum_2_8_2, i32 %mul9_8_2_1

]]></Node>
<StgValue><ssdm name="sum_2_8_2_1"/></StgValue>
</operation>
</state>

<state id="522" st_id="522">

<operation id="1985" st_id="522" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:53 %sum_2_8_2_1 = fadd i32 %sum_2_8_2, i32 %mul9_8_2_1

]]></Node>
<StgValue><ssdm name="sum_2_8_2_1"/></StgValue>
</operation>
</state>

<state id="523" st_id="523">

<operation id="1986" st_id="523" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:53 %sum_2_8_2_1 = fadd i32 %sum_2_8_2, i32 %mul9_8_2_1

]]></Node>
<StgValue><ssdm name="sum_2_8_2_1"/></StgValue>
</operation>
</state>

<state id="524" st_id="524">

<operation id="1987" st_id="524" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:53 %sum_2_8_2_1 = fadd i32 %sum_2_8_2, i32 %mul9_8_2_1

]]></Node>
<StgValue><ssdm name="sum_2_8_2_1"/></StgValue>
</operation>
</state>

<state id="525" st_id="525">

<operation id="1988" st_id="525" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:53 %sum_2_8_2_1 = fadd i32 %sum_2_8_2, i32 %mul9_8_2_1

]]></Node>
<StgValue><ssdm name="sum_2_8_2_1"/></StgValue>
</operation>
</state>

<state id="526" st_id="526">
</state>

<state id="527" st_id="527">

<operation id="1989" st_id="527" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:59 %sum_2_8_2_2 = fadd i32 %sum_2_8_2_1, i32 %mul9_8_2_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2_2"/></StgValue>
</operation>
</state>

<state id="528" st_id="528">

<operation id="1990" st_id="528" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:59 %sum_2_8_2_2 = fadd i32 %sum_2_8_2_1, i32 %mul9_8_2_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2_2"/></StgValue>
</operation>
</state>

<state id="529" st_id="529">

<operation id="1991" st_id="529" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:59 %sum_2_8_2_2 = fadd i32 %sum_2_8_2_1, i32 %mul9_8_2_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2_2"/></StgValue>
</operation>
</state>

<state id="530" st_id="530">

<operation id="1992" st_id="530" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:59 %sum_2_8_2_2 = fadd i32 %sum_2_8_2_1, i32 %mul9_8_2_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2_2"/></StgValue>
</operation>
</state>

<state id="531" st_id="531">

<operation id="1993" st_id="531" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.8:59 %sum_2_8_2_2 = fadd i32 %sum_2_8_2_1, i32 %mul9_8_2_2

]]></Node>
<StgValue><ssdm name="sum_2_8_2_2"/></StgValue>
</operation>
</state>

<state id="532" st_id="532">

<operation id="1994" st_id="532" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="712" bw="64" op_0_bw="33">
<![CDATA[
.split4.8:1 %t_3_8_cast = zext i33 %t_3_8

]]></Node>
<StgValue><ssdm name="t_3_8_cast"/></StgValue>
</operation>

<operation id="1995" st_id="532" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="714" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.8:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="1996" st_id="532" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="771" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.8:60 %add_ln58_8 = add i33 %t_3_8, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_8"/></StgValue>
</operation>

<operation id="1997" st_id="532" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="772" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.8:61 %out_addr_17 = getelementptr i32 %out_r, i64 0, i64 %t_3_8_cast

]]></Node>
<StgValue><ssdm name="out_addr_17"/></StgValue>
</operation>

<operation id="1998" st_id="532" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="773" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.8:62 %store_ln58 = store i32 %sum_2_8_2_2, i11 %out_addr_17

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="1999" st_id="532" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="774" bw="0" op_0_bw="0">
<![CDATA[
.split4.8:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="533" st_id="533">

<operation id="2000" st_id="533" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="776" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.8:0 %add_ln44_18 = add i32 %zext_ln44_2, i32 %add_ln44_16

]]></Node>
<StgValue><ssdm name="add_ln44_18"/></StgValue>
</operation>

<operation id="2001" st_id="533" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="777" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.8:1 %add_ln44_19 = add i64 %i_0, i64 9

]]></Node>
<StgValue><ssdm name="add_ln44_19"/></StgValue>
</operation>

<operation id="2002" st_id="533" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="778" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.8:2 %icmp_ln44_9 = icmp_slt  i64 %add_ln44_19, i64 %zext_ln44_1

]]></Node>
<StgValue><ssdm name="icmp_ln44_9"/></StgValue>
</operation>

<operation id="2003" st_id="533" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="779" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.8:3 %br_ln44 = br i1 %icmp_ln44_9, void %._crit_edge13.loopexit, void %.lr.ph.9

]]></Node>
<StgValue><ssdm name="br_ln44"/></StgValue>
</operation>

<operation id="2004" st_id="533" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="782" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.9:1 %empty_139 = add i11 %trunc_ln44, i11 10

]]></Node>
<StgValue><ssdm name="empty_139"/></StgValue>
</operation>

<operation id="2005" st_id="533" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln44_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="783" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.9:2 %empty_140 = mul i11 %empty_139, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_140"/></StgValue>
</operation>
</state>

<state id="534" st_id="534">

<operation id="2006" st_id="534" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="783" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.9:2 %empty_140 = mul i11 %empty_139, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_140"/></StgValue>
</operation>
</state>

<state id="535" st_id="535">

<operation id="2007" st_id="535" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="783" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.9:2 %empty_140 = mul i11 %empty_139, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_140"/></StgValue>
</operation>
</state>

<state id="536" st_id="536">

<operation id="2008" st_id="536" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="781" bw="33" op_0_bw="32">
<![CDATA[
.lr.ph.9:0 %add_ln44_26_cast = sext i32 %add_ln44_18

]]></Node>
<StgValue><ssdm name="add_ln44_26_cast"/></StgValue>
</operation>

<operation id="2009" st_id="536" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="783" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.lr.ph.9:2 %empty_140 = mul i11 %empty_139, i11 %zext_ln44

]]></Node>
<StgValue><ssdm name="empty_140"/></StgValue>
</operation>

<operation id="2010" st_id="536" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="784" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph.9:3 %br_ln47 = br void

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>
</state>

<state id="537" st_id="537">

<operation id="2011" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="787" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:1 %j_9 = phi i6 %add_ln47_9, void %.split4.9, i6 1, void %.lr.ph.9

]]></Node>
<StgValue><ssdm name="j_9"/></StgValue>
</operation>

<operation id="2012" st_id="537" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="789" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:3 %icmp_ln47_9 = icmp_eq  i6 %j_9, i6 %sub1

]]></Node>
<StgValue><ssdm name="icmp_ln47_9"/></StgValue>
</operation>

<operation id="2013" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="791" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln47 = br i1 %icmp_ln47_9, void %.split4.9, void %._crit_edge.loopexit.9

]]></Node>
<StgValue><ssdm name="br_ln47"/></StgValue>
</operation>

<operation id="2014" st_id="537" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="793" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.9:0 %add_ln47_9 = add i6 %j_9, i6 1

]]></Node>
<StgValue><ssdm name="add_ln47_9"/></StgValue>
</operation>

<operation id="2015" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="795" bw="11" op_0_bw="6">
<![CDATA[
.split4.9:2 %j_9_cast = zext i6 %j_9

]]></Node>
<StgValue><ssdm name="j_9_cast"/></StgValue>
</operation>

<operation id="2016" st_id="537" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="797" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split4.9:4 %empty_141 = add i6 %j_9, i6 63

]]></Node>
<StgValue><ssdm name="empty_141"/></StgValue>
</operation>

<operation id="2017" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="798" bw="11" op_0_bw="6">
<![CDATA[
.split4.9:5 %zext_ln8_129 = zext i6 %empty_141

]]></Node>
<StgValue><ssdm name="zext_ln8_129"/></StgValue>
</operation>

<operation id="2018" st_id="537" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="799" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:6 %add_ln8_120 = add i11 %zext_ln8_129, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_120"/></StgValue>
</operation>

<operation id="2019" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="800" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:7 %zext_ln8_130 = zext i11 %add_ln8_120

]]></Node>
<StgValue><ssdm name="zext_ln8_130"/></StgValue>
</operation>

<operation id="2020" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="801" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:8 %arr_addr_120 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_130

]]></Node>
<StgValue><ssdm name="arr_addr_120"/></StgValue>
</operation>

<operation id="2021" st_id="537" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="802" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:9 %arr_load_120 = load i11 %arr_addr_120

]]></Node>
<StgValue><ssdm name="arr_load_120"/></StgValue>
</operation>

<operation id="2022" st_id="537" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="805" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:12 %add_ln8_121 = add i11 %j_9_cast, i11 %empty_132

]]></Node>
<StgValue><ssdm name="add_ln8_121"/></StgValue>
</operation>

<operation id="2023" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="806" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:13 %zext_ln8_131 = zext i11 %add_ln8_121

]]></Node>
<StgValue><ssdm name="zext_ln8_131"/></StgValue>
</operation>

<operation id="2024" st_id="537" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="807" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:14 %arr_addr_121 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_131

]]></Node>
<StgValue><ssdm name="arr_addr_121"/></StgValue>
</operation>

<operation id="2025" st_id="537" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="808" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:15 %arr_load_121 = load i11 %arr_addr_121

]]></Node>
<StgValue><ssdm name="arr_load_121"/></StgValue>
</operation>
</state>

<state id="538" st_id="538">

<operation id="2026" st_id="538" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="802" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:9 %arr_load_120 = load i11 %arr_addr_120

]]></Node>
<StgValue><ssdm name="arr_load_120"/></StgValue>
</operation>

<operation id="2027" st_id="538" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="803" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:10 %mul9_9 = fmul i32 %arr_load_120, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_9"/></StgValue>
</operation>

<operation id="2028" st_id="538" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="808" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:15 %arr_load_121 = load i11 %arr_addr_121

]]></Node>
<StgValue><ssdm name="arr_load_121"/></StgValue>
</operation>

<operation id="2029" st_id="538" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="809" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:16 %mul9_9_0_1 = fmul i32 %arr_load_121, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_9_0_1"/></StgValue>
</operation>

<operation id="2030" st_id="538" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="811" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:18 %add_ln8_122 = add i11 %add_ln8_120, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_122"/></StgValue>
</operation>

<operation id="2031" st_id="538" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="812" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:19 %zext_ln8_132 = zext i11 %add_ln8_122

]]></Node>
<StgValue><ssdm name="zext_ln8_132"/></StgValue>
</operation>

<operation id="2032" st_id="538" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="813" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:20 %arr_addr_122 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_132

]]></Node>
<StgValue><ssdm name="arr_addr_122"/></StgValue>
</operation>

<operation id="2033" st_id="538" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="814" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:21 %arr_load_122 = load i11 %arr_addr_122

]]></Node>
<StgValue><ssdm name="arr_load_122"/></StgValue>
</operation>

<operation id="2034" st_id="538" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="817" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:24 %add_ln8_123 = add i11 %zext_ln8_129, i11 %empty_136

]]></Node>
<StgValue><ssdm name="add_ln8_123"/></StgValue>
</operation>

<operation id="2035" st_id="538" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="818" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:25 %zext_ln8_133 = zext i11 %add_ln8_123

]]></Node>
<StgValue><ssdm name="zext_ln8_133"/></StgValue>
</operation>

<operation id="2036" st_id="538" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="819" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:26 %arr_addr_123 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_133

]]></Node>
<StgValue><ssdm name="arr_addr_123"/></StgValue>
</operation>

<operation id="2037" st_id="538" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="820" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:27 %arr_load_123 = load i11 %arr_addr_123

]]></Node>
<StgValue><ssdm name="arr_load_123"/></StgValue>
</operation>

<operation id="2038" st_id="538" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="835" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:42 %add_ln8_126 = add i11 %zext_ln8_129, i11 %empty_140

]]></Node>
<StgValue><ssdm name="add_ln8_126"/></StgValue>
</operation>
</state>

<state id="539" st_id="539">

<operation id="2039" st_id="539" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="803" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:10 %mul9_9 = fmul i32 %arr_load_120, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_9"/></StgValue>
</operation>

<operation id="2040" st_id="539" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="809" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:16 %mul9_9_0_1 = fmul i32 %arr_load_121, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_9_0_1"/></StgValue>
</operation>

<operation id="2041" st_id="539" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="814" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:21 %arr_load_122 = load i11 %arr_addr_122

]]></Node>
<StgValue><ssdm name="arr_load_122"/></StgValue>
</operation>

<operation id="2042" st_id="539" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:22 %mul9_9_0_2 = fmul i32 %arr_load_122, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_9_0_2"/></StgValue>
</operation>

<operation id="2043" st_id="539" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="820" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:27 %arr_load_123 = load i11 %arr_addr_123

]]></Node>
<StgValue><ssdm name="arr_load_123"/></StgValue>
</operation>

<operation id="2044" st_id="539" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="821" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:28 %mul9_9_1 = fmul i32 %arr_load_123, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_9_1"/></StgValue>
</operation>

<operation id="2045" st_id="539" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="823" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:30 %add_ln8_124 = add i11 %j_9_cast, i11 %empty_136

]]></Node>
<StgValue><ssdm name="add_ln8_124"/></StgValue>
</operation>

<operation id="2046" st_id="539" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="824" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:31 %zext_ln8_134 = zext i11 %add_ln8_124

]]></Node>
<StgValue><ssdm name="zext_ln8_134"/></StgValue>
</operation>

<operation id="2047" st_id="539" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="825" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:32 %arr_addr_124 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_134

]]></Node>
<StgValue><ssdm name="arr_addr_124"/></StgValue>
</operation>

<operation id="2048" st_id="539" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="826" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:33 %arr_load_124 = load i11 %arr_addr_124

]]></Node>
<StgValue><ssdm name="arr_load_124"/></StgValue>
</operation>

<operation id="2049" st_id="539" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="829" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:36 %add_ln8_125 = add i11 %add_ln8_123, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_125"/></StgValue>
</operation>

<operation id="2050" st_id="539" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="830" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:37 %zext_ln8_135 = zext i11 %add_ln8_125

]]></Node>
<StgValue><ssdm name="zext_ln8_135"/></StgValue>
</operation>

<operation id="2051" st_id="539" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="831" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:38 %arr_addr_125 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_135

]]></Node>
<StgValue><ssdm name="arr_addr_125"/></StgValue>
</operation>

<operation id="2052" st_id="539" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="832" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:39 %arr_load_125 = load i11 %arr_addr_125

]]></Node>
<StgValue><ssdm name="arr_load_125"/></StgValue>
</operation>

<operation id="2053" st_id="539" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="841" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:48 %add_ln8_127 = add i11 %j_9_cast, i11 %empty_140

]]></Node>
<StgValue><ssdm name="add_ln8_127"/></StgValue>
</operation>
</state>

<state id="540" st_id="540">

<operation id="2054" st_id="540" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="803" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:10 %mul9_9 = fmul i32 %arr_load_120, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_9"/></StgValue>
</operation>

<operation id="2055" st_id="540" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="809" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:16 %mul9_9_0_1 = fmul i32 %arr_load_121, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_9_0_1"/></StgValue>
</operation>

<operation id="2056" st_id="540" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:22 %mul9_9_0_2 = fmul i32 %arr_load_122, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_9_0_2"/></StgValue>
</operation>

<operation id="2057" st_id="540" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="821" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:28 %mul9_9_1 = fmul i32 %arr_load_123, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_9_1"/></StgValue>
</operation>

<operation id="2058" st_id="540" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="826" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:33 %arr_load_124 = load i11 %arr_addr_124

]]></Node>
<StgValue><ssdm name="arr_load_124"/></StgValue>
</operation>

<operation id="2059" st_id="540" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:34 %mul9_9_1_1 = fmul i32 %arr_load_124, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_9_1_1"/></StgValue>
</operation>

<operation id="2060" st_id="540" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="832" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:39 %arr_load_125 = load i11 %arr_addr_125

]]></Node>
<StgValue><ssdm name="arr_load_125"/></StgValue>
</operation>

<operation id="2061" st_id="540" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="833" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:40 %mul9_9_1_2 = fmul i32 %arr_load_125, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_9_1_2"/></StgValue>
</operation>

<operation id="2062" st_id="540" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="836" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:43 %zext_ln8_136 = zext i11 %add_ln8_126

]]></Node>
<StgValue><ssdm name="zext_ln8_136"/></StgValue>
</operation>

<operation id="2063" st_id="540" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="837" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:44 %arr_addr_126 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_136

]]></Node>
<StgValue><ssdm name="arr_addr_126"/></StgValue>
</operation>

<operation id="2064" st_id="540" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="838" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:45 %arr_load_126 = load i11 %arr_addr_126

]]></Node>
<StgValue><ssdm name="arr_load_126"/></StgValue>
</operation>

<operation id="2065" st_id="540" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="842" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:49 %zext_ln8_137 = zext i11 %add_ln8_127

]]></Node>
<StgValue><ssdm name="zext_ln8_137"/></StgValue>
</operation>

<operation id="2066" st_id="540" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="843" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:50 %arr_addr_127 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_137

]]></Node>
<StgValue><ssdm name="arr_addr_127"/></StgValue>
</operation>

<operation id="2067" st_id="540" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="844" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:51 %arr_load_127 = load i11 %arr_addr_127

]]></Node>
<StgValue><ssdm name="arr_load_127"/></StgValue>
</operation>
</state>

<state id="541" st_id="541">

<operation id="2068" st_id="541" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="803" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:10 %mul9_9 = fmul i32 %arr_load_120, i32 %p_read_9

]]></Node>
<StgValue><ssdm name="mul9_9"/></StgValue>
</operation>

<operation id="2069" st_id="541" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="809" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:16 %mul9_9_0_1 = fmul i32 %arr_load_121, i32 %p_read_8

]]></Node>
<StgValue><ssdm name="mul9_9_0_1"/></StgValue>
</operation>

<operation id="2070" st_id="541" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:22 %mul9_9_0_2 = fmul i32 %arr_load_122, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_9_0_2"/></StgValue>
</operation>

<operation id="2071" st_id="541" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="821" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:28 %mul9_9_1 = fmul i32 %arr_load_123, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_9_1"/></StgValue>
</operation>

<operation id="2072" st_id="541" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:34 %mul9_9_1_1 = fmul i32 %arr_load_124, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_9_1_1"/></StgValue>
</operation>

<operation id="2073" st_id="541" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="833" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:40 %mul9_9_1_2 = fmul i32 %arr_load_125, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_9_1_2"/></StgValue>
</operation>

<operation id="2074" st_id="541" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="838" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:45 %arr_load_126 = load i11 %arr_addr_126

]]></Node>
<StgValue><ssdm name="arr_load_126"/></StgValue>
</operation>

<operation id="2075" st_id="541" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:46 %mul9_9_2 = fmul i32 %arr_load_126, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_9_2"/></StgValue>
</operation>

<operation id="2076" st_id="541" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="844" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:51 %arr_load_127 = load i11 %arr_addr_127

]]></Node>
<StgValue><ssdm name="arr_load_127"/></StgValue>
</operation>

<operation id="2077" st_id="541" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="845" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:52 %mul9_9_2_1 = fmul i32 %arr_load_127, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_9_2_1"/></StgValue>
</operation>

<operation id="2078" st_id="541" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="847" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:54 %add_ln8_128 = add i11 %add_ln8_126, i11 2

]]></Node>
<StgValue><ssdm name="add_ln8_128"/></StgValue>
</operation>

<operation id="2079" st_id="541" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="848" bw="64" op_0_bw="11">
<![CDATA[
.split4.9:55 %zext_ln8_138 = zext i11 %add_ln8_128

]]></Node>
<StgValue><ssdm name="zext_ln8_138"/></StgValue>
</operation>

<operation id="2080" st_id="541" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="849" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:56 %arr_addr_128 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_138

]]></Node>
<StgValue><ssdm name="arr_addr_128"/></StgValue>
</operation>

<operation id="2081" st_id="541" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="850" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:57 %arr_load_128 = load i11 %arr_addr_128

]]></Node>
<StgValue><ssdm name="arr_load_128"/></StgValue>
</operation>
</state>

<state id="542" st_id="542">

<operation id="2082" st_id="542" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:11 %sum_2_9 = fadd i32 %mul9_9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_9"/></StgValue>
</operation>

<operation id="2083" st_id="542" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:22 %mul9_9_0_2 = fmul i32 %arr_load_122, i32 %p_read_7

]]></Node>
<StgValue><ssdm name="mul9_9_0_2"/></StgValue>
</operation>

<operation id="2084" st_id="542" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="821" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:28 %mul9_9_1 = fmul i32 %arr_load_123, i32 %p_read_6

]]></Node>
<StgValue><ssdm name="mul9_9_1"/></StgValue>
</operation>

<operation id="2085" st_id="542" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:34 %mul9_9_1_1 = fmul i32 %arr_load_124, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_9_1_1"/></StgValue>
</operation>

<operation id="2086" st_id="542" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="833" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:40 %mul9_9_1_2 = fmul i32 %arr_load_125, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_9_1_2"/></StgValue>
</operation>

<operation id="2087" st_id="542" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:46 %mul9_9_2 = fmul i32 %arr_load_126, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_9_2"/></StgValue>
</operation>

<operation id="2088" st_id="542" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="845" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:52 %mul9_9_2_1 = fmul i32 %arr_load_127, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_9_2_1"/></StgValue>
</operation>

<operation id="2089" st_id="542" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="850" bw="32" op_0_bw="11">
<![CDATA[
.split4.9:57 %arr_load_128 = load i11 %arr_addr_128

]]></Node>
<StgValue><ssdm name="arr_load_128"/></StgValue>
</operation>

<operation id="2090" st_id="542" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="851" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:58 %mul9_9_2_2 = fmul i32 %arr_load_128, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_9_2_2"/></StgValue>
</operation>
</state>

<state id="543" st_id="543">

<operation id="2091" st_id="543" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:11 %sum_2_9 = fadd i32 %mul9_9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_9"/></StgValue>
</operation>

<operation id="2092" st_id="543" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:34 %mul9_9_1_1 = fmul i32 %arr_load_124, i32 %p_read_5

]]></Node>
<StgValue><ssdm name="mul9_9_1_1"/></StgValue>
</operation>

<operation id="2093" st_id="543" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="833" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:40 %mul9_9_1_2 = fmul i32 %arr_load_125, i32 %p_read_4

]]></Node>
<StgValue><ssdm name="mul9_9_1_2"/></StgValue>
</operation>

<operation id="2094" st_id="543" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:46 %mul9_9_2 = fmul i32 %arr_load_126, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_9_2"/></StgValue>
</operation>

<operation id="2095" st_id="543" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="845" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:52 %mul9_9_2_1 = fmul i32 %arr_load_127, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_9_2_1"/></StgValue>
</operation>

<operation id="2096" st_id="543" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="851" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:58 %mul9_9_2_2 = fmul i32 %arr_load_128, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_9_2_2"/></StgValue>
</operation>
</state>

<state id="544" st_id="544">

<operation id="2097" st_id="544" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:11 %sum_2_9 = fadd i32 %mul9_9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_9"/></StgValue>
</operation>

<operation id="2098" st_id="544" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:46 %mul9_9_2 = fmul i32 %arr_load_126, i32 %p_read_3

]]></Node>
<StgValue><ssdm name="mul9_9_2"/></StgValue>
</operation>

<operation id="2099" st_id="544" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="845" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:52 %mul9_9_2_1 = fmul i32 %arr_load_127, i32 %p_read_2

]]></Node>
<StgValue><ssdm name="mul9_9_2_1"/></StgValue>
</operation>

<operation id="2100" st_id="544" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="851" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:58 %mul9_9_2_2 = fmul i32 %arr_load_128, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_9_2_2"/></StgValue>
</operation>
</state>

<state id="545" st_id="545">

<operation id="2101" st_id="545" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:11 %sum_2_9 = fadd i32 %mul9_9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_9"/></StgValue>
</operation>

<operation id="2102" st_id="545" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="851" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:58 %mul9_9_2_2 = fmul i32 %arr_load_128, i32 %p_read_1

]]></Node>
<StgValue><ssdm name="mul9_9_2_2"/></StgValue>
</operation>
</state>

<state id="546" st_id="546">

<operation id="2103" st_id="546" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:11 %sum_2_9 = fadd i32 %mul9_9, i32 0

]]></Node>
<StgValue><ssdm name="sum_2_9"/></StgValue>
</operation>
</state>

<state id="547" st_id="547">

<operation id="2104" st_id="547" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:17 %sum_2_9_0_1 = fadd i32 %sum_2_9, i32 %mul9_9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_9_0_1"/></StgValue>
</operation>
</state>

<state id="548" st_id="548">

<operation id="2105" st_id="548" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:17 %sum_2_9_0_1 = fadd i32 %sum_2_9, i32 %mul9_9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_9_0_1"/></StgValue>
</operation>
</state>

<state id="549" st_id="549">

<operation id="2106" st_id="549" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:17 %sum_2_9_0_1 = fadd i32 %sum_2_9, i32 %mul9_9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_9_0_1"/></StgValue>
</operation>
</state>

<state id="550" st_id="550">

<operation id="2107" st_id="550" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:17 %sum_2_9_0_1 = fadd i32 %sum_2_9, i32 %mul9_9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_9_0_1"/></StgValue>
</operation>
</state>

<state id="551" st_id="551">

<operation id="2108" st_id="551" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:17 %sum_2_9_0_1 = fadd i32 %sum_2_9, i32 %mul9_9_0_1

]]></Node>
<StgValue><ssdm name="sum_2_9_0_1"/></StgValue>
</operation>
</state>

<state id="552" st_id="552">
</state>

<state id="553" st_id="553">

<operation id="2109" st_id="553" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:23 %sum_2_9_0_2 = fadd i32 %sum_2_9_0_1, i32 %mul9_9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_9_0_2"/></StgValue>
</operation>
</state>

<state id="554" st_id="554">

<operation id="2110" st_id="554" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:23 %sum_2_9_0_2 = fadd i32 %sum_2_9_0_1, i32 %mul9_9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_9_0_2"/></StgValue>
</operation>
</state>

<state id="555" st_id="555">

<operation id="2111" st_id="555" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:23 %sum_2_9_0_2 = fadd i32 %sum_2_9_0_1, i32 %mul9_9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_9_0_2"/></StgValue>
</operation>
</state>

<state id="556" st_id="556">

<operation id="2112" st_id="556" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:23 %sum_2_9_0_2 = fadd i32 %sum_2_9_0_1, i32 %mul9_9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_9_0_2"/></StgValue>
</operation>
</state>

<state id="557" st_id="557">

<operation id="2113" st_id="557" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:23 %sum_2_9_0_2 = fadd i32 %sum_2_9_0_1, i32 %mul9_9_0_2

]]></Node>
<StgValue><ssdm name="sum_2_9_0_2"/></StgValue>
</operation>
</state>

<state id="558" st_id="558">

<operation id="2114" st_id="558" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:29 %sum_2_9_1 = fadd i32 %sum_2_9_0_2, i32 %mul9_9_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1"/></StgValue>
</operation>
</state>

<state id="559" st_id="559">

<operation id="2115" st_id="559" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:29 %sum_2_9_1 = fadd i32 %sum_2_9_0_2, i32 %mul9_9_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1"/></StgValue>
</operation>
</state>

<state id="560" st_id="560">

<operation id="2116" st_id="560" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:29 %sum_2_9_1 = fadd i32 %sum_2_9_0_2, i32 %mul9_9_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1"/></StgValue>
</operation>
</state>

<state id="561" st_id="561">

<operation id="2117" st_id="561" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:29 %sum_2_9_1 = fadd i32 %sum_2_9_0_2, i32 %mul9_9_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1"/></StgValue>
</operation>
</state>

<state id="562" st_id="562">

<operation id="2118" st_id="562" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:29 %sum_2_9_1 = fadd i32 %sum_2_9_0_2, i32 %mul9_9_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1"/></StgValue>
</operation>
</state>

<state id="563" st_id="563">
</state>

<state id="564" st_id="564">

<operation id="2119" st_id="564" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:35 %sum_2_9_1_1 = fadd i32 %sum_2_9_1, i32 %mul9_9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1_1"/></StgValue>
</operation>
</state>

<state id="565" st_id="565">

<operation id="2120" st_id="565" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:35 %sum_2_9_1_1 = fadd i32 %sum_2_9_1, i32 %mul9_9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1_1"/></StgValue>
</operation>
</state>

<state id="566" st_id="566">

<operation id="2121" st_id="566" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:35 %sum_2_9_1_1 = fadd i32 %sum_2_9_1, i32 %mul9_9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1_1"/></StgValue>
</operation>
</state>

<state id="567" st_id="567">

<operation id="2122" st_id="567" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:35 %sum_2_9_1_1 = fadd i32 %sum_2_9_1, i32 %mul9_9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1_1"/></StgValue>
</operation>
</state>

<state id="568" st_id="568">

<operation id="2123" st_id="568" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:35 %sum_2_9_1_1 = fadd i32 %sum_2_9_1, i32 %mul9_9_1_1

]]></Node>
<StgValue><ssdm name="sum_2_9_1_1"/></StgValue>
</operation>
</state>

<state id="569" st_id="569">

<operation id="2124" st_id="569" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:41 %sum_2_9_1_2 = fadd i32 %sum_2_9_1_1, i32 %mul9_9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_9_1_2"/></StgValue>
</operation>
</state>

<state id="570" st_id="570">

<operation id="2125" st_id="570" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:41 %sum_2_9_1_2 = fadd i32 %sum_2_9_1_1, i32 %mul9_9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_9_1_2"/></StgValue>
</operation>
</state>

<state id="571" st_id="571">

<operation id="2126" st_id="571" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:41 %sum_2_9_1_2 = fadd i32 %sum_2_9_1_1, i32 %mul9_9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_9_1_2"/></StgValue>
</operation>
</state>

<state id="572" st_id="572">

<operation id="2127" st_id="572" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:41 %sum_2_9_1_2 = fadd i32 %sum_2_9_1_1, i32 %mul9_9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_9_1_2"/></StgValue>
</operation>
</state>

<state id="573" st_id="573">

<operation id="2128" st_id="573" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:41 %sum_2_9_1_2 = fadd i32 %sum_2_9_1_1, i32 %mul9_9_1_2

]]></Node>
<StgValue><ssdm name="sum_2_9_1_2"/></StgValue>
</operation>
</state>

<state id="574" st_id="574">
</state>

<state id="575" st_id="575">

<operation id="2129" st_id="575" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:47 %sum_2_9_2 = fadd i32 %sum_2_9_1_2, i32 %mul9_9_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2"/></StgValue>
</operation>
</state>

<state id="576" st_id="576">

<operation id="2130" st_id="576" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:47 %sum_2_9_2 = fadd i32 %sum_2_9_1_2, i32 %mul9_9_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2"/></StgValue>
</operation>
</state>

<state id="577" st_id="577">

<operation id="2131" st_id="577" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:47 %sum_2_9_2 = fadd i32 %sum_2_9_1_2, i32 %mul9_9_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2"/></StgValue>
</operation>
</state>

<state id="578" st_id="578">

<operation id="2132" st_id="578" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:47 %sum_2_9_2 = fadd i32 %sum_2_9_1_2, i32 %mul9_9_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2"/></StgValue>
</operation>
</state>

<state id="579" st_id="579">

<operation id="2133" st_id="579" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:47 %sum_2_9_2 = fadd i32 %sum_2_9_1_2, i32 %mul9_9_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2"/></StgValue>
</operation>
</state>

<state id="580" st_id="580">

<operation id="2134" st_id="580" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:53 %sum_2_9_2_1 = fadd i32 %sum_2_9_2, i32 %mul9_9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_9_2_1"/></StgValue>
</operation>
</state>

<state id="581" st_id="581">

<operation id="2135" st_id="581" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:53 %sum_2_9_2_1 = fadd i32 %sum_2_9_2, i32 %mul9_9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_9_2_1"/></StgValue>
</operation>
</state>

<state id="582" st_id="582">

<operation id="2136" st_id="582" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:53 %sum_2_9_2_1 = fadd i32 %sum_2_9_2, i32 %mul9_9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_9_2_1"/></StgValue>
</operation>
</state>

<state id="583" st_id="583">

<operation id="2137" st_id="583" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:53 %sum_2_9_2_1 = fadd i32 %sum_2_9_2, i32 %mul9_9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_9_2_1"/></StgValue>
</operation>
</state>

<state id="584" st_id="584">

<operation id="2138" st_id="584" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:53 %sum_2_9_2_1 = fadd i32 %sum_2_9_2, i32 %mul9_9_2_1

]]></Node>
<StgValue><ssdm name="sum_2_9_2_1"/></StgValue>
</operation>
</state>

<state id="585" st_id="585">
</state>

<state id="586" st_id="586">

<operation id="2139" st_id="586" stage="5" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:59 %sum_2_9_2_2 = fadd i32 %sum_2_9_2_1, i32 %mul9_9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2_2"/></StgValue>
</operation>
</state>

<state id="587" st_id="587">

<operation id="2140" st_id="587" stage="4" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:59 %sum_2_9_2_2 = fadd i32 %sum_2_9_2_1, i32 %mul9_9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2_2"/></StgValue>
</operation>
</state>

<state id="588" st_id="588">

<operation id="2141" st_id="588" stage="3" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:59 %sum_2_9_2_2 = fadd i32 %sum_2_9_2_1, i32 %mul9_9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2_2"/></StgValue>
</operation>
</state>

<state id="589" st_id="589">

<operation id="2142" st_id="589" stage="2" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:59 %sum_2_9_2_2 = fadd i32 %sum_2_9_2_1, i32 %mul9_9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2_2"/></StgValue>
</operation>
</state>

<state id="590" st_id="590">

<operation id="2143" st_id="590" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="786" bw="33" op_0_bw="33" op_1_bw="0" op_2_bw="33" op_3_bw="0">
<![CDATA[
:0 %t_3_9 = phi i33 %add_ln58_9, void %.split4.9, i33 %add_ln44_26_cast, void %.lr.ph.9

]]></Node>
<StgValue><ssdm name="t_3_9"/></StgValue>
</operation>

<operation id="2144" st_id="590" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="788" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="2145" st_id="590" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="790" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_138 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 10, i64 52, i64 0

]]></Node>
<StgValue><ssdm name="empty_138"/></StgValue>
</operation>

<operation id="2146" st_id="590" stage="1" lat="5">
<core>FAddSub_fulldsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split4.9:59 %sum_2_9_2_2 = fadd i32 %sum_2_9_2_1, i32 %mul9_9_2_2

]]></Node>
<StgValue><ssdm name="sum_2_9_2_2"/></StgValue>
</operation>
</state>

<state id="591" st_id="591">

<operation id="2147" st_id="591" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="794" bw="64" op_0_bw="33">
<![CDATA[
.split4.9:1 %t_3_9_cast = zext i33 %t_3_9

]]></Node>
<StgValue><ssdm name="t_3_9_cast"/></StgValue>
</operation>

<operation id="2148" st_id="591" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="796" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.9:3 %specloopname_ln42 = specloopname void @_ssdm_op_SpecLoopName, void @empty_5

]]></Node>
<StgValue><ssdm name="specloopname_ln42"/></StgValue>
</operation>

<operation id="2149" st_id="591" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="853" bw="33" op_0_bw="33" op_1_bw="33">
<![CDATA[
.split4.9:60 %add_ln58_9 = add i33 %t_3_9, i33 1

]]></Node>
<StgValue><ssdm name="add_ln58_9"/></StgValue>
</operation>

<operation id="2150" st_id="591" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="854" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split4.9:61 %out_addr_18 = getelementptr i32 %out_r, i64 0, i64 %t_3_9_cast

]]></Node>
<StgValue><ssdm name="out_addr_18"/></StgValue>
</operation>

<operation id="2151" st_id="591" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="855" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split4.9:62 %store_ln58 = store i32 %sum_2_9_2_2, i11 %out_addr_18

]]></Node>
<StgValue><ssdm name="store_ln58"/></StgValue>
</operation>

<operation id="2152" st_id="591" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln47_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="856" bw="0" op_0_bw="0">
<![CDATA[
.split4.9:63 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="592" st_id="592">

<operation id="2153" st_id="592" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="858" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.9:0 %add_ln44_20 = add i32 %zext_ln44_2, i32 %add_ln44_18

]]></Node>
<StgValue><ssdm name="add_ln44_20"/></StgValue>
</operation>

<operation id="2154" st_id="592" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="859" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.9:1 %add_ln44_21 = add i64 %i_0, i64 10

]]></Node>
<StgValue><ssdm name="add_ln44_21"/></StgValue>
</operation>

<operation id="2155" st_id="592" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="860" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.9:2 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="593" st_id="593">

<operation id="2156" st_id="593" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="862" bw="0">
<![CDATA[
._crit_edge13.loopexit:0 %ret_ln61 = ret

]]></Node>
<StgValue><ssdm name="ret_ln61"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
