<stg><name>Loop_VConvH_proc</name>


<trans_list>

<trans id="125" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="126" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="127" from="3" to="4">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="137" from="3" to="2">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="128" from="4" to="5">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="136" from="4" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="130" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="131" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="132" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="133" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="134" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="135" from="10" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:0  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:1  call void (...)* @_ssdm_op_SpecInterface(i32* %hconv_V, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [1 x i8]* @p_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:2  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_xlim_loc, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:3  call void (...)* @_ssdm_op_SpecInterface(i32* %height, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:4  %height_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %height)

]]></Node>
<StgValue><ssdm name="height_read"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:5  %vconv_xlim_loc_read = call i32 @_ssdm_op_Read.ap_fifo.i32P(i32* %vconv_xlim_loc)

]]></Node>
<StgValue><ssdm name="vconv_xlim_loc_read"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:6  call void (...)* @_ssdm_op_SpecInterface(i32* %height_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:7  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %height_out, i32 %height_read)

]]></Node>
<StgValue><ssdm name="write_ln185"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0">
<![CDATA[
entry:8  call void (...)* @_ssdm_op_SpecInterface(i32* %vconv_xlim_loc_out, [8 x i8]* @ap_fifo_str, i32 0, i32 0, [1 x i8]* @p_str, i32 0, i32 0, [1 x i8]* @p_str, [1 x i8]* @p_str, [1 x i8]* @p_str, i32 2, i32 2, i32 16, i32 16, [1 x i8]* @p_str, [11 x i8]* @ScalarProp_str)

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
entry:9  call void @_ssdm_op_Write.ap_fifo.i32P(i32* %vconv_xlim_loc_out, i32 %vconv_xlim_loc_read)

]]></Node>
<StgValue><ssdm name="write_ln0"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="0" op_0_bw="0">
<![CDATA[
entry:10  br label %.preheader31.i.i.i

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="22" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
.preheader31.i.i.i:0  %col1_0_i_i_i = phi i11 [ %col, %VConvH_end ], [ 0, %entry ]

]]></Node>
<StgValue><ssdm name="col1_0_i_i_i"/></StgValue>
</operation>

<operation id="23" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="32" op_0_bw="11">
<![CDATA[
.preheader31.i.i.i:1  %zext_ln185 = zext i11 %col1_0_i_i_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln185"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.preheader31.i.i.i:2  %icmp_ln185 = icmp slt i32 %zext_ln185, %height_read

]]></Node>
<StgValue><ssdm name="icmp_ln185"/></StgValue>
</operation>

<operation id="25" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.preheader31.i.i.i:3  %empty = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 1079, i64 0)

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.preheader31.i.i.i:4  %col = add i11 %col1_0_i_i_i, 1

]]></Node>
<StgValue><ssdm name="col"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader31.i.i.i:5  br i1 %icmp_ln185, label %VConvH_begin, label %.exit

]]></Node>
<StgValue><ssdm name="br_ln185"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
VConvH_begin:0  call void (...)* @_ssdm_op_SpecLoopName([7 x i8]* @p_str17) nounwind

]]></Node>
<StgValue><ssdm name="specloopname_ln185"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
VConvH_begin:1  %tmp_3_i_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([7 x i8]* @p_str17)

]]></Node>
<StgValue><ssdm name="tmp_3_i_i"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="39" bw="1" op_0_bw="11" op_1_bw="11">
<![CDATA[
VConvH_begin:2  %icmp_ln197 = icmp ugt i11 %col1_0_i_i_i, 9

]]></Node>
<StgValue><ssdm name="icmp_ln197"/></StgValue>
</operation>

<operation id="31" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="0">
<![CDATA[
VConvH_begin:3  br label %0

]]></Node>
<StgValue><ssdm name="br_ln186"/></StgValue>
</operation>

<operation id="32" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln185" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="142" bw="0">
<![CDATA[
.exit:0  ret void

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="33" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0  %row2_0_i_i_i = phi i11 [ 0, %VConvH_begin ], [ %row, %VConvW_end ]

]]></Node>
<StgValue><ssdm name="row2_0_i_i_i"/></StgValue>
</operation>

<operation id="34" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="32" op_0_bw="11">
<![CDATA[
:1  %zext_ln186 = zext i11 %row2_0_i_i_i to i32

]]></Node>
<StgValue><ssdm name="zext_ln186"/></StgValue>
</operation>

<operation id="35" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %icmp_ln186 = icmp slt i32 %zext_ln186, %vconv_xlim_loc_read

]]></Node>
<StgValue><ssdm name="icmp_ln186"/></StgValue>
</operation>

<operation id="36" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:3  %empty_15 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 0, i64 1909, i64 0)

]]></Node>
<StgValue><ssdm name="empty_15"/></StgValue>
</operation>

<operation id="37" st_id="3" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
:4  %row = add i11 %row2_0_i_i_i, 1

]]></Node>
<StgValue><ssdm name="row"/></StgValue>
</operation>

<operation id="38" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5  br i1 %icmp_ln186, label %VConvW_begin, label %VConvH_end

]]></Node>
<StgValue><ssdm name="br_ln186"/></StgValue>
</operation>

<operation id="39" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
VConvW_begin:0  call void (...)* @_ssdm_op_SpecLoopName([7 x i8]* @p_str18) nounwind

]]></Node>
<StgValue><ssdm name="specloopname_ln186"/></StgValue>
</operation>

<operation id="40" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
VConvW_begin:1  %tmp_15_i_i = call i32 (...)* @_ssdm_op_SpecRegionBegin([7 x i8]* @p_str18)

]]></Node>
<StgValue><ssdm name="tmp_15_i_i"/></StgValue>
</operation>

<operation id="41" st_id="3" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
VConvW_begin:2  %tmp_1 = call i32 @_ssdm_op_Read.ap_fifo.volatile.i32P(i32* %hconv_V)

]]></Node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="42" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="64" op_0_bw="11">
<![CDATA[
VConvW_begin:3  %zext_ln192 = zext i11 %row2_0_i_i_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln192"/></StgValue>
</operation>

<operation id="43" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:4  %linebuf_0_addr = getelementptr [1920 x i32]* @linebuf_0, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_0_addr"/></StgValue>
</operation>

<operation id="44" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:5  %linebuf_1_addr = getelementptr [1920 x i32]* @linebuf_1, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_1_addr"/></StgValue>
</operation>

<operation id="45" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:6  %linebuf_2_addr = getelementptr [1920 x i32]* @linebuf_2, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_2_addr"/></StgValue>
</operation>

<operation id="46" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:7  %linebuf_3_addr = getelementptr [1920 x i32]* @linebuf_3, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_3_addr"/></StgValue>
</operation>

<operation id="47" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:8  %linebuf_4_addr = getelementptr [1920 x i32]* @linebuf_4, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_4_addr"/></StgValue>
</operation>

<operation id="48" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:9  %linebuf_5_addr = getelementptr [1920 x i32]* @linebuf_5, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_5_addr"/></StgValue>
</operation>

<operation id="49" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:10  %linebuf_6_addr = getelementptr [1920 x i32]* @linebuf_6, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_6_addr"/></StgValue>
</operation>

<operation id="50" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:11  %linebuf_7_addr = getelementptr [1920 x i32]* @linebuf_7, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_7_addr"/></StgValue>
</operation>

<operation id="51" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:12  %linebuf_8_addr = getelementptr [1920 x i32]* @linebuf_8, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_8_addr"/></StgValue>
</operation>

<operation id="52" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
VConvW_begin:13  %linebuf_9_addr = getelementptr [1920 x i32]* @linebuf_9, i64 0, i64 %zext_ln192

]]></Node>
<StgValue><ssdm name="linebuf_9_addr"/></StgValue>
</operation>

<operation id="53" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="0" op_0_bw="0">
<![CDATA[
VConvW_begin:14  br label %2

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>

<operation id="54" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
VConvH_end:0  %empty_14 = call i32 (...)* @_ssdm_op_SpecRegionEnd([7 x i8]* @p_str17, i32 %tmp_3_i_i)

]]></Node>
<StgValue><ssdm name="empty_14"/></StgValue>
</operation>

<operation id="55" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln186" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="0" op_0_bw="0">
<![CDATA[
VConvH_end:1  br label %.preheader31.i.i.i

]]></Node>
<StgValue><ssdm name="br_ln185"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="56" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:0  %tmp = phi i32 [ 0, %VConvW_begin ], [ %out_val, %._crit_edge4.i.i.i ]

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="57" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="66" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
:1  %i5_0_i_i_i = phi i4 [ 0, %VConvW_begin ], [ %i, %._crit_edge4.i.i.i ]

]]></Node>
<StgValue><ssdm name="i5_0_i_i_i"/></StgValue>
</operation>

<operation id="58" st_id="4" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="67" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
:2  %icmp_ln191 = icmp eq i4 %i5_0_i_i_i, -5

]]></Node>
<StgValue><ssdm name="icmp_ln191"/></StgValue>
</operation>

<operation id="59" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:3  %empty_17 = call i32 (...)* @_ssdm_op_SpecLoopTripCount(i64 11, i64 11, i64 11)

]]></Node>
<StgValue><ssdm name="empty_17"/></StgValue>
</operation>

<operation id="60" st_id="4" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="69" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
:4  %i = add i4 %i5_0_i_i_i, 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="61" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5  br i1 %icmp_ln191, label %1, label %_ifconv

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>

<operation id="62" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:2  %linebuf_0_load = load i32* %linebuf_0_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_0_load"/></StgValue>
</operation>

<operation id="63" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:3  %linebuf_1_load = load i32* %linebuf_1_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_1_load"/></StgValue>
</operation>

<operation id="64" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:4  %linebuf_2_load = load i32* %linebuf_2_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_2_load"/></StgValue>
</operation>

<operation id="65" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:5  %linebuf_3_load = load i32* %linebuf_3_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_3_load"/></StgValue>
</operation>

<operation id="66" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:6  %linebuf_4_load = load i32* %linebuf_4_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_4_load"/></StgValue>
</operation>

<operation id="67" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:7  %linebuf_5_load = load i32* %linebuf_5_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_5_load"/></StgValue>
</operation>

<operation id="68" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:8  %linebuf_6_load = load i32* %linebuf_6_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_6_load"/></StgValue>
</operation>

<operation id="69" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:9  %linebuf_7_load = load i32* %linebuf_7_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_7_load"/></StgValue>
</operation>

<operation id="70" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:10  %linebuf_8_load = load i32* %linebuf_8_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_8_load"/></StgValue>
</operation>

<operation id="71" st_id="4" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:11  %linebuf_9_load = load i32* %linebuf_9_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_9_load"/></StgValue>
</operation>

<operation id="72" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="131" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  br i1 %icmp_ln197, label %5, label %VConvW_end

]]></Node>
<StgValue><ssdm name="br_ln197"/></StgValue>
</operation>

<operation id="73" st_id="4" stage="1" lat="1">
<core>FIFO</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
<literal name="icmp_ln197" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="133" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
:0  call void @_ssdm_op_Write.ap_fifo.volatile.i32P(i32* %vconv_V, i32 %tmp)

]]></Node>
<StgValue><ssdm name="write_ln198"/></StgValue>
</operation>

<operation id="74" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
<literal name="icmp_ln197" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="134" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %VConvW_end

]]></Node>
<StgValue><ssdm name="br_ln198"/></StgValue>
</operation>

<operation id="75" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="136" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32">
<![CDATA[
VConvW_end:0  %empty_16 = call i32 (...)* @_ssdm_op_SpecRegionEnd([7 x i8]* @p_str18, i32 %tmp_15_i_i)

]]></Node>
<StgValue><ssdm name="empty_16"/></StgValue>
</operation>

<operation id="76" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln191" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="137" bw="0" op_0_bw="0">
<![CDATA[
VConvW_end:1  br label %0

]]></Node>
<StgValue><ssdm name="br_ln186"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="77" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:2  %linebuf_0_load = load i32* %linebuf_0_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_0_load"/></StgValue>
</operation>

<operation id="78" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="75" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:3  %linebuf_1_load = load i32* %linebuf_1_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_1_load"/></StgValue>
</operation>

<operation id="79" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:4  %linebuf_2_load = load i32* %linebuf_2_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_2_load"/></StgValue>
</operation>

<operation id="80" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="77" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:5  %linebuf_3_load = load i32* %linebuf_3_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_3_load"/></StgValue>
</operation>

<operation id="81" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:6  %linebuf_4_load = load i32* %linebuf_4_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_4_load"/></StgValue>
</operation>

<operation id="82" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:7  %linebuf_5_load = load i32* %linebuf_5_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_5_load"/></StgValue>
</operation>

<operation id="83" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:8  %linebuf_6_load = load i32* %linebuf_6_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_6_load"/></StgValue>
</operation>

<operation id="84" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="81" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:9  %linebuf_7_load = load i32* %linebuf_7_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_7_load"/></StgValue>
</operation>

<operation id="85" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="82" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:10  %linebuf_8_load = load i32* %linebuf_8_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_8_load"/></StgValue>
</operation>

<operation id="86" st_id="5" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="83" bw="32" op_0_bw="11">
<![CDATA[
_ifconv:11  %linebuf_9_load = load i32* %linebuf_9_addr, align 4

]]></Node>
<StgValue><ssdm name="linebuf_9_load"/></StgValue>
</operation>

<operation id="87" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="4">
<![CDATA[
_ifconv:14  %zext_ln193 = zext i4 %i5_0_i_i_i to i64

]]></Node>
<StgValue><ssdm name="zext_ln193"/></StgValue>
</operation>

<operation id="88" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="87" bw="4" op_0_bw="10" op_1_bw="64" op_2_bw="64">
<![CDATA[
_ifconv:15  %filt11_coeff_addr = getelementptr [11 x i10]* @filt11_coeff, i64 0, i64 %zext_ln193

]]></Node>
<StgValue><ssdm name="filt11_coeff_addr"/></StgValue>
</operation>

<operation id="89" st_id="5" stage="2" lat="2">
<core>ROM_nP</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="88" bw="10" op_0_bw="4">
<![CDATA[
_ifconv:16  %filt11_coeff_load = load i10* %filt11_coeff_addr, align 2

]]></Node>
<StgValue><ssdm name="filt11_coeff_load"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="90" st_id="6" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="73" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
_ifconv:1  %icmp_ln192 = icmp ult i4 %i5_0_i_i_i, -6

]]></Node>
<StgValue><ssdm name="icmp_ln192"/></StgValue>
</operation>

<operation id="91" st_id="6" stage="1" lat="1">
<core>MuxnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="84" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32" op_9_bw="32" op_10_bw="32" op_11_bw="4">
<![CDATA[
_ifconv:12  %tmp_4 = call i32 @_ssdm_op_Mux.ap_auto.10i32.i4(i32 %linebuf_0_load, i32 %linebuf_1_load, i32 %linebuf_2_load, i32 %linebuf_3_load, i32 %linebuf_4_load, i32 %linebuf_5_load, i32 %linebuf_6_load, i32 %linebuf_7_load, i32 %linebuf_8_load, i32 %linebuf_9_load, i4 %i5_0_i_i_i)

]]></Node>
<StgValue><ssdm name="tmp_4"/></StgValue>
</operation>

<operation id="92" st_id="6" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="85" bw="32" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
_ifconv:13  %vwin_val = select i1 %icmp_ln192, i32 %tmp_4, i32 %tmp_1

]]></Node>
<StgValue><ssdm name="vwin_val"/></StgValue>
</operation>

<operation id="93" st_id="6" stage="1" lat="2">
<core>ROM_nP</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="88" bw="10" op_0_bw="4">
<![CDATA[
_ifconv:16  %filt11_coeff_load = load i10* %filt11_coeff_addr, align 2

]]></Node>
<StgValue><ssdm name="filt11_coeff_load"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="94" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="89" bw="32" op_0_bw="10">
<![CDATA[
_ifconv:17  %zext_ln193_1 = zext i10 %filt11_coeff_load to i32

]]></Node>
<StgValue><ssdm name="zext_ln193_1"/></StgValue>
</operation>

<operation id="95" st_id="7" stage="3" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
_ifconv:18  %mul_ln193 = mul i32 %vwin_val, %zext_ln193_1

]]></Node>
<StgValue><ssdm name="mul_ln193"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="96" st_id="8" stage="2" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
_ifconv:18  %mul_ln193 = mul i32 %vwin_val, %zext_ln193_1

]]></Node>
<StgValue><ssdm name="mul_ln193"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="97" st_id="9" stage="1" lat="3">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
_ifconv:18  %mul_ln193 = mul i32 %vwin_val, %zext_ln193_1

]]></Node>
<StgValue><ssdm name="mul_ln193"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="98" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
_ifconv:0  call void (...)* @_ssdm_op_SpecLoopName([6 x i8]* @p_str19) nounwind

]]></Node>
<StgValue><ssdm name="specloopname_ln191"/></StgValue>
</operation>

<operation id="99" st_id="10" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
_ifconv:19  %out_val = add i32 %mul_ln193, %tmp

]]></Node>
<StgValue><ssdm name="out_val"/></StgValue>
</operation>

<operation id="100" st_id="10" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="92" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
_ifconv:20  %icmp_ln194 = icmp eq i4 %i5_0_i_i_i, 0

]]></Node>
<StgValue><ssdm name="icmp_ln194"/></StgValue>
</operation>

<operation id="101" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="93" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
_ifconv:21  br i1 %icmp_ln194, label %._crit_edge4.i.i.i, label %4

]]></Node>
<StgValue><ssdm name="br_ln194"/></StgValue>
</operation>

<operation id="102" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="0" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0" op_4_bw="4" op_5_bw="0" op_6_bw="4" op_7_bw="0" op_8_bw="4" op_9_bw="0" op_10_bw="4" op_11_bw="0" op_12_bw="4" op_13_bw="0" op_14_bw="4" op_15_bw="0" op_16_bw="4" op_17_bw="0" op_18_bw="4" op_19_bw="0">
<![CDATA[
:0  switch i4 %i5_0_i_i_i, label %branch9.i.i [
    i4 1, label %branch0.i.i
    i4 2, label %branch1.i.i
    i4 3, label %branch2.i.i
    i4 4, label %branch3.i.i
    i4 5, label %branch4.i.i
    i4 6, label %branch5.i.i
    i4 7, label %branch6.i.i
    i4 -8, label %branch7.i.i
    i4 -7, label %branch8.i.i
  ]

]]></Node>
<StgValue><ssdm name="switch_ln195"/></StgValue>
</operation>

<operation id="103" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="-7"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch8.i.i:0  store i32 %vwin_val, i32* %linebuf_8_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="104" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="-7"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="0" op_0_bw="0">
<![CDATA[
branch8.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="105" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="-8"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch7.i.i:0  store i32 %vwin_val, i32* %linebuf_7_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="106" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="-8"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="0" op_0_bw="0">
<![CDATA[
branch7.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="107" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="7"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch6.i.i:0  store i32 %vwin_val, i32* %linebuf_6_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="108" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="7"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="0" op_0_bw="0">
<![CDATA[
branch6.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="109" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="6"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch5.i.i:0  store i32 %vwin_val, i32* %linebuf_5_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="110" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="6"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="0" op_0_bw="0">
<![CDATA[
branch5.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="111" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="5"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch4.i.i:0  store i32 %vwin_val, i32* %linebuf_4_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="112" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="5"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="0" op_0_bw="0">
<![CDATA[
branch4.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="113" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="4"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch3.i.i:0  store i32 %vwin_val, i32* %linebuf_3_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="114" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="4"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="0" op_0_bw="0">
<![CDATA[
branch3.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="115" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="3"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch2.i.i:0  store i32 %vwin_val, i32* %linebuf_2_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="116" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="3"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="0" op_0_bw="0">
<![CDATA[
branch2.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="117" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="2"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch1.i.i:0  store i32 %vwin_val, i32* %linebuf_1_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="118" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="2"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="0" op_0_bw="0">
<![CDATA[
branch1.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="119" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="121" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch0.i.i:0  store i32 %vwin_val, i32* %linebuf_0_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="120" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="0" op_0_bw="0">
<![CDATA[
branch0.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="121" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="!1"/>
<literal name="i5_0_i_i_i" val="!2"/>
<literal name="i5_0_i_i_i" val="!3"/>
<literal name="i5_0_i_i_i" val="!4"/>
<literal name="i5_0_i_i_i" val="!5"/>
<literal name="i5_0_i_i_i" val="!6"/>
<literal name="i5_0_i_i_i" val="!7"/>
<literal name="i5_0_i_i_i" val="!8"/>
<literal name="i5_0_i_i_i" val="!9"/>
</and_exp></or_exp>
</condition>

<Node id="124" bw="0" op_0_bw="32" op_1_bw="11" op_2_bw="32">
<![CDATA[
branch9.i.i:0  store i32 %vwin_val, i32* %linebuf_9_addr, align 4

]]></Node>
<StgValue><ssdm name="store_ln195"/></StgValue>
</operation>

<operation id="122" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
<literal name="i5_0_i_i_i" val="!1"/>
<literal name="i5_0_i_i_i" val="!2"/>
<literal name="i5_0_i_i_i" val="!3"/>
<literal name="i5_0_i_i_i" val="!4"/>
<literal name="i5_0_i_i_i" val="!5"/>
<literal name="i5_0_i_i_i" val="!6"/>
<literal name="i5_0_i_i_i" val="!7"/>
<literal name="i5_0_i_i_i" val="!8"/>
<literal name="i5_0_i_i_i" val="!9"/>
</and_exp></or_exp>
</condition>

<Node id="125" bw="0" op_0_bw="0">
<![CDATA[
branch9.i.i:1  br label %3

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="123" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln194" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="127" bw="0" op_0_bw="0">
<![CDATA[
:0  br label %._crit_edge4.i.i.i

]]></Node>
<StgValue><ssdm name="br_ln195"/></StgValue>
</operation>

<operation id="124" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="129" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge4.i.i.i:0  br label %2

]]></Node>
<StgValue><ssdm name="br_ln191"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
