<stg><name>mat_mul.1</name>


<trans_list>

<trans id="178" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="179" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="3" to="11">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="233" from="3" to="4">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="225" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="227" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="228" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="229" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="230" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="231" from="10" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="190" from="11" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="242" from="12" to="20">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="243" from="12" to="13">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="235" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="236" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="237" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="238" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="239" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="240" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="241" from="19" to="12">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="201" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="252" from="21" to="29">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="253" from="21" to="22">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="245" from="22" to="23">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="246" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="247" from="24" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="248" from="25" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="249" from="26" to="27">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="250" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="251" from="28" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="212" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="262" from="30" to="38">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="263" from="30" to="31">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="255" from="31" to="32">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="256" from="32" to="33">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="257" from="33" to="34">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="258" from="34" to="35">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="259" from="35" to="36">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="260" from="36" to="37">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="261" from="37" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="223" from="38" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="39" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph7:0 %br_ln66 = br void

]]></Node>
<StgValue><ssdm name="br_ln66"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="40" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0 %i_0 = phi i6 %add_ln66, void %._crit_edge.loopexit.3, i6 0, void %.lr.ph7

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="41" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:1 %icmp_ln66 = icmp_eq  i6 %i_0, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln66"/></StgValue>
</operation>

<operation id="42" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:2 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 8, i64 8, i64 8

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="43" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:3 %br_ln66 = br i1 %icmp_ln66, void %.split2.0, void %._crit_edge8.loopexit

]]></Node>
<StgValue><ssdm name="br_ln66"/></StgValue>
</operation>

<operation id="44" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="6">
<![CDATA[
.split2.0:0 %zext_ln66 = zext i6 %i_0

]]></Node>
<StgValue><ssdm name="zext_ln66"/></StgValue>
</operation>

<operation id="45" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="13" bw="5" op_0_bw="6">
<![CDATA[
.split2.0:1 %trunc_ln66 = trunc i6 %i_0

]]></Node>
<StgValue><ssdm name="trunc_ln66"/></StgValue>
</operation>

<operation id="46" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="14" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split2.0:2 %specloopname_ln66 = specloopname void @_ssdm_op_SpecLoopName, void @empty_2

]]></Node>
<StgValue><ssdm name="specloopname_ln66"/></StgValue>
</operation>

<operation id="47" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="0">
<![CDATA[
.split2.0:3 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="48" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln66" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="130" bw="0">
<![CDATA[
._crit_edge8.loopexit:0 %ret_ln76 = ret

]]></Node>
<StgValue><ssdm name="ret_ln76"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="49" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0 %j_0 = phi i6 %add_ln70, void %.split.0, i6 0, void %.split2.0

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="50" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_0 = phi i32 %tmp_7, void %.split.0, i32 0, void %.split2.0

]]></Node>
<StgValue><ssdm name="sum_0"/></StgValue>
</operation>

<operation id="51" st_id="3" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:2 %add_ln70 = add i6 %j_0, i6 1

]]></Node>
<StgValue><ssdm name="add_ln70"/></StgValue>
</operation>

<operation id="52" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="53" st_id="3" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:4 %icmp_ln70 = icmp_eq  i6 %j_0, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln70"/></StgValue>
</operation>

<operation id="54" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_91 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 32, i64 32, i64 32

]]></Node>
<StgValue><ssdm name="empty_91"/></StgValue>
</operation>

<operation id="55" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70, void %.split.0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="56" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="64" op_0_bw="6">
<![CDATA[
.split.0:0 %j_0_cast3 = zext i6 %j_0

]]></Node>
<StgValue><ssdm name="j_0_cast3"/></StgValue>
</operation>

<operation id="57" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="27" bw="4" op_0_bw="4" op_1_bw="6" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.0:2 %tmp = partselect i4 @_ssdm_op_PartSelect.i4.i6.i32.i32, i6 %i_0, i32 1, i32 4

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="58" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="28" bw="10" op_0_bw="10" op_1_bw="4" op_2_bw="6">
<![CDATA[
.split.0:3 %add_ln = bitconcatenate i10 @_ssdm_op_BitConcatenate.i10.i4.i6, i4 %tmp, i6 %j_0

]]></Node>
<StgValue><ssdm name="add_ln"/></StgValue>
</operation>

<operation id="59" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="64" op_0_bw="10">
<![CDATA[
.split.0:4 %zext_ln72 = zext i10 %add_ln

]]></Node>
<StgValue><ssdm name="zext_ln72"/></StgValue>
</operation>

<operation id="60" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="30" bw="10" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0:5 %layer8_weights_addr = getelementptr i32 %layer8_weights, i64 0, i64 %zext_ln72

]]></Node>
<StgValue><ssdm name="layer8_weights_addr"/></StgValue>
</operation>

<operation id="61" st_id="3" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="32" op_0_bw="10">
<![CDATA[
.split.0:6 %layer8_weights_load = load i10 %layer8_weights_addr

]]></Node>
<StgValue><ssdm name="layer8_weights_load"/></StgValue>
</operation>

<operation id="62" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="32" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0:7 %input_addr = getelementptr i32 %input_r, i64 0, i64 %j_0_cast3

]]></Node>
<StgValue><ssdm name="input_addr"/></StgValue>
</operation>

<operation id="63" st_id="3" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="11">
<![CDATA[
.split.0:8 %input_load = load i11 %input_addr

]]></Node>
<StgValue><ssdm name="input_load"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="64" st_id="4" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="32" op_0_bw="10">
<![CDATA[
.split.0:6 %layer8_weights_load = load i10 %layer8_weights_addr

]]></Node>
<StgValue><ssdm name="layer8_weights_load"/></StgValue>
</operation>

<operation id="65" st_id="4" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="11">
<![CDATA[
.split.0:8 %input_load = load i11 %input_addr

]]></Node>
<StgValue><ssdm name="input_load"/></StgValue>
</operation>

<operation id="66" st_id="4" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:9 %mul4 = fmul i32 %layer8_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="67" st_id="5" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:9 %mul4 = fmul i32 %layer8_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="68" st_id="6" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:9 %mul4 = fmul i32 %layer8_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="69" st_id="7" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:9 %mul4 = fmul i32 %layer8_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="70" st_id="8" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="35" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split.0:10 %icmp_ln72 = icmp_eq  i6 %add_ln70, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln72"/></StgValue>
</operation>

<operation id="71" st_id="8" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:11 %tmp_7 = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="72" st_id="9" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:11 %tmp_7 = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="73" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.0:1 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="74" st_id="10" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="36" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:11 %tmp_7 = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>

<operation id="75" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0">
<![CDATA[
.split.0:12 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="76" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.0:0 %output_addr = getelementptr i32 %output_r, i64 0, i64 %zext_ln66

]]></Node>
<StgValue><ssdm name="output_addr"/></StgValue>
</operation>

<operation id="77" st_id="11" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.0:1 %store_ln74 = store i32 %sum_0, i11 %output_addr

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="78" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
._crit_edge.loopexit.0:2 %or_ln66 = or i5 %trunc_ln66, i5 1

]]></Node>
<StgValue><ssdm name="or_ln66"/></StgValue>
</operation>

<operation id="79" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="64" op_0_bw="5">
<![CDATA[
._crit_edge.loopexit.0:3 %or_ln66_cast4 = zext i5 %or_ln66

]]></Node>
<StgValue><ssdm name="or_ln66_cast4"/></StgValue>
</operation>

<operation id="80" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="10" op_0_bw="10" op_1_bw="5" op_2_bw="5">
<![CDATA[
._crit_edge.loopexit.0:4 %tmp_3 = bitconcatenate i10 @_ssdm_op_BitConcatenate.i10.i5.i5, i5 %or_ln66, i5 0

]]></Node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="81" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.0:5 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="82" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0 %j_1 = phi i6 %add_ln70_1, void %.split.1, i6 0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="j_1"/></StgValue>
</operation>

<operation id="83" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_19 = phi i32 %tmp_8, void %.split.1, i32 0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="sum_19"/></StgValue>
</operation>

<operation id="84" st_id="12" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:2 %add_ln70_1 = add i6 %j_1, i6 1

]]></Node>
<StgValue><ssdm name="add_ln70_1"/></StgValue>
</operation>

<operation id="85" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="86" st_id="12" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:4 %icmp_ln70_1 = icmp_eq  i6 %j_1, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln70_1"/></StgValue>
</operation>

<operation id="87" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_92 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 32, i64 32, i64 32

]]></Node>
<StgValue><ssdm name="empty_92"/></StgValue>
</operation>

<operation id="88" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="52" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70_1, void %.split.1, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="89" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="64" op_0_bw="6">
<![CDATA[
.split.1:0 %j_1_cast5 = zext i6 %j_1

]]></Node>
<StgValue><ssdm name="j_1_cast5"/></StgValue>
</operation>

<operation id="90" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="10" op_0_bw="6">
<![CDATA[
.split.1:1 %j_1_cast = zext i6 %j_1

]]></Node>
<StgValue><ssdm name="j_1_cast"/></StgValue>
</operation>

<operation id="91" st_id="12" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="10" op_0_bw="10" op_1_bw="10">
<![CDATA[
.split.1:3 %add_ln72 = add i10 %j_1_cast, i10 %tmp_3

]]></Node>
<StgValue><ssdm name="add_ln72"/></StgValue>
</operation>

<operation id="92" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="64" op_0_bw="10">
<![CDATA[
.split.1:4 %zext_ln72_4 = zext i10 %add_ln72

]]></Node>
<StgValue><ssdm name="zext_ln72_4"/></StgValue>
</operation>

<operation id="93" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="10" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1:5 %layer8_weights_addr_1 = getelementptr i32 %layer8_weights, i64 0, i64 %zext_ln72_4

]]></Node>
<StgValue><ssdm name="layer8_weights_addr_1"/></StgValue>
</operation>

<operation id="94" st_id="12" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="32" op_0_bw="10">
<![CDATA[
.split.1:6 %layer8_weights_load_1 = load i10 %layer8_weights_addr_1

]]></Node>
<StgValue><ssdm name="layer8_weights_load_1"/></StgValue>
</operation>

<operation id="95" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1:7 %input_addr_5 = getelementptr i32 %input_r, i64 0, i64 %j_1_cast5

]]></Node>
<StgValue><ssdm name="input_addr_5"/></StgValue>
</operation>

<operation id="96" st_id="12" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="32" op_0_bw="11">
<![CDATA[
.split.1:8 %input_load_1 = load i11 %input_addr_5

]]></Node>
<StgValue><ssdm name="input_load_1"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="97" st_id="13" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="32" op_0_bw="10">
<![CDATA[
.split.1:6 %layer8_weights_load_1 = load i10 %layer8_weights_addr_1

]]></Node>
<StgValue><ssdm name="layer8_weights_load_1"/></StgValue>
</operation>

<operation id="98" st_id="13" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="32" op_0_bw="11">
<![CDATA[
.split.1:8 %input_load_1 = load i11 %input_addr_5

]]></Node>
<StgValue><ssdm name="input_load_1"/></StgValue>
</operation>

<operation id="99" st_id="13" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:9 %mul4_1 = fmul i32 %layer8_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="100" st_id="14" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:9 %mul4_1 = fmul i32 %layer8_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="101" st_id="15" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:9 %mul4_1 = fmul i32 %layer8_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="102" st_id="16" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:9 %mul4_1 = fmul i32 %layer8_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="103" st_id="17" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split.1:10 %icmp_ln72_5 = icmp_eq  i6 %add_ln70_1, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln72_5"/></StgValue>
</operation>

<operation id="104" st_id="17" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:11 %tmp_8 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_5

]]></Node>
<StgValue><ssdm name="tmp_8"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="105" st_id="18" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:11 %tmp_8 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_5

]]></Node>
<StgValue><ssdm name="tmp_8"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="106" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.1:2 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="107" st_id="19" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:11 %tmp_8 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_5

]]></Node>
<StgValue><ssdm name="tmp_8"/></StgValue>
</operation>

<operation id="108" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="0" op_0_bw="0">
<![CDATA[
.split.1:12 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="109" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="68" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.1:0 %output_addr_6 = getelementptr i32 %output_r, i64 0, i64 %or_ln66_cast4

]]></Node>
<StgValue><ssdm name="output_addr_6"/></StgValue>
</operation>

<operation id="110" st_id="20" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="69" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.1:1 %store_ln74 = store i32 %sum_19, i11 %output_addr_6

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="111" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="70" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
._crit_edge.loopexit.1:2 %or_ln66_3 = or i5 %trunc_ln66, i5 2

]]></Node>
<StgValue><ssdm name="or_ln66_3"/></StgValue>
</operation>

<operation id="112" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="71" bw="64" op_0_bw="5">
<![CDATA[
._crit_edge.loopexit.1:3 %or_ln66_5_cast6 = zext i5 %or_ln66_3

]]></Node>
<StgValue><ssdm name="or_ln66_5_cast6"/></StgValue>
</operation>

<operation id="113" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="72" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.1:4 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="114" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="74" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0 %j_2 = phi i6 %add_ln70_2, void %.split.2, i6 0, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="j_2"/></StgValue>
</operation>

<operation id="115" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="75" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_2 = phi i32 %tmp_9, void %.split.2, i32 0, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="sum_2"/></StgValue>
</operation>

<operation id="116" st_id="21" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="76" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:2 %add_ln70_2 = add i6 %j_2, i6 1

]]></Node>
<StgValue><ssdm name="add_ln70_2"/></StgValue>
</operation>

<operation id="117" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="77" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="118" st_id="21" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="78" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:4 %icmp_ln70_2 = icmp_eq  i6 %j_2, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln70_2"/></StgValue>
</operation>

<operation id="119" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="79" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_93 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 32, i64 32, i64 32

]]></Node>
<StgValue><ssdm name="empty_93"/></StgValue>
</operation>

<operation id="120" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="80" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70_2, void %.split.2, void %._crit_edge.loopexit.2

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="121" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="64" op_0_bw="6">
<![CDATA[
.split.2:0 %j_2_cast7 = zext i6 %j_2

]]></Node>
<StgValue><ssdm name="j_2_cast7"/></StgValue>
</operation>

<operation id="122" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="4" op_0_bw="4" op_1_bw="5" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.2:2 %tmp_s = partselect i4 @_ssdm_op_PartSelect.i4.i5.i32.i32, i5 %or_ln66_3, i32 1, i32 4

]]></Node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="123" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="10" op_0_bw="10" op_1_bw="4" op_2_bw="6">
<![CDATA[
.split.2:3 %add_ln72_8 = bitconcatenate i10 @_ssdm_op_BitConcatenate.i10.i4.i6, i4 %tmp_s, i6 %j_2

]]></Node>
<StgValue><ssdm name="add_ln72_8"/></StgValue>
</operation>

<operation id="124" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="64" op_0_bw="10">
<![CDATA[
.split.2:4 %zext_ln72_5 = zext i10 %add_ln72_8

]]></Node>
<StgValue><ssdm name="zext_ln72_5"/></StgValue>
</operation>

<operation id="125" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="10" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2:5 %layer8_weights_addr_2 = getelementptr i32 %layer8_weights, i64 0, i64 %zext_ln72_5

]]></Node>
<StgValue><ssdm name="layer8_weights_addr_2"/></StgValue>
</operation>

<operation id="126" st_id="21" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="32" op_0_bw="10">
<![CDATA[
.split.2:6 %layer8_weights_load_2 = load i10 %layer8_weights_addr_2

]]></Node>
<StgValue><ssdm name="layer8_weights_load_2"/></StgValue>
</operation>

<operation id="127" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2:7 %input_addr_6 = getelementptr i32 %input_r, i64 0, i64 %j_2_cast7

]]></Node>
<StgValue><ssdm name="input_addr_6"/></StgValue>
</operation>

<operation id="128" st_id="21" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="11">
<![CDATA[
.split.2:8 %input_load_2 = load i11 %input_addr_6

]]></Node>
<StgValue><ssdm name="input_load_2"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="129" st_id="22" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="32" op_0_bw="10">
<![CDATA[
.split.2:6 %layer8_weights_load_2 = load i10 %layer8_weights_addr_2

]]></Node>
<StgValue><ssdm name="layer8_weights_load_2"/></StgValue>
</operation>

<operation id="130" st_id="22" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="32" op_0_bw="11">
<![CDATA[
.split.2:8 %input_load_2 = load i11 %input_addr_6

]]></Node>
<StgValue><ssdm name="input_load_2"/></StgValue>
</operation>

<operation id="131" st_id="22" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2:9 %mul4_2 = fmul i32 %layer8_weights_load_2, i32 %input_load_2

]]></Node>
<StgValue><ssdm name="mul4_2"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="132" st_id="23" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2:9 %mul4_2 = fmul i32 %layer8_weights_load_2, i32 %input_load_2

]]></Node>
<StgValue><ssdm name="mul4_2"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="133" st_id="24" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2:9 %mul4_2 = fmul i32 %layer8_weights_load_2, i32 %input_load_2

]]></Node>
<StgValue><ssdm name="mul4_2"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="134" st_id="25" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2:9 %mul4_2 = fmul i32 %layer8_weights_load_2, i32 %input_load_2

]]></Node>
<StgValue><ssdm name="mul4_2"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="135" st_id="26" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split.2:10 %icmp_ln72_6 = icmp_eq  i6 %add_ln70_2, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln72_6"/></StgValue>
</operation>

<operation id="136" st_id="26" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.2:11 %tmp_9 = facc i32 @_ssdm_op_FACC, i32 %mul4_2, i1 %icmp_ln72_6

]]></Node>
<StgValue><ssdm name="tmp_9"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="137" st_id="27" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.2:11 %tmp_9 = facc i32 @_ssdm_op_FACC, i32 %mul4_2, i1 %icmp_ln72_6

]]></Node>
<StgValue><ssdm name="tmp_9"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="138" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.2:1 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="139" st_id="28" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.2:11 %tmp_9 = facc i32 @_ssdm_op_FACC, i32 %mul4_2, i1 %icmp_ln72_6

]]></Node>
<StgValue><ssdm name="tmp_9"/></StgValue>
</operation>

<operation id="140" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="0" op_0_bw="0">
<![CDATA[
.split.2:12 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="141" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="96" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.2:0 %output_addr_7 = getelementptr i32 %output_r, i64 0, i64 %or_ln66_5_cast6

]]></Node>
<StgValue><ssdm name="output_addr_7"/></StgValue>
</operation>

<operation id="142" st_id="29" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="97" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.2:1 %store_ln74 = store i32 %sum_2, i11 %output_addr_7

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="143" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="98" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
._crit_edge.loopexit.2:2 %or_ln66_4 = or i5 %trunc_ln66, i5 3

]]></Node>
<StgValue><ssdm name="or_ln66_4"/></StgValue>
</operation>

<operation id="144" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="99" bw="64" op_0_bw="5">
<![CDATA[
._crit_edge.loopexit.2:3 %or_ln66_6_cast8 = zext i5 %or_ln66_4

]]></Node>
<StgValue><ssdm name="or_ln66_6_cast8"/></StgValue>
</operation>

<operation id="145" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="100" bw="10" op_0_bw="10" op_1_bw="5" op_2_bw="5">
<![CDATA[
._crit_edge.loopexit.2:4 %tmp_4 = bitconcatenate i10 @_ssdm_op_BitConcatenate.i10.i5.i5, i5 %or_ln66_4, i5 0

]]></Node>
<StgValue><ssdm name="tmp_4"/></StgValue>
</operation>

<operation id="146" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="101" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.2:5 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="147" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="103" bw="6" op_0_bw="6" op_1_bw="0" op_2_bw="6" op_3_bw="0">
<![CDATA[
:0 %j_3 = phi i6 %add_ln70_3, void %.split.3, i6 0, void %._crit_edge.loopexit.2

]]></Node>
<StgValue><ssdm name="j_3"/></StgValue>
</operation>

<operation id="148" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="104" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_3 = phi i32 %tmp_10, void %.split.3, i32 0, void %._crit_edge.loopexit.2

]]></Node>
<StgValue><ssdm name="sum_3"/></StgValue>
</operation>

<operation id="149" st_id="30" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="105" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
:2 %add_ln70_3 = add i6 %j_3, i6 1

]]></Node>
<StgValue><ssdm name="add_ln70_3"/></StgValue>
</operation>

<operation id="150" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="106" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="151" st_id="30" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="107" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
:4 %icmp_ln70_3 = icmp_eq  i6 %j_3, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln70_3"/></StgValue>
</operation>

<operation id="152" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="108" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_94 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 32, i64 32, i64 32

]]></Node>
<StgValue><ssdm name="empty_94"/></StgValue>
</operation>

<operation id="153" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="109" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70_3, void %.split.3, void %._crit_edge.loopexit.3

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="154" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="64" op_0_bw="6">
<![CDATA[
.split.3:0 %j_3_cast9 = zext i6 %j_3

]]></Node>
<StgValue><ssdm name="j_3_cast9"/></StgValue>
</operation>

<operation id="155" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="10" op_0_bw="6">
<![CDATA[
.split.3:1 %j_3_cast = zext i6 %j_3

]]></Node>
<StgValue><ssdm name="j_3_cast"/></StgValue>
</operation>

<operation id="156" st_id="30" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="10" op_0_bw="10" op_1_bw="10">
<![CDATA[
.split.3:3 %add_ln72_2 = add i10 %j_3_cast, i10 %tmp_4

]]></Node>
<StgValue><ssdm name="add_ln72_2"/></StgValue>
</operation>

<operation id="157" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="64" op_0_bw="10">
<![CDATA[
.split.3:4 %zext_ln72_6 = zext i10 %add_ln72_2

]]></Node>
<StgValue><ssdm name="zext_ln72_6"/></StgValue>
</operation>

<operation id="158" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="10" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3:5 %layer8_weights_addr_3 = getelementptr i32 %layer8_weights, i64 0, i64 %zext_ln72_6

]]></Node>
<StgValue><ssdm name="layer8_weights_addr_3"/></StgValue>
</operation>

<operation id="159" st_id="30" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="32" op_0_bw="10">
<![CDATA[
.split.3:6 %layer8_weights_load_3 = load i10 %layer8_weights_addr_3

]]></Node>
<StgValue><ssdm name="layer8_weights_load_3"/></StgValue>
</operation>

<operation id="160" st_id="30" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3:7 %input_addr_7 = getelementptr i32 %input_r, i64 0, i64 %j_3_cast9

]]></Node>
<StgValue><ssdm name="input_addr_7"/></StgValue>
</operation>

<operation id="161" st_id="30" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="32" op_0_bw="11">
<![CDATA[
.split.3:8 %input_load_3 = load i11 %input_addr_7

]]></Node>
<StgValue><ssdm name="input_load_3"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="162" st_id="31" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="32" op_0_bw="10">
<![CDATA[
.split.3:6 %layer8_weights_load_3 = load i10 %layer8_weights_addr_3

]]></Node>
<StgValue><ssdm name="layer8_weights_load_3"/></StgValue>
</operation>

<operation id="163" st_id="31" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="32" op_0_bw="11">
<![CDATA[
.split.3:8 %input_load_3 = load i11 %input_addr_7

]]></Node>
<StgValue><ssdm name="input_load_3"/></StgValue>
</operation>

<operation id="164" st_id="31" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3:9 %mul4_3 = fmul i32 %layer8_weights_load_3, i32 %input_load_3

]]></Node>
<StgValue><ssdm name="mul4_3"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">

<operation id="165" st_id="32" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3:9 %mul4_3 = fmul i32 %layer8_weights_load_3, i32 %input_load_3

]]></Node>
<StgValue><ssdm name="mul4_3"/></StgValue>
</operation>
</state>

<state id="33" st_id="33">

<operation id="166" st_id="33" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3:9 %mul4_3 = fmul i32 %layer8_weights_load_3, i32 %input_load_3

]]></Node>
<StgValue><ssdm name="mul4_3"/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="167" st_id="34" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3:9 %mul4_3 = fmul i32 %layer8_weights_load_3, i32 %input_load_3

]]></Node>
<StgValue><ssdm name="mul4_3"/></StgValue>
</operation>
</state>

<state id="35" st_id="35">

<operation id="168" st_id="35" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="121" bw="1" op_0_bw="6" op_1_bw="6">
<![CDATA[
.split.3:10 %icmp_ln72_7 = icmp_eq  i6 %add_ln70_3, i6 32

]]></Node>
<StgValue><ssdm name="icmp_ln72_7"/></StgValue>
</operation>

<operation id="169" st_id="35" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.3:11 %tmp_10 = facc i32 @_ssdm_op_FACC, i32 %mul4_3, i1 %icmp_ln72_7

]]></Node>
<StgValue><ssdm name="tmp_10"/></StgValue>
</operation>
</state>

<state id="36" st_id="36">

<operation id="170" st_id="36" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.3:11 %tmp_10 = facc i32 @_ssdm_op_FACC, i32 %mul4_3, i1 %icmp_ln72_7

]]></Node>
<StgValue><ssdm name="tmp_10"/></StgValue>
</operation>
</state>

<state id="37" st_id="37">

<operation id="171" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.3:2 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="172" st_id="37" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.3:11 %tmp_10 = facc i32 @_ssdm_op_FACC, i32 %mul4_3, i1 %icmp_ln72_7

]]></Node>
<StgValue><ssdm name="tmp_10"/></StgValue>
</operation>

<operation id="173" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="123" bw="0" op_0_bw="0">
<![CDATA[
.split.3:12 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="38" st_id="38">

<operation id="174" st_id="38" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="125" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
._crit_edge.loopexit.3:0 %add_ln66 = add i6 %i_0, i6 4

]]></Node>
<StgValue><ssdm name="add_ln66"/></StgValue>
</operation>

<operation id="175" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="126" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.3:1 %output_addr_8 = getelementptr i32 %output_r, i64 0, i64 %or_ln66_6_cast8

]]></Node>
<StgValue><ssdm name="output_addr_8"/></StgValue>
</operation>

<operation id="176" st_id="38" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="127" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.3:2 %store_ln74 = store i32 %sum_3, i11 %output_addr_8

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="177" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="128" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.3:3 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
