<stg><name>nfa_accept_samples_generic_hw</name>


<trans_list>

<trans id="148" from="1" to="2">
<condition id="58">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="149" from="2" to="3">
<condition id="59">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="150" from="3" to="4">
<condition id="60">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="151" from="4" to="5">
<condition id="62">
<or_exp><and_exp><literal name="tmp_i_11" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="152" from="4" to="34">
<condition id="61">
<or_exp><and_exp><literal name="tmp_i_11" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="154" from="5" to="6">
<condition id="64">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="155" from="6" to="7">
<condition id="65">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="156" from="7" to="8">
<condition id="66">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="157" from="8" to="9">
<condition id="67">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="158" from="9" to="10">
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="159" from="10" to="11">
<condition id="69">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="160" from="11" to="12">
<condition id="70">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="161" from="12" to="13">
<condition id="71">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="162" from="13" to="14">
<condition id="72">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="163" from="14" to="15">
<condition id="73">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="164" from="15" to="16">
<condition id="74">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="165" from="16" to="17">
<condition id="75">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="166" from="17" to="18">
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="167" from="18" to="26">
<condition id="77">
<or_exp><and_exp><literal name="or_cond" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="168" from="18" to="19">
<condition id="79">
<or_exp><and_exp><literal name="or_cond" val="0"/>
<literal name="stop_on_first_read" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="169" from="18" to="34">
<condition id="78">
<or_exp><and_exp><literal name="or_cond" val="0"/>
<literal name="stop_on_first_read" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="171" from="19" to="20">
<condition id="81">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="172" from="20" to="21">
<condition id="82">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="173" from="21" to="22">
<condition id="83">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="174" from="22" to="23">
<condition id="84">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="175" from="23" to="24">
<condition id="85">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="176" from="24" to="25">
<condition id="86">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="177" from="25" to="26">
<condition id="87">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="178" from="26" to="27">
<condition id="88">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="180" from="27" to="28">
<condition id="90">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="181" from="28" to="29">
<condition id="91">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="182" from="29" to="30">
<condition id="92">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="183" from="30" to="31">
<condition id="93">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="184" from="31" to="32">
<condition id="94">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="185" from="32" to="33">
<condition id="95">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="186" from="33" to="2">
<condition id="97">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="35" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="19" bw="32" op_0_bw="32">
<![CDATA[
:0  %c = alloca i32, align 4

]]></node>
<StgValue><ssdm name="c"/></StgValue>
</operation>

<operation id="36" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecBitsMap(i32* %nfa_initials_buckets), !map !27

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="37" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="21" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecBitsMap(i32* %nfa_finals_buckets), !map !33

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="38" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="22" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecBitsMap(i32* %nfa_forward_buckets), !map !37

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="39" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:4  call void (...)* @_ssdm_op_SpecBitsMap([32130 x i32]* %nfa_backward_buckets), !map !43

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="40" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:5  call void (...)* @_ssdm_op_SpecBitsMap(i8* %nfa_symbols), !map !47

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="41" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="25" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:6  call void (...)* @_ssdm_op_SpecBitsMap(i8* %sample_buffer), !map !53

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="42" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="26" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:7  call void (...)* @_ssdm_op_SpecBitsMap(i32 %sample_buffer_length), !map !59

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="43" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:8  call void (...)* @_ssdm_op_SpecBitsMap(i16 %sample_length), !map !65

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="44" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="28" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:9  call void (...)* @_ssdm_op_SpecBitsMap(i32* %indices_begin), !map !69

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="45" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:10  call void (...)* @_ssdm_op_SpecBitsMap(i16* %indices_samples), !map !75

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="46" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="30" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:11  call void (...)* @_ssdm_op_SpecBitsMap(i8* %indices_stride), !map !79

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="47" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="31" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:12  call void (...)* @_ssdm_op_SpecBitsMap(i16 %i_size), !map !83

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="48" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:13  call void (...)* @_ssdm_op_SpecBitsMap(i16 %begin_index), !map !87

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="49" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="33" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:14  call void (...)* @_ssdm_op_SpecBitsMap(i16 %begin_sample), !map !91

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="50" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="34" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:15  call void (...)* @_ssdm_op_SpecBitsMap(i16 %end_index), !map !95

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="51" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="0" op_0_bw="0" op_1_bw="16">
<![CDATA[
:16  call void (...)* @_ssdm_op_SpecBitsMap(i16 %end_sample), !map !99

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="52" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="36" bw="0" op_0_bw="0" op_1_bw="1">
<![CDATA[
:17  call void (...)* @_ssdm_op_SpecBitsMap(i1 %stop_on_first), !map !103

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="53" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="37" bw="0" op_0_bw="0" op_1_bw="1">
<![CDATA[
:18  call void (...)* @_ssdm_op_SpecBitsMap(i1 %accept), !map !107

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="54" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="38" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
:19  call void (...)* @_ssdm_op_SpecBitsMap(i32 0) nounwind, !map !111

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="55" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="39" bw="0" op_0_bw="0" op_1_bw="8">
<![CDATA[
:20  call void (...)* @_ssdm_op_SpecTopModule([30 x i8]* @str) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="56" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:21  %accept_read = call i1 @_ssdm_op_Read.ap_none.i1(i1 %accept)

]]></node>
<StgValue><ssdm name="accept_read"/></StgValue>
</operation>

<operation id="57" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="41" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:22  %stop_on_first_read = call i1 @_ssdm_op_Read.ap_none.i1(i1 %stop_on_first)

]]></node>
<StgValue><ssdm name="stop_on_first_read"/></StgValue>
</operation>

<operation id="58" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="42" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:23  %end_sample_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %end_sample)

]]></node>
<StgValue><ssdm name="end_sample_read"/></StgValue>
</operation>

<operation id="59" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="43" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:24  %end_index_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %end_index)

]]></node>
<StgValue><ssdm name="end_index_read"/></StgValue>
</operation>

<operation id="60" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="44" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:25  %begin_sample_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %begin_sample)

]]></node>
<StgValue><ssdm name="begin_sample_read"/></StgValue>
</operation>

<operation id="61" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="45" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:26  %begin_index_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %begin_index)

]]></node>
<StgValue><ssdm name="begin_index_read"/></StgValue>
</operation>

<operation id="62" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="46" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:27  %sample_length_read = call i16 @_ssdm_op_Read.ap_none.i16(i16 %sample_length)

]]></node>
<StgValue><ssdm name="sample_length_read"/></StgValue>
</operation>

<operation id="63" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="47" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:28  %sample_buffer_length_read = call i32 @_ssdm_op_Read.ap_none.i32(i32 %sample_buffer_length)

]]></node>
<StgValue><ssdm name="sample_buffer_length_read"/></StgValue>
</operation>

<operation id="64" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="48" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
:29  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="65" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="49" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:30  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_initials_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="66" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="50" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:31  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_finals_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="67" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="51" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:32  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_forward_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="68" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="52" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:33  call void (...)* @_ssdm_op_SpecWire(i8* %nfa_symbols, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="69" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="53" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:34  call void (...)* @_ssdm_op_SpecBus(i8* %sample_buffer, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="70" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="54" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:35  call void (...)* @_ssdm_op_SpecWire(i32 %sample_buffer_length, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="71" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="55" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:36  call void (...)* @_ssdm_op_SpecWire(i16 %sample_length, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="72" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="56" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="8">
<![CDATA[
:37  call void (...)* @_ssdm_op_SpecBus(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="73" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="57" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:38  call void (...)* @_ssdm_op_SpecWire(i16 %i_size, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="74" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="58" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8">
<![CDATA[
:39  call void (...)* @_ssdm_op_SpecWire(i16 %begin_index, i16 %begin_sample, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="75" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="59" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8">
<![CDATA[
:40  call void (...)* @_ssdm_op_SpecWire(i16 %end_index, i16 %end_sample, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="76" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="60" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:41  call void (...)* @_ssdm_op_SpecWire(i1 %stop_on_first, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="77" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="61" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:42  call void (...)* @_ssdm_op_SpecWire(i1 %accept, [8 x i8]* @p_str36, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="78" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="62" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:43  call void (...)* @_ssdm_op_SpecWire(i32 0, [11 x i8]* @p_str37, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="79" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="63" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:44  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_initials_buckets, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="80" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="64" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:45  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_finals_buckets, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="81" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="65" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:46  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_forward_buckets, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="82" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="66" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:47  call void (...)* @_ssdm_op_SpecIFCore(i8* %nfa_symbols, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="83" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="67" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:48  call void (...)* @_ssdm_op_SpecIFCore(i8* %sample_buffer, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="84" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="68" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:49  call void (...)* @_ssdm_op_SpecIFCore(i32 %sample_buffer_length, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="85" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="69" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:50  call void (...)* @_ssdm_op_SpecIFCore(i16 %sample_length, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="86" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="70" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8" op_9_bw="8">
<![CDATA[
:51  call void (...)* @_ssdm_op_SpecIFCore(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="87" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="71" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:52  call void (...)* @_ssdm_op_SpecIFCore(i16 %i_size, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="88" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="72" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:53  call void (...)* @_ssdm_op_SpecIFCore(i16 %begin_index, i16 %begin_sample, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="89" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="73" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:54  call void (...)* @_ssdm_op_SpecIFCore(i16 %end_index, i16 %end_sample, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="90" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="74" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:55  call void (...)* @_ssdm_op_SpecIFCore(i1 %stop_on_first, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="91" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="75" bw="0" op_0_bw="0" op_1_bw="1" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:56  call void (...)* @_ssdm_op_SpecIFCore(i1 %accept, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="92" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="76" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:57  call void (...)* @_ssdm_op_SpecIFCore(i32 0, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="93" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="77" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:58  store i32 0, i32* %c, align 4

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="94" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="78" bw="0" op_0_bw="0">
<![CDATA[
:59  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="95" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="80" bw="16" op_0_bw="16" op_1_bw="0">
<![CDATA[
:0  %i_index = phi i16 [ %begin_index_read, %0 ], [ %i_index_1, %._crit_edge3 ]

]]></node>
<StgValue><ssdm name="i_index"/></StgValue>
</operation>

<operation id="96" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="81" bw="16" op_0_bw="16" op_1_bw="0">
<![CDATA[
:1  %i_sample = phi i16 [ %begin_sample_read, %0 ], [ %i_sample_1, %._crit_edge3 ]

]]></node>
<StgValue><ssdm name="i_sample"/></StgValue>
</operation>

<operation id="97" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="1" op_0_bw="16" op_1_bw="16">
<![CDATA[
:4  %tmp_i = icmp eq i16 %i_sample, %end_sample_read

]]></node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="98" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="21">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="85" bw="1" op_0_bw="16" op_1_bw="16">
<![CDATA[
:5  %tmp_i_10 = icmp eq i16 %i_index, %end_index_read

]]></node>
<StgValue><ssdm name="tmp_i_10"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="99" st_id="3" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="22">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="86" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:6  %tmp_i_11 = and i1 %tmp_i, %tmp_i_10

]]></node>
<StgValue><ssdm name="tmp_i_11"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="100" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="23">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="82" bw="32" op_0_bw="32">
<![CDATA[
:2  %c_load = load i32* %c, align 4

]]></node>
<StgValue><ssdm name="c_load"/></StgValue>
</operation>

<operation id="101" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="23">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="83" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="16" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecIFCore(i16 %end_index, i16 %end_sample, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="102" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="23">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="87" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:7  br i1 %tmp_i_11, label %._crit_edge, label %2

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="103" st_id="4" stage="14" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="24">
<or_exp><and_exp><literal name="tmp_i_11" val="0"/>
</and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="104" st_id="5" stage="13" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="105" st_id="6" stage="12" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="26">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="106" st_id="7" stage="11" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="27">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="107" st_id="8" stage="10" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="28">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="108" st_id="9" stage="9" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="29">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="109" st_id="10" stage="8" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="30">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="110" st_id="11" stage="7" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="31">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="111" st_id="12" stage="6" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="32">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="112" st_id="13" stage="5" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="33">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="113" st_id="14" stage="4" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="34">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="114" st_id="15" stage="3" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="35">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="115" st_id="16" stage="2" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="36">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="116" st_id="17" stage="1" lat="14">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="37">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="32" op_0_bw="32" op_1_bw="16" op_2_bw="16" op_3_bw="32" op_4_bw="16" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:2  %offset = call fastcc i32 @sample_iterator_get_offset(i16 %i_index, i16 %i_sample, i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i32 %sample_buffer_length_read, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>

<operation id="117" st_id="17" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="37">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="92" bw="1" op_0_bw="1" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:3  %r = call fastcc i1 @nfa_accept_sample(i32* %nfa_initials_buckets, i32* %nfa_finals_buckets, i32* %nfa_forward_buckets, i8* %nfa_symbols, i8* %sample_buffer, i32 %offset, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="r"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="118" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="89" bw="32" op_0_bw="32" op_1_bw="8">
<![CDATA[
:0  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str41)

]]></node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="119" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="90" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 65535, i32 2000, [1 x i8]* @p_str1132) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="120" st_id="18" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="92" bw="1" op_0_bw="1" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8" op_5_bw="8" op_6_bw="32" op_7_bw="16">
<![CDATA[
:3  %r = call fastcc i1 @nfa_accept_sample(i32* %nfa_initials_buckets, i32* %nfa_finals_buckets, i32* %nfa_forward_buckets, i8* %nfa_symbols, i8* %sample_buffer, i32 %offset, i16 %sample_length_read)

]]></node>
<StgValue><ssdm name="r"/></StgValue>
</operation>

<operation id="121" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="93" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
:4  %or_cond = xor i1 %r, %accept_read

]]></node>
<StgValue><ssdm name="or_cond"/></StgValue>
</operation>

<operation id="122" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="94" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5  br i1 %or_cond, label %._crit_edge3, label %3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="123" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp><literal name="or_cond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="96" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  br i1 %stop_on_first_read, label %._crit_edge, label %4

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="124" st_id="18" stage="8" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp><literal name="or_cond" val="0"/>
<literal name="stop_on_first_read" val="0"/>
</and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="125" st_id="19" stage="7" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="41">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="126" st_id="20" stage="6" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="42">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="127" st_id="21" stage="5" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="43">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="128" st_id="22" stage="4" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="44">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="129" st_id="23" stage="3" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="45">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="130" st_id="24" stage="2" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="46">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="131" st_id="25" stage="1" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %c_1 = add nsw i32 %c_load, 1

]]></node>
<StgValue><ssdm name="c_1"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="132" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="48">
<or_exp><and_exp><literal name="or_cond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="99" bw="0" op_0_bw="32" op_1_bw="32">
<![CDATA[
:1  store i32 %c_1, i32* %c, align 4

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="133" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="48">
<or_exp><and_exp><literal name="or_cond" val="0"/>
</and_exp></or_exp>
</condition>

<node id="100" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %._crit_edge3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="134" st_id="26" stage="8" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="49">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="135" st_id="27" stage="7" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="50">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="136" st_id="28" stage="6" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="51">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="137" st_id="29" stage="5" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="52">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="138" st_id="30" stage="4" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="53">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="139" st_id="31" stage="3" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="54">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">

<operation id="140" st_id="32" stage="2" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="55">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>
</state>

<state id="33" st_id="33">

<operation id="141" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="102" bw="32" op_0_bw="32" op_1_bw="8" op_2_bw="32">
<![CDATA[
._crit_edge3:0  %empty = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str41, i32 %tmp)

]]></node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="142" st_id="33" stage="1" lat="8">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="16" op_3_bw="8" op_4_bw="16" op_5_bw="16">
<![CDATA[
._crit_edge3:1  %call_ret = call fastcc { i16, i16 } @sample_iterator_next(i32* %indices_begin, i16* %indices_samples, i8* %indices_stride, i16 %i_index, i16 %i_sample)

]]></node>
<StgValue><ssdm name="call_ret"/></StgValue>
</operation>

<operation id="143" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="104" bw="16" op_0_bw="32">
<![CDATA[
._crit_edge3:2  %i_index_1 = extractvalue { i16, i16 } %call_ret, 0

]]></node>
<StgValue><ssdm name="i_index_1"/></StgValue>
</operation>

<operation id="144" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="105" bw="16" op_0_bw="32">
<![CDATA[
._crit_edge3:3  %i_sample_1 = extractvalue { i16, i16 } %call_ret, 1

]]></node>
<StgValue><ssdm name="i_sample_1"/></StgValue>
</operation>

<operation id="145" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="106" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge3:4  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="146" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="57">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="108" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
._crit_edge:0  %p_0 = phi i32 [ %c_load, %1 ], [ 1, %3 ]

]]></node>
<StgValue><ssdm name="p_0"/></StgValue>
</operation>

<operation id="147" st_id="34" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="57">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="109" bw="0" op_0_bw="32">
<![CDATA[
._crit_edge:1  ret i32 %p_0

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
