<stg><name>mat_mul.3</name>


<trans_list>

<trans id="79" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="109" from="2" to="10">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="110" from="2" to="3">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="102" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="103" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="104" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="105" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="106" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="107" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="108" from="9" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="90" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="119" from="11" to="19">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="120" from="11" to="12">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="112" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="113" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="114" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="115" from="15" to="16">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="116" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="117" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="118" from="18" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
.lr.ph7:0 %empty = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 0, i64 0

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.lr.ph7:1 %specloopname_ln66 = specloopname void @_ssdm_op_SpecLoopName, void @empty_2

]]></Node>
<StgValue><ssdm name="specloopname_ln66"/></StgValue>
</operation>

<operation id="22" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph7:2 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="23" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
:0 %j_0 = phi i4 %add_ln70, void %.split.0, i4 0, void %.lr.ph7

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_0 = phi i32 %tmp, void %.split.0, i32 0, void %.lr.ph7

]]></Node>
<StgValue><ssdm name="sum_0"/></StgValue>
</operation>

<operation id="25" st_id="2" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
:2 %add_ln70 = add i4 %j_0, i4 1

]]></Node>
<StgValue><ssdm name="add_ln70"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
:4 %icmp_ln70 = icmp_eq  i4 %j_0, i4 8

]]></Node>
<StgValue><ssdm name="icmp_ln70"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_85 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 8, i64 8, i64 8

]]></Node>
<StgValue><ssdm name="empty_85"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70, void %.split.0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="17" bw="64" op_0_bw="4">
<![CDATA[
.split.0:0 %j_0_cast = zext i4 %j_0

]]></Node>
<StgValue><ssdm name="j_0_cast"/></StgValue>
</operation>

<operation id="31" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="19" bw="4" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0:2 %layer10_weights_addr = getelementptr i32 %layer10_weights, i64 0, i64 %j_0_cast

]]></Node>
<StgValue><ssdm name="layer10_weights_addr"/></StgValue>
</operation>

<operation id="32" st_id="2" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="4">
<![CDATA[
.split.0:3 %layer10_weights_load = load i4 %layer10_weights_addr

]]></Node>
<StgValue><ssdm name="layer10_weights_load"/></StgValue>
</operation>

<operation id="33" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="21" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0:4 %input_addr = getelementptr i32 %input_r, i64 0, i64 %j_0_cast

]]></Node>
<StgValue><ssdm name="input_addr"/></StgValue>
</operation>

<operation id="34" st_id="2" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="11">
<![CDATA[
.split.0:5 %input_load = load i11 %input_addr

]]></Node>
<StgValue><ssdm name="input_load"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="35" st_id="3" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="20" bw="32" op_0_bw="4">
<![CDATA[
.split.0:3 %layer10_weights_load = load i4 %layer10_weights_addr

]]></Node>
<StgValue><ssdm name="layer10_weights_load"/></StgValue>
</operation>

<operation id="36" st_id="3" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="22" bw="32" op_0_bw="11">
<![CDATA[
.split.0:5 %input_load = load i11 %input_addr

]]></Node>
<StgValue><ssdm name="input_load"/></StgValue>
</operation>

<operation id="37" st_id="3" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:6 %mul4 = fmul i32 %layer10_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="38" st_id="4" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:6 %mul4 = fmul i32 %layer10_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="39" st_id="5" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:6 %mul4 = fmul i32 %layer10_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="40" st_id="6" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="23" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0:6 %mul4 = fmul i32 %layer10_weights_load, i32 %input_load

]]></Node>
<StgValue><ssdm name="mul4"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="41" st_id="7" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="24" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.split.0:7 %icmp_ln72 = icmp_eq  i4 %add_ln70, i4 8

]]></Node>
<StgValue><ssdm name="icmp_ln72"/></StgValue>
</operation>

<operation id="42" st_id="7" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:8 %tmp = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="43" st_id="8" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:8 %tmp = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="44" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="18" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.0:1 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="45" st_id="9" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.0:8 %tmp = facc i32 @_ssdm_op_FACC, i32 %mul4, i1 %icmp_ln72

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="46" st_id="9" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="0" op_0_bw="0">
<![CDATA[
.split.0:9 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="47" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.0:0 %output_addr = getelementptr i32 %output_r, i64 0, i64 0

]]></Node>
<StgValue><ssdm name="output_addr"/></StgValue>
</operation>

<operation id="48" st_id="10" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.0:1 %store_ln74 = store i32 %sum_0, i11 %output_addr

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="49" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.0:2 %br_ln70 = br void

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="50" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="4" op_0_bw="4" op_1_bw="0" op_2_bw="4" op_3_bw="0">
<![CDATA[
:0 %j_1 = phi i4 %add_ln70_1, void %.split.1, i4 0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="j_1"/></StgValue>
</operation>

<operation id="51" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %sum_19 = phi i32 %tmp_2, void %.split.1, i32 0, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="sum_19"/></StgValue>
</operation>

<operation id="52" st_id="11" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
:2 %add_ln70_1 = add i4 %j_1, i4 1

]]></Node>
<StgValue><ssdm name="add_ln70_1"/></StgValue>
</operation>

<operation id="53" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="54" st_id="11" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
:4 %icmp_ln70_1 = icmp_eq  i4 %j_1, i4 8

]]></Node>
<StgValue><ssdm name="icmp_ln70_1"/></StgValue>
</operation>

<operation id="55" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:5 %empty_86 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 8, i64 8, i64 8

]]></Node>
<StgValue><ssdm name="empty_86"/></StgValue>
</operation>

<operation id="56" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6 %br_ln70 = br i1 %icmp_ln70_1, void %.split.1, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="br_ln70"/></StgValue>
</operation>

<operation id="57" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="40" bw="64" op_0_bw="4">
<![CDATA[
.split.1:0 %j_1_cast = zext i4 %j_1

]]></Node>
<StgValue><ssdm name="j_1_cast"/></StgValue>
</operation>

<operation id="58" st_id="11" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="42" bw="4" op_0_bw="4" op_1_bw="4">
<![CDATA[
.split.1:2 %xor_ln72 = xor i4 %j_1, i4 8

]]></Node>
<StgValue><ssdm name="xor_ln72"/></StgValue>
</operation>

<operation id="59" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="43" bw="64" op_0_bw="4">
<![CDATA[
.split.1:3 %zext_ln72 = zext i4 %xor_ln72

]]></Node>
<StgValue><ssdm name="zext_ln72"/></StgValue>
</operation>

<operation id="60" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="44" bw="4" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1:4 %layer10_weights_addr_1 = getelementptr i32 %layer10_weights, i64 0, i64 %zext_ln72

]]></Node>
<StgValue><ssdm name="layer10_weights_addr_1"/></StgValue>
</operation>

<operation id="61" st_id="11" stage="2" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="32" op_0_bw="4">
<![CDATA[
.split.1:5 %layer10_weights_load_1 = load i4 %layer10_weights_addr_1

]]></Node>
<StgValue><ssdm name="layer10_weights_load_1"/></StgValue>
</operation>

<operation id="62" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="46" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1:6 %input_addr_1 = getelementptr i32 %input_r, i64 0, i64 %j_1_cast

]]></Node>
<StgValue><ssdm name="input_addr_1"/></StgValue>
</operation>

<operation id="63" st_id="11" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="11">
<![CDATA[
.split.1:7 %input_load_1 = load i11 %input_addr_1

]]></Node>
<StgValue><ssdm name="input_load_1"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="64" st_id="12" stage="1" lat="2">
<core>ROM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="45" bw="32" op_0_bw="4">
<![CDATA[
.split.1:5 %layer10_weights_load_1 = load i4 %layer10_weights_addr_1

]]></Node>
<StgValue><ssdm name="layer10_weights_load_1"/></StgValue>
</operation>

<operation id="65" st_id="12" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="11">
<![CDATA[
.split.1:7 %input_load_1 = load i11 %input_addr_1

]]></Node>
<StgValue><ssdm name="input_load_1"/></StgValue>
</operation>

<operation id="66" st_id="12" stage="4" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:8 %mul4_1 = fmul i32 %layer10_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="67" st_id="13" stage="3" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:8 %mul4_1 = fmul i32 %layer10_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="68" st_id="14" stage="2" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:8 %mul4_1 = fmul i32 %layer10_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="69" st_id="15" stage="1" lat="4">
<core>FMul_maxdsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="48" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1:8 %mul4_1 = fmul i32 %layer10_weights_load_1, i32 %input_load_1

]]></Node>
<StgValue><ssdm name="mul4_1"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="70" st_id="16" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="49" bw="1" op_0_bw="4" op_1_bw="4">
<![CDATA[
.split.1:9 %icmp_ln72_1 = icmp_eq  i4 %add_ln70_1, i4 8

]]></Node>
<StgValue><ssdm name="icmp_ln72_1"/></StgValue>
</operation>

<operation id="71" st_id="16" stage="3" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:10 %tmp_2 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_1

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="72" st_id="17" stage="2" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:10 %tmp_2 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_1

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="73" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="41" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.1:1 %specloopname_ln65 = specloopname void @_ssdm_op_SpecLoopName, void @empty

]]></Node>
<StgValue><ssdm name="specloopname_ln65"/></StgValue>
</operation>

<operation id="74" st_id="18" stage="1" lat="3">
<core>FAcc_nodsp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="32" op_0_bw="32" op_1_bw="32" op_2_bw="1">
<![CDATA[
.split.1:10 %tmp_2 = facc i32 @_ssdm_op_FACC, i32 %mul4_1, i1 %icmp_ln72_1

]]></Node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>

<operation id="75" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln70_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="0" op_0_bw="0">
<![CDATA[
.split.1:11 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="76" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="53" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
._crit_edge.loopexit.1:0 %output_addr_2 = getelementptr i32 %output_r, i64 0, i64 1

]]></Node>
<StgValue><ssdm name="output_addr_2"/></StgValue>
</operation>

<operation id="77" st_id="19" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="54" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.1:1 %store_ln74 = store i32 %sum_19, i11 %output_addr_2

]]></Node>
<StgValue><ssdm name="store_ln74"/></StgValue>
</operation>

<operation id="78" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="55" bw="0">
<![CDATA[
._crit_edge.loopexit.1:2 %ret_ln76 = ret

]]></Node>
<StgValue><ssdm name="ret_ln76"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
