<stg><name>bitset_next</name>


<trans_list>

<trans id="39" from="1" to="2">
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="3" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="5" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge:0  %r_bucket_read = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %r_bucket)

]]></node>
<StgValue><ssdm name="r_bucket_read"/></StgValue>
</operation>

<operation id="4" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="6" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
._crit_edge:1  %r_bucket_index_read = call i8 @_ssdm_op_Read.ap_auto.i8(i8 %r_bucket_index)

]]></node>
<StgValue><ssdm name="r_bucket_index_read"/></StgValue>
</operation>

<operation id="5" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="7" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
._crit_edge:2  %r_bit_read = call i8 @_ssdm_op_Read.ap_auto.i8(i8 %r_bit)

]]></node>
<StgValue><ssdm name="r_bit_read"/></StgValue>
</operation>

<operation id="6" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="8" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge:3  %p_read_1 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %p_read)

]]></node>
<StgValue><ssdm name="p_read_1"/></StgValue>
</operation>

<operation id="7" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="2" op_0_bw="8">
<![CDATA[
._crit_edge:4  %tmp = trunc i8 %r_bucket_index_read to i2

]]></node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="8" st_id="1" stage="1" lat="1">
<core>AddSub</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="10" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge:5  %tmp_1 = add i32 %r_bucket_read, -1

]]></node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="9" st_id="1" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="11" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge:6  %bus_assign = and i32 %tmp_1, %r_bucket_read

]]></node>
<StgValue><ssdm name="bus_assign"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="12" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge:7  %tmp_3 = icmp eq i32 %bus_assign, 0

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="13" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge:8  br i1 %tmp_3, label %.preheader, label %0

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
</and_exp></or_exp>
</condition>

<node id="19" bw="1" op_0_bw="2" op_1_bw="2">
<![CDATA[
.preheader:0  %tmp_25_1 = icmp eq i2 %tmp, 0

]]></node>
<StgValue><ssdm name="tmp_25_1"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="3">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
</and_exp></or_exp>
</condition>

<node id="20" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
.preheader:1  br i1 %tmp_25_1, label %2, label %.loopexit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
<literal name="tmp_25_1" val="1"/>
</and_exp></or_exp>
</condition>

<node id="22" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %tmp_27_1 = icmp eq i32 %p_read_1, 0

]]></node>
<StgValue><ssdm name="tmp_27_1"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="15">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
<literal name="tmp_25_1" val="1"/>
</and_exp></or_exp>
</condition>

<node id="23" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:1  br i1 %tmp_27_1, label %.loopexit, label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="14">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
<literal name="tmp_25_1" val="1"/>
<literal name="tmp_27_1" val="0"/>
</and_exp></or_exp>
</condition>

<node id="25" bw="5" op_0_bw="5" op_1_bw="32">
<![CDATA[
:0  %tmp_i1 = call fastcc zeroext i5 @_bsf32_hw(i32 %p_read_1) nounwind

]]></node>
<StgValue><ssdm name="tmp_i1"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="14">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
<literal name="tmp_25_1" val="1"/>
<literal name="tmp_27_1" val="0"/>
</and_exp></or_exp>
</condition>

<node id="26" bw="8" op_0_bw="5">
<![CDATA[
:1  %agg_result_bit_write_assign_trunc3_ext = zext i5 %tmp_i1 to i8

]]></node>
<StgValue><ssdm name="agg_result_bit_write_assign_trunc3_ext"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="14">
<or_exp><and_exp><literal name="tmp_3" val="1"/>
<literal name="tmp_25_1" val="1"/>
<literal name="tmp_27_1" val="0"/>
</and_exp></or_exp>
</condition>

<node id="27" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %.loopexit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="19" st_id="2" stage="1" lat="1">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="0">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="15" bw="5" op_0_bw="5" op_1_bw="32">
<![CDATA[
:0  %tmp_i = call fastcc zeroext i5 @_bsf32_hw(i32 %bus_assign) nounwind

]]></node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="20" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="0">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="16" bw="8" op_0_bw="5">
<![CDATA[
:1  %agg_result_bit_write_assign_trunc_ext = zext i5 %tmp_i to i8

]]></node>
<StgValue><ssdm name="agg_result_bit_write_assign_trunc_ext"/></StgValue>
</operation>

<operation id="21" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="0">
<or_exp><and_exp><literal name="tmp_3" val="0"/>
</and_exp></or_exp>
</condition>

<node id="17" bw="0" op_0_bw="0">
<![CDATA[
:2  br label %.loopexit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="22" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
.loopexit:0  %agg_result_bucket_write_assign = phi i32 [ %p_read_1, %1 ], [ %bus_assign, %0 ], [ 0, %.preheader ], [ %p_read_1, %2 ]

]]></node>
<StgValue><ssdm name="agg_result_bucket_write_assign"/></StgValue>
</operation>

<operation id="23" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="30" bw="1" op_0_bw="1" op_1_bw="0" op_2_bw="1" op_3_bw="0">
<![CDATA[
.loopexit:1  %agg_result_end_write_assign = phi i1 [ false, %1 ], [ false, %0 ], [ true, %.preheader ], [ true, %2 ]

]]></node>
<StgValue><ssdm name="agg_result_end_write_assign"/></StgValue>
</operation>

<operation id="24" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="31" bw="2" op_0_bw="2" op_1_bw="0" op_2_bw="2" op_3_bw="0">
<![CDATA[
.loopexit:2  %agg_result_bucket_index_write_assign = phi i2 [ 1, %1 ], [ %tmp, %0 ], [ -2, %.preheader ], [ -2, %2 ]

]]></node>
<StgValue><ssdm name="agg_result_bucket_index_write_assign"/></StgValue>
</operation>

<operation id="25" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="8" op_0_bw="8" op_1_bw="0" op_2_bw="8" op_3_bw="0">
<![CDATA[
.loopexit:3  %agg_result_bit_write_assign = phi i8 [ %agg_result_bit_write_assign_trunc3_ext, %1 ], [ %agg_result_bit_write_assign_trunc_ext, %0 ], [ %r_bit_read, %.preheader ], [ %r_bit_read, %2 ]

]]></node>
<StgValue><ssdm name="agg_result_bit_write_assign"/></StgValue>
</operation>

<operation id="26" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="33" bw="8" op_0_bw="2">
<![CDATA[
.loopexit:4  %agg_result_bucket_index_write_assign_cast = zext i2 %agg_result_bucket_index_write_assign to i8

]]></node>
<StgValue><ssdm name="agg_result_bucket_index_write_assign_cast"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="34" bw="49" op_0_bw="49" op_1_bw="8">
<![CDATA[
.loopexit:5  %mrv = insertvalue { i8, i8, i32, i1 } undef, i8 %agg_result_bit_write_assign, 0

]]></node>
<StgValue><ssdm name="mrv"/></StgValue>
</operation>

<operation id="28" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="49" op_0_bw="49" op_1_bw="8">
<![CDATA[
.loopexit:6  %mrv_1 = insertvalue { i8, i8, i32, i1 } %mrv, i8 %agg_result_bucket_index_write_assign_cast, 1

]]></node>
<StgValue><ssdm name="mrv_1"/></StgValue>
</operation>

<operation id="29" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="36" bw="49" op_0_bw="49" op_1_bw="32">
<![CDATA[
.loopexit:7  %mrv_2 = insertvalue { i8, i8, i32, i1 } %mrv_1, i32 %agg_result_bucket_write_assign, 2

]]></node>
<StgValue><ssdm name="mrv_2"/></StgValue>
</operation>

<operation id="30" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="37" bw="49" op_0_bw="49" op_1_bw="1">
<![CDATA[
.loopexit:8  %mrv_3 = insertvalue { i8, i8, i32, i1 } %mrv_2, i1 %agg_result_end_write_assign, 3

]]></node>
<StgValue><ssdm name="mrv_3"/></StgValue>
</operation>

<operation id="31" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="12">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="38" bw="0" op_0_bw="49">
<![CDATA[
.loopexit:9  ret { i8, i8, i32, i1 } %mrv_3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
