<stg><name>maxPooling</name>


<trans_list>

<trans id="1309" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1310" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1311" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1312" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1313" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1314" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1315" from="7" to="8">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1316" from="8" to="9">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1317" from="9" to="10">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1318" from="10" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1319" from="11" to="12">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1320" from="11" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1322" from="12" to="13">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1323" from="13" to="14">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1324" from="14" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1482" from="15" to="22">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1483" from="15" to="16">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1476" from="16" to="17">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1477" from="17" to="18">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1478" from="18" to="19">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1479" from="19" to="20">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1480" from="20" to="21">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1481" from="21" to="15">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1334" from="22" to="23">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1335" from="22" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1337" from="23" to="24">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1338" from="24" to="25">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1339" from="25" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1491" from="26" to="33">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1492" from="26" to="27">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1485" from="27" to="28">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1486" from="28" to="29">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1487" from="29" to="30">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1488" from="30" to="31">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1489" from="31" to="32">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1490" from="32" to="26">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1349" from="33" to="34">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1350" from="33" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1352" from="34" to="35">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1353" from="35" to="36">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1354" from="36" to="37">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1500" from="37" to="44">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1501" from="37" to="38">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1494" from="38" to="39">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1495" from="39" to="40">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1496" from="40" to="41">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1497" from="41" to="42">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1498" from="42" to="43">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1499" from="43" to="37">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1364" from="44" to="45">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1365" from="44" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1367" from="45" to="46">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1368" from="46" to="47">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1369" from="47" to="48">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1509" from="48" to="55">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1510" from="48" to="49">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1503" from="49" to="50">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1504" from="50" to="51">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1505" from="51" to="52">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1506" from="52" to="53">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1507" from="53" to="54">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1508" from="54" to="48">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1379" from="55" to="56">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1380" from="55" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1382" from="56" to="57">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1383" from="57" to="58">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1384" from="58" to="59">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1518" from="59" to="66">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1519" from="59" to="60">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1512" from="60" to="61">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1513" from="61" to="62">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1514" from="62" to="63">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1515" from="63" to="64">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1516" from="64" to="65">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1517" from="65" to="59">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1394" from="66" to="67">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1395" from="66" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1397" from="67" to="68">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1398" from="68" to="69">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1399" from="69" to="70">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1527" from="70" to="77">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1528" from="70" to="71">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1521" from="71" to="72">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1522" from="72" to="73">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1523" from="73" to="74">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1524" from="74" to="75">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1525" from="75" to="76">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1526" from="76" to="70">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1409" from="77" to="78">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_6" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1410" from="77" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_6" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1412" from="78" to="79">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1413" from="79" to="80">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1414" from="80" to="81">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1536" from="81" to="88">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1537" from="81" to="82">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1530" from="82" to="83">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1531" from="83" to="84">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1532" from="84" to="85">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1533" from="85" to="86">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1534" from="86" to="87">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1535" from="87" to="81">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1424" from="88" to="89">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1425" from="88" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1427" from="89" to="90">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1428" from="90" to="91">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1429" from="91" to="92">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1545" from="92" to="99">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1546" from="92" to="93">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1539" from="93" to="94">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1540" from="94" to="95">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1541" from="95" to="96">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1542" from="96" to="97">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1543" from="97" to="98">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1544" from="98" to="92">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1439" from="99" to="100">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_8" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1440" from="99" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_8" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1442" from="100" to="101">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1443" from="101" to="102">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1444" from="102" to="103">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1554" from="103" to="110">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1555" from="103" to="104">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1548" from="104" to="105">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1549" from="105" to="106">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1550" from="106" to="107">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1551" from="107" to="108">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1552" from="108" to="109">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1553" from="109" to="103">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1454" from="110" to="111">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1455" from="110" to="122">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1457" from="111" to="112">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1458" from="112" to="113">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1459" from="113" to="114">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1557" from="114" to="115">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1558" from="115" to="116">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1559" from="116" to="117">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1560" from="117" to="118">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1561" from="118" to="119">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1563" from="119" to="121">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1564" from="119" to="120">
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="1562" from="120" to="114">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="1474" from="121" to="11">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="123" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.lr.ph9:0 %h_read = read i5 @_ssdm_op_Read.ap_auto.i5, i5 %h

]]></Node>
<StgValue><ssdm name="h_read"/></StgValue>
</operation>

<operation id="124" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.lr.ph9:2 %sub = add i5 %h_read, i5 31

]]></Node>
<StgValue><ssdm name="sub"/></StgValue>
</operation>

<operation id="125" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="6" op_0_bw="5">
<![CDATA[
.lr.ph9:9 %zext_ln29_5 = zext i5 %sub

]]></Node>
<StgValue><ssdm name="zext_ln29_5"/></StgValue>
</operation>

<operation id="126" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:13 %add_ln29_29 = add i6 %zext_ln29_5, i6 19

]]></Node>
<StgValue><ssdm name="add_ln29_29"/></StgValue>
</operation>

<operation id="127" st_id="1" stage="10" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="128" st_id="2" stage="9" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="129" st_id="3" stage="8" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="130" st_id="4" stage="7" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="131" st_id="5" stage="6" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="132" st_id="6" stage="5" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="133" st_id="7" stage="4" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="134" st_id="8" stage="3" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="135" st_id="9" stage="2" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="136" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:1 %w_read = read i6 @_ssdm_op_Read.ap_auto.i6, i6 %w

]]></Node>
<StgValue><ssdm name="w_read"/></StgValue>
</operation>

<operation id="137" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:3 %sub1 = add i6 %w_read, i6 63

]]></Node>
<StgValue><ssdm name="sub1"/></StgValue>
</operation>

<operation id="138" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="7" op_0_bw="6">
<![CDATA[
.lr.ph9:4 %zext_ln29_1 = zext i6 %sub1

]]></Node>
<StgValue><ssdm name="zext_ln29_1"/></StgValue>
</operation>

<operation id="139" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:5 %add_ln29 = add i6 %w_read, i6 62

]]></Node>
<StgValue><ssdm name="add_ln29"/></StgValue>
</operation>

<operation id="140" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="5" op_0_bw="5" op_1_bw="6" op_2_bw="32" op_3_bw="32">
<![CDATA[
.lr.ph9:6 %trunc_ln = partselect i5 @_ssdm_op_PartSelect.i5.i6.i32.i32, i6 %add_ln29, i32 1, i32 5

]]></Node>
<StgValue><ssdm name="trunc_ln"/></StgValue>
</operation>

<operation id="141" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="11" op_0_bw="6">
<![CDATA[
.lr.ph9:7 %zext_ln29_2 = zext i6 %w_read

]]></Node>
<StgValue><ssdm name="zext_ln29_2"/></StgValue>
</operation>

<operation id="142" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="5">
<![CDATA[
.lr.ph9:8 %zext_ln29 = zext i5 %sub

]]></Node>
<StgValue><ssdm name="zext_ln29"/></StgValue>
</operation>

<operation id="143" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="5" op_0_bw="5" op_1_bw="5">
<![CDATA[
.lr.ph9:10 %add_ln29_1 = add i5 %trunc_ln, i5 1

]]></Node>
<StgValue><ssdm name="add_ln29_1"/></StgValue>
</operation>

<operation id="144" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="5">
<![CDATA[
.lr.ph9:11 %zext_ln29_3 = zext i5 %add_ln29_1

]]></Node>
<StgValue><ssdm name="zext_ln29_3"/></StgValue>
</operation>

<operation id="145" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="11" op_0_bw="5">
<![CDATA[
.lr.ph9:12 %zext_ln29_4 = zext i5 %add_ln29_1

]]></Node>
<StgValue><ssdm name="zext_ln29_4"/></StgValue>
</operation>

<operation id="146" st_id="10" stage="1" lat="10">
<core>DivnS_SEQ</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="5" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:14 %urem_ln29 = urem i6 %add_ln29_29, i6 20

]]></Node>
<StgValue><ssdm name="urem_ln29"/></StgValue>
</operation>

<operation id="147" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="5" op_0_bw="5">
<![CDATA[
.lr.ph9:15 %trunc_ln29 = trunc i5 %urem_ln29

]]></Node>
<StgValue><ssdm name="trunc_ln29"/></StgValue>
</operation>

<operation id="148" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="6" op_0_bw="5">
<![CDATA[
.lr.ph9:16 %zext_ln29_6 = zext i5 %trunc_ln29

]]></Node>
<StgValue><ssdm name="zext_ln29_6"/></StgValue>
</operation>

<operation id="149" st_id="10" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
.lr.ph9:17 %sub_ln29 = sub i6 %add_ln29_29, i6 %zext_ln29_6

]]></Node>
<StgValue><ssdm name="sub_ln29"/></StgValue>
</operation>

<operation id="150" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="64" op_0_bw="6">
<![CDATA[
.lr.ph9:18 %zext_ln29_7 = zext i6 %sub_ln29

]]></Node>
<StgValue><ssdm name="zext_ln29_7"/></StgValue>
</operation>

<operation id="151" st_id="10" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="0" op_0_bw="0">
<![CDATA[
.lr.ph9:19 %br_ln29 = br void

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="152" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:0 %i_0 = phi i64 %add_ln29_28, void %._crit_edge.loopexit.9, i64 0, void %.lr.ph9

]]></Node>
<StgValue><ssdm name="i_0"/></StgValue>
</operation>

<operation id="153" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0">
<![CDATA[
:1 %t_0 = phi i32 %add_ln29_27, void %._crit_edge.loopexit.9, i32 0, void %.lr.ph9

]]></Node>
<StgValue><ssdm name="t_0"/></StgValue>
</operation>

<operation id="154" st_id="11" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:2 %icmp_ln29 = icmp_eq  i64 %i_0, i64 %zext_ln29_7

]]></Node>
<StgValue><ssdm name="icmp_ln29"/></StgValue>
</operation>

<operation id="155" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:3 %br_ln29 = br i1 %icmp_ln29, void %.split4.0, void %._crit_edge10

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="156" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="31" bw="11" op_0_bw="64">
<![CDATA[
.split4.0:0 %trunc_ln29_1 = trunc i64 %i_0

]]></Node>
<StgValue><ssdm name="trunc_ln29_1"/></StgValue>
</operation>

<operation id="157" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="33" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:2 %empty = or i11 %trunc_ln29_1, i11 1

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="158" st_id="11" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="34" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:3 %empty_36 = mul i11 %trunc_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_36"/></StgValue>
</operation>

<operation id="159" st_id="11" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="35" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:4 %empty_37 = mul i11 %empty, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_37"/></StgValue>
</operation>

<operation id="160" st_id="11" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="37" bw="7" op_0_bw="7" op_1_bw="7">
<![CDATA[
.split4.0:6 %add_ln32_19 = add i7 %zext_ln29_1, i7 1

]]></Node>
<StgValue><ssdm name="add_ln32_19"/></StgValue>
</operation>

<operation id="161" st_id="11" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="38" bw="6" op_0_bw="6" op_1_bw="7" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split4.0:7 %tmp = partselect i6 @_ssdm_op_PartSelect.i6.i7.i32.i32, i7 %add_ln32_19, i32 1, i32 6

]]></Node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="162" st_id="12" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:3 %empty_36 = mul i11 %trunc_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_36"/></StgValue>
</operation>

<operation id="163" st_id="12" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:4 %empty_37 = mul i11 %empty, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_37"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="164" st_id="13" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:3 %empty_36 = mul i11 %trunc_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_36"/></StgValue>
</operation>

<operation id="165" st_id="13" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:4 %empty_37 = mul i11 %empty, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_37"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="166" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split4.0:1 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_4

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="167" st_id="14" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:3 %empty_36 = mul i11 %trunc_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_36"/></StgValue>
</operation>

<operation id="168" st_id="14" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.0:4 %empty_37 = mul i11 %empty, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_37"/></StgValue>
</operation>

<operation id="169" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="11" op_0_bw="32">
<![CDATA[
.split4.0:5 %trunc_ln32 = trunc i32 %t_0

]]></Node>
<StgValue><ssdm name="trunc_ln32"/></StgValue>
</operation>

<operation id="170" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="7" op_0_bw="7" op_1_bw="6" op_2_bw="1">
<![CDATA[
.split4.0:8 %tmp_1 = bitconcatenate i7 @_ssdm_op_BitConcatenate.i7.i6.i1, i6 %tmp, i1 0

]]></Node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>

<operation id="171" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="64" op_0_bw="7">
<![CDATA[
.split4.0:9 %zext_ln32 = zext i7 %tmp_1

]]></Node>
<StgValue><ssdm name="zext_ln32"/></StgValue>
</operation>

<operation id="172" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="0" op_0_bw="0">
<![CDATA[
.split4.0:10 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="173" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_0 = phi i11 %add_ln34, void %.split.0_ifconv, i11 %trunc_ln32, void %.split4.0

]]></Node>
<StgValue><ssdm name="t_1_0"/></StgValue>
</operation>

<operation id="174" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_0 = phi i64 %add_ln32, void %.split.0_ifconv, i64 0, void %.split4.0

]]></Node>
<StgValue><ssdm name="j_0"/></StgValue>
</operation>

<operation id="175" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="176" st_id="15" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32 = icmp_eq  i64 %j_0, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32"/></StgValue>
</operation>

<operation id="177" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_38 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_38"/></StgValue>
</operation>

<operation id="178" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32, void %.split.0_ifconv, void %._crit_edge.loopexit.0

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="179" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="52" bw="11" op_0_bw="64">
<![CDATA[
.split.0_ifconv:2 %empty_39 = trunc i64 %j_0

]]></Node>
<StgValue><ssdm name="empty_39"/></StgValue>
</operation>

<operation id="180" st_id="15" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="54" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:4 %add_ln8 = add i11 %empty_39, i11 %empty_36

]]></Node>
<StgValue><ssdm name="add_ln8"/></StgValue>
</operation>

<operation id="181" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="55" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:5 %zext_ln8 = zext i11 %add_ln8

]]></Node>
<StgValue><ssdm name="zext_ln8"/></StgValue>
</operation>

<operation id="182" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="56" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:6 %arr_addr = getelementptr i32 %arr, i64 0, i64 %zext_ln8

]]></Node>
<StgValue><ssdm name="arr_addr"/></StgValue>
</operation>

<operation id="183" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:7 %arr_load = load i11 %arr_addr

]]></Node>
<StgValue><ssdm name="arr_load"/></StgValue>
</operation>

<operation id="184" st_id="15" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="58" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:8 %add_ln8_1 = add i11 %empty_39, i11 %empty_37

]]></Node>
<StgValue><ssdm name="add_ln8_1"/></StgValue>
</operation>

<operation id="185" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="59" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:9 %zext_ln8_1 = zext i11 %add_ln8_1

]]></Node>
<StgValue><ssdm name="zext_ln8_1"/></StgValue>
</operation>

<operation id="186" st_id="15" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="60" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:10 %arr_addr_1 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_1

]]></Node>
<StgValue><ssdm name="arr_addr_1"/></StgValue>
</operation>

<operation id="187" st_id="15" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:11 %arr_load_1 = load i11 %arr_addr_1

]]></Node>
<StgValue><ssdm name="arr_load_1"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="188" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="57" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:7 %arr_load = load i11 %arr_addr

]]></Node>
<StgValue><ssdm name="arr_load"/></StgValue>
</operation>

<operation id="189" st_id="16" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="61" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:11 %arr_load_1 = load i11 %arr_addr_1

]]></Node>
<StgValue><ssdm name="arr_load_1"/></StgValue>
</operation>

<operation id="190" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="62" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:12 %or_ln34 = or i11 %empty_39, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34"/></StgValue>
</operation>

<operation id="191" st_id="16" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="63" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:13 %add_ln8_2 = add i11 %or_ln34, i11 %empty_36

]]></Node>
<StgValue><ssdm name="add_ln8_2"/></StgValue>
</operation>

<operation id="192" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="64" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:14 %zext_ln8_2 = zext i11 %add_ln8_2

]]></Node>
<StgValue><ssdm name="zext_ln8_2"/></StgValue>
</operation>

<operation id="193" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="65" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:15 %arr_addr_2 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_2

]]></Node>
<StgValue><ssdm name="arr_addr_2"/></StgValue>
</operation>

<operation id="194" st_id="16" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:16 %arr_load_2 = load i11 %arr_addr_2

]]></Node>
<StgValue><ssdm name="arr_load_2"/></StgValue>
</operation>

<operation id="195" st_id="16" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="67" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:17 %add_ln8_3 = add i11 %or_ln34, i11 %empty_37

]]></Node>
<StgValue><ssdm name="add_ln8_3"/></StgValue>
</operation>

<operation id="196" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="68" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:18 %zext_ln8_3 = zext i11 %add_ln8_3

]]></Node>
<StgValue><ssdm name="zext_ln8_3"/></StgValue>
</operation>

<operation id="197" st_id="16" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="69" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:19 %arr_addr_3 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_3

]]></Node>
<StgValue><ssdm name="arr_addr_3"/></StgValue>
</operation>

<operation id="198" st_id="16" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:20 %arr_load_3 = load i11 %arr_addr_3

]]></Node>
<StgValue><ssdm name="arr_load_3"/></StgValue>
</operation>

<operation id="199" st_id="16" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:34 %tmp_1036 = fcmp_ogt  i32 %arr_load, i32 %arr_load_1

]]></Node>
<StgValue><ssdm name="tmp_1036"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="200" st_id="17" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="50" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.0_ifconv:0 %add_ln32 = add i64 %j_0, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32"/></StgValue>
</operation>

<operation id="201" st_id="17" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="66" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:16 %arr_load_2 = load i11 %arr_addr_2

]]></Node>
<StgValue><ssdm name="arr_load_2"/></StgValue>
</operation>

<operation id="202" st_id="17" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="70" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:20 %arr_load_3 = load i11 %arr_addr_3

]]></Node>
<StgValue><ssdm name="arr_load_3"/></StgValue>
</operation>

<operation id="203" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="71" bw="32" op_0_bw="32">
<![CDATA[
.split.0_ifconv:21 %bitcast_ln13 = bitcast i32 %arr_load

]]></Node>
<StgValue><ssdm name="bitcast_ln13"/></StgValue>
</operation>

<operation id="204" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="72" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.0_ifconv:22 %tmp_s = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="205" st_id="17" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="73" bw="23" op_0_bw="32">
<![CDATA[
.split.0_ifconv:23 %trunc_ln13 = trunc i32 %bitcast_ln13

]]></Node>
<StgValue><ssdm name="trunc_ln13"/></StgValue>
</operation>

<operation id="206" st_id="17" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="77" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.0_ifconv:27 %icmp_ln13 = icmp_ne  i8 %tmp_s, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13"/></StgValue>
</operation>

<operation id="207" st_id="17" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="78" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.0_ifconv:28 %icmp_ln13_1 = icmp_eq  i23 %trunc_ln13, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_1"/></StgValue>
</operation>

<operation id="208" st_id="17" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="79" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:29 %or_ln13 = or i1 %icmp_ln13_1, i1 %icmp_ln13

]]></Node>
<StgValue><ssdm name="or_ln13"/></StgValue>
</operation>

<operation id="209" st_id="17" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="84" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:34 %tmp_1036 = fcmp_ogt  i32 %arr_load, i32 %arr_load_1

]]></Node>
<StgValue><ssdm name="tmp_1036"/></StgValue>
</operation>

<operation id="210" st_id="17" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:43 %tmp_1038 = fcmp_ogt  i32 %arr_load, i32 %arr_load_2

]]></Node>
<StgValue><ssdm name="tmp_1038"/></StgValue>
</operation>

<operation id="211" st_id="17" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:52 %tmp_1040 = fcmp_ogt  i32 %arr_load, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1040"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="212" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="74" bw="32" op_0_bw="32">
<![CDATA[
.split.0_ifconv:24 %bitcast_ln13_1 = bitcast i32 %arr_load_1

]]></Node>
<StgValue><ssdm name="bitcast_ln13_1"/></StgValue>
</operation>

<operation id="213" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="75" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.0_ifconv:25 %tmp_1035 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_1, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1035"/></StgValue>
</operation>

<operation id="214" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="76" bw="23" op_0_bw="32">
<![CDATA[
.split.0_ifconv:26 %trunc_ln13_1 = trunc i32 %bitcast_ln13_1

]]></Node>
<StgValue><ssdm name="trunc_ln13_1"/></StgValue>
</operation>

<operation id="215" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="80" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.0_ifconv:30 %icmp_ln13_2 = icmp_ne  i8 %tmp_1035, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_2"/></StgValue>
</operation>

<operation id="216" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="81" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.0_ifconv:31 %icmp_ln13_3 = icmp_eq  i23 %trunc_ln13_1, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_3"/></StgValue>
</operation>

<operation id="217" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="82" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:32 %or_ln13_1 = or i1 %icmp_ln13_3, i1 %icmp_ln13_2

]]></Node>
<StgValue><ssdm name="or_ln13_1"/></StgValue>
</operation>

<operation id="218" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="83" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:33 %and_ln13 = and i1 %or_ln13, i1 %or_ln13_1

]]></Node>
<StgValue><ssdm name="and_ln13"/></StgValue>
</operation>

<operation id="219" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="85" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:35 %and_ln13_2 = and i1 %and_ln13, i1 %tmp_1036

]]></Node>
<StgValue><ssdm name="and_ln13_2"/></StgValue>
</operation>

<operation id="220" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="86" bw="32" op_0_bw="32">
<![CDATA[
.split.0_ifconv:36 %bitcast_ln13_2 = bitcast i32 %arr_load_2

]]></Node>
<StgValue><ssdm name="bitcast_ln13_2"/></StgValue>
</operation>

<operation id="221" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="87" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.0_ifconv:37 %tmp_1037 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_2, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1037"/></StgValue>
</operation>

<operation id="222" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="88" bw="23" op_0_bw="32">
<![CDATA[
.split.0_ifconv:38 %trunc_ln13_2 = trunc i32 %bitcast_ln13_2

]]></Node>
<StgValue><ssdm name="trunc_ln13_2"/></StgValue>
</operation>

<operation id="223" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="89" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.0_ifconv:39 %icmp_ln13_4 = icmp_ne  i8 %tmp_1037, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_4"/></StgValue>
</operation>

<operation id="224" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="90" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.0_ifconv:40 %icmp_ln13_5 = icmp_eq  i23 %trunc_ln13_2, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_5"/></StgValue>
</operation>

<operation id="225" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="91" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:41 %or_ln13_2 = or i1 %icmp_ln13_5, i1 %icmp_ln13_4

]]></Node>
<StgValue><ssdm name="or_ln13_2"/></StgValue>
</operation>

<operation id="226" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="92" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:42 %and_ln13_3 = and i1 %or_ln13, i1 %or_ln13_2

]]></Node>
<StgValue><ssdm name="and_ln13_3"/></StgValue>
</operation>

<operation id="227" st_id="18" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="93" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:43 %tmp_1038 = fcmp_ogt  i32 %arr_load, i32 %arr_load_2

]]></Node>
<StgValue><ssdm name="tmp_1038"/></StgValue>
</operation>

<operation id="228" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="94" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:44 %and_ln13_4 = and i1 %and_ln13_3, i1 %tmp_1038

]]></Node>
<StgValue><ssdm name="and_ln13_4"/></StgValue>
</operation>

<operation id="229" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="95" bw="32" op_0_bw="32">
<![CDATA[
.split.0_ifconv:45 %bitcast_ln13_3 = bitcast i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="bitcast_ln13_3"/></StgValue>
</operation>

<operation id="230" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="96" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.0_ifconv:46 %tmp_1039 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_3, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1039"/></StgValue>
</operation>

<operation id="231" st_id="18" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="97" bw="23" op_0_bw="32">
<![CDATA[
.split.0_ifconv:47 %trunc_ln13_3 = trunc i32 %bitcast_ln13_3

]]></Node>
<StgValue><ssdm name="trunc_ln13_3"/></StgValue>
</operation>

<operation id="232" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="98" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.0_ifconv:48 %icmp_ln13_6 = icmp_ne  i8 %tmp_1039, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_6"/></StgValue>
</operation>

<operation id="233" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="99" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.0_ifconv:49 %icmp_ln13_7 = icmp_eq  i23 %trunc_ln13_3, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_7"/></StgValue>
</operation>

<operation id="234" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="100" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:50 %or_ln13_3 = or i1 %icmp_ln13_7, i1 %icmp_ln13_6

]]></Node>
<StgValue><ssdm name="or_ln13_3"/></StgValue>
</operation>

<operation id="235" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="101" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:51 %and_ln13_5 = and i1 %or_ln13, i1 %or_ln13_3

]]></Node>
<StgValue><ssdm name="and_ln13_5"/></StgValue>
</operation>

<operation id="236" st_id="18" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="102" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:52 %tmp_1040 = fcmp_ogt  i32 %arr_load, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1040"/></StgValue>
</operation>

<operation id="237" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="103" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:53 %and_ln13_6 = and i1 %and_ln13_5, i1 %tmp_1040

]]></Node>
<StgValue><ssdm name="and_ln13_6"/></StgValue>
</operation>

<operation id="238" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="104" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:54 %and_ln13_7 = and i1 %and_ln13_4, i1 %and_ln13_6

]]></Node>
<StgValue><ssdm name="and_ln13_7"/></StgValue>
</operation>

<operation id="239" st_id="18" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="105" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:55 %and_ln13_1 = and i1 %and_ln13_7, i1 %and_ln13_2

]]></Node>
<StgValue><ssdm name="and_ln13_1"/></StgValue>
</operation>

<operation id="240" st_id="18" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:57 %tmp_1041 = fcmp_ogt  i32 %arr_load_1, i32 %arr_load_2

]]></Node>
<StgValue><ssdm name="tmp_1041"/></StgValue>
</operation>

<operation id="241" st_id="18" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:60 %tmp_1042 = fcmp_ogt  i32 %arr_load_1, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1042"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="242" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="106" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:56 %and_ln16_10 = and i1 %or_ln13_1, i1 %or_ln13_2

]]></Node>
<StgValue><ssdm name="and_ln16_10"/></StgValue>
</operation>

<operation id="243" st_id="19" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="107" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:57 %tmp_1041 = fcmp_ogt  i32 %arr_load_1, i32 %arr_load_2

]]></Node>
<StgValue><ssdm name="tmp_1041"/></StgValue>
</operation>

<operation id="244" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="108" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:58 %and_ln16_11 = and i1 %and_ln16_10, i1 %tmp_1041

]]></Node>
<StgValue><ssdm name="and_ln16_11"/></StgValue>
</operation>

<operation id="245" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="109" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:59 %and_ln16_12 = and i1 %or_ln13_1, i1 %or_ln13_3

]]></Node>
<StgValue><ssdm name="and_ln16_12"/></StgValue>
</operation>

<operation id="246" st_id="19" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="110" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:60 %tmp_1042 = fcmp_ogt  i32 %arr_load_1, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1042"/></StgValue>
</operation>

<operation id="247" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="111" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:61 %and_ln16_13 = and i1 %and_ln16_12, i1 %tmp_1042

]]></Node>
<StgValue><ssdm name="and_ln16_13"/></StgValue>
</operation>

<operation id="248" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="112" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:62 %and_ln16 = and i1 %and_ln16_11, i1 %and_ln16_13

]]></Node>
<StgValue><ssdm name="and_ln16"/></StgValue>
</operation>

<operation id="249" st_id="19" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:64 %tmp_1043 = fcmp_ogt  i32 %arr_load_2, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1043"/></StgValue>
</operation>

<operation id="250" st_id="19" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="116" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.0_ifconv:66 %select_ln13 = select i1 %and_ln13_1, i11 %add_ln8, i11 %add_ln8_3

]]></Node>
<StgValue><ssdm name="select_ln13"/></StgValue>
</operation>

<operation id="251" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="117" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:67 %xor_ln13 = xor i1 %and_ln13_1, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13"/></StgValue>
</operation>

<operation id="252" st_id="19" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="118" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:68 %and_ln16_14 = and i1 %and_ln16, i1 %xor_ln13

]]></Node>
<StgValue><ssdm name="and_ln16_14"/></StgValue>
</operation>

<operation id="253" st_id="19" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="119" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.0_ifconv:69 %select_ln16 = select i1 %and_ln16_14, i11 %add_ln8_1, i11 %select_ln13

]]></Node>
<StgValue><ssdm name="select_ln16"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="254" st_id="20" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="113" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:63 %and_ln19 = and i1 %or_ln13_2, i1 %or_ln13_3

]]></Node>
<StgValue><ssdm name="and_ln19"/></StgValue>
</operation>

<operation id="255" st_id="20" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="114" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.0_ifconv:64 %tmp_1043 = fcmp_ogt  i32 %arr_load_2, i32 %arr_load_3

]]></Node>
<StgValue><ssdm name="tmp_1043"/></StgValue>
</operation>

<operation id="256" st_id="20" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="115" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:65 %and_ln19_1 = and i1 %and_ln19, i1 %tmp_1043

]]></Node>
<StgValue><ssdm name="and_ln19_1"/></StgValue>
</operation>

<operation id="257" st_id="20" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="120" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:70 %or_ln16 = or i1 %and_ln13_1, i1 %and_ln16

]]></Node>
<StgValue><ssdm name="or_ln16"/></StgValue>
</operation>

<operation id="258" st_id="20" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="121" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:71 %xor_ln16 = xor i1 %or_ln16, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16"/></StgValue>
</operation>

<operation id="259" st_id="20" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="122" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.0_ifconv:72 %and_ln19_2 = and i1 %and_ln19_1, i1 %xor_ln16

]]></Node>
<StgValue><ssdm name="and_ln19_2"/></StgValue>
</operation>

<operation id="260" st_id="20" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="123" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.0_ifconv:73 %select_ln19 = select i1 %and_ln19_2, i11 %add_ln8_2, i11 %select_ln16

]]></Node>
<StgValue><ssdm name="select_ln19"/></StgValue>
</operation>

<operation id="261" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="124" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:74 %zext_ln8_40 = zext i11 %select_ln19

]]></Node>
<StgValue><ssdm name="zext_ln8_40"/></StgValue>
</operation>

<operation id="262" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="125" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:75 %arr_addr_40 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_40

]]></Node>
<StgValue><ssdm name="arr_addr_40"/></StgValue>
</operation>

<operation id="263" st_id="20" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="126" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:76 %arr_load_40 = load i11 %arr_addr_40

]]></Node>
<StgValue><ssdm name="arr_load_40"/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="264" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="51" bw="64" op_0_bw="11">
<![CDATA[
.split.0_ifconv:1 %t_1_0_cast = zext i11 %t_1_0

]]></Node>
<StgValue><ssdm name="t_1_0_cast"/></StgValue>
</operation>

<operation id="265" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="53" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.0_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="266" st_id="21" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="126" bw="32" op_0_bw="11">
<![CDATA[
.split.0_ifconv:76 %arr_load_40 = load i11 %arr_addr_40

]]></Node>
<StgValue><ssdm name="arr_load_40"/></StgValue>
</operation>

<operation id="267" st_id="21" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="127" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.0_ifconv:77 %add_ln34 = add i11 %t_1_0, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34"/></StgValue>
</operation>

<operation id="268" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="128" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.0_ifconv:78 %out_addr = getelementptr i32 %out_r, i64 0, i64 %t_1_0_cast

]]></Node>
<StgValue><ssdm name="out_addr"/></StgValue>
</operation>

<operation id="269" st_id="21" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="129" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.0_ifconv:79 %store_ln34 = store i32 %arr_load_40, i11 %out_addr

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="270" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="130" bw="0" op_0_bw="0">
<![CDATA[
.split.0_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="271" st_id="22" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="132" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.0:0 %add_ln29_2 = add i32 %zext_ln29_3, i32 %t_0

]]></Node>
<StgValue><ssdm name="add_ln29_2"/></StgValue>
</operation>

<operation id="272" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="133" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.0:1 %or_ln29 = or i64 %i_0, i64 2

]]></Node>
<StgValue><ssdm name="or_ln29"/></StgValue>
</operation>

<operation id="273" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="134" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.0:2 %or_ln29_1 = or i11 %trunc_ln29_1, i11 2

]]></Node>
<StgValue><ssdm name="or_ln29_1"/></StgValue>
</operation>

<operation id="274" st_id="22" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="135" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.0:3 %icmp_ln29_1 = icmp_slt  i64 %or_ln29, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_1"/></StgValue>
</operation>

<operation id="275" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="136" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.0:4 %br_ln29 = br i1 %icmp_ln29_1, void %._crit_edge10, void %.split4.1

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="276" st_id="22" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="138" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:0 %empty_40 = or i11 %trunc_ln29_1, i11 3

]]></Node>
<StgValue><ssdm name="empty_40"/></StgValue>
</operation>

<operation id="277" st_id="22" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="139" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:1 %empty_41 = mul i11 %or_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="278" st_id="22" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_1" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="140" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:2 %empty_42 = mul i11 %empty_40, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="279" st_id="23" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="139" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:1 %empty_41 = mul i11 %or_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="280" st_id="23" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="140" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:2 %empty_42 = mul i11 %empty_40, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="281" st_id="24" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="139" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:1 %empty_41 = mul i11 %or_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="282" st_id="24" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="140" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:2 %empty_42 = mul i11 %empty_40, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="283" st_id="25" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="139" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:1 %empty_41 = mul i11 %or_ln29_1, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_41"/></StgValue>
</operation>

<operation id="284" st_id="25" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="140" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:2 %empty_42 = mul i11 %empty_40, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_42"/></StgValue>
</operation>

<operation id="285" st_id="25" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="141" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.1:3 %add_ln32_10 = add i11 %zext_ln29_4, i11 %trunc_ln32

]]></Node>
<StgValue><ssdm name="add_ln32_10"/></StgValue>
</operation>

<operation id="286" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="142" bw="0" op_0_bw="0">
<![CDATA[
.split4.1:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="287" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="144" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_1 = phi i11 %add_ln34_1, void %.split.1_ifconv, i11 %add_ln32_10, void %.split4.1

]]></Node>
<StgValue><ssdm name="t_1_1"/></StgValue>
</operation>

<operation id="288" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="145" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_1 = phi i64 %add_ln32_1, void %.split.1_ifconv, i64 0, void %.split4.1

]]></Node>
<StgValue><ssdm name="j_1"/></StgValue>
</operation>

<operation id="289" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="146" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="290" st_id="26" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="147" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_1 = icmp_eq  i64 %j_1, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_1"/></StgValue>
</operation>

<operation id="291" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="148" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_43 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_43"/></StgValue>
</operation>

<operation id="292" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="149" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_1, void %.split.1_ifconv, void %._crit_edge.loopexit.1

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="293" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="153" bw="11" op_0_bw="64">
<![CDATA[
.split.1_ifconv:2 %empty_44 = trunc i64 %j_1

]]></Node>
<StgValue><ssdm name="empty_44"/></StgValue>
</operation>

<operation id="294" st_id="26" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="155" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:4 %add_ln8_4 = add i11 %empty_44, i11 %empty_41

]]></Node>
<StgValue><ssdm name="add_ln8_4"/></StgValue>
</operation>

<operation id="295" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="156" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:5 %zext_ln8_4 = zext i11 %add_ln8_4

]]></Node>
<StgValue><ssdm name="zext_ln8_4"/></StgValue>
</operation>

<operation id="296" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="157" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:6 %arr_addr_4 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_4

]]></Node>
<StgValue><ssdm name="arr_addr_4"/></StgValue>
</operation>

<operation id="297" st_id="26" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:7 %arr_load_4 = load i11 %arr_addr_4

]]></Node>
<StgValue><ssdm name="arr_load_4"/></StgValue>
</operation>

<operation id="298" st_id="26" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="159" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:8 %add_ln8_5 = add i11 %empty_44, i11 %empty_42

]]></Node>
<StgValue><ssdm name="add_ln8_5"/></StgValue>
</operation>

<operation id="299" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="160" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:9 %zext_ln8_5 = zext i11 %add_ln8_5

]]></Node>
<StgValue><ssdm name="zext_ln8_5"/></StgValue>
</operation>

<operation id="300" st_id="26" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="161" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:10 %arr_addr_5 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_5

]]></Node>
<StgValue><ssdm name="arr_addr_5"/></StgValue>
</operation>

<operation id="301" st_id="26" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="162" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:11 %arr_load_5 = load i11 %arr_addr_5

]]></Node>
<StgValue><ssdm name="arr_load_5"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="302" st_id="27" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="158" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:7 %arr_load_4 = load i11 %arr_addr_4

]]></Node>
<StgValue><ssdm name="arr_load_4"/></StgValue>
</operation>

<operation id="303" st_id="27" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="162" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:11 %arr_load_5 = load i11 %arr_addr_5

]]></Node>
<StgValue><ssdm name="arr_load_5"/></StgValue>
</operation>

<operation id="304" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="163" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:12 %or_ln34_1 = or i11 %empty_44, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_1"/></StgValue>
</operation>

<operation id="305" st_id="27" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="164" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:13 %add_ln8_6 = add i11 %or_ln34_1, i11 %empty_41

]]></Node>
<StgValue><ssdm name="add_ln8_6"/></StgValue>
</operation>

<operation id="306" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="165" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:14 %zext_ln8_6 = zext i11 %add_ln8_6

]]></Node>
<StgValue><ssdm name="zext_ln8_6"/></StgValue>
</operation>

<operation id="307" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="166" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:15 %arr_addr_6 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_6

]]></Node>
<StgValue><ssdm name="arr_addr_6"/></StgValue>
</operation>

<operation id="308" st_id="27" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="167" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:16 %arr_load_6 = load i11 %arr_addr_6

]]></Node>
<StgValue><ssdm name="arr_load_6"/></StgValue>
</operation>

<operation id="309" st_id="27" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="168" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:17 %add_ln8_7 = add i11 %or_ln34_1, i11 %empty_42

]]></Node>
<StgValue><ssdm name="add_ln8_7"/></StgValue>
</operation>

<operation id="310" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="169" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:18 %zext_ln8_7 = zext i11 %add_ln8_7

]]></Node>
<StgValue><ssdm name="zext_ln8_7"/></StgValue>
</operation>

<operation id="311" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="170" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:19 %arr_addr_7 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_7

]]></Node>
<StgValue><ssdm name="arr_addr_7"/></StgValue>
</operation>

<operation id="312" st_id="27" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:20 %arr_load_7 = load i11 %arr_addr_7

]]></Node>
<StgValue><ssdm name="arr_load_7"/></StgValue>
</operation>

<operation id="313" st_id="27" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="185" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:34 %tmp_1046 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_5

]]></Node>
<StgValue><ssdm name="tmp_1046"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="314" st_id="28" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="151" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.1_ifconv:0 %add_ln32_1 = add i64 %j_1, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_1"/></StgValue>
</operation>

<operation id="315" st_id="28" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="167" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:16 %arr_load_6 = load i11 %arr_addr_6

]]></Node>
<StgValue><ssdm name="arr_load_6"/></StgValue>
</operation>

<operation id="316" st_id="28" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="171" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:20 %arr_load_7 = load i11 %arr_addr_7

]]></Node>
<StgValue><ssdm name="arr_load_7"/></StgValue>
</operation>

<operation id="317" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="172" bw="32" op_0_bw="32">
<![CDATA[
.split.1_ifconv:21 %bitcast_ln13_4 = bitcast i32 %arr_load_4

]]></Node>
<StgValue><ssdm name="bitcast_ln13_4"/></StgValue>
</operation>

<operation id="318" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="173" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.1_ifconv:22 %tmp_1044 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_4, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1044"/></StgValue>
</operation>

<operation id="319" st_id="28" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="174" bw="23" op_0_bw="32">
<![CDATA[
.split.1_ifconv:23 %trunc_ln13_4 = trunc i32 %bitcast_ln13_4

]]></Node>
<StgValue><ssdm name="trunc_ln13_4"/></StgValue>
</operation>

<operation id="320" st_id="28" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="178" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.1_ifconv:27 %icmp_ln13_8 = icmp_ne  i8 %tmp_1044, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_8"/></StgValue>
</operation>

<operation id="321" st_id="28" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="179" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.1_ifconv:28 %icmp_ln13_9 = icmp_eq  i23 %trunc_ln13_4, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_9"/></StgValue>
</operation>

<operation id="322" st_id="28" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="180" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:29 %or_ln13_4 = or i1 %icmp_ln13_9, i1 %icmp_ln13_8

]]></Node>
<StgValue><ssdm name="or_ln13_4"/></StgValue>
</operation>

<operation id="323" st_id="28" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="185" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:34 %tmp_1046 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_5

]]></Node>
<StgValue><ssdm name="tmp_1046"/></StgValue>
</operation>

<operation id="324" st_id="28" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="194" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:43 %tmp_1048 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_6

]]></Node>
<StgValue><ssdm name="tmp_1048"/></StgValue>
</operation>

<operation id="325" st_id="28" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="203" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:52 %tmp_1050 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1050"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="326" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="175" bw="32" op_0_bw="32">
<![CDATA[
.split.1_ifconv:24 %bitcast_ln13_5 = bitcast i32 %arr_load_5

]]></Node>
<StgValue><ssdm name="bitcast_ln13_5"/></StgValue>
</operation>

<operation id="327" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="176" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.1_ifconv:25 %tmp_1045 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_5, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1045"/></StgValue>
</operation>

<operation id="328" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="177" bw="23" op_0_bw="32">
<![CDATA[
.split.1_ifconv:26 %trunc_ln13_5 = trunc i32 %bitcast_ln13_5

]]></Node>
<StgValue><ssdm name="trunc_ln13_5"/></StgValue>
</operation>

<operation id="329" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="181" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.1_ifconv:30 %icmp_ln13_10 = icmp_ne  i8 %tmp_1045, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_10"/></StgValue>
</operation>

<operation id="330" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="182" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.1_ifconv:31 %icmp_ln13_11 = icmp_eq  i23 %trunc_ln13_5, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_11"/></StgValue>
</operation>

<operation id="331" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="183" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:32 %or_ln13_5 = or i1 %icmp_ln13_11, i1 %icmp_ln13_10

]]></Node>
<StgValue><ssdm name="or_ln13_5"/></StgValue>
</operation>

<operation id="332" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="184" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:33 %and_ln13_8 = and i1 %or_ln13_4, i1 %or_ln13_5

]]></Node>
<StgValue><ssdm name="and_ln13_8"/></StgValue>
</operation>

<operation id="333" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="186" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:35 %and_ln13_9 = and i1 %and_ln13_8, i1 %tmp_1046

]]></Node>
<StgValue><ssdm name="and_ln13_9"/></StgValue>
</operation>

<operation id="334" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="187" bw="32" op_0_bw="32">
<![CDATA[
.split.1_ifconv:36 %bitcast_ln13_6 = bitcast i32 %arr_load_6

]]></Node>
<StgValue><ssdm name="bitcast_ln13_6"/></StgValue>
</operation>

<operation id="335" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="188" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.1_ifconv:37 %tmp_1047 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_6, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1047"/></StgValue>
</operation>

<operation id="336" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="189" bw="23" op_0_bw="32">
<![CDATA[
.split.1_ifconv:38 %trunc_ln13_6 = trunc i32 %bitcast_ln13_6

]]></Node>
<StgValue><ssdm name="trunc_ln13_6"/></StgValue>
</operation>

<operation id="337" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="190" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.1_ifconv:39 %icmp_ln13_12 = icmp_ne  i8 %tmp_1047, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_12"/></StgValue>
</operation>

<operation id="338" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="191" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.1_ifconv:40 %icmp_ln13_13 = icmp_eq  i23 %trunc_ln13_6, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_13"/></StgValue>
</operation>

<operation id="339" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="192" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:41 %or_ln13_6 = or i1 %icmp_ln13_13, i1 %icmp_ln13_12

]]></Node>
<StgValue><ssdm name="or_ln13_6"/></StgValue>
</operation>

<operation id="340" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="193" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:42 %and_ln13_10 = and i1 %or_ln13_4, i1 %or_ln13_6

]]></Node>
<StgValue><ssdm name="and_ln13_10"/></StgValue>
</operation>

<operation id="341" st_id="29" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="194" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:43 %tmp_1048 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_6

]]></Node>
<StgValue><ssdm name="tmp_1048"/></StgValue>
</operation>

<operation id="342" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="195" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:44 %and_ln13_20 = and i1 %and_ln13_10, i1 %tmp_1048

]]></Node>
<StgValue><ssdm name="and_ln13_20"/></StgValue>
</operation>

<operation id="343" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="196" bw="32" op_0_bw="32">
<![CDATA[
.split.1_ifconv:45 %bitcast_ln13_7 = bitcast i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="bitcast_ln13_7"/></StgValue>
</operation>

<operation id="344" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="197" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.1_ifconv:46 %tmp_1049 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_7, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1049"/></StgValue>
</operation>

<operation id="345" st_id="29" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="198" bw="23" op_0_bw="32">
<![CDATA[
.split.1_ifconv:47 %trunc_ln13_7 = trunc i32 %bitcast_ln13_7

]]></Node>
<StgValue><ssdm name="trunc_ln13_7"/></StgValue>
</operation>

<operation id="346" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="199" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.1_ifconv:48 %icmp_ln13_14 = icmp_ne  i8 %tmp_1049, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_14"/></StgValue>
</operation>

<operation id="347" st_id="29" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="200" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.1_ifconv:49 %icmp_ln13_15 = icmp_eq  i23 %trunc_ln13_7, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_15"/></StgValue>
</operation>

<operation id="348" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="201" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:50 %or_ln13_7 = or i1 %icmp_ln13_15, i1 %icmp_ln13_14

]]></Node>
<StgValue><ssdm name="or_ln13_7"/></StgValue>
</operation>

<operation id="349" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="202" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:51 %and_ln13_21 = and i1 %or_ln13_4, i1 %or_ln13_7

]]></Node>
<StgValue><ssdm name="and_ln13_21"/></StgValue>
</operation>

<operation id="350" st_id="29" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="203" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:52 %tmp_1050 = fcmp_ogt  i32 %arr_load_4, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1050"/></StgValue>
</operation>

<operation id="351" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="204" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:53 %and_ln13_22 = and i1 %and_ln13_21, i1 %tmp_1050

]]></Node>
<StgValue><ssdm name="and_ln13_22"/></StgValue>
</operation>

<operation id="352" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="205" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:54 %and_ln13_23 = and i1 %and_ln13_20, i1 %and_ln13_22

]]></Node>
<StgValue><ssdm name="and_ln13_23"/></StgValue>
</operation>

<operation id="353" st_id="29" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="206" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:55 %and_ln13_11 = and i1 %and_ln13_23, i1 %and_ln13_9

]]></Node>
<StgValue><ssdm name="and_ln13_11"/></StgValue>
</operation>

<operation id="354" st_id="29" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="208" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:57 %tmp_1051 = fcmp_ogt  i32 %arr_load_5, i32 %arr_load_6

]]></Node>
<StgValue><ssdm name="tmp_1051"/></StgValue>
</operation>

<operation id="355" st_id="29" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="211" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:60 %tmp_1052 = fcmp_ogt  i32 %arr_load_5, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1052"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="356" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="207" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:56 %and_ln16_15 = and i1 %or_ln13_5, i1 %or_ln13_6

]]></Node>
<StgValue><ssdm name="and_ln16_15"/></StgValue>
</operation>

<operation id="357" st_id="30" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="208" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:57 %tmp_1051 = fcmp_ogt  i32 %arr_load_5, i32 %arr_load_6

]]></Node>
<StgValue><ssdm name="tmp_1051"/></StgValue>
</operation>

<operation id="358" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="209" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:58 %and_ln16_16 = and i1 %and_ln16_15, i1 %tmp_1051

]]></Node>
<StgValue><ssdm name="and_ln16_16"/></StgValue>
</operation>

<operation id="359" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="210" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:59 %and_ln16_17 = and i1 %or_ln13_5, i1 %or_ln13_7

]]></Node>
<StgValue><ssdm name="and_ln16_17"/></StgValue>
</operation>

<operation id="360" st_id="30" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="211" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:60 %tmp_1052 = fcmp_ogt  i32 %arr_load_5, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1052"/></StgValue>
</operation>

<operation id="361" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="212" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:61 %and_ln16_18 = and i1 %and_ln16_17, i1 %tmp_1052

]]></Node>
<StgValue><ssdm name="and_ln16_18"/></StgValue>
</operation>

<operation id="362" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="213" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:62 %and_ln16_1 = and i1 %and_ln16_16, i1 %and_ln16_18

]]></Node>
<StgValue><ssdm name="and_ln16_1"/></StgValue>
</operation>

<operation id="363" st_id="30" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="215" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:64 %tmp_1053 = fcmp_ogt  i32 %arr_load_6, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1053"/></StgValue>
</operation>

<operation id="364" st_id="30" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="217" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.1_ifconv:66 %select_ln13_1 = select i1 %and_ln13_11, i11 %add_ln8_4, i11 %add_ln8_7

]]></Node>
<StgValue><ssdm name="select_ln13_1"/></StgValue>
</operation>

<operation id="365" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="218" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:67 %xor_ln13_1 = xor i1 %and_ln13_11, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_1"/></StgValue>
</operation>

<operation id="366" st_id="30" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="219" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:68 %and_ln16_19 = and i1 %and_ln16_1, i1 %xor_ln13_1

]]></Node>
<StgValue><ssdm name="and_ln16_19"/></StgValue>
</operation>

<operation id="367" st_id="30" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="220" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.1_ifconv:69 %select_ln16_1 = select i1 %and_ln16_19, i11 %add_ln8_5, i11 %select_ln13_1

]]></Node>
<StgValue><ssdm name="select_ln16_1"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="368" st_id="31" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="214" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:63 %and_ln19_3 = and i1 %or_ln13_6, i1 %or_ln13_7

]]></Node>
<StgValue><ssdm name="and_ln19_3"/></StgValue>
</operation>

<operation id="369" st_id="31" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="215" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.1_ifconv:64 %tmp_1053 = fcmp_ogt  i32 %arr_load_6, i32 %arr_load_7

]]></Node>
<StgValue><ssdm name="tmp_1053"/></StgValue>
</operation>

<operation id="370" st_id="31" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="216" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:65 %and_ln19_4 = and i1 %and_ln19_3, i1 %tmp_1053

]]></Node>
<StgValue><ssdm name="and_ln19_4"/></StgValue>
</operation>

<operation id="371" st_id="31" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="221" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:70 %or_ln16_1 = or i1 %and_ln13_11, i1 %and_ln16_1

]]></Node>
<StgValue><ssdm name="or_ln16_1"/></StgValue>
</operation>

<operation id="372" st_id="31" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="222" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:71 %xor_ln16_1 = xor i1 %or_ln16_1, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_1"/></StgValue>
</operation>

<operation id="373" st_id="31" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="223" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.1_ifconv:72 %and_ln19_5 = and i1 %and_ln19_4, i1 %xor_ln16_1

]]></Node>
<StgValue><ssdm name="and_ln19_5"/></StgValue>
</operation>

<operation id="374" st_id="31" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="224" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.1_ifconv:73 %select_ln19_1 = select i1 %and_ln19_5, i11 %add_ln8_6, i11 %select_ln16_1

]]></Node>
<StgValue><ssdm name="select_ln19_1"/></StgValue>
</operation>

<operation id="375" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="225" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:74 %zext_ln8_41 = zext i11 %select_ln19_1

]]></Node>
<StgValue><ssdm name="zext_ln8_41"/></StgValue>
</operation>

<operation id="376" st_id="31" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="226" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:75 %arr_addr_41 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_41

]]></Node>
<StgValue><ssdm name="arr_addr_41"/></StgValue>
</operation>

<operation id="377" st_id="31" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="227" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:76 %arr_load_41 = load i11 %arr_addr_41

]]></Node>
<StgValue><ssdm name="arr_load_41"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">

<operation id="378" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="152" bw="64" op_0_bw="11">
<![CDATA[
.split.1_ifconv:1 %t_1_1_cast = zext i11 %t_1_1

]]></Node>
<StgValue><ssdm name="t_1_1_cast"/></StgValue>
</operation>

<operation id="379" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="154" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.1_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="380" st_id="32" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="227" bw="32" op_0_bw="11">
<![CDATA[
.split.1_ifconv:76 %arr_load_41 = load i11 %arr_addr_41

]]></Node>
<StgValue><ssdm name="arr_load_41"/></StgValue>
</operation>

<operation id="381" st_id="32" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="228" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.1_ifconv:77 %add_ln34_1 = add i11 %t_1_1, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_1"/></StgValue>
</operation>

<operation id="382" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="229" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.1_ifconv:78 %out_addr_1 = getelementptr i32 %out_r, i64 0, i64 %t_1_1_cast

]]></Node>
<StgValue><ssdm name="out_addr_1"/></StgValue>
</operation>

<operation id="383" st_id="32" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="230" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.1_ifconv:79 %store_ln34 = store i32 %arr_load_41, i11 %out_addr_1

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="384" st_id="32" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_1" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="231" bw="0" op_0_bw="0">
<![CDATA[
.split.1_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="33" st_id="33">

<operation id="385" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="233" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.1:0 %trunc_ln29_2 = trunc i32 %add_ln29_2

]]></Node>
<StgValue><ssdm name="trunc_ln29_2"/></StgValue>
</operation>

<operation id="386" st_id="33" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="234" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.1:1 %add_ln29_3 = add i32 %zext_ln29_3, i32 %add_ln29_2

]]></Node>
<StgValue><ssdm name="add_ln29_3"/></StgValue>
</operation>

<operation id="387" st_id="33" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="235" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.1:2 %add_ln29_4 = add i64 %i_0, i64 4

]]></Node>
<StgValue><ssdm name="add_ln29_4"/></StgValue>
</operation>

<operation id="388" st_id="33" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="236" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.1:3 %add_ln29_5 = add i11 %trunc_ln29_1, i11 4

]]></Node>
<StgValue><ssdm name="add_ln29_5"/></StgValue>
</operation>

<operation id="389" st_id="33" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="237" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.1:4 %icmp_ln29_2 = icmp_slt  i64 %add_ln29_4, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_2"/></StgValue>
</operation>

<operation id="390" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="238" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.1:5 %br_ln29 = br i1 %icmp_ln29_2, void %._crit_edge10, void %.split4.2

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="391" st_id="33" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_2" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="240" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:0 %empty_45 = or i11 %add_ln29_5, i11 1

]]></Node>
<StgValue><ssdm name="empty_45"/></StgValue>
</operation>

<operation id="392" st_id="33" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_2" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="241" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:1 %empty_46 = mul i11 %add_ln29_5, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_46"/></StgValue>
</operation>

<operation id="393" st_id="33" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_2" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="242" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:2 %empty_47 = mul i11 %empty_45, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_47"/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="394" st_id="34" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="241" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:1 %empty_46 = mul i11 %add_ln29_5, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_46"/></StgValue>
</operation>

<operation id="395" st_id="34" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="242" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:2 %empty_47 = mul i11 %empty_45, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_47"/></StgValue>
</operation>
</state>

<state id="35" st_id="35">

<operation id="396" st_id="35" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="241" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:1 %empty_46 = mul i11 %add_ln29_5, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_46"/></StgValue>
</operation>

<operation id="397" st_id="35" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="242" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:2 %empty_47 = mul i11 %empty_45, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_47"/></StgValue>
</operation>
</state>

<state id="36" st_id="36">

<operation id="398" st_id="36" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="241" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:1 %empty_46 = mul i11 %add_ln29_5, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_46"/></StgValue>
</operation>

<operation id="399" st_id="36" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="242" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:2 %empty_47 = mul i11 %empty_45, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_47"/></StgValue>
</operation>

<operation id="400" st_id="36" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="243" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.2:3 %add_ln32_11 = add i11 %zext_ln29_4, i11 %trunc_ln29_2

]]></Node>
<StgValue><ssdm name="add_ln32_11"/></StgValue>
</operation>

<operation id="401" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="244" bw="0" op_0_bw="0">
<![CDATA[
.split4.2:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="37" st_id="37">

<operation id="402" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="246" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_2 = phi i11 %add_ln34_2, void %.split.2_ifconv, i11 %add_ln32_11, void %.split4.2

]]></Node>
<StgValue><ssdm name="t_1_2"/></StgValue>
</operation>

<operation id="403" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="247" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_2 = phi i64 %add_ln32_2, void %.split.2_ifconv, i64 0, void %.split4.2

]]></Node>
<StgValue><ssdm name="j_2"/></StgValue>
</operation>

<operation id="404" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="248" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="405" st_id="37" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="249" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_2 = icmp_eq  i64 %j_2, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_2"/></StgValue>
</operation>

<operation id="406" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="250" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_48 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_48"/></StgValue>
</operation>

<operation id="407" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="251" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_2, void %.split.2_ifconv, void %._crit_edge.loopexit.2

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="408" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="255" bw="11" op_0_bw="64">
<![CDATA[
.split.2_ifconv:2 %empty_49 = trunc i64 %j_2

]]></Node>
<StgValue><ssdm name="empty_49"/></StgValue>
</operation>

<operation id="409" st_id="37" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="257" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:4 %add_ln8_8 = add i11 %empty_49, i11 %empty_46

]]></Node>
<StgValue><ssdm name="add_ln8_8"/></StgValue>
</operation>

<operation id="410" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="258" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:5 %zext_ln8_8 = zext i11 %add_ln8_8

]]></Node>
<StgValue><ssdm name="zext_ln8_8"/></StgValue>
</operation>

<operation id="411" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="259" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:6 %arr_addr_8 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_8

]]></Node>
<StgValue><ssdm name="arr_addr_8"/></StgValue>
</operation>

<operation id="412" st_id="37" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:7 %arr_load_8 = load i11 %arr_addr_8

]]></Node>
<StgValue><ssdm name="arr_load_8"/></StgValue>
</operation>

<operation id="413" st_id="37" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="261" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:8 %add_ln8_9 = add i11 %empty_49, i11 %empty_47

]]></Node>
<StgValue><ssdm name="add_ln8_9"/></StgValue>
</operation>

<operation id="414" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="262" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:9 %zext_ln8_9 = zext i11 %add_ln8_9

]]></Node>
<StgValue><ssdm name="zext_ln8_9"/></StgValue>
</operation>

<operation id="415" st_id="37" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="263" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:10 %arr_addr_9 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_9

]]></Node>
<StgValue><ssdm name="arr_addr_9"/></StgValue>
</operation>

<operation id="416" st_id="37" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="264" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:11 %arr_load_9 = load i11 %arr_addr_9

]]></Node>
<StgValue><ssdm name="arr_load_9"/></StgValue>
</operation>
</state>

<state id="38" st_id="38">

<operation id="417" st_id="38" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="260" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:7 %arr_load_8 = load i11 %arr_addr_8

]]></Node>
<StgValue><ssdm name="arr_load_8"/></StgValue>
</operation>

<operation id="418" st_id="38" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="264" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:11 %arr_load_9 = load i11 %arr_addr_9

]]></Node>
<StgValue><ssdm name="arr_load_9"/></StgValue>
</operation>

<operation id="419" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="265" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:12 %or_ln34_2 = or i11 %empty_49, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_2"/></StgValue>
</operation>

<operation id="420" st_id="38" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="266" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:13 %add_ln8_10 = add i11 %or_ln34_2, i11 %empty_46

]]></Node>
<StgValue><ssdm name="add_ln8_10"/></StgValue>
</operation>

<operation id="421" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="267" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:14 %zext_ln8_10 = zext i11 %add_ln8_10

]]></Node>
<StgValue><ssdm name="zext_ln8_10"/></StgValue>
</operation>

<operation id="422" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="268" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:15 %arr_addr_10 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_10

]]></Node>
<StgValue><ssdm name="arr_addr_10"/></StgValue>
</operation>

<operation id="423" st_id="38" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="269" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:16 %arr_load_10 = load i11 %arr_addr_10

]]></Node>
<StgValue><ssdm name="arr_load_10"/></StgValue>
</operation>

<operation id="424" st_id="38" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="270" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:17 %add_ln8_11 = add i11 %or_ln34_2, i11 %empty_47

]]></Node>
<StgValue><ssdm name="add_ln8_11"/></StgValue>
</operation>

<operation id="425" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="271" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:18 %zext_ln8_11 = zext i11 %add_ln8_11

]]></Node>
<StgValue><ssdm name="zext_ln8_11"/></StgValue>
</operation>

<operation id="426" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="272" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:19 %arr_addr_11 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_11

]]></Node>
<StgValue><ssdm name="arr_addr_11"/></StgValue>
</operation>

<operation id="427" st_id="38" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="273" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:20 %arr_load_11 = load i11 %arr_addr_11

]]></Node>
<StgValue><ssdm name="arr_load_11"/></StgValue>
</operation>

<operation id="428" st_id="38" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="287" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:34 %tmp_1056 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_9

]]></Node>
<StgValue><ssdm name="tmp_1056"/></StgValue>
</operation>
</state>

<state id="39" st_id="39">

<operation id="429" st_id="39" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="253" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.2_ifconv:0 %add_ln32_2 = add i64 %j_2, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_2"/></StgValue>
</operation>

<operation id="430" st_id="39" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="269" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:16 %arr_load_10 = load i11 %arr_addr_10

]]></Node>
<StgValue><ssdm name="arr_load_10"/></StgValue>
</operation>

<operation id="431" st_id="39" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="273" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:20 %arr_load_11 = load i11 %arr_addr_11

]]></Node>
<StgValue><ssdm name="arr_load_11"/></StgValue>
</operation>

<operation id="432" st_id="39" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="274" bw="32" op_0_bw="32">
<![CDATA[
.split.2_ifconv:21 %bitcast_ln13_8 = bitcast i32 %arr_load_8

]]></Node>
<StgValue><ssdm name="bitcast_ln13_8"/></StgValue>
</operation>

<operation id="433" st_id="39" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="275" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.2_ifconv:22 %tmp_1054 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_8, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1054"/></StgValue>
</operation>

<operation id="434" st_id="39" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="276" bw="23" op_0_bw="32">
<![CDATA[
.split.2_ifconv:23 %trunc_ln13_8 = trunc i32 %bitcast_ln13_8

]]></Node>
<StgValue><ssdm name="trunc_ln13_8"/></StgValue>
</operation>

<operation id="435" st_id="39" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="280" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.2_ifconv:27 %icmp_ln13_16 = icmp_ne  i8 %tmp_1054, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_16"/></StgValue>
</operation>

<operation id="436" st_id="39" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="281" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.2_ifconv:28 %icmp_ln13_17 = icmp_eq  i23 %trunc_ln13_8, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_17"/></StgValue>
</operation>

<operation id="437" st_id="39" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="282" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:29 %or_ln13_8 = or i1 %icmp_ln13_17, i1 %icmp_ln13_16

]]></Node>
<StgValue><ssdm name="or_ln13_8"/></StgValue>
</operation>

<operation id="438" st_id="39" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="287" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:34 %tmp_1056 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_9

]]></Node>
<StgValue><ssdm name="tmp_1056"/></StgValue>
</operation>

<operation id="439" st_id="39" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="296" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:43 %tmp_1058 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_10

]]></Node>
<StgValue><ssdm name="tmp_1058"/></StgValue>
</operation>

<operation id="440" st_id="39" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="305" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:52 %tmp_1060 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1060"/></StgValue>
</operation>
</state>

<state id="40" st_id="40">

<operation id="441" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="277" bw="32" op_0_bw="32">
<![CDATA[
.split.2_ifconv:24 %bitcast_ln13_9 = bitcast i32 %arr_load_9

]]></Node>
<StgValue><ssdm name="bitcast_ln13_9"/></StgValue>
</operation>

<operation id="442" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="278" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.2_ifconv:25 %tmp_1055 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_9, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1055"/></StgValue>
</operation>

<operation id="443" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="279" bw="23" op_0_bw="32">
<![CDATA[
.split.2_ifconv:26 %trunc_ln13_9 = trunc i32 %bitcast_ln13_9

]]></Node>
<StgValue><ssdm name="trunc_ln13_9"/></StgValue>
</operation>

<operation id="444" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="283" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.2_ifconv:30 %icmp_ln13_18 = icmp_ne  i8 %tmp_1055, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_18"/></StgValue>
</operation>

<operation id="445" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="284" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.2_ifconv:31 %icmp_ln13_19 = icmp_eq  i23 %trunc_ln13_9, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_19"/></StgValue>
</operation>

<operation id="446" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="285" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:32 %or_ln13_9 = or i1 %icmp_ln13_19, i1 %icmp_ln13_18

]]></Node>
<StgValue><ssdm name="or_ln13_9"/></StgValue>
</operation>

<operation id="447" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="286" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:33 %and_ln13_24 = and i1 %or_ln13_8, i1 %or_ln13_9

]]></Node>
<StgValue><ssdm name="and_ln13_24"/></StgValue>
</operation>

<operation id="448" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="288" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:35 %and_ln13_25 = and i1 %and_ln13_24, i1 %tmp_1056

]]></Node>
<StgValue><ssdm name="and_ln13_25"/></StgValue>
</operation>

<operation id="449" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="289" bw="32" op_0_bw="32">
<![CDATA[
.split.2_ifconv:36 %bitcast_ln13_10 = bitcast i32 %arr_load_10

]]></Node>
<StgValue><ssdm name="bitcast_ln13_10"/></StgValue>
</operation>

<operation id="450" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="290" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.2_ifconv:37 %tmp_1057 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_10, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1057"/></StgValue>
</operation>

<operation id="451" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="291" bw="23" op_0_bw="32">
<![CDATA[
.split.2_ifconv:38 %trunc_ln13_10 = trunc i32 %bitcast_ln13_10

]]></Node>
<StgValue><ssdm name="trunc_ln13_10"/></StgValue>
</operation>

<operation id="452" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="292" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.2_ifconv:39 %icmp_ln13_20 = icmp_ne  i8 %tmp_1057, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_20"/></StgValue>
</operation>

<operation id="453" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="293" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.2_ifconv:40 %icmp_ln13_21 = icmp_eq  i23 %trunc_ln13_10, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_21"/></StgValue>
</operation>

<operation id="454" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="294" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:41 %or_ln13_10 = or i1 %icmp_ln13_21, i1 %icmp_ln13_20

]]></Node>
<StgValue><ssdm name="or_ln13_10"/></StgValue>
</operation>

<operation id="455" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="295" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:42 %and_ln13_26 = and i1 %or_ln13_8, i1 %or_ln13_10

]]></Node>
<StgValue><ssdm name="and_ln13_26"/></StgValue>
</operation>

<operation id="456" st_id="40" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="296" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:43 %tmp_1058 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_10

]]></Node>
<StgValue><ssdm name="tmp_1058"/></StgValue>
</operation>

<operation id="457" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="297" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:44 %and_ln13_27 = and i1 %and_ln13_26, i1 %tmp_1058

]]></Node>
<StgValue><ssdm name="and_ln13_27"/></StgValue>
</operation>

<operation id="458" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="298" bw="32" op_0_bw="32">
<![CDATA[
.split.2_ifconv:45 %bitcast_ln13_11 = bitcast i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="bitcast_ln13_11"/></StgValue>
</operation>

<operation id="459" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="299" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.2_ifconv:46 %tmp_1059 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_11, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1059"/></StgValue>
</operation>

<operation id="460" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="300" bw="23" op_0_bw="32">
<![CDATA[
.split.2_ifconv:47 %trunc_ln13_11 = trunc i32 %bitcast_ln13_11

]]></Node>
<StgValue><ssdm name="trunc_ln13_11"/></StgValue>
</operation>

<operation id="461" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="301" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.2_ifconv:48 %icmp_ln13_22 = icmp_ne  i8 %tmp_1059, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_22"/></StgValue>
</operation>

<operation id="462" st_id="40" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="302" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.2_ifconv:49 %icmp_ln13_23 = icmp_eq  i23 %trunc_ln13_11, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_23"/></StgValue>
</operation>

<operation id="463" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="303" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:50 %or_ln13_11 = or i1 %icmp_ln13_23, i1 %icmp_ln13_22

]]></Node>
<StgValue><ssdm name="or_ln13_11"/></StgValue>
</operation>

<operation id="464" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="304" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:51 %and_ln13_28 = and i1 %or_ln13_8, i1 %or_ln13_11

]]></Node>
<StgValue><ssdm name="and_ln13_28"/></StgValue>
</operation>

<operation id="465" st_id="40" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="305" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:52 %tmp_1060 = fcmp_ogt  i32 %arr_load_8, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1060"/></StgValue>
</operation>

<operation id="466" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="306" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:53 %and_ln13_29 = and i1 %and_ln13_28, i1 %tmp_1060

]]></Node>
<StgValue><ssdm name="and_ln13_29"/></StgValue>
</operation>

<operation id="467" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="307" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:54 %and_ln13_30 = and i1 %and_ln13_27, i1 %and_ln13_29

]]></Node>
<StgValue><ssdm name="and_ln13_30"/></StgValue>
</operation>

<operation id="468" st_id="40" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="308" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:55 %and_ln13_12 = and i1 %and_ln13_30, i1 %and_ln13_25

]]></Node>
<StgValue><ssdm name="and_ln13_12"/></StgValue>
</operation>

<operation id="469" st_id="40" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="310" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:57 %tmp_1061 = fcmp_ogt  i32 %arr_load_9, i32 %arr_load_10

]]></Node>
<StgValue><ssdm name="tmp_1061"/></StgValue>
</operation>

<operation id="470" st_id="40" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="313" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:60 %tmp_1062 = fcmp_ogt  i32 %arr_load_9, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1062"/></StgValue>
</operation>
</state>

<state id="41" st_id="41">

<operation id="471" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="309" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:56 %and_ln16_20 = and i1 %or_ln13_9, i1 %or_ln13_10

]]></Node>
<StgValue><ssdm name="and_ln16_20"/></StgValue>
</operation>

<operation id="472" st_id="41" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="310" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:57 %tmp_1061 = fcmp_ogt  i32 %arr_load_9, i32 %arr_load_10

]]></Node>
<StgValue><ssdm name="tmp_1061"/></StgValue>
</operation>

<operation id="473" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="311" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:58 %and_ln16_21 = and i1 %and_ln16_20, i1 %tmp_1061

]]></Node>
<StgValue><ssdm name="and_ln16_21"/></StgValue>
</operation>

<operation id="474" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="312" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:59 %and_ln16_22 = and i1 %or_ln13_9, i1 %or_ln13_11

]]></Node>
<StgValue><ssdm name="and_ln16_22"/></StgValue>
</operation>

<operation id="475" st_id="41" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="313" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:60 %tmp_1062 = fcmp_ogt  i32 %arr_load_9, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1062"/></StgValue>
</operation>

<operation id="476" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="314" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:61 %and_ln16_23 = and i1 %and_ln16_22, i1 %tmp_1062

]]></Node>
<StgValue><ssdm name="and_ln16_23"/></StgValue>
</operation>

<operation id="477" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="315" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:62 %and_ln16_2 = and i1 %and_ln16_21, i1 %and_ln16_23

]]></Node>
<StgValue><ssdm name="and_ln16_2"/></StgValue>
</operation>

<operation id="478" st_id="41" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:64 %tmp_1063 = fcmp_ogt  i32 %arr_load_10, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1063"/></StgValue>
</operation>

<operation id="479" st_id="41" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="319" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.2_ifconv:66 %select_ln13_2 = select i1 %and_ln13_12, i11 %add_ln8_8, i11 %add_ln8_11

]]></Node>
<StgValue><ssdm name="select_ln13_2"/></StgValue>
</operation>

<operation id="480" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="320" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:67 %xor_ln13_2 = xor i1 %and_ln13_12, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_2"/></StgValue>
</operation>

<operation id="481" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="321" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:68 %and_ln16_24 = and i1 %and_ln16_2, i1 %xor_ln13_2

]]></Node>
<StgValue><ssdm name="and_ln16_24"/></StgValue>
</operation>

<operation id="482" st_id="41" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="322" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.2_ifconv:69 %select_ln16_2 = select i1 %and_ln16_24, i11 %add_ln8_9, i11 %select_ln13_2

]]></Node>
<StgValue><ssdm name="select_ln16_2"/></StgValue>
</operation>
</state>

<state id="42" st_id="42">

<operation id="483" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="316" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:63 %and_ln19_6 = and i1 %or_ln13_10, i1 %or_ln13_11

]]></Node>
<StgValue><ssdm name="and_ln19_6"/></StgValue>
</operation>

<operation id="484" st_id="42" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="317" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.2_ifconv:64 %tmp_1063 = fcmp_ogt  i32 %arr_load_10, i32 %arr_load_11

]]></Node>
<StgValue><ssdm name="tmp_1063"/></StgValue>
</operation>

<operation id="485" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="318" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:65 %and_ln19_7 = and i1 %and_ln19_6, i1 %tmp_1063

]]></Node>
<StgValue><ssdm name="and_ln19_7"/></StgValue>
</operation>

<operation id="486" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="323" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:70 %or_ln16_2 = or i1 %and_ln13_12, i1 %and_ln16_2

]]></Node>
<StgValue><ssdm name="or_ln16_2"/></StgValue>
</operation>

<operation id="487" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="324" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:71 %xor_ln16_2 = xor i1 %or_ln16_2, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_2"/></StgValue>
</operation>

<operation id="488" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="325" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.2_ifconv:72 %and_ln19_8 = and i1 %and_ln19_7, i1 %xor_ln16_2

]]></Node>
<StgValue><ssdm name="and_ln19_8"/></StgValue>
</operation>

<operation id="489" st_id="42" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="326" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.2_ifconv:73 %select_ln19_2 = select i1 %and_ln19_8, i11 %add_ln8_10, i11 %select_ln16_2

]]></Node>
<StgValue><ssdm name="select_ln19_2"/></StgValue>
</operation>

<operation id="490" st_id="42" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="327" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:74 %zext_ln8_42 = zext i11 %select_ln19_2

]]></Node>
<StgValue><ssdm name="zext_ln8_42"/></StgValue>
</operation>

<operation id="491" st_id="42" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="328" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:75 %arr_addr_42 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_42

]]></Node>
<StgValue><ssdm name="arr_addr_42"/></StgValue>
</operation>

<operation id="492" st_id="42" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:76 %arr_load_42 = load i11 %arr_addr_42

]]></Node>
<StgValue><ssdm name="arr_load_42"/></StgValue>
</operation>
</state>

<state id="43" st_id="43">

<operation id="493" st_id="43" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="254" bw="64" op_0_bw="11">
<![CDATA[
.split.2_ifconv:1 %t_1_2_cast = zext i11 %t_1_2

]]></Node>
<StgValue><ssdm name="t_1_2_cast"/></StgValue>
</operation>

<operation id="494" st_id="43" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="256" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.2_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="495" st_id="43" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="329" bw="32" op_0_bw="11">
<![CDATA[
.split.2_ifconv:76 %arr_load_42 = load i11 %arr_addr_42

]]></Node>
<StgValue><ssdm name="arr_load_42"/></StgValue>
</operation>

<operation id="496" st_id="43" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="330" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.2_ifconv:77 %add_ln34_2 = add i11 %t_1_2, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_2"/></StgValue>
</operation>

<operation id="497" st_id="43" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="331" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.2_ifconv:78 %out_addr_2 = getelementptr i32 %out_r, i64 0, i64 %t_1_2_cast

]]></Node>
<StgValue><ssdm name="out_addr_2"/></StgValue>
</operation>

<operation id="498" st_id="43" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="332" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.2_ifconv:79 %store_ln34 = store i32 %arr_load_42, i11 %out_addr_2

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="499" st_id="43" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_2" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="333" bw="0" op_0_bw="0">
<![CDATA[
.split.2_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="44" st_id="44">

<operation id="500" st_id="44" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="335" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.2:0 %trunc_ln29_3 = trunc i32 %add_ln29_3

]]></Node>
<StgValue><ssdm name="trunc_ln29_3"/></StgValue>
</operation>

<operation id="501" st_id="44" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="336" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.2:1 %add_ln29_6 = add i32 %zext_ln29_3, i32 %add_ln29_3

]]></Node>
<StgValue><ssdm name="add_ln29_6"/></StgValue>
</operation>

<operation id="502" st_id="44" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="337" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.2:2 %add_ln29_7 = add i64 %i_0, i64 6

]]></Node>
<StgValue><ssdm name="add_ln29_7"/></StgValue>
</operation>

<operation id="503" st_id="44" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="338" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.2:3 %add_ln29_8 = add i11 %trunc_ln29_1, i11 6

]]></Node>
<StgValue><ssdm name="add_ln29_8"/></StgValue>
</operation>

<operation id="504" st_id="44" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="339" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.2:4 %icmp_ln29_3 = icmp_slt  i64 %add_ln29_7, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_3"/></StgValue>
</operation>

<operation id="505" st_id="44" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="340" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.2:5 %br_ln29 = br i1 %icmp_ln29_3, void %._crit_edge10, void %.split4.3

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="506" st_id="44" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_3" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="342" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:0 %empty_50 = or i11 %add_ln29_8, i11 1

]]></Node>
<StgValue><ssdm name="empty_50"/></StgValue>
</operation>

<operation id="507" st_id="44" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_3" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="343" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:1 %empty_51 = mul i11 %add_ln29_8, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_51"/></StgValue>
</operation>

<operation id="508" st_id="44" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_3" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="344" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:2 %empty_52 = mul i11 %empty_50, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_52"/></StgValue>
</operation>
</state>

<state id="45" st_id="45">

<operation id="509" st_id="45" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="343" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:1 %empty_51 = mul i11 %add_ln29_8, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_51"/></StgValue>
</operation>

<operation id="510" st_id="45" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="344" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:2 %empty_52 = mul i11 %empty_50, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_52"/></StgValue>
</operation>
</state>

<state id="46" st_id="46">

<operation id="511" st_id="46" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="343" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:1 %empty_51 = mul i11 %add_ln29_8, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_51"/></StgValue>
</operation>

<operation id="512" st_id="46" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="344" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:2 %empty_52 = mul i11 %empty_50, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_52"/></StgValue>
</operation>
</state>

<state id="47" st_id="47">

<operation id="513" st_id="47" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="343" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:1 %empty_51 = mul i11 %add_ln29_8, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_51"/></StgValue>
</operation>

<operation id="514" st_id="47" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="344" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:2 %empty_52 = mul i11 %empty_50, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_52"/></StgValue>
</operation>

<operation id="515" st_id="47" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="345" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.3:3 %add_ln32_12 = add i11 %zext_ln29_4, i11 %trunc_ln29_3

]]></Node>
<StgValue><ssdm name="add_ln32_12"/></StgValue>
</operation>

<operation id="516" st_id="47" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="346" bw="0" op_0_bw="0">
<![CDATA[
.split4.3:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="48" st_id="48">

<operation id="517" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="348" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_3 = phi i11 %add_ln34_3, void %.split.3_ifconv, i11 %add_ln32_12, void %.split4.3

]]></Node>
<StgValue><ssdm name="t_1_3"/></StgValue>
</operation>

<operation id="518" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="349" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_3 = phi i64 %add_ln32_3, void %.split.3_ifconv, i64 0, void %.split4.3

]]></Node>
<StgValue><ssdm name="j_3"/></StgValue>
</operation>

<operation id="519" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="350" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="520" st_id="48" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="351" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_3 = icmp_eq  i64 %j_3, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_3"/></StgValue>
</operation>

<operation id="521" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="352" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_53 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_53"/></StgValue>
</operation>

<operation id="522" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="353" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_3, void %.split.3_ifconv, void %._crit_edge.loopexit.3

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="523" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="357" bw="11" op_0_bw="64">
<![CDATA[
.split.3_ifconv:2 %empty_54 = trunc i64 %j_3

]]></Node>
<StgValue><ssdm name="empty_54"/></StgValue>
</operation>

<operation id="524" st_id="48" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="359" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:4 %add_ln8_12 = add i11 %empty_54, i11 %empty_51

]]></Node>
<StgValue><ssdm name="add_ln8_12"/></StgValue>
</operation>

<operation id="525" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="360" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:5 %zext_ln8_12 = zext i11 %add_ln8_12

]]></Node>
<StgValue><ssdm name="zext_ln8_12"/></StgValue>
</operation>

<operation id="526" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="361" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:6 %arr_addr_12 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_12

]]></Node>
<StgValue><ssdm name="arr_addr_12"/></StgValue>
</operation>

<operation id="527" st_id="48" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="362" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:7 %arr_load_12 = load i11 %arr_addr_12

]]></Node>
<StgValue><ssdm name="arr_load_12"/></StgValue>
</operation>

<operation id="528" st_id="48" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="363" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:8 %add_ln8_13 = add i11 %empty_54, i11 %empty_52

]]></Node>
<StgValue><ssdm name="add_ln8_13"/></StgValue>
</operation>

<operation id="529" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="364" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:9 %zext_ln8_13 = zext i11 %add_ln8_13

]]></Node>
<StgValue><ssdm name="zext_ln8_13"/></StgValue>
</operation>

<operation id="530" st_id="48" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="365" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:10 %arr_addr_13 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_13

]]></Node>
<StgValue><ssdm name="arr_addr_13"/></StgValue>
</operation>

<operation id="531" st_id="48" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="366" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:11 %arr_load_13 = load i11 %arr_addr_13

]]></Node>
<StgValue><ssdm name="arr_load_13"/></StgValue>
</operation>
</state>

<state id="49" st_id="49">

<operation id="532" st_id="49" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="362" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:7 %arr_load_12 = load i11 %arr_addr_12

]]></Node>
<StgValue><ssdm name="arr_load_12"/></StgValue>
</operation>

<operation id="533" st_id="49" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="366" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:11 %arr_load_13 = load i11 %arr_addr_13

]]></Node>
<StgValue><ssdm name="arr_load_13"/></StgValue>
</operation>

<operation id="534" st_id="49" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="367" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:12 %or_ln34_3 = or i11 %empty_54, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_3"/></StgValue>
</operation>

<operation id="535" st_id="49" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="368" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:13 %add_ln8_14 = add i11 %or_ln34_3, i11 %empty_51

]]></Node>
<StgValue><ssdm name="add_ln8_14"/></StgValue>
</operation>

<operation id="536" st_id="49" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="369" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:14 %zext_ln8_14 = zext i11 %add_ln8_14

]]></Node>
<StgValue><ssdm name="zext_ln8_14"/></StgValue>
</operation>

<operation id="537" st_id="49" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="370" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:15 %arr_addr_14 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_14

]]></Node>
<StgValue><ssdm name="arr_addr_14"/></StgValue>
</operation>

<operation id="538" st_id="49" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="371" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:16 %arr_load_14 = load i11 %arr_addr_14

]]></Node>
<StgValue><ssdm name="arr_load_14"/></StgValue>
</operation>

<operation id="539" st_id="49" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="372" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:17 %add_ln8_15 = add i11 %or_ln34_3, i11 %empty_52

]]></Node>
<StgValue><ssdm name="add_ln8_15"/></StgValue>
</operation>

<operation id="540" st_id="49" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="373" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:18 %zext_ln8_15 = zext i11 %add_ln8_15

]]></Node>
<StgValue><ssdm name="zext_ln8_15"/></StgValue>
</operation>

<operation id="541" st_id="49" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="374" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:19 %arr_addr_15 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_15

]]></Node>
<StgValue><ssdm name="arr_addr_15"/></StgValue>
</operation>

<operation id="542" st_id="49" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="375" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:20 %arr_load_15 = load i11 %arr_addr_15

]]></Node>
<StgValue><ssdm name="arr_load_15"/></StgValue>
</operation>

<operation id="543" st_id="49" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="389" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:34 %tmp_1066 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_13

]]></Node>
<StgValue><ssdm name="tmp_1066"/></StgValue>
</operation>
</state>

<state id="50" st_id="50">

<operation id="544" st_id="50" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="355" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.3_ifconv:0 %add_ln32_3 = add i64 %j_3, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_3"/></StgValue>
</operation>

<operation id="545" st_id="50" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="371" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:16 %arr_load_14 = load i11 %arr_addr_14

]]></Node>
<StgValue><ssdm name="arr_load_14"/></StgValue>
</operation>

<operation id="546" st_id="50" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="375" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:20 %arr_load_15 = load i11 %arr_addr_15

]]></Node>
<StgValue><ssdm name="arr_load_15"/></StgValue>
</operation>

<operation id="547" st_id="50" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="376" bw="32" op_0_bw="32">
<![CDATA[
.split.3_ifconv:21 %bitcast_ln13_12 = bitcast i32 %arr_load_12

]]></Node>
<StgValue><ssdm name="bitcast_ln13_12"/></StgValue>
</operation>

<operation id="548" st_id="50" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="377" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.3_ifconv:22 %tmp_1064 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_12, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1064"/></StgValue>
</operation>

<operation id="549" st_id="50" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="378" bw="23" op_0_bw="32">
<![CDATA[
.split.3_ifconv:23 %trunc_ln13_12 = trunc i32 %bitcast_ln13_12

]]></Node>
<StgValue><ssdm name="trunc_ln13_12"/></StgValue>
</operation>

<operation id="550" st_id="50" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="382" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.3_ifconv:27 %icmp_ln13_24 = icmp_ne  i8 %tmp_1064, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_24"/></StgValue>
</operation>

<operation id="551" st_id="50" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="383" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.3_ifconv:28 %icmp_ln13_25 = icmp_eq  i23 %trunc_ln13_12, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_25"/></StgValue>
</operation>

<operation id="552" st_id="50" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="384" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:29 %or_ln13_12 = or i1 %icmp_ln13_25, i1 %icmp_ln13_24

]]></Node>
<StgValue><ssdm name="or_ln13_12"/></StgValue>
</operation>

<operation id="553" st_id="50" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="389" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:34 %tmp_1066 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_13

]]></Node>
<StgValue><ssdm name="tmp_1066"/></StgValue>
</operation>

<operation id="554" st_id="50" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="398" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:43 %tmp_1068 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_14

]]></Node>
<StgValue><ssdm name="tmp_1068"/></StgValue>
</operation>

<operation id="555" st_id="50" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="407" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:52 %tmp_1070 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1070"/></StgValue>
</operation>
</state>

<state id="51" st_id="51">

<operation id="556" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="379" bw="32" op_0_bw="32">
<![CDATA[
.split.3_ifconv:24 %bitcast_ln13_13 = bitcast i32 %arr_load_13

]]></Node>
<StgValue><ssdm name="bitcast_ln13_13"/></StgValue>
</operation>

<operation id="557" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="380" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.3_ifconv:25 %tmp_1065 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_13, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1065"/></StgValue>
</operation>

<operation id="558" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="381" bw="23" op_0_bw="32">
<![CDATA[
.split.3_ifconv:26 %trunc_ln13_13 = trunc i32 %bitcast_ln13_13

]]></Node>
<StgValue><ssdm name="trunc_ln13_13"/></StgValue>
</operation>

<operation id="559" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="385" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.3_ifconv:30 %icmp_ln13_26 = icmp_ne  i8 %tmp_1065, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_26"/></StgValue>
</operation>

<operation id="560" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="386" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.3_ifconv:31 %icmp_ln13_27 = icmp_eq  i23 %trunc_ln13_13, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_27"/></StgValue>
</operation>

<operation id="561" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="387" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:32 %or_ln13_13 = or i1 %icmp_ln13_27, i1 %icmp_ln13_26

]]></Node>
<StgValue><ssdm name="or_ln13_13"/></StgValue>
</operation>

<operation id="562" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="388" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:33 %and_ln13_31 = and i1 %or_ln13_12, i1 %or_ln13_13

]]></Node>
<StgValue><ssdm name="and_ln13_31"/></StgValue>
</operation>

<operation id="563" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="390" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:35 %and_ln13_32 = and i1 %and_ln13_31, i1 %tmp_1066

]]></Node>
<StgValue><ssdm name="and_ln13_32"/></StgValue>
</operation>

<operation id="564" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="391" bw="32" op_0_bw="32">
<![CDATA[
.split.3_ifconv:36 %bitcast_ln13_14 = bitcast i32 %arr_load_14

]]></Node>
<StgValue><ssdm name="bitcast_ln13_14"/></StgValue>
</operation>

<operation id="565" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="392" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.3_ifconv:37 %tmp_1067 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_14, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1067"/></StgValue>
</operation>

<operation id="566" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="393" bw="23" op_0_bw="32">
<![CDATA[
.split.3_ifconv:38 %trunc_ln13_14 = trunc i32 %bitcast_ln13_14

]]></Node>
<StgValue><ssdm name="trunc_ln13_14"/></StgValue>
</operation>

<operation id="567" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="394" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.3_ifconv:39 %icmp_ln13_28 = icmp_ne  i8 %tmp_1067, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_28"/></StgValue>
</operation>

<operation id="568" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="395" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.3_ifconv:40 %icmp_ln13_29 = icmp_eq  i23 %trunc_ln13_14, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_29"/></StgValue>
</operation>

<operation id="569" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="396" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:41 %or_ln13_14 = or i1 %icmp_ln13_29, i1 %icmp_ln13_28

]]></Node>
<StgValue><ssdm name="or_ln13_14"/></StgValue>
</operation>

<operation id="570" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="397" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:42 %and_ln13_33 = and i1 %or_ln13_12, i1 %or_ln13_14

]]></Node>
<StgValue><ssdm name="and_ln13_33"/></StgValue>
</operation>

<operation id="571" st_id="51" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="398" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:43 %tmp_1068 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_14

]]></Node>
<StgValue><ssdm name="tmp_1068"/></StgValue>
</operation>

<operation id="572" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="399" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:44 %and_ln13_34 = and i1 %and_ln13_33, i1 %tmp_1068

]]></Node>
<StgValue><ssdm name="and_ln13_34"/></StgValue>
</operation>

<operation id="573" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="400" bw="32" op_0_bw="32">
<![CDATA[
.split.3_ifconv:45 %bitcast_ln13_15 = bitcast i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="bitcast_ln13_15"/></StgValue>
</operation>

<operation id="574" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="401" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.3_ifconv:46 %tmp_1069 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_15, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1069"/></StgValue>
</operation>

<operation id="575" st_id="51" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="402" bw="23" op_0_bw="32">
<![CDATA[
.split.3_ifconv:47 %trunc_ln13_15 = trunc i32 %bitcast_ln13_15

]]></Node>
<StgValue><ssdm name="trunc_ln13_15"/></StgValue>
</operation>

<operation id="576" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="403" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.3_ifconv:48 %icmp_ln13_30 = icmp_ne  i8 %tmp_1069, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_30"/></StgValue>
</operation>

<operation id="577" st_id="51" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="404" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.3_ifconv:49 %icmp_ln13_31 = icmp_eq  i23 %trunc_ln13_15, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_31"/></StgValue>
</operation>

<operation id="578" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="405" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:50 %or_ln13_15 = or i1 %icmp_ln13_31, i1 %icmp_ln13_30

]]></Node>
<StgValue><ssdm name="or_ln13_15"/></StgValue>
</operation>

<operation id="579" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="406" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:51 %and_ln13_35 = and i1 %or_ln13_12, i1 %or_ln13_15

]]></Node>
<StgValue><ssdm name="and_ln13_35"/></StgValue>
</operation>

<operation id="580" st_id="51" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="407" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:52 %tmp_1070 = fcmp_ogt  i32 %arr_load_12, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1070"/></StgValue>
</operation>

<operation id="581" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="408" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:53 %and_ln13_36 = and i1 %and_ln13_35, i1 %tmp_1070

]]></Node>
<StgValue><ssdm name="and_ln13_36"/></StgValue>
</operation>

<operation id="582" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="409" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:54 %and_ln13_37 = and i1 %and_ln13_34, i1 %and_ln13_36

]]></Node>
<StgValue><ssdm name="and_ln13_37"/></StgValue>
</operation>

<operation id="583" st_id="51" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="410" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:55 %and_ln13_13 = and i1 %and_ln13_37, i1 %and_ln13_32

]]></Node>
<StgValue><ssdm name="and_ln13_13"/></StgValue>
</operation>

<operation id="584" st_id="51" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:57 %tmp_1071 = fcmp_ogt  i32 %arr_load_13, i32 %arr_load_14

]]></Node>
<StgValue><ssdm name="tmp_1071"/></StgValue>
</operation>

<operation id="585" st_id="51" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="415" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:60 %tmp_1072 = fcmp_ogt  i32 %arr_load_13, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1072"/></StgValue>
</operation>
</state>

<state id="52" st_id="52">

<operation id="586" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="411" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:56 %and_ln16_25 = and i1 %or_ln13_13, i1 %or_ln13_14

]]></Node>
<StgValue><ssdm name="and_ln16_25"/></StgValue>
</operation>

<operation id="587" st_id="52" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="412" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:57 %tmp_1071 = fcmp_ogt  i32 %arr_load_13, i32 %arr_load_14

]]></Node>
<StgValue><ssdm name="tmp_1071"/></StgValue>
</operation>

<operation id="588" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="413" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:58 %and_ln16_26 = and i1 %and_ln16_25, i1 %tmp_1071

]]></Node>
<StgValue><ssdm name="and_ln16_26"/></StgValue>
</operation>

<operation id="589" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="414" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:59 %and_ln16_27 = and i1 %or_ln13_13, i1 %or_ln13_15

]]></Node>
<StgValue><ssdm name="and_ln16_27"/></StgValue>
</operation>

<operation id="590" st_id="52" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="415" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:60 %tmp_1072 = fcmp_ogt  i32 %arr_load_13, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1072"/></StgValue>
</operation>

<operation id="591" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="416" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:61 %and_ln16_28 = and i1 %and_ln16_27, i1 %tmp_1072

]]></Node>
<StgValue><ssdm name="and_ln16_28"/></StgValue>
</operation>

<operation id="592" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="417" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:62 %and_ln16_3 = and i1 %and_ln16_26, i1 %and_ln16_28

]]></Node>
<StgValue><ssdm name="and_ln16_3"/></StgValue>
</operation>

<operation id="593" st_id="52" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="419" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:64 %tmp_1073 = fcmp_ogt  i32 %arr_load_14, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1073"/></StgValue>
</operation>

<operation id="594" st_id="52" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="421" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.3_ifconv:66 %select_ln13_3 = select i1 %and_ln13_13, i11 %add_ln8_12, i11 %add_ln8_15

]]></Node>
<StgValue><ssdm name="select_ln13_3"/></StgValue>
</operation>

<operation id="595" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="422" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:67 %xor_ln13_3 = xor i1 %and_ln13_13, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_3"/></StgValue>
</operation>

<operation id="596" st_id="52" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="423" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:68 %and_ln16_29 = and i1 %and_ln16_3, i1 %xor_ln13_3

]]></Node>
<StgValue><ssdm name="and_ln16_29"/></StgValue>
</operation>

<operation id="597" st_id="52" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="424" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.3_ifconv:69 %select_ln16_3 = select i1 %and_ln16_29, i11 %add_ln8_13, i11 %select_ln13_3

]]></Node>
<StgValue><ssdm name="select_ln16_3"/></StgValue>
</operation>
</state>

<state id="53" st_id="53">

<operation id="598" st_id="53" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="418" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:63 %and_ln19_9 = and i1 %or_ln13_14, i1 %or_ln13_15

]]></Node>
<StgValue><ssdm name="and_ln19_9"/></StgValue>
</operation>

<operation id="599" st_id="53" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="419" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.3_ifconv:64 %tmp_1073 = fcmp_ogt  i32 %arr_load_14, i32 %arr_load_15

]]></Node>
<StgValue><ssdm name="tmp_1073"/></StgValue>
</operation>

<operation id="600" st_id="53" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="420" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:65 %and_ln19_10 = and i1 %and_ln19_9, i1 %tmp_1073

]]></Node>
<StgValue><ssdm name="and_ln19_10"/></StgValue>
</operation>

<operation id="601" st_id="53" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="425" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:70 %or_ln16_3 = or i1 %and_ln13_13, i1 %and_ln16_3

]]></Node>
<StgValue><ssdm name="or_ln16_3"/></StgValue>
</operation>

<operation id="602" st_id="53" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="426" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:71 %xor_ln16_3 = xor i1 %or_ln16_3, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_3"/></StgValue>
</operation>

<operation id="603" st_id="53" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="427" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.3_ifconv:72 %and_ln19_11 = and i1 %and_ln19_10, i1 %xor_ln16_3

]]></Node>
<StgValue><ssdm name="and_ln19_11"/></StgValue>
</operation>

<operation id="604" st_id="53" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="428" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.3_ifconv:73 %select_ln19_3 = select i1 %and_ln19_11, i11 %add_ln8_14, i11 %select_ln16_3

]]></Node>
<StgValue><ssdm name="select_ln19_3"/></StgValue>
</operation>

<operation id="605" st_id="53" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="429" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:74 %zext_ln8_43 = zext i11 %select_ln19_3

]]></Node>
<StgValue><ssdm name="zext_ln8_43"/></StgValue>
</operation>

<operation id="606" st_id="53" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="430" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:75 %arr_addr_43 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_43

]]></Node>
<StgValue><ssdm name="arr_addr_43"/></StgValue>
</operation>

<operation id="607" st_id="53" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="431" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:76 %arr_load_43 = load i11 %arr_addr_43

]]></Node>
<StgValue><ssdm name="arr_load_43"/></StgValue>
</operation>
</state>

<state id="54" st_id="54">

<operation id="608" st_id="54" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="356" bw="64" op_0_bw="11">
<![CDATA[
.split.3_ifconv:1 %t_1_3_cast = zext i11 %t_1_3

]]></Node>
<StgValue><ssdm name="t_1_3_cast"/></StgValue>
</operation>

<operation id="609" st_id="54" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="358" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.3_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="610" st_id="54" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="431" bw="32" op_0_bw="11">
<![CDATA[
.split.3_ifconv:76 %arr_load_43 = load i11 %arr_addr_43

]]></Node>
<StgValue><ssdm name="arr_load_43"/></StgValue>
</operation>

<operation id="611" st_id="54" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="432" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.3_ifconv:77 %add_ln34_3 = add i11 %t_1_3, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_3"/></StgValue>
</operation>

<operation id="612" st_id="54" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="433" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.3_ifconv:78 %out_addr_3 = getelementptr i32 %out_r, i64 0, i64 %t_1_3_cast

]]></Node>
<StgValue><ssdm name="out_addr_3"/></StgValue>
</operation>

<operation id="613" st_id="54" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="434" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.3_ifconv:79 %store_ln34 = store i32 %arr_load_43, i11 %out_addr_3

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="614" st_id="54" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_3" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="435" bw="0" op_0_bw="0">
<![CDATA[
.split.3_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="55" st_id="55">

<operation id="615" st_id="55" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="437" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.3:0 %trunc_ln29_4 = trunc i32 %add_ln29_6

]]></Node>
<StgValue><ssdm name="trunc_ln29_4"/></StgValue>
</operation>

<operation id="616" st_id="55" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="438" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.3:1 %add_ln29_9 = add i32 %zext_ln29_3, i32 %add_ln29_6

]]></Node>
<StgValue><ssdm name="add_ln29_9"/></StgValue>
</operation>

<operation id="617" st_id="55" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="439" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.3:2 %add_ln29_10 = add i64 %i_0, i64 8

]]></Node>
<StgValue><ssdm name="add_ln29_10"/></StgValue>
</operation>

<operation id="618" st_id="55" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="440" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.3:3 %add_ln29_11 = add i11 %trunc_ln29_1, i11 8

]]></Node>
<StgValue><ssdm name="add_ln29_11"/></StgValue>
</operation>

<operation id="619" st_id="55" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="441" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.3:4 %icmp_ln29_4 = icmp_slt  i64 %add_ln29_10, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_4"/></StgValue>
</operation>

<operation id="620" st_id="55" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="442" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.3:5 %br_ln29 = br i1 %icmp_ln29_4, void %._crit_edge10, void %.split4.4

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="621" st_id="55" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="444" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:0 %empty_55 = or i11 %add_ln29_11, i11 1

]]></Node>
<StgValue><ssdm name="empty_55"/></StgValue>
</operation>

<operation id="622" st_id="55" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="445" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:1 %empty_56 = mul i11 %add_ln29_11, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="623" st_id="55" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="446" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:2 %empty_57 = mul i11 %empty_55, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>

<operation id="624" st_id="55" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_4" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="447" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:3 %add_ln32_13 = add i11 %zext_ln29_4, i11 %trunc_ln29_4

]]></Node>
<StgValue><ssdm name="add_ln32_13"/></StgValue>
</operation>
</state>

<state id="56" st_id="56">

<operation id="625" st_id="56" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="445" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:1 %empty_56 = mul i11 %add_ln29_11, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="626" st_id="56" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="446" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:2 %empty_57 = mul i11 %empty_55, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>
</state>

<state id="57" st_id="57">

<operation id="627" st_id="57" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="445" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:1 %empty_56 = mul i11 %add_ln29_11, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="628" st_id="57" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="446" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:2 %empty_57 = mul i11 %empty_55, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>
</state>

<state id="58" st_id="58">

<operation id="629" st_id="58" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="445" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:1 %empty_56 = mul i11 %add_ln29_11, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_56"/></StgValue>
</operation>

<operation id="630" st_id="58" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="446" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.4:2 %empty_57 = mul i11 %empty_55, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_57"/></StgValue>
</operation>

<operation id="631" st_id="58" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="448" bw="0" op_0_bw="0">
<![CDATA[
.split4.4:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="59" st_id="59">

<operation id="632" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="450" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_4 = phi i11 %add_ln34_4, void %.split.4_ifconv, i11 %add_ln32_13, void %.split4.4

]]></Node>
<StgValue><ssdm name="t_1_4"/></StgValue>
</operation>

<operation id="633" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="451" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_4 = phi i64 %add_ln32_4, void %.split.4_ifconv, i64 0, void %.split4.4

]]></Node>
<StgValue><ssdm name="j_4"/></StgValue>
</operation>

<operation id="634" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="452" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="635" st_id="59" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="453" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_4 = icmp_eq  i64 %j_4, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_4"/></StgValue>
</operation>

<operation id="636" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="454" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_58 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_58"/></StgValue>
</operation>

<operation id="637" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="455" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_4, void %.split.4_ifconv, void %._crit_edge.loopexit.4

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="638" st_id="59" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="457" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.4_ifconv:0 %add_ln32_4 = add i64 %j_4, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_4"/></StgValue>
</operation>

<operation id="639" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="459" bw="11" op_0_bw="64">
<![CDATA[
.split.4_ifconv:2 %empty_59 = trunc i64 %j_4

]]></Node>
<StgValue><ssdm name="empty_59"/></StgValue>
</operation>

<operation id="640" st_id="59" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="461" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:4 %add_ln8_16 = add i11 %empty_59, i11 %empty_56

]]></Node>
<StgValue><ssdm name="add_ln8_16"/></StgValue>
</operation>

<operation id="641" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="462" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:5 %zext_ln8_16 = zext i11 %add_ln8_16

]]></Node>
<StgValue><ssdm name="zext_ln8_16"/></StgValue>
</operation>

<operation id="642" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="463" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:6 %arr_addr_16 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_16

]]></Node>
<StgValue><ssdm name="arr_addr_16"/></StgValue>
</operation>

<operation id="643" st_id="59" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="464" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:7 %arr_load_16 = load i11 %arr_addr_16

]]></Node>
<StgValue><ssdm name="arr_load_16"/></StgValue>
</operation>

<operation id="644" st_id="59" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="465" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:8 %add_ln8_17 = add i11 %empty_59, i11 %empty_57

]]></Node>
<StgValue><ssdm name="add_ln8_17"/></StgValue>
</operation>

<operation id="645" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="466" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:9 %zext_ln8_17 = zext i11 %add_ln8_17

]]></Node>
<StgValue><ssdm name="zext_ln8_17"/></StgValue>
</operation>

<operation id="646" st_id="59" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="467" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:10 %arr_addr_17 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_17

]]></Node>
<StgValue><ssdm name="arr_addr_17"/></StgValue>
</operation>

<operation id="647" st_id="59" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="468" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:11 %arr_load_17 = load i11 %arr_addr_17

]]></Node>
<StgValue><ssdm name="arr_load_17"/></StgValue>
</operation>
</state>

<state id="60" st_id="60">

<operation id="648" st_id="60" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="464" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:7 %arr_load_16 = load i11 %arr_addr_16

]]></Node>
<StgValue><ssdm name="arr_load_16"/></StgValue>
</operation>

<operation id="649" st_id="60" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="468" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:11 %arr_load_17 = load i11 %arr_addr_17

]]></Node>
<StgValue><ssdm name="arr_load_17"/></StgValue>
</operation>

<operation id="650" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="469" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:12 %or_ln34_4 = or i11 %empty_59, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_4"/></StgValue>
</operation>

<operation id="651" st_id="60" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="470" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:13 %add_ln8_18 = add i11 %or_ln34_4, i11 %empty_56

]]></Node>
<StgValue><ssdm name="add_ln8_18"/></StgValue>
</operation>

<operation id="652" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="471" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:14 %zext_ln8_18 = zext i11 %add_ln8_18

]]></Node>
<StgValue><ssdm name="zext_ln8_18"/></StgValue>
</operation>

<operation id="653" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="472" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:15 %arr_addr_18 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_18

]]></Node>
<StgValue><ssdm name="arr_addr_18"/></StgValue>
</operation>

<operation id="654" st_id="60" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="473" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:16 %arr_load_18 = load i11 %arr_addr_18

]]></Node>
<StgValue><ssdm name="arr_load_18"/></StgValue>
</operation>

<operation id="655" st_id="60" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="474" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:17 %add_ln8_19 = add i11 %or_ln34_4, i11 %empty_57

]]></Node>
<StgValue><ssdm name="add_ln8_19"/></StgValue>
</operation>

<operation id="656" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="475" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:18 %zext_ln8_19 = zext i11 %add_ln8_19

]]></Node>
<StgValue><ssdm name="zext_ln8_19"/></StgValue>
</operation>

<operation id="657" st_id="60" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="476" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:19 %arr_addr_19 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_19

]]></Node>
<StgValue><ssdm name="arr_addr_19"/></StgValue>
</operation>

<operation id="658" st_id="60" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="477" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:20 %arr_load_19 = load i11 %arr_addr_19

]]></Node>
<StgValue><ssdm name="arr_load_19"/></StgValue>
</operation>

<operation id="659" st_id="60" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="491" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:34 %tmp_1076 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_17

]]></Node>
<StgValue><ssdm name="tmp_1076"/></StgValue>
</operation>
</state>

<state id="61" st_id="61">

<operation id="660" st_id="61" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="473" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:16 %arr_load_18 = load i11 %arr_addr_18

]]></Node>
<StgValue><ssdm name="arr_load_18"/></StgValue>
</operation>

<operation id="661" st_id="61" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="477" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:20 %arr_load_19 = load i11 %arr_addr_19

]]></Node>
<StgValue><ssdm name="arr_load_19"/></StgValue>
</operation>

<operation id="662" st_id="61" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="478" bw="32" op_0_bw="32">
<![CDATA[
.split.4_ifconv:21 %bitcast_ln13_16 = bitcast i32 %arr_load_16

]]></Node>
<StgValue><ssdm name="bitcast_ln13_16"/></StgValue>
</operation>

<operation id="663" st_id="61" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="479" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.4_ifconv:22 %tmp_1074 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_16, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1074"/></StgValue>
</operation>

<operation id="664" st_id="61" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="480" bw="23" op_0_bw="32">
<![CDATA[
.split.4_ifconv:23 %trunc_ln13_16 = trunc i32 %bitcast_ln13_16

]]></Node>
<StgValue><ssdm name="trunc_ln13_16"/></StgValue>
</operation>

<operation id="665" st_id="61" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="484" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.4_ifconv:27 %icmp_ln13_32 = icmp_ne  i8 %tmp_1074, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_32"/></StgValue>
</operation>

<operation id="666" st_id="61" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="485" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.4_ifconv:28 %icmp_ln13_33 = icmp_eq  i23 %trunc_ln13_16, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_33"/></StgValue>
</operation>

<operation id="667" st_id="61" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="486" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:29 %or_ln13_16 = or i1 %icmp_ln13_33, i1 %icmp_ln13_32

]]></Node>
<StgValue><ssdm name="or_ln13_16"/></StgValue>
</operation>

<operation id="668" st_id="61" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="491" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:34 %tmp_1076 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_17

]]></Node>
<StgValue><ssdm name="tmp_1076"/></StgValue>
</operation>

<operation id="669" st_id="61" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:43 %tmp_1078 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_18

]]></Node>
<StgValue><ssdm name="tmp_1078"/></StgValue>
</operation>

<operation id="670" st_id="61" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="509" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:52 %tmp_1080 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1080"/></StgValue>
</operation>
</state>

<state id="62" st_id="62">

<operation id="671" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="481" bw="32" op_0_bw="32">
<![CDATA[
.split.4_ifconv:24 %bitcast_ln13_17 = bitcast i32 %arr_load_17

]]></Node>
<StgValue><ssdm name="bitcast_ln13_17"/></StgValue>
</operation>

<operation id="672" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="482" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.4_ifconv:25 %tmp_1075 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_17, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1075"/></StgValue>
</operation>

<operation id="673" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="483" bw="23" op_0_bw="32">
<![CDATA[
.split.4_ifconv:26 %trunc_ln13_17 = trunc i32 %bitcast_ln13_17

]]></Node>
<StgValue><ssdm name="trunc_ln13_17"/></StgValue>
</operation>

<operation id="674" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="487" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.4_ifconv:30 %icmp_ln13_34 = icmp_ne  i8 %tmp_1075, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_34"/></StgValue>
</operation>

<operation id="675" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="488" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.4_ifconv:31 %icmp_ln13_35 = icmp_eq  i23 %trunc_ln13_17, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_35"/></StgValue>
</operation>

<operation id="676" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="489" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:32 %or_ln13_17 = or i1 %icmp_ln13_35, i1 %icmp_ln13_34

]]></Node>
<StgValue><ssdm name="or_ln13_17"/></StgValue>
</operation>

<operation id="677" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="490" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:33 %and_ln13_38 = and i1 %or_ln13_16, i1 %or_ln13_17

]]></Node>
<StgValue><ssdm name="and_ln13_38"/></StgValue>
</operation>

<operation id="678" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="492" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:35 %and_ln13_39 = and i1 %and_ln13_38, i1 %tmp_1076

]]></Node>
<StgValue><ssdm name="and_ln13_39"/></StgValue>
</operation>

<operation id="679" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="493" bw="32" op_0_bw="32">
<![CDATA[
.split.4_ifconv:36 %bitcast_ln13_18 = bitcast i32 %arr_load_18

]]></Node>
<StgValue><ssdm name="bitcast_ln13_18"/></StgValue>
</operation>

<operation id="680" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="494" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.4_ifconv:37 %tmp_1077 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_18, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1077"/></StgValue>
</operation>

<operation id="681" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="495" bw="23" op_0_bw="32">
<![CDATA[
.split.4_ifconv:38 %trunc_ln13_18 = trunc i32 %bitcast_ln13_18

]]></Node>
<StgValue><ssdm name="trunc_ln13_18"/></StgValue>
</operation>

<operation id="682" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="496" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.4_ifconv:39 %icmp_ln13_36 = icmp_ne  i8 %tmp_1077, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_36"/></StgValue>
</operation>

<operation id="683" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="497" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.4_ifconv:40 %icmp_ln13_37 = icmp_eq  i23 %trunc_ln13_18, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_37"/></StgValue>
</operation>

<operation id="684" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="498" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:41 %or_ln13_18 = or i1 %icmp_ln13_37, i1 %icmp_ln13_36

]]></Node>
<StgValue><ssdm name="or_ln13_18"/></StgValue>
</operation>

<operation id="685" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="499" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:42 %and_ln13_40 = and i1 %or_ln13_16, i1 %or_ln13_18

]]></Node>
<StgValue><ssdm name="and_ln13_40"/></StgValue>
</operation>

<operation id="686" st_id="62" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="500" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:43 %tmp_1078 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_18

]]></Node>
<StgValue><ssdm name="tmp_1078"/></StgValue>
</operation>

<operation id="687" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="501" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:44 %and_ln13_41 = and i1 %and_ln13_40, i1 %tmp_1078

]]></Node>
<StgValue><ssdm name="and_ln13_41"/></StgValue>
</operation>

<operation id="688" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="502" bw="32" op_0_bw="32">
<![CDATA[
.split.4_ifconv:45 %bitcast_ln13_19 = bitcast i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="bitcast_ln13_19"/></StgValue>
</operation>

<operation id="689" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="503" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.4_ifconv:46 %tmp_1079 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_19, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1079"/></StgValue>
</operation>

<operation id="690" st_id="62" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="504" bw="23" op_0_bw="32">
<![CDATA[
.split.4_ifconv:47 %trunc_ln13_19 = trunc i32 %bitcast_ln13_19

]]></Node>
<StgValue><ssdm name="trunc_ln13_19"/></StgValue>
</operation>

<operation id="691" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="505" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.4_ifconv:48 %icmp_ln13_38 = icmp_ne  i8 %tmp_1079, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_38"/></StgValue>
</operation>

<operation id="692" st_id="62" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="506" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.4_ifconv:49 %icmp_ln13_39 = icmp_eq  i23 %trunc_ln13_19, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_39"/></StgValue>
</operation>

<operation id="693" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="507" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:50 %or_ln13_19 = or i1 %icmp_ln13_39, i1 %icmp_ln13_38

]]></Node>
<StgValue><ssdm name="or_ln13_19"/></StgValue>
</operation>

<operation id="694" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="508" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:51 %and_ln13_42 = and i1 %or_ln13_16, i1 %or_ln13_19

]]></Node>
<StgValue><ssdm name="and_ln13_42"/></StgValue>
</operation>

<operation id="695" st_id="62" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="509" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:52 %tmp_1080 = fcmp_ogt  i32 %arr_load_16, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1080"/></StgValue>
</operation>

<operation id="696" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="510" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:53 %and_ln13_43 = and i1 %and_ln13_42, i1 %tmp_1080

]]></Node>
<StgValue><ssdm name="and_ln13_43"/></StgValue>
</operation>

<operation id="697" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="511" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:54 %and_ln13_44 = and i1 %and_ln13_41, i1 %and_ln13_43

]]></Node>
<StgValue><ssdm name="and_ln13_44"/></StgValue>
</operation>

<operation id="698" st_id="62" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="512" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:55 %and_ln13_14 = and i1 %and_ln13_44, i1 %and_ln13_39

]]></Node>
<StgValue><ssdm name="and_ln13_14"/></StgValue>
</operation>

<operation id="699" st_id="62" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="514" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:57 %tmp_1081 = fcmp_ogt  i32 %arr_load_17, i32 %arr_load_18

]]></Node>
<StgValue><ssdm name="tmp_1081"/></StgValue>
</operation>

<operation id="700" st_id="62" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:60 %tmp_1082 = fcmp_ogt  i32 %arr_load_17, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1082"/></StgValue>
</operation>
</state>

<state id="63" st_id="63">

<operation id="701" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="513" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:56 %and_ln16_30 = and i1 %or_ln13_17, i1 %or_ln13_18

]]></Node>
<StgValue><ssdm name="and_ln16_30"/></StgValue>
</operation>

<operation id="702" st_id="63" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="514" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:57 %tmp_1081 = fcmp_ogt  i32 %arr_load_17, i32 %arr_load_18

]]></Node>
<StgValue><ssdm name="tmp_1081"/></StgValue>
</operation>

<operation id="703" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="515" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:58 %and_ln16_31 = and i1 %and_ln16_30, i1 %tmp_1081

]]></Node>
<StgValue><ssdm name="and_ln16_31"/></StgValue>
</operation>

<operation id="704" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="516" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:59 %and_ln16_32 = and i1 %or_ln13_17, i1 %or_ln13_19

]]></Node>
<StgValue><ssdm name="and_ln16_32"/></StgValue>
</operation>

<operation id="705" st_id="63" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="517" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:60 %tmp_1082 = fcmp_ogt  i32 %arr_load_17, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1082"/></StgValue>
</operation>

<operation id="706" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="518" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:61 %and_ln16_33 = and i1 %and_ln16_32, i1 %tmp_1082

]]></Node>
<StgValue><ssdm name="and_ln16_33"/></StgValue>
</operation>

<operation id="707" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="519" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:62 %and_ln16_4 = and i1 %and_ln16_31, i1 %and_ln16_33

]]></Node>
<StgValue><ssdm name="and_ln16_4"/></StgValue>
</operation>

<operation id="708" st_id="63" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="521" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:64 %tmp_1083 = fcmp_ogt  i32 %arr_load_18, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1083"/></StgValue>
</operation>

<operation id="709" st_id="63" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="523" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.4_ifconv:66 %select_ln13_4 = select i1 %and_ln13_14, i11 %add_ln8_16, i11 %add_ln8_19

]]></Node>
<StgValue><ssdm name="select_ln13_4"/></StgValue>
</operation>

<operation id="710" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="524" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:67 %xor_ln13_4 = xor i1 %and_ln13_14, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_4"/></StgValue>
</operation>

<operation id="711" st_id="63" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="525" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:68 %and_ln16_34 = and i1 %and_ln16_4, i1 %xor_ln13_4

]]></Node>
<StgValue><ssdm name="and_ln16_34"/></StgValue>
</operation>

<operation id="712" st_id="63" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="526" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.4_ifconv:69 %select_ln16_4 = select i1 %and_ln16_34, i11 %add_ln8_17, i11 %select_ln13_4

]]></Node>
<StgValue><ssdm name="select_ln16_4"/></StgValue>
</operation>
</state>

<state id="64" st_id="64">

<operation id="713" st_id="64" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="520" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:63 %and_ln19_12 = and i1 %or_ln13_18, i1 %or_ln13_19

]]></Node>
<StgValue><ssdm name="and_ln19_12"/></StgValue>
</operation>

<operation id="714" st_id="64" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="521" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.4_ifconv:64 %tmp_1083 = fcmp_ogt  i32 %arr_load_18, i32 %arr_load_19

]]></Node>
<StgValue><ssdm name="tmp_1083"/></StgValue>
</operation>

<operation id="715" st_id="64" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="522" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:65 %and_ln19_13 = and i1 %and_ln19_12, i1 %tmp_1083

]]></Node>
<StgValue><ssdm name="and_ln19_13"/></StgValue>
</operation>

<operation id="716" st_id="64" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="527" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:70 %or_ln16_4 = or i1 %and_ln13_14, i1 %and_ln16_4

]]></Node>
<StgValue><ssdm name="or_ln16_4"/></StgValue>
</operation>

<operation id="717" st_id="64" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="528" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:71 %xor_ln16_4 = xor i1 %or_ln16_4, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_4"/></StgValue>
</operation>

<operation id="718" st_id="64" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="529" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.4_ifconv:72 %and_ln19_14 = and i1 %and_ln19_13, i1 %xor_ln16_4

]]></Node>
<StgValue><ssdm name="and_ln19_14"/></StgValue>
</operation>

<operation id="719" st_id="64" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="530" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.4_ifconv:73 %select_ln19_4 = select i1 %and_ln19_14, i11 %add_ln8_18, i11 %select_ln16_4

]]></Node>
<StgValue><ssdm name="select_ln19_4"/></StgValue>
</operation>

<operation id="720" st_id="64" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="531" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:74 %zext_ln8_44 = zext i11 %select_ln19_4

]]></Node>
<StgValue><ssdm name="zext_ln8_44"/></StgValue>
</operation>

<operation id="721" st_id="64" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="532" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:75 %arr_addr_44 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_44

]]></Node>
<StgValue><ssdm name="arr_addr_44"/></StgValue>
</operation>

<operation id="722" st_id="64" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="533" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:76 %arr_load_44 = load i11 %arr_addr_44

]]></Node>
<StgValue><ssdm name="arr_load_44"/></StgValue>
</operation>
</state>

<state id="65" st_id="65">

<operation id="723" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="458" bw="64" op_0_bw="11">
<![CDATA[
.split.4_ifconv:1 %t_1_4_cast = zext i11 %t_1_4

]]></Node>
<StgValue><ssdm name="t_1_4_cast"/></StgValue>
</operation>

<operation id="724" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="460" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.4_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="725" st_id="65" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="533" bw="32" op_0_bw="11">
<![CDATA[
.split.4_ifconv:76 %arr_load_44 = load i11 %arr_addr_44

]]></Node>
<StgValue><ssdm name="arr_load_44"/></StgValue>
</operation>

<operation id="726" st_id="65" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="534" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.4_ifconv:77 %add_ln34_4 = add i11 %t_1_4, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_4"/></StgValue>
</operation>

<operation id="727" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="535" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.4_ifconv:78 %out_addr_4 = getelementptr i32 %out_r, i64 0, i64 %t_1_4_cast

]]></Node>
<StgValue><ssdm name="out_addr_4"/></StgValue>
</operation>

<operation id="728" st_id="65" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="536" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.4_ifconv:79 %store_ln34 = store i32 %arr_load_44, i11 %out_addr_4

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="729" st_id="65" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_4" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="537" bw="0" op_0_bw="0">
<![CDATA[
.split.4_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="66" st_id="66">

<operation id="730" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="539" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.4:0 %trunc_ln29_5 = trunc i32 %add_ln29_9

]]></Node>
<StgValue><ssdm name="trunc_ln29_5"/></StgValue>
</operation>

<operation id="731" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="540" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.4:1 %add_ln29_12 = add i32 %zext_ln29_3, i32 %add_ln29_9

]]></Node>
<StgValue><ssdm name="add_ln29_12"/></StgValue>
</operation>

<operation id="732" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="541" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.4:2 %add_ln29_13 = add i64 %i_0, i64 10

]]></Node>
<StgValue><ssdm name="add_ln29_13"/></StgValue>
</operation>

<operation id="733" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="542" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.4:3 %add_ln29_14 = add i11 %trunc_ln29_1, i11 10

]]></Node>
<StgValue><ssdm name="add_ln29_14"/></StgValue>
</operation>

<operation id="734" st_id="66" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="543" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.4:4 %icmp_ln29_5 = icmp_slt  i64 %add_ln29_13, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_5"/></StgValue>
</operation>

<operation id="735" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="544" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.4:5 %br_ln29 = br i1 %icmp_ln29_5, void %._crit_edge10, void %.split4.5

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="736" st_id="66" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="546" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:0 %empty_60 = or i11 %add_ln29_14, i11 1

]]></Node>
<StgValue><ssdm name="empty_60"/></StgValue>
</operation>

<operation id="737" st_id="66" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="547" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:1 %empty_61 = mul i11 %add_ln29_14, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_61"/></StgValue>
</operation>

<operation id="738" st_id="66" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="548" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:2 %empty_62 = mul i11 %empty_60, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_62"/></StgValue>
</operation>

<operation id="739" st_id="66" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_5" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="549" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:3 %add_ln32_14 = add i11 %zext_ln29_4, i11 %trunc_ln29_5

]]></Node>
<StgValue><ssdm name="add_ln32_14"/></StgValue>
</operation>
</state>

<state id="67" st_id="67">

<operation id="740" st_id="67" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="547" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:1 %empty_61 = mul i11 %add_ln29_14, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_61"/></StgValue>
</operation>

<operation id="741" st_id="67" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="548" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:2 %empty_62 = mul i11 %empty_60, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_62"/></StgValue>
</operation>
</state>

<state id="68" st_id="68">

<operation id="742" st_id="68" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="547" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:1 %empty_61 = mul i11 %add_ln29_14, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_61"/></StgValue>
</operation>

<operation id="743" st_id="68" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="548" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:2 %empty_62 = mul i11 %empty_60, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_62"/></StgValue>
</operation>
</state>

<state id="69" st_id="69">

<operation id="744" st_id="69" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="547" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:1 %empty_61 = mul i11 %add_ln29_14, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_61"/></StgValue>
</operation>

<operation id="745" st_id="69" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="548" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.5:2 %empty_62 = mul i11 %empty_60, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_62"/></StgValue>
</operation>

<operation id="746" st_id="69" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="550" bw="0" op_0_bw="0">
<![CDATA[
.split4.5:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="70" st_id="70">

<operation id="747" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="552" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_5 = phi i11 %add_ln34_5, void %.split.5_ifconv, i11 %add_ln32_14, void %.split4.5

]]></Node>
<StgValue><ssdm name="t_1_5"/></StgValue>
</operation>

<operation id="748" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="553" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_5 = phi i64 %add_ln32_5, void %.split.5_ifconv, i64 0, void %.split4.5

]]></Node>
<StgValue><ssdm name="j_5"/></StgValue>
</operation>

<operation id="749" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="554" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="750" st_id="70" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="555" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_5 = icmp_eq  i64 %j_5, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_5"/></StgValue>
</operation>

<operation id="751" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="556" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_63 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_63"/></StgValue>
</operation>

<operation id="752" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="557" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_5, void %.split.5_ifconv, void %._crit_edge.loopexit.5

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="753" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="561" bw="11" op_0_bw="64">
<![CDATA[
.split.5_ifconv:2 %empty_64 = trunc i64 %j_5

]]></Node>
<StgValue><ssdm name="empty_64"/></StgValue>
</operation>

<operation id="754" st_id="70" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="563" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:4 %add_ln8_20 = add i11 %empty_64, i11 %empty_61

]]></Node>
<StgValue><ssdm name="add_ln8_20"/></StgValue>
</operation>

<operation id="755" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="564" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:5 %zext_ln8_20 = zext i11 %add_ln8_20

]]></Node>
<StgValue><ssdm name="zext_ln8_20"/></StgValue>
</operation>

<operation id="756" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="565" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:6 %arr_addr_20 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_20

]]></Node>
<StgValue><ssdm name="arr_addr_20"/></StgValue>
</operation>

<operation id="757" st_id="70" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="566" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:7 %arr_load_20 = load i11 %arr_addr_20

]]></Node>
<StgValue><ssdm name="arr_load_20"/></StgValue>
</operation>

<operation id="758" st_id="70" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="567" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:8 %add_ln8_21 = add i11 %empty_64, i11 %empty_62

]]></Node>
<StgValue><ssdm name="add_ln8_21"/></StgValue>
</operation>

<operation id="759" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="568" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:9 %zext_ln8_21 = zext i11 %add_ln8_21

]]></Node>
<StgValue><ssdm name="zext_ln8_21"/></StgValue>
</operation>

<operation id="760" st_id="70" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="569" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:10 %arr_addr_21 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_21

]]></Node>
<StgValue><ssdm name="arr_addr_21"/></StgValue>
</operation>

<operation id="761" st_id="70" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:11 %arr_load_21 = load i11 %arr_addr_21

]]></Node>
<StgValue><ssdm name="arr_load_21"/></StgValue>
</operation>
</state>

<state id="71" st_id="71">

<operation id="762" st_id="71" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="566" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:7 %arr_load_20 = load i11 %arr_addr_20

]]></Node>
<StgValue><ssdm name="arr_load_20"/></StgValue>
</operation>

<operation id="763" st_id="71" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="570" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:11 %arr_load_21 = load i11 %arr_addr_21

]]></Node>
<StgValue><ssdm name="arr_load_21"/></StgValue>
</operation>

<operation id="764" st_id="71" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="571" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:12 %or_ln34_5 = or i11 %empty_64, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_5"/></StgValue>
</operation>

<operation id="765" st_id="71" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="572" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:13 %add_ln8_22 = add i11 %or_ln34_5, i11 %empty_61

]]></Node>
<StgValue><ssdm name="add_ln8_22"/></StgValue>
</operation>

<operation id="766" st_id="71" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="573" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:14 %zext_ln8_22 = zext i11 %add_ln8_22

]]></Node>
<StgValue><ssdm name="zext_ln8_22"/></StgValue>
</operation>

<operation id="767" st_id="71" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="574" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:15 %arr_addr_22 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_22

]]></Node>
<StgValue><ssdm name="arr_addr_22"/></StgValue>
</operation>

<operation id="768" st_id="71" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:16 %arr_load_22 = load i11 %arr_addr_22

]]></Node>
<StgValue><ssdm name="arr_load_22"/></StgValue>
</operation>

<operation id="769" st_id="71" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="576" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:17 %add_ln8_23 = add i11 %or_ln34_5, i11 %empty_62

]]></Node>
<StgValue><ssdm name="add_ln8_23"/></StgValue>
</operation>

<operation id="770" st_id="71" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="577" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:18 %zext_ln8_23 = zext i11 %add_ln8_23

]]></Node>
<StgValue><ssdm name="zext_ln8_23"/></StgValue>
</operation>

<operation id="771" st_id="71" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="578" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:19 %arr_addr_23 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_23

]]></Node>
<StgValue><ssdm name="arr_addr_23"/></StgValue>
</operation>

<operation id="772" st_id="71" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="579" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:20 %arr_load_23 = load i11 %arr_addr_23

]]></Node>
<StgValue><ssdm name="arr_load_23"/></StgValue>
</operation>

<operation id="773" st_id="71" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:34 %tmp_1086 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_21

]]></Node>
<StgValue><ssdm name="tmp_1086"/></StgValue>
</operation>
</state>

<state id="72" st_id="72">

<operation id="774" st_id="72" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="559" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.5_ifconv:0 %add_ln32_5 = add i64 %j_5, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_5"/></StgValue>
</operation>

<operation id="775" st_id="72" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="575" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:16 %arr_load_22 = load i11 %arr_addr_22

]]></Node>
<StgValue><ssdm name="arr_load_22"/></StgValue>
</operation>

<operation id="776" st_id="72" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="579" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:20 %arr_load_23 = load i11 %arr_addr_23

]]></Node>
<StgValue><ssdm name="arr_load_23"/></StgValue>
</operation>

<operation id="777" st_id="72" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="580" bw="32" op_0_bw="32">
<![CDATA[
.split.5_ifconv:21 %bitcast_ln13_20 = bitcast i32 %arr_load_20

]]></Node>
<StgValue><ssdm name="bitcast_ln13_20"/></StgValue>
</operation>

<operation id="778" st_id="72" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="581" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.5_ifconv:22 %tmp_1084 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_20, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1084"/></StgValue>
</operation>

<operation id="779" st_id="72" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="582" bw="23" op_0_bw="32">
<![CDATA[
.split.5_ifconv:23 %trunc_ln13_20 = trunc i32 %bitcast_ln13_20

]]></Node>
<StgValue><ssdm name="trunc_ln13_20"/></StgValue>
</operation>

<operation id="780" st_id="72" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="586" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.5_ifconv:27 %icmp_ln13_40 = icmp_ne  i8 %tmp_1084, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_40"/></StgValue>
</operation>

<operation id="781" st_id="72" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="587" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.5_ifconv:28 %icmp_ln13_41 = icmp_eq  i23 %trunc_ln13_20, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_41"/></StgValue>
</operation>

<operation id="782" st_id="72" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="588" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:29 %or_ln13_20 = or i1 %icmp_ln13_41, i1 %icmp_ln13_40

]]></Node>
<StgValue><ssdm name="or_ln13_20"/></StgValue>
</operation>

<operation id="783" st_id="72" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="593" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:34 %tmp_1086 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_21

]]></Node>
<StgValue><ssdm name="tmp_1086"/></StgValue>
</operation>

<operation id="784" st_id="72" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="602" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:43 %tmp_1088 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_22

]]></Node>
<StgValue><ssdm name="tmp_1088"/></StgValue>
</operation>

<operation id="785" st_id="72" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="611" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:52 %tmp_1090 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1090"/></StgValue>
</operation>
</state>

<state id="73" st_id="73">

<operation id="786" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="583" bw="32" op_0_bw="32">
<![CDATA[
.split.5_ifconv:24 %bitcast_ln13_21 = bitcast i32 %arr_load_21

]]></Node>
<StgValue><ssdm name="bitcast_ln13_21"/></StgValue>
</operation>

<operation id="787" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="584" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.5_ifconv:25 %tmp_1085 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_21, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1085"/></StgValue>
</operation>

<operation id="788" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="585" bw="23" op_0_bw="32">
<![CDATA[
.split.5_ifconv:26 %trunc_ln13_21 = trunc i32 %bitcast_ln13_21

]]></Node>
<StgValue><ssdm name="trunc_ln13_21"/></StgValue>
</operation>

<operation id="789" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="589" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.5_ifconv:30 %icmp_ln13_42 = icmp_ne  i8 %tmp_1085, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_42"/></StgValue>
</operation>

<operation id="790" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="590" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.5_ifconv:31 %icmp_ln13_43 = icmp_eq  i23 %trunc_ln13_21, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_43"/></StgValue>
</operation>

<operation id="791" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="591" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:32 %or_ln13_21 = or i1 %icmp_ln13_43, i1 %icmp_ln13_42

]]></Node>
<StgValue><ssdm name="or_ln13_21"/></StgValue>
</operation>

<operation id="792" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="592" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:33 %and_ln13_45 = and i1 %or_ln13_20, i1 %or_ln13_21

]]></Node>
<StgValue><ssdm name="and_ln13_45"/></StgValue>
</operation>

<operation id="793" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="594" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:35 %and_ln13_46 = and i1 %and_ln13_45, i1 %tmp_1086

]]></Node>
<StgValue><ssdm name="and_ln13_46"/></StgValue>
</operation>

<operation id="794" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="595" bw="32" op_0_bw="32">
<![CDATA[
.split.5_ifconv:36 %bitcast_ln13_22 = bitcast i32 %arr_load_22

]]></Node>
<StgValue><ssdm name="bitcast_ln13_22"/></StgValue>
</operation>

<operation id="795" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="596" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.5_ifconv:37 %tmp_1087 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_22, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1087"/></StgValue>
</operation>

<operation id="796" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="597" bw="23" op_0_bw="32">
<![CDATA[
.split.5_ifconv:38 %trunc_ln13_22 = trunc i32 %bitcast_ln13_22

]]></Node>
<StgValue><ssdm name="trunc_ln13_22"/></StgValue>
</operation>

<operation id="797" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="598" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.5_ifconv:39 %icmp_ln13_44 = icmp_ne  i8 %tmp_1087, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_44"/></StgValue>
</operation>

<operation id="798" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="599" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.5_ifconv:40 %icmp_ln13_45 = icmp_eq  i23 %trunc_ln13_22, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_45"/></StgValue>
</operation>

<operation id="799" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="600" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:41 %or_ln13_22 = or i1 %icmp_ln13_45, i1 %icmp_ln13_44

]]></Node>
<StgValue><ssdm name="or_ln13_22"/></StgValue>
</operation>

<operation id="800" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="601" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:42 %and_ln13_47 = and i1 %or_ln13_20, i1 %or_ln13_22

]]></Node>
<StgValue><ssdm name="and_ln13_47"/></StgValue>
</operation>

<operation id="801" st_id="73" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="602" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:43 %tmp_1088 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_22

]]></Node>
<StgValue><ssdm name="tmp_1088"/></StgValue>
</operation>

<operation id="802" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="603" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:44 %and_ln13_48 = and i1 %and_ln13_47, i1 %tmp_1088

]]></Node>
<StgValue><ssdm name="and_ln13_48"/></StgValue>
</operation>

<operation id="803" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="604" bw="32" op_0_bw="32">
<![CDATA[
.split.5_ifconv:45 %bitcast_ln13_23 = bitcast i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="bitcast_ln13_23"/></StgValue>
</operation>

<operation id="804" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="605" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.5_ifconv:46 %tmp_1089 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_23, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1089"/></StgValue>
</operation>

<operation id="805" st_id="73" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="606" bw="23" op_0_bw="32">
<![CDATA[
.split.5_ifconv:47 %trunc_ln13_23 = trunc i32 %bitcast_ln13_23

]]></Node>
<StgValue><ssdm name="trunc_ln13_23"/></StgValue>
</operation>

<operation id="806" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="607" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.5_ifconv:48 %icmp_ln13_46 = icmp_ne  i8 %tmp_1089, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_46"/></StgValue>
</operation>

<operation id="807" st_id="73" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="608" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.5_ifconv:49 %icmp_ln13_47 = icmp_eq  i23 %trunc_ln13_23, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_47"/></StgValue>
</operation>

<operation id="808" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="609" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:50 %or_ln13_23 = or i1 %icmp_ln13_47, i1 %icmp_ln13_46

]]></Node>
<StgValue><ssdm name="or_ln13_23"/></StgValue>
</operation>

<operation id="809" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="610" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:51 %and_ln13_49 = and i1 %or_ln13_20, i1 %or_ln13_23

]]></Node>
<StgValue><ssdm name="and_ln13_49"/></StgValue>
</operation>

<operation id="810" st_id="73" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="611" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:52 %tmp_1090 = fcmp_ogt  i32 %arr_load_20, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1090"/></StgValue>
</operation>

<operation id="811" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="612" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:53 %and_ln13_50 = and i1 %and_ln13_49, i1 %tmp_1090

]]></Node>
<StgValue><ssdm name="and_ln13_50"/></StgValue>
</operation>

<operation id="812" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="613" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:54 %and_ln13_51 = and i1 %and_ln13_48, i1 %and_ln13_50

]]></Node>
<StgValue><ssdm name="and_ln13_51"/></StgValue>
</operation>

<operation id="813" st_id="73" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="614" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:55 %and_ln13_15 = and i1 %and_ln13_51, i1 %and_ln13_46

]]></Node>
<StgValue><ssdm name="and_ln13_15"/></StgValue>
</operation>

<operation id="814" st_id="73" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="616" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:57 %tmp_1091 = fcmp_ogt  i32 %arr_load_21, i32 %arr_load_22

]]></Node>
<StgValue><ssdm name="tmp_1091"/></StgValue>
</operation>

<operation id="815" st_id="73" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="619" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:60 %tmp_1092 = fcmp_ogt  i32 %arr_load_21, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1092"/></StgValue>
</operation>
</state>

<state id="74" st_id="74">

<operation id="816" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="615" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:56 %and_ln16_35 = and i1 %or_ln13_21, i1 %or_ln13_22

]]></Node>
<StgValue><ssdm name="and_ln16_35"/></StgValue>
</operation>

<operation id="817" st_id="74" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="616" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:57 %tmp_1091 = fcmp_ogt  i32 %arr_load_21, i32 %arr_load_22

]]></Node>
<StgValue><ssdm name="tmp_1091"/></StgValue>
</operation>

<operation id="818" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="617" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:58 %and_ln16_36 = and i1 %and_ln16_35, i1 %tmp_1091

]]></Node>
<StgValue><ssdm name="and_ln16_36"/></StgValue>
</operation>

<operation id="819" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="618" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:59 %and_ln16_37 = and i1 %or_ln13_21, i1 %or_ln13_23

]]></Node>
<StgValue><ssdm name="and_ln16_37"/></StgValue>
</operation>

<operation id="820" st_id="74" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="619" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:60 %tmp_1092 = fcmp_ogt  i32 %arr_load_21, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1092"/></StgValue>
</operation>

<operation id="821" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="620" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:61 %and_ln16_38 = and i1 %and_ln16_37, i1 %tmp_1092

]]></Node>
<StgValue><ssdm name="and_ln16_38"/></StgValue>
</operation>

<operation id="822" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="621" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:62 %and_ln16_5 = and i1 %and_ln16_36, i1 %and_ln16_38

]]></Node>
<StgValue><ssdm name="and_ln16_5"/></StgValue>
</operation>

<operation id="823" st_id="74" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="623" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:64 %tmp_1093 = fcmp_ogt  i32 %arr_load_22, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1093"/></StgValue>
</operation>

<operation id="824" st_id="74" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="625" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.5_ifconv:66 %select_ln13_5 = select i1 %and_ln13_15, i11 %add_ln8_20, i11 %add_ln8_23

]]></Node>
<StgValue><ssdm name="select_ln13_5"/></StgValue>
</operation>

<operation id="825" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="626" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:67 %xor_ln13_5 = xor i1 %and_ln13_15, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_5"/></StgValue>
</operation>

<operation id="826" st_id="74" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="627" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:68 %and_ln16_39 = and i1 %and_ln16_5, i1 %xor_ln13_5

]]></Node>
<StgValue><ssdm name="and_ln16_39"/></StgValue>
</operation>

<operation id="827" st_id="74" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="628" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.5_ifconv:69 %select_ln16_5 = select i1 %and_ln16_39, i11 %add_ln8_21, i11 %select_ln13_5

]]></Node>
<StgValue><ssdm name="select_ln16_5"/></StgValue>
</operation>
</state>

<state id="75" st_id="75">

<operation id="828" st_id="75" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="622" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:63 %and_ln19_15 = and i1 %or_ln13_22, i1 %or_ln13_23

]]></Node>
<StgValue><ssdm name="and_ln19_15"/></StgValue>
</operation>

<operation id="829" st_id="75" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="623" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.5_ifconv:64 %tmp_1093 = fcmp_ogt  i32 %arr_load_22, i32 %arr_load_23

]]></Node>
<StgValue><ssdm name="tmp_1093"/></StgValue>
</operation>

<operation id="830" st_id="75" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="624" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:65 %and_ln19_16 = and i1 %and_ln19_15, i1 %tmp_1093

]]></Node>
<StgValue><ssdm name="and_ln19_16"/></StgValue>
</operation>

<operation id="831" st_id="75" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="629" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:70 %or_ln16_5 = or i1 %and_ln13_15, i1 %and_ln16_5

]]></Node>
<StgValue><ssdm name="or_ln16_5"/></StgValue>
</operation>

<operation id="832" st_id="75" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="630" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:71 %xor_ln16_5 = xor i1 %or_ln16_5, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_5"/></StgValue>
</operation>

<operation id="833" st_id="75" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="631" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.5_ifconv:72 %and_ln19_17 = and i1 %and_ln19_16, i1 %xor_ln16_5

]]></Node>
<StgValue><ssdm name="and_ln19_17"/></StgValue>
</operation>

<operation id="834" st_id="75" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="632" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.5_ifconv:73 %select_ln19_5 = select i1 %and_ln19_17, i11 %add_ln8_22, i11 %select_ln16_5

]]></Node>
<StgValue><ssdm name="select_ln19_5"/></StgValue>
</operation>

<operation id="835" st_id="75" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="633" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:74 %zext_ln8_45 = zext i11 %select_ln19_5

]]></Node>
<StgValue><ssdm name="zext_ln8_45"/></StgValue>
</operation>

<operation id="836" st_id="75" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="634" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:75 %arr_addr_45 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_45

]]></Node>
<StgValue><ssdm name="arr_addr_45"/></StgValue>
</operation>

<operation id="837" st_id="75" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="635" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:76 %arr_load_45 = load i11 %arr_addr_45

]]></Node>
<StgValue><ssdm name="arr_load_45"/></StgValue>
</operation>
</state>

<state id="76" st_id="76">

<operation id="838" st_id="76" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="560" bw="64" op_0_bw="11">
<![CDATA[
.split.5_ifconv:1 %t_1_5_cast = zext i11 %t_1_5

]]></Node>
<StgValue><ssdm name="t_1_5_cast"/></StgValue>
</operation>

<operation id="839" st_id="76" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="562" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.5_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="840" st_id="76" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="635" bw="32" op_0_bw="11">
<![CDATA[
.split.5_ifconv:76 %arr_load_45 = load i11 %arr_addr_45

]]></Node>
<StgValue><ssdm name="arr_load_45"/></StgValue>
</operation>

<operation id="841" st_id="76" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="636" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.5_ifconv:77 %add_ln34_5 = add i11 %t_1_5, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_5"/></StgValue>
</operation>

<operation id="842" st_id="76" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="637" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.5_ifconv:78 %out_addr_5 = getelementptr i32 %out_r, i64 0, i64 %t_1_5_cast

]]></Node>
<StgValue><ssdm name="out_addr_5"/></StgValue>
</operation>

<operation id="843" st_id="76" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="638" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.5_ifconv:79 %store_ln34 = store i32 %arr_load_45, i11 %out_addr_5

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="844" st_id="76" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_5" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="639" bw="0" op_0_bw="0">
<![CDATA[
.split.5_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="77" st_id="77">

<operation id="845" st_id="77" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="641" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.5:0 %trunc_ln29_6 = trunc i32 %add_ln29_12

]]></Node>
<StgValue><ssdm name="trunc_ln29_6"/></StgValue>
</operation>

<operation id="846" st_id="77" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="642" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.5:1 %add_ln29_15 = add i32 %zext_ln29_3, i32 %add_ln29_12

]]></Node>
<StgValue><ssdm name="add_ln29_15"/></StgValue>
</operation>

<operation id="847" st_id="77" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="643" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.5:2 %add_ln29_16 = add i64 %i_0, i64 12

]]></Node>
<StgValue><ssdm name="add_ln29_16"/></StgValue>
</operation>

<operation id="848" st_id="77" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="644" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.5:3 %add_ln29_17 = add i11 %trunc_ln29_1, i11 12

]]></Node>
<StgValue><ssdm name="add_ln29_17"/></StgValue>
</operation>

<operation id="849" st_id="77" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="645" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.5:4 %icmp_ln29_6 = icmp_slt  i64 %add_ln29_16, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_6"/></StgValue>
</operation>

<operation id="850" st_id="77" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="646" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.5:5 %br_ln29 = br i1 %icmp_ln29_6, void %._crit_edge10, void %.split4.6

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="851" st_id="77" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_6" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="648" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:0 %empty_65 = or i11 %add_ln29_17, i11 1

]]></Node>
<StgValue><ssdm name="empty_65"/></StgValue>
</operation>

<operation id="852" st_id="77" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_6" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="649" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:1 %empty_66 = mul i11 %add_ln29_17, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_66"/></StgValue>
</operation>

<operation id="853" st_id="77" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_6" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="650" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:2 %empty_67 = mul i11 %empty_65, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_67"/></StgValue>
</operation>
</state>

<state id="78" st_id="78">

<operation id="854" st_id="78" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="649" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:1 %empty_66 = mul i11 %add_ln29_17, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_66"/></StgValue>
</operation>

<operation id="855" st_id="78" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="650" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:2 %empty_67 = mul i11 %empty_65, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_67"/></StgValue>
</operation>
</state>

<state id="79" st_id="79">

<operation id="856" st_id="79" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="649" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:1 %empty_66 = mul i11 %add_ln29_17, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_66"/></StgValue>
</operation>

<operation id="857" st_id="79" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="650" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:2 %empty_67 = mul i11 %empty_65, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_67"/></StgValue>
</operation>
</state>

<state id="80" st_id="80">

<operation id="858" st_id="80" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="649" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:1 %empty_66 = mul i11 %add_ln29_17, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_66"/></StgValue>
</operation>

<operation id="859" st_id="80" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="650" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:2 %empty_67 = mul i11 %empty_65, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_67"/></StgValue>
</operation>

<operation id="860" st_id="80" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="651" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.6:3 %add_ln32_15 = add i11 %zext_ln29_4, i11 %trunc_ln29_6

]]></Node>
<StgValue><ssdm name="add_ln32_15"/></StgValue>
</operation>

<operation id="861" st_id="80" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="652" bw="0" op_0_bw="0">
<![CDATA[
.split4.6:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="81" st_id="81">

<operation id="862" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="654" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_6 = phi i11 %add_ln34_6, void %.split.6_ifconv, i11 %add_ln32_15, void %.split4.6

]]></Node>
<StgValue><ssdm name="t_1_6"/></StgValue>
</operation>

<operation id="863" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="655" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_6 = phi i64 %add_ln32_6, void %.split.6_ifconv, i64 0, void %.split4.6

]]></Node>
<StgValue><ssdm name="j_6"/></StgValue>
</operation>

<operation id="864" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="656" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="865" st_id="81" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="657" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_6 = icmp_eq  i64 %j_6, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_6"/></StgValue>
</operation>

<operation id="866" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="658" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_68 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_68"/></StgValue>
</operation>

<operation id="867" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="659" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_6, void %.split.6_ifconv, void %._crit_edge.loopexit.6

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="868" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="663" bw="11" op_0_bw="64">
<![CDATA[
.split.6_ifconv:2 %empty_69 = trunc i64 %j_6

]]></Node>
<StgValue><ssdm name="empty_69"/></StgValue>
</operation>

<operation id="869" st_id="81" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="665" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:4 %add_ln8_24 = add i11 %empty_69, i11 %empty_66

]]></Node>
<StgValue><ssdm name="add_ln8_24"/></StgValue>
</operation>

<operation id="870" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="666" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:5 %zext_ln8_24 = zext i11 %add_ln8_24

]]></Node>
<StgValue><ssdm name="zext_ln8_24"/></StgValue>
</operation>

<operation id="871" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="667" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:6 %arr_addr_24 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_24

]]></Node>
<StgValue><ssdm name="arr_addr_24"/></StgValue>
</operation>

<operation id="872" st_id="81" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="668" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:7 %arr_load_24 = load i11 %arr_addr_24

]]></Node>
<StgValue><ssdm name="arr_load_24"/></StgValue>
</operation>

<operation id="873" st_id="81" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="669" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:8 %add_ln8_25 = add i11 %empty_69, i11 %empty_67

]]></Node>
<StgValue><ssdm name="add_ln8_25"/></StgValue>
</operation>

<operation id="874" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="670" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:9 %zext_ln8_25 = zext i11 %add_ln8_25

]]></Node>
<StgValue><ssdm name="zext_ln8_25"/></StgValue>
</operation>

<operation id="875" st_id="81" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="671" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:10 %arr_addr_25 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_25

]]></Node>
<StgValue><ssdm name="arr_addr_25"/></StgValue>
</operation>

<operation id="876" st_id="81" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="672" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:11 %arr_load_25 = load i11 %arr_addr_25

]]></Node>
<StgValue><ssdm name="arr_load_25"/></StgValue>
</operation>
</state>

<state id="82" st_id="82">

<operation id="877" st_id="82" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="668" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:7 %arr_load_24 = load i11 %arr_addr_24

]]></Node>
<StgValue><ssdm name="arr_load_24"/></StgValue>
</operation>

<operation id="878" st_id="82" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="672" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:11 %arr_load_25 = load i11 %arr_addr_25

]]></Node>
<StgValue><ssdm name="arr_load_25"/></StgValue>
</operation>

<operation id="879" st_id="82" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="673" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:12 %or_ln34_6 = or i11 %empty_69, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_6"/></StgValue>
</operation>

<operation id="880" st_id="82" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="674" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:13 %add_ln8_26 = add i11 %or_ln34_6, i11 %empty_66

]]></Node>
<StgValue><ssdm name="add_ln8_26"/></StgValue>
</operation>

<operation id="881" st_id="82" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="675" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:14 %zext_ln8_26 = zext i11 %add_ln8_26

]]></Node>
<StgValue><ssdm name="zext_ln8_26"/></StgValue>
</operation>

<operation id="882" st_id="82" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="676" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:15 %arr_addr_26 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_26

]]></Node>
<StgValue><ssdm name="arr_addr_26"/></StgValue>
</operation>

<operation id="883" st_id="82" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="677" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:16 %arr_load_26 = load i11 %arr_addr_26

]]></Node>
<StgValue><ssdm name="arr_load_26"/></StgValue>
</operation>

<operation id="884" st_id="82" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="678" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:17 %add_ln8_27 = add i11 %or_ln34_6, i11 %empty_67

]]></Node>
<StgValue><ssdm name="add_ln8_27"/></StgValue>
</operation>

<operation id="885" st_id="82" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="679" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:18 %zext_ln8_27 = zext i11 %add_ln8_27

]]></Node>
<StgValue><ssdm name="zext_ln8_27"/></StgValue>
</operation>

<operation id="886" st_id="82" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="680" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:19 %arr_addr_27 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_27

]]></Node>
<StgValue><ssdm name="arr_addr_27"/></StgValue>
</operation>

<operation id="887" st_id="82" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:20 %arr_load_27 = load i11 %arr_addr_27

]]></Node>
<StgValue><ssdm name="arr_load_27"/></StgValue>
</operation>

<operation id="888" st_id="82" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="695" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:34 %tmp_1096 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_25

]]></Node>
<StgValue><ssdm name="tmp_1096"/></StgValue>
</operation>
</state>

<state id="83" st_id="83">

<operation id="889" st_id="83" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="661" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.6_ifconv:0 %add_ln32_6 = add i64 %j_6, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_6"/></StgValue>
</operation>

<operation id="890" st_id="83" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="677" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:16 %arr_load_26 = load i11 %arr_addr_26

]]></Node>
<StgValue><ssdm name="arr_load_26"/></StgValue>
</operation>

<operation id="891" st_id="83" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="681" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:20 %arr_load_27 = load i11 %arr_addr_27

]]></Node>
<StgValue><ssdm name="arr_load_27"/></StgValue>
</operation>

<operation id="892" st_id="83" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="682" bw="32" op_0_bw="32">
<![CDATA[
.split.6_ifconv:21 %bitcast_ln13_24 = bitcast i32 %arr_load_24

]]></Node>
<StgValue><ssdm name="bitcast_ln13_24"/></StgValue>
</operation>

<operation id="893" st_id="83" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="683" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.6_ifconv:22 %tmp_1094 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_24, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1094"/></StgValue>
</operation>

<operation id="894" st_id="83" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="684" bw="23" op_0_bw="32">
<![CDATA[
.split.6_ifconv:23 %trunc_ln13_24 = trunc i32 %bitcast_ln13_24

]]></Node>
<StgValue><ssdm name="trunc_ln13_24"/></StgValue>
</operation>

<operation id="895" st_id="83" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="688" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.6_ifconv:27 %icmp_ln13_48 = icmp_ne  i8 %tmp_1094, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_48"/></StgValue>
</operation>

<operation id="896" st_id="83" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="689" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.6_ifconv:28 %icmp_ln13_49 = icmp_eq  i23 %trunc_ln13_24, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_49"/></StgValue>
</operation>

<operation id="897" st_id="83" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="690" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:29 %or_ln13_24 = or i1 %icmp_ln13_49, i1 %icmp_ln13_48

]]></Node>
<StgValue><ssdm name="or_ln13_24"/></StgValue>
</operation>

<operation id="898" st_id="83" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="695" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:34 %tmp_1096 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_25

]]></Node>
<StgValue><ssdm name="tmp_1096"/></StgValue>
</operation>

<operation id="899" st_id="83" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="704" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:43 %tmp_1098 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_26

]]></Node>
<StgValue><ssdm name="tmp_1098"/></StgValue>
</operation>

<operation id="900" st_id="83" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="713" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:52 %tmp_1100 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1100"/></StgValue>
</operation>
</state>

<state id="84" st_id="84">

<operation id="901" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="685" bw="32" op_0_bw="32">
<![CDATA[
.split.6_ifconv:24 %bitcast_ln13_25 = bitcast i32 %arr_load_25

]]></Node>
<StgValue><ssdm name="bitcast_ln13_25"/></StgValue>
</operation>

<operation id="902" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="686" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.6_ifconv:25 %tmp_1095 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_25, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1095"/></StgValue>
</operation>

<operation id="903" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="687" bw="23" op_0_bw="32">
<![CDATA[
.split.6_ifconv:26 %trunc_ln13_25 = trunc i32 %bitcast_ln13_25

]]></Node>
<StgValue><ssdm name="trunc_ln13_25"/></StgValue>
</operation>

<operation id="904" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="691" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.6_ifconv:30 %icmp_ln13_50 = icmp_ne  i8 %tmp_1095, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_50"/></StgValue>
</operation>

<operation id="905" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="692" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.6_ifconv:31 %icmp_ln13_51 = icmp_eq  i23 %trunc_ln13_25, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_51"/></StgValue>
</operation>

<operation id="906" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="693" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:32 %or_ln13_25 = or i1 %icmp_ln13_51, i1 %icmp_ln13_50

]]></Node>
<StgValue><ssdm name="or_ln13_25"/></StgValue>
</operation>

<operation id="907" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="694" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:33 %and_ln13_52 = and i1 %or_ln13_24, i1 %or_ln13_25

]]></Node>
<StgValue><ssdm name="and_ln13_52"/></StgValue>
</operation>

<operation id="908" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="696" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:35 %and_ln13_53 = and i1 %and_ln13_52, i1 %tmp_1096

]]></Node>
<StgValue><ssdm name="and_ln13_53"/></StgValue>
</operation>

<operation id="909" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="697" bw="32" op_0_bw="32">
<![CDATA[
.split.6_ifconv:36 %bitcast_ln13_26 = bitcast i32 %arr_load_26

]]></Node>
<StgValue><ssdm name="bitcast_ln13_26"/></StgValue>
</operation>

<operation id="910" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="698" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.6_ifconv:37 %tmp_1097 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_26, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1097"/></StgValue>
</operation>

<operation id="911" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="699" bw="23" op_0_bw="32">
<![CDATA[
.split.6_ifconv:38 %trunc_ln13_26 = trunc i32 %bitcast_ln13_26

]]></Node>
<StgValue><ssdm name="trunc_ln13_26"/></StgValue>
</operation>

<operation id="912" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="700" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.6_ifconv:39 %icmp_ln13_52 = icmp_ne  i8 %tmp_1097, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_52"/></StgValue>
</operation>

<operation id="913" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="701" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.6_ifconv:40 %icmp_ln13_53 = icmp_eq  i23 %trunc_ln13_26, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_53"/></StgValue>
</operation>

<operation id="914" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="702" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:41 %or_ln13_26 = or i1 %icmp_ln13_53, i1 %icmp_ln13_52

]]></Node>
<StgValue><ssdm name="or_ln13_26"/></StgValue>
</operation>

<operation id="915" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="703" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:42 %and_ln13_54 = and i1 %or_ln13_24, i1 %or_ln13_26

]]></Node>
<StgValue><ssdm name="and_ln13_54"/></StgValue>
</operation>

<operation id="916" st_id="84" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="704" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:43 %tmp_1098 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_26

]]></Node>
<StgValue><ssdm name="tmp_1098"/></StgValue>
</operation>

<operation id="917" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="705" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:44 %and_ln13_55 = and i1 %and_ln13_54, i1 %tmp_1098

]]></Node>
<StgValue><ssdm name="and_ln13_55"/></StgValue>
</operation>

<operation id="918" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="706" bw="32" op_0_bw="32">
<![CDATA[
.split.6_ifconv:45 %bitcast_ln13_27 = bitcast i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="bitcast_ln13_27"/></StgValue>
</operation>

<operation id="919" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="707" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.6_ifconv:46 %tmp_1099 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_27, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1099"/></StgValue>
</operation>

<operation id="920" st_id="84" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="708" bw="23" op_0_bw="32">
<![CDATA[
.split.6_ifconv:47 %trunc_ln13_27 = trunc i32 %bitcast_ln13_27

]]></Node>
<StgValue><ssdm name="trunc_ln13_27"/></StgValue>
</operation>

<operation id="921" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="709" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.6_ifconv:48 %icmp_ln13_54 = icmp_ne  i8 %tmp_1099, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_54"/></StgValue>
</operation>

<operation id="922" st_id="84" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="710" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.6_ifconv:49 %icmp_ln13_55 = icmp_eq  i23 %trunc_ln13_27, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_55"/></StgValue>
</operation>

<operation id="923" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="711" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:50 %or_ln13_27 = or i1 %icmp_ln13_55, i1 %icmp_ln13_54

]]></Node>
<StgValue><ssdm name="or_ln13_27"/></StgValue>
</operation>

<operation id="924" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="712" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:51 %and_ln13_56 = and i1 %or_ln13_24, i1 %or_ln13_27

]]></Node>
<StgValue><ssdm name="and_ln13_56"/></StgValue>
</operation>

<operation id="925" st_id="84" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="713" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:52 %tmp_1100 = fcmp_ogt  i32 %arr_load_24, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1100"/></StgValue>
</operation>

<operation id="926" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="714" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:53 %and_ln13_57 = and i1 %and_ln13_56, i1 %tmp_1100

]]></Node>
<StgValue><ssdm name="and_ln13_57"/></StgValue>
</operation>

<operation id="927" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="715" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:54 %and_ln13_58 = and i1 %and_ln13_55, i1 %and_ln13_57

]]></Node>
<StgValue><ssdm name="and_ln13_58"/></StgValue>
</operation>

<operation id="928" st_id="84" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="716" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:55 %and_ln13_16 = and i1 %and_ln13_58, i1 %and_ln13_53

]]></Node>
<StgValue><ssdm name="and_ln13_16"/></StgValue>
</operation>

<operation id="929" st_id="84" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="718" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:57 %tmp_1101 = fcmp_ogt  i32 %arr_load_25, i32 %arr_load_26

]]></Node>
<StgValue><ssdm name="tmp_1101"/></StgValue>
</operation>

<operation id="930" st_id="84" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:60 %tmp_1102 = fcmp_ogt  i32 %arr_load_25, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1102"/></StgValue>
</operation>
</state>

<state id="85" st_id="85">

<operation id="931" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="717" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:56 %and_ln16_40 = and i1 %or_ln13_25, i1 %or_ln13_26

]]></Node>
<StgValue><ssdm name="and_ln16_40"/></StgValue>
</operation>

<operation id="932" st_id="85" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="718" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:57 %tmp_1101 = fcmp_ogt  i32 %arr_load_25, i32 %arr_load_26

]]></Node>
<StgValue><ssdm name="tmp_1101"/></StgValue>
</operation>

<operation id="933" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="719" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:58 %and_ln16_41 = and i1 %and_ln16_40, i1 %tmp_1101

]]></Node>
<StgValue><ssdm name="and_ln16_41"/></StgValue>
</operation>

<operation id="934" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="720" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:59 %and_ln16_42 = and i1 %or_ln13_25, i1 %or_ln13_27

]]></Node>
<StgValue><ssdm name="and_ln16_42"/></StgValue>
</operation>

<operation id="935" st_id="85" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="721" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:60 %tmp_1102 = fcmp_ogt  i32 %arr_load_25, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1102"/></StgValue>
</operation>

<operation id="936" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="722" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:61 %and_ln16_43 = and i1 %and_ln16_42, i1 %tmp_1102

]]></Node>
<StgValue><ssdm name="and_ln16_43"/></StgValue>
</operation>

<operation id="937" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="723" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:62 %and_ln16_6 = and i1 %and_ln16_41, i1 %and_ln16_43

]]></Node>
<StgValue><ssdm name="and_ln16_6"/></StgValue>
</operation>

<operation id="938" st_id="85" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="725" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:64 %tmp_1103 = fcmp_ogt  i32 %arr_load_26, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1103"/></StgValue>
</operation>

<operation id="939" st_id="85" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="727" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.6_ifconv:66 %select_ln13_6 = select i1 %and_ln13_16, i11 %add_ln8_24, i11 %add_ln8_27

]]></Node>
<StgValue><ssdm name="select_ln13_6"/></StgValue>
</operation>

<operation id="940" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="728" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:67 %xor_ln13_6 = xor i1 %and_ln13_16, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_6"/></StgValue>
</operation>

<operation id="941" st_id="85" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="729" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:68 %and_ln16_44 = and i1 %and_ln16_6, i1 %xor_ln13_6

]]></Node>
<StgValue><ssdm name="and_ln16_44"/></StgValue>
</operation>

<operation id="942" st_id="85" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="730" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.6_ifconv:69 %select_ln16_6 = select i1 %and_ln16_44, i11 %add_ln8_25, i11 %select_ln13_6

]]></Node>
<StgValue><ssdm name="select_ln16_6"/></StgValue>
</operation>
</state>

<state id="86" st_id="86">

<operation id="943" st_id="86" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="724" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:63 %and_ln19_18 = and i1 %or_ln13_26, i1 %or_ln13_27

]]></Node>
<StgValue><ssdm name="and_ln19_18"/></StgValue>
</operation>

<operation id="944" st_id="86" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="725" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.6_ifconv:64 %tmp_1103 = fcmp_ogt  i32 %arr_load_26, i32 %arr_load_27

]]></Node>
<StgValue><ssdm name="tmp_1103"/></StgValue>
</operation>

<operation id="945" st_id="86" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="726" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:65 %and_ln19_19 = and i1 %and_ln19_18, i1 %tmp_1103

]]></Node>
<StgValue><ssdm name="and_ln19_19"/></StgValue>
</operation>

<operation id="946" st_id="86" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="731" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:70 %or_ln16_6 = or i1 %and_ln13_16, i1 %and_ln16_6

]]></Node>
<StgValue><ssdm name="or_ln16_6"/></StgValue>
</operation>

<operation id="947" st_id="86" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="732" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:71 %xor_ln16_6 = xor i1 %or_ln16_6, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_6"/></StgValue>
</operation>

<operation id="948" st_id="86" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="733" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.6_ifconv:72 %and_ln19_20 = and i1 %and_ln19_19, i1 %xor_ln16_6

]]></Node>
<StgValue><ssdm name="and_ln19_20"/></StgValue>
</operation>

<operation id="949" st_id="86" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="734" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.6_ifconv:73 %select_ln19_6 = select i1 %and_ln19_20, i11 %add_ln8_26, i11 %select_ln16_6

]]></Node>
<StgValue><ssdm name="select_ln19_6"/></StgValue>
</operation>

<operation id="950" st_id="86" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="735" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:74 %zext_ln8_46 = zext i11 %select_ln19_6

]]></Node>
<StgValue><ssdm name="zext_ln8_46"/></StgValue>
</operation>

<operation id="951" st_id="86" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="736" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:75 %arr_addr_46 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_46

]]></Node>
<StgValue><ssdm name="arr_addr_46"/></StgValue>
</operation>

<operation id="952" st_id="86" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="737" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:76 %arr_load_46 = load i11 %arr_addr_46

]]></Node>
<StgValue><ssdm name="arr_load_46"/></StgValue>
</operation>
</state>

<state id="87" st_id="87">

<operation id="953" st_id="87" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="662" bw="64" op_0_bw="11">
<![CDATA[
.split.6_ifconv:1 %t_1_6_cast = zext i11 %t_1_6

]]></Node>
<StgValue><ssdm name="t_1_6_cast"/></StgValue>
</operation>

<operation id="954" st_id="87" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="664" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.6_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="955" st_id="87" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="737" bw="32" op_0_bw="11">
<![CDATA[
.split.6_ifconv:76 %arr_load_46 = load i11 %arr_addr_46

]]></Node>
<StgValue><ssdm name="arr_load_46"/></StgValue>
</operation>

<operation id="956" st_id="87" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="738" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.6_ifconv:77 %add_ln34_6 = add i11 %t_1_6, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_6"/></StgValue>
</operation>

<operation id="957" st_id="87" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="739" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.6_ifconv:78 %out_addr_6 = getelementptr i32 %out_r, i64 0, i64 %t_1_6_cast

]]></Node>
<StgValue><ssdm name="out_addr_6"/></StgValue>
</operation>

<operation id="958" st_id="87" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="740" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.6_ifconv:79 %store_ln34 = store i32 %arr_load_46, i11 %out_addr_6

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="959" st_id="87" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_6" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="741" bw="0" op_0_bw="0">
<![CDATA[
.split.6_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="88" st_id="88">

<operation id="960" st_id="88" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="743" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.6:0 %trunc_ln29_7 = trunc i32 %add_ln29_15

]]></Node>
<StgValue><ssdm name="trunc_ln29_7"/></StgValue>
</operation>

<operation id="961" st_id="88" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="744" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.6:1 %add_ln29_18 = add i32 %zext_ln29_3, i32 %add_ln29_15

]]></Node>
<StgValue><ssdm name="add_ln29_18"/></StgValue>
</operation>

<operation id="962" st_id="88" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="745" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.6:2 %add_ln29_19 = add i64 %i_0, i64 14

]]></Node>
<StgValue><ssdm name="add_ln29_19"/></StgValue>
</operation>

<operation id="963" st_id="88" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="746" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.6:3 %add_ln29_20 = add i11 %trunc_ln29_1, i11 14

]]></Node>
<StgValue><ssdm name="add_ln29_20"/></StgValue>
</operation>

<operation id="964" st_id="88" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="747" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.6:4 %icmp_ln29_7 = icmp_slt  i64 %add_ln29_19, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_7"/></StgValue>
</operation>

<operation id="965" st_id="88" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="748" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.6:5 %br_ln29 = br i1 %icmp_ln29_7, void %._crit_edge10, void %.split4.7

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="966" st_id="88" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="750" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:0 %empty_70 = or i11 %add_ln29_20, i11 1

]]></Node>
<StgValue><ssdm name="empty_70"/></StgValue>
</operation>

<operation id="967" st_id="88" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="751" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:1 %empty_71 = mul i11 %add_ln29_20, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_71"/></StgValue>
</operation>

<operation id="968" st_id="88" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="752" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:2 %empty_72 = mul i11 %empty_70, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_72"/></StgValue>
</operation>

<operation id="969" st_id="88" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_7" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="753" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:3 %add_ln32_16 = add i11 %zext_ln29_4, i11 %trunc_ln29_7

]]></Node>
<StgValue><ssdm name="add_ln32_16"/></StgValue>
</operation>
</state>

<state id="89" st_id="89">

<operation id="970" st_id="89" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="751" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:1 %empty_71 = mul i11 %add_ln29_20, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_71"/></StgValue>
</operation>

<operation id="971" st_id="89" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="752" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:2 %empty_72 = mul i11 %empty_70, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_72"/></StgValue>
</operation>
</state>

<state id="90" st_id="90">

<operation id="972" st_id="90" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="751" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:1 %empty_71 = mul i11 %add_ln29_20, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_71"/></StgValue>
</operation>

<operation id="973" st_id="90" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="752" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:2 %empty_72 = mul i11 %empty_70, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_72"/></StgValue>
</operation>
</state>

<state id="91" st_id="91">

<operation id="974" st_id="91" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="751" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:1 %empty_71 = mul i11 %add_ln29_20, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_71"/></StgValue>
</operation>

<operation id="975" st_id="91" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="752" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.7:2 %empty_72 = mul i11 %empty_70, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_72"/></StgValue>
</operation>

<operation id="976" st_id="91" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="754" bw="0" op_0_bw="0">
<![CDATA[
.split4.7:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="92" st_id="92">

<operation id="977" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="756" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_7 = phi i11 %add_ln34_7, void %.split.7_ifconv, i11 %add_ln32_16, void %.split4.7

]]></Node>
<StgValue><ssdm name="t_1_7"/></StgValue>
</operation>

<operation id="978" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="757" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_7 = phi i64 %add_ln32_7, void %.split.7_ifconv, i64 0, void %.split4.7

]]></Node>
<StgValue><ssdm name="j_7"/></StgValue>
</operation>

<operation id="979" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="758" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="980" st_id="92" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="759" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_7 = icmp_eq  i64 %j_7, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_7"/></StgValue>
</operation>

<operation id="981" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="760" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_73 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_73"/></StgValue>
</operation>

<operation id="982" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="761" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_7, void %.split.7_ifconv, void %._crit_edge.loopexit.7

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="983" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="765" bw="11" op_0_bw="64">
<![CDATA[
.split.7_ifconv:2 %empty_74 = trunc i64 %j_7

]]></Node>
<StgValue><ssdm name="empty_74"/></StgValue>
</operation>

<operation id="984" st_id="92" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="767" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:4 %add_ln8_28 = add i11 %empty_74, i11 %empty_71

]]></Node>
<StgValue><ssdm name="add_ln8_28"/></StgValue>
</operation>

<operation id="985" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="768" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:5 %zext_ln8_28 = zext i11 %add_ln8_28

]]></Node>
<StgValue><ssdm name="zext_ln8_28"/></StgValue>
</operation>

<operation id="986" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="769" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:6 %arr_addr_28 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_28

]]></Node>
<StgValue><ssdm name="arr_addr_28"/></StgValue>
</operation>

<operation id="987" st_id="92" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:7 %arr_load_28 = load i11 %arr_addr_28

]]></Node>
<StgValue><ssdm name="arr_load_28"/></StgValue>
</operation>

<operation id="988" st_id="92" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="771" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:8 %add_ln8_29 = add i11 %empty_74, i11 %empty_72

]]></Node>
<StgValue><ssdm name="add_ln8_29"/></StgValue>
</operation>

<operation id="989" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="772" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:9 %zext_ln8_29 = zext i11 %add_ln8_29

]]></Node>
<StgValue><ssdm name="zext_ln8_29"/></StgValue>
</operation>

<operation id="990" st_id="92" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="773" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:10 %arr_addr_29 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_29

]]></Node>
<StgValue><ssdm name="arr_addr_29"/></StgValue>
</operation>

<operation id="991" st_id="92" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="774" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:11 %arr_load_29 = load i11 %arr_addr_29

]]></Node>
<StgValue><ssdm name="arr_load_29"/></StgValue>
</operation>
</state>

<state id="93" st_id="93">

<operation id="992" st_id="93" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="770" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:7 %arr_load_28 = load i11 %arr_addr_28

]]></Node>
<StgValue><ssdm name="arr_load_28"/></StgValue>
</operation>

<operation id="993" st_id="93" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="774" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:11 %arr_load_29 = load i11 %arr_addr_29

]]></Node>
<StgValue><ssdm name="arr_load_29"/></StgValue>
</operation>

<operation id="994" st_id="93" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="775" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:12 %or_ln34_7 = or i11 %empty_74, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_7"/></StgValue>
</operation>

<operation id="995" st_id="93" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="776" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:13 %add_ln8_30 = add i11 %or_ln34_7, i11 %empty_71

]]></Node>
<StgValue><ssdm name="add_ln8_30"/></StgValue>
</operation>

<operation id="996" st_id="93" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="777" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:14 %zext_ln8_30 = zext i11 %add_ln8_30

]]></Node>
<StgValue><ssdm name="zext_ln8_30"/></StgValue>
</operation>

<operation id="997" st_id="93" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="778" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:15 %arr_addr_30 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_30

]]></Node>
<StgValue><ssdm name="arr_addr_30"/></StgValue>
</operation>

<operation id="998" st_id="93" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="779" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:16 %arr_load_30 = load i11 %arr_addr_30

]]></Node>
<StgValue><ssdm name="arr_load_30"/></StgValue>
</operation>

<operation id="999" st_id="93" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="780" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:17 %add_ln8_31 = add i11 %or_ln34_7, i11 %empty_72

]]></Node>
<StgValue><ssdm name="add_ln8_31"/></StgValue>
</operation>

<operation id="1000" st_id="93" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="781" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:18 %zext_ln8_31 = zext i11 %add_ln8_31

]]></Node>
<StgValue><ssdm name="zext_ln8_31"/></StgValue>
</operation>

<operation id="1001" st_id="93" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="782" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:19 %arr_addr_31 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_31

]]></Node>
<StgValue><ssdm name="arr_addr_31"/></StgValue>
</operation>

<operation id="1002" st_id="93" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="783" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:20 %arr_load_31 = load i11 %arr_addr_31

]]></Node>
<StgValue><ssdm name="arr_load_31"/></StgValue>
</operation>

<operation id="1003" st_id="93" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="797" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:34 %tmp_1106 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_29

]]></Node>
<StgValue><ssdm name="tmp_1106"/></StgValue>
</operation>
</state>

<state id="94" st_id="94">

<operation id="1004" st_id="94" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="763" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.7_ifconv:0 %add_ln32_7 = add i64 %j_7, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_7"/></StgValue>
</operation>

<operation id="1005" st_id="94" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="779" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:16 %arr_load_30 = load i11 %arr_addr_30

]]></Node>
<StgValue><ssdm name="arr_load_30"/></StgValue>
</operation>

<operation id="1006" st_id="94" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="783" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:20 %arr_load_31 = load i11 %arr_addr_31

]]></Node>
<StgValue><ssdm name="arr_load_31"/></StgValue>
</operation>

<operation id="1007" st_id="94" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="784" bw="32" op_0_bw="32">
<![CDATA[
.split.7_ifconv:21 %bitcast_ln13_28 = bitcast i32 %arr_load_28

]]></Node>
<StgValue><ssdm name="bitcast_ln13_28"/></StgValue>
</operation>

<operation id="1008" st_id="94" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="785" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.7_ifconv:22 %tmp_1104 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_28, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1104"/></StgValue>
</operation>

<operation id="1009" st_id="94" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="786" bw="23" op_0_bw="32">
<![CDATA[
.split.7_ifconv:23 %trunc_ln13_28 = trunc i32 %bitcast_ln13_28

]]></Node>
<StgValue><ssdm name="trunc_ln13_28"/></StgValue>
</operation>

<operation id="1010" st_id="94" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="790" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.7_ifconv:27 %icmp_ln13_56 = icmp_ne  i8 %tmp_1104, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_56"/></StgValue>
</operation>

<operation id="1011" st_id="94" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="791" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.7_ifconv:28 %icmp_ln13_57 = icmp_eq  i23 %trunc_ln13_28, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_57"/></StgValue>
</operation>

<operation id="1012" st_id="94" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="792" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:29 %or_ln13_28 = or i1 %icmp_ln13_57, i1 %icmp_ln13_56

]]></Node>
<StgValue><ssdm name="or_ln13_28"/></StgValue>
</operation>

<operation id="1013" st_id="94" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="797" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:34 %tmp_1106 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_29

]]></Node>
<StgValue><ssdm name="tmp_1106"/></StgValue>
</operation>

<operation id="1014" st_id="94" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="806" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:43 %tmp_1108 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_30

]]></Node>
<StgValue><ssdm name="tmp_1108"/></StgValue>
</operation>

<operation id="1015" st_id="94" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:52 %tmp_1110 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1110"/></StgValue>
</operation>
</state>

<state id="95" st_id="95">

<operation id="1016" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="787" bw="32" op_0_bw="32">
<![CDATA[
.split.7_ifconv:24 %bitcast_ln13_29 = bitcast i32 %arr_load_29

]]></Node>
<StgValue><ssdm name="bitcast_ln13_29"/></StgValue>
</operation>

<operation id="1017" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="788" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.7_ifconv:25 %tmp_1105 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_29, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1105"/></StgValue>
</operation>

<operation id="1018" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="789" bw="23" op_0_bw="32">
<![CDATA[
.split.7_ifconv:26 %trunc_ln13_29 = trunc i32 %bitcast_ln13_29

]]></Node>
<StgValue><ssdm name="trunc_ln13_29"/></StgValue>
</operation>

<operation id="1019" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="793" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.7_ifconv:30 %icmp_ln13_58 = icmp_ne  i8 %tmp_1105, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_58"/></StgValue>
</operation>

<operation id="1020" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="794" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.7_ifconv:31 %icmp_ln13_59 = icmp_eq  i23 %trunc_ln13_29, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_59"/></StgValue>
</operation>

<operation id="1021" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="795" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:32 %or_ln13_29 = or i1 %icmp_ln13_59, i1 %icmp_ln13_58

]]></Node>
<StgValue><ssdm name="or_ln13_29"/></StgValue>
</operation>

<operation id="1022" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="796" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:33 %and_ln13_59 = and i1 %or_ln13_28, i1 %or_ln13_29

]]></Node>
<StgValue><ssdm name="and_ln13_59"/></StgValue>
</operation>

<operation id="1023" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="798" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:35 %and_ln13_60 = and i1 %and_ln13_59, i1 %tmp_1106

]]></Node>
<StgValue><ssdm name="and_ln13_60"/></StgValue>
</operation>

<operation id="1024" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="799" bw="32" op_0_bw="32">
<![CDATA[
.split.7_ifconv:36 %bitcast_ln13_30 = bitcast i32 %arr_load_30

]]></Node>
<StgValue><ssdm name="bitcast_ln13_30"/></StgValue>
</operation>

<operation id="1025" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="800" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.7_ifconv:37 %tmp_1107 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_30, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1107"/></StgValue>
</operation>

<operation id="1026" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="801" bw="23" op_0_bw="32">
<![CDATA[
.split.7_ifconv:38 %trunc_ln13_30 = trunc i32 %bitcast_ln13_30

]]></Node>
<StgValue><ssdm name="trunc_ln13_30"/></StgValue>
</operation>

<operation id="1027" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="802" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.7_ifconv:39 %icmp_ln13_60 = icmp_ne  i8 %tmp_1107, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_60"/></StgValue>
</operation>

<operation id="1028" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="803" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.7_ifconv:40 %icmp_ln13_61 = icmp_eq  i23 %trunc_ln13_30, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_61"/></StgValue>
</operation>

<operation id="1029" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="804" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:41 %or_ln13_30 = or i1 %icmp_ln13_61, i1 %icmp_ln13_60

]]></Node>
<StgValue><ssdm name="or_ln13_30"/></StgValue>
</operation>

<operation id="1030" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="805" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:42 %and_ln13_61 = and i1 %or_ln13_28, i1 %or_ln13_30

]]></Node>
<StgValue><ssdm name="and_ln13_61"/></StgValue>
</operation>

<operation id="1031" st_id="95" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="806" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:43 %tmp_1108 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_30

]]></Node>
<StgValue><ssdm name="tmp_1108"/></StgValue>
</operation>

<operation id="1032" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="807" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:44 %and_ln13_62 = and i1 %and_ln13_61, i1 %tmp_1108

]]></Node>
<StgValue><ssdm name="and_ln13_62"/></StgValue>
</operation>

<operation id="1033" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="808" bw="32" op_0_bw="32">
<![CDATA[
.split.7_ifconv:45 %bitcast_ln13_31 = bitcast i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="bitcast_ln13_31"/></StgValue>
</operation>

<operation id="1034" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="809" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.7_ifconv:46 %tmp_1109 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_31, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1109"/></StgValue>
</operation>

<operation id="1035" st_id="95" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="810" bw="23" op_0_bw="32">
<![CDATA[
.split.7_ifconv:47 %trunc_ln13_31 = trunc i32 %bitcast_ln13_31

]]></Node>
<StgValue><ssdm name="trunc_ln13_31"/></StgValue>
</operation>

<operation id="1036" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="811" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.7_ifconv:48 %icmp_ln13_62 = icmp_ne  i8 %tmp_1109, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_62"/></StgValue>
</operation>

<operation id="1037" st_id="95" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="812" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.7_ifconv:49 %icmp_ln13_63 = icmp_eq  i23 %trunc_ln13_31, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_63"/></StgValue>
</operation>

<operation id="1038" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="813" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:50 %or_ln13_31 = or i1 %icmp_ln13_63, i1 %icmp_ln13_62

]]></Node>
<StgValue><ssdm name="or_ln13_31"/></StgValue>
</operation>

<operation id="1039" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="814" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:51 %and_ln13_63 = and i1 %or_ln13_28, i1 %or_ln13_31

]]></Node>
<StgValue><ssdm name="and_ln13_63"/></StgValue>
</operation>

<operation id="1040" st_id="95" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="815" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:52 %tmp_1110 = fcmp_ogt  i32 %arr_load_28, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1110"/></StgValue>
</operation>

<operation id="1041" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="816" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:53 %and_ln13_64 = and i1 %and_ln13_63, i1 %tmp_1110

]]></Node>
<StgValue><ssdm name="and_ln13_64"/></StgValue>
</operation>

<operation id="1042" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="817" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:54 %and_ln13_65 = and i1 %and_ln13_62, i1 %and_ln13_64

]]></Node>
<StgValue><ssdm name="and_ln13_65"/></StgValue>
</operation>

<operation id="1043" st_id="95" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="818" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:55 %and_ln13_17 = and i1 %and_ln13_65, i1 %and_ln13_60

]]></Node>
<StgValue><ssdm name="and_ln13_17"/></StgValue>
</operation>

<operation id="1044" st_id="95" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="820" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:57 %tmp_1111 = fcmp_ogt  i32 %arr_load_29, i32 %arr_load_30

]]></Node>
<StgValue><ssdm name="tmp_1111"/></StgValue>
</operation>

<operation id="1045" st_id="95" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="823" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:60 %tmp_1112 = fcmp_ogt  i32 %arr_load_29, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1112"/></StgValue>
</operation>
</state>

<state id="96" st_id="96">

<operation id="1046" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="819" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:56 %and_ln16_45 = and i1 %or_ln13_29, i1 %or_ln13_30

]]></Node>
<StgValue><ssdm name="and_ln16_45"/></StgValue>
</operation>

<operation id="1047" st_id="96" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="820" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:57 %tmp_1111 = fcmp_ogt  i32 %arr_load_29, i32 %arr_load_30

]]></Node>
<StgValue><ssdm name="tmp_1111"/></StgValue>
</operation>

<operation id="1048" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="821" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:58 %and_ln16_46 = and i1 %and_ln16_45, i1 %tmp_1111

]]></Node>
<StgValue><ssdm name="and_ln16_46"/></StgValue>
</operation>

<operation id="1049" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="822" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:59 %and_ln16_47 = and i1 %or_ln13_29, i1 %or_ln13_31

]]></Node>
<StgValue><ssdm name="and_ln16_47"/></StgValue>
</operation>

<operation id="1050" st_id="96" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="823" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:60 %tmp_1112 = fcmp_ogt  i32 %arr_load_29, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1112"/></StgValue>
</operation>

<operation id="1051" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="824" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:61 %and_ln16_48 = and i1 %and_ln16_47, i1 %tmp_1112

]]></Node>
<StgValue><ssdm name="and_ln16_48"/></StgValue>
</operation>

<operation id="1052" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="825" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:62 %and_ln16_7 = and i1 %and_ln16_46, i1 %and_ln16_48

]]></Node>
<StgValue><ssdm name="and_ln16_7"/></StgValue>
</operation>

<operation id="1053" st_id="96" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:64 %tmp_1113 = fcmp_ogt  i32 %arr_load_30, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1113"/></StgValue>
</operation>

<operation id="1054" st_id="96" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="829" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.7_ifconv:66 %select_ln13_7 = select i1 %and_ln13_17, i11 %add_ln8_28, i11 %add_ln8_31

]]></Node>
<StgValue><ssdm name="select_ln13_7"/></StgValue>
</operation>

<operation id="1055" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="830" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:67 %xor_ln13_7 = xor i1 %and_ln13_17, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_7"/></StgValue>
</operation>

<operation id="1056" st_id="96" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="831" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:68 %and_ln16_49 = and i1 %and_ln16_7, i1 %xor_ln13_7

]]></Node>
<StgValue><ssdm name="and_ln16_49"/></StgValue>
</operation>

<operation id="1057" st_id="96" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="832" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.7_ifconv:69 %select_ln16_7 = select i1 %and_ln16_49, i11 %add_ln8_29, i11 %select_ln13_7

]]></Node>
<StgValue><ssdm name="select_ln16_7"/></StgValue>
</operation>
</state>

<state id="97" st_id="97">

<operation id="1058" st_id="97" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="826" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:63 %and_ln19_21 = and i1 %or_ln13_30, i1 %or_ln13_31

]]></Node>
<StgValue><ssdm name="and_ln19_21"/></StgValue>
</operation>

<operation id="1059" st_id="97" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="827" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.7_ifconv:64 %tmp_1113 = fcmp_ogt  i32 %arr_load_30, i32 %arr_load_31

]]></Node>
<StgValue><ssdm name="tmp_1113"/></StgValue>
</operation>

<operation id="1060" st_id="97" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="828" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:65 %and_ln19_22 = and i1 %and_ln19_21, i1 %tmp_1113

]]></Node>
<StgValue><ssdm name="and_ln19_22"/></StgValue>
</operation>

<operation id="1061" st_id="97" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="833" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:70 %or_ln16_7 = or i1 %and_ln13_17, i1 %and_ln16_7

]]></Node>
<StgValue><ssdm name="or_ln16_7"/></StgValue>
</operation>

<operation id="1062" st_id="97" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="834" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:71 %xor_ln16_7 = xor i1 %or_ln16_7, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_7"/></StgValue>
</operation>

<operation id="1063" st_id="97" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="835" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.7_ifconv:72 %and_ln19_23 = and i1 %and_ln19_22, i1 %xor_ln16_7

]]></Node>
<StgValue><ssdm name="and_ln19_23"/></StgValue>
</operation>

<operation id="1064" st_id="97" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="836" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.7_ifconv:73 %select_ln19_7 = select i1 %and_ln19_23, i11 %add_ln8_30, i11 %select_ln16_7

]]></Node>
<StgValue><ssdm name="select_ln19_7"/></StgValue>
</operation>

<operation id="1065" st_id="97" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="837" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:74 %zext_ln8_47 = zext i11 %select_ln19_7

]]></Node>
<StgValue><ssdm name="zext_ln8_47"/></StgValue>
</operation>

<operation id="1066" st_id="97" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="838" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:75 %arr_addr_47 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_47

]]></Node>
<StgValue><ssdm name="arr_addr_47"/></StgValue>
</operation>

<operation id="1067" st_id="97" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:76 %arr_load_47 = load i11 %arr_addr_47

]]></Node>
<StgValue><ssdm name="arr_load_47"/></StgValue>
</operation>
</state>

<state id="98" st_id="98">

<operation id="1068" st_id="98" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="764" bw="64" op_0_bw="11">
<![CDATA[
.split.7_ifconv:1 %t_1_7_cast = zext i11 %t_1_7

]]></Node>
<StgValue><ssdm name="t_1_7_cast"/></StgValue>
</operation>

<operation id="1069" st_id="98" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="766" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.7_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="1070" st_id="98" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="839" bw="32" op_0_bw="11">
<![CDATA[
.split.7_ifconv:76 %arr_load_47 = load i11 %arr_addr_47

]]></Node>
<StgValue><ssdm name="arr_load_47"/></StgValue>
</operation>

<operation id="1071" st_id="98" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="840" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.7_ifconv:77 %add_ln34_7 = add i11 %t_1_7, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_7"/></StgValue>
</operation>

<operation id="1072" st_id="98" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="841" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.7_ifconv:78 %out_addr_7 = getelementptr i32 %out_r, i64 0, i64 %t_1_7_cast

]]></Node>
<StgValue><ssdm name="out_addr_7"/></StgValue>
</operation>

<operation id="1073" st_id="98" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="842" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.7_ifconv:79 %store_ln34 = store i32 %arr_load_47, i11 %out_addr_7

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="1074" st_id="98" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_7" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="843" bw="0" op_0_bw="0">
<![CDATA[
.split.7_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="99" st_id="99">

<operation id="1075" st_id="99" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="845" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.7:0 %trunc_ln29_8 = trunc i32 %add_ln29_18

]]></Node>
<StgValue><ssdm name="trunc_ln29_8"/></StgValue>
</operation>

<operation id="1076" st_id="99" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="846" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.7:1 %add_ln29_21 = add i32 %zext_ln29_3, i32 %add_ln29_18

]]></Node>
<StgValue><ssdm name="add_ln29_21"/></StgValue>
</operation>

<operation id="1077" st_id="99" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="847" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.7:2 %add_ln29_22 = add i64 %i_0, i64 16

]]></Node>
<StgValue><ssdm name="add_ln29_22"/></StgValue>
</operation>

<operation id="1078" st_id="99" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="848" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.7:3 %add_ln29_23 = add i11 %trunc_ln29_1, i11 16

]]></Node>
<StgValue><ssdm name="add_ln29_23"/></StgValue>
</operation>

<operation id="1079" st_id="99" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="849" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.7:4 %icmp_ln29_8 = icmp_slt  i64 %add_ln29_22, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_8"/></StgValue>
</operation>

<operation id="1080" st_id="99" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="850" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.7:5 %br_ln29 = br i1 %icmp_ln29_8, void %._crit_edge10, void %.split4.8

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="1081" st_id="99" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_8" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="852" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:0 %empty_75 = or i11 %add_ln29_23, i11 1

]]></Node>
<StgValue><ssdm name="empty_75"/></StgValue>
</operation>

<operation id="1082" st_id="99" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_8" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="853" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:1 %empty_76 = mul i11 %add_ln29_23, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_76"/></StgValue>
</operation>

<operation id="1083" st_id="99" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_8" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="854" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:2 %empty_77 = mul i11 %empty_75, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_77"/></StgValue>
</operation>
</state>

<state id="100" st_id="100">

<operation id="1084" st_id="100" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="853" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:1 %empty_76 = mul i11 %add_ln29_23, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_76"/></StgValue>
</operation>

<operation id="1085" st_id="100" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="854" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:2 %empty_77 = mul i11 %empty_75, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_77"/></StgValue>
</operation>
</state>

<state id="101" st_id="101">

<operation id="1086" st_id="101" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="853" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:1 %empty_76 = mul i11 %add_ln29_23, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_76"/></StgValue>
</operation>

<operation id="1087" st_id="101" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="854" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:2 %empty_77 = mul i11 %empty_75, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_77"/></StgValue>
</operation>
</state>

<state id="102" st_id="102">

<operation id="1088" st_id="102" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="853" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:1 %empty_76 = mul i11 %add_ln29_23, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_76"/></StgValue>
</operation>

<operation id="1089" st_id="102" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="854" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:2 %empty_77 = mul i11 %empty_75, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_77"/></StgValue>
</operation>

<operation id="1090" st_id="102" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="855" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.8:3 %add_ln32_17 = add i11 %zext_ln29_4, i11 %trunc_ln29_8

]]></Node>
<StgValue><ssdm name="add_ln32_17"/></StgValue>
</operation>

<operation id="1091" st_id="102" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="856" bw="0" op_0_bw="0">
<![CDATA[
.split4.8:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="103" st_id="103">

<operation id="1092" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="858" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_8 = phi i11 %add_ln34_8, void %.split.8_ifconv, i11 %add_ln32_17, void %.split4.8

]]></Node>
<StgValue><ssdm name="t_1_8"/></StgValue>
</operation>

<operation id="1093" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="859" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_8 = phi i64 %add_ln32_8, void %.split.8_ifconv, i64 0, void %.split4.8

]]></Node>
<StgValue><ssdm name="j_8"/></StgValue>
</operation>

<operation id="1094" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="860" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1095" st_id="103" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="861" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_8 = icmp_eq  i64 %j_8, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_8"/></StgValue>
</operation>

<operation id="1096" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="862" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_78 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_78"/></StgValue>
</operation>

<operation id="1097" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="863" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_8, void %.split.8_ifconv, void %._crit_edge.loopexit.8

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="1098" st_id="103" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="865" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.8_ifconv:0 %add_ln32_8 = add i64 %j_8, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_8"/></StgValue>
</operation>

<operation id="1099" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="867" bw="11" op_0_bw="64">
<![CDATA[
.split.8_ifconv:2 %empty_79 = trunc i64 %j_8

]]></Node>
<StgValue><ssdm name="empty_79"/></StgValue>
</operation>

<operation id="1100" st_id="103" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="869" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:4 %add_ln8_32 = add i11 %empty_79, i11 %empty_76

]]></Node>
<StgValue><ssdm name="add_ln8_32"/></StgValue>
</operation>

<operation id="1101" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="870" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:5 %zext_ln8_32 = zext i11 %add_ln8_32

]]></Node>
<StgValue><ssdm name="zext_ln8_32"/></StgValue>
</operation>

<operation id="1102" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="871" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:6 %arr_addr_32 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_32

]]></Node>
<StgValue><ssdm name="arr_addr_32"/></StgValue>
</operation>

<operation id="1103" st_id="103" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="872" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:7 %arr_load_32 = load i11 %arr_addr_32

]]></Node>
<StgValue><ssdm name="arr_load_32"/></StgValue>
</operation>

<operation id="1104" st_id="103" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="873" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:8 %add_ln8_33 = add i11 %empty_79, i11 %empty_77

]]></Node>
<StgValue><ssdm name="add_ln8_33"/></StgValue>
</operation>

<operation id="1105" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="874" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:9 %zext_ln8_33 = zext i11 %add_ln8_33

]]></Node>
<StgValue><ssdm name="zext_ln8_33"/></StgValue>
</operation>

<operation id="1106" st_id="103" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="875" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:10 %arr_addr_33 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_33

]]></Node>
<StgValue><ssdm name="arr_addr_33"/></StgValue>
</operation>

<operation id="1107" st_id="103" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="876" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:11 %arr_load_33 = load i11 %arr_addr_33

]]></Node>
<StgValue><ssdm name="arr_load_33"/></StgValue>
</operation>
</state>

<state id="104" st_id="104">

<operation id="1108" st_id="104" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="872" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:7 %arr_load_32 = load i11 %arr_addr_32

]]></Node>
<StgValue><ssdm name="arr_load_32"/></StgValue>
</operation>

<operation id="1109" st_id="104" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="876" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:11 %arr_load_33 = load i11 %arr_addr_33

]]></Node>
<StgValue><ssdm name="arr_load_33"/></StgValue>
</operation>

<operation id="1110" st_id="104" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="877" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:12 %or_ln34_8 = or i11 %empty_79, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_8"/></StgValue>
</operation>

<operation id="1111" st_id="104" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="878" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:13 %add_ln8_34 = add i11 %or_ln34_8, i11 %empty_76

]]></Node>
<StgValue><ssdm name="add_ln8_34"/></StgValue>
</operation>

<operation id="1112" st_id="104" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="879" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:14 %zext_ln8_34 = zext i11 %add_ln8_34

]]></Node>
<StgValue><ssdm name="zext_ln8_34"/></StgValue>
</operation>

<operation id="1113" st_id="104" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="880" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:15 %arr_addr_34 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_34

]]></Node>
<StgValue><ssdm name="arr_addr_34"/></StgValue>
</operation>

<operation id="1114" st_id="104" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="881" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:16 %arr_load_34 = load i11 %arr_addr_34

]]></Node>
<StgValue><ssdm name="arr_load_34"/></StgValue>
</operation>

<operation id="1115" st_id="104" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="882" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:17 %add_ln8_35 = add i11 %or_ln34_8, i11 %empty_77

]]></Node>
<StgValue><ssdm name="add_ln8_35"/></StgValue>
</operation>

<operation id="1116" st_id="104" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="883" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:18 %zext_ln8_35 = zext i11 %add_ln8_35

]]></Node>
<StgValue><ssdm name="zext_ln8_35"/></StgValue>
</operation>

<operation id="1117" st_id="104" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="884" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:19 %arr_addr_35 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_35

]]></Node>
<StgValue><ssdm name="arr_addr_35"/></StgValue>
</operation>

<operation id="1118" st_id="104" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="885" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:20 %arr_load_35 = load i11 %arr_addr_35

]]></Node>
<StgValue><ssdm name="arr_load_35"/></StgValue>
</operation>

<operation id="1119" st_id="104" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="899" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:34 %tmp_1116 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_33

]]></Node>
<StgValue><ssdm name="tmp_1116"/></StgValue>
</operation>
</state>

<state id="105" st_id="105">

<operation id="1120" st_id="105" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="881" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:16 %arr_load_34 = load i11 %arr_addr_34

]]></Node>
<StgValue><ssdm name="arr_load_34"/></StgValue>
</operation>

<operation id="1121" st_id="105" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="885" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:20 %arr_load_35 = load i11 %arr_addr_35

]]></Node>
<StgValue><ssdm name="arr_load_35"/></StgValue>
</operation>

<operation id="1122" st_id="105" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="886" bw="32" op_0_bw="32">
<![CDATA[
.split.8_ifconv:21 %bitcast_ln13_32 = bitcast i32 %arr_load_32

]]></Node>
<StgValue><ssdm name="bitcast_ln13_32"/></StgValue>
</operation>

<operation id="1123" st_id="105" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="887" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.8_ifconv:22 %tmp_1114 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_32, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1114"/></StgValue>
</operation>

<operation id="1124" st_id="105" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="888" bw="23" op_0_bw="32">
<![CDATA[
.split.8_ifconv:23 %trunc_ln13_32 = trunc i32 %bitcast_ln13_32

]]></Node>
<StgValue><ssdm name="trunc_ln13_32"/></StgValue>
</operation>

<operation id="1125" st_id="105" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="892" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.8_ifconv:27 %icmp_ln13_64 = icmp_ne  i8 %tmp_1114, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_64"/></StgValue>
</operation>

<operation id="1126" st_id="105" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="893" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.8_ifconv:28 %icmp_ln13_65 = icmp_eq  i23 %trunc_ln13_32, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_65"/></StgValue>
</operation>

<operation id="1127" st_id="105" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="894" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:29 %or_ln13_32 = or i1 %icmp_ln13_65, i1 %icmp_ln13_64

]]></Node>
<StgValue><ssdm name="or_ln13_32"/></StgValue>
</operation>

<operation id="1128" st_id="105" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="899" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:34 %tmp_1116 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_33

]]></Node>
<StgValue><ssdm name="tmp_1116"/></StgValue>
</operation>

<operation id="1129" st_id="105" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="908" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:43 %tmp_1118 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_34

]]></Node>
<StgValue><ssdm name="tmp_1118"/></StgValue>
</operation>

<operation id="1130" st_id="105" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="917" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:52 %tmp_1120 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1120"/></StgValue>
</operation>
</state>

<state id="106" st_id="106">

<operation id="1131" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="889" bw="32" op_0_bw="32">
<![CDATA[
.split.8_ifconv:24 %bitcast_ln13_33 = bitcast i32 %arr_load_33

]]></Node>
<StgValue><ssdm name="bitcast_ln13_33"/></StgValue>
</operation>

<operation id="1132" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="890" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.8_ifconv:25 %tmp_1115 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_33, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1115"/></StgValue>
</operation>

<operation id="1133" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="891" bw="23" op_0_bw="32">
<![CDATA[
.split.8_ifconv:26 %trunc_ln13_33 = trunc i32 %bitcast_ln13_33

]]></Node>
<StgValue><ssdm name="trunc_ln13_33"/></StgValue>
</operation>

<operation id="1134" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="895" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.8_ifconv:30 %icmp_ln13_66 = icmp_ne  i8 %tmp_1115, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_66"/></StgValue>
</operation>

<operation id="1135" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="896" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.8_ifconv:31 %icmp_ln13_67 = icmp_eq  i23 %trunc_ln13_33, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_67"/></StgValue>
</operation>

<operation id="1136" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="897" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:32 %or_ln13_33 = or i1 %icmp_ln13_67, i1 %icmp_ln13_66

]]></Node>
<StgValue><ssdm name="or_ln13_33"/></StgValue>
</operation>

<operation id="1137" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="898" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:33 %and_ln13_66 = and i1 %or_ln13_32, i1 %or_ln13_33

]]></Node>
<StgValue><ssdm name="and_ln13_66"/></StgValue>
</operation>

<operation id="1138" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="900" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:35 %and_ln13_67 = and i1 %and_ln13_66, i1 %tmp_1116

]]></Node>
<StgValue><ssdm name="and_ln13_67"/></StgValue>
</operation>

<operation id="1139" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="901" bw="32" op_0_bw="32">
<![CDATA[
.split.8_ifconv:36 %bitcast_ln13_34 = bitcast i32 %arr_load_34

]]></Node>
<StgValue><ssdm name="bitcast_ln13_34"/></StgValue>
</operation>

<operation id="1140" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="902" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.8_ifconv:37 %tmp_1117 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_34, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1117"/></StgValue>
</operation>

<operation id="1141" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="903" bw="23" op_0_bw="32">
<![CDATA[
.split.8_ifconv:38 %trunc_ln13_34 = trunc i32 %bitcast_ln13_34

]]></Node>
<StgValue><ssdm name="trunc_ln13_34"/></StgValue>
</operation>

<operation id="1142" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="904" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.8_ifconv:39 %icmp_ln13_68 = icmp_ne  i8 %tmp_1117, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_68"/></StgValue>
</operation>

<operation id="1143" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="905" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.8_ifconv:40 %icmp_ln13_69 = icmp_eq  i23 %trunc_ln13_34, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_69"/></StgValue>
</operation>

<operation id="1144" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="906" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:41 %or_ln13_34 = or i1 %icmp_ln13_69, i1 %icmp_ln13_68

]]></Node>
<StgValue><ssdm name="or_ln13_34"/></StgValue>
</operation>

<operation id="1145" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="907" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:42 %and_ln13_68 = and i1 %or_ln13_32, i1 %or_ln13_34

]]></Node>
<StgValue><ssdm name="and_ln13_68"/></StgValue>
</operation>

<operation id="1146" st_id="106" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="908" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:43 %tmp_1118 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_34

]]></Node>
<StgValue><ssdm name="tmp_1118"/></StgValue>
</operation>

<operation id="1147" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="909" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:44 %and_ln13_69 = and i1 %and_ln13_68, i1 %tmp_1118

]]></Node>
<StgValue><ssdm name="and_ln13_69"/></StgValue>
</operation>

<operation id="1148" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="910" bw="32" op_0_bw="32">
<![CDATA[
.split.8_ifconv:45 %bitcast_ln13_35 = bitcast i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="bitcast_ln13_35"/></StgValue>
</operation>

<operation id="1149" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="911" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.8_ifconv:46 %tmp_1119 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_35, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1119"/></StgValue>
</operation>

<operation id="1150" st_id="106" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="912" bw="23" op_0_bw="32">
<![CDATA[
.split.8_ifconv:47 %trunc_ln13_35 = trunc i32 %bitcast_ln13_35

]]></Node>
<StgValue><ssdm name="trunc_ln13_35"/></StgValue>
</operation>

<operation id="1151" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="913" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.8_ifconv:48 %icmp_ln13_70 = icmp_ne  i8 %tmp_1119, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_70"/></StgValue>
</operation>

<operation id="1152" st_id="106" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="914" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.8_ifconv:49 %icmp_ln13_71 = icmp_eq  i23 %trunc_ln13_35, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_71"/></StgValue>
</operation>

<operation id="1153" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="915" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:50 %or_ln13_35 = or i1 %icmp_ln13_71, i1 %icmp_ln13_70

]]></Node>
<StgValue><ssdm name="or_ln13_35"/></StgValue>
</operation>

<operation id="1154" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="916" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:51 %and_ln13_70 = and i1 %or_ln13_32, i1 %or_ln13_35

]]></Node>
<StgValue><ssdm name="and_ln13_70"/></StgValue>
</operation>

<operation id="1155" st_id="106" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="917" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:52 %tmp_1120 = fcmp_ogt  i32 %arr_load_32, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1120"/></StgValue>
</operation>

<operation id="1156" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="918" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:53 %and_ln13_71 = and i1 %and_ln13_70, i1 %tmp_1120

]]></Node>
<StgValue><ssdm name="and_ln13_71"/></StgValue>
</operation>

<operation id="1157" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="919" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:54 %and_ln13_72 = and i1 %and_ln13_69, i1 %and_ln13_71

]]></Node>
<StgValue><ssdm name="and_ln13_72"/></StgValue>
</operation>

<operation id="1158" st_id="106" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="920" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:55 %and_ln13_18 = and i1 %and_ln13_72, i1 %and_ln13_67

]]></Node>
<StgValue><ssdm name="and_ln13_18"/></StgValue>
</operation>

<operation id="1159" st_id="106" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="922" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:57 %tmp_1121 = fcmp_ogt  i32 %arr_load_33, i32 %arr_load_34

]]></Node>
<StgValue><ssdm name="tmp_1121"/></StgValue>
</operation>

<operation id="1160" st_id="106" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="925" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:60 %tmp_1122 = fcmp_ogt  i32 %arr_load_33, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1122"/></StgValue>
</operation>
</state>

<state id="107" st_id="107">

<operation id="1161" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="921" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:56 %and_ln16_50 = and i1 %or_ln13_33, i1 %or_ln13_34

]]></Node>
<StgValue><ssdm name="and_ln16_50"/></StgValue>
</operation>

<operation id="1162" st_id="107" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="922" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:57 %tmp_1121 = fcmp_ogt  i32 %arr_load_33, i32 %arr_load_34

]]></Node>
<StgValue><ssdm name="tmp_1121"/></StgValue>
</operation>

<operation id="1163" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="923" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:58 %and_ln16_51 = and i1 %and_ln16_50, i1 %tmp_1121

]]></Node>
<StgValue><ssdm name="and_ln16_51"/></StgValue>
</operation>

<operation id="1164" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="924" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:59 %and_ln16_52 = and i1 %or_ln13_33, i1 %or_ln13_35

]]></Node>
<StgValue><ssdm name="and_ln16_52"/></StgValue>
</operation>

<operation id="1165" st_id="107" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="925" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:60 %tmp_1122 = fcmp_ogt  i32 %arr_load_33, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1122"/></StgValue>
</operation>

<operation id="1166" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="926" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:61 %and_ln16_53 = and i1 %and_ln16_52, i1 %tmp_1122

]]></Node>
<StgValue><ssdm name="and_ln16_53"/></StgValue>
</operation>

<operation id="1167" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="927" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:62 %and_ln16_8 = and i1 %and_ln16_51, i1 %and_ln16_53

]]></Node>
<StgValue><ssdm name="and_ln16_8"/></StgValue>
</operation>

<operation id="1168" st_id="107" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="929" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:64 %tmp_1123 = fcmp_ogt  i32 %arr_load_34, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1123"/></StgValue>
</operation>

<operation id="1169" st_id="107" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="931" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.8_ifconv:66 %select_ln13_8 = select i1 %and_ln13_18, i11 %add_ln8_32, i11 %add_ln8_35

]]></Node>
<StgValue><ssdm name="select_ln13_8"/></StgValue>
</operation>

<operation id="1170" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="932" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:67 %xor_ln13_8 = xor i1 %and_ln13_18, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_8"/></StgValue>
</operation>

<operation id="1171" st_id="107" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="933" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:68 %and_ln16_54 = and i1 %and_ln16_8, i1 %xor_ln13_8

]]></Node>
<StgValue><ssdm name="and_ln16_54"/></StgValue>
</operation>

<operation id="1172" st_id="107" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="934" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.8_ifconv:69 %select_ln16_8 = select i1 %and_ln16_54, i11 %add_ln8_33, i11 %select_ln13_8

]]></Node>
<StgValue><ssdm name="select_ln16_8"/></StgValue>
</operation>
</state>

<state id="108" st_id="108">

<operation id="1173" st_id="108" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="928" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:63 %and_ln19_24 = and i1 %or_ln13_34, i1 %or_ln13_35

]]></Node>
<StgValue><ssdm name="and_ln19_24"/></StgValue>
</operation>

<operation id="1174" st_id="108" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="929" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.8_ifconv:64 %tmp_1123 = fcmp_ogt  i32 %arr_load_34, i32 %arr_load_35

]]></Node>
<StgValue><ssdm name="tmp_1123"/></StgValue>
</operation>

<operation id="1175" st_id="108" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="930" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:65 %and_ln19_25 = and i1 %and_ln19_24, i1 %tmp_1123

]]></Node>
<StgValue><ssdm name="and_ln19_25"/></StgValue>
</operation>

<operation id="1176" st_id="108" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="935" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:70 %or_ln16_8 = or i1 %and_ln13_18, i1 %and_ln16_8

]]></Node>
<StgValue><ssdm name="or_ln16_8"/></StgValue>
</operation>

<operation id="1177" st_id="108" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="936" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:71 %xor_ln16_8 = xor i1 %or_ln16_8, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_8"/></StgValue>
</operation>

<operation id="1178" st_id="108" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="937" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.8_ifconv:72 %and_ln19_26 = and i1 %and_ln19_25, i1 %xor_ln16_8

]]></Node>
<StgValue><ssdm name="and_ln19_26"/></StgValue>
</operation>

<operation id="1179" st_id="108" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="938" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.8_ifconv:73 %select_ln19_8 = select i1 %and_ln19_26, i11 %add_ln8_34, i11 %select_ln16_8

]]></Node>
<StgValue><ssdm name="select_ln19_8"/></StgValue>
</operation>

<operation id="1180" st_id="108" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="939" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:74 %zext_ln8_48 = zext i11 %select_ln19_8

]]></Node>
<StgValue><ssdm name="zext_ln8_48"/></StgValue>
</operation>

<operation id="1181" st_id="108" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="940" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:75 %arr_addr_48 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_48

]]></Node>
<StgValue><ssdm name="arr_addr_48"/></StgValue>
</operation>

<operation id="1182" st_id="108" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="941" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:76 %arr_load_48 = load i11 %arr_addr_48

]]></Node>
<StgValue><ssdm name="arr_load_48"/></StgValue>
</operation>
</state>

<state id="109" st_id="109">

<operation id="1183" st_id="109" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="866" bw="64" op_0_bw="11">
<![CDATA[
.split.8_ifconv:1 %t_1_8_cast = zext i11 %t_1_8

]]></Node>
<StgValue><ssdm name="t_1_8_cast"/></StgValue>
</operation>

<operation id="1184" st_id="109" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="868" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.8_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="1185" st_id="109" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="941" bw="32" op_0_bw="11">
<![CDATA[
.split.8_ifconv:76 %arr_load_48 = load i11 %arr_addr_48

]]></Node>
<StgValue><ssdm name="arr_load_48"/></StgValue>
</operation>

<operation id="1186" st_id="109" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="942" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.8_ifconv:77 %add_ln34_8 = add i11 %t_1_8, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_8"/></StgValue>
</operation>

<operation id="1187" st_id="109" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="943" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.8_ifconv:78 %out_addr_8 = getelementptr i32 %out_r, i64 0, i64 %t_1_8_cast

]]></Node>
<StgValue><ssdm name="out_addr_8"/></StgValue>
</operation>

<operation id="1188" st_id="109" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="944" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.8_ifconv:79 %store_ln34 = store i32 %arr_load_48, i11 %out_addr_8

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="1189" st_id="109" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_8" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="945" bw="0" op_0_bw="0">
<![CDATA[
.split.8_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="110" st_id="110">

<operation id="1190" st_id="110" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="947" bw="11" op_0_bw="32">
<![CDATA[
._crit_edge.loopexit.8:0 %trunc_ln29_9 = trunc i32 %add_ln29_21

]]></Node>
<StgValue><ssdm name="trunc_ln29_9"/></StgValue>
</operation>

<operation id="1191" st_id="110" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="948" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.8:1 %add_ln29_24 = add i32 %zext_ln29_3, i32 %add_ln29_21

]]></Node>
<StgValue><ssdm name="add_ln29_24"/></StgValue>
</operation>

<operation id="1192" st_id="110" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="949" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.8:2 %add_ln29_25 = add i64 %i_0, i64 18

]]></Node>
<StgValue><ssdm name="add_ln29_25"/></StgValue>
</operation>

<operation id="1193" st_id="110" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="950" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
._crit_edge.loopexit.8:3 %add_ln29_26 = add i11 %trunc_ln29_1, i11 18

]]></Node>
<StgValue><ssdm name="add_ln29_26"/></StgValue>
</operation>

<operation id="1194" st_id="110" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="951" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.8:4 %icmp_ln29_9 = icmp_slt  i64 %add_ln29_25, i64 %zext_ln29

]]></Node>
<StgValue><ssdm name="icmp_ln29_9"/></StgValue>
</operation>

<operation id="1195" st_id="110" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="952" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
._crit_edge.loopexit.8:5 %br_ln29 = br i1 %icmp_ln29_9, void %._crit_edge10, void %.split4.9

]]></Node>
<StgValue><ssdm name="br_ln29"/></StgValue>
</operation>

<operation id="1196" st_id="110" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="954" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:0 %empty_80 = or i11 %add_ln29_26, i11 1

]]></Node>
<StgValue><ssdm name="empty_80"/></StgValue>
</operation>

<operation id="1197" st_id="110" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="955" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:1 %empty_81 = mul i11 %add_ln29_26, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_81"/></StgValue>
</operation>

<operation id="1198" st_id="110" stage="4" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="956" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:2 %empty_82 = mul i11 %empty_80, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_82"/></StgValue>
</operation>

<operation id="1199" st_id="110" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln29_9" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="957" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:3 %add_ln32_18 = add i11 %zext_ln29_4, i11 %trunc_ln29_9

]]></Node>
<StgValue><ssdm name="add_ln32_18"/></StgValue>
</operation>
</state>

<state id="111" st_id="111">

<operation id="1200" st_id="111" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="955" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:1 %empty_81 = mul i11 %add_ln29_26, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_81"/></StgValue>
</operation>

<operation id="1201" st_id="111" stage="3" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="956" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:2 %empty_82 = mul i11 %empty_80, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_82"/></StgValue>
</operation>
</state>

<state id="112" st_id="112">

<operation id="1202" st_id="112" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="955" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:1 %empty_81 = mul i11 %add_ln29_26, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_81"/></StgValue>
</operation>

<operation id="1203" st_id="112" stage="2" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="956" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:2 %empty_82 = mul i11 %empty_80, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_82"/></StgValue>
</operation>
</state>

<state id="113" st_id="113">

<operation id="1204" st_id="113" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="955" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:1 %empty_81 = mul i11 %add_ln29_26, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_81"/></StgValue>
</operation>

<operation id="1205" st_id="113" stage="1" lat="4">
<core>DSP48</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="956" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split4.9:2 %empty_82 = mul i11 %empty_80, i11 %zext_ln29_2

]]></Node>
<StgValue><ssdm name="empty_82"/></StgValue>
</operation>

<operation id="1206" st_id="113" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="958" bw="0" op_0_bw="0">
<![CDATA[
.split4.9:4 %br_ln32 = br void

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>
</state>

<state id="114" st_id="114">

<operation id="1207" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="961" bw="64" op_0_bw="64" op_1_bw="0" op_2_bw="64" op_3_bw="0">
<![CDATA[
:1 %j_9 = phi i64 %add_ln32_9, void %.split.9_ifconv, i64 0, void %.split4.9

]]></Node>
<StgValue><ssdm name="j_9"/></StgValue>
</operation>

<operation id="1208" st_id="114" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="963" bw="1" op_0_bw="64" op_1_bw="64">
<![CDATA[
:3 %icmp_ln32_9 = icmp_eq  i64 %j_9, i64 %zext_ln32

]]></Node>
<StgValue><ssdm name="icmp_ln32_9"/></StgValue>
</operation>

<operation id="1209" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="965" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:5 %br_ln32 = br i1 %icmp_ln32_9, void %.split.9_ifconv, void %._crit_edge.loopexit.9

]]></Node>
<StgValue><ssdm name="br_ln32"/></StgValue>
</operation>

<operation id="1210" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="969" bw="11" op_0_bw="64">
<![CDATA[
.split.9_ifconv:2 %empty_84 = trunc i64 %j_9

]]></Node>
<StgValue><ssdm name="empty_84"/></StgValue>
</operation>

<operation id="1211" st_id="114" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="971" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:4 %add_ln8_36 = add i11 %empty_84, i11 %empty_81

]]></Node>
<StgValue><ssdm name="add_ln8_36"/></StgValue>
</operation>

<operation id="1212" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="972" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:5 %zext_ln8_36 = zext i11 %add_ln8_36

]]></Node>
<StgValue><ssdm name="zext_ln8_36"/></StgValue>
</operation>

<operation id="1213" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="973" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:6 %arr_addr_36 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_36

]]></Node>
<StgValue><ssdm name="arr_addr_36"/></StgValue>
</operation>

<operation id="1214" st_id="114" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="974" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:7 %arr_load_36 = load i11 %arr_addr_36

]]></Node>
<StgValue><ssdm name="arr_load_36"/></StgValue>
</operation>

<operation id="1215" st_id="114" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="975" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:8 %add_ln8_37 = add i11 %empty_84, i11 %empty_82

]]></Node>
<StgValue><ssdm name="add_ln8_37"/></StgValue>
</operation>

<operation id="1216" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="976" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:9 %zext_ln8_37 = zext i11 %add_ln8_37

]]></Node>
<StgValue><ssdm name="zext_ln8_37"/></StgValue>
</operation>

<operation id="1217" st_id="114" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="977" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:10 %arr_addr_37 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_37

]]></Node>
<StgValue><ssdm name="arr_addr_37"/></StgValue>
</operation>

<operation id="1218" st_id="114" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="978" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:11 %arr_load_37 = load i11 %arr_addr_37

]]></Node>
<StgValue><ssdm name="arr_load_37"/></StgValue>
</operation>
</state>

<state id="115" st_id="115">

<operation id="1219" st_id="115" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="974" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:7 %arr_load_36 = load i11 %arr_addr_36

]]></Node>
<StgValue><ssdm name="arr_load_36"/></StgValue>
</operation>

<operation id="1220" st_id="115" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="978" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:11 %arr_load_37 = load i11 %arr_addr_37

]]></Node>
<StgValue><ssdm name="arr_load_37"/></StgValue>
</operation>

<operation id="1221" st_id="115" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="979" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:12 %or_ln34_9 = or i11 %empty_84, i11 1

]]></Node>
<StgValue><ssdm name="or_ln34_9"/></StgValue>
</operation>

<operation id="1222" st_id="115" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="980" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:13 %add_ln8_38 = add i11 %or_ln34_9, i11 %empty_81

]]></Node>
<StgValue><ssdm name="add_ln8_38"/></StgValue>
</operation>

<operation id="1223" st_id="115" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="981" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:14 %zext_ln8_38 = zext i11 %add_ln8_38

]]></Node>
<StgValue><ssdm name="zext_ln8_38"/></StgValue>
</operation>

<operation id="1224" st_id="115" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="982" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:15 %arr_addr_38 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_38

]]></Node>
<StgValue><ssdm name="arr_addr_38"/></StgValue>
</operation>

<operation id="1225" st_id="115" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="983" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:16 %arr_load_38 = load i11 %arr_addr_38

]]></Node>
<StgValue><ssdm name="arr_load_38"/></StgValue>
</operation>

<operation id="1226" st_id="115" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="984" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:17 %add_ln8_39 = add i11 %or_ln34_9, i11 %empty_82

]]></Node>
<StgValue><ssdm name="add_ln8_39"/></StgValue>
</operation>

<operation id="1227" st_id="115" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="985" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:18 %zext_ln8_39 = zext i11 %add_ln8_39

]]></Node>
<StgValue><ssdm name="zext_ln8_39"/></StgValue>
</operation>

<operation id="1228" st_id="115" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="986" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:19 %arr_addr_39 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_39

]]></Node>
<StgValue><ssdm name="arr_addr_39"/></StgValue>
</operation>

<operation id="1229" st_id="115" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="987" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:20 %arr_load_39 = load i11 %arr_addr_39

]]></Node>
<StgValue><ssdm name="arr_load_39"/></StgValue>
</operation>

<operation id="1230" st_id="115" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1001" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:34 %tmp_1126 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_37

]]></Node>
<StgValue><ssdm name="tmp_1126"/></StgValue>
</operation>
</state>

<state id="116" st_id="116">

<operation id="1231" st_id="116" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="967" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
.split.9_ifconv:0 %add_ln32_9 = add i64 %j_9, i64 2

]]></Node>
<StgValue><ssdm name="add_ln32_9"/></StgValue>
</operation>

<operation id="1232" st_id="116" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="983" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:16 %arr_load_38 = load i11 %arr_addr_38

]]></Node>
<StgValue><ssdm name="arr_load_38"/></StgValue>
</operation>

<operation id="1233" st_id="116" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="987" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:20 %arr_load_39 = load i11 %arr_addr_39

]]></Node>
<StgValue><ssdm name="arr_load_39"/></StgValue>
</operation>

<operation id="1234" st_id="116" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="988" bw="32" op_0_bw="32">
<![CDATA[
.split.9_ifconv:21 %bitcast_ln13_36 = bitcast i32 %arr_load_36

]]></Node>
<StgValue><ssdm name="bitcast_ln13_36"/></StgValue>
</operation>

<operation id="1235" st_id="116" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="989" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.9_ifconv:22 %tmp_1124 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_36, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1124"/></StgValue>
</operation>

<operation id="1236" st_id="116" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="990" bw="23" op_0_bw="32">
<![CDATA[
.split.9_ifconv:23 %trunc_ln13_36 = trunc i32 %bitcast_ln13_36

]]></Node>
<StgValue><ssdm name="trunc_ln13_36"/></StgValue>
</operation>

<operation id="1237" st_id="116" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="994" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.9_ifconv:27 %icmp_ln13_72 = icmp_ne  i8 %tmp_1124, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_72"/></StgValue>
</operation>

<operation id="1238" st_id="116" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="995" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.9_ifconv:28 %icmp_ln13_73 = icmp_eq  i23 %trunc_ln13_36, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_73"/></StgValue>
</operation>

<operation id="1239" st_id="116" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="996" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:29 %or_ln13_36 = or i1 %icmp_ln13_73, i1 %icmp_ln13_72

]]></Node>
<StgValue><ssdm name="or_ln13_36"/></StgValue>
</operation>

<operation id="1240" st_id="116" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1001" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:34 %tmp_1126 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_37

]]></Node>
<StgValue><ssdm name="tmp_1126"/></StgValue>
</operation>

<operation id="1241" st_id="116" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1010" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:43 %tmp_1128 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_38

]]></Node>
<StgValue><ssdm name="tmp_1128"/></StgValue>
</operation>

<operation id="1242" st_id="116" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1019" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:52 %tmp_1130 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1130"/></StgValue>
</operation>
</state>

<state id="117" st_id="117">

<operation id="1243" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="991" bw="32" op_0_bw="32">
<![CDATA[
.split.9_ifconv:24 %bitcast_ln13_37 = bitcast i32 %arr_load_37

]]></Node>
<StgValue><ssdm name="bitcast_ln13_37"/></StgValue>
</operation>

<operation id="1244" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="992" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.9_ifconv:25 %tmp_1125 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_37, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1125"/></StgValue>
</operation>

<operation id="1245" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="993" bw="23" op_0_bw="32">
<![CDATA[
.split.9_ifconv:26 %trunc_ln13_37 = trunc i32 %bitcast_ln13_37

]]></Node>
<StgValue><ssdm name="trunc_ln13_37"/></StgValue>
</operation>

<operation id="1246" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="997" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.9_ifconv:30 %icmp_ln13_74 = icmp_ne  i8 %tmp_1125, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_74"/></StgValue>
</operation>

<operation id="1247" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="998" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.9_ifconv:31 %icmp_ln13_75 = icmp_eq  i23 %trunc_ln13_37, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_75"/></StgValue>
</operation>

<operation id="1248" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="999" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:32 %or_ln13_37 = or i1 %icmp_ln13_75, i1 %icmp_ln13_74

]]></Node>
<StgValue><ssdm name="or_ln13_37"/></StgValue>
</operation>

<operation id="1249" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1000" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:33 %and_ln13_73 = and i1 %or_ln13_36, i1 %or_ln13_37

]]></Node>
<StgValue><ssdm name="and_ln13_73"/></StgValue>
</operation>

<operation id="1250" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1002" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:35 %and_ln13_74 = and i1 %and_ln13_73, i1 %tmp_1126

]]></Node>
<StgValue><ssdm name="and_ln13_74"/></StgValue>
</operation>

<operation id="1251" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1003" bw="32" op_0_bw="32">
<![CDATA[
.split.9_ifconv:36 %bitcast_ln13_38 = bitcast i32 %arr_load_38

]]></Node>
<StgValue><ssdm name="bitcast_ln13_38"/></StgValue>
</operation>

<operation id="1252" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1004" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.9_ifconv:37 %tmp_1127 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_38, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1127"/></StgValue>
</operation>

<operation id="1253" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1005" bw="23" op_0_bw="32">
<![CDATA[
.split.9_ifconv:38 %trunc_ln13_38 = trunc i32 %bitcast_ln13_38

]]></Node>
<StgValue><ssdm name="trunc_ln13_38"/></StgValue>
</operation>

<operation id="1254" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1006" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.9_ifconv:39 %icmp_ln13_76 = icmp_ne  i8 %tmp_1127, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_76"/></StgValue>
</operation>

<operation id="1255" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1007" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.9_ifconv:40 %icmp_ln13_77 = icmp_eq  i23 %trunc_ln13_38, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_77"/></StgValue>
</operation>

<operation id="1256" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1008" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:41 %or_ln13_38 = or i1 %icmp_ln13_77, i1 %icmp_ln13_76

]]></Node>
<StgValue><ssdm name="or_ln13_38"/></StgValue>
</operation>

<operation id="1257" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1009" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:42 %and_ln13_75 = and i1 %or_ln13_36, i1 %or_ln13_38

]]></Node>
<StgValue><ssdm name="and_ln13_75"/></StgValue>
</operation>

<operation id="1258" st_id="117" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1010" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:43 %tmp_1128 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_38

]]></Node>
<StgValue><ssdm name="tmp_1128"/></StgValue>
</operation>

<operation id="1259" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1011" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:44 %and_ln13_76 = and i1 %and_ln13_75, i1 %tmp_1128

]]></Node>
<StgValue><ssdm name="and_ln13_76"/></StgValue>
</operation>

<operation id="1260" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1012" bw="32" op_0_bw="32">
<![CDATA[
.split.9_ifconv:45 %bitcast_ln13_39 = bitcast i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="bitcast_ln13_39"/></StgValue>
</operation>

<operation id="1261" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1013" bw="8" op_0_bw="8" op_1_bw="32" op_2_bw="32" op_3_bw="32">
<![CDATA[
.split.9_ifconv:46 %tmp_1129 = partselect i8 @_ssdm_op_PartSelect.i8.i32.i32.i32, i32 %bitcast_ln13_39, i32 23, i32 30

]]></Node>
<StgValue><ssdm name="tmp_1129"/></StgValue>
</operation>

<operation id="1262" st_id="117" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1014" bw="23" op_0_bw="32">
<![CDATA[
.split.9_ifconv:47 %trunc_ln13_39 = trunc i32 %bitcast_ln13_39

]]></Node>
<StgValue><ssdm name="trunc_ln13_39"/></StgValue>
</operation>

<operation id="1263" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1015" bw="1" op_0_bw="8" op_1_bw="8">
<![CDATA[
.split.9_ifconv:48 %icmp_ln13_78 = icmp_ne  i8 %tmp_1129, i8 255

]]></Node>
<StgValue><ssdm name="icmp_ln13_78"/></StgValue>
</operation>

<operation id="1264" st_id="117" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1016" bw="1" op_0_bw="23" op_1_bw="23">
<![CDATA[
.split.9_ifconv:49 %icmp_ln13_79 = icmp_eq  i23 %trunc_ln13_39, i23 0

]]></Node>
<StgValue><ssdm name="icmp_ln13_79"/></StgValue>
</operation>

<operation id="1265" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1017" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:50 %or_ln13_39 = or i1 %icmp_ln13_79, i1 %icmp_ln13_78

]]></Node>
<StgValue><ssdm name="or_ln13_39"/></StgValue>
</operation>

<operation id="1266" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1018" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:51 %and_ln13_77 = and i1 %or_ln13_36, i1 %or_ln13_39

]]></Node>
<StgValue><ssdm name="and_ln13_77"/></StgValue>
</operation>

<operation id="1267" st_id="117" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1019" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:52 %tmp_1130 = fcmp_ogt  i32 %arr_load_36, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1130"/></StgValue>
</operation>

<operation id="1268" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1020" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:53 %and_ln13_78 = and i1 %and_ln13_77, i1 %tmp_1130

]]></Node>
<StgValue><ssdm name="and_ln13_78"/></StgValue>
</operation>

<operation id="1269" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1021" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:54 %and_ln13_79 = and i1 %and_ln13_76, i1 %and_ln13_78

]]></Node>
<StgValue><ssdm name="and_ln13_79"/></StgValue>
</operation>

<operation id="1270" st_id="117" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1022" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:55 %and_ln13_19 = and i1 %and_ln13_79, i1 %and_ln13_74

]]></Node>
<StgValue><ssdm name="and_ln13_19"/></StgValue>
</operation>

<operation id="1271" st_id="117" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1024" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:57 %tmp_1131 = fcmp_ogt  i32 %arr_load_37, i32 %arr_load_38

]]></Node>
<StgValue><ssdm name="tmp_1131"/></StgValue>
</operation>

<operation id="1272" st_id="117" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1027" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:60 %tmp_1132 = fcmp_ogt  i32 %arr_load_37, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1132"/></StgValue>
</operation>
</state>

<state id="118" st_id="118">

<operation id="1273" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1023" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:56 %and_ln16_55 = and i1 %or_ln13_37, i1 %or_ln13_38

]]></Node>
<StgValue><ssdm name="and_ln16_55"/></StgValue>
</operation>

<operation id="1274" st_id="118" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1024" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:57 %tmp_1131 = fcmp_ogt  i32 %arr_load_37, i32 %arr_load_38

]]></Node>
<StgValue><ssdm name="tmp_1131"/></StgValue>
</operation>

<operation id="1275" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1025" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:58 %and_ln16_56 = and i1 %and_ln16_55, i1 %tmp_1131

]]></Node>
<StgValue><ssdm name="and_ln16_56"/></StgValue>
</operation>

<operation id="1276" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1026" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:59 %and_ln16_57 = and i1 %or_ln13_37, i1 %or_ln13_39

]]></Node>
<StgValue><ssdm name="and_ln16_57"/></StgValue>
</operation>

<operation id="1277" st_id="118" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1027" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:60 %tmp_1132 = fcmp_ogt  i32 %arr_load_37, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1132"/></StgValue>
</operation>

<operation id="1278" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1028" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:61 %and_ln16_58 = and i1 %and_ln16_57, i1 %tmp_1132

]]></Node>
<StgValue><ssdm name="and_ln16_58"/></StgValue>
</operation>

<operation id="1279" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1029" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:62 %and_ln16_9 = and i1 %and_ln16_56, i1 %and_ln16_58

]]></Node>
<StgValue><ssdm name="and_ln16_9"/></StgValue>
</operation>

<operation id="1280" st_id="118" stage="2" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1031" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:64 %tmp_1133 = fcmp_ogt  i32 %arr_load_38, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1133"/></StgValue>
</operation>

<operation id="1281" st_id="118" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1033" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.9_ifconv:66 %select_ln13_9 = select i1 %and_ln13_19, i11 %add_ln8_36, i11 %add_ln8_39

]]></Node>
<StgValue><ssdm name="select_ln13_9"/></StgValue>
</operation>

<operation id="1282" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1034" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:67 %xor_ln13_9 = xor i1 %and_ln13_19, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln13_9"/></StgValue>
</operation>

<operation id="1283" st_id="118" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1035" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:68 %and_ln16_59 = and i1 %and_ln16_9, i1 %xor_ln13_9

]]></Node>
<StgValue><ssdm name="and_ln16_59"/></StgValue>
</operation>

<operation id="1284" st_id="118" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1036" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.9_ifconv:69 %select_ln16_9 = select i1 %and_ln16_59, i11 %add_ln8_37, i11 %select_ln13_9

]]></Node>
<StgValue><ssdm name="select_ln16_9"/></StgValue>
</operation>
</state>

<state id="119" st_id="119">

<operation id="1285" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="960" bw="11" op_0_bw="11" op_1_bw="0" op_2_bw="11" op_3_bw="0">
<![CDATA[
:0 %t_1_9 = phi i11 %add_ln34_9, void %.split.9_ifconv, i11 %add_ln32_18, void %.split4.9

]]></Node>
<StgValue><ssdm name="t_1_9"/></StgValue>
</operation>

<operation id="1286" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="962" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
:2 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="1287" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="964" bw="32" op_0_bw="32" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
:4 %empty_83 = speclooptripcount i32 @_ssdm_op_SpecLoopTripCount, i64 0, i64 32, i64 0

]]></Node>
<StgValue><ssdm name="empty_83"/></StgValue>
</operation>

<operation id="1288" st_id="119" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1030" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:63 %and_ln19_27 = and i1 %or_ln13_38, i1 %or_ln13_39

]]></Node>
<StgValue><ssdm name="and_ln19_27"/></StgValue>
</operation>

<operation id="1289" st_id="119" stage="1" lat="2">
<core>FCompare</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1031" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
.split.9_ifconv:64 %tmp_1133 = fcmp_ogt  i32 %arr_load_38, i32 %arr_load_39

]]></Node>
<StgValue><ssdm name="tmp_1133"/></StgValue>
</operation>

<operation id="1290" st_id="119" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1032" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:65 %and_ln19_28 = and i1 %and_ln19_27, i1 %tmp_1133

]]></Node>
<StgValue><ssdm name="and_ln19_28"/></StgValue>
</operation>

<operation id="1291" st_id="119" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1037" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:70 %or_ln16_9 = or i1 %and_ln13_19, i1 %and_ln16_9

]]></Node>
<StgValue><ssdm name="or_ln16_9"/></StgValue>
</operation>

<operation id="1292" st_id="119" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1038" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:71 %xor_ln16_9 = xor i1 %or_ln16_9, i1 1

]]></Node>
<StgValue><ssdm name="xor_ln16_9"/></StgValue>
</operation>

<operation id="1293" st_id="119" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1039" bw="1" op_0_bw="1" op_1_bw="1">
<![CDATA[
.split.9_ifconv:72 %and_ln19_29 = and i1 %and_ln19_28, i1 %xor_ln16_9

]]></Node>
<StgValue><ssdm name="and_ln19_29"/></StgValue>
</operation>

<operation id="1294" st_id="119" stage="1" lat="1">
<core>Sel</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1040" bw="11" op_0_bw="1" op_1_bw="11" op_2_bw="11">
<![CDATA[
.split.9_ifconv:73 %select_ln19_9 = select i1 %and_ln19_29, i11 %add_ln8_38, i11 %select_ln16_9

]]></Node>
<StgValue><ssdm name="select_ln19_9"/></StgValue>
</operation>

<operation id="1295" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1041" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:74 %zext_ln8_49 = zext i11 %select_ln19_9

]]></Node>
<StgValue><ssdm name="zext_ln8_49"/></StgValue>
</operation>

<operation id="1296" st_id="119" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1042" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:75 %arr_addr_49 = getelementptr i32 %arr, i64 0, i64 %zext_ln8_49

]]></Node>
<StgValue><ssdm name="arr_addr_49"/></StgValue>
</operation>

<operation id="1297" st_id="119" stage="2" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1043" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:76 %arr_load_49 = load i11 %arr_addr_49

]]></Node>
<StgValue><ssdm name="arr_load_49"/></StgValue>
</operation>
</state>

<state id="120" st_id="120">

<operation id="1298" st_id="120" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="968" bw="64" op_0_bw="11">
<![CDATA[
.split.9_ifconv:1 %t_1_9_cast = zext i11 %t_1_9

]]></Node>
<StgValue><ssdm name="t_1_9_cast"/></StgValue>
</operation>

<operation id="1299" st_id="120" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="970" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
.split.9_ifconv:3 %specloopname_ln28 = specloopname void @_ssdm_op_SpecLoopName, void @empty_0

]]></Node>
<StgValue><ssdm name="specloopname_ln28"/></StgValue>
</operation>

<operation id="1300" st_id="120" stage="1" lat="2">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1043" bw="32" op_0_bw="11">
<![CDATA[
.split.9_ifconv:76 %arr_load_49 = load i11 %arr_addr_49

]]></Node>
<StgValue><ssdm name="arr_load_49"/></StgValue>
</operation>

<operation id="1301" st_id="120" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1044" bw="11" op_0_bw="11" op_1_bw="11">
<![CDATA[
.split.9_ifconv:77 %add_ln34_9 = add i11 %t_1_9, i11 1

]]></Node>
<StgValue><ssdm name="add_ln34_9"/></StgValue>
</operation>

<operation id="1302" st_id="120" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1045" bw="11" op_0_bw="32" op_1_bw="64" op_2_bw="64">
<![CDATA[
.split.9_ifconv:78 %out_addr_9 = getelementptr i32 %out_r, i64 0, i64 %t_1_9_cast

]]></Node>
<StgValue><ssdm name="out_addr_9"/></StgValue>
</operation>

<operation id="1303" st_id="120" stage="1" lat="1">
<core>RAM</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1046" bw="0" op_0_bw="32" op_1_bw="11">
<![CDATA[
.split.9_ifconv:79 %store_ln34 = store i32 %arr_load_49, i11 %out_addr_9

]]></Node>
<StgValue><ssdm name="store_ln34"/></StgValue>
</operation>

<operation id="1304" st_id="120" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln32_9" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="1047" bw="0" op_0_bw="0">
<![CDATA[
.split.9_ifconv:80 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="121" st_id="121">

<operation id="1305" st_id="121" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="1049" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
._crit_edge.loopexit.9:0 %add_ln29_27 = add i32 %zext_ln29_3, i32 %add_ln29_24

]]></Node>
<StgValue><ssdm name="add_ln29_27"/></StgValue>
</operation>

<operation id="1306" st_id="121" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="1050" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
._crit_edge.loopexit.9:1 %add_ln29_28 = add i64 %i_0, i64 20

]]></Node>
<StgValue><ssdm name="add_ln29_28"/></StgValue>
</operation>

<operation id="1307" st_id="121" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="1051" bw="0" op_0_bw="0">
<![CDATA[
._crit_edge.loopexit.9:2 %br_ln0 = br void

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>
</state>

<state id="122" st_id="122">

<operation id="1308" st_id="122" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="1053" bw="0">
<![CDATA[
._crit_edge10:0 %ret_ln37 = ret

]]></Node>
<StgValue><ssdm name="ret_ln37"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
