<stg><name>nfa_accept_sample</name>


<trans_list>

<trans id="189" from="1" to="2">
<condition id="87">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="190" from="2" to="3">
<condition id="88">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="191" from="3" to="4">
<condition id="89">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="192" from="4" to="5">
<condition id="90">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="193" from="5" to="6">
<condition id="91">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="194" from="6" to="7">
<condition id="92">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="195" from="7" to="8">
<condition id="93">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="196" from="8" to="9">
<condition id="94">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="197" from="9" to="10">
<condition id="95">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="198" from="10" to="11">
<condition id="96">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="199" from="11" to="12">
<condition id="97">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="200" from="12" to="13">
<condition id="98">
<or_exp><and_exp><literal name="tmp_s" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="201" from="12" to="39">
<condition id="99">
<or_exp><and_exp><literal name="tmp_s" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="203" from="13" to="14">
<condition id="101">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="204" from="14" to="15">
<condition id="102">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="205" from="15" to="16">
<condition id="103">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="206" from="16" to="17">
<condition id="104">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="207" from="17" to="18">
<condition id="105">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="208" from="18" to="19">
<condition id="106">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="209" from="19" to="20">
<condition id="107">
<or_exp><and_exp><literal name="tmp_2_i" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="210" from="19" to="21">
<condition id="108">
<or_exp><and_exp><literal name="tmp_2_i" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="212" from="20" to="21">
<condition id="111">
<or_exp><and_exp><literal name="tmp_2_1_i" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="213" from="20" to="24">
<condition id="110">
<or_exp><and_exp><literal name="tmp_2_1_i" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="214" from="21" to="22">
<condition id="112">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="215" from="22" to="23">
<condition id="113">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="216" from="23" to="24">
<condition id="114">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="217" from="24" to="25">
<condition id="115">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="218" from="25" to="26">
<condition id="116">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="233" from="25" to="45">
<condition id="132">
<or_exp><and_exp><literal name="j_end" val="1"/>
<literal name="any" val="0"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="234" from="25" to="5">
<condition id="134">
<or_exp><and_exp><literal name="j_end" val="1"/>
<literal name="any" val="1"/>
</and_exp></or_exp>
</condition>
</trans>

<trans id="220" from="26" to="27">
<condition id="118">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="221" from="27" to="28">
<condition id="119">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="222" from="28" to="29">
<condition id="120">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="223" from="29" to="30">
<condition id="121">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="224" from="30" to="31">
<condition id="122">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="225" from="31" to="32">
<condition id="123">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="226" from="32" to="33">
<condition id="124">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="227" from="33" to="34">
<condition id="125">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="228" from="34" to="35">
<condition id="126">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="229" from="35" to="36">
<condition id="127">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="230" from="36" to="37">
<condition id="128">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="231" from="37" to="38">
<condition id="129">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="232" from="38" to="25">
<condition id="131">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="236" from="39" to="40">
<condition id="136">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="237" from="40" to="41">
<condition id="137">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="238" from="41" to="42">
<condition id="138">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="239" from="42" to="43">
<condition id="139">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="240" from="43" to="44">
<condition id="140">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="241" from="44" to="45">
<condition id="141">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="46" st_id="1" stage="3" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="36">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:15  %call_ret2 = call fastcc { i32, i32 } @nfa_get_initials(i32* %nfa_initials_buckets)

]]></node>
<StgValue><ssdm name="call_ret2"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="47" st_id="2" stage="2" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="37">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:15  %call_ret2 = call fastcc { i32, i32 } @nfa_get_initials(i32* %nfa_initials_buckets)

]]></node>
<StgValue><ssdm name="call_ret2"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="48" st_id="3" stage="1" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:15  %call_ret2 = call fastcc { i32, i32 } @nfa_get_initials(i32* %nfa_initials_buckets)

]]></node>
<StgValue><ssdm name="call_ret2"/></StgValue>
</operation>

<operation id="49" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="32" op_0_bw="64">
<![CDATA[
:16  %current_buckets_0 = extractvalue { i32, i32 } %call_ret2, 0

]]></node>
<StgValue><ssdm name="current_buckets_0"/></StgValue>
</operation>

<operation id="50" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="38">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="25" bw="32" op_0_bw="64">
<![CDATA[
:17  %current_buckets_1 = extractvalue { i32, i32 } %call_ret2, 1

]]></node>
<StgValue><ssdm name="current_buckets_1"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="51" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="8" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:0  call void (...)* @_ssdm_op_SpecIFCore(i8* %sample, [1 x i8]* @p_str11, [7 x i8]* @p_str38, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="52" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_forward_buckets, [1 x i8]* @p_str11, [7 x i8]* @p_str38, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="53" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="10" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecBus(i8* %sample, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="54" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="11" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_forward_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="55" st_id="4" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="12" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:4  %length_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %length_r)

]]></node>
<StgValue><ssdm name="length_read"/></StgValue>
</operation>

<operation id="56" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="13" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:5  %tmp_3 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %empty)

]]></node>
<StgValue><ssdm name="tmp_3"/></StgValue>
</operation>

<operation id="57" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="14" bw="8" op_0_bw="8" op_1_bw="32">
<![CDATA[
:6  %sample_addr = getelementptr i8* %sample, i32 %tmp_3

]]></node>
<StgValue><ssdm name="sample_addr"/></StgValue>
</operation>

<operation id="58" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="15" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:7  call void (...)* @_ssdm_op_SpecIFCore(i8* %nfa_symbols, [1 x i8]* @p_str11, [7 x i8]* @p_str39, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="59" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="16" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:8  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_finals_buckets, [1 x i8]* @p_str11, [7 x i8]* @p_str38, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="60" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="17" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:9  call void (...)* @_ssdm_op_SpecIFCore(i32* %nfa_initials_buckets, [1 x i8]* @p_str11, [7 x i8]* @p_str38, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="61" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="18" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:10  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_finals_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="62" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="19" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:11  call void (...)* @_ssdm_op_SpecBus(i32* %nfa_initials_buckets, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str11)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="63" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:12  call void (...)* @_ssdm_op_SpecIFCore(i16 %length_r, [1 x i8]* @p_str11, [7 x i8]* @p_str39, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="64" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="21" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:13  call void (...)* @_ssdm_op_SpecBus(i8* %sample_addr, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str11) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="65" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="22" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
:14  call void (...)* @_ssdm_op_SpecPipeline(i32 1, i32 1, i32 1, [1 x i8]* @p_str11) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="66" st_id="4" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="39">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="26" bw="0" op_0_bw="0">
<![CDATA[
:18  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="67" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="30" bw="16" op_0_bw="16" op_1_bw="0">
<![CDATA[
:2  %i = phi i16 [ 0, %0 ], [ %i_1, %6 ]

]]></node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="68" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="31" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
:3  %p_01_rec = phi i32 [ 0, %0 ], [ %p_rec, %6 ]

]]></node>
<StgValue><ssdm name="p_01_rec"/></StgValue>
</operation>

<operation id="69" st_id="5" stage="8" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>

<operation id="70" st_id="5" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="34" bw="1" op_0_bw="16" op_1_bw="16">
<![CDATA[
:6  %tmp_s = icmp ult i16 %i, %length_read

]]></node>
<StgValue><ssdm name="tmp_s"/></StgValue>
</operation>

<operation id="71" st_id="5" stage="4" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="40">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  %i_1 = add i16 %i, 1

]]></node>
<StgValue><ssdm name="i_1"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="72" st_id="6" stage="7" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="41">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>

<operation id="73" st_id="6" stage="3" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="41">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  %i_1 = add i16 %i, 1

]]></node>
<StgValue><ssdm name="i_1"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="74" st_id="7" stage="6" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="42">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>

<operation id="75" st_id="7" stage="2" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="42">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  %i_1 = add i16 %i, 1

]]></node>
<StgValue><ssdm name="i_1"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="76" st_id="8" stage="5" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="43">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>

<operation id="77" st_id="8" stage="1" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="43">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="35" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:7  %i_1 = add i16 %i, 1

]]></node>
<StgValue><ssdm name="i_1"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="78" st_id="9" stage="4" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="44">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="79" st_id="10" stage="3" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="45">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="80" st_id="11" stage="2" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="46">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="81" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="28" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
:0  %next_buckets_1 = phi i32 [ %current_buckets_1, %0 ], [ %tmp_buckets_1_3, %6 ]

]]></node>
<StgValue><ssdm name="next_buckets_1"/></StgValue>
</operation>

<operation id="82" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
:1  %next_buckets_0 = phi i32 [ %current_buckets_0, %0 ], [ %tmp_buckets_0_3, %6 ]

]]></node>
<StgValue><ssdm name="next_buckets_0"/></StgValue>
</operation>

<operation id="83" st_id="12" stage="1" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="32" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %sum = add i32 %p_01_rec, %tmp_3

]]></node>
<StgValue><ssdm name="sum"/></StgValue>
</operation>

<operation id="84" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="33" bw="8" op_0_bw="8" op_1_bw="32">
<![CDATA[
:5  %sample_addr_1 = getelementptr i8* %sample, i32 %sum

]]></node>
<StgValue><ssdm name="sample_addr_1"/></StgValue>
</operation>

<operation id="85" st_id="12" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="47">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="36" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:8  br i1 %tmp_s, label %2, label %7

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="86" st_id="12" stage="8" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="48">
<or_exp><and_exp><literal name="tmp_s" val="1"/>
</and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>

<operation id="87" st_id="12" stage="3" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="49">
<or_exp><and_exp><literal name="tmp_s" val="0"/>
</and_exp></or_exp>
</condition>

<node id="111" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:0  %call_ret4 = call fastcc { i32, i32 } @nfa_get_finals(i32* %nfa_finals_buckets)

]]></node>
<StgValue><ssdm name="call_ret4"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="88" st_id="13" stage="7" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="50">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="89" st_id="14" stage="6" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="51">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>
</state>

<state id="15" st_id="15">

<operation id="90" st_id="15" stage="5" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="52">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>
</state>

<state id="16" st_id="16">

<operation id="91" st_id="16" stage="4" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="53">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>
</state>

<state id="17" st_id="17">

<operation id="92" st_id="17" stage="3" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="54">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>
</state>

<state id="18" st_id="18">

<operation id="93" st_id="18" stage="2" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="55">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>

<operation id="94" st_id="18" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="55">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="41" bw="1" op_0_bw="1" op_1_bw="8" op_2_bw="32">
<![CDATA[
:3  %sym_req = call i1 @_ssdm_op_ReadReq.ap_bus.i8P(i8* %sample_addr_1, i32 1)

]]></node>
<StgValue><ssdm name="sym_req"/></StgValue>
</operation>

<operation id="95" st_id="18" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="55">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="43" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:5  %tmp_2_i = icmp eq i32 %next_buckets_0, 0

]]></node>
<StgValue><ssdm name="tmp_2_i"/></StgValue>
</operation>
</state>

<state id="19" st_id="19">

<operation id="96" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="38" bw="32" op_0_bw="32" op_1_bw="8">
<![CDATA[
:0  %tmp = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str12)

]]></node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="97" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="39" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 1024, i32 512, [1 x i8]* @p_str11) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="98" st_id="19" stage="1" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="40" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:2  %p_rec = add i32 %p_01_rec, 1

]]></node>
<StgValue><ssdm name="p_rec"/></StgValue>
</operation>

<operation id="99" st_id="19" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="42" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
:4  %sym = call i8 @_ssdm_op_Read.ap_bus.i8P(i8* %sample_addr_1)

]]></node>
<StgValue><ssdm name="sym"/></StgValue>
</operation>

<operation id="100" st_id="19" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="56">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="44" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:6  br i1 %tmp_2_i, label %4, label %3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="101" st_id="19" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="57">
<or_exp><and_exp><literal name="tmp_2_i" val="1"/>
</and_exp></or_exp>
</condition>

<node id="46" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:0  %tmp_2_1_i = icmp eq i32 %next_buckets_1, 0

]]></node>
<StgValue><ssdm name="tmp_2_1_i"/></StgValue>
</operation>
</state>

<state id="20" st_id="20">

<operation id="102" st_id="20" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="58">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="47" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:1  br i1 %tmp_2_1_i, label %bitset_first.exit.preheader, label %3

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="21" st_id="21">

<operation id="103" st_id="21" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="59">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="49" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
:0  %bus_assign = phi i32 [ %next_buckets_0, %2 ], [ %next_buckets_1, %4 ]

]]></node>
<StgValue><ssdm name="bus_assign"/></StgValue>
</operation>

<operation id="104" st_id="21" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="59">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="52" bw="5" op_0_bw="5" op_1_bw="32">
<![CDATA[
:3  %r_bit = call fastcc zeroext i5 @_bsf32_hw(i32 %bus_assign) nounwind

]]></node>
<StgValue><ssdm name="r_bit"/></StgValue>
</operation>
</state>

<state id="22" st_id="22">

<operation id="105" st_id="22" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="60">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="52" bw="5" op_0_bw="5" op_1_bw="32">
<![CDATA[
:3  %r_bit = call fastcc zeroext i5 @_bsf32_hw(i32 %bus_assign) nounwind

]]></node>
<StgValue><ssdm name="r_bit"/></StgValue>
</operation>
</state>

<state id="23" st_id="23">

<operation id="106" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="61">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="50" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
:1  %agg_result_bucket_index_0_lcssa4_i = phi i1 [ false, %2 ], [ true, %4 ]

]]></node>
<StgValue><ssdm name="agg_result_bucket_index_0_lcssa4_i"/></StgValue>
</operation>

<operation id="107" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="61">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="51" bw="2" op_0_bw="1">
<![CDATA[
:2  %agg_result_bucket_index_0_lcssa4_i_cast_cast = zext i1 %agg_result_bucket_index_0_lcssa4_i to i2

]]></node>
<StgValue><ssdm name="agg_result_bucket_index_0_lcssa4_i_cast_cast"/></StgValue>
</operation>

<operation id="108" st_id="23" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="61">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="53" bw="0" op_0_bw="0">
<![CDATA[
:4  br label %bitset_first.exit.preheader

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="24" st_id="24">

<operation id="109" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="55" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
bitset_first.exit.preheader:0  %j_bucket1_ph = phi i32 [ 0, %4 ], [ %bus_assign, %3 ]

]]></node>
<StgValue><ssdm name="j_bucket1_ph"/></StgValue>
</operation>

<operation id="110" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="56" bw="2" op_0_bw="2" op_1_bw="0">
<![CDATA[
bitset_first.exit.preheader:1  %j_bucket_index1_ph = phi i2 [ -2, %4 ], [ %agg_result_bucket_index_0_lcssa4_i_cast_cast, %3 ]

]]></node>
<StgValue><ssdm name="j_bucket_index1_ph"/></StgValue>
</operation>

<operation id="111" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="57" bw="5" op_0_bw="5" op_1_bw="0">
<![CDATA[
bitset_first.exit.preheader:2  %j_bit1_ph = phi i5 [ undef, %4 ], [ %r_bit, %3 ]

]]></node>
<StgValue><ssdm name="j_bit1_ph"/></StgValue>
</operation>

<operation id="112" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="58" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
bitset_first.exit.preheader:3  %j_end_ph = phi i1 [ true, %4 ], [ false, %3 ]

]]></node>
<StgValue><ssdm name="j_end_ph"/></StgValue>
</operation>

<operation id="113" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="59" bw="8" op_0_bw="2">
<![CDATA[
bitset_first.exit.preheader:4  %j_bucket_index1_ph_cast = zext i2 %j_bucket_index1_ph to i8

]]></node>
<StgValue><ssdm name="j_bucket_index1_ph_cast"/></StgValue>
</operation>

<operation id="114" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="60" bw="8" op_0_bw="5">
<![CDATA[
bitset_first.exit.preheader:5  %j_bit1_ph_cast = zext i5 %j_bit1_ph to i8

]]></node>
<StgValue><ssdm name="j_bit1_ph_cast"/></StgValue>
</operation>

<operation id="115" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="61" bw="14" op_0_bw="8">
<![CDATA[
bitset_first.exit.preheader:6  %tmp_18_i_cast = zext i8 %sym to i14

]]></node>
<StgValue><ssdm name="tmp_18_i_cast"/></StgValue>
</operation>

<operation id="116" st_id="24" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="62">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="62" bw="0" op_0_bw="0">
<![CDATA[
bitset_first.exit.preheader:7  br label %bitset_first.exit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="25" st_id="25">

<operation id="117" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="64" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
bitset_first.exit:0  %tmp_buckets_1_3 = phi i32 [ %next_buckets_1_1, %bitset_element.exit ], [ 0, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="tmp_buckets_1_3"/></StgValue>
</operation>

<operation id="118" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="65" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
bitset_first.exit:1  %tmp_buckets_0_3 = phi i32 [ %next_buckets_0_1, %bitset_element.exit ], [ 0, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="tmp_buckets_0_3"/></StgValue>
</operation>

<operation id="119" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="66" bw="32" op_0_bw="32" op_1_bw="0">
<![CDATA[
bitset_first.exit:2  %j_bucket1 = phi i32 [ %j_bucket, %bitset_element.exit ], [ %j_bucket1_ph, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="j_bucket1"/></StgValue>
</operation>

<operation id="120" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="67" bw="8" op_0_bw="8" op_1_bw="0">
<![CDATA[
bitset_first.exit:3  %j_bucket_index1 = phi i8 [ %j_bucket_index, %bitset_element.exit ], [ %j_bucket_index1_ph_cast, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="j_bucket_index1"/></StgValue>
</operation>

<operation id="121" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="68" bw="8" op_0_bw="8" op_1_bw="0">
<![CDATA[
bitset_first.exit:4  %j_bit1 = phi i8 [ %j_bit, %bitset_element.exit ], [ %j_bit1_ph_cast, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="j_bit1"/></StgValue>
</operation>

<operation id="122" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="69" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
bitset_first.exit:5  %j_end = phi i1 [ %p_s, %bitset_element.exit ], [ %j_end_ph, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="j_end"/></StgValue>
</operation>

<operation id="123" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="70" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
bitset_first.exit:6  %any = phi i1 [ true, %bitset_element.exit ], [ false, %bitset_first.exit.preheader ]

]]></node>
<StgValue><ssdm name="any"/></StgValue>
</operation>

<operation id="124" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="63">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="71" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
bitset_first.exit:7  br i1 %j_end, label %5, label %bitset_element.exit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="125" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="64">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>

<node id="75" bw="1" op_0_bw="8">
<![CDATA[
bitset_element.exit:2  %tmp_5 = trunc i8 %j_bucket_index1 to i1

]]></node>
<StgValue><ssdm name="tmp_5"/></StgValue>
</operation>

<operation id="126" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="64">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>

<node id="76" bw="6" op_0_bw="6" op_1_bw="1" op_2_bw="5">
<![CDATA[
bitset_element.exit:3  %tmp_i = call i6 @_ssdm_op_BitConcatenate.i6.i1.i5(i1 %tmp_5, i5 0)

]]></node>
<StgValue><ssdm name="tmp_i"/></StgValue>
</operation>

<operation id="127" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="64">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>

<node id="77" bw="6" op_0_bw="8">
<![CDATA[
bitset_element.exit:4  %tmp_6 = trunc i8 %j_bit1 to i6

]]></node>
<StgValue><ssdm name="tmp_6"/></StgValue>
</operation>

<operation id="128" st_id="25" stage="2" lat="2">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="64">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>

<node id="78" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
bitset_element.exit:5  %state = add i6 %tmp_i, %tmp_6

]]></node>
<StgValue><ssdm name="state"/></StgValue>
</operation>

<operation id="129" st_id="25" stage="12" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="64">
<or_exp><and_exp><literal name="j_end" val="0"/>
</and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>

<operation id="130" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="65">
<or_exp><and_exp><literal name="j_end" val="1"/>
</and_exp></or_exp>
</condition>

<node id="106" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
:0  br i1 %any, label %6, label %.loopexit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="131" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="66">
<or_exp><and_exp><literal name="j_end" val="1"/>
<literal name="any" val="1"/>
</and_exp></or_exp>
</condition>

<node id="108" bw="32" op_0_bw="32" op_1_bw="8" op_2_bw="32">
<![CDATA[
:0  %empty_13 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str12, i32 %tmp)

]]></node>
<StgValue><ssdm name="empty_13"/></StgValue>
</operation>

<operation id="132" st_id="25" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="66">
<or_exp><and_exp><literal name="j_end" val="1"/>
<literal name="any" val="1"/>
</and_exp></or_exp>
</condition>

<node id="109" bw="0" op_0_bw="0">
<![CDATA[
:1  br label %1

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="26" st_id="26">

<operation id="133" st_id="26" stage="1" lat="2">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="67">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="78" bw="6" op_0_bw="6" op_1_bw="6">
<![CDATA[
bitset_element.exit:5  %state = add i6 %tmp_i, %tmp_6

]]></node>
<StgValue><ssdm name="state"/></StgValue>
</operation>

<operation id="134" st_id="26" stage="11" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="67">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="27" st_id="27">

<operation id="135" st_id="27" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="81" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
bitset_element.exit:8  %nfa_symbols_read = call i8 @_ssdm_op_Read.ap_auto.i8P(i8* %nfa_symbols)

]]></node>
<StgValue><ssdm name="nfa_symbols_read"/></StgValue>
</operation>

<operation id="136" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="82" bw="14" op_0_bw="6">
<![CDATA[
bitset_element.exit:9  %tmp_15_i_cast = zext i6 %state to i14

]]></node>
<StgValue><ssdm name="tmp_15_i_cast"/></StgValue>
</operation>

<operation id="137" st_id="27" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="83" bw="14" op_0_bw="8">
<![CDATA[
bitset_element.exit:10  %tmp_16_i_cast = zext i8 %nfa_symbols_read to i14

]]></node>
<StgValue><ssdm name="tmp_16_i_cast"/></StgValue>
</operation>

<operation id="138" st_id="27" stage="4" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:11  %tmp_17_i = mul i14 %tmp_16_i_cast, %tmp_15_i_cast

]]></node>
<StgValue><ssdm name="tmp_17_i"/></StgValue>
</operation>

<operation id="139" st_id="27" stage="10" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="68">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="28" st_id="28">

<operation id="140" st_id="28" stage="3" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="69">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:11  %tmp_17_i = mul i14 %tmp_16_i_cast, %tmp_15_i_cast

]]></node>
<StgValue><ssdm name="tmp_17_i"/></StgValue>
</operation>

<operation id="141" st_id="28" stage="9" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="69">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="29" st_id="29">

<operation id="142" st_id="29" stage="2" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="70">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:11  %tmp_17_i = mul i14 %tmp_16_i_cast, %tmp_15_i_cast

]]></node>
<StgValue><ssdm name="tmp_17_i"/></StgValue>
</operation>

<operation id="143" st_id="29" stage="8" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="70">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="30" st_id="30">

<operation id="144" st_id="30" stage="1" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="71">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="84" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:11  %tmp_17_i = mul i14 %tmp_16_i_cast, %tmp_15_i_cast

]]></node>
<StgValue><ssdm name="tmp_17_i"/></StgValue>
</operation>

<operation id="145" st_id="30" stage="7" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="71">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="31" st_id="31">

<operation id="146" st_id="31" stage="4" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="72">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="85" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:12  %offset_i = add i14 %tmp_17_i, %tmp_18_i_cast

]]></node>
<StgValue><ssdm name="offset_i"/></StgValue>
</operation>

<operation id="147" st_id="31" stage="6" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="72">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="32" st_id="32">

<operation id="148" st_id="32" stage="3" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="73">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="85" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:12  %offset_i = add i14 %tmp_17_i, %tmp_18_i_cast

]]></node>
<StgValue><ssdm name="offset_i"/></StgValue>
</operation>

<operation id="149" st_id="32" stage="5" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="73">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="33" st_id="33">

<operation id="150" st_id="33" stage="2" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="74">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="85" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:12  %offset_i = add i14 %tmp_17_i, %tmp_18_i_cast

]]></node>
<StgValue><ssdm name="offset_i"/></StgValue>
</operation>

<operation id="151" st_id="33" stage="4" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="74">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="34" st_id="34">

<operation id="152" st_id="34" stage="1" lat="4">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="75">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="85" bw="14" op_0_bw="14" op_1_bw="14">
<![CDATA[
bitset_element.exit:12  %offset_i = add i14 %tmp_17_i, %tmp_18_i_cast

]]></node>
<StgValue><ssdm name="offset_i"/></StgValue>
</operation>

<operation id="153" st_id="34" stage="3" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="75">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="35" st_id="35">

<operation id="154" st_id="35" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="86" bw="15" op_0_bw="15" op_1_bw="14" op_2_bw="1">
<![CDATA[
bitset_element.exit:13  %tmp_5_i = call i15 @_ssdm_op_BitConcatenate.i15.i14.i1(i14 %offset_i, i1 false)

]]></node>
<StgValue><ssdm name="tmp_5_i"/></StgValue>
</operation>

<operation id="155" st_id="35" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="87" bw="32" op_0_bw="15">
<![CDATA[
bitset_element.exit:14  %tmp_5_i_cast = zext i15 %tmp_5_i to i32

]]></node>
<StgValue><ssdm name="tmp_5_i_cast"/></StgValue>
</operation>

<operation id="156" st_id="35" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="88" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:15  %nfa_forward_buckets_addr = getelementptr i32* %nfa_forward_buckets, i32 %tmp_5_i_cast

]]></node>
<StgValue><ssdm name="nfa_forward_buckets_addr"/></StgValue>
</operation>

<operation id="157" st_id="35" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="89" bw="1" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
bitset_element.exit:16  %tmp_buckets_0_2_req = call i1 @_ssdm_op_ReadReq.ap_bus.i32P(i32* %nfa_forward_buckets_addr, i32 1)

]]></node>
<StgValue><ssdm name="tmp_buckets_0_2_req"/></StgValue>
</operation>

<operation id="158" st_id="35" stage="2" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="76">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>
</state>

<state id="36" st_id="36">

<operation id="159" st_id="36" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="90" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:17  %tmp_buckets_0_1 = call i32 @_ssdm_op_Read.ap_bus.i32P(i32* %nfa_forward_buckets_addr)

]]></node>
<StgValue><ssdm name="tmp_buckets_0_1"/></StgValue>
</operation>

<operation id="160" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="91" bw="15" op_0_bw="15" op_1_bw="14" op_2_bw="1">
<![CDATA[
bitset_element.exit:18  %tmp_6_i = call i15 @_ssdm_op_BitConcatenate.i15.i14.i1(i14 %offset_i, i1 true)

]]></node>
<StgValue><ssdm name="tmp_6_i"/></StgValue>
</operation>

<operation id="161" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="92" bw="32" op_0_bw="15">
<![CDATA[
bitset_element.exit:19  %tmp_6_i_cast = zext i15 %tmp_6_i to i32

]]></node>
<StgValue><ssdm name="tmp_6_i_cast"/></StgValue>
</operation>

<operation id="162" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="93" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:20  %nfa_forward_buckets_addr_1 = getelementptr i32* %nfa_forward_buckets, i32 %tmp_6_i_cast

]]></node>
<StgValue><ssdm name="nfa_forward_buckets_addr_1"/></StgValue>
</operation>

<operation id="163" st_id="36" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="94" bw="1" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
bitset_element.exit:21  %tmp_buckets_1_2_req = call i1 @_ssdm_op_ReadReq.ap_bus.i32P(i32* %nfa_forward_buckets_addr_1, i32 1)

]]></node>
<StgValue><ssdm name="tmp_buckets_1_2_req"/></StgValue>
</operation>

<operation id="164" st_id="36" stage="1" lat="12">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="99" bw="49" op_0_bw="49" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32">
<![CDATA[
bitset_element.exit:26  %call_ret8 = call fastcc { i8, i8, i32, i1 } @bitset_next(i32 %next_buckets_1, i8 %j_bit1, i8 %j_bucket_index1, i32 %j_bucket1)

]]></node>
<StgValue><ssdm name="call_ret8"/></StgValue>
</operation>

<operation id="165" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="100" bw="8" op_0_bw="49">
<![CDATA[
bitset_element.exit:27  %j_bit = extractvalue { i8, i8, i32, i1 } %call_ret8, 0

]]></node>
<StgValue><ssdm name="j_bit"/></StgValue>
</operation>

<operation id="166" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="101" bw="8" op_0_bw="49">
<![CDATA[
bitset_element.exit:28  %j_bucket_index = extractvalue { i8, i8, i32, i1 } %call_ret8, 1

]]></node>
<StgValue><ssdm name="j_bucket_index"/></StgValue>
</operation>

<operation id="167" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="102" bw="32" op_0_bw="49">
<![CDATA[
bitset_element.exit:29  %j_bucket = extractvalue { i8, i8, i32, i1 } %call_ret8, 2

]]></node>
<StgValue><ssdm name="j_bucket"/></StgValue>
</operation>

<operation id="168" st_id="36" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="77">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="103" bw="1" op_0_bw="49">
<![CDATA[
bitset_element.exit:30  %p_s = extractvalue { i8, i8, i32, i1 } %call_ret8, 3

]]></node>
<StgValue><ssdm name="p_s"/></StgValue>
</operation>
</state>

<state id="37" st_id="37">

<operation id="169" st_id="37" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="78">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="95" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:22  %tmp_buckets_1_1 = call i32 @_ssdm_op_Read.ap_bus.i32P(i32* %nfa_forward_buckets_addr_1)

]]></node>
<StgValue><ssdm name="tmp_buckets_1_1"/></StgValue>
</operation>

<operation id="170" st_id="37" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="78">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="96" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:23  %next_buckets_0_1 = or i32 %tmp_buckets_0_3, %tmp_buckets_0_1

]]></node>
<StgValue><ssdm name="next_buckets_0_1"/></StgValue>
</operation>
</state>

<state id="38" st_id="38">

<operation id="171" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="73" bw="32" op_0_bw="32" op_1_bw="8">
<![CDATA[
bitset_element.exit:0  %tmp_4 = call i32 (...)* @_ssdm_op_SpecRegionBegin([12 x i8]* @p_str13)

]]></node>
<StgValue><ssdm name="tmp_4"/></StgValue>
</operation>

<operation id="172" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="74" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="8">
<![CDATA[
bitset_element.exit:1  call void (...)* @_ssdm_op_SpecLoopTripCount(i32 0, i32 64, i32 5, [1 x i8]* @p_str11) nounwind

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="173" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="79" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
bitset_element.exit:6  call void (...)* @_ssdm_op_SpecIFCore(i8* %nfa_symbols, [1 x i8]* @p_str11, [7 x i8]* @p_str39, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="174" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="80" bw="0" op_0_bw="0" op_1_bw="8" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
bitset_element.exit:7  call void (...)* @_ssdm_op_SpecIFCore(i8* %nfa_symbols, [1 x i8]* @p_str11, [7 x i8]* @p_str39, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [1 x i8]* @p_str11, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="175" st_id="38" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="97" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
bitset_element.exit:24  %next_buckets_1_1 = or i32 %tmp_buckets_1_3, %tmp_buckets_1_1

]]></node>
<StgValue><ssdm name="next_buckets_1_1"/></StgValue>
</operation>

<operation id="176" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="98" bw="32" op_0_bw="32" op_1_bw="8" op_2_bw="32">
<![CDATA[
bitset_element.exit:25  %empty_12 = call i32 (...)* @_ssdm_op_SpecRegionEnd([12 x i8]* @p_str13, i32 %tmp_4)

]]></node>
<StgValue><ssdm name="empty_12"/></StgValue>
</operation>

<operation id="177" st_id="38" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="79">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="104" bw="0" op_0_bw="0">
<![CDATA[
bitset_element.exit:31  br label %bitset_first.exit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="39" st_id="39">

<operation id="178" st_id="39" stage="2" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="80">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="111" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:0  %call_ret4 = call fastcc { i32, i32 } @nfa_get_finals(i32* %nfa_finals_buckets)

]]></node>
<StgValue><ssdm name="call_ret4"/></StgValue>
</operation>
</state>

<state id="40" st_id="40">

<operation id="179" st_id="40" stage="1" lat="3">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="81">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="111" bw="64" op_0_bw="64" op_1_bw="32">
<![CDATA[
:0  %call_ret4 = call fastcc { i32, i32 } @nfa_get_finals(i32* %nfa_finals_buckets)

]]></node>
<StgValue><ssdm name="call_ret4"/></StgValue>
</operation>

<operation id="180" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="81">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="112" bw="32" op_0_bw="64">
<![CDATA[
:1  %tmp_buckets_0 = extractvalue { i32, i32 } %call_ret4, 0

]]></node>
<StgValue><ssdm name="tmp_buckets_0"/></StgValue>
</operation>

<operation id="181" st_id="40" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="81">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="113" bw="32" op_0_bw="64">
<![CDATA[
:2  %tmp_buckets_1 = extractvalue { i32, i32 } %call_ret4, 1

]]></node>
<StgValue><ssdm name="tmp_buckets_1"/></StgValue>
</operation>
</state>

<state id="41" st_id="41">

<operation id="182" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="82">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="114" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:3  %current_buckets_0_1 = and i32 %next_buckets_0, %tmp_buckets_0

]]></node>
<StgValue><ssdm name="current_buckets_0_1"/></StgValue>
</operation>

<operation id="183" st_id="41" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="82">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="115" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:4  %current_buckets_1_1 = and i32 %next_buckets_1, %tmp_buckets_1

]]></node>
<StgValue><ssdm name="current_buckets_1_1"/></StgValue>
</operation>
</state>

<state id="42" st_id="42">

<operation id="184" st_id="42" stage="1" lat="1">
<core>LogicGate</core>
<MemPortIdVec></MemPortIdVec>
<condition id="83">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="116" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:5  %tmp_1 = or i32 %current_buckets_1_1, %current_buckets_0_1

]]></node>
<StgValue><ssdm name="tmp_1"/></StgValue>
</operation>
</state>

<state id="43" st_id="43">

<operation id="185" st_id="43" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="84">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="117" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
:6  %tmp_2 = icmp ne i32 %tmp_1, 0

]]></node>
<StgValue><ssdm name="tmp_2"/></StgValue>
</operation>
</state>

<state id="44" st_id="44">

<operation id="186" st_id="44" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="85">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="118" bw="0" op_0_bw="0">
<![CDATA[
:7  br label %.loopexit

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>

<state id="45" st_id="45">

<operation id="187" st_id="45" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="86">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="120" bw="1" op_0_bw="1" op_1_bw="0">
<![CDATA[
.loopexit:0  %p_0 = phi i1 [ %tmp_2, %7 ], [ false, %5 ]

]]></node>
<StgValue><ssdm name="p_0"/></StgValue>
</operation>

<operation id="188" st_id="45" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="86">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="121" bw="0" op_0_bw="1">
<![CDATA[
.loopexit:1  ret i1 %p_0

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
