<stg><name>vmul2</name>


<trans_list>

<trans id="54" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="55" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="56" from="3" to="4">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="57" from="4" to="5">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="58" from="5" to="6">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="59" from="6" to="7">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="8" st_id="1" stage="1" lat="1">
<core>s_axilite</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
entry:0 %size_read = read i32 @_ssdm_op_Read.ap_none.i32, i32 %size

]]></Node>
<StgValue><ssdm name="size_read"/></StgValue>
</operation>

<operation id="9" st_id="1" stage="1" lat="1">
<core>s_axilite</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:1 %out_r_read = read i64 @_ssdm_op_Read.s_axilite.i64, i64 %out_r

]]></Node>
<StgValue><ssdm name="out_r_read"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>s_axilite</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:2 %in2_read = read i64 @_ssdm_op_Read.s_axilite.i64, i64 %in2

]]></Node>
<StgValue><ssdm name="in2_read"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>s_axilite</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="13" bw="64" op_0_bw="64" op_1_bw="64">
<![CDATA[
entry:3 %in1_read = read i64 @_ssdm_op_Read.s_axilite.i64, i64 %in1

]]></Node>
<StgValue><ssdm name="in1_read"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="32" op_0_bw="64">
<![CDATA[
entry:4 %size_c11 = alloca i64 1

]]></Node>
<StgValue><ssdm name="size_c11"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="32" op_0_bw="64">
<![CDATA[
entry:7 %size_c = alloca i64 1

]]></Node>
<StgValue><ssdm name="size_c"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="64" op_0_bw="64">
<![CDATA[
entry:10 %out_r_c = alloca i64 1

]]></Node>
<StgValue><ssdm name="out_r_c"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="46" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64">
<![CDATA[
entry:36 %call_ln100 = call void @entry_proc, i64 %out_r_read, i64 %out_r_c

]]></Node>
<StgValue><ssdm name="call_ln100"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="16" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32" op_5_bw="32">
<![CDATA[
entry:37 %call_ln102 = call void @load_input, i32 %gmem0, i64 %in1_read, i32 %size_read, i32 %size_c11, i32 %in1_stream

]]></Node>
<StgValue><ssdm name="call_ln102"/></StgValue>
</operation>

<operation id="17" st_id="2" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32">
<![CDATA[
entry:38 %call_ln103 = call void @load_input.1, i32 %gmem1, i64 %in2_read, i32 %size_read, i32 %in2_stream

]]></Node>
<StgValue><ssdm name="call_ln103"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="18" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="47" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32" op_5_bw="32">
<![CDATA[
entry:37 %call_ln102 = call void @load_input, i32 %gmem0, i64 %in1_read, i32 %size_read, i32 %size_c11, i32 %in1_stream

]]></Node>
<StgValue><ssdm name="call_ln102"/></StgValue>
</operation>

<operation id="19" st_id="3" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="48" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32">
<![CDATA[
entry:38 %call_ln103 = call void @load_input.1, i32 %gmem1, i64 %in2_read, i32 %size_read, i32 %in2_stream

]]></Node>
<StgValue><ssdm name="call_ln103"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="20" st_id="4" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
entry:39 %call_ln104 = call void @compute_add, i32 %size_c11, i32 %size_c, i32 %in1_stream, i32 %in2_stream, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln104"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="21" st_id="5" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="49" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="0" op_7_bw="0">
<![CDATA[
entry:39 %call_ln104 = call void @compute_add, i32 %size_c11, i32 %size_c, i32 %in1_stream, i32 %in2_stream, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln104"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="22" st_id="6" stage="2" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="0" op_7_bw="0">
<![CDATA[
entry:40 %call_ln105 = call void @store_result, i32 %gmem0, i64 %out_r_c, i32 %size_c, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln105"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="23" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
entry:5 %empty = specchannel i32 @_ssdm_op_SpecChannel, void @size_c11_str, i32 1, void @p_str, void @p_str, i32 2, i32 0, i32 %size_c11, i32 %size_c11

]]></Node>
<StgValue><ssdm name="empty"/></StgValue>
</operation>

<operation id="24" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:6 %specinterface_ln100 = specinterface void @_ssdm_op_SpecInterface, i32 %size_c11, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @p_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln100"/></StgValue>
</operation>

<operation id="25" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
entry:8 %empty_26 = specchannel i32 @_ssdm_op_SpecChannel, void @size_c_str, i32 1, void @p_str, void @p_str, i32 2, i32 0, i32 %size_c, i32 %size_c

]]></Node>
<StgValue><ssdm name="empty_26"/></StgValue>
</operation>

<operation id="26" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:9 %specinterface_ln100 = specinterface void @_ssdm_op_SpecInterface, i32 %size_c, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @p_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln100"/></StgValue>
</operation>

<operation id="27" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="21" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="64" op_8_bw="64">
<![CDATA[
entry:11 %empty_27 = specchannel i32 @_ssdm_op_SpecChannel, void @out_r_c_str, i32 1, void @p_str, void @p_str, i32 4, i32 0, i64 %out_r_c, i64 %out_r_c

]]></Node>
<StgValue><ssdm name="empty_27"/></StgValue>
</operation>

<operation id="28" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:12 %specinterface_ln100 = specinterface void @_ssdm_op_SpecInterface, i64 %out_r_c, void @ap_fifo_str, i32 0, i32 0, void @p_str, i32 0, i32 0, void @p_str, void @p_str, void @p_str, i32 2, i32 2, i32 16, i32 16, void @p_str, void @p_str, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln100"/></StgValue>
</operation>

<operation id="29" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="0">
<![CDATA[
entry:13 %specdataflowpipeline_ln100 = specdataflowpipeline void @_ssdm_op_SpecDataflowPipeline, i32 4294967295, i32 0, void @empty_3

]]></Node>
<StgValue><ssdm name="specdataflowpipeline_ln100"/></StgValue>
</operation>

<operation id="30" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
entry:14 %empty_28 = specchannel i32 @_ssdm_op_SpecChannel, void @in1_stream_str, i32 1, void @p_str, void @p_str, i32 2, i32 2, i32 %in1_stream, i32 %in1_stream

]]></Node>
<StgValue><ssdm name="empty_28"/></StgValue>
</operation>

<operation id="31" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
entry:15 %empty_29 = specchannel i32 @_ssdm_op_SpecChannel, void @in2_stream_str, i32 1, void @p_str, void @p_str, i32 2, i32 2, i32 %in2_stream, i32 %in2_stream

]]></Node>
<StgValue><ssdm name="empty_29"/></StgValue>
</operation>

<operation id="32" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="26" bw="32" op_0_bw="32" op_1_bw="0" op_2_bw="32" op_3_bw="0" op_4_bw="0" op_5_bw="32" op_6_bw="32" op_7_bw="32" op_8_bw="32">
<![CDATA[
entry:16 %empty_30 = specchannel i32 @_ssdm_op_SpecChannel, void @out_stream_str, i32 1, void @p_str, void @p_str, i32 2, i32 2, i32 %out_stream, i32 %out_stream

]]></Node>
<StgValue><ssdm name="empty_30"/></StgValue>
</operation>

<operation id="33" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
entry:17 %spectopmodule_ln91 = spectopmodule void @_ssdm_op_SpecTopModule, void @empty_5

]]></Node>
<StgValue><ssdm name="spectopmodule_ln91"/></StgValue>
</operation>

<operation id="34" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="28" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:18 %specinterface_ln91 = specinterface void @_ssdm_op_SpecInterface, i32 0, void @empty_4, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln91"/></StgValue>
</operation>

<operation id="35" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="29" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:19 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %gmem0, void @empty_1, i32 0, i32 0, void @empty_3, i32 64, i32 0, void @empty_11, void @empty_10, void @empty_3, i32 16, i32 16, i32 16, i32 16, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="36" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="30" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
entry:20 %specbitsmap_ln0 = specbitsmap void @_ssdm_op_SpecBitsMap, i32 %gmem0

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="37" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="31" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:21 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %gmem1, void @empty_1, i32 0, i32 0, void @empty_3, i32 64, i32 0, void @empty_9, void @empty_10, void @empty_3, i32 16, i32 16, i32 16, i32 16, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="38" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="32" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
entry:22 %specbitsmap_ln0 = specbitsmap void @_ssdm_op_SpecBitsMap, i32 %gmem1

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="39" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="33" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:23 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %in1, void @empty_8, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_13, void @empty_14, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="40" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="34" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:24 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %in1, void @empty_15, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="41" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="35" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:25 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %in2, void @empty_8, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_13, void @empty_0, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="42" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="36" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:26 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %in2, void @empty_15, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="43" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="37" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:27 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %out_r, void @empty_8, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_13, void @empty, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="44" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="38" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:28 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i64 %out_r, void @empty_15, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_16, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="45" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="39" bw="0" op_0_bw="0" op_1_bw="32">
<![CDATA[
entry:29 %specbitsmap_ln0 = specbitsmap void @_ssdm_op_SpecBitsMap, i32 %size

]]></Node>
<StgValue><ssdm name="specbitsmap_ln0"/></StgValue>
</operation>

<operation id="46" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="40" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:30 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %size, void @empty_8, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_13, void @empty_2, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="47" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="41" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:31 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %size, void @empty_7, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="48" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="42" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:32 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 0, void @empty_8, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_13, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="49" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="43" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:33 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="50" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="44" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:34 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in2_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="51" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="45" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
entry:35 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %out_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="52" st_id="7" stage="1" lat="2">
<core></core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="50" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="64" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="0" op_7_bw="0">
<![CDATA[
entry:40 %call_ln105 = call void @store_result, i32 %gmem0, i64 %out_r_c, i32 %size_c, i32 %out_stream

]]></Node>
<StgValue><ssdm name="call_ln105"/></StgValue>
</operation>

<operation id="53" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="51" bw="0">
<![CDATA[
entry:41 %ret_ln106 = ret

]]></Node>
<StgValue><ssdm name="ret_ln106"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
