<stg><name>load_input_Pipeline_mem_rd</name>


<trans_list>

<trans id="36" from="1" to="2">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="39" from="2" to="3">
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="2">

<operation id="6" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="5" bw="31" op_0_bw="32">
<![CDATA[
newFuncRoot:0 %i = alloca i32 1

]]></Node>
<StgValue><ssdm name="i"/></StgValue>
</operation>

<operation id="7" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="6" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
newFuncRoot:1 %size_read = read i32 @_ssdm_op_Read.ap_auto.i32, i32 %size

]]></Node>
<StgValue><ssdm name="size_read"/></StgValue>
</operation>

<operation id="8" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="7" bw="62" op_0_bw="62" op_1_bw="62">
<![CDATA[
newFuncRoot:2 %sext_ln48_read = read i62 @_ssdm_op_Read.ap_auto.i62, i62 %sext_ln48

]]></Node>
<StgValue><ssdm name="sext_ln48_read"/></StgValue>
</operation>

<operation id="9" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="8" bw="64" op_0_bw="62">
<![CDATA[
newFuncRoot:3 %sext_ln48_cast = sext i62 %sext_ln48_read

]]></Node>
<StgValue><ssdm name="sext_ln48_cast"/></StgValue>
</operation>

<operation id="10" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="9" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
newFuncRoot:4 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %gmem0, void @empty_1, i32 0, i32 0, void @empty_3, i32 64, i32 0, void @empty_11, void @empty_10, void @empty_3, i32 16, i32 16, i32 16, i32 16, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="11" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="0" op_3_bw="32" op_4_bw="32" op_5_bw="0" op_6_bw="32" op_7_bw="32" op_8_bw="0" op_9_bw="0" op_10_bw="0" op_11_bw="32" op_12_bw="32" op_13_bw="32" op_14_bw="32" op_15_bw="0" op_16_bw="0" op_17_bw="32" op_18_bw="32">
<![CDATA[
newFuncRoot:5 %specinterface_ln0 = specinterface void @_ssdm_op_SpecInterface, i32 %in1_stream, void @empty_6, i32 0, i32 0, void @empty_3, i32 0, i32 0, void @empty_3, void @empty_3, void @empty_3, i32 0, i32 0, i32 0, i32 0, void @empty_3, void @empty_3, i32 4294967295, i32 0

]]></Node>
<StgValue><ssdm name="specinterface_ln0"/></StgValue>
</operation>

<operation id="12" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="11" bw="0" op_0_bw="31" op_1_bw="31">
<![CDATA[
newFuncRoot:6 %store_ln0 = store i31 0, i31 %i

]]></Node>
<StgValue><ssdm name="store_ln0"/></StgValue>
</operation>

<operation id="13" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="12" bw="0" op_0_bw="0">
<![CDATA[
newFuncRoot:7 %br_ln0 = br void %for.inc.i

]]></Node>
<StgValue><ssdm name="br_ln0"/></StgValue>
</operation>

<operation id="14" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="14" bw="31" op_0_bw="31" op_1_bw="0">
<![CDATA[
for.inc.i:0 %i_load = load i31 %i

]]></Node>
<StgValue><ssdm name="i_load"/></StgValue>
</operation>

<operation id="15" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="15" bw="32" op_0_bw="31">
<![CDATA[
for.inc.i:1 %zext_ln48 = zext i31 %i_load

]]></Node>
<StgValue><ssdm name="zext_ln48"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>Cmp</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="18" bw="1" op_0_bw="32" op_1_bw="32">
<![CDATA[
for.inc.i:4 %icmp_ln48 = icmp_slt  i32 %zext_ln48, i32 %size_read

]]></Node>
<StgValue><ssdm name="icmp_ln48"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>Adder</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="19" bw="31" op_0_bw="31" op_1_bw="31">
<![CDATA[
for.inc.i:5 %add_ln48 = add i31 %i_load, i31 1

]]></Node>
<StgValue><ssdm name="add_ln48"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="20" bw="0" op_0_bw="1" op_1_bw="0" op_2_bw="0">
<![CDATA[
for.inc.i:6 %br_ln48 = br i1 %icmp_ln48, void %load_input.exit.exitStub, void %new.body.for.inc.i

]]></Node>
<StgValue><ssdm name="br_ln48"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln48" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="26" bw="0" op_0_bw="31" op_1_bw="31" op_2_bw="0" op_3_bw="0">
<![CDATA[
new.body.for.inc.i:4 %store_ln48 = store i31 %add_ln48, i31 %i

]]></Node>
<StgValue><ssdm name="store_ln48"/></StgValue>
</operation>
</state>

<state id="2" st_id="3">

<operation id="20" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="16" bw="32" op_0_bw="32" op_1_bw="64">
<![CDATA[
for.inc.i:2 %gmem0_addr = getelementptr i32 %gmem0, i64 %sext_ln48_cast

]]></Node>
<StgValue><ssdm name="gmem0_addr"/></StgValue>
</operation>

<operation id="21" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="17" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32" op_3_bw="32" op_4_bw="32" op_5_bw="0">
<![CDATA[
for.inc.i:3 %specpipeline_ln0 = specpipeline void @_ssdm_op_SpecPipeline, i32 4294967295, i32 0, i32 1, i32 0, void @p_str

]]></Node>
<StgValue><ssdm name="specpipeline_ln0"/></StgValue>
</operation>

<operation id="22" st_id="2" stage="1" lat="1">
<core>m_axi</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln48" val="1"/>
</and_exp></or_exp>
</condition>

<Node id="24" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
new.body.for.inc.i:2 %gmem0_addr_read = read i32 @_ssdm_op_Read.m_axi.p1i32, i32 %gmem0_addr

]]></Node>
<StgValue><ssdm name="gmem0_addr_read"/></StgValue>
</operation>

<operation id="27" st_id="2" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp><literal name="icmp_ln48" val="0"/>
</and_exp></or_exp>
</condition>

<Node id="29" bw="0">
<![CDATA[
load_input.exit.exitStub:0 %ret_ln0 = ret

]]></Node>
<StgValue><ssdm name="ret_ln0"/></StgValue>
</operation>
</state>

<state id="3" st_id="4">

<operation id="23" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="22" bw="0" op_0_bw="0" op_1_bw="64" op_2_bw="64" op_3_bw="64">
<![CDATA[
new.body.for.inc.i:0 %speclooptripcount_ln49 = speclooptripcount void @_ssdm_op_SpecLoopTripCount, i64 4096, i64 4096, i64 4096

]]></Node>
<StgValue><ssdm name="speclooptripcount_ln49"/></StgValue>
</operation>

<operation id="24" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="23" bw="0" op_0_bw="0" op_1_bw="0">
<![CDATA[
new.body.for.inc.i:1 %specloopname_ln48 = specloopname void @_ssdm_op_SpecLoopName, void @empty_12

]]></Node>
<StgValue><ssdm name="specloopname_ln48"/></StgValue>
</operation>

<operation id="25" st_id="3" stage="1" lat="1">
<core>FIFO_SRL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="25" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="32">
<![CDATA[
new.body.for.inc.i:3 %write_ln50 = write void @_ssdm_op_Write.ap_fifo.volatile.i32P0A, i32 %in1_stream, i32 %gmem0_addr_read

]]></Node>
<StgValue><ssdm name="write_ln50"/></StgValue>
</operation>

<operation id="26" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<Node id="27" bw="0" op_0_bw="0">
<![CDATA[
new.body.for.inc.i:5 %br_ln48 = br void %for.inc.i

]]></Node>
<StgValue><ssdm name="br_ln48"/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
