<stg><name>sample_iterator_get_offset</name>


<trans_list>

<trans id="62" from="1" to="2">
<condition id="13">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="63" from="2" to="3">
<condition id="14">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="64" from="3" to="4">
<condition id="15">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="65" from="4" to="5">
<condition id="16">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="66" from="5" to="6">
<condition id="17">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="67" from="6" to="7">
<condition id="18">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="68" from="7" to="8">
<condition id="19">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="69" from="8" to="9">
<condition id="20">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="70" from="9" to="10">
<condition id="21">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="71" from="10" to="11">
<condition id="22">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="72" from="11" to="12">
<condition id="23">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="73" from="12" to="13">
<condition id="24">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>

<trans id="74" from="13" to="14">
<condition id="25">
<or_exp><and_exp></and_exp></or_exp>
</condition>
</trans>
</trans_list>



<state_list>

<state id="1" st_id="1">

<operation id="15" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="14" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:6  %sample_length8 = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %sample_length)

]]></node>
<StgValue><ssdm name="sample_length8"/></StgValue>
</operation>

<operation id="16" st_id="1" stage="1" lat="1">
<core>PLB46S</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="15" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:7  %sample_buffer_size7 = call i32 @_ssdm_op_Read.ap_auto.i32(i32 %sample_buffer_size)

]]></node>
<StgValue><ssdm name="sample_buffer_size7"/></StgValue>
</operation>

<operation id="17" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="16" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:8  %i_sample_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %i_sample)

]]></node>
<StgValue><ssdm name="i_sample_read"/></StgValue>
</operation>

<operation id="18" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="17" bw="16" op_0_bw="16" op_1_bw="16">
<![CDATA[
:9  %i_index_read = call i16 @_ssdm_op_Read.ap_auto.i16(i16 %i_index)

]]></node>
<StgValue><ssdm name="i_index_read"/></StgValue>
</operation>

<operation id="19" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="18" bw="32" op_0_bw="16">
<![CDATA[
:10  %tmp = zext i16 %i_index_read to i32

]]></node>
<StgValue><ssdm name="tmp"/></StgValue>
</operation>

<operation id="20" st_id="1" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="22" bw="8" op_0_bw="8" op_1_bw="32">
<![CDATA[
:14  %indices_stride_addr = getelementptr i8* %indices_stride, i32 %tmp

]]></node>
<StgValue><ssdm name="indices_stride_addr"/></StgValue>
</operation>

<operation id="21" st_id="1" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="23" bw="1" op_0_bw="1" op_1_bw="8" op_2_bw="32">
<![CDATA[
:15  %indices_stride_load_req = call i1 @_ssdm_op_ReadReq.ap_bus.i8P(i8* %indices_stride_addr, i32 1)

]]></node>
<StgValue><ssdm name="indices_stride_load_req"/></StgValue>
</operation>
</state>

<state id="2" st_id="2">

<operation id="22" st_id="2" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="24" bw="8" op_0_bw="8" op_1_bw="8">
<![CDATA[
:16  %indices_stride_addr_read = call i8 @_ssdm_op_Read.ap_bus.i8P(i8* %indices_stride_addr)

]]></node>
<StgValue><ssdm name="indices_stride_addr_read"/></StgValue>
</operation>
</state>

<state id="3" st_id="3">

<operation id="23" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="25" bw="24" op_0_bw="8">
<![CDATA[
:17  %tmp_cast = zext i8 %indices_stride_addr_read to i24

]]></node>
<StgValue><ssdm name="tmp_cast"/></StgValue>
</operation>

<operation id="24" st_id="3" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="26" bw="24" op_0_bw="16">
<![CDATA[
:18  %tmp_6_cast = zext i16 %i_sample_read to i24

]]></node>
<StgValue><ssdm name="tmp_6_cast"/></StgValue>
</operation>

<operation id="25" st_id="3" stage="4" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="24" op_0_bw="24" op_1_bw="24">
<![CDATA[
:19  %tmp_7 = mul i24 %tmp_6_cast, %tmp_cast

]]></node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="4" st_id="4">

<operation id="26" st_id="4" stage="3" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="24" op_0_bw="24" op_1_bw="24">
<![CDATA[
:19  %tmp_7 = mul i24 %tmp_6_cast, %tmp_cast

]]></node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="5" st_id="5">

<operation id="27" st_id="5" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="19" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:11  %indices_begin_addr = getelementptr i32* %indices_begin, i32 %tmp

]]></node>
<StgValue><ssdm name="indices_begin_addr"/></StgValue>
</operation>

<operation id="28" st_id="5" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="20" bw="1" op_0_bw="1" op_1_bw="32" op_2_bw="32">
<![CDATA[
:12  %indices_begin_load_req = call i1 @_ssdm_op_ReadReq.ap_bus.i32P(i32* %indices_begin_addr, i32 1)

]]></node>
<StgValue><ssdm name="indices_begin_load_req"/></StgValue>
</operation>

<operation id="29" st_id="5" stage="2" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="24" op_0_bw="24" op_1_bw="24">
<![CDATA[
:19  %tmp_7 = mul i24 %tmp_6_cast, %tmp_cast

]]></node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="6" st_id="6">

<operation id="30" st_id="6" stage="1" lat="1">
<core>NPI64M</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="21" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:13  %indices_begin_addr_read = call i32 @_ssdm_op_Read.ap_bus.i32P(i32* %indices_begin_addr)

]]></node>
<StgValue><ssdm name="indices_begin_addr_read"/></StgValue>
</operation>

<operation id="31" st_id="6" stage="1" lat="4">
<core>MulnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="27" bw="24" op_0_bw="24" op_1_bw="24">
<![CDATA[
:19  %tmp_7 = mul i24 %tmp_6_cast, %tmp_cast

]]></node>
<StgValue><ssdm name="tmp_7"/></StgValue>
</operation>
</state>

<state id="7" st_id="7">

<operation id="32" st_id="7" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="28" bw="32" op_0_bw="24">
<![CDATA[
:20  %tmp_7_cast = zext i24 %tmp_7 to i32

]]></node>
<StgValue><ssdm name="tmp_7_cast"/></StgValue>
</operation>

<operation id="33" st_id="7" stage="8" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="8" st_id="8">

<operation id="34" st_id="8" stage="7" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="9" st_id="9">

<operation id="35" st_id="9" stage="6" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="10" st_id="10">

<operation id="36" st_id="10" stage="5" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="11" st_id="11">

<operation id="37" st_id="11" stage="4" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="12" st_id="12">

<operation id="38" st_id="12" stage="3" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="13" st_id="13">

<operation id="39" st_id="13" stage="2" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>
</state>

<state id="14" st_id="14">

<operation id="40" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="8" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:0  call void (...)* @_ssdm_op_SpecIFCore(i16* %indices_samples, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="41" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="9" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="32" op_4_bw="32" op_5_bw="32" op_6_bw="8">
<![CDATA[
:1  call void (...)* @_ssdm_op_SpecBus(i16* %indices_samples, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="42" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="10" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8" op_8_bw="8">
<![CDATA[
:2  call void (...)* @_ssdm_op_SpecIFCore(i32* %indices_begin, i8* %indices_stride, [1 x i8]* @p_str1132, [7 x i8]* @p_str38, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="43" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="11" bw="0" op_0_bw="0" op_1_bw="16" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:3  call void (...)* @_ssdm_op_SpecIFCore(i16 %sample_length, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="44" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="12" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="8" op_5_bw="8" op_6_bw="8" op_7_bw="8">
<![CDATA[
:4  call void (...)* @_ssdm_op_SpecIFCore(i32 %sample_buffer_size, [1 x i8]* @p_str1132, [7 x i8]* @p_str39, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [1 x i8]* @p_str1132, [17 x i8]* @p_str40)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="45" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="13" bw="0" op_0_bw="0" op_1_bw="32" op_2_bw="8" op_3_bw="8" op_4_bw="32" op_5_bw="32" op_6_bw="32" op_7_bw="8">
<![CDATA[
:5  call void (...)* @_ssdm_op_SpecBus(i32* %indices_begin, i8* %indices_stride, [7 x i8]* @p_str35, i32 0, i32 0, i32 0, [1 x i8]* @p_str1132)

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>

<operation id="46" st_id="14" stage="1" lat="8">
<core>AddSubnS</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="29" bw="32" op_0_bw="32" op_1_bw="32">
<![CDATA[
:21  %offset = add i32 %tmp_7_cast, %indices_begin_addr_read

]]></node>
<StgValue><ssdm name="offset"/></StgValue>
</operation>

<operation id="47" st_id="14" stage="1" lat="1">
<core>NULL</core>
<MemPortIdVec></MemPortIdVec>
<condition id="-1">
<or_exp><and_exp></and_exp></or_exp>
</condition>

<node id="30" bw="0" op_0_bw="32">
<![CDATA[
:22  ret i32 %offset

]]></node>
<StgValue><ssdm name=""/></StgValue>
</operation>
</state>
</state_list>


<ports>
</ports>


<dataflows>
</dataflows>


</stg>
