//
// Generated by Bluespec Compiler (build 7d0b6cf)
//
// On Fri Feb 28 15:58:26 EST 2020
//
//
// Ports:
// Name                         I/O  size props
// CLK                            I     1 clock
// RST_N                          I     1 reset
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module top(CLK,
	   RST_N);
  input  CLK;
  input  RST_N;

  // inlined wires
  wire [1 : 0] bram_serverAdapterA_s1_1$wget,
	       bram_serverAdapterA_writeWithResp$wget,
	       bram_serverAdapterB_s1_1$wget,
	       bram_serverAdapterB_writeWithResp$wget;
  wire bram_serverAdapterA_cnt_1$whas,
       bram_serverAdapterA_outData_deqCalled$whas,
       bram_serverAdapterA_outData_enqData$whas,
       bram_serverAdapterA_outData_outData$whas,
       bram_serverAdapterA_writeWithResp$whas,
       bram_serverAdapterB_cnt_1$whas,
       bram_serverAdapterB_outData_deqCalled$whas,
       bram_serverAdapterB_outData_enqData$whas,
       bram_serverAdapterB_outData_outData$whas,
       bram_serverAdapterB_writeWithResp$whas;

  // register bram_serverAdapterA_cnt
  reg [2 : 0] bram_serverAdapterA_cnt;
  wire [2 : 0] bram_serverAdapterA_cnt$D_IN;
  wire bram_serverAdapterA_cnt$EN;

  // register bram_serverAdapterA_s1
  reg [1 : 0] bram_serverAdapterA_s1;
  wire [1 : 0] bram_serverAdapterA_s1$D_IN;
  wire bram_serverAdapterA_s1$EN;

  // register bram_serverAdapterB_cnt
  reg [2 : 0] bram_serverAdapterB_cnt;
  wire [2 : 0] bram_serverAdapterB_cnt$D_IN;
  wire bram_serverAdapterB_cnt$EN;

  // register bram_serverAdapterB_s1
  reg [1 : 0] bram_serverAdapterB_s1;
  wire [1 : 0] bram_serverAdapterB_s1$D_IN;
  wire bram_serverAdapterB_s1$EN;

  // register cycle_count
  reg [31 : 0] cycle_count;
  wire [31 : 0] cycle_count$D_IN;
  wire cycle_count$EN;

  // register debug
  reg debug;
  wire debug$D_IN, debug$EN;

  // register dreq
  reg [67 : 0] dreq;
  wire [67 : 0] dreq$D_IN;
  wire dreq$EN;

  // register ireq
  reg [67 : 0] ireq;
  wire [67 : 0] ireq$D_IN;
  wire ireq$EN;

  // ports of submodule bram_memory
  wire [31 : 0] bram_memory$DIA,
		bram_memory$DIB,
		bram_memory$DOA,
		bram_memory$DOB;
  wire [13 : 0] bram_memory$ADDRA, bram_memory$ADDRB;
  wire [3 : 0] bram_memory$WEA, bram_memory$WEB;
  wire bram_memory$ENA, bram_memory$ENB;

  // ports of submodule bram_serverAdapterA_outDataCore
  wire [31 : 0] bram_serverAdapterA_outDataCore$D_IN,
		bram_serverAdapterA_outDataCore$D_OUT;
  wire bram_serverAdapterA_outDataCore$CLR,
       bram_serverAdapterA_outDataCore$DEQ,
       bram_serverAdapterA_outDataCore$EMPTY_N,
       bram_serverAdapterA_outDataCore$ENQ,
       bram_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule bram_serverAdapterB_outDataCore
  wire [31 : 0] bram_serverAdapterB_outDataCore$D_IN,
		bram_serverAdapterB_outDataCore$D_OUT;
  wire bram_serverAdapterB_outDataCore$CLR,
       bram_serverAdapterB_outDataCore$DEQ,
       bram_serverAdapterB_outDataCore$EMPTY_N,
       bram_serverAdapterB_outDataCore$ENQ,
       bram_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule rv_core
  wire [67 : 0] rv_core$rule_ExternalD_input_fromDMem_data0_data0,
		rv_core$rule_ExternalD_input_fromDMem_data0_data1,
		rv_core$rule_ExternalD_input_toDMem_data0_data0,
		rv_core$rule_ExternalD_input_toDMem_data0_data1,
		rv_core$rule_ExternalD_output_fromDMem_data0_data0,
		rv_core$rule_ExternalD_output_fromDMem_data0_data1,
		rv_core$rule_ExternalD_output_toDMem_data0_data0,
		rv_core$rule_ExternalD_output_toDMem_data0_data1,
		rv_core$rule_ExternalI_input_fromIMem_data0_data0,
		rv_core$rule_ExternalI_input_fromIMem_data0_data1,
		rv_core$rule_ExternalI_input_toIMem_data0_data0,
		rv_core$rule_ExternalI_input_toIMem_data0_data1,
		rv_core$rule_ExternalI_output_fromIMem_data0_data0,
		rv_core$rule_ExternalI_output_fromIMem_data0_data1,
		rv_core$rule_ExternalI_output_toIMem_data0_data0,
		rv_core$rule_ExternalI_output_toIMem_data0_data1;
  wire rv_core$rule_ExternalD_input_fromDMem_data0_read0,
       rv_core$rule_ExternalD_input_fromDMem_data0_read1,
       rv_core$rule_ExternalD_input_fromDMem_data0_write0,
       rv_core$rule_ExternalD_input_fromDMem_data0_write1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_data0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_data1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_read0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_read1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_write0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_write1,
       rv_core$rule_ExternalD_input_toDMem_data0_read0,
       rv_core$rule_ExternalD_input_toDMem_data0_read1,
       rv_core$rule_ExternalD_input_toDMem_data0_write0,
       rv_core$rule_ExternalD_input_toDMem_data0_write1,
       rv_core$rule_ExternalD_input_toDMem_valid0_data0,
       rv_core$rule_ExternalD_input_toDMem_valid0_data1,
       rv_core$rule_ExternalD_input_toDMem_valid0_read0,
       rv_core$rule_ExternalD_input_toDMem_valid0_read1,
       rv_core$rule_ExternalD_input_toDMem_valid0_write0,
       rv_core$rule_ExternalD_input_toDMem_valid0_write1,
       rv_core$rule_ExternalD_output_fromDMem_valid0_data0,
       rv_core$rule_ExternalD_output_fromDMem_valid0_data1,
       rv_core$rule_ExternalD_output_toDMem_valid0_data0,
       rv_core$rule_ExternalD_output_toDMem_valid0_data1,
       rv_core$rule_ExternalI_input_fromIMem_data0_read0,
       rv_core$rule_ExternalI_input_fromIMem_data0_read1,
       rv_core$rule_ExternalI_input_fromIMem_data0_write0,
       rv_core$rule_ExternalI_input_fromIMem_data0_write1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_data0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_data1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_read0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_read1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_write0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_write1,
       rv_core$rule_ExternalI_input_toIMem_data0_read0,
       rv_core$rule_ExternalI_input_toIMem_data0_read1,
       rv_core$rule_ExternalI_input_toIMem_data0_write0,
       rv_core$rule_ExternalI_input_toIMem_data0_write1,
       rv_core$rule_ExternalI_input_toIMem_valid0_data0,
       rv_core$rule_ExternalI_input_toIMem_valid0_data1,
       rv_core$rule_ExternalI_input_toIMem_valid0_read0,
       rv_core$rule_ExternalI_input_toIMem_valid0_read1,
       rv_core$rule_ExternalI_input_toIMem_valid0_write0,
       rv_core$rule_ExternalI_input_toIMem_valid0_write1,
       rv_core$rule_ExternalI_output_fromIMem_valid0_data0,
       rv_core$rule_ExternalI_output_fromIMem_valid0_data1,
       rv_core$rule_ExternalI_output_toIMem_valid0_data0,
       rv_core$rule_ExternalI_output_toIMem_valid0_data1;

  // rule scheduling signals
  wire WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq,
       WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_requestD,
       WILL_FIRE_RL_requestI,
       WILL_FIRE_RL_responseD,
       WILL_FIRE_RL_responseI;

  // remaining internal signals
  wire [67 : 0] x1__h5965, x1__h6525;
  wire [31 : 0] x__h4924, x__h5807;
  wire [2 : 0] bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32,
	       bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91;

  // submodule bram_memory
  BRAM2BELoad #(
		.PIPELINED(1'd0),
		.ADDR_WIDTH(32'd14),
		.DATA_WIDTH(32'd32),
		.CHUNKSIZE(32'd8),
		.WE_WIDTH(32'd4),
		.MEMSIZE(15'd16384)) bram_memory(.CLKA(CLK),
					   .CLKB(CLK),
					   .ADDRA(bram_memory$ADDRA),
					   .ADDRB(bram_memory$ADDRB),
					   .DIA(bram_memory$DIA),
					   .DIB(bram_memory$DIB),
					   .WEA(bram_memory$WEA),
					   .WEB(bram_memory$WEB),
					   .ENA(bram_memory$ENA),
					   .ENB(bram_memory$ENB),
					   .DOA(bram_memory$DOA),
					   .DOB(bram_memory$DOB));

  // submodule bram_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterA_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterA_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterA_outDataCore$DEQ),
							       .CLR(bram_serverAdapterA_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterA_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterA_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterA_outDataCore$EMPTY_N));

  // submodule bram_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterB_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterB_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterB_outDataCore$DEQ),
							       .CLR(bram_serverAdapterB_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterB_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterB_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N));

  // submodule rv_core
  rv32 rv_core(.CLK(CLK),
	       .RST_N(RST_N),
	       .rule_ExternalI_input__canfire(1'b1),
	       .rule_ExternalD_input__canfire(1'b1),
	       .rule_ExternalD_input_fromDMem_data0_data0(rv_core$rule_ExternalD_input_fromDMem_data0_data0),
	       .rule_ExternalD_input_fromDMem_data0_data1(rv_core$rule_ExternalD_input_fromDMem_data0_data1),
	       .rule_ExternalD_input_fromDMem_valid0_data0(rv_core$rule_ExternalD_input_fromDMem_valid0_data0),
	       .rule_ExternalD_input_fromDMem_valid0_data1(rv_core$rule_ExternalD_input_fromDMem_valid0_data1),
	       .rule_ExternalD_input_toDMem_data0_data0(rv_core$rule_ExternalD_input_toDMem_data0_data0),
	       .rule_ExternalD_input_toDMem_data0_data1(rv_core$rule_ExternalD_input_toDMem_data0_data1),
	       .rule_ExternalD_input_toDMem_valid0_data0(rv_core$rule_ExternalD_input_toDMem_valid0_data0),
	       .rule_ExternalD_input_toDMem_valid0_data1(rv_core$rule_ExternalD_input_toDMem_valid0_data1),
	       .rule_ExternalI_input_fromIMem_data0_data0(rv_core$rule_ExternalI_input_fromIMem_data0_data0),
	       .rule_ExternalI_input_fromIMem_data0_data1(rv_core$rule_ExternalI_input_fromIMem_data0_data1),
	       .rule_ExternalI_input_fromIMem_valid0_data0(rv_core$rule_ExternalI_input_fromIMem_valid0_data0),
	       .rule_ExternalI_input_fromIMem_valid0_data1(rv_core$rule_ExternalI_input_fromIMem_valid0_data1),
	       .rule_ExternalI_input_toIMem_data0_data0(rv_core$rule_ExternalI_input_toIMem_data0_data0),
	       .rule_ExternalI_input_toIMem_data0_data1(rv_core$rule_ExternalI_input_toIMem_data0_data1),
	       .rule_ExternalI_input_toIMem_valid0_data0(rv_core$rule_ExternalI_input_toIMem_valid0_data0),
	       .rule_ExternalI_input_toIMem_valid0_data1(rv_core$rule_ExternalI_input_toIMem_valid0_data1),
	       .rule_ExternalD_input_fromDMem_data0_read0(rv_core$rule_ExternalD_input_fromDMem_data0_read0),
	       .rule_ExternalD_input_fromDMem_data0_read1(rv_core$rule_ExternalD_input_fromDMem_data0_read1),
	       .rule_ExternalD_input_fromDMem_data0_write0(rv_core$rule_ExternalD_input_fromDMem_data0_write0),
	       .rule_ExternalD_input_fromDMem_data0_write1(rv_core$rule_ExternalD_input_fromDMem_data0_write1),
	       .rule_ExternalD_input_fromDMem_valid0_read0(rv_core$rule_ExternalD_input_fromDMem_valid0_read0),
	       .rule_ExternalD_input_fromDMem_valid0_read1(rv_core$rule_ExternalD_input_fromDMem_valid0_read1),
	       .rule_ExternalD_input_fromDMem_valid0_write0(rv_core$rule_ExternalD_input_fromDMem_valid0_write0),
	       .rule_ExternalD_input_fromDMem_valid0_write1(rv_core$rule_ExternalD_input_fromDMem_valid0_write1),
	       .rule_ExternalD_input_toDMem_data0_read0(rv_core$rule_ExternalD_input_toDMem_data0_read0),
	       .rule_ExternalD_input_toDMem_data0_read1(rv_core$rule_ExternalD_input_toDMem_data0_read1),
	       .rule_ExternalD_input_toDMem_data0_write0(rv_core$rule_ExternalD_input_toDMem_data0_write0),
	       .rule_ExternalD_input_toDMem_data0_write1(rv_core$rule_ExternalD_input_toDMem_data0_write1),
	       .rule_ExternalD_input_toDMem_valid0_read0(rv_core$rule_ExternalD_input_toDMem_valid0_read0),
	       .rule_ExternalD_input_toDMem_valid0_read1(rv_core$rule_ExternalD_input_toDMem_valid0_read1),
	       .rule_ExternalD_input_toDMem_valid0_write0(rv_core$rule_ExternalD_input_toDMem_valid0_write0),
	       .rule_ExternalD_input_toDMem_valid0_write1(rv_core$rule_ExternalD_input_toDMem_valid0_write1),
	       .rule_ExternalI_input_fromIMem_data0_read0(rv_core$rule_ExternalI_input_fromIMem_data0_read0),
	       .rule_ExternalI_input_fromIMem_data0_read1(rv_core$rule_ExternalI_input_fromIMem_data0_read1),
	       .rule_ExternalI_input_fromIMem_data0_write0(rv_core$rule_ExternalI_input_fromIMem_data0_write0),
	       .rule_ExternalI_input_fromIMem_data0_write1(rv_core$rule_ExternalI_input_fromIMem_data0_write1),
	       .rule_ExternalI_input_fromIMem_valid0_read0(rv_core$rule_ExternalI_input_fromIMem_valid0_read0),
	       .rule_ExternalI_input_fromIMem_valid0_read1(rv_core$rule_ExternalI_input_fromIMem_valid0_read1),
	       .rule_ExternalI_input_fromIMem_valid0_write0(rv_core$rule_ExternalI_input_fromIMem_valid0_write0),
	       .rule_ExternalI_input_fromIMem_valid0_write1(rv_core$rule_ExternalI_input_fromIMem_valid0_write1),
	       .rule_ExternalI_input_toIMem_data0_read0(rv_core$rule_ExternalI_input_toIMem_data0_read0),
	       .rule_ExternalI_input_toIMem_data0_read1(rv_core$rule_ExternalI_input_toIMem_data0_read1),
	       .rule_ExternalI_input_toIMem_data0_write0(rv_core$rule_ExternalI_input_toIMem_data0_write0),
	       .rule_ExternalI_input_toIMem_data0_write1(rv_core$rule_ExternalI_input_toIMem_data0_write1),
	       .rule_ExternalI_input_toIMem_valid0_read0(rv_core$rule_ExternalI_input_toIMem_valid0_read0),
	       .rule_ExternalI_input_toIMem_valid0_read1(rv_core$rule_ExternalI_input_toIMem_valid0_read1),
	       .rule_ExternalI_input_toIMem_valid0_write0(rv_core$rule_ExternalI_input_toIMem_valid0_write0),
	       .rule_ExternalI_input_toIMem_valid0_write1(rv_core$rule_ExternalI_input_toIMem_valid0_write1),
	       .rule_ExternalD_output_fromDMem_data0_data0(rv_core$rule_ExternalD_output_fromDMem_data0_data0),
	       .rule_ExternalD_output_fromDMem_data0_data1(rv_core$rule_ExternalD_output_fromDMem_data0_data1),
	       .rule_ExternalD_output_fromDMem_data0_read0(),
	       .rule_ExternalD_output_fromDMem_data0_read1(),
	       .rule_ExternalD_output_fromDMem_data0_write0(),
	       .rule_ExternalD_output_fromDMem_data0_write1(),
	       .rule_ExternalD_output_fromDMem_valid0_data0(rv_core$rule_ExternalD_output_fromDMem_valid0_data0),
	       .rule_ExternalD_output_fromDMem_valid0_data1(rv_core$rule_ExternalD_output_fromDMem_valid0_data1),
	       .rule_ExternalD_output_fromDMem_valid0_read0(),
	       .rule_ExternalD_output_fromDMem_valid0_read1(),
	       .rule_ExternalD_output_fromDMem_valid0_write0(),
	       .rule_ExternalD_output_fromDMem_valid0_write1(),
	       .rule_ExternalD_output_toDMem_data0_data0(rv_core$rule_ExternalD_output_toDMem_data0_data0),
	       .rule_ExternalD_output_toDMem_data0_data1(rv_core$rule_ExternalD_output_toDMem_data0_data1),
	       .rule_ExternalD_output_toDMem_data0_read0(),
	       .rule_ExternalD_output_toDMem_data0_read1(),
	       .rule_ExternalD_output_toDMem_data0_write0(),
	       .rule_ExternalD_output_toDMem_data0_write1(),
	       .rule_ExternalD_output_toDMem_valid0_data0(rv_core$rule_ExternalD_output_toDMem_valid0_data0),
	       .rule_ExternalD_output_toDMem_valid0_data1(rv_core$rule_ExternalD_output_toDMem_valid0_data1),
	       .rule_ExternalD_output_toDMem_valid0_read0(),
	       .rule_ExternalD_output_toDMem_valid0_read1(),
	       .rule_ExternalD_output_toDMem_valid0_write0(),
	       .rule_ExternalD_output_toDMem_valid0_write1(),
	       .rule_ExternalI_output_fromIMem_data0_data0(rv_core$rule_ExternalI_output_fromIMem_data0_data0),
	       .rule_ExternalI_output_fromIMem_data0_data1(rv_core$rule_ExternalI_output_fromIMem_data0_data1),
	       .rule_ExternalI_output_fromIMem_data0_read0(),
	       .rule_ExternalI_output_fromIMem_data0_read1(),
	       .rule_ExternalI_output_fromIMem_data0_write0(),
	       .rule_ExternalI_output_fromIMem_data0_write1(),
	       .rule_ExternalI_output_fromIMem_valid0_data0(rv_core$rule_ExternalI_output_fromIMem_valid0_data0),
	       .rule_ExternalI_output_fromIMem_valid0_data1(rv_core$rule_ExternalI_output_fromIMem_valid0_data1),
	       .rule_ExternalI_output_fromIMem_valid0_read0(),
	       .rule_ExternalI_output_fromIMem_valid0_read1(),
	       .rule_ExternalI_output_fromIMem_valid0_write0(),
	       .rule_ExternalI_output_fromIMem_valid0_write1(),
	       .rule_ExternalI_output_toIMem_data0_data0(rv_core$rule_ExternalI_output_toIMem_data0_data0),
	       .rule_ExternalI_output_toIMem_data0_data1(rv_core$rule_ExternalI_output_toIMem_data0_data1),
	       .rule_ExternalI_output_toIMem_data0_read0(),
	       .rule_ExternalI_output_toIMem_data0_read1(),
	       .rule_ExternalI_output_toIMem_data0_write0(),
	       .rule_ExternalI_output_toIMem_data0_write1(),
	       .rule_ExternalI_output_toIMem_valid0_data0(rv_core$rule_ExternalI_output_toIMem_valid0_data0),
	       .rule_ExternalI_output_toIMem_valid0_data1(rv_core$rule_ExternalI_output_toIMem_valid0_data1),
	       .rule_ExternalI_output_toIMem_valid0_read0(),
	       .rule_ExternalI_output_toIMem_valid0_read1(),
	       .rule_ExternalI_output_toIMem_valid0_write0(),
	       .rule_ExternalI_output_toIMem_valid0_write1());

  // rule RL_responseD
  assign WILL_FIRE_RL_responseD =
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ||
	     (bram_serverAdapterA_outDataCore$EMPTY_N ||
	      bram_serverAdapterA_outData_enqData$whas) &&
	     bram_serverAdapterA_outData_outData$whas ;

  // rule RL_requestD
  assign WILL_FIRE_RL_requestD =
	     !rv_core$rule_ExternalD_output_toDMem_valid0_data0 ||
	     (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 ;

  // rule RL_bram_serverAdapterA_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq =
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;

  // rule RL_responseI
  assign WILL_FIRE_RL_responseI =
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ||
	     (bram_serverAdapterB_outDataCore$EMPTY_N ||
	      bram_serverAdapterB_outData_enqData$whas) &&
	     bram_serverAdapterB_outData_outData$whas ;

  // rule RL_requestI
  assign WILL_FIRE_RL_requestI =
	     !rv_core$rule_ExternalI_output_toIMem_valid0_data0 ||
	     (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;

  // rule RL_bram_serverAdapterB_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq =
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;

  // inlined wires
  assign bram_serverAdapterA_outData_enqData$whas =
	     (!bram_serverAdapterA_s1[0] ||
	      bram_serverAdapterA_outDataCore$FULL_N) &&
	     bram_serverAdapterA_s1[1] &&
	     bram_serverAdapterA_s1[0] ;
  assign bram_serverAdapterA_outData_outData$whas =
	     bram_serverAdapterA_outDataCore$EMPTY_N ||
	     !bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_cnt_1$whas =
	     WILL_FIRE_RL_requestD &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	     (!bram_serverAdapterA_writeWithResp$wget[1] ||
	      bram_serverAdapterA_writeWithResp$wget[0]) ;
  assign bram_serverAdapterA_writeWithResp$wget =
	     { rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] !=
	       4'd0,
	       1'd1 } ;
  assign bram_serverAdapterA_writeWithResp$whas =
	     WILL_FIRE_RL_requestD &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 ;
  assign bram_serverAdapterA_s1_1$wget =
	     { 1'd1,
	       !bram_serverAdapterA_writeWithResp$wget[1] ||
	       bram_serverAdapterA_writeWithResp$wget[0] } ;
  assign bram_serverAdapterB_outData_enqData$whas =
	     (!bram_serverAdapterB_s1[0] ||
	      bram_serverAdapterB_outDataCore$FULL_N) &&
	     bram_serverAdapterB_s1[1] &&
	     bram_serverAdapterB_s1[0] ;
  assign bram_serverAdapterB_outData_outData$whas =
	     bram_serverAdapterB_outDataCore$EMPTY_N ||
	     !bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_cnt_1$whas =
	     WILL_FIRE_RL_requestI &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	     (!bram_serverAdapterB_writeWithResp$wget[1] ||
	      bram_serverAdapterB_writeWithResp$wget[0]) ;
  assign bram_serverAdapterB_writeWithResp$wget =
	     { rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64] !=
	       4'd0,
	       1'd1 } ;
  assign bram_serverAdapterB_writeWithResp$whas =
	     WILL_FIRE_RL_requestI &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 ;
  assign bram_serverAdapterB_s1_1$wget =
	     { 1'd1,
	       !bram_serverAdapterB_writeWithResp$wget[1] ||
	       bram_serverAdapterB_writeWithResp$wget[0] } ;
  assign bram_serverAdapterA_outData_deqCalled$whas =
	     WILL_FIRE_RL_responseD &&
	     !rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ;
  assign bram_serverAdapterB_outData_deqCalled$whas =
	     WILL_FIRE_RL_responseI &&
	     !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ;

  // register bram_serverAdapterA_cnt
  assign bram_serverAdapterA_cnt$D_IN =
	     bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 ;
  assign bram_serverAdapterA_cnt$EN =
	     bram_serverAdapterA_cnt_1$whas ||
	     bram_serverAdapterA_outData_deqCalled$whas ;

  // register bram_serverAdapterA_s1
  assign bram_serverAdapterA_s1$D_IN =
	     { bram_serverAdapterA_writeWithResp$whas &&
	       bram_serverAdapterA_s1_1$wget[1],
	       bram_serverAdapterA_s1_1$wget[0] } ;
  assign bram_serverAdapterA_s1$EN = 1'd1 ;

  // register bram_serverAdapterB_cnt
  assign bram_serverAdapterB_cnt$D_IN =
	     bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 ;
  assign bram_serverAdapterB_cnt$EN =
	     bram_serverAdapterB_cnt_1$whas ||
	     bram_serverAdapterB_outData_deqCalled$whas ;

  // register bram_serverAdapterB_s1
  assign bram_serverAdapterB_s1$D_IN =
	     { bram_serverAdapterB_writeWithResp$whas &&
	       bram_serverAdapterB_s1_1$wget[1],
	       bram_serverAdapterB_s1_1$wget[0] } ;
  assign bram_serverAdapterB_s1$EN = 1'd1 ;

  // register cycle_count
  assign cycle_count$D_IN = cycle_count + 32'd1 ;
  assign cycle_count$EN = 1'd1 ;

  // register debug
  assign debug$D_IN = 1'b0 ;
  assign debug$EN = 1'b0 ;

  // register dreq
  assign dreq$D_IN = rv_core$rule_ExternalD_output_toDMem_data0_data0 ;
  assign dreq$EN = bram_serverAdapterA_writeWithResp$whas ;

  // register ireq
  assign ireq$D_IN = rv_core$rule_ExternalI_output_toIMem_data0_data0 ;
  assign ireq$EN = bram_serverAdapterB_writeWithResp$whas ;

  // submodule bram_memory
  assign bram_memory$ADDRA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[47:34] ;
  assign bram_memory$ADDRB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[47:34] ;
  assign bram_memory$DIA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] ;
  assign bram_memory$DIB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[31:0] ;
  assign bram_memory$WEA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] ;
  assign bram_memory$WEB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64] ;
  assign bram_memory$ENA = bram_serverAdapterA_writeWithResp$whas ;
  assign bram_memory$ENB = bram_serverAdapterB_writeWithResp$whas ;

  // submodule bram_serverAdapterA_outDataCore
  assign bram_serverAdapterA_outDataCore$D_IN = bram_memory$DOA ;
  assign bram_serverAdapterA_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     !bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     !bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$CLR = 1'b0 ;

  // submodule bram_serverAdapterB_outDataCore
  assign bram_serverAdapterB_outDataCore$D_IN = bram_memory$DOB ;
  assign bram_serverAdapterB_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     !bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     !bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$CLR = 1'b0 ;

  // submodule rv_core
  assign rv_core$rule_ExternalD_input_fromDMem_data0_data0 =
	     bram_serverAdapterA_outData_deqCalled$whas ?
	       x1__h6525 :
	       rv_core$rule_ExternalD_output_fromDMem_data0_data0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_data1 =
	     rv_core$rule_ExternalD_output_fromDMem_data0_data1 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_data0 =
	     bram_serverAdapterA_outData_deqCalled$whas ||
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_data1 =
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data1 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_data0 =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_data1 =
	     rv_core$rule_ExternalD_output_toDMem_data0_data1 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_data0 =
	     !bram_serverAdapterA_writeWithResp$whas &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_data1 =
	     rv_core$rule_ExternalD_output_toDMem_valid0_data1 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_data0 =
	     bram_serverAdapterB_outData_deqCalled$whas ?
	       x1__h5965 :
	       rv_core$rule_ExternalI_output_fromIMem_data0_data0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_data1 =
	     rv_core$rule_ExternalI_output_fromIMem_data0_data1 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_data0 =
	     bram_serverAdapterB_outData_deqCalled$whas ||
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_data1 =
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data1 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_data0 =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_data1 =
	     rv_core$rule_ExternalI_output_toIMem_data0_data1 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_data0 =
	     !bram_serverAdapterB_writeWithResp$whas &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_data1 =
	     rv_core$rule_ExternalI_output_toIMem_valid0_data1 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_write1 = 1'b0 ;

  // remaining internal signals
  assign bram_serverAdapterA_cnt_6_PLUS_IF_bram_serverA_ETC___d32 =
	     bram_serverAdapterA_cnt +
	     (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign bram_serverAdapterB_cnt_5_PLUS_IF_bram_serverA_ETC___d91 =
	     bram_serverAdapterB_cnt +
	     (bram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign x1__h5965 = { ireq[67:32], x__h4924 } ;
  assign x1__h6525 = { dreq[67:32], x__h5807 } ;
  assign x__h4924 =
	     bram_serverAdapterB_outDataCore$EMPTY_N ?
	       bram_serverAdapterB_outDataCore$D_OUT :
	       bram_memory$DOB ;
  assign x__h5807 =
	     bram_serverAdapterA_outDataCore$EMPTY_N ?
	       bram_serverAdapterA_outDataCore$D_OUT :
	       bram_memory$DOA ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	cycle_count <= `BSV_ASSIGNMENT_DELAY 32'd0;
	debug <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (bram_serverAdapterA_cnt$EN)
	  bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_cnt$D_IN;
	if (bram_serverAdapterA_s1$EN)
	  bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_s1$D_IN;
	if (bram_serverAdapterB_cnt$EN)
	  bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_cnt$D_IN;
	if (bram_serverAdapterB_s1$EN)
	  bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_s1$D_IN;
	if (cycle_count$EN)
	  cycle_count <= `BSV_ASSIGNMENT_DELAY cycle_count$D_IN;
	if (debug$EN) debug <= `BSV_ASSIGNMENT_DELAY debug$D_IN;
      end
    if (dreq$EN) dreq <= `BSV_ASSIGNMENT_DELAY dreq$D_IN;
    if (ireq$EN) ireq <= `BSV_ASSIGNMENT_DELAY ireq$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    bram_serverAdapterA_cnt = 3'h2;
    bram_serverAdapterA_s1 = 2'h2;
    bram_serverAdapterB_cnt = 3'h2;
    bram_serverAdapterB_s1 = 2'h2;
    cycle_count = 32'hAAAAAAAA;
    debug = 1'h0;
    dreq = 68'hAAAAAAAAAAAAAAAAA;
    ireq = 68'hAAAAAAAAAAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterA_s1[1] &&
	  !bram_serverAdapterA_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000000)
	$fwrite(32'h80000002,
		"%c",
		rv_core$rule_ExternalD_output_toDMem_data0_data0[7:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000004)
	$fwrite(32'h80000002,
		"%0d",
		rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000004)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] == 32'd0)
	$fdisplay(32'h80000002, "  \033[0;32mPASS\033[0m");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] != 32'd0)
	$fdisplay(32'h80000002,
		  "  \033[0;31mFAIL\033[0m (%0d)",
		  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterB_s1[1] &&
	  !bram_serverAdapterB_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("Communicating a response:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("Mem { ", "byte_en: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[67:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[63:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[31:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", x__h4924);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("Got request from core:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("Mem { ", "byte_en: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[63:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[31:0],
	       " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("\n");
  end
  // synopsys translate_on
endmodule  // top

