#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Tue Dec 25 20:07:05 2018
# Process ID: 14144
# Current directory: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1
# Command line: vivado.exe -log SOPC.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source SOPC.tcl -notrace
# Log file: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC.vdi
# Journal file: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1\vivado.jou
#-----------------------------------------------------------
source SOPC.tcl -notrace
Command: link_design -top SOPC -part xc7a100tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint 'd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/cache/cache.dcp' for cell 'cache0'
INFO: [Project 1-454] Reading design checkpoint 'd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.dcp' for cell 'clk_divider'
INFO: [Project 1-454] Reading design checkpoint 'd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/SDTrans/SDTrans.dcp' for cell 'SD_0/SD_PHY_Controller/SDMEM'
INFO: [Project 1-454] Reading design checkpoint 'd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'sealedDDR_0/clk_divider'
INFO: [Project 1-454] Reading design checkpoint 'd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/ddr2_ram/ddr2_ram.dcp' for cell 'sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram'
INFO: [Netlist 29-17] Analyzing 1382 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2018.2
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-35] Removing redundant IBUF, clk_divider/inst/clkin1_ibufg, from the path connected to top-level port: clk100mhz 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Opt 31-35] Removing redundant IBUF, sealedDDR_0/clk_divider/inst/clkin1_ibufg, from the path connected to top-level port: clk100mhz 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'clk_divider/clk_in1' is not directly connected to top level port. Synthesis is ignored for d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu/clk_wiz_for_cpu.edf but preserved for implementation. [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu/clk_wiz_for_cpu.edf:276]
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'sealedDDR_0/clk_divider/clk_in1' is not directly connected to top level port. Synthesis is ignored for d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0.edf but preserved for implementation. [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0.edf:276]
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/ddr2_ram/ddr2_ram/user_design/constraints/ddr2_ram.xdc] for cell 'sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/ddr2_ram/ddr2_ram/user_design/constraints/ddr2_ram.xdc] for cell 'sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'sealedDDR_0/clk_divider/inst'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'sealedDDR_0/clk_divider/inst'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'sealedDDR_0/clk_divider/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
get_clocks: Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1256.219 ; gain = 541.914
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'sealedDDR_0/clk_divider/inst'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc] for cell 'clk_divider/inst'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc] for cell 'clk_divider/inst'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc] for cell 'clk_divider/inst'
INFO: [Timing 38-2] Deriving generated clocks [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc:57]
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc] for cell 'clk_divider/inst'
Parsing XDC File [D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc]
CRITICAL WARNING: [Common 17-163] Missing value for option 'objects', please type 'set_property -help' for usage info. [D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc:112]
Finished Parsing XDC File [D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/constrs_1/Mips54_LoadBoard.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 571 instances were transformed.
  IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 2 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 16 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM256X1S => RAM256X1S (MUXF7, MUXF7, MUXF8, RAMS64E, RAMS64E, RAMS64E, RAMS64E): 448 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 104 instances

15 Infos, 4 Warnings, 1 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:36 . Memory (MB): peak = 1256.219 ; gain = 934.301
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[0] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[1] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[2] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[3] expects both input and output buffering but the buffers are incomplete.
INFO: [Project 1-461] DRC finished with 0 Errors, 4 Warnings
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1256.219 ; gain = 0.000

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1788be53c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1263.660 ; gain = 7.441

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 3 inverter(s) to 5 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 103575c58

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
Phase 2 Constant propagation | Checksum: 1c1df4429

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-389] Phase Constant propagation created 33 cells and removed 299 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 19bca9ad6

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 242 cells

Phase 4 BUFG optimization
INFO: [Opt 31-194] Inserted BUFG clk100mhz_IBUF_BUFG_inst to drive 623 load(s) on clock net clk100mhz_IBUF_BUFG
INFO: [Opt 31-193] Inserted 1 BUFG(s) on clock nets
Phase 4 BUFG optimization | Checksum: 17b25167b

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-662] Phase BUFG optimization created 1 cells of which 1 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 192d78512

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: e3123b01

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 1 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 1263.660 ; gain = 0.000
Ending Logic Optimization Task | Checksum: b3fda5fd

Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1263.660 ; gain = 0.000

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: b3fda5fd

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.100 . Memory (MB): peak = 1263.660 ; gain = 0.000

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: b3fda5fd

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
33 Infos, 8 Warnings, 1 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1263.660 ; gain = 7.441
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.208 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file SOPC_drc_opted.rpt -pb SOPC_drc_opted.pb -rpx SOPC_drc_opted.rpx
Command: report_drc -file SOPC_drc_opted.rpt -pb SOPC_drc_opted.pb -rpx SOPC_drc_opted.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_drc_opted.rpt.
report_drc completed successfully
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[0] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[1] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[2] expects both input and output buffering but the buffers are incomplete.
WARNING: [DRC RPBF-3] IO port buffering is incomplete: Device port SD_DAT[3] expects both input and output buffering but the buffers are incomplete.
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 4 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1263.660 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 683664f6

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1263.660 ; gain = 0.000
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1263.660 ; gain = 0.000

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1656df90b

Time (s): cpu = 00:00:16 ; elapsed = 00:00:12 . Memory (MB): peak = 1263.660 ; gain = 0.000

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 173e99e39

Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 173e99e39

Time (s): cpu = 00:00:25 ; elapsed = 00:00:19 . Memory (MB): peak = 1328.031 ; gain = 64.371
Phase 1 Placer Initialization | Checksum: 173e99e39

Time (s): cpu = 00:00:26 ; elapsed = 00:00:19 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 1c0ec5cad

Time (s): cpu = 00:00:27 ; elapsed = 00:00:20 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 2.2 Physical Synthesis In Placer
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1328.031 ; gain = 0.000

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------
|  Optimization       |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------
|  Very High Fanout   |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total              |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------


Phase 2.2 Physical Synthesis In Placer | Checksum: 18d7d4295

Time (s): cpu = 00:00:55 ; elapsed = 00:00:37 . Memory (MB): peak = 1328.031 ; gain = 64.371
Phase 2 Global Placement | Checksum: 1d42f4d1d

Time (s): cpu = 00:00:57 ; elapsed = 00:00:38 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1d42f4d1d

Time (s): cpu = 00:00:57 ; elapsed = 00:00:38 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 18e6550eb

Time (s): cpu = 00:01:01 ; elapsed = 00:00:42 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1b5857c19

Time (s): cpu = 00:01:01 ; elapsed = 00:00:42 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1151273fa

Time (s): cpu = 00:01:01 ; elapsed = 00:00:43 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1790bcccc

Time (s): cpu = 00:01:08 ; elapsed = 00:00:49 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1da63b4e0

Time (s): cpu = 00:01:09 ; elapsed = 00:00:50 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1da63b4e0

Time (s): cpu = 00:01:09 ; elapsed = 00:00:50 . Memory (MB): peak = 1328.031 ; gain = 64.371
Phase 3 Detail Placement | Checksum: 1da63b4e0

Time (s): cpu = 00:01:09 ; elapsed = 00:00:50 . Memory (MB): peak = 1328.031 ; gain = 64.371

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1d73c1246

Phase 4.1.1.1 BUFG Insertion
INFO: [Place 46-33] Processed net rst_IBUF, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-31] BUFG insertion identified 1 candidate nets, 0 success, 1 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1d73c1246

Time (s): cpu = 00:01:19 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.242. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 2439e9613

Time (s): cpu = 00:01:19 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973
Phase 4.1 Post Commit Optimization | Checksum: 2439e9613

Time (s): cpu = 00:01:19 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 2439e9613

Time (s): cpu = 00:01:20 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 2439e9613

Time (s): cpu = 00:01:20 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 20729c7d2

Time (s): cpu = 00:01:20 ; elapsed = 00:00:57 . Memory (MB): peak = 1359.633 ; gain = 95.973
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 20729c7d2

Time (s): cpu = 00:01:20 ; elapsed = 00:00:58 . Memory (MB): peak = 1359.633 ; gain = 95.973
Ending Placer Task | Checksum: 125553eb1

Time (s): cpu = 00:01:20 ; elapsed = 00:00:58 . Memory (MB): peak = 1359.633 ; gain = 95.973
INFO: [Common 17-83] Releasing license: Implementation
57 Infos, 12 Warnings, 1 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:26 ; elapsed = 00:01:01 . Memory (MB): peak = 1359.633 ; gain = 95.973
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:08 ; elapsed = 00:00:03 . Memory (MB): peak = 1365.648 ; gain = 6.016
INFO: [Common 17-1381] The checkpoint 'D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file SOPC_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.126 . Memory (MB): peak = 1365.648 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file SOPC_utilization_placed.rpt -pb SOPC_utilization_placed.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.344 . Memory (MB): peak = 1365.648 ; gain = 0.000
INFO: [runtcl-4] Executing : report_control_sets -verbose -file SOPC_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.156 . Memory (MB): peak = 1365.648 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: b6118478 ConstDB: 0 ShapeSum: 6f43ba39 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: b0c61dfa

Time (s): cpu = 00:00:54 ; elapsed = 00:00:45 . Memory (MB): peak = 1467.941 ; gain = 102.293
Post Restoration Checksum: NetGraph: 2783c21a NumContArr: 89425be0 Constraints: 0 Timing: 0

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: b0c61dfa

Time (s): cpu = 00:00:55 ; elapsed = 00:00:46 . Memory (MB): peak = 1467.941 ; gain = 102.293

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: b0c61dfa

Time (s): cpu = 00:00:55 ; elapsed = 00:00:46 . Memory (MB): peak = 1473.980 ; gain = 108.332

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: b0c61dfa

Time (s): cpu = 00:00:55 ; elapsed = 00:00:46 . Memory (MB): peak = 1473.980 ; gain = 108.332
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 107a794c5

Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 1504.371 ; gain = 138.723
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.279  | TNS=0.000  | WHS=-0.133 | THS=-11.650|

Phase 2 Router Initialization | Checksum: 1856558fe

Time (s): cpu = 00:01:10 ; elapsed = 00:00:56 . Memory (MB): peak = 1542.844 ; gain = 177.195

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1375fe1d1

Time (s): cpu = 00:01:16 ; elapsed = 00:00:59 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1044
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.211  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 22e4411ef

Time (s): cpu = 00:01:26 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.211  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: ce909704

Time (s): cpu = 00:01:27 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754
Phase 4 Rip-up And Reroute | Checksum: ce909704

Time (s): cpu = 00:01:27 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: ce909704

Time (s): cpu = 00:01:27 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: ce909704

Time (s): cpu = 00:01:27 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754
Phase 5 Delay and Skew Optimization | Checksum: ce909704

Time (s): cpu = 00:01:27 ; elapsed = 00:01:05 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 167378f06

Time (s): cpu = 00:01:29 ; elapsed = 00:01:06 . Memory (MB): peak = 1543.402 ; gain = 177.754
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.291  | TNS=0.000  | WHS=0.008  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: d03ced22

Time (s): cpu = 00:01:29 ; elapsed = 00:01:06 . Memory (MB): peak = 1543.402 ; gain = 177.754
Phase 6 Post Hold Fix | Checksum: d03ced22

Time (s): cpu = 00:01:29 ; elapsed = 00:01:06 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 2.33708 %
  Global Horizontal Routing Utilization  = 3.14756 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: d03ced22

Time (s): cpu = 00:01:29 ; elapsed = 00:01:07 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: d03ced22

Time (s): cpu = 00:01:30 ; elapsed = 00:01:07 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: c02da4a8

Time (s): cpu = 00:01:31 ; elapsed = 00:01:08 . Memory (MB): peak = 1543.402 ; gain = 177.754

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=2.291  | TNS=0.000  | WHS=0.008  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: c02da4a8

Time (s): cpu = 00:01:31 ; elapsed = 00:01:08 . Memory (MB): peak = 1543.402 ; gain = 177.754
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:31 ; elapsed = 00:01:08 . Memory (MB): peak = 1543.402 ; gain = 177.754

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
75 Infos, 12 Warnings, 1 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:39 ; elapsed = 00:01:13 . Memory (MB): peak = 1543.402 ; gain = 177.754
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:09 ; elapsed = 00:00:03 . Memory (MB): peak = 1543.402 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 1543.402 ; gain = 0.000
INFO: [runtcl-4] Executing : report_drc -file SOPC_drc_routed.rpt -pb SOPC_drc_routed.pb -rpx SOPC_drc_routed.rpx
Command: report_drc -file SOPC_drc_routed.rpt -pb SOPC_drc_routed.pb -rpx SOPC_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:12 ; elapsed = 00:00:07 . Memory (MB): peak = 1543.594 ; gain = 0.191
INFO: [runtcl-4] Executing : report_methodology -file SOPC_methodology_drc_routed.rpt -pb SOPC_methodology_drc_routed.pb -rpx SOPC_methodology_drc_routed.rpx
Command: report_methodology -file SOPC_methodology_drc_routed.rpt -pb SOPC_methodology_drc_routed.pb -rpx SOPC_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/impl_1/SOPC_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 1608.063 ; gain = 64.469
INFO: [runtcl-4] Executing : report_power -file SOPC_power_routed.rpt -pb SOPC_power_summary_routed.pb -rpx SOPC_power_routed.rpx
Command: report_power -file SOPC_power_routed.rpt -pb SOPC_power_summary_routed.pb -rpx SOPC_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
87 Infos, 12 Warnings, 1 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 1640.598 ; gain = 32.535
INFO: [runtcl-4] Executing : report_route_status -file SOPC_route_status.rpt -pb SOPC_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -file SOPC_timing_summary_routed.rpt -pb SOPC_timing_summary_routed.pb -rpx SOPC_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file SOPC_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found.
INFO: [runtcl-4] Executing : report_clock_utilization -file SOPC_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file SOPC_bus_skew_routed.rpt -pb SOPC_bus_skew_routed.pb -rpx SOPC_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Timing Stage: Requireds.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Command: write_bitstream -force SOPC.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z output sccpu/ex0/I_MDU/multiplier/z/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__0 output sccpu/ex0/I_MDU/multiplier/z__0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__1 output sccpu/ex0/I_MDU/multiplier/z__1/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__2 output sccpu/ex0/I_MDU/multiplier/z__2/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z multiplier stage sccpu/ex0/I_MDU/multiplier/z/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__0 multiplier stage sccpu/ex0/I_MDU/multiplier/z__0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__1 multiplier stage sccpu/ex0/I_MDU/multiplier/z__1/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP sccpu/ex0/I_MDU/multiplier/z__2 multiplier stage sccpu/ex0/I_MDU/multiplier/z__2/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
WARNING: [DRC PDRC-153] Gated clock check: Net sccpu/id_ex0/mem_wdata_reg[0]_0 is a gated clock net sourced by a combinational pin sccpu/id_ex0/clz_result_reg[5]_i_2/O, cell sccpu/id_ex0/clz_result_reg[5]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net sccpu/id_ex0/reg1_o_reg[31]_i_7_n_3 is a gated clock net sourced by a combinational pin sccpu/id_ex0/reg1_o_reg[31]_i_7/O, cell sccpu/id_ex0/reg1_o_reg[31]_i_7. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC PDRC-153] Gated clock check: Net sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/cstate_reg[0]_0 is a gated clock net sourced by a combinational pin sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_cmd_reg[0]_i_2/O, cell sealedDDR_0/ddr2_wr_ins/ddr2_write_ctr_imp/app_cmd_reg[0]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data.
WARNING: [DRC REQP-1709] Clock output buffering: PLLE2_ADV connectivity violation. The signal sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram/u_ddr2_ram_mig/u_ddr2_infrastructure/pll_clk3_out on the sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram/u_ddr2_ram_mig/u_ddr2_infrastructure/plle2_i/CLKOUT3 pin of sealedDDR_0/ddr2_wr_ins/weight_ddr2_ram/u_ddr2_ram_mig/u_ddr2_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 13 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./SOPC.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory when using a WebPACK part without a full Vivado license. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
105 Infos, 25 Warnings, 1 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:52 ; elapsed = 00:00:50 . Memory (MB): peak = 2102.145 ; gain = 461.547
INFO: [Common 17-206] Exiting Vivado at Tue Dec 25 20:11:56 2018...
