//
// Generated by Bluespec Compiler, version 2016.07.beta1 (build 34806, 2016-07-05)
//
// On Thu Feb 27 13:26:09 EST 2020
//
//
// Ports:
// Name                         I/O  size props
// uart_pins_SOUT                 O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// uart_pins_SIN                  I     1 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module top_fpga(CLK,
		      RST_N,

		      uart_pins_SIN,

		      uart_pins_SOUT);
  input  CLK;
  input  RST_N;

  // action method uart_pins_sin
  input  uart_pins_SIN;

  // value method uart_pins_sout
  output uart_pins_SOUT;

  // signals for module outputs
  wire uart_pins_SOUT;

  // inlined wires
  wire [1 : 0] bram_serverAdapterA_s1_1$wget, bram_serverAdapterB_s1_1$wget;
  wire bram_serverAdapterA_cnt_1$whas,
       bram_serverAdapterA_outData_deqCalled$whas,
       bram_serverAdapterA_outData_enqData$whas,
       bram_serverAdapterA_outData_outData$whas,
       bram_serverAdapterA_writeWithResp$whas,
       bram_serverAdapterB_cnt_1$whas,
       bram_serverAdapterB_outData_deqCalled$whas,
       bram_serverAdapterB_outData_enqData$whas,
       bram_serverAdapterB_outData_outData$whas,
       bram_serverAdapterB_writeWithResp$whas,
       uart_fifoXmit_r_enq$whas,
       uart_pwRecvCellCountReset$whas,
       uart_pwRecvEnableBitCount$whas,
       uart_pwRecvResetBitCount$whas,
       uart_pwXmitCellCountReset$whas,
       uart_pwXmitEnableBitCount$whas,
       uart_pwXmitLoadBuffer$whas;

  // register bram_serverAdapterA_cnt
  reg [2 : 0] bram_serverAdapterA_cnt;
  wire [2 : 0] bram_serverAdapterA_cnt$D_IN;
  wire bram_serverAdapterA_cnt$EN;

  // register bram_serverAdapterA_s1
  reg [1 : 0] bram_serverAdapterA_s1;
  wire [1 : 0] bram_serverAdapterA_s1$D_IN;
  wire bram_serverAdapterA_s1$EN;

  // register bram_serverAdapterB_cnt
  reg [2 : 0] bram_serverAdapterB_cnt;
  wire [2 : 0] bram_serverAdapterB_cnt$D_IN;
  wire bram_serverAdapterB_cnt$EN;

  // register bram_serverAdapterB_s1
  reg [1 : 0] bram_serverAdapterB_s1;
  wire [1 : 0] bram_serverAdapterB_s1$D_IN;
  wire bram_serverAdapterB_s1$EN;

  // register debug
  reg debug;
  wire debug$D_IN, debug$EN;

  // register dreq
  reg [67 : 0] dreq;
  wire [67 : 0] dreq$D_IN;
  wire dreq$EN;

  // register ireq
  reg [67 : 0] ireq;
  wire [67 : 0] ireq$D_IN;
  wire ireq$EN;

  // register uart_fifoRecv_countReg
  reg [4 : 0] uart_fifoRecv_countReg;
  wire [4 : 0] uart_fifoRecv_countReg$D_IN;
  wire uart_fifoRecv_countReg$EN;

  // register uart_fifoXmit_countReg
  reg [4 : 0] uart_fifoXmit_countReg;
  wire [4 : 0] uart_fifoXmit_countReg$D_IN;
  wire uart_fifoXmit_countReg$EN;

  // register uart_rRecvBitCount
  reg [3 : 0] uart_rRecvBitCount;
  wire [3 : 0] uart_rRecvBitCount$D_IN;
  wire uart_rRecvBitCount$EN;

  // register uart_rRecvCellCount
  reg [3 : 0] uart_rRecvCellCount;
  wire [3 : 0] uart_rRecvCellCount$D_IN;
  wire uart_rRecvCellCount$EN;

  // register uart_rRecvData
  reg uart_rRecvData;
  wire uart_rRecvData$D_IN, uart_rRecvData$EN;

  // register uart_rRecvParity
  reg uart_rRecvParity;
  wire uart_rRecvParity$D_IN, uart_rRecvParity$EN;

  // register uart_rRecvState
  reg [2 : 0] uart_rRecvState;
  reg [2 : 0] uart_rRecvState$D_IN;
  wire uart_rRecvState$EN;

  // register uart_rXmitBitCount
  reg [3 : 0] uart_rXmitBitCount;
  wire [3 : 0] uart_rXmitBitCount$D_IN;
  wire uart_rXmitBitCount$EN;

  // register uart_rXmitCellCount
  reg [3 : 0] uart_rXmitCellCount;
  wire [3 : 0] uart_rXmitCellCount$D_IN;
  wire uart_rXmitCellCount$EN;

  // register uart_rXmitDataOut
  reg uart_rXmitDataOut;
  reg uart_rXmitDataOut$D_IN;
  wire uart_rXmitDataOut$EN;

  // register uart_rXmitParity
  reg uart_rXmitParity;
  wire uart_rXmitParity$D_IN, uart_rXmitParity$EN;

  // register uart_rXmitState
  reg [2 : 0] uart_rXmitState;
  reg [2 : 0] uart_rXmitState$D_IN;
  wire uart_rXmitState$EN;

  // register uart_vrRecvBuffer_0
  reg uart_vrRecvBuffer_0;
  wire uart_vrRecvBuffer_0$D_IN, uart_vrRecvBuffer_0$EN;

  // register uart_vrRecvBuffer_1
  reg uart_vrRecvBuffer_1;
  wire uart_vrRecvBuffer_1$D_IN, uart_vrRecvBuffer_1$EN;

  // register uart_vrRecvBuffer_2
  reg uart_vrRecvBuffer_2;
  wire uart_vrRecvBuffer_2$D_IN, uart_vrRecvBuffer_2$EN;

  // register uart_vrRecvBuffer_3
  reg uart_vrRecvBuffer_3;
  wire uart_vrRecvBuffer_3$D_IN, uart_vrRecvBuffer_3$EN;

  // register uart_vrRecvBuffer_4
  reg uart_vrRecvBuffer_4;
  wire uart_vrRecvBuffer_4$D_IN, uart_vrRecvBuffer_4$EN;

  // register uart_vrRecvBuffer_5
  reg uart_vrRecvBuffer_5;
  wire uart_vrRecvBuffer_5$D_IN, uart_vrRecvBuffer_5$EN;

  // register uart_vrRecvBuffer_6
  reg uart_vrRecvBuffer_6;
  wire uart_vrRecvBuffer_6$D_IN, uart_vrRecvBuffer_6$EN;

  // register uart_vrRecvBuffer_7
  reg uart_vrRecvBuffer_7;
  wire uart_vrRecvBuffer_7$D_IN, uart_vrRecvBuffer_7$EN;

  // register uart_vrXmitBuffer_0
  reg uart_vrXmitBuffer_0;
  wire uart_vrXmitBuffer_0$D_IN, uart_vrXmitBuffer_0$EN;

  // register uart_vrXmitBuffer_1
  reg uart_vrXmitBuffer_1;
  wire uart_vrXmitBuffer_1$D_IN, uart_vrXmitBuffer_1$EN;

  // register uart_vrXmitBuffer_2
  reg uart_vrXmitBuffer_2;
  wire uart_vrXmitBuffer_2$D_IN, uart_vrXmitBuffer_2$EN;

  // register uart_vrXmitBuffer_3
  reg uart_vrXmitBuffer_3;
  wire uart_vrXmitBuffer_3$D_IN, uart_vrXmitBuffer_3$EN;

  // register uart_vrXmitBuffer_4
  reg uart_vrXmitBuffer_4;
  wire uart_vrXmitBuffer_4$D_IN, uart_vrXmitBuffer_4$EN;

  // register uart_vrXmitBuffer_5
  reg uart_vrXmitBuffer_5;
  wire uart_vrXmitBuffer_5$D_IN, uart_vrXmitBuffer_5$EN;

  // register uart_vrXmitBuffer_6
  reg uart_vrXmitBuffer_6;
  wire uart_vrXmitBuffer_6$D_IN, uart_vrXmitBuffer_6$EN;

  // register uart_vrXmitBuffer_7
  reg uart_vrXmitBuffer_7;
  wire uart_vrXmitBuffer_7$D_IN, uart_vrXmitBuffer_7$EN;

  // ports of submodule bram_memory
  wire [31 : 0] bram_memory$DIA,
		bram_memory$DIB,
		bram_memory$DOA,
		bram_memory$DOB;
  wire [13 : 0] bram_memory$ADDRA, bram_memory$ADDRB;
  wire [3 : 0] bram_memory$WEA, bram_memory$WEB;
  wire bram_memory$ENA, bram_memory$ENB;

  // ports of submodule bram_serverAdapterA_outDataCore
  wire [31 : 0] bram_serverAdapterA_outDataCore$D_IN,
		bram_serverAdapterA_outDataCore$D_OUT;
  wire bram_serverAdapterA_outDataCore$CLR,
       bram_serverAdapterA_outDataCore$DEQ,
       bram_serverAdapterA_outDataCore$EMPTY_N,
       bram_serverAdapterA_outDataCore$ENQ,
       bram_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule bram_serverAdapterB_outDataCore
  wire [31 : 0] bram_serverAdapterB_outDataCore$D_IN,
		bram_serverAdapterB_outDataCore$D_OUT;
  wire bram_serverAdapterB_outDataCore$CLR,
       bram_serverAdapterB_outDataCore$DEQ,
       bram_serverAdapterB_outDataCore$EMPTY_N,
       bram_serverAdapterB_outDataCore$ENQ,
       bram_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule rv_core
  wire [67 : 0] rv_core$rule_ExternalD_input_fromDMem_data0_data0,
		rv_core$rule_ExternalD_input_fromDMem_data0_data1,
		rv_core$rule_ExternalD_input_toDMem_data0_data0,
		rv_core$rule_ExternalD_input_toDMem_data0_data1,
		rv_core$rule_ExternalD_output_fromDMem_data0_data0,
		rv_core$rule_ExternalD_output_fromDMem_data0_data1,
		rv_core$rule_ExternalD_output_toDMem_data0_data0,
		rv_core$rule_ExternalD_output_toDMem_data0_data1,
		rv_core$rule_ExternalI_input_fromIMem_data0_data0,
		rv_core$rule_ExternalI_input_fromIMem_data0_data1,
		rv_core$rule_ExternalI_input_toIMem_data0_data0,
		rv_core$rule_ExternalI_input_toIMem_data0_data1,
		rv_core$rule_ExternalI_output_fromIMem_data0_data0,
		rv_core$rule_ExternalI_output_fromIMem_data0_data1,
		rv_core$rule_ExternalI_output_toIMem_data0_data0,
		rv_core$rule_ExternalI_output_toIMem_data0_data1;
  wire rv_core$rule_ExternalD_input_fromDMem_data0_read0,
       rv_core$rule_ExternalD_input_fromDMem_data0_read1,
       rv_core$rule_ExternalD_input_fromDMem_data0_write0,
       rv_core$rule_ExternalD_input_fromDMem_data0_write1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_data0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_data1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_read0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_read1,
       rv_core$rule_ExternalD_input_fromDMem_valid0_write0,
       rv_core$rule_ExternalD_input_fromDMem_valid0_write1,
       rv_core$rule_ExternalD_input_toDMem_data0_read0,
       rv_core$rule_ExternalD_input_toDMem_data0_read1,
       rv_core$rule_ExternalD_input_toDMem_data0_write0,
       rv_core$rule_ExternalD_input_toDMem_data0_write1,
       rv_core$rule_ExternalD_input_toDMem_valid0_data0,
       rv_core$rule_ExternalD_input_toDMem_valid0_data1,
       rv_core$rule_ExternalD_input_toDMem_valid0_read0,
       rv_core$rule_ExternalD_input_toDMem_valid0_read1,
       rv_core$rule_ExternalD_input_toDMem_valid0_write0,
       rv_core$rule_ExternalD_input_toDMem_valid0_write1,
       rv_core$rule_ExternalD_output_fromDMem_valid0_data0,
       rv_core$rule_ExternalD_output_fromDMem_valid0_data1,
       rv_core$rule_ExternalD_output_toDMem_valid0_data0,
       rv_core$rule_ExternalD_output_toDMem_valid0_data1,
       rv_core$rule_ExternalI_input_fromIMem_data0_read0,
       rv_core$rule_ExternalI_input_fromIMem_data0_read1,
       rv_core$rule_ExternalI_input_fromIMem_data0_write0,
       rv_core$rule_ExternalI_input_fromIMem_data0_write1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_data0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_data1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_read0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_read1,
       rv_core$rule_ExternalI_input_fromIMem_valid0_write0,
       rv_core$rule_ExternalI_input_fromIMem_valid0_write1,
       rv_core$rule_ExternalI_input_toIMem_data0_read0,
       rv_core$rule_ExternalI_input_toIMem_data0_read1,
       rv_core$rule_ExternalI_input_toIMem_data0_write0,
       rv_core$rule_ExternalI_input_toIMem_data0_write1,
       rv_core$rule_ExternalI_input_toIMem_valid0_data0,
       rv_core$rule_ExternalI_input_toIMem_valid0_data1,
       rv_core$rule_ExternalI_input_toIMem_valid0_read0,
       rv_core$rule_ExternalI_input_toIMem_valid0_read1,
       rv_core$rule_ExternalI_input_toIMem_valid0_write0,
       rv_core$rule_ExternalI_input_toIMem_valid0_write1,
       rv_core$rule_ExternalI_output_fromIMem_valid0_data0,
       rv_core$rule_ExternalI_output_fromIMem_valid0_data1,
       rv_core$rule_ExternalI_output_toIMem_valid0_data0,
       rv_core$rule_ExternalI_output_toIMem_valid0_data1;

  // ports of submodule uart_baudGen_rBaudCounter
  wire [15 : 0] uart_baudGen_rBaudCounter$DATA_A,
		uart_baudGen_rBaudCounter$DATA_B,
		uart_baudGen_rBaudCounter$DATA_C,
		uart_baudGen_rBaudCounter$DATA_F,
		uart_baudGen_rBaudCounter$Q_OUT;
  wire uart_baudGen_rBaudCounter$ADDA,
       uart_baudGen_rBaudCounter$ADDB,
       uart_baudGen_rBaudCounter$SETC,
       uart_baudGen_rBaudCounter$SETF;

  // ports of submodule uart_baudGen_rBaudTickCounter
  wire [2 : 0] uart_baudGen_rBaudTickCounter$DATA_A,
	       uart_baudGen_rBaudTickCounter$DATA_B,
	       uart_baudGen_rBaudTickCounter$DATA_C,
	       uart_baudGen_rBaudTickCounter$DATA_F;
  wire uart_baudGen_rBaudTickCounter$ADDA,
       uart_baudGen_rBaudTickCounter$ADDB,
       uart_baudGen_rBaudTickCounter$SETC,
       uart_baudGen_rBaudTickCounter$SETF;

  // ports of submodule uart_fifoRecv
  wire [7 : 0] uart_fifoRecv$D_IN;
  wire uart_fifoRecv$CLR, uart_fifoRecv$DEQ, uart_fifoRecv$ENQ;

  // ports of submodule uart_fifoXmit
  wire [7 : 0] uart_fifoXmit$D_IN, uart_fifoXmit$D_OUT;
  wire uart_fifoXmit$CLR,
       uart_fifoXmit$DEQ,
       uart_fifoXmit$EMPTY_N,
       uart_fifoXmit$ENQ,
       uart_fifoXmit$FULL_N;

  // rule scheduling signals
  wire WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq,
       WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_requestD,
       WILL_FIRE_RL_requestI,
       WILL_FIRE_RL_responseD,
       WILL_FIRE_RL_responseI,
       WILL_FIRE_RL_uart_receive_find_center_of_bit_cell,
       WILL_FIRE_RL_uart_receive_parity_bit,
       WILL_FIRE_RL_uart_receive_sample_pin,
       WILL_FIRE_RL_uart_receive_stop_first_bit,
       WILL_FIRE_RL_uart_receive_stop_last_bit,
       WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample,
       WILL_FIRE_RL_uart_receive_wait_for_start_bit,
       WILL_FIRE_RL_uart_transmit_buffer_load,
       WILL_FIRE_RL_uart_transmit_buffer_shift,
       WILL_FIRE_RL_uart_transmit_send_parity_bit,
       WILL_FIRE_RL_uart_transmit_send_start_bit,
       WILL_FIRE_RL_uart_transmit_send_stop_bit,
       WILL_FIRE_RL_uart_transmit_send_stop_bit1_5,
       WILL_FIRE_RL_uart_transmit_send_stop_bit2,
       WILL_FIRE_RL_uart_transmit_shift_next_bit,
       WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time,
       WILL_FIRE_RL_uart_transmit_wait_for_start_command;

  // inputs to muxes for submodule ports
  reg [2 : 0] MUX_uart_rRecvState$write_1__VAL_3;
  wire [2 : 0] MUX_uart_rRecvState$write_1__VAL_1,
	       MUX_uart_rRecvState$write_1__VAL_2,
	       MUX_uart_rRecvState$write_1__VAL_4,
	       MUX_uart_rXmitState$write_1__VAL_1,
	       MUX_uart_rXmitState$write_1__VAL_2,
	       MUX_uart_rXmitState$write_1__VAL_3,
	       MUX_uart_rXmitState$write_1__VAL_4,
	       MUX_uart_rXmitState$write_1__VAL_5,
	       MUX_uart_rXmitState$write_1__VAL_6,
	       MUX_uart_rXmitState$write_1__VAL_7;
  wire MUX_uart_rRecvState$write_1__SEL_6,
       MUX_uart_rXmitDataOut$write_1__SEL_1,
       MUX_uart_rXmitDataOut$write_1__SEL_2,
       MUX_uart_rXmitDataOut$write_1__SEL_3;

  // remaining internal signals
  wire [67 : 0] x1__h16618, x1__h17178;
  wire [31 : 0] x__h15478, x__h16460;
  wire [3 : 0] x__h3093, x__h4734, x__h6528, x__h6554;
  wire [2 : 0] bram_serverAdapterA_cnt_79_PLUS_IF_bram_server_ETC___d185,
	       bram_serverAdapterB_cnt_38_PLUS_IF_bram_server_ETC___d244;
  wire [1 : 0] ab__h12023, ab__h13371;
  wire _dor2uart_pwXmitCellCountReset$EN_wset,
       uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29,
       z__h7942,
       z__h7949,
       z__h7956,
       z__h7963,
       z__h7970,
       z__h7977;

  // value method uart_pins_sout
  assign uart_pins_SOUT = uart_rXmitDataOut ;

  // submodule bram_memory
  BRAM2BELoad #(
		.PIPELINED(1'd0),
		.ADDR_WIDTH(32'd14),
		.DATA_WIDTH(32'd32),
		.CHUNKSIZE(32'd8),
		.WE_WIDTH(32'd4),
		.MEMSIZE(15'd16384)) bram_memory(.CLKA(CLK),
					   .CLKB(CLK),
					   .ADDRA(bram_memory$ADDRA),
					   .ADDRB(bram_memory$ADDRB),
					   .DIA(bram_memory$DIA),
					   .DIB(bram_memory$DIB),
					   .WEA(bram_memory$WEA),
					   .WEB(bram_memory$WEB),
					   .ENA(bram_memory$ENA),
					   .ENB(bram_memory$ENB),
					   .DOA(bram_memory$DOA),
					   .DOB(bram_memory$DOB));

  // submodule bram_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterA_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterA_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterA_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterA_outDataCore$DEQ),
							       .CLR(bram_serverAdapterA_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterA_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterA_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterA_outDataCore$EMPTY_N));

  // submodule bram_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) bram_serverAdapterB_outDataCore(.RST(RST_N),
							       .CLK(CLK),
							       .D_IN(bram_serverAdapterB_outDataCore$D_IN),
							       .ENQ(bram_serverAdapterB_outDataCore$ENQ),
							       .DEQ(bram_serverAdapterB_outDataCore$DEQ),
							       .CLR(bram_serverAdapterB_outDataCore$CLR),
							       .D_OUT(bram_serverAdapterB_outDataCore$D_OUT),
							       .FULL_N(bram_serverAdapterB_outDataCore$FULL_N),
							       .EMPTY_N(bram_serverAdapterB_outDataCore$EMPTY_N));

  // submodule rv_core
  rv32 rv_core(.CLK(CLK),
			       .RST_N(RST_N),
			       .rule_ExternalI_input__canfire(32'd1),
			       .rule_ExternalD_input__canfire(32'd1),
			       .rule_ExternalD_input_fromDMem_data0_data0(rv_core$rule_ExternalD_input_fromDMem_data0_data0),
			       .rule_ExternalD_input_fromDMem_data0_data1(rv_core$rule_ExternalD_input_fromDMem_data0_data1),
			       .rule_ExternalD_input_fromDMem_valid0_data0(rv_core$rule_ExternalD_input_fromDMem_valid0_data0),
			       .rule_ExternalD_input_fromDMem_valid0_data1(rv_core$rule_ExternalD_input_fromDMem_valid0_data1),
			       .rule_ExternalD_input_toDMem_data0_data0(rv_core$rule_ExternalD_input_toDMem_data0_data0),
			       .rule_ExternalD_input_toDMem_data0_data1(rv_core$rule_ExternalD_input_toDMem_data0_data1),
			       .rule_ExternalD_input_toDMem_valid0_data0(rv_core$rule_ExternalD_input_toDMem_valid0_data0),
			       .rule_ExternalD_input_toDMem_valid0_data1(rv_core$rule_ExternalD_input_toDMem_valid0_data1),
			       .rule_ExternalI_input_fromIMem_data0_data0(rv_core$rule_ExternalI_input_fromIMem_data0_data0),
			       .rule_ExternalI_input_fromIMem_data0_data1(rv_core$rule_ExternalI_input_fromIMem_data0_data1),
			       .rule_ExternalI_input_fromIMem_valid0_data0(rv_core$rule_ExternalI_input_fromIMem_valid0_data0),
			       .rule_ExternalI_input_fromIMem_valid0_data1(rv_core$rule_ExternalI_input_fromIMem_valid0_data1),
			       .rule_ExternalI_input_toIMem_data0_data0(rv_core$rule_ExternalI_input_toIMem_data0_data0),
			       .rule_ExternalI_input_toIMem_data0_data1(rv_core$rule_ExternalI_input_toIMem_data0_data1),
			       .rule_ExternalI_input_toIMem_valid0_data0(rv_core$rule_ExternalI_input_toIMem_valid0_data0),
			       .rule_ExternalI_input_toIMem_valid0_data1(rv_core$rule_ExternalI_input_toIMem_valid0_data1),
			       .rule_ExternalD_input_fromDMem_data0_read0(rv_core$rule_ExternalD_input_fromDMem_data0_read0),
			       .rule_ExternalD_input_fromDMem_data0_read1(rv_core$rule_ExternalD_input_fromDMem_data0_read1),
			       .rule_ExternalD_input_fromDMem_data0_write0(rv_core$rule_ExternalD_input_fromDMem_data0_write0),
			       .rule_ExternalD_input_fromDMem_data0_write1(rv_core$rule_ExternalD_input_fromDMem_data0_write1),
			       .rule_ExternalD_input_fromDMem_valid0_read0(rv_core$rule_ExternalD_input_fromDMem_valid0_read0),
			       .rule_ExternalD_input_fromDMem_valid0_read1(rv_core$rule_ExternalD_input_fromDMem_valid0_read1),
			       .rule_ExternalD_input_fromDMem_valid0_write0(rv_core$rule_ExternalD_input_fromDMem_valid0_write0),
			       .rule_ExternalD_input_fromDMem_valid0_write1(rv_core$rule_ExternalD_input_fromDMem_valid0_write1),
			       .rule_ExternalD_input_toDMem_data0_read0(rv_core$rule_ExternalD_input_toDMem_data0_read0),
			       .rule_ExternalD_input_toDMem_data0_read1(rv_core$rule_ExternalD_input_toDMem_data0_read1),
			       .rule_ExternalD_input_toDMem_data0_write0(rv_core$rule_ExternalD_input_toDMem_data0_write0),
			       .rule_ExternalD_input_toDMem_data0_write1(rv_core$rule_ExternalD_input_toDMem_data0_write1),
			       .rule_ExternalD_input_toDMem_valid0_read0(rv_core$rule_ExternalD_input_toDMem_valid0_read0),
			       .rule_ExternalD_input_toDMem_valid0_read1(rv_core$rule_ExternalD_input_toDMem_valid0_read1),
			       .rule_ExternalD_input_toDMem_valid0_write0(rv_core$rule_ExternalD_input_toDMem_valid0_write0),
			       .rule_ExternalD_input_toDMem_valid0_write1(rv_core$rule_ExternalD_input_toDMem_valid0_write1),
			       .rule_ExternalI_input_fromIMem_data0_read0(rv_core$rule_ExternalI_input_fromIMem_data0_read0),
			       .rule_ExternalI_input_fromIMem_data0_read1(rv_core$rule_ExternalI_input_fromIMem_data0_read1),
			       .rule_ExternalI_input_fromIMem_data0_write0(rv_core$rule_ExternalI_input_fromIMem_data0_write0),
			       .rule_ExternalI_input_fromIMem_data0_write1(rv_core$rule_ExternalI_input_fromIMem_data0_write1),
			       .rule_ExternalI_input_fromIMem_valid0_read0(rv_core$rule_ExternalI_input_fromIMem_valid0_read0),
			       .rule_ExternalI_input_fromIMem_valid0_read1(rv_core$rule_ExternalI_input_fromIMem_valid0_read1),
			       .rule_ExternalI_input_fromIMem_valid0_write0(rv_core$rule_ExternalI_input_fromIMem_valid0_write0),
			       .rule_ExternalI_input_fromIMem_valid0_write1(rv_core$rule_ExternalI_input_fromIMem_valid0_write1),
			       .rule_ExternalI_input_toIMem_data0_read0(rv_core$rule_ExternalI_input_toIMem_data0_read0),
			       .rule_ExternalI_input_toIMem_data0_read1(rv_core$rule_ExternalI_input_toIMem_data0_read1),
			       .rule_ExternalI_input_toIMem_data0_write0(rv_core$rule_ExternalI_input_toIMem_data0_write0),
			       .rule_ExternalI_input_toIMem_data0_write1(rv_core$rule_ExternalI_input_toIMem_data0_write1),
			       .rule_ExternalI_input_toIMem_valid0_read0(rv_core$rule_ExternalI_input_toIMem_valid0_read0),
			       .rule_ExternalI_input_toIMem_valid0_read1(rv_core$rule_ExternalI_input_toIMem_valid0_read1),
			       .rule_ExternalI_input_toIMem_valid0_write0(rv_core$rule_ExternalI_input_toIMem_valid0_write0),
			       .rule_ExternalI_input_toIMem_valid0_write1(rv_core$rule_ExternalI_input_toIMem_valid0_write1),
			       .rule_ExternalD_output_fromDMem_data0_data0(rv_core$rule_ExternalD_output_fromDMem_data0_data0),
			       .rule_ExternalD_output_fromDMem_data0_data1(rv_core$rule_ExternalD_output_fromDMem_data0_data1),
			       .rule_ExternalD_output_fromDMem_data0_read0(),
			       .rule_ExternalD_output_fromDMem_data0_read1(),
			       .rule_ExternalD_output_fromDMem_data0_write0(),
			       .rule_ExternalD_output_fromDMem_data0_write1(),
			       .rule_ExternalD_output_fromDMem_valid0_data0(rv_core$rule_ExternalD_output_fromDMem_valid0_data0),
			       .rule_ExternalD_output_fromDMem_valid0_data1(rv_core$rule_ExternalD_output_fromDMem_valid0_data1),
			       .rule_ExternalD_output_fromDMem_valid0_read0(),
			       .rule_ExternalD_output_fromDMem_valid0_read1(),
			       .rule_ExternalD_output_fromDMem_valid0_write0(),
			       .rule_ExternalD_output_fromDMem_valid0_write1(),
			       .rule_ExternalD_output_toDMem_data0_data0(rv_core$rule_ExternalD_output_toDMem_data0_data0),
			       .rule_ExternalD_output_toDMem_data0_data1(rv_core$rule_ExternalD_output_toDMem_data0_data1),
			       .rule_ExternalD_output_toDMem_data0_read0(),
			       .rule_ExternalD_output_toDMem_data0_read1(),
			       .rule_ExternalD_output_toDMem_data0_write0(),
			       .rule_ExternalD_output_toDMem_data0_write1(),
			       .rule_ExternalD_output_toDMem_valid0_data0(rv_core$rule_ExternalD_output_toDMem_valid0_data0),
			       .rule_ExternalD_output_toDMem_valid0_data1(rv_core$rule_ExternalD_output_toDMem_valid0_data1),
			       .rule_ExternalD_output_toDMem_valid0_read0(),
			       .rule_ExternalD_output_toDMem_valid0_read1(),
			       .rule_ExternalD_output_toDMem_valid0_write0(),
			       .rule_ExternalD_output_toDMem_valid0_write1(),
			       .rule_ExternalI_output_fromIMem_data0_data0(rv_core$rule_ExternalI_output_fromIMem_data0_data0),
			       .rule_ExternalI_output_fromIMem_data0_data1(rv_core$rule_ExternalI_output_fromIMem_data0_data1),
			       .rule_ExternalI_output_fromIMem_data0_read0(),
			       .rule_ExternalI_output_fromIMem_data0_read1(),
			       .rule_ExternalI_output_fromIMem_data0_write0(),
			       .rule_ExternalI_output_fromIMem_data0_write1(),
			       .rule_ExternalI_output_fromIMem_valid0_data0(rv_core$rule_ExternalI_output_fromIMem_valid0_data0),
			       .rule_ExternalI_output_fromIMem_valid0_data1(rv_core$rule_ExternalI_output_fromIMem_valid0_data1),
			       .rule_ExternalI_output_fromIMem_valid0_read0(),
			       .rule_ExternalI_output_fromIMem_valid0_read1(),
			       .rule_ExternalI_output_fromIMem_valid0_write0(),
			       .rule_ExternalI_output_fromIMem_valid0_write1(),
			       .rule_ExternalI_output_toIMem_data0_data0(rv_core$rule_ExternalI_output_toIMem_data0_data0),
			       .rule_ExternalI_output_toIMem_data0_data1(rv_core$rule_ExternalI_output_toIMem_data0_data1),
			       .rule_ExternalI_output_toIMem_data0_read0(),
			       .rule_ExternalI_output_toIMem_data0_read1(),
			       .rule_ExternalI_output_toIMem_data0_write0(),
			       .rule_ExternalI_output_toIMem_data0_write1(),
			       .rule_ExternalI_output_toIMem_valid0_data0(rv_core$rule_ExternalI_output_toIMem_valid0_data0),
			       .rule_ExternalI_output_toIMem_valid0_data1(rv_core$rule_ExternalI_output_toIMem_valid0_data1),
			       .rule_ExternalI_output_toIMem_valid0_read0(),
			       .rule_ExternalI_output_toIMem_valid0_read1(),
			       .rule_ExternalI_output_toIMem_valid0_write0(),
			       .rule_ExternalI_output_toIMem_valid0_write1());

  // submodule uart_baudGen_rBaudCounter
  Counter #(.width(32'd16), .init(16'd0)) uart_baudGen_rBaudCounter(.CLK(CLK),
								    .RST(RST_N),
								    .DATA_A(uart_baudGen_rBaudCounter$DATA_A),
								    .DATA_B(uart_baudGen_rBaudCounter$DATA_B),
								    .DATA_C(uart_baudGen_rBaudCounter$DATA_C),
								    .DATA_F(uart_baudGen_rBaudCounter$DATA_F),
								    .ADDA(uart_baudGen_rBaudCounter$ADDA),
								    .ADDB(uart_baudGen_rBaudCounter$ADDB),
								    .SETC(uart_baudGen_rBaudCounter$SETC),
								    .SETF(uart_baudGen_rBaudCounter$SETF),
								    .Q_OUT(uart_baudGen_rBaudCounter$Q_OUT));

  // submodule uart_baudGen_rBaudTickCounter
  Counter #(.width(32'd3),
	    .init(3'd0)) uart_baudGen_rBaudTickCounter(.CLK(CLK),
						       .RST(RST_N),
						       .DATA_A(uart_baudGen_rBaudTickCounter$DATA_A),
						       .DATA_B(uart_baudGen_rBaudTickCounter$DATA_B),
						       .DATA_C(uart_baudGen_rBaudTickCounter$DATA_C),
						       .DATA_F(uart_baudGen_rBaudTickCounter$DATA_F),
						       .ADDA(uart_baudGen_rBaudTickCounter$ADDA),
						       .ADDB(uart_baudGen_rBaudTickCounter$ADDB),
						       .SETC(uart_baudGen_rBaudTickCounter$SETC),
						       .SETF(uart_baudGen_rBaudTickCounter$SETF),
						       .Q_OUT());

  // submodule uart_fifoRecv
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) uart_fifoRecv(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(uart_fifoRecv$D_IN),
					     .ENQ(uart_fifoRecv$ENQ),
					     .DEQ(uart_fifoRecv$DEQ),
					     .CLR(uart_fifoRecv$CLR),
					     .D_OUT(),
					     .FULL_N(),
					     .EMPTY_N());

  // submodule uart_fifoXmit
  SizedFIFO #(.p1width(32'd8),
	      .p2depth(32'd16),
	      .p3cntr_width(32'd4),
	      .guarded(32'd1)) uart_fifoXmit(.RST(RST_N),
					     .CLK(CLK),
					     .D_IN(uart_fifoXmit$D_IN),
					     .ENQ(uart_fifoXmit$ENQ),
					     .DEQ(uart_fifoXmit$DEQ),
					     .CLR(uart_fifoXmit$CLR),
					     .D_OUT(uart_fifoXmit$D_OUT),
					     .FULL_N(uart_fifoXmit$FULL_N),
					     .EMPTY_N(uart_fifoXmit$EMPTY_N));

  // rule RL_uart_receive_wait_for_start_bit
  assign WILL_FIRE_RL_uart_receive_wait_for_start_bit =
	     uart_rRecvState == 3'd0 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_find_center_of_bit_cell
  assign WILL_FIRE_RL_uart_receive_find_center_of_bit_cell =
	     uart_rRecvState == 3'd1 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_wait_bit_cell_time_for_sample
  assign WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample =
	     uart_rRecvState == 3'd2 && uart_rRecvCellCount == 4'hF &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_sample_pin
  assign WILL_FIRE_RL_uart_receive_sample_pin =
	     uart_rRecvState == 3'd3 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_parity_bit
  assign WILL_FIRE_RL_uart_receive_parity_bit =
	     uart_rRecvState == 3'd4 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_stop_first_bit
  assign WILL_FIRE_RL_uart_receive_stop_first_bit =
	     uart_rRecvState == 3'd5 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_receive_stop_last_bit
  assign WILL_FIRE_RL_uart_receive_stop_last_bit =
	     uart_rRecvState == 3'd6 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_wait_for_start_command
  assign WILL_FIRE_RL_uart_transmit_wait_for_start_command =
	     uart_rXmitState == 3'd0 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_send_start_bit
  assign WILL_FIRE_RL_uart_transmit_send_start_bit =
	     uart_rXmitState == 3'd1 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_wait_1_bit_cell_time
  assign WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time =
	     uart_rXmitState == 3'd2 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_shift_next_bit
  assign WILL_FIRE_RL_uart_transmit_shift_next_bit =
	     uart_rXmitState == 3'd3 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_buffer_load
  assign WILL_FIRE_RL_uart_transmit_buffer_load =
	     uart_fifoXmit$EMPTY_N && uart_pwXmitLoadBuffer$whas ;

  // rule RL_uart_transmit_buffer_shift
  assign WILL_FIRE_RL_uart_transmit_buffer_shift =
	     !uart_pwXmitLoadBuffer$whas &&
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ;

  // rule RL_uart_transmit_send_parity_bit
  assign WILL_FIRE_RL_uart_transmit_send_parity_bit =
	     uart_rXmitState == 3'd7 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_send_stop_bit
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit =
	     uart_rXmitState == 3'd4 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_send_stop_bit1_5
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 =
	     uart_rXmitState == 3'd5 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_uart_transmit_send_stop_bit2
  assign WILL_FIRE_RL_uart_transmit_send_stop_bit2 =
	     uart_rXmitState == 3'd6 &&
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // rule RL_responseD
  assign WILL_FIRE_RL_responseD =
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ||
	     (bram_serverAdapterA_outDataCore$EMPTY_N ||
	      bram_serverAdapterA_outData_enqData$whas) &&
	     bram_serverAdapterA_outData_outData$whas ;

  // rule RL_requestD
  assign WILL_FIRE_RL_requestD =
	     !rv_core$rule_ExternalD_output_toDMem_valid0_data0 ||
	     (bram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
	     (rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] !=
	      4'hF ||
	      rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] !=
	      32'h40000000 ||
	      uart_fifoXmit$FULL_N) ;

  // rule RL_bram_serverAdapterA_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq =
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;

  // rule RL_responseI
  assign WILL_FIRE_RL_responseI =
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ||
	     (bram_serverAdapterB_outDataCore$EMPTY_N ||
	      bram_serverAdapterB_outData_enqData$whas) &&
	     bram_serverAdapterB_outData_outData$whas ;

  // rule RL_requestI
  assign WILL_FIRE_RL_requestI =
	     !rv_core$rule_ExternalI_output_toIMem_valid0_data0 ||
	     (bram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;

  // rule RL_bram_serverAdapterB_outData_enqAndDeq
  assign WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq =
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;

  // inputs to muxes for submodule ports
  assign MUX_uart_rRecvState$write_1__SEL_6 =
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_1 =
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_2 =
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ;
  assign MUX_uart_rXmitDataOut$write_1__SEL_3 =
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ;
  assign MUX_uart_rRecvState$write_1__VAL_1 = uart_rRecvData ? 3'd0 : 3'd1 ;
  assign MUX_uart_rRecvState$write_1__VAL_2 =
	     (uart_rRecvCellCount == 4'h4) ?
	       (uart_rRecvData ? 3'd0 : 3'd2) :
	       3'd1 ;
  always@(uart_rRecvBitCount)
  begin
    case (uart_rRecvBitCount)
      4'd8, 4'd9, 4'd10: MUX_uart_rRecvState$write_1__VAL_3 = 3'd6;
      default: MUX_uart_rRecvState$write_1__VAL_3 = 3'd3;
    endcase
  end
  assign MUX_uart_rRecvState$write_1__VAL_4 = uart_rRecvData ? 3'd2 : 3'd0 ;
  assign MUX_uart_rXmitState$write_1__VAL_1 =
	     uart_fifoXmit$EMPTY_N ? 3'd1 : 3'd0 ;
  assign MUX_uart_rXmitState$write_1__VAL_2 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd2 : 3'd1 ;
  assign MUX_uart_rXmitState$write_1__VAL_3 =
	     (uart_rXmitCellCount == 4'hF) ?
	       ((uart_rXmitBitCount == 4'd7) ? 3'd4 : 3'd3) :
	       3'd2 ;
  assign MUX_uart_rXmitState$write_1__VAL_4 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd4 : 3'd7 ;
  assign MUX_uart_rXmitState$write_1__VAL_5 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd4 ;
  assign MUX_uart_rXmitState$write_1__VAL_6 =
	     (uart_rXmitCellCount == 4'h7) ? 3'd0 : 3'd5 ;
  assign MUX_uart_rXmitState$write_1__VAL_7 =
	     (uart_rXmitCellCount == 4'hF) ? 3'd0 : 3'd6 ;

  // inlined wires
  assign bram_serverAdapterA_outData_enqData$whas =
	     (!bram_serverAdapterA_s1[0] ||
	      bram_serverAdapterA_outDataCore$FULL_N) &&
	     bram_serverAdapterA_s1[1] &&
	     bram_serverAdapterA_s1[0] ;
  assign bram_serverAdapterA_outData_outData$whas =
	     bram_serverAdapterA_outDataCore$EMPTY_N ||
	     !bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_cnt_1$whas =
	     WILL_FIRE_RL_requestD &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	     (!ab__h12023[1] || ab__h12023[0]) ;
  assign bram_serverAdapterA_writeWithResp$whas =
	     WILL_FIRE_RL_requestD &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 ;
  assign bram_serverAdapterA_s1_1$wget =
	     { 1'd1, !ab__h12023[1] || ab__h12023[0] } ;
  assign bram_serverAdapterB_outData_enqData$whas =
	     (!bram_serverAdapterB_s1[0] ||
	      bram_serverAdapterB_outDataCore$FULL_N) &&
	     bram_serverAdapterB_s1[1] &&
	     bram_serverAdapterB_s1[0] ;
  assign bram_serverAdapterB_outData_outData$whas =
	     bram_serverAdapterB_outDataCore$EMPTY_N ||
	     !bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_cnt_1$whas =
	     WILL_FIRE_RL_requestI &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	     (!ab__h13371[1] || ab__h13371[0]) ;
  assign bram_serverAdapterB_writeWithResp$whas =
	     WILL_FIRE_RL_requestI &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 ;
  assign bram_serverAdapterB_s1_1$wget =
	     { 1'd1, !ab__h13371[1] || ab__h13371[0] } ;
  assign uart_pwRecvCellCountReset$whas =
	     WILL_FIRE_RL_uart_receive_find_center_of_bit_cell &&
	     uart_rRecvCellCount == 4'h4 ||
	     WILL_FIRE_RL_uart_receive_stop_last_bit ||
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ||
	     WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit ;
  assign uart_pwRecvResetBitCount$whas =
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit && uart_rRecvData ;
  assign uart_pwRecvEnableBitCount$whas =
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;
  assign uart_fifoXmit_r_enq$whas =
	     WILL_FIRE_RL_requestD &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] ==
	     4'hF &&
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	     32'h40000000 ;
  assign uart_pwXmitCellCountReset$whas =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
	     uart_fifoXmit$EMPTY_N ||
	     _dor2uart_pwXmitCellCountReset$EN_wset &&
	     uart_rXmitCellCount == 4'hF ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 &&
	     uart_rXmitCellCount == 4'h7 ;
  assign uart_pwXmitEnableBitCount$whas =
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time &&
	     uart_rXmitCellCount == 4'hF &&
	     uart_rXmitBitCount != 4'd7 ;
  assign uart_pwXmitLoadBuffer$whas =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command &&
	     uart_fifoXmit$EMPTY_N ;
  assign bram_serverAdapterA_outData_deqCalled$whas =
	     WILL_FIRE_RL_responseD &&
	     !rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ;
  assign bram_serverAdapterB_outData_deqCalled$whas =
	     WILL_FIRE_RL_responseI &&
	     !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ;

  // register bram_serverAdapterA_cnt
  assign bram_serverAdapterA_cnt$D_IN =
	     bram_serverAdapterA_cnt_79_PLUS_IF_bram_server_ETC___d185 ;
  assign bram_serverAdapterA_cnt$EN =
	     bram_serverAdapterA_cnt_1$whas ||
	     bram_serverAdapterA_outData_deqCalled$whas ;

  // register bram_serverAdapterA_s1
  assign bram_serverAdapterA_s1$D_IN =
	     { bram_serverAdapterA_writeWithResp$whas &&
	       bram_serverAdapterA_s1_1$wget[1],
	       bram_serverAdapterA_s1_1$wget[0] } ;
  assign bram_serverAdapterA_s1$EN = 1'd1 ;

  // register bram_serverAdapterB_cnt
  assign bram_serverAdapterB_cnt$D_IN =
	     bram_serverAdapterB_cnt_38_PLUS_IF_bram_server_ETC___d244 ;
  assign bram_serverAdapterB_cnt$EN =
	     bram_serverAdapterB_cnt_1$whas ||
	     bram_serverAdapterB_outData_deqCalled$whas ;

  // register bram_serverAdapterB_s1
  assign bram_serverAdapterB_s1$D_IN =
	     { bram_serverAdapterB_writeWithResp$whas &&
	       bram_serverAdapterB_s1_1$wget[1],
	       bram_serverAdapterB_s1_1$wget[0] } ;
  assign bram_serverAdapterB_s1$EN = 1'd1 ;

  // register debug
  assign debug$D_IN = 1'b0 ;
  assign debug$EN = 1'b0 ;

  // register dreq
  assign dreq$D_IN = rv_core$rule_ExternalD_output_toDMem_data0_data0 ;
  assign dreq$EN = bram_serverAdapterA_writeWithResp$whas ;

  // register ireq
  assign ireq$D_IN = rv_core$rule_ExternalI_output_toIMem_data0_data0 ;
  assign ireq$EN = bram_serverAdapterB_writeWithResp$whas ;

  // register uart_fifoRecv_countReg
  assign uart_fifoRecv_countReg$D_IN =
	     WILL_FIRE_RL_uart_receive_stop_last_bit ?
	       uart_fifoRecv_countReg + 5'd1 :
	       uart_fifoRecv_countReg - 5'd1 ;
  assign uart_fifoRecv_countReg$EN =
	     WILL_FIRE_RL_uart_receive_stop_last_bit != 1'b0 ;

  // register uart_fifoXmit_countReg
  assign uart_fifoXmit_countReg$D_IN =
	     uart_fifoXmit_r_enq$whas ?
	       uart_fifoXmit_countReg + 5'd1 :
	       uart_fifoXmit_countReg - 5'd1 ;
  assign uart_fifoXmit_countReg$EN =
	     uart_fifoXmit_r_enq$whas !=
	     WILL_FIRE_RL_uart_transmit_buffer_load ;

  // register uart_rRecvBitCount
  assign uart_rRecvBitCount$D_IN =
	     uart_pwRecvResetBitCount$whas ? 4'd0 : x__h4734 ;
  assign uart_rRecvBitCount$EN =
	     uart_pwRecvResetBitCount$whas || uart_pwRecvEnableBitCount$whas ;

  // register uart_rRecvCellCount
  assign uart_rRecvCellCount$D_IN =
	     uart_pwRecvCellCountReset$whas ? 4'd0 : x__h3093 ;
  assign uart_rRecvCellCount$EN =
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // register uart_rRecvData
  assign uart_rRecvData$D_IN = uart_pins_SIN ;
  assign uart_rRecvData$EN = 1'd1 ;

  // register uart_rRecvParity
  assign uart_rRecvParity$D_IN = uart_rRecvData ;
  assign uart_rRecvParity$EN = WILL_FIRE_RL_uart_receive_parity_bit ;

  // register uart_rRecvState
  always@(WILL_FIRE_RL_uart_receive_wait_for_start_bit or
	  MUX_uart_rRecvState$write_1__VAL_1 or
	  WILL_FIRE_RL_uart_receive_find_center_of_bit_cell or
	  MUX_uart_rRecvState$write_1__VAL_2 or
	  WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample or
	  MUX_uart_rRecvState$write_1__VAL_3 or
	  WILL_FIRE_RL_uart_receive_stop_first_bit or
	  MUX_uart_rRecvState$write_1__VAL_4 or
	  WILL_FIRE_RL_uart_receive_stop_last_bit or
	  MUX_uart_rRecvState$write_1__SEL_6)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_uart_receive_wait_for_start_bit:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_1;
      WILL_FIRE_RL_uart_receive_find_center_of_bit_cell:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_2;
      WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_3;
      WILL_FIRE_RL_uart_receive_stop_first_bit:
	  uart_rRecvState$D_IN = MUX_uart_rRecvState$write_1__VAL_4;
      WILL_FIRE_RL_uart_receive_stop_last_bit: uart_rRecvState$D_IN = 3'd0;
      MUX_uart_rRecvState$write_1__SEL_6: uart_rRecvState$D_IN = 3'd2;
      default: uart_rRecvState$D_IN = 3'b010 /* unspecified value */ ;
    endcase
  end
  assign uart_rRecvState$EN =
	     WILL_FIRE_RL_uart_receive_wait_for_start_bit ||
	     WILL_FIRE_RL_uart_receive_find_center_of_bit_cell ||
	     WILL_FIRE_RL_uart_receive_wait_bit_cell_time_for_sample ||
	     WILL_FIRE_RL_uart_receive_stop_first_bit ||
	     WILL_FIRE_RL_uart_receive_stop_last_bit ||
	     WILL_FIRE_RL_uart_receive_parity_bit ||
	     WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_rXmitBitCount
  assign uart_rXmitBitCount$D_IN =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ?
	       4'd0 :
	       x__h6554 ;
  assign uart_rXmitBitCount$EN =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
	     uart_pwXmitEnableBitCount$whas ;

  // register uart_rXmitCellCount
  assign uart_rXmitCellCount$D_IN =
	     uart_pwXmitCellCountReset$whas ? 4'd0 : x__h6528 ;
  assign uart_rXmitCellCount$EN =
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // register uart_rXmitDataOut
  always@(MUX_uart_rXmitDataOut$write_1__SEL_1 or
	  uart_vrXmitBuffer_0 or
	  MUX_uart_rXmitDataOut$write_1__SEL_2 or
	  MUX_uart_rXmitDataOut$write_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_uart_rXmitDataOut$write_1__SEL_1:
	  uart_rXmitDataOut$D_IN = uart_vrXmitBuffer_0;
      MUX_uart_rXmitDataOut$write_1__SEL_2: uart_rXmitDataOut$D_IN = 1'b0;
      MUX_uart_rXmitDataOut$write_1__SEL_3: uart_rXmitDataOut$D_IN = 1'b1;
      default: uart_rXmitDataOut$D_IN = 1'b0 /* unspecified value */ ;
    endcase
  end
  assign uart_rXmitDataOut$EN =
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ;

  // register uart_rXmitParity
  assign uart_rXmitParity$D_IN = z__h7977 ^ uart_fifoXmit$D_OUT[7] ;
  assign uart_rXmitParity$EN = WILL_FIRE_RL_uart_transmit_buffer_load ;

  // register uart_rXmitState
  always@(WILL_FIRE_RL_uart_transmit_wait_for_start_command or
	  MUX_uart_rXmitState$write_1__VAL_1 or
	  WILL_FIRE_RL_uart_transmit_send_start_bit or
	  MUX_uart_rXmitState$write_1__VAL_2 or
	  WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time or
	  MUX_uart_rXmitState$write_1__VAL_3 or
	  WILL_FIRE_RL_uart_transmit_send_parity_bit or
	  MUX_uart_rXmitState$write_1__VAL_4 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit or
	  MUX_uart_rXmitState$write_1__VAL_5 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 or
	  MUX_uart_rXmitState$write_1__VAL_6 or
	  WILL_FIRE_RL_uart_transmit_send_stop_bit2 or
	  MUX_uart_rXmitState$write_1__VAL_7 or
	  WILL_FIRE_RL_uart_transmit_shift_next_bit)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_uart_transmit_wait_for_start_command:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_1;
      WILL_FIRE_RL_uart_transmit_send_start_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_2;
      WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_3;
      WILL_FIRE_RL_uart_transmit_send_parity_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_4;
      WILL_FIRE_RL_uart_transmit_send_stop_bit:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_5;
      WILL_FIRE_RL_uart_transmit_send_stop_bit1_5:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_6;
      WILL_FIRE_RL_uart_transmit_send_stop_bit2:
	  uart_rXmitState$D_IN = MUX_uart_rXmitState$write_1__VAL_7;
      WILL_FIRE_RL_uart_transmit_shift_next_bit: uart_rXmitState$D_IN = 3'd2;
      default: uart_rXmitState$D_IN = 3'b010 /* unspecified value */ ;
    endcase
  end
  assign uart_rXmitState$EN =
	     WILL_FIRE_RL_uart_transmit_wait_for_start_command ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit1_5 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_shift_next_bit ;

  // register uart_vrRecvBuffer_0
  assign uart_vrRecvBuffer_0$D_IN = uart_vrRecvBuffer_1 ;
  assign uart_vrRecvBuffer_0$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_1
  assign uart_vrRecvBuffer_1$D_IN = uart_vrRecvBuffer_2 ;
  assign uart_vrRecvBuffer_1$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_2
  assign uart_vrRecvBuffer_2$D_IN = uart_vrRecvBuffer_3 ;
  assign uart_vrRecvBuffer_2$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_3
  assign uart_vrRecvBuffer_3$D_IN = uart_vrRecvBuffer_4 ;
  assign uart_vrRecvBuffer_3$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_4
  assign uart_vrRecvBuffer_4$D_IN = uart_vrRecvBuffer_5 ;
  assign uart_vrRecvBuffer_4$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_5
  assign uart_vrRecvBuffer_5$D_IN = uart_vrRecvBuffer_6 ;
  assign uart_vrRecvBuffer_5$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_6
  assign uart_vrRecvBuffer_6$D_IN = uart_vrRecvBuffer_7 ;
  assign uart_vrRecvBuffer_6$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrRecvBuffer_7
  assign uart_vrRecvBuffer_7$D_IN = uart_rRecvData ;
  assign uart_vrRecvBuffer_7$EN = WILL_FIRE_RL_uart_receive_sample_pin ;

  // register uart_vrXmitBuffer_0
  assign uart_vrXmitBuffer_0$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[0] :
	       uart_vrXmitBuffer_1 ;
  assign uart_vrXmitBuffer_0$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_1
  assign uart_vrXmitBuffer_1$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[1] :
	       uart_vrXmitBuffer_2 ;
  assign uart_vrXmitBuffer_1$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_2
  assign uart_vrXmitBuffer_2$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[2] :
	       uart_vrXmitBuffer_3 ;
  assign uart_vrXmitBuffer_2$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_3
  assign uart_vrXmitBuffer_3$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[3] :
	       uart_vrXmitBuffer_4 ;
  assign uart_vrXmitBuffer_3$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_4
  assign uart_vrXmitBuffer_4$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[4] :
	       uart_vrXmitBuffer_5 ;
  assign uart_vrXmitBuffer_4$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_5
  assign uart_vrXmitBuffer_5$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[5] :
	       uart_vrXmitBuffer_6 ;
  assign uart_vrXmitBuffer_5$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_6
  assign uart_vrXmitBuffer_6$D_IN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ?
	       uart_fifoXmit$D_OUT[6] :
	       uart_vrXmitBuffer_7 ;
  assign uart_vrXmitBuffer_6$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // register uart_vrXmitBuffer_7
  assign uart_vrXmitBuffer_7$D_IN =
	     !WILL_FIRE_RL_uart_transmit_buffer_load ||
	     uart_fifoXmit$D_OUT[7] ;
  assign uart_vrXmitBuffer_7$EN =
	     WILL_FIRE_RL_uart_transmit_buffer_load ||
	     WILL_FIRE_RL_uart_transmit_buffer_shift ;

  // submodule bram_memory
  assign bram_memory$ADDRA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[47:34] ;
  assign bram_memory$ADDRB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[47:34] ;
  assign bram_memory$DIA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] ;
  assign bram_memory$DIB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[31:0] ;
  assign bram_memory$WEA =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] ;
  assign bram_memory$WEB =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64] ;
  assign bram_memory$ENA = bram_serverAdapterA_writeWithResp$whas ;
  assign bram_memory$ENB = bram_serverAdapterB_writeWithResp$whas ;

  // submodule bram_serverAdapterA_outDataCore
  assign bram_serverAdapterA_outDataCore$D_IN = bram_memory$DOA ;
  assign bram_serverAdapterA_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$FULL_N &&
	     !bram_serverAdapterA_outData_deqCalled$whas &&
	     bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterA_outData_enqAndDeq ||
	     bram_serverAdapterA_outDataCore$EMPTY_N &&
	     bram_serverAdapterA_outData_deqCalled$whas &&
	     !bram_serverAdapterA_outData_enqData$whas ;
  assign bram_serverAdapterA_outDataCore$CLR = 1'b0 ;

  // submodule bram_serverAdapterB_outDataCore
  assign bram_serverAdapterB_outDataCore$D_IN = bram_memory$DOB ;
  assign bram_serverAdapterB_outDataCore$ENQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$FULL_N &&
	     !bram_serverAdapterB_outData_deqCalled$whas &&
	     bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$DEQ =
	     WILL_FIRE_RL_bram_serverAdapterB_outData_enqAndDeq ||
	     bram_serverAdapterB_outDataCore$EMPTY_N &&
	     bram_serverAdapterB_outData_deqCalled$whas &&
	     !bram_serverAdapterB_outData_enqData$whas ;
  assign bram_serverAdapterB_outDataCore$CLR = 1'b0 ;

  // submodule rv_core
  assign rv_core$rule_ExternalD_input_fromDMem_data0_data0 =
	     bram_serverAdapterA_outData_deqCalled$whas ?
	       x1__h17178 :
	       rv_core$rule_ExternalD_output_fromDMem_data0_data0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_data1 =
	     rv_core$rule_ExternalD_output_fromDMem_data0_data1 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_data0 =
	     bram_serverAdapterA_outData_deqCalled$whas ||
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_data1 =
	     rv_core$rule_ExternalD_output_fromDMem_valid0_data1 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_data0 =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_data1 =
	     rv_core$rule_ExternalD_output_toDMem_data0_data1 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_data0 =
	     !bram_serverAdapterA_writeWithResp$whas &&
	     rv_core$rule_ExternalD_output_toDMem_valid0_data0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_data1 =
	     rv_core$rule_ExternalD_output_toDMem_valid0_data1 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_data0 =
	     bram_serverAdapterB_outData_deqCalled$whas ?
	       x1__h16618 :
	       rv_core$rule_ExternalI_output_fromIMem_data0_data0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_data1 =
	     rv_core$rule_ExternalI_output_fromIMem_data0_data1 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_data0 =
	     bram_serverAdapterB_outData_deqCalled$whas ||
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_data1 =
	     rv_core$rule_ExternalI_output_fromIMem_valid0_data1 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_data0 =
	     rv_core$rule_ExternalI_output_toIMem_data0_data0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_data1 =
	     rv_core$rule_ExternalI_output_toIMem_data0_data1 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_data0 =
	     !bram_serverAdapterB_writeWithResp$whas &&
	     rv_core$rule_ExternalI_output_toIMem_valid0_data0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_data1 =
	     rv_core$rule_ExternalI_output_toIMem_valid0_data1 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_fromDMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalD_input_toDMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_fromIMem_valid0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_data0_write1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_read0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_read1 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_write0 = 1'b0 ;
  assign rv_core$rule_ExternalI_input_toIMem_valid0_write1 = 1'b0 ;

  // submodule uart_baudGen_rBaudCounter
  assign uart_baudGen_rBaudCounter$DATA_A = 16'd1 ;
  assign uart_baudGen_rBaudCounter$DATA_B = 16'h0 ;
  assign uart_baudGen_rBaudCounter$DATA_C = 16'h0 ;
  assign uart_baudGen_rBaudCounter$DATA_F = 16'd0 ;
  assign uart_baudGen_rBaudCounter$ADDA =
	     uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;
  assign uart_baudGen_rBaudCounter$ADDB = 1'b0 ;
  assign uart_baudGen_rBaudCounter$SETC = 1'b0 ;
  assign uart_baudGen_rBaudCounter$SETF =
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;

  // submodule uart_baudGen_rBaudTickCounter
  assign uart_baudGen_rBaudTickCounter$DATA_A = 3'd1 ;
  assign uart_baudGen_rBaudTickCounter$DATA_B = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$DATA_C = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$DATA_F = 3'h0 ;
  assign uart_baudGen_rBaudTickCounter$ADDA =
	     !uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 ;
  assign uart_baudGen_rBaudTickCounter$ADDB = 1'b0 ;
  assign uart_baudGen_rBaudTickCounter$SETC = 1'b0 ;
  assign uart_baudGen_rBaudTickCounter$SETF = 1'b0 ;

  // submodule uart_fifoRecv
  assign uart_fifoRecv$D_IN =
	     { uart_vrRecvBuffer_7,
	       uart_vrRecvBuffer_6,
	       uart_vrRecvBuffer_5,
	       uart_vrRecvBuffer_4,
	       uart_vrRecvBuffer_3,
	       uart_vrRecvBuffer_2,
	       uart_vrRecvBuffer_1,
	       uart_vrRecvBuffer_0 } ;
  assign uart_fifoRecv$ENQ = WILL_FIRE_RL_uart_receive_stop_last_bit ;
  assign uart_fifoRecv$DEQ = 1'b0 ;
  assign uart_fifoRecv$CLR = 1'b0 ;

  // submodule uart_fifoXmit
  assign uart_fifoXmit$D_IN =
	     rv_core$rule_ExternalD_output_toDMem_data0_data0[7:0] ;
  assign uart_fifoXmit$ENQ = uart_fifoXmit_r_enq$whas ;
  assign uart_fifoXmit$DEQ = WILL_FIRE_RL_uart_transmit_buffer_load ;
  assign uart_fifoXmit$CLR = 1'b0 ;

  // remaining internal signals
  assign _dor2uart_pwXmitCellCountReset$EN_wset =
	     WILL_FIRE_RL_uart_transmit_send_stop_bit2 ||
	     WILL_FIRE_RL_uart_transmit_send_stop_bit ||
	     WILL_FIRE_RL_uart_transmit_send_parity_bit ||
	     WILL_FIRE_RL_uart_transmit_wait_1_bit_cell_time ||
	     WILL_FIRE_RL_uart_transmit_send_start_bit ;
  assign ab__h12023 =
	     { rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] !=
	       4'd0,
	       1'd1 } ;
  assign ab__h13371 =
	     { rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64] !=
	       4'd0,
	       1'd1 } ;
  assign bram_serverAdapterA_cnt_79_PLUS_IF_bram_server_ETC___d185 =
	     bram_serverAdapterA_cnt +
	     (bram_serverAdapterA_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign bram_serverAdapterB_cnt_38_PLUS_IF_bram_server_ETC___d244 =
	     bram_serverAdapterB_cnt +
	     (bram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
	     (bram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign uart_baudGen_rBaudCounter_value_PLUS_1_8_ULT_54___d29 =
	     uart_baudGen_rBaudCounter$Q_OUT + 16'd1 < 16'd54 ;
  assign x1__h16618 = { ireq[67:32], x__h15478 } ;
  assign x1__h17178 = { dreq[67:32], x__h16460 } ;
  assign x__h15478 =
	     bram_serverAdapterB_outDataCore$EMPTY_N ?
	       bram_serverAdapterB_outDataCore$D_OUT :
	       bram_memory$DOB ;
  assign x__h16460 =
	     bram_serverAdapterA_outDataCore$EMPTY_N ?
	       bram_serverAdapterA_outDataCore$D_OUT :
	       bram_memory$DOA ;
  assign x__h3093 = uart_rRecvCellCount + 4'd1 ;
  assign x__h4734 = uart_rRecvBitCount + 4'd1 ;
  assign x__h6528 = uart_rXmitCellCount + 4'd1 ;
  assign x__h6554 = uart_rXmitBitCount + 4'd1 ;
  assign z__h7942 = uart_fifoXmit$D_OUT[0] ^ uart_fifoXmit$D_OUT[1] ;
  assign z__h7949 = z__h7942 ^ uart_fifoXmit$D_OUT[2] ;
  assign z__h7956 = z__h7949 ^ uart_fifoXmit$D_OUT[3] ;
  assign z__h7963 = z__h7956 ^ uart_fifoXmit$D_OUT[4] ;
  assign z__h7970 = z__h7963 ^ uart_fifoXmit$D_OUT[5] ;
  assign z__h7977 = z__h7970 ^ uart_fifoXmit$D_OUT[6] ;

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	debug <= `BSV_ASSIGNMENT_DELAY 1'd0;
	uart_fifoRecv_countReg <= `BSV_ASSIGNMENT_DELAY 5'd0;
	uart_fifoXmit_countReg <= `BSV_ASSIGNMENT_DELAY 5'd0;
	uart_rRecvData <= `BSV_ASSIGNMENT_DELAY 1'd1;
      end
    else
      begin
        if (bram_serverAdapterA_cnt$EN)
	  bram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_cnt$D_IN;
	if (bram_serverAdapterA_s1$EN)
	  bram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterA_s1$D_IN;
	if (bram_serverAdapterB_cnt$EN)
	  bram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_cnt$D_IN;
	if (bram_serverAdapterB_s1$EN)
	  bram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
	      bram_serverAdapterB_s1$D_IN;
	if (debug$EN) debug <= `BSV_ASSIGNMENT_DELAY debug$D_IN;
	if (uart_fifoRecv_countReg$EN)
	  uart_fifoRecv_countReg <= `BSV_ASSIGNMENT_DELAY
	      uart_fifoRecv_countReg$D_IN;
	if (uart_fifoXmit_countReg$EN)
	  uart_fifoXmit_countReg <= `BSV_ASSIGNMENT_DELAY
	      uart_fifoXmit_countReg$D_IN;
	if (uart_rRecvData$EN)
	  uart_rRecvData <= `BSV_ASSIGNMENT_DELAY uart_rRecvData$D_IN;
      end
    if (dreq$EN) dreq <= `BSV_ASSIGNMENT_DELAY dreq$D_IN;
    if (ireq$EN) ireq <= `BSV_ASSIGNMENT_DELAY ireq$D_IN;
    if (uart_vrRecvBuffer_0$EN)
      uart_vrRecvBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_0$D_IN;
    if (uart_vrRecvBuffer_1$EN)
      uart_vrRecvBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_1$D_IN;
    if (uart_vrRecvBuffer_2$EN)
      uart_vrRecvBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_2$D_IN;
    if (uart_vrRecvBuffer_3$EN)
      uart_vrRecvBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_3$D_IN;
    if (uart_vrRecvBuffer_4$EN)
      uart_vrRecvBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_4$D_IN;
    if (uart_vrRecvBuffer_5$EN)
      uart_vrRecvBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_5$D_IN;
    if (uart_vrRecvBuffer_6$EN)
      uart_vrRecvBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_6$D_IN;
    if (uart_vrRecvBuffer_7$EN)
      uart_vrRecvBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrRecvBuffer_7$D_IN;
    if (uart_vrXmitBuffer_0$EN)
      uart_vrXmitBuffer_0 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_0$D_IN;
    if (uart_vrXmitBuffer_1$EN)
      uart_vrXmitBuffer_1 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_1$D_IN;
    if (uart_vrXmitBuffer_2$EN)
      uart_vrXmitBuffer_2 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_2$D_IN;
    if (uart_vrXmitBuffer_3$EN)
      uart_vrXmitBuffer_3 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_3$D_IN;
    if (uart_vrXmitBuffer_4$EN)
      uart_vrXmitBuffer_4 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_4$D_IN;
    if (uart_vrXmitBuffer_5$EN)
      uart_vrXmitBuffer_5 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_5$D_IN;
    if (uart_vrXmitBuffer_6$EN)
      uart_vrXmitBuffer_6 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_6$D_IN;
    if (uart_vrXmitBuffer_7$EN)
      uart_vrXmitBuffer_7 <= `BSV_ASSIGNMENT_DELAY uart_vrXmitBuffer_7$D_IN;
  end

  always@(posedge CLK or `BSV_RESET_EDGE RST_N)
  if (RST_N == `BSV_RESET_VALUE)
    begin
      uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rRecvParity <= `BSV_ASSIGNMENT_DELAY 1'd0;
      uart_rRecvState <= `BSV_ASSIGNMENT_DELAY 3'd0;
      uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
      uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY 1'd1;
      uart_rXmitParity <= `BSV_ASSIGNMENT_DELAY 1'd0;
      uart_rXmitState <= `BSV_ASSIGNMENT_DELAY 3'd0;
    end
  else
    begin
      if (uart_rRecvBitCount$EN)
	uart_rRecvBitCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvBitCount$D_IN;
      if (uart_rRecvCellCount$EN)
	uart_rRecvCellCount <= `BSV_ASSIGNMENT_DELAY uart_rRecvCellCount$D_IN;
      if (uart_rRecvParity$EN)
	uart_rRecvParity <= `BSV_ASSIGNMENT_DELAY uart_rRecvParity$D_IN;
      if (uart_rRecvState$EN)
	uart_rRecvState <= `BSV_ASSIGNMENT_DELAY uart_rRecvState$D_IN;
      if (uart_rXmitBitCount$EN)
	uart_rXmitBitCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitBitCount$D_IN;
      if (uart_rXmitCellCount$EN)
	uart_rXmitCellCount <= `BSV_ASSIGNMENT_DELAY uart_rXmitCellCount$D_IN;
      if (uart_rXmitDataOut$EN)
	uart_rXmitDataOut <= `BSV_ASSIGNMENT_DELAY uart_rXmitDataOut$D_IN;
      if (uart_rXmitParity$EN)
	uart_rXmitParity <= `BSV_ASSIGNMENT_DELAY uart_rXmitParity$D_IN;
      if (uart_rXmitState$EN)
	uart_rXmitState <= `BSV_ASSIGNMENT_DELAY uart_rXmitState$D_IN;
    end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    bram_serverAdapterA_cnt = 3'h2;
    bram_serverAdapterA_s1 = 2'h2;
    bram_serverAdapterB_cnt = 3'h2;
    bram_serverAdapterB_s1 = 2'h2;
    debug = 1'h0;
    dreq = 68'hAAAAAAAAAAAAAAAAA;
    ireq = 68'hAAAAAAAAAAAAAAAAA;
    uart_fifoRecv_countReg = 5'h0A;
    uart_fifoXmit_countReg = 5'h0A;
    uart_rRecvBitCount = 4'hA;
    uart_rRecvCellCount = 4'hA;
    uart_rRecvData = 1'h0;
    uart_rRecvParity = 1'h0;
    uart_rRecvState = 3'h2;
    uart_rXmitBitCount = 4'hA;
    uart_rXmitCellCount = 4'hA;
    uart_rXmitDataOut = 1'h0;
    uart_rXmitParity = 1'h0;
    uart_rXmitState = 3'h2;
    uart_vrRecvBuffer_0 = 1'h0;
    uart_vrRecvBuffer_1 = 1'h0;
    uart_vrRecvBuffer_2 = 1'h0;
    uart_vrRecvBuffer_3 = 1'h0;
    uart_vrRecvBuffer_4 = 1'h0;
    uart_vrRecvBuffer_5 = 1'h0;
    uart_vrRecvBuffer_6 = 1'h0;
    uart_vrRecvBuffer_7 = 1'h0;
    uart_vrXmitBuffer_0 = 1'h0;
    uart_vrXmitBuffer_1 = 1'h0;
    uart_vrXmitBuffer_2 = 1'h0;
    uart_vrXmitBuffer_3 = 1'h0;
    uart_vrXmitBuffer_4 = 1'h0;
    uart_vrXmitBuffer_5 = 1'h0;
    uart_vrXmitBuffer_6 = 1'h0;
    uart_vrXmitBuffer_7 = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterA_s1[1] &&
	  !bram_serverAdapterA_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000000)
	$fwrite(32'h80000002,
		"%c",
		rv_core$rule_ExternalD_output_toDMem_data0_data0[7:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000004)
	$fwrite(32'h80000002,
		"%0d",
		rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40000004)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] == 32'd0)
	$fdisplay(32'h80000002, "  \033[0;32mPASS\033[0m");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0] != 32'd0)
	$fdisplay(32'h80000002,
		  "  \033[0;31mFAIL\033[0m %0d",
		  rv_core$rule_ExternalD_output_toDMem_data0_data0[31:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000)
	$fflush(32'h80000002);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestD &&
	  rv_core$rule_ExternalD_output_toDMem_valid0_data0 &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[67:64] == 4'hF &&
	  rv_core$rule_ExternalD_output_toDMem_data0_data0[63:32] ==
	  32'h40001000)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (bram_serverAdapterB_s1[1] &&
	  !bram_serverAdapterB_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("Communicating a response:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("Mem { ", "byte_en: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[67:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[63:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", ireq[31:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("'h%h", x__h15478);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_responseI &&
	  !rv_core$rule_ExternalI_output_fromIMem_valid0_data0 &&
	  debug)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("Got request from core:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("Mem { ", "byte_en: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[67:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write(", ", "addr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[63:32]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write(", ", "data: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("'h%h",
	       rv_core$rule_ExternalI_output_toIMem_data0_data0[31:0],
	       " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_requestI &&
	  rv_core$rule_ExternalI_output_toIMem_valid0_data0 &&
	  debug)
	$write("\n");
  end
  // synopsys translate_on
endmodule  // top_fpga

