#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:03:12 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Mon Dec 24 20:24:01 2018
# Process ID: 40840
# Current directory: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1
# Command line: vivado.exe -log clk_wiz_for_cpu.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_for_cpu.tcl
# Log file: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/clk_wiz_for_cpu.vds
# Journal file: D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1\vivado.jou
#-----------------------------------------------------------
source clk_wiz_for_cpu.tcl -notrace
Command: synth_design -top clk_wiz_for_cpu -part xc7a100tcsg324-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 54368 
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Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 385.379 ; gain = 97.914
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INFO: [Synth 8-6157] synthesizing module 'clk_wiz_for_cpu' [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.v:70]
INFO: [Synth 8-6157] synthesizing module 'clk_wiz_for_cpu_clk_wiz' [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_clk_wiz.v:68]
INFO: [Synth 8-6157] synthesizing module 'IBUF' [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
	Parameter IOSTANDARD bound to: DEFAULT - type: string 
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (1#1) [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:19473]
INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 15.625000 - type: float 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
	Parameter CLKOUT0_DIVIDE_F bound to: 78.125000 - type: float 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
	Parameter COMPENSATION bound to: ZHOLD - type: string 
	Parameter DIVCLK_DIVIDE bound to: 2 - type: integer 
	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
	Parameter IS_PSEN_INVERTED bound to: 1'b0 
	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
	Parameter IS_RST_INVERTED bound to: 1'b0 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter REF_JITTER2 bound to: 0.010000 - type: float 
	Parameter SS_EN bound to: FALSE - type: string 
	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
	Parameter STARTUP_WAIT bound to: FALSE - type: string 
INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (2#1) [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:25762]
INFO: [Synth 8-6157] synthesizing module 'BUFG' [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (3#1) [D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v:609]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_for_cpu_clk_wiz' (4#1) [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_clk_wiz.v:68]
INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_for_cpu' (5#1) [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.v:70]
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Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
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Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
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INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_ooc.xdc] for cell 'inst'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_ooc.xdc] for cell 'inst'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc] for cell 'inst'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc] for cell 'inst'
Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc] for cell 'inst'
Finished Parsing XDC File [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc] for cell 'inst'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_for_cpu_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_for_cpu_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Parsing XDC File [D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 699.977 ; gain = 0.000
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Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
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Start Loading Part and Timing Information
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Loading part: xc7a100tcsg324-1
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
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Start Applying 'set_property' XDC Constraints
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Applied set_property DONT_TOUCH = true for inst. (constraint file  D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/dont_touch.xdc, line 9).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start RTL Component Statistics 
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Detailed RTL Component Info : 
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Finished RTL Component Statistics 
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Start RTL Hierarchical Component Statistics 
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Hierarchical RTL Component report 
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Finished RTL Hierarchical Component Statistics
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Start Part Resource Summary
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Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
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Finished Part Resource Summary
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Start Cross Boundary and Area Optimization
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Warning: Parallel synthesis criteria is not met 
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Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 699.977 ; gain = 412.512
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
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Start Timing Optimization
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Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
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Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
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Finished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
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Start Renaming Generated Instances
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Finished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
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Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Start Renaming Generated Ports
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Finished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Start Writing Synthesis Report
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Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-----------+------+
|      |Cell       |Count |
+------+-----------+------+
|1     |BUFG       |     2|
|2     |MMCME2_ADV |     1|
|3     |IBUF       |     1|
+------+-----------+------+

Report Instance Areas: 
+------+---------+------------------------+------+
|      |Instance |Module                  |Cells |
+------+---------+------------------------+------+
|1     |top      |                        |     4|
|2     |  inst   |clk_wiz_for_cpu_clk_wiz |     4|
+------+---------+------------------------+------+
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Finished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
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Synthesis finished with 0 errors, 0 critical warnings and 0 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 754.410 ; gain = 207.582
Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

INFO: [Common 17-83] Releasing license: Synthesis
25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:37 . Memory (MB): peak = 773.555 ; gain = 497.559
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint 'D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/clk_wiz_for_cpu.dcp' has been generated.
INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xci
WARNING: [Constraints 18-5210] No constraint will be written out.
INFO: [Common 17-1381] The checkpoint 'D:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/clk_wiz_for_cpu.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_for_cpu_utilization_synth.rpt -pb clk_wiz_for_cpu_utilization_synth.pb
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 777.934 ; gain = 0.000
INFO: [Common 17-206] Exiting Vivado at Mon Dec 24 20:24:45 2018...
