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// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 12

// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
cache your_instance_name (
  .a(a),      // input wire [8 : 0] a
  .d(d),      // input wire [31 : 0] d
  .clk(clk),  // input wire clk
  .we(we),    // input wire we
  .spo(spo)  // output wire [31 : 0] spo
);
// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file cache.v when simulating
// the core, cache. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

