
í
Command: %s
53*	vivadotcl2a
Msynth_design -top clk_wiz_for_cpu -part xc7a100tcsg324-1 -mode out_of_context2default:defaultZ4-113hpxê
:
Starting synth_design
149*	vivadotclZ4-321hpxê
ü
@Attempting to get a license for feature '%s' and/or device '%s'
308*common2
	Synthesis2default:default2
xc7a100t2default:defaultZ17-347hpxê
è
0Got license for feature '%s' and/or device '%s'
310*common2
	Synthesis2default:default2
xc7a100t2default:defaultZ17-349hpxê
§
%s*synth2ã
wStarting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 385.379 ; gain = 97.914
2default:defaulthpxê
»
synthesizing module '%s'%s4497*oasys2#
clk_wiz_for_cpu2default:default2
2default:default2∞
ôd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.v2default:default2
702default:default8@Z8-6157hpxê
ÿ
synthesizing module '%s'%s4497*oasys2+
clk_wiz_for_cpu_clk_wiz2default:default2
2default:default2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_clk_wiz.v2default:default2
682default:default8@Z8-6157hpxê
⁄
synthesizing module '%s'%s4497*oasys2
IBUF2default:default2
2default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
194732default:default8@Z8-6157hpxê
g
%s
*synth2O
;	Parameter CAPACITANCE bound to: DONT_CARE - type: string 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter IBUF_DELAY_VALUE bound to: 0 - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter IBUF_LOW_PWR bound to: TRUE - type: string 
2default:defaulthp
x
ê
f
%s
*synth2N
:	Parameter IFD_DELAY_VALUE bound to: AUTO - type: string 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter IOSTANDARD bound to: DEFAULT - type: string 
2default:defaulthp
x
ê
ï
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
IBUF2default:default2
2default:default2
12default:default2
12default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
194732default:default8@Z8-6155hpxê
‡
synthesizing module '%s'%s4497*oasys2

MMCME2_ADV2default:default2
2default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
257622default:default8@Z8-6157hpxê
e
%s
*synth2M
9	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
2default:defaulthp
x
ê
j
%s
*synth2R
>	Parameter CLKFBOUT_MULT_F bound to: 15.625000 - type: float 
2default:defaulthp
x
ê
h
%s
*synth2P
<	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
h
%s
*synth2P
<	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKIN2_PERIOD bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT0_DIVIDE_F bound to: 78.125000 - type: float 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT1_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT2_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT3_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT4_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT5_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
c
%s
*synth2K
7	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
2default:defaulthp
x
ê
l
%s
*synth2T
@	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
2default:defaulthp
x
ê
g
%s
*synth2O
;	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
2default:defaulthp
x
ê
k
%s
*synth2S
?	Parameter CLKOUT6_USE_FINE_PS bound to: FALSE - type: string 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter COMPENSATION bound to: ZHOLD - type: string 
2default:defaulthp
x
ê
b
%s
*synth2J
6	Parameter DIVCLK_DIVIDE bound to: 2 - type: integer 
2default:defaulthp
x
ê
\
%s
*synth2D
0	Parameter IS_CLKINSEL_INVERTED bound to: 1'b0 
2default:defaulthp
x
ê
X
%s
*synth2@
,	Parameter IS_PSEN_INVERTED bound to: 1'b0 
2default:defaulthp
x
ê
\
%s
*synth2D
0	Parameter IS_PSINCDEC_INVERTED bound to: 1'b0 
2default:defaulthp
x
ê
Z
%s
*synth2B
.	Parameter IS_PWRDWN_INVERTED bound to: 1'b0 
2default:defaulthp
x
ê
W
%s
*synth2?
+	Parameter IS_RST_INVERTED bound to: 1'b0 
2default:defaulthp
x
ê
e
%s
*synth2M
9	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
2default:defaulthp
x
ê
e
%s
*synth2M
9	Parameter REF_JITTER2 bound to: 0.010000 - type: float 
2default:defaulthp
x
ê
]
%s
*synth2E
1	Parameter SS_EN bound to: FALSE - type: string 
2default:defaulthp
x
ê
e
%s
*synth2M
9	Parameter SS_MODE bound to: CENTER_HIGH - type: string 
2default:defaulthp
x
ê
f
%s
*synth2N
:	Parameter SS_MOD_PERIOD bound to: 10000 - type: integer 
2default:defaulthp
x
ê
d
%s
*synth2L
8	Parameter STARTUP_WAIT bound to: FALSE - type: string 
2default:defaulthp
x
ê
õ
'done synthesizing module '%s'%s (%s#%s)4495*oasys2

MMCME2_ADV2default:default2
2default:default2
22default:default2
12default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
257622default:default8@Z8-6155hpxê
ÿ
synthesizing module '%s'%s4497*oasys2
BUFG2default:default2
2default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
6092default:default8@Z8-6157hpxê
ì
'done synthesizing module '%s'%s (%s#%s)4495*oasys2
BUFG2default:default2
2default:default2
32default:default2
12default:default2K
5D:/Xilinx/Vivado/2018.2/scripts/rt/data/unisim_comp.v2default:default2
6092default:default8@Z8-6155hpxê
ì
'done synthesizing module '%s'%s (%s#%s)4495*oasys2+
clk_wiz_for_cpu_clk_wiz2default:default2
2default:default2
42default:default2
12default:default2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_clk_wiz.v2default:default2
682default:default8@Z8-6155hpxê
É
'done synthesizing module '%s'%s (%s#%s)4495*oasys2#
clk_wiz_for_cpu2default:default2
2default:default2
52default:default2
12default:default2∞
ôd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.v2default:default2
702default:default8@Z8-6155hpxê
•
%s*synth2å
xFinished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
2default:defaulthpxê
D
%s
*synth2,

Report Check Netlist: 
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
u
%s
*synth2]
I|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
2default:defaulthp
x
ê
u
%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
M
%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
±
%s*synth2ò
ÉFinished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Ø
%s*synth2ñ
ÅFinished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 440.613 ; gain = 153.148
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
e
-Analyzing %s Unisim elements for replacement
17*netlist2
22default:defaultZ29-17hpxê
j
2Unisim Transformation completed in %s CPU seconds
28*netlist2
02default:defaultZ29-28hpxê
W
Loading part %s157*device2$
xc7a100tcsg324-12default:defaultZ21-403hpxê
K
)Preparing netlist for logic optimization
349*projectZ1-570hpxê
>

Processing XDC Constraints
244*projectZ1-262hpxê
=
Initializing timing engine
348*projectZ1-569hpxê
¢
$Parsing XDC File [%s] for cell '%s'
848*designutils2∂
üd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_ooc.xdc2default:default2
inst	2default:default8Z20-848hpxê
´
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2∂
üd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_ooc.xdc2default:default2
inst	2default:default8Z20-847hpxê
§
$Parsing XDC File [%s] for cell '%s'
848*designutils2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc2default:default2
inst	2default:default8Z20-848hpxê
≠
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2∏
°d:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu_board.xdc2default:default2
inst	2default:default8Z20-847hpxê
û
$Parsing XDC File [%s] for cell '%s'
848*designutils2≤
õd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc2default:default2
inst	2default:default8Z20-848hpxê
ß
-Finished Parsing XDC File [%s] for cell '%s'
847*designutils2≤
õd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc2default:default2
inst	2default:default8Z20-847hpxê
Ê
ŸImplementation specific constraints were found while reading constraint file [%s]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [%s].
233*project2∞
õd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xdc2default:default25
!.Xil/clk_wiz_for_cpu_propImpl.xdc2default:defaultZ1-236hpxê
8
Deriving generated clocks
2*timingZ38-2hpxê
Í
Parsing XDC File [%s]
179*designutils2®
ëD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/dont_touch.xdc2default:default8Z20-179hpxê
Û
Finished Parsing XDC File [%s]
178*designutils2®
ëD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/dont_touch.xdc2default:default8Z20-178hpxê
H
&Completed Processing XDC Constraints

245*projectZ1-263hpxê
~
!Unisim Transformation Summary:
%s111*project29
%No Unisim elements were transformed.
2default:defaultZ1-111hpxê
ô
I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common24
 Constraint Validation Runtime : 2default:default2
00:00:002default:default2 
00:00:00.0352default:default2
699.9772default:default2
0.0002default:defaultZ17-268hpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
´
%s*synth2í
~Finished Constraint Validation : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
V
%s
*synth2>
*Start Loading Part and Timing Information
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Loading part: xc7a100tcsg324-1
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
∫
%s*synth2°
åFinished Loading Part and Timing Information : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Z
%s
*synth2B
.Start Applying 'set_property' XDC Constraints
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
æ
%s*synth2•
êFinished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Ø
%s*synth2ñ
ÅFinished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 699.977 ; gain = 412.512
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
E
%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
L
%s
*synth24
 Start RTL Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Detailed RTL Component Info : 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
O
%s
*synth27
#Finished RTL Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
Y
%s
*synth2A
-Start RTL Hierarchical Component Statistics 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
O
%s
*synth27
#Hierarchical RTL Component report 
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
[
%s
*synth2C
/Finished RTL Hierarchical Component Statistics
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
H
%s
*synth20
Start Part Resource Summary
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
É
%s
*synth2k
WPart Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
K
%s
*synth23
Finished Part Resource Summary
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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W
%s
*synth2?
+Start Cross Boundary and Area Optimization
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2E
1Warning: Parallel synthesis criteria is not met 
2default:defaulthp
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2¢
çFinished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 699.977 ; gain = 412.512
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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R
%s
*synth2:
&Start Applying XDC Timing Constraints
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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∂
%s*synth2ù
àFinished Applying XDC Timing Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
F
%s
*synth2.
Start Timing Optimization
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
ê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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©
%s*synth2ê
|Finished Timing Optimization : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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E
%s
*synth2-
Start Technology Mapping
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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®
%s*synth2è
{Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:32 . Memory (MB): peak = 753.023 ; gain = 465.559
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2-

Report RTL Partitions: 
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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%s
*synth2?
+| |RTL Partition |Replication |Instances |
2default:defaulthp
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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W
%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2'
Start IO Insertion
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Q
%s
*synth29
%Start Flattening Before IO Insertion
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2<
(Finished Flattening Before IO Insertion
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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H
%s
*synth20
Start Final Netlist Cleanup
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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K
%s
*synth23
Finished Final Netlist Cleanup
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2â
uFinished IO Insertion : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2,

Report Check Netlist: 
2default:defaulthp
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
x
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%s
*synth2]
I|      |Item              |Errors |Warnings |Status |Description       |
2default:defaulthp
x
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
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%s
*synth2]
I|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
2default:defaulthp
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%s
*synth2]
I+------+------------------+-------+---------+-------+------------------+
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth27
#Start Renaming Generated Instances
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s*synth2ö
ÖFinished Renaming Generated Instances : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
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*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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Report RTL Partitions: 
2default:defaulthp
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++-+--------------+------------+----------+
2default:defaulthp
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%s
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+| |RTL Partition |Replication |Instances |
2default:defaulthp
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*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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%s
*synth2?
++-+--------------+------------+----------+
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth24
 Start Rebuilding User Hierarchy
2default:defaulthp
x
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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∞
%s*synth2ó
ÇFinished Rebuilding User Hierarchy : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth23
Start Renaming Generated Ports
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
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2default:defaulthp
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%s*synth2ñ
ÅFinished Renaming Generated Ports : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth25
!Start Handling Custom Attributes
2default:defaulthp
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2f
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2default:defaulthp
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%s*synth2ò
ÉFinished Handling Custom Attributes : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
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2default:defaulthp
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%s
*synth22
Start Renaming Generated Nets
2default:defaulthp
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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2default:defaulthp
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%s*synth2ï
ÄFinished Renaming Generated Nets : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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~
%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth23
Start Writing Synthesis Report
2default:defaulthp
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%s
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R---------------------------------------------------------------------------------
2default:defaulthp
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Report BlackBoxes: 
2default:defaulthp
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%s
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+-+--------------+----------+
2default:defaulthp
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%s
*synth22
| |BlackBox name |Instances |
2default:defaulthp
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%s
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+-+--------------+----------+
2default:defaulthp
x
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%s
*synth22
+-+--------------+----------+
2default:defaulthp
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Report Cell Usage: 
2default:defaulthpxê
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%s*synth20
+------+-----------+------+
2default:defaulthpxê
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%s*synth20
|      |Cell       |Count |
2default:defaulthpxê
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%s*synth20
+------+-----------+------+
2default:defaulthpxê
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%s*synth20
|1     |BUFG       |     2|
2default:defaulthpxê
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%s*synth20
|2     |MMCME2_ADV |     1|
2default:defaulthpxê
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%s*synth20
|3     |IBUF       |     1|
2default:defaulthpxê
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%s*synth20
+------+-----------+------+
2default:defaulthpxê
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%s
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Report Instance Areas: 
2default:defaulthp
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%s
*synth2G
3+------+---------+------------------------+------+
2default:defaulthp
x
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%s
*synth2G
3|      |Instance |Module                  |Cells |
2default:defaulthp
x
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%s
*synth2G
3+------+---------+------------------------+------+
2default:defaulthp
x
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_
%s
*synth2G
3|1     |top      |                        |     4|
2default:defaulthp
x
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_
%s
*synth2G
3|2     |  inst   |clk_wiz_for_cpu_clk_wiz |     4|
2default:defaulthp
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%s
*synth2G
3+------+---------+------------------------+------+
2default:defaulthp
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%s
*synth2f
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2default:defaulthp
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%s*synth2ñ
ÅFinished Writing Synthesis Report : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthpxê
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%s
*synth2f
R---------------------------------------------------------------------------------
2default:defaulthp
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%s
*synth2Z
FSynthesis finished with 0 errors, 0 critical warnings and 0 warnings.
2default:defaulthp
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%s
*synth2í
~Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:24 . Memory (MB): peak = 754.410 ; gain = 207.582
2default:defaulthp
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*synth2ì
Synthesis Optimization Complete : Time (s): cpu = 00:00:31 ; elapsed = 00:00:34 . Memory (MB): peak = 754.410 ; gain = 466.945
2default:defaulthp
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 Translating synthesized netlist
350*projectZ1-571hpxê
e
-Analyzing %s Unisim elements for replacement
17*netlist2
22default:defaultZ29-17hpxê
j
2Unisim Transformation completed in %s CPU seconds
28*netlist2
02default:defaultZ29-28hpxê
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)Preparing netlist for logic optimization
349*projectZ1-570hpxê
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)Pushed %s inverter(s) to %s load pin(s).
98*opt2
02default:default2
02default:defaultZ31-138hpxê
~
!Unisim Transformation Summary:
%s111*project29
%No Unisim elements were transformed.
2default:defaultZ1-111hpxê
U
Releasing license: %s
83*common2
	Synthesis2default:defaultZ17-83hpxê
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G%s Infos, %s Warnings, %s Critical Warnings and %s Errors encountered.
28*	vivadotcl2
252default:default2
02default:default2
02default:default2
02default:defaultZ4-41hpxê
^
%s completed successfully
29*	vivadotcl2 
synth_design2default:defaultZ4-42hpxê
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I%sTime (s): cpu = %s ; elapsed = %s . Memory (MB): peak = %s ; gain = %s
268*common2"
synth_design: 2default:default2
00:00:332default:default2
00:00:372default:default2
773.5552default:default2
497.5592default:defaultZ17-268hpxê
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 The %s '%s' has been generated.
621*common2

checkpoint2default:default2´
ñD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/clk_wiz_for_cpu.dcp2default:defaultZ17-1381hpxê
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,Added synthesis output to IP cache for IP %s415*coretcl2∞
õd:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.srcs/sources_1/ip/clk_wiz_for_cpu/clk_wiz_for_cpu.xci2default:defaultZ2-1482hpxê
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"No constraint will be written out.1103*constraintsZ18-5210hpxê
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 The %s '%s' has been generated.
621*common2

checkpoint2default:default2´
ñD:/WeCloudSync/6.MI_PROJECTS/IncredibleVivado/Pipeline_with_ThreeLevelMem/Pipeline_with_ThreeLevelMem.runs/clk_wiz_for_cpu_synth_1/clk_wiz_for_cpu.dcp2default:defaultZ17-1381hpxê
•
%s4*runtcl2à
tExecuting : report_utilization -file clk_wiz_for_cpu_utilization_synth.rpt -pb clk_wiz_for_cpu_utilization_synth.pb
2default:defaulthpxê
à
sreport_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 777.934 ; gain = 0.000
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Exiting %s at %s...
206*common2
Vivado2default:default2,
Mon Dec 24 20:24:45 20182default:defaultZ17-206hpxê


End Record