;
; Z180 REGISTERS
;
Z180_CNTLA0	.EQU	Z180_BASE + $00	; ASCI0 CONTROL A
Z180_CNTLA1	.EQU	Z180_BASE + $01	; ASCI1 CONTROL A
Z180_CNTLB0	.EQU	Z180_BASE + $02	; ASCI0 CONTROL B
Z180_CNTLB1	.EQU	Z180_BASE + $03	; ASCI1 CONTROL B
Z180_STAT0	.EQU	Z180_BASE + $04	; ASCI0 STATUS
Z180_STAT1	.EQU	Z180_BASE + $05	; ASCI1 STATUS
Z180_TDR0	.EQU	Z180_BASE + $06	; ASCI0 TRANSMIT
Z180_TDR1	.EQU	Z180_BASE + $07	; ASCI1 TRANSMIT
Z180_RDR0	.EQU	Z180_BASE + $08	; ASCI0 RECEIVE
Z180_RDR1	.EQU	Z180_BASE + $09	; ASCI1 RECEIVE
Z180_CNTR	.EQU	Z180_BASE + $0A	; CSI/O CONTROL
Z180_TRDR	.EQU	Z180_BASE + $0B	; CSI/O TRANSMIT/RECEIVE
Z180_TMDR0L	.EQU	Z180_BASE + $0C	; TIMER 0 DATA LO
Z180_TMDR0H	.EQU	Z180_BASE + $0D	; TIMER 0 DATA HI
Z180_RLDR0L	.EQU	Z180_BASE + $0E	; TIMER 0 RELOAD LO
Z180_RLDR0H	.EQU	Z180_BASE + $0F	; TIMER 0 RELOAD HI
Z180_TCR	.EQU	Z180_BASE + $10	; TIMER CONTROL
;	
Z180_ASEXT0	.EQU	Z180_BASE + $12	; ASCI0 EXTENSION CONTROL (Z8S180)
Z180_ASEXT1	.EQU	Z180_BASE + $13	; ASCI1 EXTENSION CONTROL (Z8S180)
;
Z180_TMDR1L	.EQU	Z180_BASE + $14	; TIMER 1 DATA LO
Z180_TMDR1H	.EQU	Z180_BASE + $15	; TIMER 1 DATA HI
Z180_RLDR1L	.EQU	Z180_BASE + $16	; TIMER 1 RELOAD LO
Z180_RLDR1H	.EQU	Z180_BASE + $17	; TIMER 1 RELOAD HI
Z180_FRC	.EQU	Z180_BASE + $18	; FREE RUNNING COUNTER

Z180_ASTC0L	.EQU	Z180_BASE + $1A	; ASCI0 TIME CONSTANT LO (Z8S180)
Z180_ASTC0H	.EQU	Z180_BASE + $1B	; ASCI0 TIME CONSTANT HI (Z8S180)
Z180_ASTC1L	.EQU	Z180_BASE + $1C	; ASCI1 TIME CONSTANT LO (Z8S180)
Z180_ASTC1H	.EQU	Z180_BASE + $1D	; ASCI1 TIME CONSTANT HI (Z8S180)
Z180_CMR	.EQU	Z180_BASE + $1E	; CLOCK MULTIPLIER (LATEST Z8S180)
Z180_CCR	.EQU	Z180_BASE + $1F	; CPU CONTROL (Z8S180)
;
Z180_SAR0L	.EQU	Z180_BASE + $20	; DMA0 SOURCE ADDR LO
Z180_SAR0H	.EQU	Z180_BASE + $21	; DMA0 SOURCE ADDR HI
Z180_SAR0B	.EQU	Z180_BASE + $22	; DMA0 SOURCE ADDR BANK
Z180_DAR0L	.EQU	Z180_BASE + $23	; DMA0 DEST ADDR LO
Z180_DAR0H	.EQU	Z180_BASE + $24	; DMA0 DEST ADDR HI
Z180_DAR0B	.EQU	Z180_BASE + $25	; DMA0 DEST ADDR BANK
Z180_BCR0L	.EQU	Z180_BASE + $26	; DMA0 BYTE COUNT LO
Z180_BCR0H	.EQU	Z180_BASE + $27	; DMA0 BYTE COUNT HI
Z180_MAR1L	.EQU	Z180_BASE + $28	; DMA1 MEMORY ADDR LO
Z180_MAR1H	.EQU	Z180_BASE + $29	; DMA1 MEMORY ADDR HI
Z180_MAR1B	.EQU	Z180_BASE + $2A	; DMA1 MEMORY ADDR BANK
Z180_IAR1L	.EQU	Z180_BASE + $2B	; DMA1 I/O ADDR LO
Z180_IAR1H	.EQU	Z180_BASE + $2C	; DMA1 I/O ADDR HI
Z180_IAR1B	.EQU	Z180_BASE + $2D	; DMA1 I/O ADDR BANK (Z8S180)
Z180_BCR1L	.EQU	Z180_BASE + $2E	; DMA1 BYTE COUNT LO
Z180_BCR1H	.EQU	Z180_BASE + $2F	; DMA1 BYTE COUNT HI
Z180_DSTAT	.EQU	Z180_BASE + $30	; DMA STATUS
Z180_DMODE	.EQU	Z180_BASE + $31	; DMA MODE
Z180_DCNTL	.EQU	Z180_BASE + $32	; DMA/WAIT CONTROL
Z180_IL		.EQU	Z180_BASE + $33	; INTERRUPT VECTOR LOAD
Z180_ITC	.EQU	Z180_BASE + $34	; INT/TRAP CONTROL
;
Z180_RCR	.EQU	Z180_BASE + $36	; REFRESH CONTROL
;
Z180_CBR	.EQU	Z180_BASE + $38	; MMU COMMON BASE REGISTER
Z180_BBR	.EQU	Z180_BASE + $39	; MMU BANK BASE REGISTER
Z180_CBAR	.EQU	Z180_BASE + $3A	; MMU COMMON/BANK AREA REGISTER
;
Z180_OMCR	.EQU	Z180_BASE + $3E	; OPERATION MODE CONTROL
Z180_ICR	.EQU	Z180_BASE + $3F	; I/O CONTROL REGISTER
