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    <title>Other clock drivers editor</title>
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    <h2>Other clock drivers editor</h2>
    <p>
      Other clock drivers-editor shows the clocks within the component
      that are not directly associated with a top-level port.  This
      kind of clocks could be i.e. virtual clocks or generated clocks.
    </p>
    <p>
      The mandatory <b>clock name</b> identifies the other clock driver.
    </p>
    <p>
      <b>Clock source</b> is optional and defines the physical path and name of the clock generation cell. 
      E.g. a component instantiated in VHDL and its output, like 'i_clkGen/clk1'. The waveform of the clock signal 
      has 4 parameters. Time units are either <strong>ps</strong> (picosecond) or <strong>ns</strong> (nanosecond).
    </p>
    <p>
      <b>Clock period</b> defines the length of one cycle of clock pulse, e.g. 10 ns.
    </p>
    <p>
      <b>Pulse offset</b> describes the time delay from start of the cycle to the first transition.
    </p>
    <p>
      <b>Pulse value</b> defines the logic value which the first transition is made to, either 0 or 1.
    </p>
    <p>
      <b>Pulse duration</b> specifies how long the value defined in pulse value is held, e.g. 5 ns.
    </p>
    <p>
      Other clock drivers editor provides a context menu (right mouse
      button) with the following options:
    </p>
    <ul>
      <li>Add new clock (Add row)</li>
      <li>Remove clock (Remove row)</li>
      <li>Clear the selected cells</li>
      <li>Copy the contents of the selected cells to clipboard</li>
      <li>Paste the contents of the clipboard to the selected cells</li>
      <li>Import a csv-file to the editor</li>
      <li>Export the contents of the editor to a csv-file</li>
    </ul>

    <hr>
    <p>
      EXAMPLE. Component Foo has a regular clock input port ClkIn and two additional
      clock sources clk0 and clk1 generated by instantiation clk_gen.
    </p>    
    <p>
        <img src="../images/clk_drivers.png" alt"clk_example"><br>
    </p>
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