read_verilog ../xilinx_ultraram_single_port_write_first.v
hierarchy -top xilinx_ultraram_single_port_write_first
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd xilinx_ultraram_single_port_write_first
#Vivado synthesizes 1 RAMB18E1, 28 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 44 t:FDRE
select -assert-count 8 t:LUT5
select -assert-count 8 t:LUT2
select -assert-count 3 t:LUT3
select -assert-count 16 t:RAM128X1D

select -assert-none t:BUFG t:FDRE t:LUT5 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
