Daniel-Nikpayuk_SICP-Solutions/Chapter 3/3.3/exercise-3.30 (ripple-carry-adder)/exercise.lsp
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;; Copyright 2015 Daniel Nikpayuk
;;
;; This file is part of SICP Solutions.
;;
;; SICP Solutions is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License
;; as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version.
;;
;; SICP Solutions is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
;; of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License along with SICP Solutions. If not, see
;; <http://www.gnu.org/licenses/>.
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(define (half-adder a b s c)
  (let ((d (make-wire)) (e (make-wire)))
    (or-gate a b d)
    (and-gate a b c)
    (inverter c e)
    (and-gate d e s)
    'ok))

(define (full-adder a b c-in sum c-out)
  (let ((s (make-wire))
        (c1 (make-wire))
        (c2 (make-wire)))
    (half-adder b c-in s c1)
    (half-adder a s sum c2)
    (or-gate c1 c2 c-out)
    'ok))

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;; Assumes A, B, S are same size without safety checks.
(define (ripple-carry-adder A B S c)
 (if (null? S) 'ok
  (
   (full-adder (car A) (car B) c (car S) c)
   (ripple-carry-adder (cdr A) (cdr B) (cdr S) c)
  )
 )
)

;; The delay of a full-adder is 2 * half-adder-delay + or-gate-delay.
;; == 2 * ( max( and-gate-delay , or-gate-delay ) + inverter-gate-delay + and-gate-delay ) + or-gate-delay.

;; Thus the delay of 'n' full-adders is:
;; n * ( 2 * ( max( and-gate-delay , or-gate-delay ) + inverter-gate-delay + and-gate-delay ) + or-gate-delay )

